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Commit 76d067ac33947f08fbbdea27bae5f3a263eda3f3

Authored by Prabhakar Kushwaha
Committed by Scott Wood
1 parent 807fc702e0
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

driver/mtd:IFC: Fix possible memory leak 

if priv->bank >= MAX_BANK, priv should be freed before returning ENODEV.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scott@tyr.buserror.net>

Showing 1 changed file with 1 additions and 0 deletions Inline Diff

drivers/mtd/nand/fsl_ifc_nand.c
Diff comments   View file @ 76d067a
1 /* Integrated Flash Controller NAND Machine Driver 1 /* Integrated Flash Controller NAND Machine Driver
2 * 2 *
3 * Copyright (c) 2012 Freescale Semiconductor, Inc 3 * Copyright (c) 2012 Freescale Semiconductor, Inc
4 * 4 *
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com> 5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21 21
22 #include <common.h> 22 #include <common.h>
23 #include <malloc.h> 23 #include <malloc.h>
24 24
25 #include <linux/mtd/mtd.h> 25 #include <linux/mtd/mtd.h>
26 #include <linux/mtd/nand.h> 26 #include <linux/mtd/nand.h>
27 #include <linux/mtd/nand_ecc.h> 27 #include <linux/mtd/nand_ecc.h>
28 28
29 #include <asm/io.h> 29 #include <asm/io.h>
30 #include <asm/errno.h> 30 #include <asm/errno.h>
31 #include <asm/fsl_ifc.h> 31 #include <asm/fsl_ifc.h>
32 32
33 #define MAX_BANKS 4 33 #define MAX_BANKS 4
34 #define ERR_BYTE 0xFF /* Value returned for read bytes 34 #define ERR_BYTE 0xFF /* Value returned for read bytes
35 when read failed */ 35 when read failed */
36 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC 36 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
37 NAND Machine */ 37 NAND Machine */
38 38
39 struct fsl_ifc_ctrl; 39 struct fsl_ifc_ctrl;
40 40
41 /* mtd information per set */ 41 /* mtd information per set */
42 struct fsl_ifc_mtd { 42 struct fsl_ifc_mtd {
43 struct mtd_info mtd; 43 struct mtd_info mtd;
44 struct nand_chip chip; 44 struct nand_chip chip;
45 struct fsl_ifc_ctrl *ctrl; 45 struct fsl_ifc_ctrl *ctrl;
46 46
47 struct device *dev; 47 struct device *dev;
48 int bank; /* Chip select bank number */ 48 int bank; /* Chip select bank number */
49 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */ 49 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
50 u8 __iomem *vbase; /* Chip select base virtual address */ 50 u8 __iomem *vbase; /* Chip select base virtual address */
51 }; 51 };
52 52
53 /* overview of the fsl ifc controller */ 53 /* overview of the fsl ifc controller */
54 struct fsl_ifc_ctrl { 54 struct fsl_ifc_ctrl {
55 struct nand_hw_control controller; 55 struct nand_hw_control controller;
56 struct fsl_ifc_mtd *chips[MAX_BANKS]; 56 struct fsl_ifc_mtd *chips[MAX_BANKS];
57 57
58 /* device info */ 58 /* device info */
59 struct fsl_ifc *regs; 59 struct fsl_ifc *regs;
60 uint8_t __iomem *addr; /* Address of assigned IFC buffer */ 60 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
61 unsigned int cs_nand; /* On which chipsel NAND is connected */ 61 unsigned int cs_nand; /* On which chipsel NAND is connected */
62 unsigned int page; /* Last page written to / read from */ 62 unsigned int page; /* Last page written to / read from */
63 unsigned int read_bytes; /* Number of bytes read during command */ 63 unsigned int read_bytes; /* Number of bytes read during command */
64 unsigned int column; /* Saved column from SEQIN */ 64 unsigned int column; /* Saved column from SEQIN */
65 unsigned int index; /* Pointer to next byte to 'read' */ 65 unsigned int index; /* Pointer to next byte to 'read' */
66 unsigned int status; /* status read from NEESR after last op */ 66 unsigned int status; /* status read from NEESR after last op */
67 unsigned int oob; /* Non zero if operating on OOB data */ 67 unsigned int oob; /* Non zero if operating on OOB data */
68 unsigned int eccread; /* Non zero for a full-page ECC read */ 68 unsigned int eccread; /* Non zero for a full-page ECC read */
69 }; 69 };
70 70
71 static struct fsl_ifc_ctrl *ifc_ctrl; 71 static struct fsl_ifc_ctrl *ifc_ctrl;
72 72
73 /* 512-byte page with 4-bit ECC, 8-bit */ 73 /* 512-byte page with 4-bit ECC, 8-bit */
74 static struct nand_ecclayout oob_512_8bit_ecc4 = { 74 static struct nand_ecclayout oob_512_8bit_ecc4 = {
75 .eccbytes = 8, 75 .eccbytes = 8,
76 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15}, 76 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
77 .oobfree = { {0, 5}, {6, 2} }, 77 .oobfree = { {0, 5}, {6, 2} },
78 }; 78 };
79 79
80 /* 512-byte page with 4-bit ECC, 16-bit */ 80 /* 512-byte page with 4-bit ECC, 16-bit */
81 static struct nand_ecclayout oob_512_16bit_ecc4 = { 81 static struct nand_ecclayout oob_512_16bit_ecc4 = {
82 .eccbytes = 8, 82 .eccbytes = 8,
83 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15}, 83 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
84 .oobfree = { {2, 6}, }, 84 .oobfree = { {2, 6}, },
85 }; 85 };
86 86
87 /* 2048-byte page size with 4-bit ECC */ 87 /* 2048-byte page size with 4-bit ECC */
88 static struct nand_ecclayout oob_2048_ecc4 = { 88 static struct nand_ecclayout oob_2048_ecc4 = {
89 .eccbytes = 32, 89 .eccbytes = 32,
90 .eccpos = { 90 .eccpos = {
91 8, 9, 10, 11, 12, 13, 14, 15, 91 8, 9, 10, 11, 12, 13, 14, 15,
92 16, 17, 18, 19, 20, 21, 22, 23, 92 16, 17, 18, 19, 20, 21, 22, 23,
93 24, 25, 26, 27, 28, 29, 30, 31, 93 24, 25, 26, 27, 28, 29, 30, 31,
94 32, 33, 34, 35, 36, 37, 38, 39, 94 32, 33, 34, 35, 36, 37, 38, 39,
95 }, 95 },
96 .oobfree = { {2, 6}, {40, 24} }, 96 .oobfree = { {2, 6}, {40, 24} },
97 }; 97 };
98 98
99 /* 4096-byte page size with 4-bit ECC */ 99 /* 4096-byte page size with 4-bit ECC */
100 static struct nand_ecclayout oob_4096_ecc4 = { 100 static struct nand_ecclayout oob_4096_ecc4 = {
101 .eccbytes = 64, 101 .eccbytes = 64,
102 .eccpos = { 102 .eccpos = {
103 8, 9, 10, 11, 12, 13, 14, 15, 103 8, 9, 10, 11, 12, 13, 14, 15,
104 16, 17, 18, 19, 20, 21, 22, 23, 104 16, 17, 18, 19, 20, 21, 22, 23,
105 24, 25, 26, 27, 28, 29, 30, 31, 105 24, 25, 26, 27, 28, 29, 30, 31,
106 32, 33, 34, 35, 36, 37, 38, 39, 106 32, 33, 34, 35, 36, 37, 38, 39,
107 40, 41, 42, 43, 44, 45, 46, 47, 107 40, 41, 42, 43, 44, 45, 46, 47,
108 48, 49, 50, 51, 52, 53, 54, 55, 108 48, 49, 50, 51, 52, 53, 54, 55,
109 56, 57, 58, 59, 60, 61, 62, 63, 109 56, 57, 58, 59, 60, 61, 62, 63,
110 64, 65, 66, 67, 68, 69, 70, 71, 110 64, 65, 66, 67, 68, 69, 70, 71,
111 }, 111 },
112 .oobfree = { {2, 6}, {72, 56} }, 112 .oobfree = { {2, 6}, {72, 56} },
113 }; 113 };
114 114
115 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */ 115 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
116 static struct nand_ecclayout oob_4096_ecc8 = { 116 static struct nand_ecclayout oob_4096_ecc8 = {
117 .eccbytes = 128, 117 .eccbytes = 128,
118 .eccpos = { 118 .eccpos = {
119 8, 9, 10, 11, 12, 13, 14, 15, 119 8, 9, 10, 11, 12, 13, 14, 15,
120 16, 17, 18, 19, 20, 21, 22, 23, 120 16, 17, 18, 19, 20, 21, 22, 23,
121 24, 25, 26, 27, 28, 29, 30, 31, 121 24, 25, 26, 27, 28, 29, 30, 31,
122 32, 33, 34, 35, 36, 37, 38, 39, 122 32, 33, 34, 35, 36, 37, 38, 39,
123 40, 41, 42, 43, 44, 45, 46, 47, 123 40, 41, 42, 43, 44, 45, 46, 47,
124 48, 49, 50, 51, 52, 53, 54, 55, 124 48, 49, 50, 51, 52, 53, 54, 55,
125 56, 57, 58, 59, 60, 61, 62, 63, 125 56, 57, 58, 59, 60, 61, 62, 63,
126 64, 65, 66, 67, 68, 69, 70, 71, 126 64, 65, 66, 67, 68, 69, 70, 71,
127 72, 73, 74, 75, 76, 77, 78, 79, 127 72, 73, 74, 75, 76, 77, 78, 79,
128 80, 81, 82, 83, 84, 85, 86, 87, 128 80, 81, 82, 83, 84, 85, 86, 87,
129 88, 89, 90, 91, 92, 93, 94, 95, 129 88, 89, 90, 91, 92, 93, 94, 95,
130 96, 97, 98, 99, 100, 101, 102, 103, 130 96, 97, 98, 99, 100, 101, 102, 103,
131 104, 105, 106, 107, 108, 109, 110, 111, 131 104, 105, 106, 107, 108, 109, 110, 111,
132 112, 113, 114, 115, 116, 117, 118, 119, 132 112, 113, 114, 115, 116, 117, 118, 119,
133 120, 121, 122, 123, 124, 125, 126, 127, 133 120, 121, 122, 123, 124, 125, 126, 127,
134 128, 129, 130, 131, 132, 133, 134, 135, 134 128, 129, 130, 131, 132, 133, 134, 135,
135 }, 135 },
136 .oobfree = { {2, 6}, {136, 82} }, 136 .oobfree = { {2, 6}, {136, 82} },
137 }; 137 };
138 138
139 139
140 /* 140 /*
141 * Generic flash bbt descriptors 141 * Generic flash bbt descriptors
142 */ 142 */
143 static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 143 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
144 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 144 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
145 145
146 static struct nand_bbt_descr bbt_main_descr = { 146 static struct nand_bbt_descr bbt_main_descr = {
147 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 147 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
148 NAND_BBT_2BIT | NAND_BBT_VERSION, 148 NAND_BBT_2BIT | NAND_BBT_VERSION,
149 .offs = 2, /* 0 on 8-bit small page */ 149 .offs = 2, /* 0 on 8-bit small page */
150 .len = 4, 150 .len = 4,
151 .veroffs = 6, 151 .veroffs = 6,
152 .maxblocks = 4, 152 .maxblocks = 4,
153 .pattern = bbt_pattern, 153 .pattern = bbt_pattern,
154 }; 154 };
155 155
156 static struct nand_bbt_descr bbt_mirror_descr = { 156 static struct nand_bbt_descr bbt_mirror_descr = {
157 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 157 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
158 NAND_BBT_2BIT | NAND_BBT_VERSION, 158 NAND_BBT_2BIT | NAND_BBT_VERSION,
159 .offs = 2, /* 0 on 8-bit small page */ 159 .offs = 2, /* 0 on 8-bit small page */
160 .len = 4, 160 .len = 4,
161 .veroffs = 6, 161 .veroffs = 6,
162 .maxblocks = 4, 162 .maxblocks = 4,
163 .pattern = mirror_pattern, 163 .pattern = mirror_pattern,
164 }; 164 };
165 165
166 /* 166 /*
167 * Set up the IFC hardware block and page address fields, and the ifc nand 167 * Set up the IFC hardware block and page address fields, and the ifc nand
168 * structure addr field to point to the correct IFC buffer in memory 168 * structure addr field to point to the correct IFC buffer in memory
169 */ 169 */
170 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) 170 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
171 { 171 {
172 struct nand_chip *chip = mtd->priv; 172 struct nand_chip *chip = mtd->priv;
173 struct fsl_ifc_mtd *priv = chip->priv; 173 struct fsl_ifc_mtd *priv = chip->priv;
174 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 174 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
175 struct fsl_ifc *ifc = ctrl->regs; 175 struct fsl_ifc *ifc = ctrl->regs;
176 int buf_num; 176 int buf_num;
177 177
178 ctrl->page = page_addr; 178 ctrl->page = page_addr;
179 179
180 /* Program ROW0/COL0 */ 180 /* Program ROW0/COL0 */
181 out_be32(&ifc->ifc_nand.row0, page_addr); 181 out_be32(&ifc->ifc_nand.row0, page_addr);
182 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); 182 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
183 183
184 buf_num = page_addr & priv->bufnum_mask; 184 buf_num = page_addr & priv->bufnum_mask;
185 185
186 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2); 186 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
187 ctrl->index = column; 187 ctrl->index = column;
188 188
189 /* for OOB data point to the second half of the buffer */ 189 /* for OOB data point to the second half of the buffer */
190 if (oob) 190 if (oob)
191 ctrl->index += mtd->writesize; 191 ctrl->index += mtd->writesize;
192 } 192 }
193 193
194 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, 194 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
195 unsigned int bufnum) 195 unsigned int bufnum)
196 { 196 {
197 struct nand_chip *chip = mtd->priv; 197 struct nand_chip *chip = mtd->priv;
198 struct fsl_ifc_mtd *priv = chip->priv; 198 struct fsl_ifc_mtd *priv = chip->priv;
199 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2); 199 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
200 u32 __iomem *main = (u32 *)addr; 200 u32 __iomem *main = (u32 *)addr;
201 u8 __iomem *oob = addr + mtd->writesize; 201 u8 __iomem *oob = addr + mtd->writesize;
202 int i; 202 int i;
203 203
204 for (i = 0; i < mtd->writesize / 4; i++) { 204 for (i = 0; i < mtd->writesize / 4; i++) {
205 if (__raw_readl(&main[i]) != 0xffffffff) 205 if (__raw_readl(&main[i]) != 0xffffffff)
206 return 0; 206 return 0;
207 } 207 }
208 208
209 for (i = 0; i < chip->ecc.layout->eccbytes; i++) { 209 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
210 int pos = chip->ecc.layout->eccpos[i]; 210 int pos = chip->ecc.layout->eccpos[i];
211 211
212 if (__raw_readb(&oob[pos]) != 0xff) 212 if (__raw_readb(&oob[pos]) != 0xff)
213 return 0; 213 return 0;
214 } 214 }
215 215
216 return 1; 216 return 1;
217 } 217 }
218 218
219 /* returns nonzero if entire page is blank */ 219 /* returns nonzero if entire page is blank */
220 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, 220 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
221 u32 *eccstat, unsigned int bufnum) 221 u32 *eccstat, unsigned int bufnum)
222 { 222 {
223 u32 reg = eccstat[bufnum / 4]; 223 u32 reg = eccstat[bufnum / 4];
224 int errors; 224 int errors;
225 225
226 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15; 226 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
227 227
228 return errors; 228 return errors;
229 } 229 }
230 230
231 /* 231 /*
232 * execute IFC NAND command and wait for it to complete 232 * execute IFC NAND command and wait for it to complete
233 */ 233 */
234 static int fsl_ifc_run_command(struct mtd_info *mtd) 234 static int fsl_ifc_run_command(struct mtd_info *mtd)
235 { 235 {
236 struct nand_chip *chip = mtd->priv; 236 struct nand_chip *chip = mtd->priv;
237 struct fsl_ifc_mtd *priv = chip->priv; 237 struct fsl_ifc_mtd *priv = chip->priv;
238 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 238 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
239 struct fsl_ifc *ifc = ctrl->regs; 239 struct fsl_ifc *ifc = ctrl->regs;
240 long long end_tick; 240 long long end_tick;
241 u32 eccstat[4]; 241 u32 eccstat[4];
242 int i; 242 int i;
243 243
244 /* set the chip select for NAND Transaction */ 244 /* set the chip select for NAND Transaction */
245 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); 245 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
246 246
247 /* start read/write seq */ 247 /* start read/write seq */
248 out_be32(&ifc->ifc_nand.nandseq_strt, 248 out_be32(&ifc->ifc_nand.nandseq_strt,
249 IFC_NAND_SEQ_STRT_FIR_STRT); 249 IFC_NAND_SEQ_STRT_FIR_STRT);
250 250
251 /* wait for NAND Machine complete flag or timeout */ 251 /* wait for NAND Machine complete flag or timeout */
252 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); 252 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
253 253
254 while (end_tick > get_ticks()) { 254 while (end_tick > get_ticks()) {
255 ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); 255 ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
256 256
257 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC) 257 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
258 break; 258 break;
259 } 259 }
260 260
261 out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); 261 out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
262 262
263 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER) 263 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
264 printf("%s: Flash Time Out Error\n", __func__); 264 printf("%s: Flash Time Out Error\n", __func__);
265 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER) 265 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
266 printf("%s: Write Protect Error\n", __func__); 266 printf("%s: Write Protect Error\n", __func__);
267 267
268 if (ctrl->eccread) { 268 if (ctrl->eccread) {
269 int errors; 269 int errors;
270 int bufnum = ctrl->page & priv->bufnum_mask; 270 int bufnum = ctrl->page & priv->bufnum_mask;
271 int sector = bufnum * chip->ecc.steps; 271 int sector = bufnum * chip->ecc.steps;
272 int sector_end = sector + chip->ecc.steps - 1; 272 int sector_end = sector + chip->ecc.steps - 1;
273 273
274 for (i = sector / 4; i <= sector_end / 4; i++) 274 for (i = sector / 4; i <= sector_end / 4; i++)
275 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); 275 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
276 276
277 for (i = sector; i <= sector_end; i++) { 277 for (i = sector; i <= sector_end; i++) {
278 errors = check_read_ecc(mtd, ctrl, eccstat, i); 278 errors = check_read_ecc(mtd, ctrl, eccstat, i);
279 279
280 if (errors == 15) { 280 if (errors == 15) {
281 /* 281 /*
282 * Uncorrectable error. 282 * Uncorrectable error.
283 * OK only if the whole page is blank. 283 * OK only if the whole page is blank.
284 * 284 *
285 * We disable ECCER reporting due to erratum 285 * We disable ECCER reporting due to erratum
286 * IFC-A002770 -- so report it now if we 286 * IFC-A002770 -- so report it now if we
287 * see an uncorrectable error in ECCSTAT. 287 * see an uncorrectable error in ECCSTAT.
288 */ 288 */
289 if (!is_blank(mtd, ctrl, bufnum)) 289 if (!is_blank(mtd, ctrl, bufnum))
290 ctrl->status |= 290 ctrl->status |=
291 IFC_NAND_EVTER_STAT_ECCER; 291 IFC_NAND_EVTER_STAT_ECCER;
292 break; 292 break;
293 } 293 }
294 294
295 mtd->ecc_stats.corrected += errors; 295 mtd->ecc_stats.corrected += errors;
296 } 296 }
297 297
298 ctrl->eccread = 0; 298 ctrl->eccread = 0;
299 } 299 }
300 300
301 /* returns 0 on success otherwise non-zero) */ 301 /* returns 0 on success otherwise non-zero) */
302 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO; 302 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
303 } 303 }
304 304
305 static void fsl_ifc_do_read(struct nand_chip *chip, 305 static void fsl_ifc_do_read(struct nand_chip *chip,
306 int oob, 306 int oob,
307 struct mtd_info *mtd) 307 struct mtd_info *mtd)
308 { 308 {
309 struct fsl_ifc_mtd *priv = chip->priv; 309 struct fsl_ifc_mtd *priv = chip->priv;
310 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 310 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
311 struct fsl_ifc *ifc = ctrl->regs; 311 struct fsl_ifc *ifc = ctrl->regs;
312 312
313 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ 313 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
314 if (mtd->writesize > 512) { 314 if (mtd->writesize > 512) {
315 out_be32(&ifc->ifc_nand.nand_fir0, 315 out_be32(&ifc->ifc_nand.nand_fir0,
316 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 316 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
317 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 317 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
318 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 318 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
319 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | 319 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
320 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); 320 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
321 out_be32(&ifc->ifc_nand.nand_fir1, 0x0); 321 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
322 322
323 out_be32(&ifc->ifc_nand.nand_fcr0, 323 out_be32(&ifc->ifc_nand.nand_fcr0,
324 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | 324 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
325 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); 325 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
326 } else { 326 } else {
327 out_be32(&ifc->ifc_nand.nand_fir0, 327 out_be32(&ifc->ifc_nand.nand_fir0,
328 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 328 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
329 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 329 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
330 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 330 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
331 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); 331 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
332 332
333 if (oob) 333 if (oob)
334 out_be32(&ifc->ifc_nand.nand_fcr0, 334 out_be32(&ifc->ifc_nand.nand_fcr0,
335 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); 335 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
336 else 336 else
337 out_be32(&ifc->ifc_nand.nand_fcr0, 337 out_be32(&ifc->ifc_nand.nand_fcr0,
338 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); 338 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
339 } 339 }
340 } 340 }
341 341
342 /* cmdfunc send commands to the IFC NAND Machine */ 342 /* cmdfunc send commands to the IFC NAND Machine */
343 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, 343 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
344 int column, int page_addr) 344 int column, int page_addr)
345 { 345 {
346 struct nand_chip *chip = mtd->priv; 346 struct nand_chip *chip = mtd->priv;
347 struct fsl_ifc_mtd *priv = chip->priv; 347 struct fsl_ifc_mtd *priv = chip->priv;
348 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 348 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
349 struct fsl_ifc *ifc = ctrl->regs; 349 struct fsl_ifc *ifc = ctrl->regs;
350 350
351 /* clear the read buffer */ 351 /* clear the read buffer */
352 ctrl->read_bytes = 0; 352 ctrl->read_bytes = 0;
353 if (command != NAND_CMD_PAGEPROG) 353 if (command != NAND_CMD_PAGEPROG)
354 ctrl->index = 0; 354 ctrl->index = 0;
355 355
356 switch (command) { 356 switch (command) {
357 /* READ0 read the entire buffer to use hardware ECC. */ 357 /* READ0 read the entire buffer to use hardware ECC. */
358 case NAND_CMD_READ0: { 358 case NAND_CMD_READ0: {
359 out_be32(&ifc->ifc_nand.nand_fbcr, 0); 359 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
360 set_addr(mtd, 0, page_addr, 0); 360 set_addr(mtd, 0, page_addr, 0);
361 361
362 ctrl->read_bytes = mtd->writesize + mtd->oobsize; 362 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
363 ctrl->index += column; 363 ctrl->index += column;
364 364
365 if (chip->ecc.mode == NAND_ECC_HW) 365 if (chip->ecc.mode == NAND_ECC_HW)
366 ctrl->eccread = 1; 366 ctrl->eccread = 1;
367 367
368 fsl_ifc_do_read(chip, 0, mtd); 368 fsl_ifc_do_read(chip, 0, mtd);
369 fsl_ifc_run_command(mtd); 369 fsl_ifc_run_command(mtd);
370 return; 370 return;
371 } 371 }
372 372
373 /* READOOB reads only the OOB because no ECC is performed. */ 373 /* READOOB reads only the OOB because no ECC is performed. */
374 case NAND_CMD_READOOB: 374 case NAND_CMD_READOOB:
375 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); 375 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
376 set_addr(mtd, column, page_addr, 1); 376 set_addr(mtd, column, page_addr, 1);
377 377
378 ctrl->read_bytes = mtd->writesize + mtd->oobsize; 378 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
379 379
380 fsl_ifc_do_read(chip, 1, mtd); 380 fsl_ifc_do_read(chip, 1, mtd);
381 fsl_ifc_run_command(mtd); 381 fsl_ifc_run_command(mtd);
382 382
383 return; 383 return;
384 384
385 /* READID must read all possible bytes while CEB is active */ 385 /* READID must read all possible bytes while CEB is active */
386 case NAND_CMD_READID: 386 case NAND_CMD_READID:
387 case NAND_CMD_PARAM: { 387 case NAND_CMD_PARAM: {
388 int timing = IFC_FIR_OP_RB; 388 int timing = IFC_FIR_OP_RB;
389 if (command == NAND_CMD_PARAM) 389 if (command == NAND_CMD_PARAM)
390 timing = IFC_FIR_OP_RBCD; 390 timing = IFC_FIR_OP_RBCD;
391 391
392 out_be32(&ifc->ifc_nand.nand_fir0, 392 out_be32(&ifc->ifc_nand.nand_fir0,
393 (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | 393 (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
394 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | 394 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
395 (timing << IFC_NAND_FIR0_OP2_SHIFT)); 395 (timing << IFC_NAND_FIR0_OP2_SHIFT));
396 out_be32(&ifc->ifc_nand.nand_fcr0, 396 out_be32(&ifc->ifc_nand.nand_fcr0,
397 command << IFC_NAND_FCR0_CMD0_SHIFT); 397 command << IFC_NAND_FCR0_CMD0_SHIFT);
398 out_be32(&ifc->ifc_nand.row3, column); 398 out_be32(&ifc->ifc_nand.row3, column);
399 399
400 /* 400 /*
401 * although currently it's 8 bytes for READID, we always read 401 * although currently it's 8 bytes for READID, we always read
402 * the maximum 256 bytes(for PARAM) 402 * the maximum 256 bytes(for PARAM)
403 */ 403 */
404 out_be32(&ifc->ifc_nand.nand_fbcr, 256); 404 out_be32(&ifc->ifc_nand.nand_fbcr, 256);
405 ctrl->read_bytes = 256; 405 ctrl->read_bytes = 256;
406 406
407 set_addr(mtd, 0, 0, 0); 407 set_addr(mtd, 0, 0, 0);
408 fsl_ifc_run_command(mtd); 408 fsl_ifc_run_command(mtd);
409 return; 409 return;
410 } 410 }
411 411
412 /* ERASE1 stores the block and page address */ 412 /* ERASE1 stores the block and page address */
413 case NAND_CMD_ERASE1: 413 case NAND_CMD_ERASE1:
414 set_addr(mtd, 0, page_addr, 0); 414 set_addr(mtd, 0, page_addr, 0);
415 return; 415 return;
416 416
417 /* ERASE2 uses the block and page address from ERASE1 */ 417 /* ERASE2 uses the block and page address from ERASE1 */
418 case NAND_CMD_ERASE2: 418 case NAND_CMD_ERASE2:
419 out_be32(&ifc->ifc_nand.nand_fir0, 419 out_be32(&ifc->ifc_nand.nand_fir0,
420 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 420 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
421 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | 421 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
422 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); 422 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
423 423
424 out_be32(&ifc->ifc_nand.nand_fcr0, 424 out_be32(&ifc->ifc_nand.nand_fcr0,
425 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | 425 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
426 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); 426 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
427 427
428 out_be32(&ifc->ifc_nand.nand_fbcr, 0); 428 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
429 ctrl->read_bytes = 0; 429 ctrl->read_bytes = 0;
430 fsl_ifc_run_command(mtd); 430 fsl_ifc_run_command(mtd);
431 return; 431 return;
432 432
433 /* SEQIN sets up the addr buffer and all registers except the length */ 433 /* SEQIN sets up the addr buffer and all registers except the length */
434 case NAND_CMD_SEQIN: { 434 case NAND_CMD_SEQIN: {
435 u32 nand_fcr0; 435 u32 nand_fcr0;
436 ctrl->column = column; 436 ctrl->column = column;
437 ctrl->oob = 0; 437 ctrl->oob = 0;
438 438
439 if (mtd->writesize > 512) { 439 if (mtd->writesize > 512) {
440 nand_fcr0 = 440 nand_fcr0 =
441 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | 441 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
442 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT); 442 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
443 443
444 out_be32(&ifc->ifc_nand.nand_fir0, 444 out_be32(&ifc->ifc_nand.nand_fir0,
445 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 445 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
446 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 446 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
447 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 447 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
448 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | 448 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
449 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT)); 449 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
450 out_be32(&ifc->ifc_nand.nand_fir1, 0); 450 out_be32(&ifc->ifc_nand.nand_fir1, 0);
451 } else { 451 } else {
452 nand_fcr0 = ((NAND_CMD_PAGEPROG << 452 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
453 IFC_NAND_FCR0_CMD1_SHIFT) | 453 IFC_NAND_FCR0_CMD1_SHIFT) |
454 (NAND_CMD_SEQIN << 454 (NAND_CMD_SEQIN <<
455 IFC_NAND_FCR0_CMD2_SHIFT)); 455 IFC_NAND_FCR0_CMD2_SHIFT));
456 456
457 out_be32(&ifc->ifc_nand.nand_fir0, 457 out_be32(&ifc->ifc_nand.nand_fir0,
458 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 458 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
459 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | 459 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
460 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | 460 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
461 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | 461 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
462 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); 462 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
463 out_be32(&ifc->ifc_nand.nand_fir1, 463 out_be32(&ifc->ifc_nand.nand_fir1,
464 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT)); 464 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
465 465
466 if (column >= mtd->writesize) 466 if (column >= mtd->writesize)
467 nand_fcr0 |= 467 nand_fcr0 |=
468 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT; 468 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
469 else 469 else
470 nand_fcr0 |= 470 nand_fcr0 |=
471 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT; 471 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
472 } 472 }
473 473
474 if (column >= mtd->writesize) { 474 if (column >= mtd->writesize) {
475 /* OOB area --> READOOB */ 475 /* OOB area --> READOOB */
476 column -= mtd->writesize; 476 column -= mtd->writesize;
477 ctrl->oob = 1; 477 ctrl->oob = 1;
478 } 478 }
479 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); 479 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
480 set_addr(mtd, column, page_addr, ctrl->oob); 480 set_addr(mtd, column, page_addr, ctrl->oob);
481 return; 481 return;
482 } 482 }
483 483
484 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ 484 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
485 case NAND_CMD_PAGEPROG: 485 case NAND_CMD_PAGEPROG:
486 if (ctrl->oob) 486 if (ctrl->oob)
487 out_be32(&ifc->ifc_nand.nand_fbcr, 487 out_be32(&ifc->ifc_nand.nand_fbcr,
488 ctrl->index - ctrl->column); 488 ctrl->index - ctrl->column);
489 else 489 else
490 out_be32(&ifc->ifc_nand.nand_fbcr, 0); 490 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
491 491
492 fsl_ifc_run_command(mtd); 492 fsl_ifc_run_command(mtd);
493 return; 493 return;
494 494
495 case NAND_CMD_STATUS: 495 case NAND_CMD_STATUS:
496 out_be32(&ifc->ifc_nand.nand_fir0, 496 out_be32(&ifc->ifc_nand.nand_fir0,
497 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 497 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
498 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); 498 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
499 out_be32(&ifc->ifc_nand.nand_fcr0, 499 out_be32(&ifc->ifc_nand.nand_fcr0,
500 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); 500 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
501 out_be32(&ifc->ifc_nand.nand_fbcr, 1); 501 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
502 set_addr(mtd, 0, 0, 0); 502 set_addr(mtd, 0, 0, 0);
503 ctrl->read_bytes = 1; 503 ctrl->read_bytes = 1;
504 504
505 fsl_ifc_run_command(mtd); 505 fsl_ifc_run_command(mtd);
506 506
507 /* Chip sometimes reporting write protect even when it's not */ 507 /* Chip sometimes reporting write protect even when it's not */
508 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); 508 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
509 return; 509 return;
510 510
511 case NAND_CMD_RESET: 511 case NAND_CMD_RESET:
512 out_be32(&ifc->ifc_nand.nand_fir0, 512 out_be32(&ifc->ifc_nand.nand_fir0,
513 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); 513 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
514 out_be32(&ifc->ifc_nand.nand_fcr0, 514 out_be32(&ifc->ifc_nand.nand_fcr0,
515 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); 515 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
516 fsl_ifc_run_command(mtd); 516 fsl_ifc_run_command(mtd);
517 return; 517 return;
518 518
519 default: 519 default:
520 printf("%s: error, unsupported command 0x%x.\n", 520 printf("%s: error, unsupported command 0x%x.\n",
521 __func__, command); 521 __func__, command);
522 } 522 }
523 } 523 }
524 524
525 /* 525 /*
526 * Write buf to the IFC NAND Controller Data Buffer 526 * Write buf to the IFC NAND Controller Data Buffer
527 */ 527 */
528 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) 528 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
529 { 529 {
530 struct nand_chip *chip = mtd->priv; 530 struct nand_chip *chip = mtd->priv;
531 struct fsl_ifc_mtd *priv = chip->priv; 531 struct fsl_ifc_mtd *priv = chip->priv;
532 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 532 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
533 unsigned int bufsize = mtd->writesize + mtd->oobsize; 533 unsigned int bufsize = mtd->writesize + mtd->oobsize;
534 534
535 if (len <= 0) { 535 if (len <= 0) {
536 printf("%s of %d bytes", __func__, len); 536 printf("%s of %d bytes", __func__, len);
537 ctrl->status = 0; 537 ctrl->status = 0;
538 return; 538 return;
539 } 539 }
540 540
541 if ((unsigned int)len > bufsize - ctrl->index) { 541 if ((unsigned int)len > bufsize - ctrl->index) {
542 printf("%s beyond end of buffer " 542 printf("%s beyond end of buffer "
543 "(%d requested, %u available)\n", 543 "(%d requested, %u available)\n",
544 __func__, len, bufsize - ctrl->index); 544 __func__, len, bufsize - ctrl->index);
545 len = bufsize - ctrl->index; 545 len = bufsize - ctrl->index;
546 } 546 }
547 547
548 memcpy_toio(&ctrl->addr[ctrl->index], buf, len); 548 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
549 ctrl->index += len; 549 ctrl->index += len;
550 } 550 }
551 551
552 /* 552 /*
553 * read a byte from either the IFC hardware buffer if it has any data left 553 * read a byte from either the IFC hardware buffer if it has any data left
554 * otherwise issue a command to read a single byte. 554 * otherwise issue a command to read a single byte.
555 */ 555 */
556 static u8 fsl_ifc_read_byte(struct mtd_info *mtd) 556 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
557 { 557 {
558 struct nand_chip *chip = mtd->priv; 558 struct nand_chip *chip = mtd->priv;
559 struct fsl_ifc_mtd *priv = chip->priv; 559 struct fsl_ifc_mtd *priv = chip->priv;
560 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 560 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
561 561
562 /* If there are still bytes in the IFC buffer, then use the 562 /* If there are still bytes in the IFC buffer, then use the
563 * next byte. */ 563 * next byte. */
564 if (ctrl->index < ctrl->read_bytes) 564 if (ctrl->index < ctrl->read_bytes)
565 return in_8(&ctrl->addr[ctrl->index++]); 565 return in_8(&ctrl->addr[ctrl->index++]);
566 566
567 printf("%s beyond end of buffer\n", __func__); 567 printf("%s beyond end of buffer\n", __func__);
568 return ERR_BYTE; 568 return ERR_BYTE;
569 } 569 }
570 570
571 /* 571 /*
572 * Read two bytes from the IFC hardware buffer 572 * Read two bytes from the IFC hardware buffer
573 * read function for 16-bit buswith 573 * read function for 16-bit buswith
574 */ 574 */
575 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) 575 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
576 { 576 {
577 struct nand_chip *chip = mtd->priv; 577 struct nand_chip *chip = mtd->priv;
578 struct fsl_ifc_mtd *priv = chip->priv; 578 struct fsl_ifc_mtd *priv = chip->priv;
579 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 579 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
580 uint16_t data; 580 uint16_t data;
581 581
582 /* 582 /*
583 * If there are still bytes in the IFC buffer, then use the 583 * If there are still bytes in the IFC buffer, then use the
584 * next byte. 584 * next byte.
585 */ 585 */
586 if (ctrl->index < ctrl->read_bytes) { 586 if (ctrl->index < ctrl->read_bytes) {
587 data = in_be16((uint16_t *)&ctrl-> 587 data = in_be16((uint16_t *)&ctrl->
588 addr[ctrl->index]); 588 addr[ctrl->index]);
589 ctrl->index += 2; 589 ctrl->index += 2;
590 return (uint8_t)data; 590 return (uint8_t)data;
591 } 591 }
592 592
593 printf("%s beyond end of buffer\n", __func__); 593 printf("%s beyond end of buffer\n", __func__);
594 return ERR_BYTE; 594 return ERR_BYTE;
595 } 595 }
596 596
597 /* 597 /*
598 * Read from the IFC Controller Data Buffer 598 * Read from the IFC Controller Data Buffer
599 */ 599 */
600 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) 600 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
601 { 601 {
602 struct nand_chip *chip = mtd->priv; 602 struct nand_chip *chip = mtd->priv;
603 struct fsl_ifc_mtd *priv = chip->priv; 603 struct fsl_ifc_mtd *priv = chip->priv;
604 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 604 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
605 int avail; 605 int avail;
606 606
607 if (len < 0) 607 if (len < 0)
608 return; 608 return;
609 609
610 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index); 610 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
611 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail); 611 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
612 ctrl->index += avail; 612 ctrl->index += avail;
613 613
614 if (len > avail) 614 if (len > avail)
615 printf("%s beyond end of buffer " 615 printf("%s beyond end of buffer "
616 "(%d requested, %d available)\n", 616 "(%d requested, %d available)\n",
617 __func__, len, avail); 617 __func__, len, avail);
618 } 618 }
619 619
620 /* 620 /*
621 * Verify buffer against the IFC Controller Data Buffer 621 * Verify buffer against the IFC Controller Data Buffer
622 */ 622 */
623 static int fsl_ifc_verify_buf(struct mtd_info *mtd, 623 static int fsl_ifc_verify_buf(struct mtd_info *mtd,
624 const u_char *buf, int len) 624 const u_char *buf, int len)
625 { 625 {
626 struct nand_chip *chip = mtd->priv; 626 struct nand_chip *chip = mtd->priv;
627 struct fsl_ifc_mtd *priv = chip->priv; 627 struct fsl_ifc_mtd *priv = chip->priv;
628 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 628 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
629 int i; 629 int i;
630 630
631 if (len < 0) { 631 if (len < 0) {
632 printf("%s of %d bytes", __func__, len); 632 printf("%s of %d bytes", __func__, len);
633 return -EINVAL; 633 return -EINVAL;
634 } 634 }
635 635
636 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { 636 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
637 printf("%s beyond end of buffer " 637 printf("%s beyond end of buffer "
638 "(%d requested, %u available)\n", 638 "(%d requested, %u available)\n",
639 __func__, len, ctrl->read_bytes - ctrl->index); 639 __func__, len, ctrl->read_bytes - ctrl->index);
640 640
641 ctrl->index = ctrl->read_bytes; 641 ctrl->index = ctrl->read_bytes;
642 return -EINVAL; 642 return -EINVAL;
643 } 643 }
644 644
645 for (i = 0; i < len; i++) 645 for (i = 0; i < len; i++)
646 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) 646 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
647 break; 647 break;
648 648
649 ctrl->index += len; 649 ctrl->index += len;
650 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO; 650 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
651 } 651 }
652 652
653 /* This function is called after Program and Erase Operations to 653 /* This function is called after Program and Erase Operations to
654 * check for success or failure. 654 * check for success or failure.
655 */ 655 */
656 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) 656 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
657 { 657 {
658 struct fsl_ifc_mtd *priv = chip->priv; 658 struct fsl_ifc_mtd *priv = chip->priv;
659 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 659 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
660 struct fsl_ifc *ifc = ctrl->regs; 660 struct fsl_ifc *ifc = ctrl->regs;
661 u32 nand_fsr; 661 u32 nand_fsr;
662 662
663 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) 663 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
664 return NAND_STATUS_FAIL; 664 return NAND_STATUS_FAIL;
665 665
666 /* Use READ_STATUS command, but wait for the device to be ready */ 666 /* Use READ_STATUS command, but wait for the device to be ready */
667 out_be32(&ifc->ifc_nand.nand_fir0, 667 out_be32(&ifc->ifc_nand.nand_fir0,
668 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 668 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
669 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); 669 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
670 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << 670 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
671 IFC_NAND_FCR0_CMD0_SHIFT); 671 IFC_NAND_FCR0_CMD0_SHIFT);
672 out_be32(&ifc->ifc_nand.nand_fbcr, 1); 672 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
673 set_addr(mtd, 0, 0, 0); 673 set_addr(mtd, 0, 0, 0);
674 ctrl->read_bytes = 1; 674 ctrl->read_bytes = 1;
675 675
676 fsl_ifc_run_command(mtd); 676 fsl_ifc_run_command(mtd);
677 677
678 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) 678 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
679 return NAND_STATUS_FAIL; 679 return NAND_STATUS_FAIL;
680 680
681 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr); 681 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
682 682
683 /* Chip sometimes reporting write protect even when it's not */ 683 /* Chip sometimes reporting write protect even when it's not */
684 nand_fsr = nand_fsr | NAND_STATUS_WP; 684 nand_fsr = nand_fsr | NAND_STATUS_WP;
685 return nand_fsr; 685 return nand_fsr;
686 } 686 }
687 687
688 static int fsl_ifc_read_page(struct mtd_info *mtd, 688 static int fsl_ifc_read_page(struct mtd_info *mtd,
689 struct nand_chip *chip, 689 struct nand_chip *chip,
690 uint8_t *buf, int page) 690 uint8_t *buf, int page)
691 { 691 {
692 struct fsl_ifc_mtd *priv = chip->priv; 692 struct fsl_ifc_mtd *priv = chip->priv;
693 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 693 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
694 694
695 fsl_ifc_read_buf(mtd, buf, mtd->writesize); 695 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
696 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); 696 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
697 697
698 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) 698 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
699 mtd->ecc_stats.failed++; 699 mtd->ecc_stats.failed++;
700 700
701 return 0; 701 return 0;
702 } 702 }
703 703
704 /* ECC will be calculated automatically, and errors will be detected in 704 /* ECC will be calculated automatically, and errors will be detected in
705 * waitfunc. 705 * waitfunc.
706 */ 706 */
707 static void fsl_ifc_write_page(struct mtd_info *mtd, 707 static void fsl_ifc_write_page(struct mtd_info *mtd,
708 struct nand_chip *chip, 708 struct nand_chip *chip,
709 const uint8_t *buf) 709 const uint8_t *buf)
710 { 710 {
711 fsl_ifc_write_buf(mtd, buf, mtd->writesize); 711 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
712 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize); 712 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
713 } 713 }
714 714
715 static void fsl_ifc_ctrl_init(void) 715 static void fsl_ifc_ctrl_init(void)
716 { 716 {
717 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL); 717 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
718 if (!ifc_ctrl) 718 if (!ifc_ctrl)
719 return; 719 return;
720 720
721 ifc_ctrl->regs = IFC_BASE_ADDR; 721 ifc_ctrl->regs = IFC_BASE_ADDR;
722 722
723 /* clear event registers */ 723 /* clear event registers */
724 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); 724 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
725 out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); 725 out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
726 726
727 /* Enable error and event for any detected errors */ 727 /* Enable error and event for any detected errors */
728 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, 728 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
729 IFC_NAND_EVTER_EN_OPC_EN | 729 IFC_NAND_EVTER_EN_OPC_EN |
730 IFC_NAND_EVTER_EN_PGRDCMPL_EN | 730 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
731 IFC_NAND_EVTER_EN_FTOER_EN | 731 IFC_NAND_EVTER_EN_FTOER_EN |
732 IFC_NAND_EVTER_EN_WPER_EN); 732 IFC_NAND_EVTER_EN_WPER_EN);
733 733
734 out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); 734 out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
735 } 735 }
736 736
737 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) 737 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
738 { 738 {
739 } 739 }
740 740
741 int board_nand_init(struct nand_chip *nand) 741 int board_nand_init(struct nand_chip *nand)
742 { 742 {
743 struct fsl_ifc_mtd *priv; 743 struct fsl_ifc_mtd *priv;
744 struct nand_ecclayout *layout; 744 struct nand_ecclayout *layout;
745 uint32_t cspr = 0, csor = 0; 745 uint32_t cspr = 0, csor = 0;
746 746
747 if (!ifc_ctrl) { 747 if (!ifc_ctrl) {
748 fsl_ifc_ctrl_init(); 748 fsl_ifc_ctrl_init();
749 if (!ifc_ctrl) 749 if (!ifc_ctrl)
750 return -1; 750 return -1;
751 } 751 }
752 752
753 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 753 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
754 if (!priv) 754 if (!priv)
755 return -ENOMEM; 755 return -ENOMEM;
756 756
757 priv->ctrl = ifc_ctrl; 757 priv->ctrl = ifc_ctrl;
758 priv->vbase = nand->IO_ADDR_R; 758 priv->vbase = nand->IO_ADDR_R;
759 759
760 /* Find which chip select it is connected to. 760 /* Find which chip select it is connected to.
761 */ 761 */
762 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { 762 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
763 phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R); 763 phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
764 764
765 cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); 765 cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
766 csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); 766 csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
767 767
768 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && 768 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
769 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(base_addr)) { 769 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(base_addr)) {
770 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT; 770 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
771 break; 771 break;
772 } 772 }
773 } 773 }
774 774
775 if (priv->bank >= MAX_BANKS) { 775 if (priv->bank >= MAX_BANKS) {
776 printf("%s: address did not match any " 776 printf("%s: address did not match any "
777 "chip selects\n", __func__); 777 "chip selects\n", __func__);
778 kfree(priv);
778 return -ENODEV; 779 return -ENODEV;
779 } 780 }
780 781
781 ifc_ctrl->chips[priv->bank] = priv; 782 ifc_ctrl->chips[priv->bank] = priv;
782 783
783 /* fill in nand_chip structure */ 784 /* fill in nand_chip structure */
784 /* set up function call table */ 785 /* set up function call table */
785 786
786 nand->write_buf = fsl_ifc_write_buf; 787 nand->write_buf = fsl_ifc_write_buf;
787 nand->read_buf = fsl_ifc_read_buf; 788 nand->read_buf = fsl_ifc_read_buf;
788 nand->verify_buf = fsl_ifc_verify_buf; 789 nand->verify_buf = fsl_ifc_verify_buf;
789 nand->select_chip = fsl_ifc_select_chip; 790 nand->select_chip = fsl_ifc_select_chip;
790 nand->cmdfunc = fsl_ifc_cmdfunc; 791 nand->cmdfunc = fsl_ifc_cmdfunc;
791 nand->waitfunc = fsl_ifc_wait; 792 nand->waitfunc = fsl_ifc_wait;
792 793
793 /* set up nand options */ 794 /* set up nand options */
794 nand->bbt_td = &bbt_main_descr; 795 nand->bbt_td = &bbt_main_descr;
795 nand->bbt_md = &bbt_mirror_descr; 796 nand->bbt_md = &bbt_mirror_descr;
796 797
797 /* set up nand options */ 798 /* set up nand options */
798 nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR | 799 nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
799 NAND_USE_FLASH_BBT; 800 NAND_USE_FLASH_BBT;
800 801
801 if (cspr & CSPR_PORT_SIZE_16) { 802 if (cspr & CSPR_PORT_SIZE_16) {
802 nand->read_byte = fsl_ifc_read_byte16; 803 nand->read_byte = fsl_ifc_read_byte16;
803 nand->options |= NAND_BUSWIDTH_16; 804 nand->options |= NAND_BUSWIDTH_16;
804 } else { 805 } else {
805 nand->read_byte = fsl_ifc_read_byte; 806 nand->read_byte = fsl_ifc_read_byte;
806 } 807 }
807 808
808 nand->controller = &ifc_ctrl->controller; 809 nand->controller = &ifc_ctrl->controller;
809 nand->priv = priv; 810 nand->priv = priv;
810 811
811 nand->ecc.read_page = fsl_ifc_read_page; 812 nand->ecc.read_page = fsl_ifc_read_page;
812 nand->ecc.write_page = fsl_ifc_write_page; 813 nand->ecc.write_page = fsl_ifc_write_page;
813 814
814 /* Hardware generates ECC per 512 Bytes */ 815 /* Hardware generates ECC per 512 Bytes */
815 nand->ecc.size = 512; 816 nand->ecc.size = 512;
816 nand->ecc.bytes = 8; 817 nand->ecc.bytes = 8;
817 818
818 switch (csor & CSOR_NAND_PGS_MASK) { 819 switch (csor & CSOR_NAND_PGS_MASK) {
819 case CSOR_NAND_PGS_512: 820 case CSOR_NAND_PGS_512:
820 if (nand->options & NAND_BUSWIDTH_16) { 821 if (nand->options & NAND_BUSWIDTH_16) {
821 layout = &oob_512_16bit_ecc4; 822 layout = &oob_512_16bit_ecc4;
822 } else { 823 } else {
823 layout = &oob_512_8bit_ecc4; 824 layout = &oob_512_8bit_ecc4;
824 825
825 /* Avoid conflict with bad block marker */ 826 /* Avoid conflict with bad block marker */
826 bbt_main_descr.offs = 0; 827 bbt_main_descr.offs = 0;
827 bbt_mirror_descr.offs = 0; 828 bbt_mirror_descr.offs = 0;
828 } 829 }
829 830
830 priv->bufnum_mask = 15; 831 priv->bufnum_mask = 15;
831 break; 832 break;
832 833
833 case CSOR_NAND_PGS_2K: 834 case CSOR_NAND_PGS_2K:
834 layout = &oob_2048_ecc4; 835 layout = &oob_2048_ecc4;
835 priv->bufnum_mask = 3; 836 priv->bufnum_mask = 3;
836 break; 837 break;
837 838
838 case CSOR_NAND_PGS_4K: 839 case CSOR_NAND_PGS_4K:
839 if ((csor & CSOR_NAND_ECC_MODE_MASK) == 840 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
840 CSOR_NAND_ECC_MODE_4) { 841 CSOR_NAND_ECC_MODE_4) {
841 layout = &oob_4096_ecc4; 842 layout = &oob_4096_ecc4;
842 } else { 843 } else {
843 layout = &oob_4096_ecc8; 844 layout = &oob_4096_ecc8;
844 nand->ecc.bytes = 16; 845 nand->ecc.bytes = 16;
845 } 846 }
846 847
847 priv->bufnum_mask = 1; 848 priv->bufnum_mask = 1;
848 break; 849 break;
849 850
850 default: 851 default:
851 printf("ifc nand: bad csor %#x: bad page size\n", csor); 852 printf("ifc nand: bad csor %#x: bad page size\n", csor);
852 return -ENODEV; 853 return -ENODEV;
853 } 854 }
854 855
855 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */ 856 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
856 if (csor & CSOR_NAND_ECC_DEC_EN) { 857 if (csor & CSOR_NAND_ECC_DEC_EN) {
857 nand->ecc.mode = NAND_ECC_HW; 858 nand->ecc.mode = NAND_ECC_HW;
858 nand->ecc.layout = layout; 859 nand->ecc.layout = layout;
859 } else { 860 } else {
860 nand->ecc.mode = NAND_ECC_SOFT; 861 nand->ecc.mode = NAND_ECC_SOFT;
861 } 862 }
862 863
863 return 0; 864 return 0;
864 } 865 }
865 866