Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 7ae8350f67eea861280a4cbd2d067777a0e87153

Authored by Simon Glass
Committed by Tom Rini
1 parent 905949190d
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ti: armv7: Move SPL SDRAM init to the right place, drop unused CONFIG_SPL_STACK 

Currently in some cases SDRAM init requires global_data to be available
and soon this will not be available prior to board_init_f().  Adjust the
code paths in these cases to be correct.  In some cases we had the SPL
stack be in DDR as we might have large stacks (due to Falcon Mode +
Environment).  In these cases switch to CONFIG_SPL_STACK_R.  In other
cases we had simply been setting CONFIG_SPL_STACK into SRAM.  In these
cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also
in SRAM) so drop those lines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested on Beagleboard, Beagleboard xM
Tested-by: Matt Porter <mporter@konsulko.com>
Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Showing 23 changed files with 36 additions and 25 deletions Inline Diff

arch/arm/cpu/armv7/am33xx/board.c
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * board.c 2 * board.c
3 * 3 *
4 * Common board functions for AM33XX based boards 4 * Common board functions for AM33XX based boards
5 * 5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <dm.h> 12 #include <dm.h>
13 #include <errno.h> 13 #include <errno.h>
14 #include <ns16550.h> 14 #include <ns16550.h>
15 #include <spl.h> 15 #include <spl.h>
16 #include <asm/arch/cpu.h> 16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h> 17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h> 18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h> 20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h> 21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mem.h> 22 #include <asm/arch/mem.h>
23 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/sys_proto.h>
25 #include <asm/io.h> 25 #include <asm/io.h>
26 #include <asm/emif.h> 26 #include <asm/emif.h>
27 #include <asm/gpio.h> 27 #include <asm/gpio.h>
28 #include <i2c.h> 28 #include <i2c.h>
29 #include <miiphy.h> 29 #include <miiphy.h>
30 #include <cpsw.h> 30 #include <cpsw.h>
31 #include <asm/errno.h> 31 #include <asm/errno.h>
32 #include <linux/compiler.h> 32 #include <linux/compiler.h>
33 #include <linux/usb/ch9.h> 33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h> 34 #include <linux/usb/gadget.h>
35 #include <linux/usb/musb.h> 35 #include <linux/usb/musb.h>
36 #include <asm/omap_musb.h> 36 #include <asm/omap_musb.h>
37 #include <asm/davinci_rtc.h> 37 #include <asm/davinci_rtc.h>
38 38
39 DECLARE_GLOBAL_DATA_PTR; 39 DECLARE_GLOBAL_DATA_PTR;
40 40
41 #ifdef CONFIG_DM_GPIO 41 #ifdef CONFIG_DM_GPIO
42 static const struct omap_gpio_platdata am33xx_gpio[] = { 42 static const struct omap_gpio_platdata am33xx_gpio[] = {
43 { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, 43 { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
44 { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, 44 { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
45 { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, 45 { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
46 { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, 46 { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
47 #ifdef CONFIG_AM43XX 47 #ifdef CONFIG_AM43XX
48 { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX }, 48 { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
49 { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX }, 49 { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
50 #endif 50 #endif
51 }; 51 };
52 52
53 U_BOOT_DEVICES(am33xx_gpios) = { 53 U_BOOT_DEVICES(am33xx_gpios) = {
54 { "gpio_omap", &am33xx_gpio[0] }, 54 { "gpio_omap", &am33xx_gpio[0] },
55 { "gpio_omap", &am33xx_gpio[1] }, 55 { "gpio_omap", &am33xx_gpio[1] },
56 { "gpio_omap", &am33xx_gpio[2] }, 56 { "gpio_omap", &am33xx_gpio[2] },
57 { "gpio_omap", &am33xx_gpio[3] }, 57 { "gpio_omap", &am33xx_gpio[3] },
58 #ifdef CONFIG_AM43XX 58 #ifdef CONFIG_AM43XX
59 { "gpio_omap", &am33xx_gpio[4] }, 59 { "gpio_omap", &am33xx_gpio[4] },
60 { "gpio_omap", &am33xx_gpio[5] }, 60 { "gpio_omap", &am33xx_gpio[5] },
61 #endif 61 #endif
62 }; 62 };
63 63
64 # ifndef CONFIG_OF_CONTROL 64 # ifndef CONFIG_OF_CONTROL
65 /* 65 /*
66 * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove 66 * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
67 * the CONFIGs. At the same time, we should move this to the board files. 67 * the CONFIGs. At the same time, we should move this to the board files.
68 */ 68 */
69 static const struct ns16550_platdata am33xx_serial[] = { 69 static const struct ns16550_platdata am33xx_serial[] = {
70 { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK }, 70 { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
71 # ifdef CONFIG_SYS_NS16550_COM2 71 # ifdef CONFIG_SYS_NS16550_COM2
72 { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK }, 72 { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
73 # ifdef CONFIG_SYS_NS16550_COM3 73 # ifdef CONFIG_SYS_NS16550_COM3
74 { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK }, 74 { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
75 { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK }, 75 { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
76 { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK }, 76 { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
77 { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK }, 77 { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
78 # endif 78 # endif
79 # endif 79 # endif
80 }; 80 };
81 81
82 U_BOOT_DEVICES(am33xx_uarts) = { 82 U_BOOT_DEVICES(am33xx_uarts) = {
83 { "serial_omap", &am33xx_serial[0] }, 83 { "serial_omap", &am33xx_serial[0] },
84 # ifdef CONFIG_SYS_NS16550_COM2 84 # ifdef CONFIG_SYS_NS16550_COM2
85 { "serial_omap", &am33xx_serial[1] }, 85 { "serial_omap", &am33xx_serial[1] },
86 # ifdef CONFIG_SYS_NS16550_COM3 86 # ifdef CONFIG_SYS_NS16550_COM3
87 { "serial_omap", &am33xx_serial[2] }, 87 { "serial_omap", &am33xx_serial[2] },
88 { "serial_omap", &am33xx_serial[3] }, 88 { "serial_omap", &am33xx_serial[3] },
89 { "serial_omap", &am33xx_serial[4] }, 89 { "serial_omap", &am33xx_serial[4] },
90 { "serial_omap", &am33xx_serial[5] }, 90 { "serial_omap", &am33xx_serial[5] },
91 # endif 91 # endif
92 # endif 92 # endif
93 }; 93 };
94 # endif 94 # endif
95 95
96 #else 96 #else
97 97
98 static const struct gpio_bank gpio_bank_am33xx[] = { 98 static const struct gpio_bank gpio_bank_am33xx[] = {
99 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, 99 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
100 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, 100 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
101 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, 101 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
102 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, 102 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
103 #ifdef CONFIG_AM43XX 103 #ifdef CONFIG_AM43XX
104 { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX }, 104 { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
105 { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX }, 105 { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
106 #endif 106 #endif
107 }; 107 };
108 108
109 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 109 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
110 110
111 #endif 111 #endif
112 112
113 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) 113 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
114 int cpu_mmc_init(bd_t *bis) 114 int cpu_mmc_init(bd_t *bis)
115 { 115 {
116 int ret; 116 int ret;
117 117
118 ret = omap_mmc_init(0, 0, 0, -1, -1); 118 ret = omap_mmc_init(0, 0, 0, -1, -1);
119 if (ret) 119 if (ret)
120 return ret; 120 return ret;
121 121
122 return omap_mmc_init(1, 0, 0, -1, -1); 122 return omap_mmc_init(1, 0, 0, -1, -1);
123 } 123 }
124 #endif 124 #endif
125 125
126 /* AM33XX has two MUSB controllers which can be host or gadget */ 126 /* AM33XX has two MUSB controllers which can be host or gadget */
127 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \ 127 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
128 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) 128 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
129 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 129 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
130 130
131 /* USB 2.0 PHY Control */ 131 /* USB 2.0 PHY Control */
132 #define CM_PHY_PWRDN (1 << 0) 132 #define CM_PHY_PWRDN (1 << 0)
133 #define CM_PHY_OTG_PWRDN (1 << 1) 133 #define CM_PHY_OTG_PWRDN (1 << 1)
134 #define OTGVDET_EN (1 << 19) 134 #define OTGVDET_EN (1 << 19)
135 #define OTGSESSENDEN (1 << 20) 135 #define OTGSESSENDEN (1 << 20)
136 136
137 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 137 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
138 { 138 {
139 if (on) { 139 if (on) {
140 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 140 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
141 OTGVDET_EN | OTGSESSENDEN); 141 OTGVDET_EN | OTGSESSENDEN);
142 } else { 142 } else {
143 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 143 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
144 } 144 }
145 } 145 }
146 146
147 static struct musb_hdrc_config musb_config = { 147 static struct musb_hdrc_config musb_config = {
148 .multipoint = 1, 148 .multipoint = 1,
149 .dyn_fifo = 1, 149 .dyn_fifo = 1,
150 .num_eps = 16, 150 .num_eps = 16,
151 .ram_bits = 12, 151 .ram_bits = 12,
152 }; 152 };
153 153
154 #ifdef CONFIG_AM335X_USB0 154 #ifdef CONFIG_AM335X_USB0
155 static void am33xx_otg0_set_phy_power(u8 on) 155 static void am33xx_otg0_set_phy_power(u8 on)
156 { 156 {
157 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 157 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
158 } 158 }
159 159
160 struct omap_musb_board_data otg0_board_data = { 160 struct omap_musb_board_data otg0_board_data = {
161 .set_phy_power = am33xx_otg0_set_phy_power, 161 .set_phy_power = am33xx_otg0_set_phy_power,
162 }; 162 };
163 163
164 static struct musb_hdrc_platform_data otg0_plat = { 164 static struct musb_hdrc_platform_data otg0_plat = {
165 .mode = CONFIG_AM335X_USB0_MODE, 165 .mode = CONFIG_AM335X_USB0_MODE,
166 .config = &musb_config, 166 .config = &musb_config,
167 .power = 50, 167 .power = 50,
168 .platform_ops = &musb_dsps_ops, 168 .platform_ops = &musb_dsps_ops,
169 .board_data = &otg0_board_data, 169 .board_data = &otg0_board_data,
170 }; 170 };
171 #endif 171 #endif
172 172
173 #ifdef CONFIG_AM335X_USB1 173 #ifdef CONFIG_AM335X_USB1
174 static void am33xx_otg1_set_phy_power(u8 on) 174 static void am33xx_otg1_set_phy_power(u8 on)
175 { 175 {
176 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 176 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
177 } 177 }
178 178
179 struct omap_musb_board_data otg1_board_data = { 179 struct omap_musb_board_data otg1_board_data = {
180 .set_phy_power = am33xx_otg1_set_phy_power, 180 .set_phy_power = am33xx_otg1_set_phy_power,
181 }; 181 };
182 182
183 static struct musb_hdrc_platform_data otg1_plat = { 183 static struct musb_hdrc_platform_data otg1_plat = {
184 .mode = CONFIG_AM335X_USB1_MODE, 184 .mode = CONFIG_AM335X_USB1_MODE,
185 .config = &musb_config, 185 .config = &musb_config,
186 .power = 50, 186 .power = 50,
187 .platform_ops = &musb_dsps_ops, 187 .platform_ops = &musb_dsps_ops,
188 .board_data = &otg1_board_data, 188 .board_data = &otg1_board_data,
189 }; 189 };
190 #endif 190 #endif
191 #endif 191 #endif
192 192
193 int arch_misc_init(void) 193 int arch_misc_init(void)
194 { 194 {
195 #ifdef CONFIG_AM335X_USB0 195 #ifdef CONFIG_AM335X_USB0
196 musb_register(&otg0_plat, &otg0_board_data, 196 musb_register(&otg0_plat, &otg0_board_data,
197 (void *)USB0_OTG_BASE); 197 (void *)USB0_OTG_BASE);
198 #endif 198 #endif
199 #ifdef CONFIG_AM335X_USB1 199 #ifdef CONFIG_AM335X_USB1
200 musb_register(&otg1_plat, &otg1_board_data, 200 musb_register(&otg1_plat, &otg1_board_data,
201 (void *)USB1_OTG_BASE); 201 (void *)USB1_OTG_BASE);
202 #endif 202 #endif
203 return 0; 203 return 0;
204 } 204 }
205 205
206 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 206 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
207 /* 207 /*
208 * In the case of non-SPL based booting we'll want to call these 208 * In the case of non-SPL based booting we'll want to call these
209 * functions a tiny bit later as it will require gd to be set and cleared 209 * functions a tiny bit later as it will require gd to be set and cleared
210 * and that's not true in s_init in this case so we cannot do it there. 210 * and that's not true in s_init in this case so we cannot do it there.
211 */ 211 */
212 int board_early_init_f(void) 212 int board_early_init_f(void)
213 { 213 {
214 prcm_init(); 214 prcm_init();
215 set_mux_conf_regs(); 215 set_mux_conf_regs();
216 216
217 return 0; 217 return 0;
218 } 218 }
219 219
220 /* 220 /*
221 * This function is the place to do per-board things such as ramp up the 221 * This function is the place to do per-board things such as ramp up the
222 * MPU clock frequency. 222 * MPU clock frequency.
223 */ 223 */
224 __weak void am33xx_spl_board_init(void) 224 __weak void am33xx_spl_board_init(void)
225 { 225 {
226 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 226 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
227 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 227 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
228 } 228 }
229 229
230 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 230 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
231 static void rtc32k_enable(void) 231 static void rtc32k_enable(void)
232 { 232 {
233 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 233 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
234 234
235 /* 235 /*
236 * Unlock the RTC's registers. For more details please see the 236 * Unlock the RTC's registers. For more details please see the
237 * RTC_SS section of the TRM. In order to unlock we need to 237 * RTC_SS section of the TRM. In order to unlock we need to
238 * write these specific values (keys) in this order. 238 * write these specific values (keys) in this order.
239 */ 239 */
240 writel(RTC_KICK0R_WE, &rtc->kick0r); 240 writel(RTC_KICK0R_WE, &rtc->kick0r);
241 writel(RTC_KICK1R_WE, &rtc->kick1r); 241 writel(RTC_KICK1R_WE, &rtc->kick1r);
242 242
243 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 243 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
244 writel((1 << 3) | (1 << 6), &rtc->osc); 244 writel((1 << 3) | (1 << 6), &rtc->osc);
245 } 245 }
246 #endif 246 #endif
247 247
248 static void uart_soft_reset(void) 248 static void uart_soft_reset(void)
249 { 249 {
250 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 250 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
251 u32 regval; 251 u32 regval;
252 252
253 regval = readl(&uart_base->uartsyscfg); 253 regval = readl(&uart_base->uartsyscfg);
254 regval |= UART_RESET; 254 regval |= UART_RESET;
255 writel(regval, &uart_base->uartsyscfg); 255 writel(regval, &uart_base->uartsyscfg);
256 while ((readl(&uart_base->uartsyssts) & 256 while ((readl(&uart_base->uartsyssts) &
257 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 257 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
258 ; 258 ;
259 259
260 /* Disable smart idle */ 260 /* Disable smart idle */
261 regval = readl(&uart_base->uartsyscfg); 261 regval = readl(&uart_base->uartsyscfg);
262 regval |= UART_SMART_IDLE_EN; 262 regval |= UART_SMART_IDLE_EN;
263 writel(regval, &uart_base->uartsyscfg); 263 writel(regval, &uart_base->uartsyscfg);
264 } 264 }
265 265
266 static void watchdog_disable(void) 266 static void watchdog_disable(void)
267 { 267 {
268 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 268 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
269 269
270 writel(0xAAAA, &wdtimer->wdtwspr); 270 writel(0xAAAA, &wdtimer->wdtwspr);
271 while (readl(&wdtimer->wdtwwps) != 0x0) 271 while (readl(&wdtimer->wdtwwps) != 0x0)
272 ; 272 ;
273 writel(0x5555, &wdtimer->wdtwspr); 273 writel(0x5555, &wdtimer->wdtwspr);
274 while (readl(&wdtimer->wdtwwps) != 0x0) 274 while (readl(&wdtimer->wdtwwps) != 0x0)
275 ; 275 ;
276 } 276 }
277 277
278 #ifdef CONFIG_SPL_BUILD
279 void board_init_f(ulong dummy)
280 {
281 board_early_init_f();
282 sdram_init();
283 }
284 #endif
285
278 void s_init(void) 286 void s_init(void)
279 { 287 {
280 /* 288 /*
281 * The ROM will only have set up sufficient pinmux to allow for the 289 * The ROM will only have set up sufficient pinmux to allow for the
282 * first 4KiB NOR to be read, we must finish doing what we know of 290 * first 4KiB NOR to be read, we must finish doing what we know of
283 * the NOR mux in this space in order to continue. 291 * the NOR mux in this space in order to continue.
284 */ 292 */
285 #ifdef CONFIG_NOR_BOOT 293 #ifdef CONFIG_NOR_BOOT
286 enable_norboot_pin_mux(); 294 enable_norboot_pin_mux();
287 #endif 295 #endif
288 watchdog_disable(); 296 watchdog_disable();
289 set_uart_mux_conf(); 297 set_uart_mux_conf();
290 setup_clocks_for_console(); 298 setup_clocks_for_console();
291 uart_soft_reset(); 299 uart_soft_reset();
292 #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT) 300 #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
301 /* TODO: This does not work, gd is not available yet */
293 gd->baudrate = CONFIG_BAUDRATE; 302 gd->baudrate = CONFIG_BAUDRATE;
294 serial_init(); 303 serial_init();
295 gd->have_console = 1; 304 gd->have_console = 1;
296 #endif 305 #endif
297 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 306 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
298 /* Enable RTC32K clock */ 307 /* Enable RTC32K clock */
299 rtc32k_enable(); 308 rtc32k_enable();
300 #endif
301 #ifdef CONFIG_SPL_BUILD
302 board_early_init_f();
303 sdram_init();
arch/arm/cpu/armv7/omap-common/hwinit-common.c
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * 2 *
3 * Common functions for OMAP4/5 based boards 3 * Common functions for OMAP4/5 based boards
4 * 4 *
5 * (C) Copyright 2010 5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com> 6 * Texas Instruments, <www.ti.com>
7 * 7 *
8 * Author : 8 * Author :
9 * Aneesh V <aneesh@ti.com> 9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com> 10 * Steve Sakoman <steve@sakoman.com>
11 * 11 *
12 * SPDX-License-Identifier: GPL-2.0+ 12 * SPDX-License-Identifier: GPL-2.0+
13 */ 13 */
14 #include <common.h> 14 #include <common.h>
15 #include <spl.h> 15 #include <spl.h>
16 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/sys_proto.h>
17 #include <linux/sizes.h> 17 #include <linux/sizes.h>
18 #include <asm/emif.h> 18 #include <asm/emif.h>
19 #include <asm/omap_common.h> 19 #include <asm/omap_common.h>
20 #include <linux/compiler.h> 20 #include <linux/compiler.h>
21 #include <asm/system.h> 21 #include <asm/system.h>
22 22
23 DECLARE_GLOBAL_DATA_PTR; 23 DECLARE_GLOBAL_DATA_PTR;
24 24
25 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) 25 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
26 { 26 {
27 int i; 27 int i;
28 struct pad_conf_entry *pad = (struct pad_conf_entry *) array; 28 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
29 29
30 for (i = 0; i < size; i++, pad++) 30 for (i = 0; i < size; i++, pad++)
31 writew(pad->val, base + pad->offset); 31 writew(pad->val, base + pad->offset);
32 } 32 }
33 33
34 static void set_mux_conf_regs(void) 34 static void set_mux_conf_regs(void)
35 { 35 {
36 switch (omap_hw_init_context()) { 36 switch (omap_hw_init_context()) {
37 case OMAP_INIT_CONTEXT_SPL: 37 case OMAP_INIT_CONTEXT_SPL:
38 set_muxconf_regs_essential(); 38 set_muxconf_regs_essential();
39 break; 39 break;
40 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: 40 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
41 break; 41 break;
42 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: 42 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
43 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: 43 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
44 set_muxconf_regs_essential(); 44 set_muxconf_regs_essential();
45 break; 45 break;
46 } 46 }
47 } 47 }
48 48
49 u32 cortex_rev(void) 49 u32 cortex_rev(void)
50 { 50 {
51 51
52 unsigned int rev; 52 unsigned int rev;
53 53
54 /* Read Main ID Register (MIDR) */ 54 /* Read Main ID Register (MIDR) */
55 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); 55 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
56 56
57 return rev; 57 return rev;
58 } 58 }
59 59
60 static void omap_rev_string(void) 60 static void omap_rev_string(void)
61 { 61 {
62 u32 omap_rev = omap_revision(); 62 u32 omap_rev = omap_revision();
63 u32 soc_variant = (omap_rev & 0xF0000000) >> 28; 63 u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
64 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; 64 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
65 u32 major_rev = (omap_rev & 0x00000F00) >> 8; 65 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
66 u32 minor_rev = (omap_rev & 0x000000F0) >> 4; 66 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
67 67
68 if (soc_variant) 68 if (soc_variant)
69 printf("OMAP"); 69 printf("OMAP");
70 else 70 else
71 printf("DRA"); 71 printf("DRA");
72 printf("%x ES%x.%x\n", omap_variant, major_rev, 72 printf("%x ES%x.%x\n", omap_variant, major_rev,
73 minor_rev); 73 minor_rev);
74 } 74 }
75 75
76 #ifdef CONFIG_SPL_BUILD 76 #ifdef CONFIG_SPL_BUILD
77 void spl_display_print(void) 77 void spl_display_print(void)
78 { 78 {
79 omap_rev_string(); 79 omap_rev_string();
80 } 80 }
81 #endif 81 #endif
82 82
83 void __weak srcomp_enable(void) 83 void __weak srcomp_enable(void)
84 { 84 {
85 } 85 }
86 86
87 #ifdef CONFIG_ARCH_CPU_INIT 87 #ifdef CONFIG_ARCH_CPU_INIT
88 /* 88 /*
89 * SOC specific cpu init 89 * SOC specific cpu init
90 */ 90 */
91 int arch_cpu_init(void) 91 int arch_cpu_init(void)
92 { 92 {
93 save_omap_boot_params(); 93 save_omap_boot_params();
94 return 0; 94 return 0;
95 } 95 }
96 #endif /* CONFIG_ARCH_CPU_INIT */ 96 #endif /* CONFIG_ARCH_CPU_INIT */
97 97
98 /* 98 /*
99 * Routine: s_init 99 * Routine: s_init
100 * Description: Does early system init of watchdog, muxing, andclocks 100 * Description: Does early system init of watchdog, muxing, andclocks
101 * Watchdog disable is done always. For the rest what gets done 101 * Watchdog disable is done always. For the rest what gets done
102 * depends on the boot mode in which this function is executed 102 * depends on the boot mode in which this function is executed
103 * 1. s_init of SPL running from SRAM 103 * 1. s_init of SPL running from SRAM
104 * 2. s_init of U-Boot running from FLASH 104 * 2. s_init of U-Boot running from FLASH
105 * 3. s_init of U-Boot loaded to SDRAM by SPL 105 * 3. s_init of U-Boot loaded to SDRAM by SPL
106 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the 106 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
107 * Configuration Header feature 107 * Configuration Header feature
108 * Please have a look at the respective functions to see what gets 108 * Please have a look at the respective functions to see what gets
109 * done in each of these cases 109 * done in each of these cases
110 * This function is called with SRAM stack. 110 * This function is called with SRAM stack.
111 */ 111 */
112 void s_init(void) 112 void s_init(void)
113 { 113 {
114 init_omap_revision(); 114 init_omap_revision();
115 hw_data_init(); 115 hw_data_init();
116 116
117 #ifdef CONFIG_SPL_BUILD 117 #ifdef CONFIG_SPL_BUILD
118 if (warm_reset() && 118 if (warm_reset() &&
119 (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0))) 119 (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
120 force_emif_self_refresh(); 120 force_emif_self_refresh();
121 #endif 121 #endif
122 watchdog_init(); 122 watchdog_init();
123 set_mux_conf_regs(); 123 set_mux_conf_regs();
124 #ifdef CONFIG_SPL_BUILD 124 #ifdef CONFIG_SPL_BUILD
125 srcomp_enable(); 125 srcomp_enable();
126 setup_clocks_for_console(); 126 setup_clocks_for_console();
127 127
128 do_io_settings(); 128 do_io_settings();
129 #endif 129 #endif
130 prcm_init(); 130 prcm_init();
131 }
132
131 #ifdef CONFIG_SPL_BUILD 133 #ifdef CONFIG_SPL_BUILD
134 void board_init_f(ulong dummy)
135 {
132 #ifdef CONFIG_BOARD_EARLY_INIT_F 136 #ifdef CONFIG_BOARD_EARLY_INIT_F
133 board_early_init_f(); 137 board_early_init_f();
134 #endif 138 #endif
135 /* For regular u-boot sdram_init() is called from dram_init() */ 139 /* For regular u-boot sdram_init() is called from dram_init() */
136 sdram_init(); 140 sdram_init();
137 #endif
138 } 141 }
142 #endif
139 143
140 /* 144 /*
141 * Routine: wait_for_command_complete 145 * Routine: wait_for_command_complete
142 * Description: Wait for posting to finish on watchdog 146 * Description: Wait for posting to finish on watchdog
143 */ 147 */
144 void wait_for_command_complete(struct watchdog *wd_base) 148 void wait_for_command_complete(struct watchdog *wd_base)
145 { 149 {
146 int pending = 1; 150 int pending = 1;
147 do { 151 do {
148 pending = readl(&wd_base->wwps); 152 pending = readl(&wd_base->wwps);
149 } while (pending); 153 } while (pending);
150 } 154 }
151 155
152 /* 156 /*
153 * Routine: watchdog_init 157 * Routine: watchdog_init
154 * Description: Shut down watch dogs 158 * Description: Shut down watch dogs
155 */ 159 */
156 void watchdog_init(void) 160 void watchdog_init(void)
157 { 161 {
158 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; 162 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
159 163
160 writel(WD_UNLOCK1, &wd2_base->wspr); 164 writel(WD_UNLOCK1, &wd2_base->wspr);
161 wait_for_command_complete(wd2_base); 165 wait_for_command_complete(wd2_base);
162 writel(WD_UNLOCK2, &wd2_base->wspr); 166 writel(WD_UNLOCK2, &wd2_base->wspr);
163 } 167 }
164 168
165 169
166 /* 170 /*
167 * This function finds the SDRAM size available in the system 171 * This function finds the SDRAM size available in the system
168 * based on DMM section configurations 172 * based on DMM section configurations
169 * This is needed because the size of memory installed may be 173 * This is needed because the size of memory installed may be
170 * different on different versions of the board 174 * different on different versions of the board
171 */ 175 */
172 u32 omap_sdram_size(void) 176 u32 omap_sdram_size(void)
173 { 177 {
174 u32 section, i, valid; 178 u32 section, i, valid;
175 u64 sdram_start = 0, sdram_end = 0, addr, 179 u64 sdram_start = 0, sdram_end = 0, addr,
176 size, total_size = 0, trap_size = 0, trap_start = 0; 180 size, total_size = 0, trap_size = 0, trap_start = 0;
177 181
178 for (i = 0; i < 4; i++) { 182 for (i = 0; i < 4; i++) {
179 section = __raw_readl(DMM_BASE + i*4); 183 section = __raw_readl(DMM_BASE + i*4);
180 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> 184 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
181 (EMIF_SDRC_ADDRSPC_SHIFT); 185 (EMIF_SDRC_ADDRSPC_SHIFT);
182 addr = section & EMIF_SYS_ADDR_MASK; 186 addr = section & EMIF_SYS_ADDR_MASK;
183 187
184 /* See if the address is valid */ 188 /* See if the address is valid */
185 if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && 189 if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
186 (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { 190 (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
187 size = ((section & EMIF_SYS_SIZE_MASK) >> 191 size = ((section & EMIF_SYS_SIZE_MASK) >>
188 EMIF_SYS_SIZE_SHIFT); 192 EMIF_SYS_SIZE_SHIFT);
189 size = 1 << size; 193 size = 1 << size;
190 size *= SZ_16M; 194 size *= SZ_16M;
191 195
192 if (valid != DMM_SDRC_ADDR_SPC_INVALID) { 196 if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
193 if (!sdram_start || (addr < sdram_start)) 197 if (!sdram_start || (addr < sdram_start))
194 sdram_start = addr; 198 sdram_start = addr;
195 if (!sdram_end || ((addr + size) > sdram_end)) 199 if (!sdram_end || ((addr + size) > sdram_end))
196 sdram_end = addr + size; 200 sdram_end = addr + size;
197 } else { 201 } else {
198 trap_size = size; 202 trap_size = size;
199 trap_start = addr; 203 trap_start = addr;
200 } 204 }
201 } 205 }
202 } 206 }
203 207
204 if ((trap_start >= sdram_start) && (trap_start < sdram_end)) 208 if ((trap_start >= sdram_start) && (trap_start < sdram_end))
205 total_size = (sdram_end - sdram_start) - (trap_size); 209 total_size = (sdram_end - sdram_start) - (trap_size);
206 else 210 else
207 total_size = sdram_end - sdram_start; 211 total_size = sdram_end - sdram_start;
208 212
209 return total_size; 213 return total_size;
210 } 214 }
211 215
212 216
213 /* 217 /*
214 * Routine: dram_init 218 * Routine: dram_init
215 * Description: sets uboots idea of sdram size 219 * Description: sets uboots idea of sdram size
216 */ 220 */
217 int dram_init(void) 221 int dram_init(void)
218 { 222 {
219 sdram_init(); 223 sdram_init();
220 gd->ram_size = omap_sdram_size(); 224 gd->ram_size = omap_sdram_size();
221 return 0; 225 return 0;
222 } 226 }
223 227
224 /* 228 /*
225 * Print board information 229 * Print board information
226 */ 230 */
227 int checkboard(void) 231 int checkboard(void)
228 { 232 {
229 puts(sysinfo.board_string); 233 puts(sysinfo.board_string);
230 return 0; 234 return 0;
231 } 235 }
232 236
233 /* 237 /*
234 * get_device_type(): tell if GP/HS/EMU/TST 238 * get_device_type(): tell if GP/HS/EMU/TST
235 */ 239 */
236 u32 get_device_type(void) 240 u32 get_device_type(void)
237 { 241 {
238 return (readl((*ctrl)->control_status) & 242 return (readl((*ctrl)->control_status) &
239 (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; 243 (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
240 } 244 }
241 245
242 #if defined(CONFIG_DISPLAY_CPUINFO) 246 #if defined(CONFIG_DISPLAY_CPUINFO)
243 /* 247 /*
244 * Print CPU information 248 * Print CPU information
245 */ 249 */
246 int print_cpuinfo(void) 250 int print_cpuinfo(void)
247 { 251 {
248 puts("CPU : "); 252 puts("CPU : ");
249 omap_rev_string(); 253 omap_rev_string();
250 254
251 return 0; 255 return 0;
252 } 256 }
253 #endif 257 #endif
arch/arm/cpu/armv7/omap3/board.c
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * 2 *
3 * Common board functions for OMAP3 based boards. 3 * Common board functions for OMAP3 based boards.
4 * 4 *
5 * (C) Copyright 2004-2008 5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com> 6 * Texas Instruments, <www.ti.com>
7 * 7 *
8 * Author : 8 * Author :
9 * Sunil Kumar <sunilsaini05@gmail.com> 9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com> 10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
11 * 11 *
12 * Derived from Beagle Board and 3430 SDP code by 12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com> 13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com> 14 * Syed Mohammed Khasim <khasim@ti.com>
15 * 15 *
16 * 16 *
17 * SPDX-License-Identifier: GPL-2.0+ 17 * SPDX-License-Identifier: GPL-2.0+
18 */ 18 */
19 #include <common.h> 19 #include <common.h>
20 #include <dm.h> 20 #include <dm.h>
21 #include <mmc.h> 21 #include <mmc.h>
22 #include <spl.h> 22 #include <spl.h>
23 #include <asm/io.h> 23 #include <asm/io.h>
24 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mem.h> 25 #include <asm/arch/mem.h>
26 #include <asm/cache.h> 26 #include <asm/cache.h>
27 #include <asm/armv7.h> 27 #include <asm/armv7.h>
28 #include <asm/gpio.h> 28 #include <asm/gpio.h>
29 #include <asm/omap_common.h> 29 #include <asm/omap_common.h>
30 #include <asm/arch/mmc_host_def.h> 30 #include <asm/arch/mmc_host_def.h>
31 #include <i2c.h> 31 #include <i2c.h>
32 #include <linux/compiler.h> 32 #include <linux/compiler.h>
33 33
34 DECLARE_GLOBAL_DATA_PTR; 34 DECLARE_GLOBAL_DATA_PTR;
35 35
36 /* Declarations */ 36 /* Declarations */
37 extern omap3_sysinfo sysinfo; 37 extern omap3_sysinfo sysinfo;
38 static void omap3_setup_aux_cr(void); 38 static void omap3_setup_aux_cr(void);
39 #ifndef CONFIG_SYS_L2CACHE_OFF 39 #ifndef CONFIG_SYS_L2CACHE_OFF
40 static void omap3_invalidate_l2_cache_secure(void); 40 static void omap3_invalidate_l2_cache_secure(void);
41 #endif 41 #endif
42 42
43 #ifdef CONFIG_DM_GPIO 43 #ifdef CONFIG_DM_GPIO
44 static const struct omap_gpio_platdata omap34xx_gpio[] = { 44 static const struct omap_gpio_platdata omap34xx_gpio[] = {
45 { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, 45 { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
46 { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, 46 { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
47 { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, 47 { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
48 { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, 48 { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
49 { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, 49 { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
50 { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, 50 { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
51 }; 51 };
52 52
53 U_BOOT_DEVICES(am33xx_gpios) = { 53 U_BOOT_DEVICES(am33xx_gpios) = {
54 { "gpio_omap", &omap34xx_gpio[0] }, 54 { "gpio_omap", &omap34xx_gpio[0] },
55 { "gpio_omap", &omap34xx_gpio[1] }, 55 { "gpio_omap", &omap34xx_gpio[1] },
56 { "gpio_omap", &omap34xx_gpio[2] }, 56 { "gpio_omap", &omap34xx_gpio[2] },
57 { "gpio_omap", &omap34xx_gpio[3] }, 57 { "gpio_omap", &omap34xx_gpio[3] },
58 { "gpio_omap", &omap34xx_gpio[4] }, 58 { "gpio_omap", &omap34xx_gpio[4] },
59 { "gpio_omap", &omap34xx_gpio[5] }, 59 { "gpio_omap", &omap34xx_gpio[5] },
60 }; 60 };
61 61
62 #else 62 #else
63 63
64 static const struct gpio_bank gpio_bank_34xx[6] = { 64 static const struct gpio_bank gpio_bank_34xx[6] = {
65 { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, 65 { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
66 { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, 66 { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
67 { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, 67 { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
68 { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, 68 { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
69 { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, 69 { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
70 { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, 70 { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
71 }; 71 };
72 72
73 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; 73 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
74 74
75 #endif 75 #endif
76 76
77 #ifdef CONFIG_SPL_BUILD 77 #ifdef CONFIG_SPL_BUILD
78 /* 78 /*
79 * We use static variables because global data is not ready yet. 79 * We use static variables because global data is not ready yet.
80 * Initialized data is available in SPL right from the beginning. 80 * Initialized data is available in SPL right from the beginning.
81 * We would not typically need to save these parameters in regular 81 * We would not typically need to save these parameters in regular
82 * U-Boot. This is needed only in SPL at the moment. 82 * U-Boot. This is needed only in SPL at the moment.
83 */ 83 */
84 u32 omap3_boot_device = BOOT_DEVICE_NAND; 84 u32 omap3_boot_device = BOOT_DEVICE_NAND;
85 85
86 /* auto boot mode detection is not possible for OMAP3 - hard code */ 86 /* auto boot mode detection is not possible for OMAP3 - hard code */
87 u32 spl_boot_mode(void) 87 u32 spl_boot_mode(void)
88 { 88 {
89 switch (spl_boot_device()) { 89 switch (spl_boot_device()) {
90 case BOOT_DEVICE_MMC2: 90 case BOOT_DEVICE_MMC2:
91 return MMCSD_MODE_RAW; 91 return MMCSD_MODE_RAW;
92 case BOOT_DEVICE_MMC1: 92 case BOOT_DEVICE_MMC1:
93 return MMCSD_MODE_FS; 93 return MMCSD_MODE_FS;
94 break; 94 break;
95 default: 95 default:
96 puts("spl: ERROR: unknown device - can't select boot mode\n"); 96 puts("spl: ERROR: unknown device - can't select boot mode\n");
97 hang(); 97 hang();
98 } 98 }
99 } 99 }
100 100
101 u32 spl_boot_device(void) 101 u32 spl_boot_device(void)
102 { 102 {
103 return omap3_boot_device; 103 return omap3_boot_device;
104 } 104 }
105 105
106 int board_mmc_init(bd_t *bis) 106 int board_mmc_init(bd_t *bis)
107 { 107 {
108 switch (spl_boot_device()) { 108 switch (spl_boot_device()) {
109 case BOOT_DEVICE_MMC1: 109 case BOOT_DEVICE_MMC1:
110 omap_mmc_init(0, 0, 0, -1, -1); 110 omap_mmc_init(0, 0, 0, -1, -1);
111 break; 111 break;
112 case BOOT_DEVICE_MMC2: 112 case BOOT_DEVICE_MMC2:
113 case BOOT_DEVICE_MMC2_2: 113 case BOOT_DEVICE_MMC2_2:
114 omap_mmc_init(1, 0, 0, -1, -1); 114 omap_mmc_init(1, 0, 0, -1, -1);
115 break; 115 break;
116 } 116 }
117 return 0; 117 return 0;
118 } 118 }
119 119
120 void spl_board_init(void) 120 void spl_board_init(void)
121 { 121 {
122 preloader_console_init(); 122 preloader_console_init();
123 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) 123 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
124 gpmc_init(); 124 gpmc_init();
125 #endif 125 #endif
126 #ifdef CONFIG_SPL_I2C_SUPPORT 126 #ifdef CONFIG_SPL_I2C_SUPPORT
127 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 127 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
128 #endif 128 #endif
129 } 129 }
130 #endif /* CONFIG_SPL_BUILD */ 130 #endif /* CONFIG_SPL_BUILD */
131 131
132 132
133 /****************************************************************************** 133 /******************************************************************************
134 * Routine: secure_unlock 134 * Routine: secure_unlock
135 * Description: Setup security registers for access 135 * Description: Setup security registers for access
136 * (GP Device only) 136 * (GP Device only)
137 *****************************************************************************/ 137 *****************************************************************************/
138 void secure_unlock_mem(void) 138 void secure_unlock_mem(void)
139 { 139 {
140 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM; 140 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
141 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM; 141 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
142 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM; 142 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
143 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM; 143 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
144 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE; 144 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
145 145
146 /* Protection Module Register Target APE (PM_RT) */ 146 /* Protection Module Register Target APE (PM_RT) */
147 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1); 147 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
148 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0); 148 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
149 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0); 149 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
150 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1); 150 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
151 151
152 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0); 152 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
153 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0); 153 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
154 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0); 154 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
155 155
156 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0); 156 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
157 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0); 157 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
158 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0); 158 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
159 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2); 159 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
160 160
161 /* IVA Changes */ 161 /* IVA Changes */
162 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0); 162 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
163 writel(UNLOCK_3, &pm_iva2_base->read_permission_0); 163 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
164 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0); 164 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
165 165
166 /* SDRC region 0 public */ 166 /* SDRC region 0 public */
167 writel(UNLOCK_1, &sms_base->rg_att0); 167 writel(UNLOCK_1, &sms_base->rg_att0);
168 } 168 }
169 169
170 /****************************************************************************** 170 /******************************************************************************
171 * Routine: secureworld_exit() 171 * Routine: secureworld_exit()
172 * Description: If chip is EMU and boot type is external 172 * Description: If chip is EMU and boot type is external
173 * configure secure registers and exit secure world 173 * configure secure registers and exit secure world
174 * general use. 174 * general use.
175 *****************************************************************************/ 175 *****************************************************************************/
176 void secureworld_exit(void) 176 void secureworld_exit(void)
177 { 177 {
178 unsigned long i; 178 unsigned long i;
179 179
180 /* configure non-secure access control register */ 180 /* configure non-secure access control register */
181 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i)); 181 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
182 /* enabling co-processor CP10 and CP11 accesses in NS world */ 182 /* enabling co-processor CP10 and CP11 accesses in NS world */
183 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); 183 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
184 /* 184 /*
185 * allow allocation of locked TLBs and L2 lines in NS world 185 * allow allocation of locked TLBs and L2 lines in NS world
186 * allow use of PLE registers in NS world also 186 * allow use of PLE registers in NS world also
187 */ 187 */
188 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); 188 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
189 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i)); 189 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
190 190
191 /* Enable ASA in ACR register */ 191 /* Enable ASA in ACR register */
192 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); 192 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
193 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i)); 193 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
194 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); 194 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
195 195
196 /* Exiting secure world */ 196 /* Exiting secure world */
197 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i)); 197 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
198 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); 198 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
199 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i)); 199 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
200 } 200 }
201 201
202 /****************************************************************************** 202 /******************************************************************************
203 * Routine: try_unlock_sram() 203 * Routine: try_unlock_sram()
204 * Description: If chip is GP/EMU(special) type, unlock the SRAM for 204 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
205 * general use. 205 * general use.
206 *****************************************************************************/ 206 *****************************************************************************/
207 void try_unlock_memory(void) 207 void try_unlock_memory(void)
208 { 208 {
209 int mode; 209 int mode;
210 int in_sdram = is_running_in_sdram(); 210 int in_sdram = is_running_in_sdram();
211 211
212 /* 212 /*
213 * if GP device unlock device SRAM for general use 213 * if GP device unlock device SRAM for general use
214 * secure code breaks for Secure/Emulation device - HS/E/T 214 * secure code breaks for Secure/Emulation device - HS/E/T
215 */ 215 */
216 mode = get_device_type(); 216 mode = get_device_type();
217 if (mode == GP_DEVICE) 217 if (mode == GP_DEVICE)
218 secure_unlock_mem(); 218 secure_unlock_mem();
219 219
220 /* 220 /*
221 * If device is EMU and boot is XIP external booting 221 * If device is EMU and boot is XIP external booting
222 * Unlock firewalls and disable L2 and put chip 222 * Unlock firewalls and disable L2 and put chip
223 * out of secure world 223 * out of secure world
224 * 224 *
225 * Assuming memories are unlocked by the demon who put us in SDRAM 225 * Assuming memories are unlocked by the demon who put us in SDRAM
226 */ 226 */
227 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) 227 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
228 && (!in_sdram)) { 228 && (!in_sdram)) {
229 secure_unlock_mem(); 229 secure_unlock_mem();
230 secureworld_exit(); 230 secureworld_exit();
231 } 231 }
232 232
233 return; 233 return;
234 } 234 }
235 235
236 /****************************************************************************** 236 /******************************************************************************
237 * Routine: s_init 237 * Routine: s_init
238 * Description: Does early system init of muxing and clocks. 238 * Description: Does early system init of muxing and clocks.
239 * - Called path is with SRAM stack. 239 * - Called path is with SRAM stack.
240 *****************************************************************************/ 240 *****************************************************************************/
241 void s_init(void) 241 void s_init(void)
242 { 242 {
243 int in_sdram = is_running_in_sdram();
244
245 watchdog_init(); 243 watchdog_init();
246 244
247 try_unlock_memory(); 245 try_unlock_memory();
248 246
249 /* Errata workarounds */ 247 /* Errata workarounds */
250 omap3_setup_aux_cr(); 248 omap3_setup_aux_cr();
251 249
252 #ifndef CONFIG_SYS_L2CACHE_OFF 250 #ifndef CONFIG_SYS_L2CACHE_OFF
253 /* Invalidate L2-cache from secure mode */ 251 /* Invalidate L2-cache from secure mode */
254 omap3_invalidate_l2_cache_secure(); 252 omap3_invalidate_l2_cache_secure();
255 #endif 253 #endif
256 254
257 set_muxconf_regs(); 255 set_muxconf_regs();
258 sdelay(100); 256 sdelay(100);
259 257
260 prcm_init(); 258 prcm_init();
261 259
262 per_clocks_enable(); 260 per_clocks_enable();
263 261
264 #ifdef CONFIG_USB_EHCI_OMAP 262 #ifdef CONFIG_USB_EHCI_OMAP
265 ehci_clocks_enable(); 263 ehci_clocks_enable();
266 #endif 264 #endif
265 }
267 266
268 if (!in_sdram) 267 #ifdef CONFIG_SPL_BUILD
269 mem_init(); 268 void board_init_f(ulong dummy)
269 {
270 mem_init();
270 } 271 }
272 #endif
271 273
272 /* 274 /*
273 * Routine: misc_init_r 275 * Routine: misc_init_r
274 * Description: A basic misc_init_r that just displays the die ID 276 * Description: A basic misc_init_r that just displays the die ID
275 */ 277 */
276 int __weak misc_init_r(void) 278 int __weak misc_init_r(void)
277 { 279 {
278 dieid_num_r(); 280 dieid_num_r();
279 281
280 return 0; 282 return 0;
281 } 283 }
282 284
283 /****************************************************************************** 285 /******************************************************************************
284 * Routine: wait_for_command_complete 286 * Routine: wait_for_command_complete
285 * Description: Wait for posting to finish on watchdog 287 * Description: Wait for posting to finish on watchdog
286 *****************************************************************************/ 288 *****************************************************************************/
287 static void wait_for_command_complete(struct watchdog *wd_base) 289 static void wait_for_command_complete(struct watchdog *wd_base)
288 { 290 {
289 int pending = 1; 291 int pending = 1;
290 do { 292 do {
291 pending = readl(&wd_base->wwps); 293 pending = readl(&wd_base->wwps);
292 } while (pending); 294 } while (pending);
293 } 295 }
294 296
295 /****************************************************************************** 297 /******************************************************************************
296 * Routine: watchdog_init 298 * Routine: watchdog_init
297 * Description: Shut down watch dogs 299 * Description: Shut down watch dogs
298 *****************************************************************************/ 300 *****************************************************************************/
299 void watchdog_init(void) 301 void watchdog_init(void)
300 { 302 {
301 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE; 303 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
302 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 304 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
303 305
304 /* 306 /*
305 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is 307 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
306 * either taken care of by ROM (HS/EMU) or not accessible (GP). 308 * either taken care of by ROM (HS/EMU) or not accessible (GP).
307 * We need to take care of WD2-MPU or take a PRCM reset. WD3 309 * We need to take care of WD2-MPU or take a PRCM reset. WD3
308 * should not be running and does not generate a PRCM reset. 310 * should not be running and does not generate a PRCM reset.
309 */ 311 */
310 312
311 setbits_le32(&prcm_base->fclken_wkup, 0x20); 313 setbits_le32(&prcm_base->fclken_wkup, 0x20);
312 setbits_le32(&prcm_base->iclken_wkup, 0x20); 314 setbits_le32(&prcm_base->iclken_wkup, 0x20);
313 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); 315 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
314 316
315 writel(WD_UNLOCK1, &wd2_base->wspr); 317 writel(WD_UNLOCK1, &wd2_base->wspr);
316 wait_for_command_complete(wd2_base); 318 wait_for_command_complete(wd2_base);
317 writel(WD_UNLOCK2, &wd2_base->wspr); 319 writel(WD_UNLOCK2, &wd2_base->wspr);
318 } 320 }
319 321
320 /****************************************************************************** 322 /******************************************************************************
321 * Dummy function to handle errors for EABI incompatibility 323 * Dummy function to handle errors for EABI incompatibility
322 *****************************************************************************/ 324 *****************************************************************************/
323 void abort(void) 325 void abort(void)
324 { 326 {
325 } 327 }
326 328
327 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) 329 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
328 /****************************************************************************** 330 /******************************************************************************
329 * OMAP3 specific command to switch between NAND HW and SW ecc 331 * OMAP3 specific command to switch between NAND HW and SW ecc
330 *****************************************************************************/ 332 *****************************************************************************/
331 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 333 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
332 { 334 {
333 if (argc < 2 || argc > 3) 335 if (argc < 2 || argc > 3)
334 goto usage; 336 goto usage;
335 337
336 if (strncmp(argv[1], "hw", 2) == 0) { 338 if (strncmp(argv[1], "hw", 2) == 0) {
337 if (argc == 2) { 339 if (argc == 2) {
338 omap_nand_switch_ecc(1, 1); 340 omap_nand_switch_ecc(1, 1);
339 } else { 341 } else {
340 if (strncmp(argv[2], "hamming", 7) == 0) 342 if (strncmp(argv[2], "hamming", 7) == 0)
341 omap_nand_switch_ecc(1, 1); 343 omap_nand_switch_ecc(1, 1);
342 else if (strncmp(argv[2], "bch8", 4) == 0) 344 else if (strncmp(argv[2], "bch8", 4) == 0)
343 omap_nand_switch_ecc(1, 8); 345 omap_nand_switch_ecc(1, 8);
344 else 346 else
345 goto usage; 347 goto usage;
346 } 348 }
347 } else if (strncmp(argv[1], "sw", 2) == 0) { 349 } else if (strncmp(argv[1], "sw", 2) == 0) {
348 omap_nand_switch_ecc(0, 0); 350 omap_nand_switch_ecc(0, 0);
349 } else { 351 } else {
350 goto usage; 352 goto usage;
351 } 353 }
352 354
353 return 0; 355 return 0;
354 356
355 usage: 357 usage:
356 printf ("Usage: nandecc %s\n", cmdtp->usage); 358 printf ("Usage: nandecc %s\n", cmdtp->usage);
357 return 1; 359 return 1;
358 } 360 }
359 361
360 U_BOOT_CMD( 362 U_BOOT_CMD(
361 nandecc, 3, 1, do_switch_ecc, 363 nandecc, 3, 1, do_switch_ecc,
362 "switch OMAP3 NAND ECC calculation algorithm", 364 "switch OMAP3 NAND ECC calculation algorithm",
363 "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and" 365 "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
364 " 8-bit BCH\n" 366 " 8-bit BCH\n"
365 " ecc calculation (second parameter may" 367 " ecc calculation (second parameter may"
366 " be omitted).\n" 368 " be omitted).\n"
367 "nandecc sw - Switch to NAND software ecc algorithm." 369 "nandecc sw - Switch to NAND software ecc algorithm."
368 ); 370 );
369 371
370 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ 372 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
371 373
372 #ifdef CONFIG_DISPLAY_BOARDINFO 374 #ifdef CONFIG_DISPLAY_BOARDINFO
373 /** 375 /**
374 * Print board information 376 * Print board information
375 */ 377 */
376 int checkboard (void) 378 int checkboard (void)
377 { 379 {
378 char *mem_s ; 380 char *mem_s ;
379 381
380 if (is_mem_sdr()) 382 if (is_mem_sdr())
381 mem_s = "mSDR"; 383 mem_s = "mSDR";
382 else 384 else
383 mem_s = "LPDDR"; 385 mem_s = "LPDDR";
384 386
385 printf("%s + %s/%s\n", sysinfo.board_string, mem_s, 387 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
386 sysinfo.nand_string); 388 sysinfo.nand_string);
387 389
388 return 0; 390 return 0;
389 } 391 }
390 #endif /* CONFIG_DISPLAY_BOARDINFO */ 392 #endif /* CONFIG_DISPLAY_BOARDINFO */
391 393
392 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) 394 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
393 { 395 {
394 u32 i, num_params = *parameters; 396 u32 i, num_params = *parameters;
395 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA; 397 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
396 398
397 /* 399 /*
398 * copy the parameters to an un-cached area to avoid coherency 400 * copy the parameters to an un-cached area to avoid coherency
399 * issues 401 * issues
400 */ 402 */
401 for (i = 0; i < num_params; i++) { 403 for (i = 0; i < num_params; i++) {
402 __raw_writel(*parameters, sram_scratch_space); 404 __raw_writel(*parameters, sram_scratch_space);
403 parameters++; 405 parameters++;
404 sram_scratch_space++; 406 sram_scratch_space++;
405 } 407 }
406 408
407 /* Now make the PPA call */ 409 /* Now make the PPA call */
408 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); 410 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
409 } 411 }
410 412
411 static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) 413 static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
412 { 414 {
413 u32 acr; 415 u32 acr;
414 416
415 /* Read ACR */ 417 /* Read ACR */
416 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); 418 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
417 acr &= ~clear_bits; 419 acr &= ~clear_bits;
418 acr |= set_bits; 420 acr |= set_bits;
419 421
420 if (get_device_type() == GP_DEVICE) { 422 if (get_device_type() == GP_DEVICE) {
421 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR, 423 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
422 acr); 424 acr);
423 } else { 425 } else {
424 struct emu_hal_params emu_romcode_params; 426 struct emu_hal_params emu_romcode_params;
425 emu_romcode_params.num_params = 1; 427 emu_romcode_params.num_params = 1;
426 emu_romcode_params.param1 = acr; 428 emu_romcode_params.param1 = acr;
427 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, 429 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
428 (u32 *)&emu_romcode_params); 430 (u32 *)&emu_romcode_params);
429 } 431 }
430 } 432 }
431 433
432 static void omap3_setup_aux_cr(void) 434 static void omap3_setup_aux_cr(void)
433 { 435 {
434 /* Workaround for Cortex-A8 errata: #454179 #430973 436 /* Workaround for Cortex-A8 errata: #454179 #430973
435 * Set "IBE" bit 437 * Set "IBE" bit
436 * Set "Disable Branch Size Mispredicts" bit 438 * Set "Disable Branch Size Mispredicts" bit
437 * Workaround for erratum #621766 439 * Workaround for erratum #621766
438 * Enable L1NEON bit 440 * Enable L1NEON bit
439 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 441 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
440 */ 442 */
441 omap3_update_aux_cr_secure(0xE0, 0); 443 omap3_update_aux_cr_secure(0xE0, 0);
442 } 444 }
443 445
444 #ifndef CONFIG_SYS_L2CACHE_OFF 446 #ifndef CONFIG_SYS_L2CACHE_OFF
445 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) 447 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
446 { 448 {
447 u32 acr; 449 u32 acr;
448 450
449 /* Read ACR */ 451 /* Read ACR */
450 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); 452 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
451 acr &= ~clear_bits; 453 acr &= ~clear_bits;
452 acr |= set_bits; 454 acr |= set_bits;
453 455
454 /* Write ACR - affects non-secure banked bits */ 456 /* Write ACR - affects non-secure banked bits */
455 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); 457 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
456 } 458 }
457 459
458 /* Invalidate the entire L2 cache from secure mode */ 460 /* Invalidate the entire L2 cache from secure mode */
459 static void omap3_invalidate_l2_cache_secure(void) 461 static void omap3_invalidate_l2_cache_secure(void)
460 { 462 {
461 if (get_device_type() == GP_DEVICE) { 463 if (get_device_type() == GP_DEVICE) {
462 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, 464 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
463 0); 465 0);
464 } else { 466 } else {
465 struct emu_hal_params emu_romcode_params; 467 struct emu_hal_params emu_romcode_params;
466 emu_romcode_params.num_params = 1; 468 emu_romcode_params.num_params = 1;
467 emu_romcode_params.param1 = 0; 469 emu_romcode_params.param1 = 0;
468 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL, 470 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
469 (u32 *)&emu_romcode_params); 471 (u32 *)&emu_romcode_params);
470 } 472 }
471 } 473 }
472 474
473 void v7_outer_cache_enable(void) 475 void v7_outer_cache_enable(void)
474 { 476 {
475 /* Set L2EN */ 477 /* Set L2EN */
476 omap3_update_aux_cr_secure(0x2, 0); 478 omap3_update_aux_cr_secure(0x2, 0);
477 479
478 /* 480 /*
479 * On some revisions L2EN bit is banked on some revisions it's not 481 * On some revisions L2EN bit is banked on some revisions it's not
480 * No harm in setting both banked bits(in fact this is required 482 * No harm in setting both banked bits(in fact this is required
481 * by an erratum) 483 * by an erratum)
482 */ 484 */
483 omap3_update_aux_cr(0x2, 0); 485 omap3_update_aux_cr(0x2, 0);
484 } 486 }
485 487
486 void omap3_outer_cache_disable(void) 488 void omap3_outer_cache_disable(void)
487 { 489 {
488 /* Clear L2EN */ 490 /* Clear L2EN */
489 omap3_update_aux_cr_secure(0, 0x2); 491 omap3_update_aux_cr_secure(0, 0x2);
490 492
491 /* 493 /*
492 * On some revisions L2EN bit is banked on some revisions it's not 494 * On some revisions L2EN bit is banked on some revisions it's not
493 * No harm in clearing both banked bits(in fact this is required 495 * No harm in clearing both banked bits(in fact this is required
494 * by an erratum) 496 * by an erratum)
495 */ 497 */
496 omap3_update_aux_cr(0, 0x2); 498 omap3_update_aux_cr(0, 0x2);
497 } 499 }
configs/am335x_boneblack_defconfig
Diff comments   View file @ 7ae8350
1 CONFIG_SPL=y 1 CONFIG_SPL=y
2 CONFIG_SPL_STACK_R=y
3 CONFIG_SPL_STACK_R_ADDR=0x82000000
2 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" 4 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
3 +S:CONFIG_ARM=y 5 +S:CONFIG_ARM=y
4 +S:CONFIG_TARGET_AM335X_EVM=y 6 +S:CONFIG_TARGET_AM335X_EVM=y
5 7
configs/am335x_boneblack_vboot_defconfig
Diff comments   View file @ 7ae8350
1 CONFIG_SPL=y 1 CONFIG_SPL=y
2 CONFIG_SPL_STACK_R=y
3 CONFIG_SPL_STACK_R_ADDR=0x82000000
2 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT" 4 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
3 +S:CONFIG_ARM=y 5 +S:CONFIG_ARM=y
4 +S:CONFIG_TARGET_AM335X_EVM=y 6 +S:CONFIG_TARGET_AM335X_EVM=y
5 CONFIG_OF_CONTROL=y 7 CONFIG_OF_CONTROL=y
6 CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack" 8 CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
7 CONFIG_FIT=y 9 CONFIG_FIT=y
8 CONFIG_FIT_VERBOSE=y 10 CONFIG_FIT_VERBOSE=y
9 CONFIG_FIT_SIGNATURE=y 11 CONFIG_FIT_SIGNATURE=y
10 CONFIG_DM=y 12 CONFIG_DM=y
11 13
configs/am335x_evm_defconfig
Diff comments   View file @ 7ae8350
1 CONFIG_SPL=y 1 CONFIG_SPL=y
2 CONFIG_SPL_STACK_R=y
3 CONFIG_SPL_STACK_R_ADDR=0x82000000
2 CONFIG_SYS_EXTRA_OPTIONS="NAND" 4 CONFIG_SYS_EXTRA_OPTIONS="NAND"
3 CONFIG_CONS_INDEX=1 5 CONFIG_CONS_INDEX=1
4 +S:CONFIG_ARM=y 6 +S:CONFIG_ARM=y
5 +S:CONFIG_TARGET_AM335X_EVM=y 7 +S:CONFIG_TARGET_AM335X_EVM=y
6 8
configs/am335x_evm_nor_defconfig
Diff comments   View file @ 7ae8350
1 CONFIG_SPL=y 1 CONFIG_SPL=y
2 CONFIG_SPL_STACK_R=y
3 CONFIG_SPL_STACK_R_ADDR=0x82000000
2 CONFIG_SYS_EXTRA_OPTIONS="NAND" 4 CONFIG_SYS_EXTRA_OPTIONS="NAND"
3 CONFIG_CONS_INDEX=1 5 CONFIG_CONS_INDEX=1
4 +S:CONFIG_ARM=y 6 +S:CONFIG_ARM=y
5 +S:CONFIG_TARGET_AM335X_EVM=y 7 +S:CONFIG_TARGET_AM335X_EVM=y
6 CONFIG_NOR=y 8 CONFIG_NOR=y
7 9
configs/am335x_evm_spiboot_defconfig
Diff comments   View file @ 7ae8350
1 CONFIG_SPL=y 1 CONFIG_SPL=y
2 CONFIG_SPL_STACK_R=y
3 CONFIG_SPL_STACK_R_ADDR=0x82000000
2 CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT" 4 CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
3 CONFIG_CONS_INDEX=1 5 CONFIG_CONS_INDEX=1
4 +S:CONFIG_ARM=y 6 +S:CONFIG_ARM=y
5 +S:CONFIG_TARGET_AM335X_EVM=y 7 +S:CONFIG_TARGET_AM335X_EVM=y
6 8
configs/am335x_evm_usbspl_defconfig
Diff comments   View file @ 7ae8350
1 CONFIG_SPL=y 1 CONFIG_SPL=y
2 CONFIG_SPL_STACK_R=y
3 CONFIG_SPL_STACK_R_ADDR=0x82000000
2 CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
3 CONFIG_CONS_INDEX=1 5 CONFIG_CONS_INDEX=1
4 +S:CONFIG_ARM=y 6 +S:CONFIG_ARM=y
5 +S:CONFIG_TARGET_AM335X_EVM=y 7 +S:CONFIG_TARGET_AM335X_EVM=y
6 8
configs/am335x_igep0033_defconfig
Diff comments   View file @ 7ae8350
1 CONFIG_SPL=y 1 CONFIG_SPL=y
2 CONFIG_SPL_STACK_R=y
3 CONFIG_SPL_STACK_R_ADDR=0x82000000
2 +S:CONFIG_ARM=y 4 +S:CONFIG_ARM=y
3 +S:CONFIG_TARGET_AM335X_IGEP0033=y 5 +S:CONFIG_TARGET_AM335X_IGEP0033=y
4 CONFIG_SYS_MALLOC_F=y 6 CONFIG_SYS_MALLOC_F=y
5 CONFIG_SYS_MALLOC_F_LEN=0x400 7 CONFIG_SYS_MALLOC_F_LEN=0x400
6 8
include/configs/am3517_crane.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard.
3 * 3 *
4 * Author: Srinath.R <srinath@mistralsolutions.com> 4 * Author: Srinath.R <srinath@mistralsolutions.com>
5 * 5 *
6 * Based on include/configs/am3517evm.h 6 * Based on include/configs/am3517evm.h
7 * 7 *
8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd
9 * 9 *
10 * SPDX-License-Identifier: GPL-2.0+ 10 * SPDX-License-Identifier: GPL-2.0+
11 */ 11 */
12 12
13 #ifndef __CONFIG_H 13 #ifndef __CONFIG_H
14 #define __CONFIG_H 14 #define __CONFIG_H
15 15
16 /* 16 /*
17 * High Level Configuration Options 17 * High Level Configuration Options
18 */ 18 */
19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */
20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ 20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
21 #define CONFIG_OMAP_COMMON 21 #define CONFIG_OMAP_COMMON
22 22
23 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 23 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
24 24
25 #include <asm/arch/cpu.h> /* get chip and board defs */ 25 #include <asm/arch/cpu.h> /* get chip and board defs */
26 #include <asm/arch/omap3.h> 26 #include <asm/arch/omap3.h>
27 27
28 /* 28 /*
29 * Display CPU and Board information 29 * Display CPU and Board information
30 */ 30 */
31 #define CONFIG_DISPLAY_CPUINFO 1 31 #define CONFIG_DISPLAY_CPUINFO 1
32 #define CONFIG_DISPLAY_BOARDINFO 1 32 #define CONFIG_DISPLAY_BOARDINFO 1
33 33
34 /* Clock Defines */ 34 /* Clock Defines */
35 #define V_OSCK 26000000 /* Clock output from T2 */ 35 #define V_OSCK 26000000 /* Clock output from T2 */
36 #define V_SCLK (V_OSCK >> 1) 36 #define V_SCLK (V_OSCK >> 1)
37 37
38 #define CONFIG_MISC_INIT_R 38 #define CONFIG_MISC_INIT_R
39 39
40 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 40 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41 #define CONFIG_SETUP_MEMORY_TAGS 1 41 #define CONFIG_SETUP_MEMORY_TAGS 1
42 #define CONFIG_INITRD_TAG 1 42 #define CONFIG_INITRD_TAG 1
43 #define CONFIG_REVISION_TAG 1 43 #define CONFIG_REVISION_TAG 1
44 44
45 /* 45 /*
46 * Size of malloc() pool 46 * Size of malloc() pool
47 */ 47 */
48 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 48 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
50 /* initial data */ 50 /* initial data */
51 /* 51 /*
52 * DDR related 52 * DDR related
53 */ 53 */
54 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 54 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
55 55
56 /* 56 /*
57 * Hardware drivers 57 * Hardware drivers
58 */ 58 */
59 59
60 /* 60 /*
61 * NS16550 Configuration 61 * NS16550 Configuration
62 */ 62 */
63 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 63 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
64 64
65 #define CONFIG_SYS_NS16550 65 #define CONFIG_SYS_NS16550
66 #define CONFIG_SYS_NS16550_SERIAL 66 #define CONFIG_SYS_NS16550_SERIAL
67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
69 69
70 /* 70 /*
71 * select serial console configuration 71 * select serial console configuration
72 */ 72 */
73 #define CONFIG_CONS_INDEX 3 73 #define CONFIG_CONS_INDEX 3
74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
75 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 75 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
76 76
77 /* allow to overwrite serial and ethaddr */ 77 /* allow to overwrite serial and ethaddr */
78 #define CONFIG_ENV_OVERWRITE 78 #define CONFIG_ENV_OVERWRITE
79 #define CONFIG_BAUDRATE 115200 79 #define CONFIG_BAUDRATE 115200
80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
81 115200} 81 115200}
82 #define CONFIG_GENERIC_MMC 1 82 #define CONFIG_GENERIC_MMC 1
83 #define CONFIG_MMC 1 83 #define CONFIG_MMC 1
84 #define CONFIG_OMAP_HSMMC 1 84 #define CONFIG_OMAP_HSMMC 1
85 #define CONFIG_DOS_PARTITION 1 85 #define CONFIG_DOS_PARTITION 1
86 86
87 /* 87 /*
88 * USB configuration 88 * USB configuration
89 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 89 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
90 * Enable CONFIG_MUSB_UDC for Device functionalities. 90 * Enable CONFIG_MUSB_UDC for Device functionalities.
91 */ 91 */
92 #define CONFIG_USB_AM35X 1 92 #define CONFIG_USB_AM35X 1
93 #define CONFIG_MUSB_HCD 1 93 #define CONFIG_MUSB_HCD 1
94 94
95 #ifdef CONFIG_USB_AM35X 95 #ifdef CONFIG_USB_AM35X
96 96
97 #ifdef CONFIG_MUSB_HCD 97 #ifdef CONFIG_MUSB_HCD
98 #define CONFIG_CMD_USB 98 #define CONFIG_CMD_USB
99 99
100 #define CONFIG_USB_STORAGE 100 #define CONFIG_USB_STORAGE
101 #define CONGIG_CMD_STORAGE 101 #define CONGIG_CMD_STORAGE
102 #define CONFIG_CMD_FAT 102 #define CONFIG_CMD_FAT
103 103
104 #ifdef CONFIG_USB_KEYBOARD 104 #ifdef CONFIG_USB_KEYBOARD
105 #define CONFIG_SYS_USB_EVENT_POLL 105 #define CONFIG_SYS_USB_EVENT_POLL
106 #define CONFIG_PREBOOT "usb start" 106 #define CONFIG_PREBOOT "usb start"
107 #endif /* CONFIG_USB_KEYBOARD */ 107 #endif /* CONFIG_USB_KEYBOARD */
108 108
109 #endif /* CONFIG_MUSB_HCD */ 109 #endif /* CONFIG_MUSB_HCD */
110 110
111 #ifdef CONFIG_MUSB_UDC 111 #ifdef CONFIG_MUSB_UDC
112 /* USB device configuration */ 112 /* USB device configuration */
113 #define CONFIG_USB_DEVICE 1 113 #define CONFIG_USB_DEVICE 1
114 #define CONFIG_USB_TTY 1 114 #define CONFIG_USB_TTY 1
115 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 115 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
116 /* Change these to suit your needs */ 116 /* Change these to suit your needs */
117 #define CONFIG_USBD_VENDORID 0x0451 117 #define CONFIG_USBD_VENDORID 0x0451
118 #define CONFIG_USBD_PRODUCTID 0x5678 118 #define CONFIG_USBD_PRODUCTID 0x5678
119 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 119 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
120 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 120 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
121 #endif /* CONFIG_MUSB_UDC */ 121 #endif /* CONFIG_MUSB_UDC */
122 122
123 #endif /* CONFIG_USB_AM35X */ 123 #endif /* CONFIG_USB_AM35X */
124 124
125 /* commands to include */ 125 /* commands to include */
126 #include <config_cmd_default.h> 126 #include <config_cmd_default.h>
127 127
128 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 128 #define CONFIG_CMD_EXT2 /* EXT2 Support */
129 #define CONFIG_CMD_FAT /* FAT support */ 129 #define CONFIG_CMD_FAT /* FAT support */
130 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 130 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
131 131
132 #define CONFIG_CMD_I2C /* I2C serial bus support */ 132 #define CONFIG_CMD_I2C /* I2C serial bus support */
133 #define CONFIG_CMD_MMC /* MMC support */ 133 #define CONFIG_CMD_MMC /* MMC support */
134 #define CONFIG_CMD_NAND /* NAND support */ 134 #define CONFIG_CMD_NAND /* NAND support */
135 #define CONFIG_CMD_DHCP 135 #define CONFIG_CMD_DHCP
136 #undef CONFIG_CMD_PING 136 #undef CONFIG_CMD_PING
137 137
138 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 138 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
139 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 139 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
140 #undef CONFIG_CMD_IMI /* iminfo */ 140 #undef CONFIG_CMD_IMI /* iminfo */
141 #undef CONFIG_CMD_IMLS /* List all found images */ 141 #undef CONFIG_CMD_IMLS /* List all found images */
142 142
143 #define CONFIG_SYS_NO_FLASH 143 #define CONFIG_SYS_NO_FLASH
144 #define CONFIG_SYS_I2C 144 #define CONFIG_SYS_I2C
145 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 145 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
146 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 146 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
147 #define CONFIG_SYS_I2C_OMAP34XX 147 #define CONFIG_SYS_I2C_OMAP34XX
148 148
149 #undef CONFIG_CMD_NET 149 #undef CONFIG_CMD_NET
150 #undef CONFIG_CMD_NFS 150 #undef CONFIG_CMD_NFS
151 /* 151 /*
152 * Board NAND Info. 152 * Board NAND Info.
153 */ 153 */
154 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 154 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
155 /* to access nand */ 155 /* to access nand */
156 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 156 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
157 /* to access */ 157 /* to access */
158 /* nand at CS0 */ 158 /* nand at CS0 */
159 159
160 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 160 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
161 /* NAND devices */ 161 /* NAND devices */
162 162
163 #define CONFIG_JFFS2_NAND 163 #define CONFIG_JFFS2_NAND
164 /* nand device jffs2 lives on */ 164 /* nand device jffs2 lives on */
165 #define CONFIG_JFFS2_DEV "nand0" 165 #define CONFIG_JFFS2_DEV "nand0"
166 /* start of jffs2 partition */ 166 /* start of jffs2 partition */
167 #define CONFIG_JFFS2_PART_OFFSET 0x680000 167 #define CONFIG_JFFS2_PART_OFFSET 0x680000
168 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 168 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
169 169
170 /* Environment information */ 170 /* Environment information */
171 #define CONFIG_BOOTDELAY 10 171 #define CONFIG_BOOTDELAY 10
172 172
173 #define CONFIG_BOOTFILE "uImage" 173 #define CONFIG_BOOTFILE "uImage"
174 174
175 #define CONFIG_EXTRA_ENV_SETTINGS \ 175 #define CONFIG_EXTRA_ENV_SETTINGS \
176 "loadaddr=0x82000000\0" \ 176 "loadaddr=0x82000000\0" \
177 "console=ttyS2,115200n8\0" \ 177 "console=ttyS2,115200n8\0" \
178 "mmcdev=0\0" \ 178 "mmcdev=0\0" \
179 "mmcargs=setenv bootargs console=${console} " \ 179 "mmcargs=setenv bootargs console=${console} " \
180 "root=/dev/mmcblk0p2 rw " \ 180 "root=/dev/mmcblk0p2 rw " \
181 "rootfstype=ext3 rootwait\0" \ 181 "rootfstype=ext3 rootwait\0" \
182 "nandargs=setenv bootargs console=${console} " \ 182 "nandargs=setenv bootargs console=${console} " \
183 "root=/dev/mtdblock4 rw " \ 183 "root=/dev/mtdblock4 rw " \
184 "rootfstype=jffs2\0" \ 184 "rootfstype=jffs2\0" \
185 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 185 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
186 "bootscript=echo Running bootscript from mmc ...; " \ 186 "bootscript=echo Running bootscript from mmc ...; " \
187 "source ${loadaddr}\0" \ 187 "source ${loadaddr}\0" \
188 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 188 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
189 "mmcboot=echo Booting from mmc ...; " \ 189 "mmcboot=echo Booting from mmc ...; " \
190 "run mmcargs; " \ 190 "run mmcargs; " \
191 "bootm ${loadaddr}\0" \ 191 "bootm ${loadaddr}\0" \
192 "nandboot=echo Booting from nand ...; " \ 192 "nandboot=echo Booting from nand ...; " \
193 "run nandargs; " \ 193 "run nandargs; " \
194 "nand read ${loadaddr} 280000 400000; " \ 194 "nand read ${loadaddr} 280000 400000; " \
195 "bootm ${loadaddr}\0" \ 195 "bootm ${loadaddr}\0" \
196 196
197 #define CONFIG_BOOTCOMMAND \ 197 #define CONFIG_BOOTCOMMAND \
198 "mmc dev ${mmcdev}; if mmc rescan; then " \ 198 "mmc dev ${mmcdev}; if mmc rescan; then " \
199 "if run loadbootscript; then " \ 199 "if run loadbootscript; then " \
200 "run bootscript; " \ 200 "run bootscript; " \
201 "else " \ 201 "else " \
202 "if run loaduimage; then " \ 202 "if run loaduimage; then " \
203 "run mmcboot; " \ 203 "run mmcboot; " \
204 "else run nandboot; " \ 204 "else run nandboot; " \
205 "fi; " \ 205 "fi; " \
206 "fi; " \ 206 "fi; " \
207 "else run nandboot; fi" 207 "else run nandboot; fi"
208 208
209 #define CONFIG_AUTO_COMPLETE 1 209 #define CONFIG_AUTO_COMPLETE 1
210 /* 210 /*
211 * Miscellaneous configurable options 211 * Miscellaneous configurable options
212 */ 212 */
213 #define V_PROMPT "AM3517_CRANE # " 213 #define V_PROMPT "AM3517_CRANE # "
214 214
215 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 215 #define CONFIG_SYS_LONGHELP /* undef to save memory */
216 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 216 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
217 #define CONFIG_SYS_PROMPT V_PROMPT 217 #define CONFIG_SYS_PROMPT V_PROMPT
218 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 218 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
219 /* Print Buffer Size */ 219 /* Print Buffer Size */
220 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 220 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
221 sizeof(CONFIG_SYS_PROMPT) + 16) 221 sizeof(CONFIG_SYS_PROMPT) + 16)
222 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 222 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
223 /* args */ 223 /* args */
224 /* Boot Argument Buffer Size */ 224 /* Boot Argument Buffer Size */
225 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 225 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
226 /* memtest works on */ 226 /* memtest works on */
227 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 227 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
228 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 228 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
229 0x01F00000) /* 31MB */ 229 0x01F00000) /* 31MB */
230 230
231 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 231 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
232 /* address */ 232 /* address */
233 233
234 /* 234 /*
235 * AM3517 has 12 GP timers, they can be driven by the system clock 235 * AM3517 has 12 GP timers, they can be driven by the system clock
236 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 236 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
237 * This rate is divided by a local divisor. 237 * This rate is divided by a local divisor.
238 */ 238 */
239 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 239 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
240 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 240 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
241 241
242 /*----------------------------------------------------------------------- 242 /*-----------------------------------------------------------------------
243 * Physical Memory Map 243 * Physical Memory Map
244 */ 244 */
245 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 245 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
246 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 246 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
247 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 247 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
248 248
249 /*----------------------------------------------------------------------- 249 /*-----------------------------------------------------------------------
250 * FLASH and environment organization 250 * FLASH and environment organization
251 */ 251 */
252 252
253 /* **** PISMO SUPPORT *** */ 253 /* **** PISMO SUPPORT *** */
254 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 254 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
255 /* on one chip */ 255 /* on one chip */
256 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 256 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
257 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 257 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
258 258
259 #define CONFIG_SYS_FLASH_BASE NAND_BASE 259 #define CONFIG_SYS_FLASH_BASE NAND_BASE
260 260
261 /* Monitor at start of flash */ 261 /* Monitor at start of flash */
262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
263 263
264 #define CONFIG_NAND_OMAP_GPMC 264 #define CONFIG_NAND_OMAP_GPMC
265 #define CONFIG_ENV_IS_IN_NAND 1 265 #define CONFIG_ENV_IS_IN_NAND 1
266 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 266 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
267 267
268 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 268 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
269 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 269 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
270 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 270 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
271 271
272 /*----------------------------------------------------------------------- 272 /*-----------------------------------------------------------------------
273 * CFI FLASH driver setup 273 * CFI FLASH driver setup
274 */ 274 */
275 /* timeout values are in ticks */ 275 /* timeout values are in ticks */
276 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 276 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
277 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 277 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
278 278
279 /* Flash banks JFFS2 should use */ 279 /* Flash banks JFFS2 should use */
280 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 280 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
281 CONFIG_SYS_MAX_NAND_DEVICE) 281 CONFIG_SYS_MAX_NAND_DEVICE)
282 #define CONFIG_SYS_JFFS2_MEM_NAND 282 #define CONFIG_SYS_JFFS2_MEM_NAND
283 /* use flash_info[2] */ 283 /* use flash_info[2] */
284 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 284 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
285 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 285 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
286 286
287 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 287 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
288 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 288 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
289 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 289 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
290 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 290 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
291 CONFIG_SYS_INIT_RAM_SIZE - \ 291 CONFIG_SYS_INIT_RAM_SIZE - \
292 GENERATED_GBL_DATA_SIZE) 292 GENERATED_GBL_DATA_SIZE)
293 293
294 /* Defines for SPL */ 294 /* Defines for SPL */
295 #define CONFIG_SPL_FRAMEWORK 295 #define CONFIG_SPL_FRAMEWORK
296 #define CONFIG_SPL_BOARD_INIT 296 #define CONFIG_SPL_BOARD_INIT
297 #define CONFIG_SPL_NAND_SIMPLE 297 #define CONFIG_SPL_NAND_SIMPLE
298 #define CONFIG_SPL_TEXT_BASE 0x40200800 298 #define CONFIG_SPL_TEXT_BASE 0x40200800
299 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 299 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
300 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
301 300
302 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 301 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
303 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 302 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
304 303
305 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 304 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
306 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 305 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
307 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 306 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
308 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 307 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
309 308
310 #define CONFIG_SPL_LIBCOMMON_SUPPORT 309 #define CONFIG_SPL_LIBCOMMON_SUPPORT
311 #define CONFIG_SPL_LIBDISK_SUPPORT 310 #define CONFIG_SPL_LIBDISK_SUPPORT
312 #define CONFIG_SPL_I2C_SUPPORT 311 #define CONFIG_SPL_I2C_SUPPORT
313 #define CONFIG_SPL_LIBGENERIC_SUPPORT 312 #define CONFIG_SPL_LIBGENERIC_SUPPORT
314 #define CONFIG_SPL_MMC_SUPPORT 313 #define CONFIG_SPL_MMC_SUPPORT
315 #define CONFIG_SPL_FAT_SUPPORT 314 #define CONFIG_SPL_FAT_SUPPORT
316 #define CONFIG_SPL_SERIAL_SUPPORT 315 #define CONFIG_SPL_SERIAL_SUPPORT
317 #define CONFIG_SPL_NAND_SUPPORT 316 #define CONFIG_SPL_NAND_SUPPORT
318 #define CONFIG_SPL_NAND_BASE 317 #define CONFIG_SPL_NAND_BASE
319 #define CONFIG_SPL_NAND_DRIVERS 318 #define CONFIG_SPL_NAND_DRIVERS
320 #define CONFIG_SPL_NAND_ECC 319 #define CONFIG_SPL_NAND_ECC
321 #define CONFIG_SPL_POWER_SUPPORT 320 #define CONFIG_SPL_POWER_SUPPORT
322 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 321 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
323 322
324 /* NAND boot config */ 323 /* NAND boot config */
325 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 324 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
326 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 325 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
327 #define CONFIG_SYS_NAND_PAGE_COUNT 64 326 #define CONFIG_SYS_NAND_PAGE_COUNT 64
328 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 327 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
329 #define CONFIG_SYS_NAND_OOBSIZE 64 328 #define CONFIG_SYS_NAND_OOBSIZE 64
330 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 329 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
331 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 330 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
332 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 331 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
333 10, 11, 12, 13} 332 10, 11, 12, 13}
334 #define CONFIG_SYS_NAND_ECCSIZE 512 333 #define CONFIG_SYS_NAND_ECCSIZE 512
335 #define CONFIG_SYS_NAND_ECCBYTES 3 334 #define CONFIG_SYS_NAND_ECCBYTES 3
336 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 335 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
337 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 336 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
338 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 337 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
339 338
340 /* 339 /*
341 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 340 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
342 * 64 bytes before this address should be set aside for u-boot.img's 341 * 64 bytes before this address should be set aside for u-boot.img's
343 * header. That is 0x800FFFC0--0x80100000 should not be used for any 342 * header. That is 0x800FFFC0--0x80100000 should not be used for any
344 * other needs. 343 * other needs.
345 */ 344 */
346 #define CONFIG_SYS_TEXT_BASE 0x80100000 345 #define CONFIG_SYS_TEXT_BASE 0x80100000
347 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 346 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
348 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 347 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
349 348
350 #endif /* __CONFIG_H */ 349 #endif /* __CONFIG_H */
351 350
include/configs/am3517_evm.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * am3517_evm.h - Default configuration for AM3517 EVM board. 2 * am3517_evm.h - Default configuration for AM3517 EVM board.
3 * 3 *
4 * Author: Vaibhav Hiremath <hvaibhav@ti.com> 4 * Author: Vaibhav Hiremath <hvaibhav@ti.com>
5 * 5 *
6 * Based on omap3_evm_config.h 6 * Based on omap3_evm_config.h
7 * 7 *
8 * Copyright (C) 2010 Texas Instruments Incorporated 8 * Copyright (C) 2010 Texas Instruments Incorporated
9 * 9 *
10 * SPDX-License-Identifier: GPL-2.0+ 10 * SPDX-License-Identifier: GPL-2.0+
11 */ 11 */
12 12
13 #ifndef __CONFIG_H 13 #ifndef __CONFIG_H
14 #define __CONFIG_H 14 #define __CONFIG_H
15 15
16 /* 16 /*
17 * High Level Configuration Options 17 * High Level Configuration Options
18 */ 18 */
19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */
20 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ 20 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
21 #define CONFIG_OMAP_COMMON 21 #define CONFIG_OMAP_COMMON
22 22
23 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 23 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
24 24
25 #include <asm/arch/cpu.h> /* get chip and board defs */ 25 #include <asm/arch/cpu.h> /* get chip and board defs */
26 #include <asm/arch/omap3.h> 26 #include <asm/arch/omap3.h>
27 27
28 /* 28 /*
29 * Display CPU and Board information 29 * Display CPU and Board information
30 */ 30 */
31 #define CONFIG_DISPLAY_CPUINFO 1 31 #define CONFIG_DISPLAY_CPUINFO 1
32 #define CONFIG_DISPLAY_BOARDINFO 1 32 #define CONFIG_DISPLAY_BOARDINFO 1
33 33
34 /* Clock Defines */ 34 /* Clock Defines */
35 #define V_OSCK 26000000 /* Clock output from T2 */ 35 #define V_OSCK 26000000 /* Clock output from T2 */
36 #define V_SCLK (V_OSCK >> 1) 36 #define V_SCLK (V_OSCK >> 1)
37 37
38 #define CONFIG_MISC_INIT_R 38 #define CONFIG_MISC_INIT_R
39 39
40 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 40 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41 #define CONFIG_SETUP_MEMORY_TAGS 1 41 #define CONFIG_SETUP_MEMORY_TAGS 1
42 #define CONFIG_INITRD_TAG 1 42 #define CONFIG_INITRD_TAG 1
43 #define CONFIG_REVISION_TAG 1 43 #define CONFIG_REVISION_TAG 1
44 44
45 /* 45 /*
46 * Size of malloc() pool 46 * Size of malloc() pool
47 */ 47 */
48 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 48 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
50 /* 50 /*
51 * DDR related 51 * DDR related
52 */ 52 */
53 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 53 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
54 54
55 /* 55 /*
56 * Hardware drivers 56 * Hardware drivers
57 */ 57 */
58 58
59 /* 59 /*
60 * OMAP GPIO configuration 60 * OMAP GPIO configuration
61 */ 61 */
62 #define CONFIG_OMAP_GPIO 62 #define CONFIG_OMAP_GPIO
63 63
64 /* 64 /*
65 * NS16550 Configuration 65 * NS16550 Configuration
66 */ 66 */
67 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 67 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
68 68
69 #define CONFIG_SYS_NS16550 69 #define CONFIG_SYS_NS16550
70 #define CONFIG_SYS_NS16550_SERIAL 70 #define CONFIG_SYS_NS16550_SERIAL
71 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 71 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
72 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 72 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
73 73
74 /* 74 /*
75 * select serial console configuration 75 * select serial console configuration
76 */ 76 */
77 #define CONFIG_CONS_INDEX 3 77 #define CONFIG_CONS_INDEX 3
78 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 78 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
79 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ 79 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */
80 80
81 /* allow to overwrite serial and ethaddr */ 81 /* allow to overwrite serial and ethaddr */
82 #define CONFIG_ENV_OVERWRITE 82 #define CONFIG_ENV_OVERWRITE
83 #define CONFIG_BAUDRATE 115200 83 #define CONFIG_BAUDRATE 115200
84 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 84 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
85 115200} 85 115200}
86 #define CONFIG_MMC 1 86 #define CONFIG_MMC 1
87 #define CONFIG_GENERIC_MMC 1 87 #define CONFIG_GENERIC_MMC 1
88 #define CONFIG_OMAP_HSMMC 1 88 #define CONFIG_OMAP_HSMMC 1
89 #define CONFIG_DOS_PARTITION 1 89 #define CONFIG_DOS_PARTITION 1
90 90
91 /* 91 /*
92 * USB configuration 92 * USB configuration
93 * Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard 93 * Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard
94 * Enable CONFIG_MUSB_GADGET for Device functionalities. 94 * Enable CONFIG_MUSB_GADGET for Device functionalities.
95 */ 95 */
96 #define CONFIG_USB_MUSB_AM35X 96 #define CONFIG_USB_MUSB_AM35X
97 #define CONFIG_MUSB_HOST 97 #define CONFIG_MUSB_HOST
98 #define CONFIG_MUSB_PIO_ONLY 98 #define CONFIG_MUSB_PIO_ONLY
99 99
100 #ifdef CONFIG_USB_MUSB_AM35X 100 #ifdef CONFIG_USB_MUSB_AM35X
101 101
102 #ifdef CONFIG_MUSB_HOST 102 #ifdef CONFIG_MUSB_HOST
103 #define CONFIG_CMD_USB 103 #define CONFIG_CMD_USB
104 104
105 #define CONFIG_USB_STORAGE 105 #define CONFIG_USB_STORAGE
106 #define CONGIG_CMD_STORAGE 106 #define CONGIG_CMD_STORAGE
107 #define CONFIG_CMD_FAT 107 #define CONFIG_CMD_FAT
108 108
109 #ifdef CONFIG_USB_KEYBOARD 109 #ifdef CONFIG_USB_KEYBOARD
110 #define CONFIG_SYS_USB_EVENT_POLL 110 #define CONFIG_SYS_USB_EVENT_POLL
111 #define CONFIG_PREBOOT "usb start" 111 #define CONFIG_PREBOOT "usb start"
112 #endif /* CONFIG_USB_KEYBOARD */ 112 #endif /* CONFIG_USB_KEYBOARD */
113 113
114 #endif /* CONFIG_MUSB_HOST */ 114 #endif /* CONFIG_MUSB_HOST */
115 115
116 #ifdef CONFIG_MUSB_GADGET 116 #ifdef CONFIG_MUSB_GADGET
117 #define CONFIG_USB_GADGET_DUALSPEED 117 #define CONFIG_USB_GADGET_DUALSPEED
118 #define CONFIG_USB_ETHER 118 #define CONFIG_USB_ETHER
119 #define CONFIG_USB_ETH_RNDIS 119 #define CONFIG_USB_ETH_RNDIS
120 #endif /* CONFIG_MUSB_GADGET */ 120 #endif /* CONFIG_MUSB_GADGET */
121 121
122 #endif /* CONFIG_USB_MUSB_AM35X */ 122 #endif /* CONFIG_USB_MUSB_AM35X */
123 123
124 /* commands to include */ 124 /* commands to include */
125 #include <config_cmd_default.h> 125 #include <config_cmd_default.h>
126 126
127 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 127 #define CONFIG_CMD_EXT2 /* EXT2 Support */
128 #define CONFIG_CMD_FAT /* FAT support */ 128 #define CONFIG_CMD_FAT /* FAT support */
129 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 129 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
130 130
131 #define CONFIG_CMD_I2C /* I2C serial bus support */ 131 #define CONFIG_CMD_I2C /* I2C serial bus support */
132 #define CONFIG_CMD_MMC /* MMC support */ 132 #define CONFIG_CMD_MMC /* MMC support */
133 #define CONFIG_CMD_NAND /* NAND support */ 133 #define CONFIG_CMD_NAND /* NAND support */
134 #define CONFIG_CMD_DHCP 134 #define CONFIG_CMD_DHCP
135 #undef CONFIG_CMD_PING 135 #undef CONFIG_CMD_PING
136 136
137 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 137 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
138 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 138 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
139 #undef CONFIG_CMD_IMI /* iminfo */ 139 #undef CONFIG_CMD_IMI /* iminfo */
140 #undef CONFIG_CMD_IMLS /* List all found images */ 140 #undef CONFIG_CMD_IMLS /* List all found images */
141 141
142 #define CONFIG_SYS_NO_FLASH 142 #define CONFIG_SYS_NO_FLASH
143 #define CONFIG_SYS_I2C 143 #define CONFIG_SYS_I2C
144 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 144 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
145 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 145 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
146 #define CONFIG_SYS_I2C_OMAP34XX 146 #define CONFIG_SYS_I2C_OMAP34XX
147 147
148 /* 148 /*
149 * Ethernet 149 * Ethernet
150 */ 150 */
151 #define CONFIG_DRIVER_TI_EMAC 151 #define CONFIG_DRIVER_TI_EMAC
152 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 152 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
153 #define CONFIG_MII 153 #define CONFIG_MII
154 #define CONFIG_BOOTP_DEFAULT 154 #define CONFIG_BOOTP_DEFAULT
155 #define CONFIG_BOOTP_DNS 155 #define CONFIG_BOOTP_DNS
156 #define CONFIG_BOOTP_DNS2 156 #define CONFIG_BOOTP_DNS2
157 #define CONFIG_BOOTP_SEND_HOSTNAME 157 #define CONFIG_BOOTP_SEND_HOSTNAME
158 #define CONFIG_NET_RETRY_COUNT 10 158 #define CONFIG_NET_RETRY_COUNT 10
159 159
160 /* 160 /*
161 * Board NAND Info. 161 * Board NAND Info.
162 */ 162 */
163 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 163 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
164 /* to access nand */ 164 /* to access nand */
165 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 165 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
166 /* to access */ 166 /* to access */
167 /* nand at CS0 */ 167 /* nand at CS0 */
168 168
169 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 169 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
170 /* NAND devices */ 170 /* NAND devices */
171 #define CONFIG_JFFS2_NAND 171 #define CONFIG_JFFS2_NAND
172 /* nand device jffs2 lives on */ 172 /* nand device jffs2 lives on */
173 #define CONFIG_JFFS2_DEV "nand0" 173 #define CONFIG_JFFS2_DEV "nand0"
174 /* start of jffs2 partition */ 174 /* start of jffs2 partition */
175 #define CONFIG_JFFS2_PART_OFFSET 0x680000 175 #define CONFIG_JFFS2_PART_OFFSET 0x680000
176 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 176 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
177 177
178 /* Environment information */ 178 /* Environment information */
179 #define CONFIG_BOOTDELAY 10 179 #define CONFIG_BOOTDELAY 10
180 180
181 #define CONFIG_BOOTFILE "uImage" 181 #define CONFIG_BOOTFILE "uImage"
182 182
183 #define CONFIG_EXTRA_ENV_SETTINGS \ 183 #define CONFIG_EXTRA_ENV_SETTINGS \
184 "loadaddr=0x82000000\0" \ 184 "loadaddr=0x82000000\0" \
185 "console=ttyO2,115200n8\0" \ 185 "console=ttyO2,115200n8\0" \
186 "mmcdev=0\0" \ 186 "mmcdev=0\0" \
187 "mmcargs=setenv bootargs console=${console} " \ 187 "mmcargs=setenv bootargs console=${console} " \
188 "root=/dev/mmcblk0p2 rw rootwait\0" \ 188 "root=/dev/mmcblk0p2 rw rootwait\0" \
189 "nandargs=setenv bootargs console=${console} " \ 189 "nandargs=setenv bootargs console=${console} " \
190 "root=/dev/mtdblock4 rw " \ 190 "root=/dev/mtdblock4 rw " \
191 "rootfstype=jffs2\0" \ 191 "rootfstype=jffs2\0" \
192 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 192 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
193 "bootscript=echo Running bootscript from mmc ...; " \ 193 "bootscript=echo Running bootscript from mmc ...; " \
194 "source ${loadaddr}\0" \ 194 "source ${loadaddr}\0" \
195 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 195 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
196 "mmcboot=echo Booting from mmc ...; " \ 196 "mmcboot=echo Booting from mmc ...; " \
197 "run mmcargs; " \ 197 "run mmcargs; " \
198 "bootm ${loadaddr}\0" \ 198 "bootm ${loadaddr}\0" \
199 "nandboot=echo Booting from nand ...; " \ 199 "nandboot=echo Booting from nand ...; " \
200 "run nandargs; " \ 200 "run nandargs; " \
201 "nand read ${loadaddr} 280000 400000; " \ 201 "nand read ${loadaddr} 280000 400000; " \
202 "bootm ${loadaddr}\0" \ 202 "bootm ${loadaddr}\0" \
203 203
204 #define CONFIG_BOOTCOMMAND \ 204 #define CONFIG_BOOTCOMMAND \
205 "mmc dev ${mmcdev}; if mmc rescan; then " \ 205 "mmc dev ${mmcdev}; if mmc rescan; then " \
206 "if run loadbootscript; then " \ 206 "if run loadbootscript; then " \
207 "run bootscript; " \ 207 "run bootscript; " \
208 "else " \ 208 "else " \
209 "if run loaduimage; then " \ 209 "if run loaduimage; then " \
210 "run mmcboot; " \ 210 "run mmcboot; " \
211 "else run nandboot; " \ 211 "else run nandboot; " \
212 "fi; " \ 212 "fi; " \
213 "fi; " \ 213 "fi; " \
214 "else run nandboot; fi" 214 "else run nandboot; fi"
215 215
216 #define CONFIG_AUTO_COMPLETE 1 216 #define CONFIG_AUTO_COMPLETE 1
217 /* 217 /*
218 * Miscellaneous configurable options 218 * Miscellaneous configurable options
219 */ 219 */
220 #define V_PROMPT "AM3517_EVM # " 220 #define V_PROMPT "AM3517_EVM # "
221 221
222 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 222 #define CONFIG_SYS_LONGHELP /* undef to save memory */
223 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 223 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
224 #define CONFIG_SYS_PROMPT V_PROMPT 224 #define CONFIG_SYS_PROMPT V_PROMPT
225 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 225 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
226 /* Print Buffer Size */ 226 /* Print Buffer Size */
227 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 227 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
228 sizeof(CONFIG_SYS_PROMPT) + 16) 228 sizeof(CONFIG_SYS_PROMPT) + 16)
229 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 229 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
230 /* args */ 230 /* args */
231 /* Boot Argument Buffer Size */ 231 /* Boot Argument Buffer Size */
232 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 232 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
233 /* memtest works on */ 233 /* memtest works on */
234 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 234 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
235 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 235 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
236 0x01F00000) /* 31MB */ 236 0x01F00000) /* 31MB */
237 237
238 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 238 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
239 /* address */ 239 /* address */
240 240
241 /* 241 /*
242 * AM3517 has 12 GP timers, they can be driven by the system clock 242 * AM3517 has 12 GP timers, they can be driven by the system clock
243 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 243 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
244 * This rate is divided by a local divisor. 244 * This rate is divided by a local divisor.
245 */ 245 */
246 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 246 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
247 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 247 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
248 248
249 /*----------------------------------------------------------------------- 249 /*-----------------------------------------------------------------------
250 * Physical Memory Map 250 * Physical Memory Map
251 */ 251 */
252 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 252 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
253 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 253 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
254 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 254 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
255 255
256 /*----------------------------------------------------------------------- 256 /*-----------------------------------------------------------------------
257 * FLASH and environment organization 257 * FLASH and environment organization
258 */ 258 */
259 259
260 /* **** PISMO SUPPORT *** */ 260 /* **** PISMO SUPPORT *** */
261 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 261 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
262 /* on one chip */ 262 /* on one chip */
263 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 263 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
264 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 264 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
265 265
266 #if defined(CONFIG_CMD_NAND) 266 #if defined(CONFIG_CMD_NAND)
267 #define CONFIG_SYS_FLASH_BASE NAND_BASE 267 #define CONFIG_SYS_FLASH_BASE NAND_BASE
268 #endif 268 #endif
269 269
270 /* Monitor at start of flash */ 270 /* Monitor at start of flash */
271 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 271 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
272 272
273 #define CONFIG_NAND_OMAP_GPMC 273 #define CONFIG_NAND_OMAP_GPMC
274 #define CONFIG_ENV_IS_IN_NAND 1 274 #define CONFIG_ENV_IS_IN_NAND 1
275 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 275 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
276 276
277 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 277 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
278 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 278 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
279 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 279 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
280 280
281 /*----------------------------------------------------------------------- 281 /*-----------------------------------------------------------------------
282 * CFI FLASH driver setup 282 * CFI FLASH driver setup
283 */ 283 */
284 /* timeout values are in ticks */ 284 /* timeout values are in ticks */
285 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 285 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
286 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 286 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
287 287
288 /* Flash banks JFFS2 should use */ 288 /* Flash banks JFFS2 should use */
289 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 289 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
290 CONFIG_SYS_MAX_NAND_DEVICE) 290 CONFIG_SYS_MAX_NAND_DEVICE)
291 #define CONFIG_SYS_JFFS2_MEM_NAND 291 #define CONFIG_SYS_JFFS2_MEM_NAND
292 /* use flash_info[2] */ 292 /* use flash_info[2] */
293 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 293 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
294 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 294 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
295 295
296 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 296 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
297 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 297 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
298 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 298 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
299 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 299 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
300 CONFIG_SYS_INIT_RAM_SIZE - \ 300 CONFIG_SYS_INIT_RAM_SIZE - \
301 GENERATED_GBL_DATA_SIZE) 301 GENERATED_GBL_DATA_SIZE)
302 302
303 /* Defines for SPL */ 303 /* Defines for SPL */
304 #define CONFIG_SPL_FRAMEWORK 304 #define CONFIG_SPL_FRAMEWORK
305 #define CONFIG_SPL_BOARD_INIT 305 #define CONFIG_SPL_BOARD_INIT
306 #define CONFIG_SPL_NAND_SIMPLE 306 #define CONFIG_SPL_NAND_SIMPLE
307 #define CONFIG_SPL_TEXT_BASE 0x40200800 307 #define CONFIG_SPL_TEXT_BASE 0x40200800
308 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 308 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
309 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
310 309
311 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 310 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
312 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 311 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
313 312
314 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 313 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
315 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 314 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
316 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 315 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
317 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 316 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
318 317
319 #define CONFIG_SPL_LIBCOMMON_SUPPORT 318 #define CONFIG_SPL_LIBCOMMON_SUPPORT
320 #define CONFIG_SPL_LIBDISK_SUPPORT 319 #define CONFIG_SPL_LIBDISK_SUPPORT
321 #define CONFIG_SPL_I2C_SUPPORT 320 #define CONFIG_SPL_I2C_SUPPORT
322 #define CONFIG_SPL_LIBGENERIC_SUPPORT 321 #define CONFIG_SPL_LIBGENERIC_SUPPORT
323 #define CONFIG_SPL_MMC_SUPPORT 322 #define CONFIG_SPL_MMC_SUPPORT
324 #define CONFIG_SPL_FAT_SUPPORT 323 #define CONFIG_SPL_FAT_SUPPORT
325 #define CONFIG_SPL_SERIAL_SUPPORT 324 #define CONFIG_SPL_SERIAL_SUPPORT
326 #define CONFIG_SPL_NAND_SUPPORT 325 #define CONFIG_SPL_NAND_SUPPORT
327 #define CONFIG_SPL_NAND_BASE 326 #define CONFIG_SPL_NAND_BASE
328 #define CONFIG_SPL_NAND_DRIVERS 327 #define CONFIG_SPL_NAND_DRIVERS
329 #define CONFIG_SPL_NAND_ECC 328 #define CONFIG_SPL_NAND_ECC
330 #define CONFIG_SPL_POWER_SUPPORT 329 #define CONFIG_SPL_POWER_SUPPORT
331 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 330 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
332 331
333 /* NAND boot config */ 332 /* NAND boot config */
334 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 333 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
335 #define CONFIG_SYS_NAND_PAGE_COUNT 64 334 #define CONFIG_SYS_NAND_PAGE_COUNT 64
336 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 335 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
337 #define CONFIG_SYS_NAND_OOBSIZE 64 336 #define CONFIG_SYS_NAND_OOBSIZE 64
338 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 337 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
339 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 338 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
340 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 339 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
341 10, 11, 12, 13} 340 10, 11, 12, 13}
342 #define CONFIG_SYS_NAND_ECCSIZE 512 341 #define CONFIG_SYS_NAND_ECCSIZE 512
343 #define CONFIG_SYS_NAND_ECCBYTES 3 342 #define CONFIG_SYS_NAND_ECCBYTES 3
344 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 343 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
345 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 344 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
346 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 345 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
347 346
348 /* 347 /*
349 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 348 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
350 * 64 bytes before this address should be set aside for u-boot.img's 349 * 64 bytes before this address should be set aside for u-boot.img's
351 * header. That is 0x800FFFC0--0x80100000 should not be used for any 350 * header. That is 0x800FFFC0--0x80100000 should not be used for any
352 * other needs. 351 * other needs.
353 */ 352 */
354 #define CONFIG_SYS_TEXT_BASE 0x80100000 353 #define CONFIG_SYS_TEXT_BASE 0x80100000
355 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 354 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
356 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 355 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
357 356
358 #endif /* __CONFIG_H */ 357 #endif /* __CONFIG_H */
359 358
include/configs/bur_am335x_common.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * bur_am335x_common.h 2 * bur_am335x_common.h
3 * 3 *
4 * common parts used by B&R AM335x based boards 4 * common parts used by B&R AM335x based boards
5 * 5 *
6 * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> - 6 * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
8 * 8 *
9 * SPDX-License-Identifier: GPL-2.0+ 9 * SPDX-License-Identifier: GPL-2.0+
10 */ 10 */
11 11
12 #ifndef __BUR_AM335X_COMMON_H__ 12 #ifndef __BUR_AM335X_COMMON_H__
13 #define __BUR_AM335X_COMMON_H__ 13 #define __BUR_AM335X_COMMON_H__
14 /* ------------------------------------------------------------------------- */ 14 /* ------------------------------------------------------------------------- */
15 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_SYS_GENERIC_BOARD
16 16
17 #define CONFIG_AM33XX 17 #define CONFIG_AM33XX
18 #define CONFIG_OMAP 18 #define CONFIG_OMAP
19 #define CONFIG_OMAP_COMMON 19 #define CONFIG_OMAP_COMMON
20 #define CONFIG_BOARD_LATE_INIT 20 #define CONFIG_BOARD_LATE_INIT
21 #define CONFIG_SYS_CACHELINE_SIZE 64 21 #define CONFIG_SYS_CACHELINE_SIZE 64
22 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ 22 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
23 23
24 /* Timer information */ 24 /* Timer information */
25 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 25 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
26 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 26 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
27 #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */ 27 #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */
28 #define CONFIG_SPL_POWER_SUPPORT 28 #define CONFIG_SPL_POWER_SUPPORT
29 #define CONFIG_POWER_TPS65217 29 #define CONFIG_POWER_TPS65217
30 30
31 #define CONFIG_SYS_NO_FLASH /* have no NOR-flash */ 31 #define CONFIG_SYS_NO_FLASH /* have no NOR-flash */
32 32
33 #include <asm/arch/omap.h> 33 #include <asm/arch/omap.h>
34 34
35 /* NS16550 Configuration */ 35 /* NS16550 Configuration */
36 #define CONFIG_SYS_NS16550 36 #define CONFIG_SYS_NS16550
37 #define CONFIG_SYS_NS16550_SERIAL 37 #define CONFIG_SYS_NS16550_SERIAL
38 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 38 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
39 #define CONFIG_SYS_NS16550_CLK 48000000 39 #define CONFIG_SYS_NS16550_CLK 48000000
40 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ 40 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
41 #define CONFIG_BAUDRATE 115200 41 #define CONFIG_BAUDRATE 115200
42 42
43 /* Network defines */ 43 /* Network defines */
44 #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ 44 #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
45 #define CONFIG_CMD_DHCP 45 #define CONFIG_CMD_DHCP
46 #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ 46 #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
47 #define CONFIG_BOOTP_SEND_HOSTNAME 47 #define CONFIG_BOOTP_SEND_HOSTNAME
48 #define CONFIG_BOOTP_GATEWAY 48 #define CONFIG_BOOTP_GATEWAY
49 #define CONFIG_BOOTP_SUBNETMASK 49 #define CONFIG_BOOTP_SUBNETMASK
50 #define CONFIG_NET_RETRY_COUNT 4 50 #define CONFIG_NET_RETRY_COUNT 4
51 #define CONFIG_CMD_PING 51 #define CONFIG_CMD_PING
52 #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ 52 #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
53 #define CONFIG_MII /* Required in net/eth.c */ 53 #define CONFIG_MII /* Required in net/eth.c */
54 #define CONFIG_SPL_ETH_SUPPORT 54 #define CONFIG_SPL_ETH_SUPPORT
55 #define CONFIG_PHYLIB 55 #define CONFIG_PHYLIB
56 #define CONFIG_PHY_NATSEMI 56 #define CONFIG_PHY_NATSEMI
57 #define CONFIG_SPL_NET_SUPPORT 57 #define CONFIG_SPL_NET_SUPPORT
58 #define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */ 58 #define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
59 #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" 59 #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
60 60
61 /* 61 /*
62 * SPL related defines. The Public RAM memory map the ROM defines the 62 * SPL related defines. The Public RAM memory map the ROM defines the
63 * area between 0x402F0400 and 0x4030B800 as a download area and 63 * area between 0x402F0400 and 0x4030B800 as a download area and
64 * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also 64 * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
65 * supports X-MODEM loading via UART, and we leverage this and then use 65 * supports X-MODEM loading via UART, and we leverage this and then use
66 * Y-MODEM to load u-boot.img, when booted over UART. 66 * Y-MODEM to load u-boot.img, when booted over UART.
67 */ 67 */
68 #define CONFIG_SPL_TEXT_BASE 0x402F0400 68 #define CONFIG_SPL_TEXT_BASE 0x402F0400
69 #define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) 69 #define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
70 70
71 /* 71 /*
72 * Since SPL did pll and ddr initialization for us, 72 * Since SPL did pll and ddr initialization for us,
73 * we don't need to do it twice. 73 * we don't need to do it twice.
74 */ 74 */
75 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) 75 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
76 #define CONFIG_SKIP_LOWLEVEL_INIT 76 #define CONFIG_SKIP_LOWLEVEL_INIT
77 #endif /* !CONFIG_SPL_BUILD, ... */ 77 #endif /* !CONFIG_SPL_BUILD, ... */
78 /* 78 /*
79 * Our DDR memory always starts at 0x80000000 and U-Boot shall have 79 * Our DDR memory always starts at 0x80000000 and U-Boot shall have
80 * relocated itself to higher in memory by the time this value is used. 80 * relocated itself to higher in memory by the time this value is used.
81 */ 81 */
82 #define CONFIG_SYS_LOAD_ADDR 0x80000000 82 #define CONFIG_SYS_LOAD_ADDR 0x80000000
83 /* 83 /*
84 * ---------------------------------------------------------------------------- 84 * ----------------------------------------------------------------------------
85 * DDR information. We say (for simplicity) that we have 1 bank, 85 * DDR information. We say (for simplicity) that we have 1 bank,
86 * always, even when we have more. We always start at 0x80000000, 86 * always, even when we have more. We always start at 0x80000000,
87 * and we place the initial stack pointer in our SRAM. 87 * and we place the initial stack pointer in our SRAM.
88 */ 88 */
89 #define CONFIG_NR_DRAM_BANKS 1 89 #define CONFIG_NR_DRAM_BANKS 1
90 #define CONFIG_SYS_SDRAM_BASE 0x80000000 90 #define CONFIG_SYS_SDRAM_BASE 0x80000000
91 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 91 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
92 GENERATED_GBL_DATA_SIZE) 92 GENERATED_GBL_DATA_SIZE)
93 93
94 /* I2C */ 94 /* I2C */
95 #define CONFIG_SYS_I2C 95 #define CONFIG_SYS_I2C
96 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 96 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
97 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 97 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
98 #define CONFIG_SYS_I2C_OMAP24XX 98 #define CONFIG_SYS_I2C_OMAP24XX
99 #define CONFIG_CMD_I2C 99 #define CONFIG_CMD_I2C
100 /* GPIO */ 100 /* GPIO */
101 #define CONFIG_OMAP_GPIO 101 #define CONFIG_OMAP_GPIO
102 #define CONFIG_CMD_GPIO 102 #define CONFIG_CMD_GPIO
103 /* 103 /*
104 * ---------------------------------------------------------------------------- 104 * ----------------------------------------------------------------------------
105 * The following are general good-enough settings for U-Boot. We set a 105 * The following are general good-enough settings for U-Boot. We set a
106 * large malloc pool as we generally have a lot of DDR, and we opt for 106 * large malloc pool as we generally have a lot of DDR, and we opt for
107 * function over binary size in the main portion of U-Boot as this is 107 * function over binary size in the main portion of U-Boot as this is
108 * generally easily constrained later if needed. We enable the config 108 * generally easily constrained later if needed. We enable the config
109 * options that give us information in the environment about what board 109 * options that give us information in the environment about what board
110 * we are on so we do not need to rely on the command prompt. We set a 110 * we are on so we do not need to rely on the command prompt. We set a
111 * console baudrate of 115200 and use the default baud rate table. 111 * console baudrate of 115200 and use the default baud rate table.
112 */ 112 */
113 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 113 #define CONFIG_SYS_MALLOC_LEN (1024 << 10)
114 #define CONFIG_SYS_HUSH_PARSER 114 #define CONFIG_SYS_HUSH_PARSER
115 #define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# " 115 #define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
116 #define CONFIG_SYS_CONSOLE_INFO_QUIET 116 #define CONFIG_SYS_CONSOLE_INFO_QUIET
117 #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ 117 #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
118 118
119 /* As stated above, the following choices are optional. */ 119 /* As stated above, the following choices are optional. */
120 #define CONFIG_SYS_LONGHELP 120 #define CONFIG_SYS_LONGHELP
121 #define CONFIG_AUTO_COMPLETE 121 #define CONFIG_AUTO_COMPLETE
122 #define CONFIG_CMDLINE_EDITING 122 #define CONFIG_CMDLINE_EDITING
123 #define CONFIG_VERSION_VARIABLE 123 #define CONFIG_VERSION_VARIABLE
124 124
125 /* We set the max number of command args high to avoid HUSH bugs. */ 125 /* We set the max number of command args high to avoid HUSH bugs. */
126 #define CONFIG_SYS_MAXARGS 64 126 #define CONFIG_SYS_MAXARGS 64
127 127
128 /* Console I/O Buffer Size */ 128 /* Console I/O Buffer Size */
129 #define CONFIG_SYS_CBSIZE 512 129 #define CONFIG_SYS_CBSIZE 512
130 /* Print Buffer Size */ 130 /* Print Buffer Size */
131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ 131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\
132 sizeof(CONFIG_SYS_PROMPT) + 16) 132 sizeof(CONFIG_SYS_PROMPT) + 16)
133 /* Boot Argument Buffer Size */ 133 /* Boot Argument Buffer Size */
134 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 134 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
135 /* 135 /*
136 * For commands to use, we take the default list and add a few other 136 * For commands to use, we take the default list and add a few other
137 * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH 137 * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
138 * prior to this include, in order to skip a few commands. When we do 138 * prior to this include, in order to skip a few commands. When we do
139 * have flash, if we expect these commands they must be enabled in that 139 * have flash, if we expect these commands they must be enabled in that
140 * config. If desired, a specific list of desired commands can be used 140 * config. If desired, a specific list of desired commands can be used
141 * instead. 141 * instead.
142 */ 142 */
143 #include <config_cmd_default.h> 143 #include <config_cmd_default.h>
144 /* undefine commands, which we do not need */ 144 /* undefine commands, which we do not need */
145 #undef CONFIG_CMD_EDITENV 145 #undef CONFIG_CMD_EDITENV
146 #undef CONFIG_CMD_FPGA 146 #undef CONFIG_CMD_FPGA
147 #undef CONFIG_CMD_IMI 147 #undef CONFIG_CMD_IMI
148 #undef CONFIG_CMD_ITEST 148 #undef CONFIG_CMD_ITEST
149 #undef CONFIG_CMD_LOADS 149 #undef CONFIG_CMD_LOADS
150 #undef CONFIG_CMD_LOADB 150 #undef CONFIG_CMD_LOADB
151 #undef CONFIG_CMD_NFS 151 #undef CONFIG_CMD_NFS
152 #undef CONFIG_CMD_SETGETDCR 152 #undef CONFIG_CMD_SETGETDCR
153 #undef CONFIG_CMD_XIMG 153 #undef CONFIG_CMD_XIMG
154 /* define command we need always */ 154 /* define command we need always */
155 #define CONFIG_CMD_ECHO 155 #define CONFIG_CMD_ECHO
156 #define CONFIG_CMD_SOURCE 156 #define CONFIG_CMD_SOURCE
157 157
158 /* 158 /*
159 * Our platforms make use of SPL to initalize the hardware (primarily 159 * Our platforms make use of SPL to initalize the hardware (primarily
160 * memory) enough for full U-Boot to be loaded. We also support Falcon 160 * memory) enough for full U-Boot to be loaded. We also support Falcon
161 * Mode so that the Linux kernel can be booted directly from SPL 161 * Mode so that the Linux kernel can be booted directly from SPL
162 * instead, if desired. We make use of the general SPL framework found 162 * instead, if desired. We make use of the general SPL framework found
163 * under common/spl/. Given our generally common memory map, we set a 163 * under common/spl/. Given our generally common memory map, we set a
164 * number of related defaults and sizes here. 164 * number of related defaults and sizes here.
165 */ 165 */
166 #define CONFIG_SPL_FRAMEWORK 166 #define CONFIG_SPL_FRAMEWORK
167 /* 167 /*
168 * Place the image at the start of the ROM defined image space. 168 * Place the image at the start of the ROM defined image space.
169 * We limit our size to the ROM-defined downloaded image area, and use the 169 * We limit our size to the ROM-defined downloaded image area, and use the
170 * rest of the space for stack. We load U-Boot itself into memory at 170 * rest of the space for stack. We load U-Boot itself into memory at
171 * 0x80800000 for legacy reasons (to not conflict with older SPLs). We 171 * 0x80800000 for legacy reasons (to not conflict with older SPLs). We
172 * have our BSS be placed 1MiB after this, to allow for the default 172 * have our BSS be placed 1MiB after this, to allow for the default
173 * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. 173 * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
174 * We have the SPL malloc pool at the end of the BSS area. 174 * We have the SPL malloc pool at the end of the BSS area.
175 * 175 *
176 * ---------------------------------------------------------------------------- 176 * ----------------------------------------------------------------------------
177 */ 177 */
178 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
179 #undef CONFIG_SYS_TEXT_BASE 178 #undef CONFIG_SYS_TEXT_BASE
180 #define CONFIG_SYS_TEXT_BASE 0x80800000 179 #define CONFIG_SYS_TEXT_BASE 0x80800000
181 #define CONFIG_SPL_BSS_START_ADDR 0x80A00000 180 #define CONFIG_SPL_BSS_START_ADDR 0x80A00000
182 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 181 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
183 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 182 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
184 CONFIG_SPL_BSS_MAX_SIZE) 183 CONFIG_SPL_BSS_MAX_SIZE)
185 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 184 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
186 185
187 /* General parts of the framework, required. */ 186 /* General parts of the framework, required. */
188 #define CONFIG_SPL_I2C_SUPPORT 187 #define CONFIG_SPL_I2C_SUPPORT
189 #define CONFIG_SPL_LIBCOMMON_SUPPORT 188 #define CONFIG_SPL_LIBCOMMON_SUPPORT
190 #define CONFIG_SPL_LIBGENERIC_SUPPORT 189 #define CONFIG_SPL_LIBGENERIC_SUPPORT
191 #define CONFIG_SPL_SERIAL_SUPPORT 190 #define CONFIG_SPL_SERIAL_SUPPORT
192 #define CONFIG_SPL_BOARD_INIT 191 #define CONFIG_SPL_BOARD_INIT
193 #define CONFIG_SPL_YMODEM_SUPPORT 192 #define CONFIG_SPL_YMODEM_SUPPORT
194 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" 193 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
195 194
196 #endif /* ! __BUR_AM335X_COMMON_H__ */ 195 #endif /* ! __BUR_AM335X_COMMON_H__ */
197 196
include/configs/cm_t35.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * (C) Copyright 2011 CompuLab, Ltd. 2 * (C) Copyright 2011 CompuLab, Ltd.
3 * Mike Rapoport <mike@compulab.co.il> 3 * Mike Rapoport <mike@compulab.co.il>
4 * Igor Grinberg <grinberg@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il>
5 * 5 *
6 * Based on omap3_beagle.h 6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008 7 * (C) Copyright 2006-2008
8 * Texas Instruments. 8 * Texas Instruments.
9 * Richard Woodruff <r-woodruff2@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com>
11 * 11 *
12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
13 * 13 *
14 * SPDX-License-Identifier: GPL-2.0+ 14 * SPDX-License-Identifier: GPL-2.0+
15 */ 15 */
16 16
17 #ifndef __CONFIG_H 17 #ifndef __CONFIG_H
18 #define __CONFIG_H 18 #define __CONFIG_H
19 19
20 /* 20 /*
21 * High Level Configuration Options 21 * High Level Configuration Options
22 */ 22 */
23 #define CONFIG_OMAP /* in a TI OMAP core */ 23 #define CONFIG_OMAP /* in a TI OMAP core */
24 #define CONFIG_OMAP_GPIO 24 #define CONFIG_OMAP_GPIO
25 #define CONFIG_CMD_GPIO 25 #define CONFIG_CMD_GPIO
26 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 26 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
27 #define CONFIG_OMAP_COMMON 27 #define CONFIG_OMAP_COMMON
28 #define CONFIG_SYS_GENERIC_BOARD 28 #define CONFIG_SYS_GENERIC_BOARD
29 29
30 #define CONFIG_SDRC /* The chip has SDRC controller */ 30 #define CONFIG_SDRC /* The chip has SDRC controller */
31 31
32 #include <asm/arch/cpu.h> /* get chip and board defs */ 32 #include <asm/arch/cpu.h> /* get chip and board defs */
33 #include <asm/arch/omap3.h> 33 #include <asm/arch/omap3.h>
34 34
35 /* 35 /*
36 * Display CPU and Board information 36 * Display CPU and Board information
37 */ 37 */
38 #define CONFIG_DISPLAY_CPUINFO 38 #define CONFIG_DISPLAY_CPUINFO
39 #define CONFIG_DISPLAY_BOARDINFO 39 #define CONFIG_DISPLAY_BOARDINFO
40 40
41 /* Clock Defines */ 41 /* Clock Defines */
42 #define V_OSCK 26000000 /* Clock output from T2 */ 42 #define V_OSCK 26000000 /* Clock output from T2 */
43 #define V_SCLK (V_OSCK >> 1) 43 #define V_SCLK (V_OSCK >> 1)
44 44
45 #define CONFIG_MISC_INIT_R 45 #define CONFIG_MISC_INIT_R
46 46
47 #define CONFIG_OF_LIBFDT 1 47 #define CONFIG_OF_LIBFDT 1
48 48
49 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 49 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
50 #define CONFIG_SETUP_MEMORY_TAGS 50 #define CONFIG_SETUP_MEMORY_TAGS
51 #define CONFIG_INITRD_TAG 51 #define CONFIG_INITRD_TAG
52 #define CONFIG_REVISION_TAG 52 #define CONFIG_REVISION_TAG
53 #define CONFIG_SERIAL_TAG 53 #define CONFIG_SERIAL_TAG
54 54
55 /* 55 /*
56 * Size of malloc() pool 56 * Size of malloc() pool
57 */ 57 */
58 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 58 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
59 /* Sector */ 59 /* Sector */
60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
61 61
62 /* 62 /*
63 * Hardware drivers 63 * Hardware drivers
64 */ 64 */
65 65
66 /* 66 /*
67 * NS16550 Configuration 67 * NS16550 Configuration
68 */ 68 */
69 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
70 70
71 #define CONFIG_SYS_NS16550 71 #define CONFIG_SYS_NS16550
72 #define CONFIG_SYS_NS16550_SERIAL 72 #define CONFIG_SYS_NS16550_SERIAL
73 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 73 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
74 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 74 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
75 75
76 /* 76 /*
77 * select serial console configuration 77 * select serial console configuration
78 */ 78 */
79 #define CONFIG_CONS_INDEX 3 79 #define CONFIG_CONS_INDEX 3
80 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 80 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
81 #define CONFIG_SERIAL3 3 /* UART3 */ 81 #define CONFIG_SERIAL3 3 /* UART3 */
82 82
83 /* allow to overwrite serial and ethaddr */ 83 /* allow to overwrite serial and ethaddr */
84 #define CONFIG_ENV_OVERWRITE 84 #define CONFIG_ENV_OVERWRITE
85 #define CONFIG_BAUDRATE 115200 85 #define CONFIG_BAUDRATE 115200
86 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 86 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
87 115200} 87 115200}
88 88
89 #define CONFIG_GENERIC_MMC 89 #define CONFIG_GENERIC_MMC
90 #define CONFIG_MMC 90 #define CONFIG_MMC
91 #define CONFIG_OMAP_HSMMC 91 #define CONFIG_OMAP_HSMMC
92 #define CONFIG_DOS_PARTITION 92 #define CONFIG_DOS_PARTITION
93 93
94 /* USB */ 94 /* USB */
95 #define CONFIG_USB_OMAP3 95 #define CONFIG_USB_OMAP3
96 #define CONFIG_USB_EHCI 96 #define CONFIG_USB_EHCI
97 #define CONFIG_USB_EHCI_OMAP 97 #define CONFIG_USB_EHCI_OMAP
98 #define CONFIG_USB_STORAGE 98 #define CONFIG_USB_STORAGE
99 #define CONFIG_MUSB_UDC 99 #define CONFIG_MUSB_UDC
100 #define CONFIG_TWL4030_USB 100 #define CONFIG_TWL4030_USB
101 #define CONFIG_CMD_USB 101 #define CONFIG_CMD_USB
102 102
103 /* USB device configuration */ 103 /* USB device configuration */
104 #define CONFIG_USB_DEVICE 104 #define CONFIG_USB_DEVICE
105 #define CONFIG_USB_TTY 105 #define CONFIG_USB_TTY
106 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 106 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
107 107
108 /* commands to include */ 108 /* commands to include */
109 #include <config_cmd_default.h> 109 #include <config_cmd_default.h>
110 110
111 #define CONFIG_CMD_CACHE 111 #define CONFIG_CMD_CACHE
112 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 112 #define CONFIG_CMD_EXT2 /* EXT2 Support */
113 #define CONFIG_CMD_FAT /* FAT support */ 113 #define CONFIG_CMD_FAT /* FAT support */
114 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 114 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
115 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 115 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
116 #define CONFIG_MTD_PARTITIONS 116 #define CONFIG_MTD_PARTITIONS
117 #define MTDIDS_DEFAULT "nand0=nand" 117 #define MTDIDS_DEFAULT "nand0=nand"
118 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 118 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
119 "1920k(u-boot),256k(u-boot-env),"\ 119 "1920k(u-boot),256k(u-boot-env),"\
120 "4m(kernel),-(fs)" 120 "4m(kernel),-(fs)"
121 121
122 #define CONFIG_CMD_I2C /* I2C serial bus support */ 122 #define CONFIG_CMD_I2C /* I2C serial bus support */
123 #define CONFIG_CMD_MMC /* MMC support */ 123 #define CONFIG_CMD_MMC /* MMC support */
124 #define CONFIG_CMD_NAND /* NAND support */ 124 #define CONFIG_CMD_NAND /* NAND support */
125 #define CONFIG_CMD_DHCP 125 #define CONFIG_CMD_DHCP
126 #define CONFIG_CMD_PING 126 #define CONFIG_CMD_PING
127 127
128 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 128 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
129 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 129 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
130 #undef CONFIG_CMD_IMLS /* List all found images */ 130 #undef CONFIG_CMD_IMLS /* List all found images */
131 131
132 #define CONFIG_SYS_NO_FLASH 132 #define CONFIG_SYS_NO_FLASH
133 #define CONFIG_SYS_I2C 133 #define CONFIG_SYS_I2C
134 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 134 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
135 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 135 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
136 #define CONFIG_SYS_I2C_OMAP34XX 136 #define CONFIG_SYS_I2C_OMAP34XX
137 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 137 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
138 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 138 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
139 #define CONFIG_SYS_I2C_EEPROM_BUS 0 139 #define CONFIG_SYS_I2C_EEPROM_BUS 0
140 #define CONFIG_I2C_MULTI_BUS 140 #define CONFIG_I2C_MULTI_BUS
141 141
142 /* 142 /*
143 * TWL4030 143 * TWL4030
144 */ 144 */
145 #define CONFIG_TWL4030_POWER 145 #define CONFIG_TWL4030_POWER
146 #define CONFIG_TWL4030_LED 146 #define CONFIG_TWL4030_LED
147 147
148 /* 148 /*
149 * Board NAND Info. 149 * Board NAND Info.
150 */ 150 */
151 #define CONFIG_SYS_NAND_QUIET_TEST 151 #define CONFIG_SYS_NAND_QUIET_TEST
152 #define CONFIG_NAND_OMAP_GPMC 152 #define CONFIG_NAND_OMAP_GPMC
153 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 153 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
154 /* to access nand */ 154 /* to access nand */
155 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 155 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
156 /* to access nand at */ 156 /* to access nand at */
157 /* CS0 */ 157 /* CS0 */
158 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 158 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
159 /* devices */ 159 /* devices */
160 160
161 /* Environment information */ 161 /* Environment information */
162 #define CONFIG_BOOTDELAY 3 162 #define CONFIG_BOOTDELAY 3
163 #define CONFIG_ZERO_BOOTDELAY_CHECK 163 #define CONFIG_ZERO_BOOTDELAY_CHECK
164 164
165 #define CONFIG_EXTRA_ENV_SETTINGS \ 165 #define CONFIG_EXTRA_ENV_SETTINGS \
166 "loadaddr=0x82000000\0" \ 166 "loadaddr=0x82000000\0" \
167 "usbtty=cdc_acm\0" \ 167 "usbtty=cdc_acm\0" \
168 "console=ttyO2,115200n8\0" \ 168 "console=ttyO2,115200n8\0" \
169 "mpurate=500\0" \ 169 "mpurate=500\0" \
170 "vram=12M\0" \ 170 "vram=12M\0" \
171 "dvimode=1024x768MR-16@60\0" \ 171 "dvimode=1024x768MR-16@60\0" \
172 "defaultdisplay=dvi\0" \ 172 "defaultdisplay=dvi\0" \
173 "mmcdev=0\0" \ 173 "mmcdev=0\0" \
174 "mmcroot=/dev/mmcblk0p2 rw\0" \ 174 "mmcroot=/dev/mmcblk0p2 rw\0" \
175 "mmcrootfstype=ext4 rootwait\0" \ 175 "mmcrootfstype=ext4 rootwait\0" \
176 "nandroot=/dev/mtdblock4 rw\0" \ 176 "nandroot=/dev/mtdblock4 rw\0" \
177 "nandrootfstype=ubifs\0" \ 177 "nandrootfstype=ubifs\0" \
178 "mmcargs=setenv bootargs console=${console} " \ 178 "mmcargs=setenv bootargs console=${console} " \
179 "mpurate=${mpurate} " \ 179 "mpurate=${mpurate} " \
180 "vram=${vram} " \ 180 "vram=${vram} " \
181 "omapfb.mode=dvi:${dvimode} " \ 181 "omapfb.mode=dvi:${dvimode} " \
182 "omapdss.def_disp=${defaultdisplay} " \ 182 "omapdss.def_disp=${defaultdisplay} " \
183 "root=${mmcroot} " \ 183 "root=${mmcroot} " \
184 "rootfstype=${mmcrootfstype}\0" \ 184 "rootfstype=${mmcrootfstype}\0" \
185 "nandargs=setenv bootargs console=${console} " \ 185 "nandargs=setenv bootargs console=${console} " \
186 "mpurate=${mpurate} " \ 186 "mpurate=${mpurate} " \
187 "vram=${vram} " \ 187 "vram=${vram} " \
188 "omapfb.mode=dvi:${dvimode} " \ 188 "omapfb.mode=dvi:${dvimode} " \
189 "omapdss.def_disp=${defaultdisplay} " \ 189 "omapdss.def_disp=${defaultdisplay} " \
190 "root=${nandroot} " \ 190 "root=${nandroot} " \
191 "rootfstype=${nandrootfstype}\0" \ 191 "rootfstype=${nandrootfstype}\0" \
192 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 192 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
193 "bootscript=echo Running bootscript from mmc ...; " \ 193 "bootscript=echo Running bootscript from mmc ...; " \
194 "source ${loadaddr}\0" \ 194 "source ${loadaddr}\0" \
195 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 195 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
196 "mmcboot=echo Booting from mmc ...; " \ 196 "mmcboot=echo Booting from mmc ...; " \
197 "run mmcargs; " \ 197 "run mmcargs; " \
198 "bootm ${loadaddr}\0" \ 198 "bootm ${loadaddr}\0" \
199 "nandboot=echo Booting from nand ...; " \ 199 "nandboot=echo Booting from nand ...; " \
200 "run nandargs; " \ 200 "run nandargs; " \
201 "nand read ${loadaddr} 2a0000 400000; " \ 201 "nand read ${loadaddr} 2a0000 400000; " \
202 "bootm ${loadaddr}\0" \ 202 "bootm ${loadaddr}\0" \
203 203
204 #define CONFIG_CMD_BOOTZ 204 #define CONFIG_CMD_BOOTZ
205 #define CONFIG_BOOTCOMMAND \ 205 #define CONFIG_BOOTCOMMAND \
206 "mmc dev ${mmcdev}; if mmc rescan; then " \ 206 "mmc dev ${mmcdev}; if mmc rescan; then " \
207 "if run loadbootscript; then " \ 207 "if run loadbootscript; then " \
208 "run bootscript; " \ 208 "run bootscript; " \
209 "else " \ 209 "else " \
210 "if run loaduimage; then " \ 210 "if run loaduimage; then " \
211 "run mmcboot; " \ 211 "run mmcboot; " \
212 "else run nandboot; " \ 212 "else run nandboot; " \
213 "fi; " \ 213 "fi; " \
214 "fi; " \ 214 "fi; " \
215 "else run nandboot; fi" 215 "else run nandboot; fi"
216 216
217 /* 217 /*
218 * Miscellaneous configurable options 218 * Miscellaneous configurable options
219 */ 219 */
220 #define CONFIG_AUTO_COMPLETE 220 #define CONFIG_AUTO_COMPLETE
221 #define CONFIG_CMDLINE_EDITING 221 #define CONFIG_CMDLINE_EDITING
222 #define CONFIG_TIMESTAMP 222 #define CONFIG_TIMESTAMP
223 #define CONFIG_SYS_AUTOLOAD "no" 223 #define CONFIG_SYS_AUTOLOAD "no"
224 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 224 #define CONFIG_SYS_LONGHELP /* undef to save memory */
225 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 225 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
226 #define CONFIG_SYS_PROMPT "CM-T3x # " 226 #define CONFIG_SYS_PROMPT "CM-T3x # "
227 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 227 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
228 /* Print Buffer Size */ 228 /* Print Buffer Size */
229 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 229 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
230 sizeof(CONFIG_SYS_PROMPT) + 16) 230 sizeof(CONFIG_SYS_PROMPT) + 16)
231 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 231 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
232 /* Boot Argument Buffer Size */ 232 /* Boot Argument Buffer Size */
233 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 233 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
234 234
235 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 235 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
236 /* works on */ 236 /* works on */
237 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 237 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
238 0x01F00000) /* 31MB */ 238 0x01F00000) /* 31MB */
239 239
240 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 240 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
241 /* load address */ 241 /* load address */
242 242
243 /* 243 /*
244 * OMAP3 has 12 GP timers, they can be driven by the system clock 244 * OMAP3 has 12 GP timers, they can be driven by the system clock
245 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 245 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
246 * This rate is divided by a local divisor. 246 * This rate is divided by a local divisor.
247 */ 247 */
248 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 248 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
249 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 249 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
250 250
251 /*----------------------------------------------------------------------- 251 /*-----------------------------------------------------------------------
252 * Physical Memory Map 252 * Physical Memory Map
253 */ 253 */
254 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 254 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
255 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 255 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
256 256
257 /*----------------------------------------------------------------------- 257 /*-----------------------------------------------------------------------
258 * FLASH and environment organization 258 * FLASH and environment organization
259 */ 259 */
260 260
261 /* **** PISMO SUPPORT *** */ 261 /* **** PISMO SUPPORT *** */
262 /* Monitor at start of flash */ 262 /* Monitor at start of flash */
263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
264 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 264 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
265 265
266 #define CONFIG_ENV_IS_IN_NAND 266 #define CONFIG_ENV_IS_IN_NAND
267 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 267 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
268 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 268 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
269 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 269 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
270 270
271 #if defined(CONFIG_CMD_NET) 271 #if defined(CONFIG_CMD_NET)
272 #define CONFIG_SMC911X 272 #define CONFIG_SMC911X
273 #define CONFIG_SMC911X_32_BIT 273 #define CONFIG_SMC911X_32_BIT
274 #define CM_T3X_SMC911X_BASE 0x2C000000 274 #define CM_T3X_SMC911X_BASE 0x2C000000
275 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 275 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
276 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 276 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
277 #endif /* (CONFIG_CMD_NET) */ 277 #endif /* (CONFIG_CMD_NET) */
278 278
279 /* additions for new relocation code, must be added to all boards */ 279 /* additions for new relocation code, must be added to all boards */
280 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 280 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
281 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 281 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
282 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 282 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
283 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 283 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
284 CONFIG_SYS_INIT_RAM_SIZE - \ 284 CONFIG_SYS_INIT_RAM_SIZE - \
285 GENERATED_GBL_DATA_SIZE) 285 GENERATED_GBL_DATA_SIZE)
286 286
287 /* Status LED */ 287 /* Status LED */
288 #define CONFIG_STATUS_LED /* Status LED enabled */ 288 #define CONFIG_STATUS_LED /* Status LED enabled */
289 #define CONFIG_BOARD_SPECIFIC_LED 289 #define CONFIG_BOARD_SPECIFIC_LED
290 #define CONFIG_GPIO_LED 290 #define CONFIG_GPIO_LED
291 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 291 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
292 #define GREEN_LED_DEV 0 292 #define GREEN_LED_DEV 0
293 #define STATUS_LED_BIT GREEN_LED_GPIO 293 #define STATUS_LED_BIT GREEN_LED_GPIO
294 #define STATUS_LED_STATE STATUS_LED_ON 294 #define STATUS_LED_STATE STATUS_LED_ON
295 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 295 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
296 #define STATUS_LED_BOOT GREEN_LED_DEV 296 #define STATUS_LED_BOOT GREEN_LED_DEV
297 297
298 #define CONFIG_SPLASHIMAGE_GUARD 298 #define CONFIG_SPLASHIMAGE_GUARD
299 299
300 /* GPIO banks */ 300 /* GPIO banks */
301 #ifdef CONFIG_STATUS_LED 301 #ifdef CONFIG_STATUS_LED
302 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 302 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
303 #endif 303 #endif
304 304
305 /* Display Configuration */ 305 /* Display Configuration */
306 #define CONFIG_OMAP3_GPIO_2 306 #define CONFIG_OMAP3_GPIO_2
307 #define CONFIG_OMAP3_GPIO_5 307 #define CONFIG_OMAP3_GPIO_5
308 #define CONFIG_VIDEO_OMAP3 308 #define CONFIG_VIDEO_OMAP3
309 #define LCD_BPP LCD_COLOR16 309 #define LCD_BPP LCD_COLOR16
310 310
311 #define CONFIG_LCD 311 #define CONFIG_LCD
312 #define CONFIG_SPLASH_SCREEN 312 #define CONFIG_SPLASH_SCREEN
313 #define CONFIG_SPLASH_SOURCE 313 #define CONFIG_SPLASH_SOURCE
314 #define CONFIG_CMD_BMP 314 #define CONFIG_CMD_BMP
315 #define CONFIG_BMP_16BPP 315 #define CONFIG_BMP_16BPP
316 #define CONFIG_SCF0403_LCD 316 #define CONFIG_SCF0403_LCD
317 317
318 #define CONFIG_OMAP3_SPI 318 #define CONFIG_OMAP3_SPI
319 319
320 /* Defines for SPL */ 320 /* Defines for SPL */
321 #define CONFIG_SPL_FRAMEWORK 321 #define CONFIG_SPL_FRAMEWORK
322 #define CONFIG_SPL_NAND_SIMPLE 322 #define CONFIG_SPL_NAND_SIMPLE
323 323
324 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 324 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
325 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 325 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
326 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 326 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
327 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 327 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
328 328
329 #define CONFIG_SPL_BOARD_INIT 329 #define CONFIG_SPL_BOARD_INIT
330 #define CONFIG_SPL_LIBCOMMON_SUPPORT 330 #define CONFIG_SPL_LIBCOMMON_SUPPORT
331 #define CONFIG_SPL_LIBDISK_SUPPORT 331 #define CONFIG_SPL_LIBDISK_SUPPORT
332 #define CONFIG_SPL_I2C_SUPPORT 332 #define CONFIG_SPL_I2C_SUPPORT
333 #define CONFIG_SPL_LIBGENERIC_SUPPORT 333 #define CONFIG_SPL_LIBGENERIC_SUPPORT
334 #define CONFIG_SPL_MMC_SUPPORT 334 #define CONFIG_SPL_MMC_SUPPORT
335 #define CONFIG_SPL_FAT_SUPPORT 335 #define CONFIG_SPL_FAT_SUPPORT
336 #define CONFIG_SPL_SERIAL_SUPPORT 336 #define CONFIG_SPL_SERIAL_SUPPORT
337 #define CONFIG_SPL_NAND_SUPPORT 337 #define CONFIG_SPL_NAND_SUPPORT
338 #define CONFIG_SPL_NAND_BASE 338 #define CONFIG_SPL_NAND_BASE
339 #define CONFIG_SPL_NAND_DRIVERS 339 #define CONFIG_SPL_NAND_DRIVERS
340 #define CONFIG_SPL_NAND_ECC 340 #define CONFIG_SPL_NAND_ECC
341 #define CONFIG_SPL_GPIO_SUPPORT 341 #define CONFIG_SPL_GPIO_SUPPORT
342 #define CONFIG_SPL_POWER_SUPPORT 342 #define CONFIG_SPL_POWER_SUPPORT
343 #define CONFIG_SPL_OMAP3_ID_NAND 343 #define CONFIG_SPL_OMAP3_ID_NAND
344 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 344 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
345 345
346 /* NAND boot config */ 346 /* NAND boot config */
347 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 347 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
348 #define CONFIG_SYS_NAND_PAGE_COUNT 64 348 #define CONFIG_SYS_NAND_PAGE_COUNT 64
349 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 349 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
350 #define CONFIG_SYS_NAND_OOBSIZE 64 350 #define CONFIG_SYS_NAND_OOBSIZE 64
351 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 351 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
352 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 352 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
353 /* 353 /*
354 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 354 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
355 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 355 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
356 */ 356 */
357 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 357 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
358 10, 11, 12 } 358 10, 11, 12 }
359 #define CONFIG_SYS_NAND_ECCSIZE 512 359 #define CONFIG_SYS_NAND_ECCSIZE 512
360 #define CONFIG_SYS_NAND_ECCBYTES 3 360 #define CONFIG_SYS_NAND_ECCBYTES 3
361 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 361 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
362 362
363 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 363 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
364 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 364 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
365 365
366 #define CONFIG_SPL_TEXT_BASE 0x40200800 366 #define CONFIG_SPL_TEXT_BASE 0x40200800
367 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 367 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
368 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
369 368
370 /* 369 /*
371 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 370 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
372 * older x-loader implementations. And move the BSS area so that it 371 * older x-loader implementations. And move the BSS area so that it
373 * doesn't overlap with TEXT_BASE. 372 * doesn't overlap with TEXT_BASE.
374 */ 373 */
375 #define CONFIG_SYS_TEXT_BASE 0x80008000 374 #define CONFIG_SYS_TEXT_BASE 0x80008000
376 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 375 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
377 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 376 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
378 377
379 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 378 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
380 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 379 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
381 380
382 #endif /* __CONFIG_H */ 381 #endif /* __CONFIG_H */
383 382
include/configs/devkit8000.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * (C) Copyright 2006-2008 2 * (C) Copyright 2006-2008
3 * Texas Instruments. 3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * 6 *
7 * (C) Copyright 2009 7 * (C) Copyright 2009
8 * Frederik Kriewitz <frederik@kriewitz.eu> 8 * Frederik Kriewitz <frederik@kriewitz.eu>
9 * 9 *
10 * Configuration settings for the DevKit8000 board. 10 * Configuration settings for the DevKit8000 board.
11 * 11 *
12 * SPDX-License-Identifier: GPL-2.0+ 12 * SPDX-License-Identifier: GPL-2.0+
13 */ 13 */
14 14
15 #ifndef __CONFIG_H 15 #ifndef __CONFIG_H
16 #define __CONFIG_H 16 #define __CONFIG_H
17 17
18 /* High Level Configuration Options */ 18 /* High Level Configuration Options */
19 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ 19 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
20 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 20 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
21 21
22 /* 22 /*
23 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 23 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
24 * 64 bytes before this address should be set aside for u-boot.img's 24 * 64 bytes before this address should be set aside for u-boot.img's
25 * header. That is 0x800FFFC0--0x80100000 should not be used for any 25 * header. That is 0x800FFFC0--0x80100000 should not be used for any
26 * other needs. 26 * other needs.
27 */ 27 */
28 #define CONFIG_SYS_TEXT_BASE 0x80100000 28 #define CONFIG_SYS_TEXT_BASE 0x80100000
29 29
30 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ 30 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
31 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 31 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
32 32
33 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 33 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
34 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 34 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
35 35
36 #define CONFIG_NAND 36 #define CONFIG_NAND
37 37
38 /* Physical Memory Map */ 38 /* Physical Memory Map */
39 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 39 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
40 40
41 #include <configs/ti_omap3_common.h> 41 #include <configs/ti_omap3_common.h>
42 42
43 /* Display CPU and Board information */ 43 /* Display CPU and Board information */
44 #define CONFIG_DISPLAY_CPUINFO 1 44 #define CONFIG_DISPLAY_CPUINFO 1
45 #define CONFIG_DISPLAY_BOARDINFO 1 45 #define CONFIG_DISPLAY_BOARDINFO 1
46 46
47 #define CONFIG_MISC_INIT_R 47 #define CONFIG_MISC_INIT_R
48 48
49 #define CONFIG_REVISION_TAG 1 49 #define CONFIG_REVISION_TAG 1
50 50
51 /* Size of malloc() pool */ 51 /* Size of malloc() pool */
52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
53 /* Sector */ 53 /* Sector */
54 #undef CONFIG_SYS_MALLOC_LEN 54 #undef CONFIG_SYS_MALLOC_LEN
55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
56 56
57 /* Hardware drivers */ 57 /* Hardware drivers */
58 /* DM9000 */ 58 /* DM9000 */
59 #define CONFIG_NET_RETRY_COUNT 20 59 #define CONFIG_NET_RETRY_COUNT 20
60 #define CONFIG_DRIVER_DM9000 1 60 #define CONFIG_DRIVER_DM9000 1
61 #define CONFIG_DM9000_BASE 0x2c000000 61 #define CONFIG_DM9000_BASE 0x2c000000
62 #define DM9000_IO CONFIG_DM9000_BASE 62 #define DM9000_IO CONFIG_DM9000_BASE
63 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 63 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
64 #define CONFIG_DM9000_USE_16BIT 1 64 #define CONFIG_DM9000_USE_16BIT 1
65 #define CONFIG_DM9000_NO_SROM 1 65 #define CONFIG_DM9000_NO_SROM 1
66 #undef CONFIG_DM9000_DEBUG 66 #undef CONFIG_DM9000_DEBUG
67 67
68 /* SPI */ 68 /* SPI */
69 #undef CONFIG_SPI 69 #undef CONFIG_SPI
70 #undef CONFIG_OMAP3_SPI 70 #undef CONFIG_OMAP3_SPI
71 71
72 /* I2C */ 72 /* I2C */
73 #undef CONFIG_SYS_I2C_OMAP24XX 73 #undef CONFIG_SYS_I2C_OMAP24XX
74 #define CONFIG_SYS_I2C_OMAP34XX 74 #define CONFIG_SYS_I2C_OMAP34XX
75 75
76 /* TWL4030 */ 76 /* TWL4030 */
77 #define CONFIG_TWL4030_LED 1 77 #define CONFIG_TWL4030_LED 1
78 78
79 /* Board NAND Info */ 79 /* Board NAND Info */
80 #define MTDIDS_DEFAULT "nand0=nand" 80 #define MTDIDS_DEFAULT "nand0=nand"
81 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 81 #define MTDPARTS_DEFAULT "mtdparts=nand:" \
82 "512k(x-loader)," \ 82 "512k(x-loader)," \
83 "1920k(u-boot)," \ 83 "1920k(u-boot)," \
84 "128k(u-boot-env)," \ 84 "128k(u-boot-env)," \
85 "4m(kernel)," \ 85 "4m(kernel)," \
86 "-(fs)" 86 "-(fs)"
87 87
88 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 88 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
89 /* to access nand */ 89 /* to access nand */
90 #define CONFIG_JFFS2_NAND 90 #define CONFIG_JFFS2_NAND
91 /* nand device jffs2 lives on */ 91 /* nand device jffs2 lives on */
92 #define CONFIG_JFFS2_DEV "nand0" 92 #define CONFIG_JFFS2_DEV "nand0"
93 /* start of jffs2 partition */ 93 /* start of jffs2 partition */
94 #define CONFIG_JFFS2_PART_OFFSET 0x680000 94 #define CONFIG_JFFS2_PART_OFFSET 0x680000
95 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 95 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
96 /* partition */ 96 /* partition */
97 97
98 /* commands to include */ 98 /* commands to include */
99 #define CONFIG_CMD_DHCP /* DHCP support */ 99 #define CONFIG_CMD_DHCP /* DHCP support */
100 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 100 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
101 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 101 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
102 102
103 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 103 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
104 #undef CONFIG_CMD_IMI /* iminfo */ 104 #undef CONFIG_CMD_IMI /* iminfo */
105 #undef CONFIG_CMD_SPI 105 #undef CONFIG_CMD_SPI
106 #undef CONFIG_CMD_GPIO 106 #undef CONFIG_CMD_GPIO
107 #undef CONFIG_CMD_ASKENV 107 #undef CONFIG_CMD_ASKENV
108 #undef CONFIG_CMD_BOOTZ 108 #undef CONFIG_CMD_BOOTZ
109 #undef CONFIG_SUPPORT_RAW_INITRD 109 #undef CONFIG_SUPPORT_RAW_INITRD
110 #undef CONFIG_FAT_WRITE 110 #undef CONFIG_FAT_WRITE
111 #undef CONFIG_CMD_EXT4 111 #undef CONFIG_CMD_EXT4
112 #undef CONFIG_CMD_FS_GENERIC 112 #undef CONFIG_CMD_FS_GENERIC
113 113
114 /* BOOTP/DHCP options */ 114 /* BOOTP/DHCP options */
115 #define CONFIG_BOOTP_SUBNETMASK 115 #define CONFIG_BOOTP_SUBNETMASK
116 #define CONFIG_BOOTP_GATEWAY 116 #define CONFIG_BOOTP_GATEWAY
117 #define CONFIG_BOOTP_HOSTNAME 117 #define CONFIG_BOOTP_HOSTNAME
118 #define CONFIG_BOOTP_NISDOMAIN 118 #define CONFIG_BOOTP_NISDOMAIN
119 #define CONFIG_BOOTP_BOOTPATH 119 #define CONFIG_BOOTP_BOOTPATH
120 #define CONFIG_BOOTP_BOOTFILESIZE 120 #define CONFIG_BOOTP_BOOTFILESIZE
121 #define CONFIG_BOOTP_DNS 121 #define CONFIG_BOOTP_DNS
122 #define CONFIG_BOOTP_DNS2 122 #define CONFIG_BOOTP_DNS2
123 #define CONFIG_BOOTP_SEND_HOSTNAME 123 #define CONFIG_BOOTP_SEND_HOSTNAME
124 #define CONFIG_BOOTP_NTPSERVER 124 #define CONFIG_BOOTP_NTPSERVER
125 #define CONFIG_BOOTP_TIMEOFFSET 125 #define CONFIG_BOOTP_TIMEOFFSET
126 #undef CONFIG_BOOTP_VENDOREX 126 #undef CONFIG_BOOTP_VENDOREX
127 127
128 /* Environment information */ 128 /* Environment information */
129 #define CONFIG_EXTRA_ENV_SETTINGS \ 129 #define CONFIG_EXTRA_ENV_SETTINGS \
130 "loadaddr=0x82000000\0" \ 130 "loadaddr=0x82000000\0" \
131 "console=ttyO2,115200n8\0" \ 131 "console=ttyO2,115200n8\0" \
132 "mmcdev=0\0" \ 132 "mmcdev=0\0" \
133 "vram=12M\0" \ 133 "vram=12M\0" \
134 "dvimode=1024x768MR-16@60\0" \ 134 "dvimode=1024x768MR-16@60\0" \
135 "defaultdisplay=dvi\0" \ 135 "defaultdisplay=dvi\0" \
136 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 136 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
137 "kernelopts=rw\0" \ 137 "kernelopts=rw\0" \
138 "commonargs=" \ 138 "commonargs=" \
139 "setenv bootargs console=${console} " \ 139 "setenv bootargs console=${console} " \
140 "vram=${vram} " \ 140 "vram=${vram} " \
141 "omapfb.mode=dvi:${dvimode} " \ 141 "omapfb.mode=dvi:${dvimode} " \
142 "omapdss.def_disp=${defaultdisplay}\0" \ 142 "omapdss.def_disp=${defaultdisplay}\0" \
143 "mmcargs=" \ 143 "mmcargs=" \
144 "run commonargs; " \ 144 "run commonargs; " \
145 "setenv bootargs ${bootargs} " \ 145 "setenv bootargs ${bootargs} " \
146 "root=/dev/mmcblk0p2 " \ 146 "root=/dev/mmcblk0p2 " \
147 "rootwait " \ 147 "rootwait " \
148 "${kernelopts}\0" \ 148 "${kernelopts}\0" \
149 "nandargs=" \ 149 "nandargs=" \
150 "run commonargs; " \ 150 "run commonargs; " \
151 "setenv bootargs ${bootargs} " \ 151 "setenv bootargs ${bootargs} " \
152 "omapfb.mode=dvi:${dvimode} " \ 152 "omapfb.mode=dvi:${dvimode} " \
153 "omapdss.def_disp=${defaultdisplay} " \ 153 "omapdss.def_disp=${defaultdisplay} " \
154 "root=/dev/mtdblock4 " \ 154 "root=/dev/mtdblock4 " \
155 "rootfstype=jffs2 " \ 155 "rootfstype=jffs2 " \
156 "${kernelopts}\0" \ 156 "${kernelopts}\0" \
157 "netargs=" \ 157 "netargs=" \
158 "run commonargs; " \ 158 "run commonargs; " \
159 "setenv bootargs ${bootargs} " \ 159 "setenv bootargs ${bootargs} " \
160 "root=/dev/nfs " \ 160 "root=/dev/nfs " \
161 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 161 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
162 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 162 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
163 "${kernelopts} " \ 163 "${kernelopts} " \
164 "dnsip1=${dnsip} " \ 164 "dnsip1=${dnsip} " \
165 "dnsip2=${dnsip2}\0" \ 165 "dnsip2=${dnsip2}\0" \
166 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 166 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
167 "bootscript=echo Running bootscript from mmc ...; " \ 167 "bootscript=echo Running bootscript from mmc ...; " \
168 "source ${loadaddr}\0" \ 168 "source ${loadaddr}\0" \
169 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 169 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
170 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 170 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
171 "mmcboot=echo Booting from mmc ...; " \ 171 "mmcboot=echo Booting from mmc ...; " \
172 "run mmcargs; " \ 172 "run mmcargs; " \
173 "bootm ${loadaddr}\0" \ 173 "bootm ${loadaddr}\0" \
174 "nandboot=echo Booting from nand ...; " \ 174 "nandboot=echo Booting from nand ...; " \
175 "run nandargs; " \ 175 "run nandargs; " \
176 "nand read ${loadaddr} 280000 400000; " \ 176 "nand read ${loadaddr} 280000 400000; " \
177 "bootm ${loadaddr}\0" \ 177 "bootm ${loadaddr}\0" \
178 "netboot=echo Booting from network ...; " \ 178 "netboot=echo Booting from network ...; " \
179 "dhcp ${loadaddr}; " \ 179 "dhcp ${loadaddr}; " \
180 "run netargs; " \ 180 "run netargs; " \
181 "bootm ${loadaddr}\0" \ 181 "bootm ${loadaddr}\0" \
182 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 182 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
183 "if run loadbootscript; then " \ 183 "if run loadbootscript; then " \
184 "run bootscript; " \ 184 "run bootscript; " \
185 "else " \ 185 "else " \
186 "if run loaduimage; then " \ 186 "if run loaduimage; then " \
187 "run mmcboot; " \ 187 "run mmcboot; " \
188 "else run nandboot; " \ 188 "else run nandboot; " \
189 "fi; " \ 189 "fi; " \
190 "fi; " \ 190 "fi; " \
191 "else run nandboot; fi\0" 191 "else run nandboot; fi\0"
192 192
193 193
194 #define CONFIG_BOOTCOMMAND "run autoboot" 194 #define CONFIG_BOOTCOMMAND "run autoboot"
195 195
196 /* Boot Argument Buffer Size */ 196 /* Boot Argument Buffer Size */
197 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 197 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
198 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 198 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
199 0x01000000) /* 16MB */ 199 0x01000000) /* 16MB */
200 200
201 /* NAND and environment organization */ 201 /* NAND and environment organization */
202 #define CONFIG_ENV_IS_IN_NAND 1 202 #define CONFIG_ENV_IS_IN_NAND 1
203 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 203 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
204 204
205 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 205 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
206 206
207 /* SRAM config */ 207 /* SRAM config */
208 #define CONFIG_SYS_SRAM_START 0x40200000 208 #define CONFIG_SYS_SRAM_START 0x40200000
209 #define CONFIG_SYS_SRAM_SIZE 0x10000 209 #define CONFIG_SYS_SRAM_SIZE 0x10000
210 210
211 /* Defines for SPL */ 211 /* Defines for SPL */
212 #undef CONFIG_SPL_MTD_SUPPORT 212 #undef CONFIG_SPL_MTD_SUPPORT
213 213
214 #undef CONFIG_SPL_TEXT_BASE 214 #undef CONFIG_SPL_TEXT_BASE
215 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 215 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
216 #undef CONFIG_SPL_STACK
217 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
218 216
219 /* NAND boot config */ 217 /* NAND boot config */
220 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 218 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
221 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 219 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
222 #define CONFIG_SYS_NAND_PAGE_COUNT 64 220 #define CONFIG_SYS_NAND_PAGE_COUNT 64
223 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 221 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
224 #define CONFIG_SYS_NAND_OOBSIZE 64 222 #define CONFIG_SYS_NAND_OOBSIZE 64
225 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 223 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
226 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 224 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
227 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 225 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
228 10, 11, 12, 13} 226 10, 11, 12, 13}
229 227
230 #define CONFIG_SYS_NAND_ECCSIZE 512 228 #define CONFIG_SYS_NAND_ECCSIZE 512
231 #define CONFIG_SYS_NAND_ECCBYTES 3 229 #define CONFIG_SYS_NAND_ECCBYTES 3
232 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 230 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
233 231
234 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 232 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
235 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 233 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
236 234
237 /* SPL OS boot options */ 235 /* SPL OS boot options */
238 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ 236 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
239 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 237 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
240 0x400000) 238 0x400000)
241 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 239 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
242 240
243 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 241 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
244 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 242 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
245 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 243 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
246 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ 244 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
247 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ 245 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
248 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ 246 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
249 247
250 #undef CONFIG_SYS_SPL_ARGS_ADDR 248 #undef CONFIG_SYS_SPL_ARGS_ADDR
251 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) 249 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
252 250
253 #endif /* __CONFIG_H */ 251 #endif /* __CONFIG_H */
254 252
include/configs/omap3_evm_common.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * Common configuration settings for the TI OMAP3 EVM board. 2 * Common configuration settings for the TI OMAP3 EVM board.
3 * 3 *
4 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef __OMAP3_EVM_COMMON_H 9 #ifndef __OMAP3_EVM_COMMON_H
10 #define __OMAP3_EVM_COMMON_H 10 #define __OMAP3_EVM_COMMON_H
11 11
12 /* 12 /*
13 * High level configuration options 13 * High level configuration options
14 */ 14 */
15 #define CONFIG_OMAP /* This is TI OMAP core */ 15 #define CONFIG_OMAP /* This is TI OMAP core */
16 #define CONFIG_OMAP_GPIO 16 #define CONFIG_OMAP_GPIO
17 #define CONFIG_OMAP_COMMON 17 #define CONFIG_OMAP_COMMON
18 18
19 #define CONFIG_SDRC /* The chip has SDRC controller */ 19 #define CONFIG_SDRC /* The chip has SDRC controller */
20 20
21 #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ 21 #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
22 #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */ 22 #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
23 23
24 /* 24 /*
25 * Clock related definitions 25 * Clock related definitions
26 */ 26 */
27 #define V_OSCK 26000000 /* Clock output from T2 */ 27 #define V_OSCK 26000000 /* Clock output from T2 */
28 #define V_SCLK (V_OSCK >> 1) 28 #define V_SCLK (V_OSCK >> 1)
29 29
30 /* 30 /*
31 * OMAP3 has 12 GP timers, they can be driven by the system clock 31 * OMAP3 has 12 GP timers, they can be driven by the system clock
32 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 32 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
33 * This rate is divided by a local divisor. 33 * This rate is divided by a local divisor.
34 */ 34 */
35 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 35 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
36 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 36 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
37 37
38 /* Size of environment - 128KB */ 38 /* Size of environment - 128KB */
39 #define CONFIG_ENV_SIZE (128 << 10) 39 #define CONFIG_ENV_SIZE (128 << 10)
40 40
41 /* Size of malloc pool */ 41 /* Size of malloc pool */
42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
43 43
44 /* 44 /*
45 * Physical Memory Map 45 * Physical Memory Map
46 * Note 1: CS1 may or may not be populated 46 * Note 1: CS1 may or may not be populated
47 * Note 2: SDRAM size is expected to be at least 32MB 47 * Note 2: SDRAM size is expected to be at least 32MB
48 */ 48 */
49 #define CONFIG_NR_DRAM_BANKS 2 49 #define CONFIG_NR_DRAM_BANKS 2
50 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 50 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
51 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 51 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
52 52
53 /* Limits for memtest */ 53 /* Limits for memtest */
54 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 54 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
55 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 55 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
56 0x01F00000) /* 31MB */ 56 0x01F00000) /* 31MB */
57 57
58 /* Default load address */ 58 /* Default load address */
59 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) 59 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
60 60
61 /* ----------------------------------------------------------------------------- 61 /* -----------------------------------------------------------------------------
62 * Hardware drivers 62 * Hardware drivers
63 * ----------------------------------------------------------------------------- 63 * -----------------------------------------------------------------------------
64 */ 64 */
65 65
66 /* 66 /*
67 * NS16550 Configuration 67 * NS16550 Configuration
68 */ 68 */
69 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
70 70
71 #define CONFIG_SYS_NS16550 71 #define CONFIG_SYS_NS16550
72 #define CONFIG_SYS_NS16550_SERIAL 72 #define CONFIG_SYS_NS16550_SERIAL
73 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 73 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
74 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 74 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
75 75
76 /* 76 /*
77 * select serial console configuration 77 * select serial console configuration
78 */ 78 */
79 #define CONFIG_CONS_INDEX 1 79 #define CONFIG_CONS_INDEX 1
80 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ 80 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
81 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 81 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
82 #define CONFIG_BAUDRATE 115200 82 #define CONFIG_BAUDRATE 115200
83 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 83 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
84 115200} 84 115200}
85 85
86 /* 86 /*
87 * I2C 87 * I2C
88 */ 88 */
89 #define CONFIG_SYS_I2C 89 #define CONFIG_SYS_I2C
90 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 90 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
91 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 91 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
92 #define CONFIG_SYS_I2C_OMAP34XX 92 #define CONFIG_SYS_I2C_OMAP34XX
93 93
94 /* 94 /*
95 * PISMO support 95 * PISMO support
96 */ 96 */
97 /* Monitor at start of flash - Reserve 2 sectors */ 97 /* Monitor at start of flash - Reserve 2 sectors */
98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
99 99
100 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 100 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
101 101
102 /* Start location & size of environment */ 102 /* Start location & size of environment */
103 #define ONENAND_ENV_OFFSET 0x260000 103 #define ONENAND_ENV_OFFSET 0x260000
104 #define SMNAND_ENV_OFFSET 0x260000 104 #define SMNAND_ENV_OFFSET 0x260000
105 105
106 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 106 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
107 107
108 /* 108 /*
109 * NAND 109 * NAND
110 */ 110 */
111 /* Physical address to access NAND */ 111 /* Physical address to access NAND */
112 #define CONFIG_SYS_NAND_ADDR NAND_BASE 112 #define CONFIG_SYS_NAND_ADDR NAND_BASE
113 113
114 /* Physical address to access NAND at CS0 */ 114 /* Physical address to access NAND at CS0 */
115 #define CONFIG_SYS_NAND_BASE NAND_BASE 115 #define CONFIG_SYS_NAND_BASE NAND_BASE
116 116
117 /* Max number of NAND devices */ 117 /* Max number of NAND devices */
118 #define CONFIG_SYS_MAX_NAND_DEVICE 1 118 #define CONFIG_SYS_MAX_NAND_DEVICE 1
119 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 119 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
120 /* Timeout values (in ticks) */ 120 /* Timeout values (in ticks) */
121 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 121 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
122 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 122 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
123 123
124 /* Flash banks JFFS2 should use */ 124 /* Flash banks JFFS2 should use */
125 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 125 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
126 CONFIG_SYS_MAX_NAND_DEVICE) 126 CONFIG_SYS_MAX_NAND_DEVICE)
127 127
128 #define CONFIG_SYS_JFFS2_MEM_NAND 128 #define CONFIG_SYS_JFFS2_MEM_NAND
129 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 129 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
130 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 130 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
131 131
132 #define CONFIG_JFFS2_NAND 132 #define CONFIG_JFFS2_NAND
133 /* nand device jffs2 lives on */ 133 /* nand device jffs2 lives on */
134 #define CONFIG_JFFS2_DEV "nand0" 134 #define CONFIG_JFFS2_DEV "nand0"
135 /* Start of jffs2 partition */ 135 /* Start of jffs2 partition */
136 #define CONFIG_JFFS2_PART_OFFSET 0x680000 136 #define CONFIG_JFFS2_PART_OFFSET 0x680000
137 /* Size of jffs2 partition */ 137 /* Size of jffs2 partition */
138 #define CONFIG_JFFS2_PART_SIZE 0xf980000 138 #define CONFIG_JFFS2_PART_SIZE 0xf980000
139 139
140 /* 140 /*
141 * USB 141 * USB
142 */ 142 */
143 #ifdef CONFIG_USB_OMAP3 143 #ifdef CONFIG_USB_OMAP3
144 144
145 #ifdef CONFIG_MUSB_HCD 145 #ifdef CONFIG_MUSB_HCD
146 #define CONFIG_CMD_USB 146 #define CONFIG_CMD_USB
147 147
148 #define CONFIG_USB_STORAGE 148 #define CONFIG_USB_STORAGE
149 #define CONGIG_CMD_STORAGE 149 #define CONGIG_CMD_STORAGE
150 #define CONFIG_CMD_FAT 150 #define CONFIG_CMD_FAT
151 151
152 #ifdef CONFIG_USB_KEYBOARD 152 #ifdef CONFIG_USB_KEYBOARD
153 #define CONFIG_SYS_USB_EVENT_POLL 153 #define CONFIG_SYS_USB_EVENT_POLL
154 #define CONFIG_PREBOOT "usb start" 154 #define CONFIG_PREBOOT "usb start"
155 #endif /* CONFIG_USB_KEYBOARD */ 155 #endif /* CONFIG_USB_KEYBOARD */
156 156
157 #endif /* CONFIG_MUSB_HCD */ 157 #endif /* CONFIG_MUSB_HCD */
158 158
159 #ifdef CONFIG_MUSB_UDC 159 #ifdef CONFIG_MUSB_UDC
160 /* USB device configuration */ 160 /* USB device configuration */
161 #define CONFIG_USB_DEVICE 161 #define CONFIG_USB_DEVICE
162 #define CONFIG_USB_TTY 162 #define CONFIG_USB_TTY
163 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 163 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
164 164
165 /* Change these to suit your needs */ 165 /* Change these to suit your needs */
166 #define CONFIG_USBD_VENDORID 0x0451 166 #define CONFIG_USBD_VENDORID 0x0451
167 #define CONFIG_USBD_PRODUCTID 0x5678 167 #define CONFIG_USBD_PRODUCTID 0x5678
168 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 168 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
169 #define CONFIG_USBD_PRODUCT_NAME "EVM" 169 #define CONFIG_USBD_PRODUCT_NAME "EVM"
170 #endif /* CONFIG_MUSB_UDC */ 170 #endif /* CONFIG_MUSB_UDC */
171 171
172 #endif /* CONFIG_USB_OMAP3 */ 172 #endif /* CONFIG_USB_OMAP3 */
173 173
174 /* ---------------------------------------------------------------------------- 174 /* ----------------------------------------------------------------------------
175 * U-boot features 175 * U-boot features
176 * ---------------------------------------------------------------------------- 176 * ----------------------------------------------------------------------------
177 */ 177 */
178 #define CONFIG_SYS_PROMPT "OMAP3_EVM # " 178 #define CONFIG_SYS_PROMPT "OMAP3_EVM # "
179 #define CONFIG_SYS_MAXARGS 16 /* max args for a command */ 179 #define CONFIG_SYS_MAXARGS 16 /* max args for a command */
180 180
181 #define CONFIG_MISC_INIT_R 181 #define CONFIG_MISC_INIT_R
182 182
183 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 183 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
184 #define CONFIG_SETUP_MEMORY_TAGS 184 #define CONFIG_SETUP_MEMORY_TAGS
185 #define CONFIG_INITRD_TAG 185 #define CONFIG_INITRD_TAG
186 #define CONFIG_REVISION_TAG 186 #define CONFIG_REVISION_TAG
187 187
188 /* Size of Console IO buffer */ 188 /* Size of Console IO buffer */
189 #define CONFIG_SYS_CBSIZE 512 189 #define CONFIG_SYS_CBSIZE 512
190 190
191 /* Size of print buffer */ 191 /* Size of print buffer */
192 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 192 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
193 sizeof(CONFIG_SYS_PROMPT) + 16) 193 sizeof(CONFIG_SYS_PROMPT) + 16)
194 194
195 /* Size of bootarg buffer */ 195 /* Size of bootarg buffer */
196 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 196 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
197 197
198 #define CONFIG_BOOTFILE "uImage" 198 #define CONFIG_BOOTFILE "uImage"
199 199
200 /* 200 /*
201 * NAND / OneNAND 201 * NAND / OneNAND
202 */ 202 */
203 #if defined(CONFIG_CMD_NAND) 203 #if defined(CONFIG_CMD_NAND)
204 #define CONFIG_SYS_FLASH_BASE NAND_BASE 204 #define CONFIG_SYS_FLASH_BASE NAND_BASE
205 205
206 #define CONFIG_NAND_OMAP_GPMC 206 #define CONFIG_NAND_OMAP_GPMC
207 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 207 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
208 #elif defined(CONFIG_CMD_ONENAND) 208 #elif defined(CONFIG_CMD_ONENAND)
209 #define CONFIG_SYS_FLASH_BASE ONENAND_MAP 209 #define CONFIG_SYS_FLASH_BASE ONENAND_MAP
210 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 210 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
211 #endif 211 #endif
212 212
213 #if !defined(CONFIG_ENV_IS_NOWHERE) 213 #if !defined(CONFIG_ENV_IS_NOWHERE)
214 #if defined(CONFIG_CMD_NAND) 214 #if defined(CONFIG_CMD_NAND)
215 #define CONFIG_ENV_IS_IN_NAND 215 #define CONFIG_ENV_IS_IN_NAND
216 #elif defined(CONFIG_CMD_ONENAND) 216 #elif defined(CONFIG_CMD_ONENAND)
217 #define CONFIG_ENV_IS_IN_ONENAND 217 #define CONFIG_ENV_IS_IN_ONENAND
218 #define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET 218 #define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
219 #endif 219 #endif
220 #endif /* CONFIG_ENV_IS_NOWHERE */ 220 #endif /* CONFIG_ENV_IS_NOWHERE */
221 221
222 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 222 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
223 223
224 #if defined(CONFIG_CMD_NET) 224 #if defined(CONFIG_CMD_NET)
225 225
226 /* Ethernet (SMSC9115 from SMSC9118 family) */ 226 /* Ethernet (SMSC9115 from SMSC9118 family) */
227 #define CONFIG_SMC911X 227 #define CONFIG_SMC911X
228 #define CONFIG_SMC911X_32_BIT 228 #define CONFIG_SMC911X_32_BIT
229 #define CONFIG_SMC911X_BASE 0x2C000000 229 #define CONFIG_SMC911X_BASE 0x2C000000
230 230
231 /* BOOTP fields */ 231 /* BOOTP fields */
232 #define CONFIG_BOOTP_SUBNETMASK 0x00000001 232 #define CONFIG_BOOTP_SUBNETMASK 0x00000001
233 #define CONFIG_BOOTP_GATEWAY 0x00000002 233 #define CONFIG_BOOTP_GATEWAY 0x00000002
234 #define CONFIG_BOOTP_HOSTNAME 0x00000004 234 #define CONFIG_BOOTP_HOSTNAME 0x00000004
235 #define CONFIG_BOOTP_BOOTPATH 0x00000010 235 #define CONFIG_BOOTP_BOOTPATH 0x00000010
236 236
237 #endif /* CONFIG_CMD_NET */ 237 #endif /* CONFIG_CMD_NET */
238 238
239 /* Support for relocation */ 239 /* Support for relocation */
240 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 240 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
241 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 241 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
242 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 242 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
243 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 243 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
244 CONFIG_SYS_INIT_RAM_SIZE - \ 244 CONFIG_SYS_INIT_RAM_SIZE - \
245 GENERATED_GBL_DATA_SIZE) 245 GENERATED_GBL_DATA_SIZE)
246 246
247 /* ----------------------------------------------------------------------------- 247 /* -----------------------------------------------------------------------------
248 * Board specific 248 * Board specific
249 * ----------------------------------------------------------------------------- 249 * -----------------------------------------------------------------------------
250 */ 250 */
251 #define CONFIG_SYS_NO_FLASH 251 #define CONFIG_SYS_NO_FLASH
252 252
253 /* Uncomment to define the board revision statically */ 253 /* Uncomment to define the board revision statically */
254 /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ 254 /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
255 255
256 #define CONFIG_SYS_CACHELINE_SIZE 64 256 #define CONFIG_SYS_CACHELINE_SIZE 64
257 257
258 /* Defines for SPL */ 258 /* Defines for SPL */
259 #define CONFIG_SPL_FRAMEWORK 259 #define CONFIG_SPL_FRAMEWORK
260 #define CONFIG_SPL_TEXT_BASE 0x40200800 260 #define CONFIG_SPL_TEXT_BASE 0x40200800
261 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 261 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
262 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
263 262
264 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 263 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
265 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 264 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
266 265
267 #define CONFIG_SPL_BOARD_INIT 266 #define CONFIG_SPL_BOARD_INIT
268 #define CONFIG_SPL_LIBCOMMON_SUPPORT 267 #define CONFIG_SPL_LIBCOMMON_SUPPORT
269 #define CONFIG_SPL_LIBDISK_SUPPORT 268 #define CONFIG_SPL_LIBDISK_SUPPORT
270 #define CONFIG_SPL_I2C_SUPPORT 269 #define CONFIG_SPL_I2C_SUPPORT
271 #define CONFIG_SPL_LIBGENERIC_SUPPORT 270 #define CONFIG_SPL_LIBGENERIC_SUPPORT
272 #define CONFIG_SPL_SERIAL_SUPPORT 271 #define CONFIG_SPL_SERIAL_SUPPORT
273 #define CONFIG_SPL_POWER_SUPPORT 272 #define CONFIG_SPL_POWER_SUPPORT
274 #define CONFIG_SPL_OMAP3_ID_NAND 273 #define CONFIG_SPL_OMAP3_ID_NAND
275 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 274 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
276 275
277 /* 276 /*
278 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 277 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
279 * 64 bytes before this address should be set aside for u-boot.img's 278 * 64 bytes before this address should be set aside for u-boot.img's
280 * header. That is 0x800FFFC0--0x80100000 should not be used for any 279 * header. That is 0x800FFFC0--0x80100000 should not be used for any
281 * other needs. 280 * other needs.
282 */ 281 */
283 #define CONFIG_SYS_TEXT_BASE 0x80100000 282 #define CONFIG_SYS_TEXT_BASE 0x80100000
284 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 283 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
285 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 284 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
286 285
287 #endif /* __OMAP3_EVM_COMMON_H */ 286 #endif /* __OMAP3_EVM_COMMON_H */
288 287
include/configs/siemens-am33x-common.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * siemens am33x common board options 2 * siemens am33x common board options
3 * (C) Copyright 2013 Siemens Schweiz AG 3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * 5 *
6 * Based on: 6 * Based on:
7 * U-Boot file:/include/configs/am335x_evm.h 7 * U-Boot file:/include/configs/am335x_evm.h
8 * 8 *
9 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 9 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
10 * 10 *
11 * SPDX-License-Identifier: GPL-2.0+ 11 * SPDX-License-Identifier: GPL-2.0+
12 */ 12 */
13 13
14 #ifndef __CONFIG_SIEMENS_AM33X_COMMON_H 14 #ifndef __CONFIG_SIEMENS_AM33X_COMMON_H
15 #define __CONFIG_SIEMENS_AM33X_COMMON_H 15 #define __CONFIG_SIEMENS_AM33X_COMMON_H
16 16
17 #define CONFIG_AM33XX 17 #define CONFIG_AM33XX
18 #define CONFIG_OMAP 18 #define CONFIG_OMAP
19 #define CONFIG_OMAP_COMMON 19 #define CONFIG_OMAP_COMMON
20 20
21 #include <asm/arch/omap.h> 21 #include <asm/arch/omap.h>
22 22
23 #define CONFIG_DMA_COHERENT 23 #define CONFIG_DMA_COHERENT
24 #define CONFIG_DMA_COHERENT_SIZE (1 << 20) 24 #define CONFIG_DMA_COHERENT_SIZE (1 << 20)
25 25
26 #define CONFIG_ENV_SIZE (0x2000) 26 #define CONFIG_ENV_SIZE (0x2000)
27 #define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) 27 #define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
28 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 28 #define CONFIG_SYS_LONGHELP /* undef to save memory */
29 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 29 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
30 #define CONFIG_SYS_PROMPT "U-Boot# " 30 #define CONFIG_SYS_PROMPT "U-Boot# "
31 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 31 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
32 #define CONFIG_BOARD_LATE_INIT 32 #define CONFIG_BOARD_LATE_INIT
33 #define CONFIG_SYS_NO_FLASH 33 #define CONFIG_SYS_NO_FLASH
34 #define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE 34 #define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE
35 35
36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
37 #define CONFIG_SETUP_MEMORY_TAGS 37 #define CONFIG_SETUP_MEMORY_TAGS
38 #define CONFIG_INITRD_TAG 38 #define CONFIG_INITRD_TAG
39 39
40 #define CONFIG_SYS_CACHELINE_SIZE 64 40 #define CONFIG_SYS_CACHELINE_SIZE 64
41 41
42 /* commands to include */ 42 /* commands to include */
43 #include <config_cmd_default.h> 43 #include <config_cmd_default.h>
44 44
45 #define CONFIG_CMD_ASKENV 45 #define CONFIG_CMD_ASKENV
46 #define CONFIG_CMD_ECHO 46 #define CONFIG_CMD_ECHO
47 #define CONFIG_CMD_CACHE 47 #define CONFIG_CMD_CACHE
48 48
49 #define CONFIG_SYS_GENERIC_BOARD 49 #define CONFIG_SYS_GENERIC_BOARD
50 50
51 #define CONFIG_ENV_VARS_UBOOT_CONFIG 51 #define CONFIG_ENV_VARS_UBOOT_CONFIG
52 #ifndef CONFIG_SPL_BUILD 52 #ifndef CONFIG_SPL_BUILD
53 #define CONFIG_ROOTPATH "/opt/eldk" 53 #define CONFIG_ROOTPATH "/opt/eldk"
54 #endif 54 #endif
55 55
56 #define CONFIG_ENV_OVERWRITE 1 56 #define CONFIG_ENV_OVERWRITE 1
57 #define CONFIG_ENV_IS_NOWHERE 57 #define CONFIG_ENV_IS_NOWHERE
58 58
59 #define CONFIG_SYS_LONGHELP 59 #define CONFIG_SYS_LONGHELP
60 #define CONFIG_CMDLINE_EDITING 60 #define CONFIG_CMDLINE_EDITING
61 #define CONFIG_AUTO_COMPLETE 61 #define CONFIG_AUTO_COMPLETE
62 #define CONFIG_SYS_AUTOLOAD "yes" 62 #define CONFIG_SYS_AUTOLOAD "yes"
63 63
64 /* Clock Defines */ 64 /* Clock Defines */
65 #define V_OSCK 24000000 /* Clock output from T2 */ 65 #define V_OSCK 24000000 /* Clock output from T2 */
66 #define V_SCLK (V_OSCK) 66 #define V_SCLK (V_OSCK)
67 67
68 /* We set the max number of command args high to avoid HUSH bugs. */ 68 /* We set the max number of command args high to avoid HUSH bugs. */
69 #define CONFIG_SYS_MAXARGS 32 69 #define CONFIG_SYS_MAXARGS 32
70 70
71 /* Console I/O Buffer Size */ 71 /* Console I/O Buffer Size */
72 #define CONFIG_SYS_CBSIZE 512 72 #define CONFIG_SYS_CBSIZE 512
73 73
74 /* Print Buffer Size */ 74 /* Print Buffer Size */
75 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 75 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
76 + sizeof(CONFIG_SYS_PROMPT) + 16) 76 + sizeof(CONFIG_SYS_PROMPT) + 16)
77 77
78 /* Boot Argument Buffer Size */ 78 /* Boot Argument Buffer Size */
79 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 79 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
80 80
81 /* 81 /*
82 * memtest works on 8 MB in DRAM after skipping 32MB from 82 * memtest works on 8 MB in DRAM after skipping 32MB from
83 * start addr of ram disk 83 * start addr of ram disk
84 */ 84 */
85 #define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) 85 #define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
86 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ 86 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
87 + (8 * 1024 * 1024)) 87 + (8 * 1024 * 1024))
88 88
89 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ 89 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
90 90
91 #define CONFIG_MMC 91 #define CONFIG_MMC
92 #define CONFIG_GENERIC_MMC 92 #define CONFIG_GENERIC_MMC
93 #define CONFIG_OMAP_HSMMC 93 #define CONFIG_OMAP_HSMMC
94 #define CONFIG_CMD_MMC 94 #define CONFIG_CMD_MMC
95 #define CONFIG_DOS_PARTITION 95 #define CONFIG_DOS_PARTITION
96 #define CONFIG_CMD_FAT 96 #define CONFIG_CMD_FAT
97 #define CONFIG_CMD_EXT2 97 #define CONFIG_CMD_EXT2
98 98
99 #define CONFIG_SPI 99 #define CONFIG_SPI
100 #define CONFIG_OMAP3_SPI 100 #define CONFIG_OMAP3_SPI
101 #define CONFIG_MTD_DEVICE 101 #define CONFIG_MTD_DEVICE
102 #define CONFIG_SPI_FLASH 102 #define CONFIG_SPI_FLASH
103 #define CONFIG_SPI_FLASH_WINBOND 103 #define CONFIG_SPI_FLASH_WINBOND
104 #define CONFIG_CMD_SF 104 #define CONFIG_CMD_SF
105 #define CONFIG_SF_DEFAULT_SPEED (75000000) 105 #define CONFIG_SF_DEFAULT_SPEED (75000000)
106 106
107 /* Physical Memory Map */ 107 /* Physical Memory Map */
108 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ 108 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
109 #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ 109 #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
110 110
111 #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 111 #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
112 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 112 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
113 GENERATED_GBL_DATA_SIZE) 113 GENERATED_GBL_DATA_SIZE)
114 /* Platform/Board specific defs */ 114 /* Platform/Board specific defs */
115 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 115 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
116 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 116 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
117 117
118 /* NS16550 Configuration */ 118 /* NS16550 Configuration */
119 #define CONFIG_SYS_NS16550 119 #define CONFIG_SYS_NS16550
120 #define CONFIG_SYS_NS16550_SERIAL 120 #define CONFIG_SYS_NS16550_SERIAL
121 #define CONFIG_SERIAL_MULTI 121 #define CONFIG_SERIAL_MULTI
122 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 122 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
123 #define CONFIG_SYS_NS16550_CLK (48000000) 123 #define CONFIG_SYS_NS16550_CLK (48000000)
124 #define CONFIG_SYS_NS16550_COM1 0x44e09000 124 #define CONFIG_SYS_NS16550_COM1 0x44e09000
125 #define CONFIG_SYS_NS16550_COM4 0x481a6000 125 #define CONFIG_SYS_NS16550_COM4 0x481a6000
126 126
127 #define CONFIG_BAUDRATE 115200 127 #define CONFIG_BAUDRATE 115200
128 128
129 #define CONFIG_SYS_CONSOLE_INFO_QUIET 129 #define CONFIG_SYS_CONSOLE_INFO_QUIET
130 #define CONFIG_SERIAL1 1 130 #define CONFIG_SERIAL1 1
131 #define CONFIG_CONS_INDEX 1 131 #define CONFIG_CONS_INDEX 1
132 132
133 /* I2C Configuration */ 133 /* I2C Configuration */
134 #define CONFIG_I2C 134 #define CONFIG_I2C
135 #define CONFIG_CMD_I2C 135 #define CONFIG_CMD_I2C
136 #define CONFIG_SYS_I2C 136 #define CONFIG_SYS_I2C
137 #define CONFIG_SYS_OMAP24_I2C_SPEED OMAP_I2C_STANDARD 137 #define CONFIG_SYS_OMAP24_I2C_SPEED OMAP_I2C_STANDARD
138 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 138 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
139 #define CONFIG_SYS_I2C_OMAP24XX 139 #define CONFIG_SYS_I2C_OMAP24XX
140 140
141 /* Defines for SPL */ 141 /* Defines for SPL */
142 #define CONFIG_SPL_FRAMEWORK 142 #define CONFIG_SPL_FRAMEWORK
143 #define CONFIG_SPL_TEXT_BASE 0x402F0400 143 #define CONFIG_SPL_TEXT_BASE 0x402F0400
144 #define CONFIG_SPL_MAX_SIZE (101 * 1024) 144 #define CONFIG_SPL_MAX_SIZE (101 * 1024)
145 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
146 145
147 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 146 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
148 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 147 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
149 148
150 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 149 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
151 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 150 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
152 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 151 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
153 #define CONFIG_SPL_MMC_SUPPORT 152 #define CONFIG_SPL_MMC_SUPPORT
154 #define CONFIG_SPL_FAT_SUPPORT 153 #define CONFIG_SPL_FAT_SUPPORT
155 #define CONFIG_FS_FAT 154 #define CONFIG_FS_FAT
156 #define CONFIG_SPL_I2C_SUPPORT 155 #define CONFIG_SPL_I2C_SUPPORT
157 156
158 #define CONFIG_SPL_LIBCOMMON_SUPPORT 157 #define CONFIG_SPL_LIBCOMMON_SUPPORT
159 #define CONFIG_SPL_LIBDISK_SUPPORT 158 #define CONFIG_SPL_LIBDISK_SUPPORT
160 #define CONFIG_SPL_LIBGENERIC_SUPPORT 159 #define CONFIG_SPL_LIBGENERIC_SUPPORT
161 #define CONFIG_SPL_SERIAL_SUPPORT 160 #define CONFIG_SPL_SERIAL_SUPPORT
162 #define CONFIG_SPL_YMODEM_SUPPORT 161 #define CONFIG_SPL_YMODEM_SUPPORT
163 162
164 #define CONFIG_SPL_GPIO_SUPPORT 163 #define CONFIG_SPL_GPIO_SUPPORT
165 #define CONFIG_SPL_WATCHDOG_SUPPORT 164 #define CONFIG_SPL_WATCHDOG_SUPPORT
166 165
167 #define CONFIG_SPL_SPI_SUPPORT 166 #define CONFIG_SPL_SPI_SUPPORT
168 #define CONFIG_SPL_SPI_FLASH_SUPPORT 167 #define CONFIG_SPL_SPI_FLASH_SUPPORT
169 #define CONFIG_SPL_SPI_LOAD 168 #define CONFIG_SPL_SPI_LOAD
170 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 169 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
171 170
172 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" 171 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
173 172
174 #define CONFIG_SPL_BOARD_INIT 173 #define CONFIG_SPL_BOARD_INIT
175 #define CONFIG_SPL_NAND_AM33XX_BCH 174 #define CONFIG_SPL_NAND_AM33XX_BCH
176 #define CONFIG_SPL_NAND_SUPPORT 175 #define CONFIG_SPL_NAND_SUPPORT
177 #define CONFIG_SPL_NAND_BASE 176 #define CONFIG_SPL_NAND_BASE
178 #define CONFIG_SPL_NAND_DRIVERS 177 #define CONFIG_SPL_NAND_DRIVERS
179 #define CONFIG_SPL_NAND_ECC 178 #define CONFIG_SPL_NAND_ECC
180 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 179 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
181 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 180 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
182 CONFIG_SYS_NAND_PAGE_SIZE) 181 CONFIG_SYS_NAND_PAGE_SIZE)
183 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 182 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
184 #define CONFIG_SYS_NAND_OOBSIZE 64 183 #define CONFIG_SYS_NAND_OOBSIZE 64
185 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 184 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
186 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 185 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
187 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 186 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
188 10, 11, 12, 13, 14, 15, 16, 17, \ 187 10, 11, 12, 13, 14, 15, 16, 17, \
189 18, 19, 20, 21, 22, 23, 24, 25, \ 188 18, 19, 20, 21, 22, 23, 24, 25, \
190 26, 27, 28, 29, 30, 31, 32, 33, \ 189 26, 27, 28, 29, 30, 31, 32, 33, \
191 34, 35, 36, 37, 38, 39, 40, 41, \ 190 34, 35, 36, 37, 38, 39, 40, 41, \
192 42, 43, 44, 45, 46, 47, 48, 49, \ 191 42, 43, 44, 45, 46, 47, 48, 49, \
193 50, 51, 52, 53, 54, 55, 56, 57, } 192 50, 51, 52, 53, 54, 55, 56, 57, }
194 193
195 #define CONFIG_SYS_NAND_ECCSIZE 512 194 #define CONFIG_SYS_NAND_ECCSIZE 512
196 #define CONFIG_SYS_NAND_ECCBYTES 14 195 #define CONFIG_SYS_NAND_ECCBYTES 14
197 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 196 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
198 197
199 #define CONFIG_SYS_NAND_ECCSTEPS 4 198 #define CONFIG_SYS_NAND_ECCSTEPS 4
200 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ 199 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
201 CONFIG_SYS_NAND_ECCSTEPS) 200 CONFIG_SYS_NAND_ECCSTEPS)
202 201
203 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 202 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
204 203
205 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 204 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
206 205
207 /* 206 /*
208 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 207 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
209 * 64 bytes before this address should be set aside for u-boot.img's 208 * 64 bytes before this address should be set aside for u-boot.img's
210 * header. That is 0x800FFFC0--0x80100000 should not be used for any 209 * header. That is 0x800FFFC0--0x80100000 should not be used for any
211 * other needs. 210 * other needs.
212 */ 211 */
213 #define CONFIG_SYS_TEXT_BASE 0x80100000 212 #define CONFIG_SYS_TEXT_BASE 0x80100000
214 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 213 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
215 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 214 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
216 215
217 /* 216 /*
218 * Since SPL did pll and ddr initialization for us, 217 * Since SPL did pll and ddr initialization for us,
219 * we don't need to do it twice. 218 * we don't need to do it twice.
220 */ 219 */
221 #ifndef CONFIG_SPL_BUILD 220 #ifndef CONFIG_SPL_BUILD
222 #define CONFIG_SKIP_LOWLEVEL_INIT 221 #define CONFIG_SKIP_LOWLEVEL_INIT
223 #endif 222 #endif
224 223
225 #ifndef CONFIG_SPL_BUILD 224 #ifndef CONFIG_SPL_BUILD
226 /* 225 /*
227 * USB configuration 226 * USB configuration
228 */ 227 */
229 #define CONFIG_USB_MUSB_DSPS 228 #define CONFIG_USB_MUSB_DSPS
230 #define CONFIG_ARCH_MISC_INIT 229 #define CONFIG_ARCH_MISC_INIT
231 #define CONFIG_MUSB_GADGET 230 #define CONFIG_MUSB_GADGET
232 #define CONFIG_MUSB_PIO_ONLY 231 #define CONFIG_MUSB_PIO_ONLY
233 #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT 232 #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
234 #undef CONFIG_USB_GADGET_DUALSPEED 233 #undef CONFIG_USB_GADGET_DUALSPEED
235 #define CONFIG_USB_GADGET_VBUS_DRAW 2 234 #define CONFIG_USB_GADGET_VBUS_DRAW 2
236 #define CONFIG_MUSB_HOST 235 #define CONFIG_MUSB_HOST
237 236
238 #define CONFIG_AM335X_USB0 237 #define CONFIG_AM335X_USB0
239 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL 238 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
240 #define CONFIG_AM335X_USB1 239 #define CONFIG_AM335X_USB1
241 #define CONFIG_AM335X_USB1_MODE MUSB_HOST 240 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
242 #ifdef CONFIG_MUSB_HOST 241 #ifdef CONFIG_MUSB_HOST
243 #define CONFIG_CMD_USB 242 #define CONFIG_CMD_USB
244 #define CONFIG_USB_STORAGE 243 #define CONFIG_USB_STORAGE
245 #endif 244 #endif
246 245
247 #ifdef CONFIG_MUSB_GADGET 246 #ifdef CONFIG_MUSB_GADGET
248 #define CONFIG_USB_ETHER 247 #define CONFIG_USB_ETHER
249 #define CONFIG_USB_ETH_RNDIS 248 #define CONFIG_USB_ETH_RNDIS
250 #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" 249 #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
251 #endif /* CONFIG_MUSB_GADGET */ 250 #endif /* CONFIG_MUSB_GADGET */
252 251
253 #define CONFIG_USB_GADGET 252 #define CONFIG_USB_GADGET
254 #define CONFIG_USBDOWNLOAD_GADGET 253 #define CONFIG_USBDOWNLOAD_GADGET
255 254
256 /* USB DRACO ID as default */ 255 /* USB DRACO ID as default */
257 #define CONFIG_USBD_HS 256 #define CONFIG_USBD_HS
258 #define CONFIG_G_DNL_VENDOR_NUM 0x0908 257 #define CONFIG_G_DNL_VENDOR_NUM 0x0908
259 #define CONFIG_G_DNL_PRODUCT_NUM 0x02d2 258 #define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
260 #define CONFIG_G_DNL_MANUFACTURER "Siemens AG" 259 #define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
261 260
262 /* USB Device Firmware Update support */ 261 /* USB Device Firmware Update support */
263 #define CONFIG_DFU_FUNCTION 262 #define CONFIG_DFU_FUNCTION
264 #define CONFIG_DFU_NAND 263 #define CONFIG_DFU_NAND
265 #define CONFIG_CMD_DFU 264 #define CONFIG_CMD_DFU
266 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) 265 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20)
267 #define DFU_MANIFEST_POLL_TIMEOUT 25000 266 #define DFU_MANIFEST_POLL_TIMEOUT 25000
268 267
269 #endif /* CONFIG_SPL_BUILD */ 268 #endif /* CONFIG_SPL_BUILD */
270 269
271 /* 270 /*
272 * Default to using SPI for environment, etc. We have multiple copies 271 * Default to using SPI for environment, etc. We have multiple copies
273 * of SPL as the ROM will check these locations. 272 * of SPL as the ROM will check these locations.
274 * 0x0 - 0x20000 : First copy of SPL 273 * 0x0 - 0x20000 : First copy of SPL
275 * 0x20000 - 0x40000 : Second copy of SPL 274 * 0x20000 - 0x40000 : Second copy of SPL
276 * 0x40000 - 0x60000 : Third copy of SPL 275 * 0x40000 - 0x60000 : Third copy of SPL
277 * 0x60000 - 0x80000 : Fourth copy of SPL 276 * 0x60000 - 0x80000 : Fourth copy of SPL
278 * 0x80000 - 0xDF000 : U-Boot 277 * 0x80000 - 0xDF000 : U-Boot
279 * 0xDF000 - 0xE0000 : U-Boot Environment 278 * 0xDF000 - 0xE0000 : U-Boot Environment
280 * 0xE0000 - 0x442000 : Linux Kernel 279 * 0xE0000 - 0x442000 : Linux Kernel
281 * 0x442000 - 0x800000 : Userland 280 * 0x442000 - 0x800000 : Userland
282 */ 281 */
283 #if defined(CONFIG_SPI_BOOT) 282 #if defined(CONFIG_SPI_BOOT)
284 # undef CONFIG_ENV_IS_NOWHERE 283 # undef CONFIG_ENV_IS_NOWHERE
285 # define CONFIG_ENV_IS_IN_SPI_FLASH 284 # define CONFIG_ENV_IS_IN_SPI_FLASH
286 # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 285 # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
287 # define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ 286 # define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */
288 # define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ 287 # define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
289 #endif /* SPI support */ 288 #endif /* SPI support */
290 289
291 /* Unsupported features */ 290 /* Unsupported features */
292 #undef CONFIG_USE_IRQ 291 #undef CONFIG_USE_IRQ
293 292
294 #define CONFIG_CMD_NET 293 #define CONFIG_CMD_NET
295 #define CONFIG_CMD_DHCP 294 #define CONFIG_CMD_DHCP
296 #define CONFIG_CMD_PING 295 #define CONFIG_CMD_PING
297 #define CONFIG_DRIVER_TI_CPSW 296 #define CONFIG_DRIVER_TI_CPSW
298 #define CONFIG_MII 297 #define CONFIG_MII
299 #define CONFIG_PHY_GIGE 298 #define CONFIG_PHY_GIGE
300 #define CONFIG_PHYLIB 299 #define CONFIG_PHYLIB
301 #define CONFIG_CMD_MII 300 #define CONFIG_CMD_MII
302 #define CONFIG_BOOTP_DEFAULT 301 #define CONFIG_BOOTP_DEFAULT
303 #define CONFIG_BOOTP_DNS 302 #define CONFIG_BOOTP_DNS
304 #define CONFIG_BOOTP_DNS2 303 #define CONFIG_BOOTP_DNS2
305 #define CONFIG_BOOTP_SEND_HOSTNAME 304 #define CONFIG_BOOTP_SEND_HOSTNAME
306 #define CONFIG_BOOTP_GATEWAY 305 #define CONFIG_BOOTP_GATEWAY
307 #define CONFIG_BOOTP_SUBNETMASK 306 #define CONFIG_BOOTP_SUBNETMASK
308 #define CONFIG_NET_RETRY_COUNT 10 307 #define CONFIG_NET_RETRY_COUNT 10
309 #define CONFIG_NET_MULTI 308 #define CONFIG_NET_MULTI
310 309
311 #define CONFIG_NAND 310 #define CONFIG_NAND
312 /* NAND support */ 311 /* NAND support */
313 #ifdef CONFIG_NAND 312 #ifdef CONFIG_NAND
314 #define CONFIG_CMD_NAND 313 #define CONFIG_CMD_NAND
315 #define CONFIG_CMD_MTDPARTS 314 #define CONFIG_CMD_MTDPARTS
316 315
317 #define MTDIDS_NAME_STR "omap2-nand.0" 316 #define MTDIDS_NAME_STR "omap2-nand.0"
318 #define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR 317 #define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
319 #define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ 318 #define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
320 "128k(spl)," \ 319 "128k(spl)," \
321 "128k(spl.backup1)," \ 320 "128k(spl.backup1)," \
322 "128k(spl.backup2)," \ 321 "128k(spl.backup2)," \
323 "128k(spl.backup3)," \ 322 "128k(spl.backup3)," \
324 "1920k(u-boot)," \ 323 "1920k(u-boot)," \
325 "128k(uboot.env)," \ 324 "128k(uboot.env)," \
326 "5120k(kernel_a)," \ 325 "5120k(kernel_a)," \
327 "5120k(kernel_b)," \ 326 "5120k(kernel_b)," \
328 "8192k(mtdoops)," \ 327 "8192k(mtdoops)," \
329 "-(rootfs)" 328 "-(rootfs)"
330 /* 329 /*
331 * chip-size = 256MiB 330 * chip-size = 256MiB
332 *| name | size | address area | 331 *| name | size | address area |
333 *------------------------------------------------------- 332 *-------------------------------------------------------
334 *| spl | 128.000 KiB | 0x 0..0x 1ffff | 333 *| spl | 128.000 KiB | 0x 0..0x 1ffff |
335 *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | 334 *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff |
336 *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | 335 *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff |
337 *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | 336 *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff |
338 *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | 337 *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff |
339 *| uboot.env | 128.000 KiB | 0x 260000..0x 27ffff | 338 *| uboot.env | 128.000 KiB | 0x 260000..0x 27ffff |
340 *| kernel_a | 5.000 MiB | 0x 280000..0x 77ffff | 339 *| kernel_a | 5.000 MiB | 0x 280000..0x 77ffff |
341 *| kernel_b | 5.000 MiB | 0x 780000..0x c7ffff | 340 *| kernel_b | 5.000 MiB | 0x 780000..0x c7ffff |
342 *| mtdoops | 8.000 MiB | 0x c80000..0x 147ffff | 341 *| mtdoops | 8.000 MiB | 0x c80000..0x 147ffff |
343 *| rootfs | 235.500 MiB | 0x 1480000..0x fffffff | 342 *| rootfs | 235.500 MiB | 0x 1480000..0x fffffff |
344 *------------------------------------------------------- 343 *-------------------------------------------------------
345 */ 344 */
346 345
347 #define DFU_ALT_INFO_NAND \ 346 #define DFU_ALT_INFO_NAND \
348 "spl part 0 1;" \ 347 "spl part 0 1;" \
349 "spl.backup1 part 0 2;" \ 348 "spl.backup1 part 0 2;" \
350 "spl.backup2 part 0 3;" \ 349 "spl.backup2 part 0 3;" \
351 "spl.backup3 part 0 4;" \ 350 "spl.backup3 part 0 4;" \
352 "u-boot part 0 5;" \ 351 "u-boot part 0 5;" \
353 "u-boot.env part 0 6;" \ 352 "u-boot.env part 0 6;" \
354 "kernel_a part 0 7;" \ 353 "kernel_a part 0 7;" \
355 "kernel_b part 0 8;" \ 354 "kernel_b part 0 8;" \
356 "rootfs partubi 0 10" 355 "rootfs partubi 0 10"
357 356
358 #define CONFIG_COMMON_ENV_SETTINGS \ 357 #define CONFIG_COMMON_ENV_SETTINGS \
359 "verify=no \0" \ 358 "verify=no \0" \
360 "project_dir=targetdir\0" \ 359 "project_dir=targetdir\0" \
361 "upgrade_available=0\0" \ 360 "upgrade_available=0\0" \
362 "altbootcmd=run bootcmd\0" \ 361 "altbootcmd=run bootcmd\0" \
363 "bootlimit=3\0" \ 362 "bootlimit=3\0" \
364 "partitionset_active=A\0" \ 363 "partitionset_active=A\0" \
365 "loadaddr=0x82000000\0" \ 364 "loadaddr=0x82000000\0" \
366 "kloadaddr=0x81000000\0" \ 365 "kloadaddr=0x81000000\0" \
367 "script_addr=0x81900000\0" \ 366 "script_addr=0x81900000\0" \
368 "console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \ 367 "console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
369 "nand_active_ubi_vol=rootfs_a\0" \ 368 "nand_active_ubi_vol=rootfs_a\0" \
370 "nand_active_ubi_vol_A=rootfs_a\0" \ 369 "nand_active_ubi_vol_A=rootfs_a\0" \
371 "nand_active_ubi_vol_B=rootfs_b\0" \ 370 "nand_active_ubi_vol_B=rootfs_b\0" \
372 "nand_root_fs_type=ubifs rootwait=1\0" \ 371 "nand_root_fs_type=ubifs rootwait=1\0" \
373 "nand_src_addr=0x280000\0" \ 372 "nand_src_addr=0x280000\0" \
374 "nand_src_addr_A=0x280000\0" \ 373 "nand_src_addr_A=0x280000\0" \
375 "nand_src_addr_B=0x780000\0" \ 374 "nand_src_addr_B=0x780000\0" \
376 "nfsopts=nolock rw mem=128M\0" \ 375 "nfsopts=nolock rw mem=128M\0" \
377 "ip_method=none\0" \ 376 "ip_method=none\0" \
378 "bootenv=uEnv.txt\0" \ 377 "bootenv=uEnv.txt\0" \
379 "bootargs_defaults=setenv bootargs " \ 378 "bootargs_defaults=setenv bootargs " \
380 "console=${console} " \ 379 "console=${console} " \
381 "${testargs} " \ 380 "${testargs} " \
382 "${optargs}\0" \ 381 "${optargs}\0" \
383 "nand_args=run bootargs_defaults;" \ 382 "nand_args=run bootargs_defaults;" \
384 "mtdparts default;" \ 383 "mtdparts default;" \
385 "setenv ${partitionset_active} true;" \ 384 "setenv ${partitionset_active} true;" \
386 "if test -n ${A}; then " \ 385 "if test -n ${A}; then " \
387 "setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \ 386 "setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \
388 "setenv nand_src_addr ${nand_src_addr_A};" \ 387 "setenv nand_src_addr ${nand_src_addr_A};" \
389 "fi;" \ 388 "fi;" \
390 "if test -n ${B}; then " \ 389 "if test -n ${B}; then " \
391 "setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \ 390 "setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \
392 "setenv nand_src_addr ${nand_src_addr_B};" \ 391 "setenv nand_src_addr ${nand_src_addr_B};" \
393 "fi;" \ 392 "fi;" \
394 "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ 393 "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
395 "ubi.mtd=9,2048;" \ 394 "ubi.mtd=9,2048;" \
396 "setenv bootargs ${bootargs} " \ 395 "setenv bootargs ${bootargs} " \
397 "root=${nand_root} noinitrd ${mtdparts} " \ 396 "root=${nand_root} noinitrd ${mtdparts} " \
398 "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ 397 "rootfstype=${nand_root_fs_type} ip=${ip_method} " \
399 "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ 398 "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
400 "=mtdoops\0" \ 399 "=mtdoops\0" \
401 "dfu_args=run bootargs_defaults;" \ 400 "dfu_args=run bootargs_defaults;" \
402 "setenv bootargs ${bootargs} ;" \ 401 "setenv bootargs ${bootargs} ;" \
403 "mtdparts default; " \ 402 "mtdparts default; " \
404 "led dfu 1;" \ 403 "led dfu 1;" \
405 "led stat 0;" \ 404 "led stat 0;" \
406 "dfu 0 nand 0;" \ 405 "dfu 0 nand 0;" \
407 "led dfu 0;" \ 406 "led dfu 0;" \
408 "led stat 1;\0" \ 407 "led stat 1;\0" \
409 "dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \ 408 "dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \
410 "net_args=run bootargs_defaults;" \ 409 "net_args=run bootargs_defaults;" \
411 "mtdparts default;" \ 410 "mtdparts default;" \
412 "setenv bootfile ${project_dir}/kernel/uImage;" \ 411 "setenv bootfile ${project_dir}/kernel/uImage;" \
413 "setenv rootpath /home/projects/${project_dir}/rootfs;" \ 412 "setenv rootpath /home/projects/${project_dir}/rootfs;" \
414 "setenv bootargs ${bootargs} " \ 413 "setenv bootargs ${bootargs} " \
415 "root=/dev/nfs ${mtdparts} " \ 414 "root=/dev/nfs ${mtdparts} " \
416 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 415 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
417 "ip=${ipaddr}:${serverip}:" \ 416 "ip=${ipaddr}:${serverip}:" \
418 "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ 417 "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
419 "nand_boot=echo Booting from nand; " \ 418 "nand_boot=echo Booting from nand; " \
420 "if test ${upgrade_available} -eq 1; then " \ 419 "if test ${upgrade_available} -eq 1; then " \
421 "if test ${bootcount} -gt ${bootlimit}; " \ 420 "if test ${bootcount} -gt ${bootlimit}; " \
422 "then " \ 421 "then " \
423 "setenv upgrade_available 0;" \ 422 "setenv upgrade_available 0;" \
424 "setenv ${partitionset_active} true;" \ 423 "setenv ${partitionset_active} true;" \
425 "if test -n ${A}; then " \ 424 "if test -n ${A}; then " \
426 "setenv partitionset_active B; " \ 425 "setenv partitionset_active B; " \
427 "env delete A; " \ 426 "env delete A; " \
428 "fi;" \ 427 "fi;" \
429 "if test -n ${B}; then " \ 428 "if test -n ${B}; then " \
430 "setenv partitionset_active A; " \ 429 "setenv partitionset_active A; " \
431 "env delete B; " \ 430 "env delete B; " \
432 "fi;" \ 431 "fi;" \
433 "saveenv; " \ 432 "saveenv; " \
434 "fi;" \ 433 "fi;" \
435 "fi;" \ 434 "fi;" \
436 "echo set ${partitionset_active}...;" \ 435 "echo set ${partitionset_active}...;" \
437 "run nand_args; " \ 436 "run nand_args; " \
438 "nand read.i ${kloadaddr} ${nand_src_addr} " \ 437 "nand read.i ${kloadaddr} ${nand_src_addr} " \
439 "${nand_img_size}; bootm ${kloadaddr}\0" \ 438 "${nand_img_size}; bootm ${kloadaddr}\0" \
440 "net_nfs=echo Booting from network ...; " \ 439 "net_nfs=echo Booting from network ...; " \
441 "run net_args; " \ 440 "run net_args; " \
442 "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \ 441 "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
443 "bootm ${kloadaddr}\0" \ 442 "bootm ${kloadaddr}\0" \
444 "flash_self=run nand_boot\0" \ 443 "flash_self=run nand_boot\0" \
445 "flash_self_test=setenv testargs test; " \ 444 "flash_self_test=setenv testargs test; " \
446 "run nand_boot\0" \ 445 "run nand_boot\0" \
447 "dfu_start=echo Preparing for dfu mode ...; " \ 446 "dfu_start=echo Preparing for dfu mode ...; " \
448 "run dfu_args; \0" \ 447 "run dfu_args; \0" \
449 "preboot=echo; "\ 448 "preboot=echo; "\
450 "echo Type 'run flash_self' to use kernel and root " \ 449 "echo Type 'run flash_self' to use kernel and root " \
451 "filesystem on memory; echo Type 'run flash_self_test' to " \ 450 "filesystem on memory; echo Type 'run flash_self_test' to " \
452 "use kernel and root filesystem on memory, boot in test " \ 451 "use kernel and root filesystem on memory, boot in test " \
453 "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \ 452 "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
454 "from memory and root filesystem over NFS; echo Type " \ 453 "from memory and root filesystem over NFS; echo Type " \
455 "'run net_nfs' to get Kernel over TFTP and mount root " \ 454 "'run net_nfs' to get Kernel over TFTP and mount root " \
456 "filesystem over NFS; " \ 455 "filesystem over NFS; " \
457 "echo Set partitionset_active variable to 'A' " \ 456 "echo Set partitionset_active variable to 'A' " \
458 "or 'B' to select kernel and rootfs partition; " \ 457 "or 'B' to select kernel and rootfs partition; " \
459 "echo" \ 458 "echo" \
460 "\0" 459 "\0"
461 460
462 #define CONFIG_NAND_OMAP_GPMC 461 #define CONFIG_NAND_OMAP_GPMC
463 #define CONFIG_NAND_OMAP_ELM 462 #define CONFIG_NAND_OMAP_ELM
464 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ 463 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
465 /* to access nand at */ 464 /* to access nand at */
466 /* CS0 */ 465 /* CS0 */
467 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND 466 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
468 devices */ 467 devices */
469 #if !defined(CONFIG_SPI_BOOT) 468 #if !defined(CONFIG_SPI_BOOT)
470 #undef CONFIG_ENV_IS_NOWHERE 469 #undef CONFIG_ENV_IS_NOWHERE
471 #define CONFIG_ENV_IS_IN_NAND 470 #define CONFIG_ENV_IS_IN_NAND
472 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ 471 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
473 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 472 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
474 #endif 473 #endif
475 #endif 474 #endif
476 475
477 #define CONFIG_OMAP_GPIO 476 #define CONFIG_OMAP_GPIO
478 477
479 /* Watchdog */ 478 /* Watchdog */
480 #define CONFIG_HW_WATCHDOG 479 #define CONFIG_HW_WATCHDOG
481 480
482 /* Stop autoboot with ESC ESC key detected */ 481 /* Stop autoboot with ESC ESC key detected */
483 #define CONFIG_AUTOBOOT_KEYED 482 #define CONFIG_AUTOBOOT_KEYED
484 #define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b" 483 #define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b"
485 #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ 484 #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
486 "press \"<Esc><Esc>\" to stop\n", bootdelay 485 "press \"<Esc><Esc>\" to stop\n", bootdelay
487 486
488 /* Reboot after 60 sec if bootcmd fails */ 487 /* Reboot after 60 sec if bootcmd fails */
489 #define CONFIG_RESET_TO_RETRY 488 #define CONFIG_RESET_TO_RETRY
490 #define CONFIG_BOOT_RETRY_TIME 60 489 #define CONFIG_BOOT_RETRY_TIME 60
491 490
492 #define CONFIG_BOOTCOUNT_LIMIT 491 #define CONFIG_BOOTCOUNT_LIMIT
493 #define CONFIG_BOOTCOUNT_ENV 492 #define CONFIG_BOOTCOUNT_ENV
494 493
495 /* Enable Device-Tree (FDT) support */ 494 /* Enable Device-Tree (FDT) support */
496 #define CONFIG_OF_LIBFDT 495 #define CONFIG_OF_LIBFDT
497 #define CONFIG_CMD_FDT 496 #define CONFIG_CMD_FDT
498 497
499 #endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */ 498 #endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
500 499
include/configs/tam3517-common.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * Copyright (C) 2011 2 * Copyright (C) 2011
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 * 4 *
5 * Copyright (C) 2009 TechNexion Ltd. 5 * Copyright (C) 2009 TechNexion Ltd.
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #ifndef __TAM3517_H 10 #ifndef __TAM3517_H
11 #define __TAM3517_H 11 #define __TAM3517_H
12 12
13 /* 13 /*
14 * High Level Configuration Options 14 * High Level Configuration Options
15 */ 15 */
16 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP /* in a TI OMAP core */
17 #define CONFIG_OMAP_GPIO 17 #define CONFIG_OMAP_GPIO
18 #define CONFIG_OMAP_COMMON 18 #define CONFIG_OMAP_COMMON
19 #define CONFIG_SYS_GENERIC_BOARD 19 #define CONFIG_SYS_GENERIC_BOARD
20 20
21 #define CONFIG_SYS_TEXT_BASE 0x80008000 21 #define CONFIG_SYS_TEXT_BASE 0x80008000
22 22
23 #define CONFIG_SYS_CACHELINE_SIZE 64 23 #define CONFIG_SYS_CACHELINE_SIZE 64
24 24
25 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 25 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
26 26
27 #include <asm/arch/cpu.h> /* get chip and board defs */ 27 #include <asm/arch/cpu.h> /* get chip and board defs */
28 #include <asm/arch/omap3.h> 28 #include <asm/arch/omap3.h>
29 29
30 /* 30 /*
31 * Display CPU and Board information 31 * Display CPU and Board information
32 */ 32 */
33 #define CONFIG_DISPLAY_CPUINFO 33 #define CONFIG_DISPLAY_CPUINFO
34 #define CONFIG_DISPLAY_BOARDINFO 34 #define CONFIG_DISPLAY_BOARDINFO
35 35
36 /* Clock Defines */ 36 /* Clock Defines */
37 #define V_OSCK 26000000 /* Clock output from T2 */ 37 #define V_OSCK 26000000 /* Clock output from T2 */
38 #define V_SCLK (V_OSCK >> 1) 38 #define V_SCLK (V_OSCK >> 1)
39 39
40 #define CONFIG_MISC_INIT_R 40 #define CONFIG_MISC_INIT_R
41 41
42 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 42 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
43 #define CONFIG_SETUP_MEMORY_TAGS 43 #define CONFIG_SETUP_MEMORY_TAGS
44 #define CONFIG_INITRD_TAG 44 #define CONFIG_INITRD_TAG
45 #define CONFIG_REVISION_TAG 45 #define CONFIG_REVISION_TAG
46 46
47 /* 47 /*
48 * Size of malloc() pool 48 * Size of malloc() pool
49 */ 49 */
50 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 50 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
51 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 51 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
52 2 * 1024 * 1024) 52 2 * 1024 * 1024)
53 /* 53 /*
54 * DDR related 54 * DDR related
55 */ 55 */
56 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 56 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
57 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 57 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
58 58
59 /* 59 /*
60 * Hardware drivers 60 * Hardware drivers
61 */ 61 */
62 62
63 /* 63 /*
64 * NS16550 Configuration 64 * NS16550 Configuration
65 */ 65 */
66 #define CONFIG_SYS_NS16550 66 #define CONFIG_SYS_NS16550
67 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
69 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
70 70
71 /* 71 /*
72 * select serial console configuration 72 * select serial console configuration
73 */ 73 */
74 #define CONFIG_CONS_INDEX 1 74 #define CONFIG_CONS_INDEX 1
75 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 75 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
76 #define CONFIG_SERIAL1 /* UART1 */ 76 #define CONFIG_SERIAL1 /* UART1 */
77 77
78 /* allow to overwrite serial and ethaddr */ 78 /* allow to overwrite serial and ethaddr */
79 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_ENV_OVERWRITE
80 #define CONFIG_BAUDRATE 115200 80 #define CONFIG_BAUDRATE 115200
81 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 81 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
82 115200} 82 115200}
83 #define CONFIG_MMC 83 #define CONFIG_MMC
84 #define CONFIG_OMAP_HSMMC 84 #define CONFIG_OMAP_HSMMC
85 #define CONFIG_GENERIC_MMC 85 #define CONFIG_GENERIC_MMC
86 #define CONFIG_DOS_PARTITION 86 #define CONFIG_DOS_PARTITION
87 87
88 /* EHCI */ 88 /* EHCI */
89 #define CONFIG_OMAP3_GPIO_5 89 #define CONFIG_OMAP3_GPIO_5
90 #define CONFIG_USB_EHCI 90 #define CONFIG_USB_EHCI
91 #define CONFIG_USB_EHCI_OMAP 91 #define CONFIG_USB_EHCI_OMAP
92 #define CONFIG_USB_ULPI 92 #define CONFIG_USB_ULPI
93 #define CONFIG_USB_ULPI_VIEWPORT_OMAP 93 #define CONFIG_USB_ULPI_VIEWPORT_OMAP
94 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 94 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
95 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 95 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
96 #define CONFIG_USB_STORAGE 96 #define CONFIG_USB_STORAGE
97 97
98 /* commands to include */ 98 /* commands to include */
99 #include <config_cmd_default.h> 99 #include <config_cmd_default.h>
100 100
101 #define CONFIG_CMD_CACHE 101 #define CONFIG_CMD_CACHE
102 #define CONFIG_CMD_DHCP 102 #define CONFIG_CMD_DHCP
103 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 103 #define CONFIG_CMD_EXT2 /* EXT2 Support */
104 #define CONFIG_CMD_FAT /* FAT support */ 104 #define CONFIG_CMD_FAT /* FAT support */
105 #define CONFIG_CMD_GPIO 105 #define CONFIG_CMD_GPIO
106 #define CONFIG_CMD_I2C /* I2C serial bus support */ 106 #define CONFIG_CMD_I2C /* I2C serial bus support */
107 #define CONFIG_CMD_MII 107 #define CONFIG_CMD_MII
108 #define CONFIG_CMD_MMC /* MMC support */ 108 #define CONFIG_CMD_MMC /* MMC support */
109 #define CONFIG_CMD_NET 109 #define CONFIG_CMD_NET
110 #define CONFIG_CMD_NFS 110 #define CONFIG_CMD_NFS
111 #define CONFIG_CMD_NAND /* NAND support */ 111 #define CONFIG_CMD_NAND /* NAND support */
112 #define CONFIG_CMD_PING 112 #define CONFIG_CMD_PING
113 #define CONFIG_CMD_USB 113 #define CONFIG_CMD_USB
114 #define CONFIG_CMD_EEPROM 114 #define CONFIG_CMD_EEPROM
115 115
116 #undef CONFIG_CMD_FLASH /* only NAND on the SOM */ 116 #undef CONFIG_CMD_FLASH /* only NAND on the SOM */
117 #undef CONFIG_CMD_IMLS 117 #undef CONFIG_CMD_IMLS
118 118
119 #define CONFIG_SYS_NO_FLASH 119 #define CONFIG_SYS_NO_FLASH
120 #define CONFIG_SYS_I2C 120 #define CONFIG_SYS_I2C
121 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 121 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000
122 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 122 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
123 #define CONFIG_SYS_I2C_OMAP34XX 123 #define CONFIG_SYS_I2C_OMAP34XX
124 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 124 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
126 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
127 127
128 /* 128 /*
129 * Board NAND Info. 129 * Board NAND Info.
130 */ 130 */
131 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 131 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
132 /* to access */ 132 /* to access */
133 /* nand at CS0 */ 133 /* nand at CS0 */
134 134
135 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 135 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
136 /* NAND devices */ 136 /* NAND devices */
137 137
138 #define CONFIG_AUTO_COMPLETE 138 #define CONFIG_AUTO_COMPLETE
139 139
140 /* 140 /*
141 * Miscellaneous configurable options 141 * Miscellaneous configurable options
142 */ 142 */
143 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 143 #define CONFIG_SYS_LONGHELP /* undef to save memory */
144 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 144 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
145 #define CONFIG_CMDLINE_EDITING 145 #define CONFIG_CMDLINE_EDITING
146 #define CONFIG_AUTO_COMPLETE 146 #define CONFIG_AUTO_COMPLETE
147 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 147 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
148 148
149 /* Print Buffer Size */ 149 /* Print Buffer Size */
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
151 sizeof(CONFIG_SYS_PROMPT) + 16) 151 sizeof(CONFIG_SYS_PROMPT) + 16)
152 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 152 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
153 /* args */ 153 /* args */
154 /* Boot Argument Buffer Size */ 154 /* Boot Argument Buffer Size */
155 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 155 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
156 /* memtest works on */ 156 /* memtest works on */
157 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 157 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
158 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 158 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
159 0x01F00000) /* 31MB */ 159 0x01F00000) /* 31MB */
160 160
161 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 161 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
162 /* address */ 162 /* address */
163 163
164 /* 164 /*
165 * AM3517 has 12 GP timers, they can be driven by the system clock 165 * AM3517 has 12 GP timers, they can be driven by the system clock
166 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 166 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
167 * This rate is divided by a local divisor. 167 * This rate is divided by a local divisor.
168 */ 168 */
169 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 169 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
170 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 170 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
171 171
172 /* 172 /*
173 * Physical Memory Map 173 * Physical Memory Map
174 */ 174 */
175 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 175 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
176 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 176 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
177 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 177 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
178 178
179 /* 179 /*
180 * FLASH and environment organization 180 * FLASH and environment organization
181 */ 181 */
182 182
183 /* **** PISMO SUPPORT *** */ 183 /* **** PISMO SUPPORT *** */
184 #define CONFIG_NAND 184 #define CONFIG_NAND
185 #define CONFIG_NAND_OMAP_GPMC 185 #define CONFIG_NAND_OMAP_GPMC
186 #define CONFIG_ENV_IS_IN_NAND 186 #define CONFIG_ENV_IS_IN_NAND
187 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 187 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
188 188
189 /* Redundant Environment */ 189 /* Redundant Environment */
190 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 190 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
191 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 191 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
192 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 192 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
193 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 193 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
194 2 * CONFIG_SYS_ENV_SECT_SIZE) 194 2 * CONFIG_SYS_ENV_SECT_SIZE)
195 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 195 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
196 196
197 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 197 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
198 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 198 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
199 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 199 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
200 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 200 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
201 CONFIG_SYS_INIT_RAM_SIZE - \ 201 CONFIG_SYS_INIT_RAM_SIZE - \
202 GENERATED_GBL_DATA_SIZE) 202 GENERATED_GBL_DATA_SIZE)
203 203
204 /* 204 /*
205 * ethernet support, EMAC 205 * ethernet support, EMAC
206 * 206 *
207 */ 207 */
208 #define CONFIG_DRIVER_TI_EMAC 208 #define CONFIG_DRIVER_TI_EMAC
209 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 209 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
210 #define CONFIG_MII 210 #define CONFIG_MII
211 #define CONFIG_EMAC_MDIO_PHY_NUM 0 211 #define CONFIG_EMAC_MDIO_PHY_NUM 0
212 #define CONFIG_BOOTP_DNS 212 #define CONFIG_BOOTP_DNS
213 #define CONFIG_BOOTP_DNS2 213 #define CONFIG_BOOTP_DNS2
214 #define CONFIG_BOOTP_SEND_HOSTNAME 214 #define CONFIG_BOOTP_SEND_HOSTNAME
215 #define CONFIG_NET_RETRY_COUNT 10 215 #define CONFIG_NET_RETRY_COUNT 10
216 216
217 /* Defines for SPL */ 217 /* Defines for SPL */
218 #define CONFIG_SPL_FRAMEWORK 218 #define CONFIG_SPL_FRAMEWORK
219 #define CONFIG_SPL_BOARD_INIT 219 #define CONFIG_SPL_BOARD_INIT
220 #define CONFIG_SPL_CONSOLE 220 #define CONFIG_SPL_CONSOLE
221 #define CONFIG_SPL_NAND_SIMPLE 221 #define CONFIG_SPL_NAND_SIMPLE
222 #define CONFIG_SPL_NAND_SOFTECC 222 #define CONFIG_SPL_NAND_SOFTECC
223 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 223 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
224 224
225 #define CONFIG_SPL_LIBCOMMON_SUPPORT 225 #define CONFIG_SPL_LIBCOMMON_SUPPORT
226 #define CONFIG_SPL_LIBDISK_SUPPORT 226 #define CONFIG_SPL_LIBDISK_SUPPORT
227 #define CONFIG_SPL_I2C_SUPPORT 227 #define CONFIG_SPL_I2C_SUPPORT
228 #define CONFIG_SPL_LIBGENERIC_SUPPORT 228 #define CONFIG_SPL_LIBGENERIC_SUPPORT
229 #define CONFIG_SPL_SERIAL_SUPPORT 229 #define CONFIG_SPL_SERIAL_SUPPORT
230 #define CONFIG_SPL_GPIO_SUPPORT 230 #define CONFIG_SPL_GPIO_SUPPORT
231 #define CONFIG_SPL_POWER_SUPPORT 231 #define CONFIG_SPL_POWER_SUPPORT
232 #define CONFIG_SPL_NAND_SUPPORT 232 #define CONFIG_SPL_NAND_SUPPORT
233 #define CONFIG_SPL_NAND_BASE 233 #define CONFIG_SPL_NAND_BASE
234 #define CONFIG_SPL_NAND_DRIVERS 234 #define CONFIG_SPL_NAND_DRIVERS
235 #define CONFIG_SPL_NAND_ECC 235 #define CONFIG_SPL_NAND_ECC
236 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 236 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
237 237
238 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 238 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
239 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 239 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
240 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
241 240
242 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 241 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
243 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 242 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
244 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 243 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
245 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 244 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
246 245
247 /* NAND boot config */ 246 /* NAND boot config */
248 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 247 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
249 #define CONFIG_SYS_NAND_PAGE_COUNT 64 248 #define CONFIG_SYS_NAND_PAGE_COUNT 64
250 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 249 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
251 #define CONFIG_SYS_NAND_OOBSIZE 64 250 #define CONFIG_SYS_NAND_OOBSIZE 64
252 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 251 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
253 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 252 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
254 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 253 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
255 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 254 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
256 48, 49, 50, 51, 52, 53, 54, 55,\ 255 48, 49, 50, 51, 52, 53, 54, 55,\
257 56, 57, 58, 59, 60, 61, 62, 63} 256 56, 57, 58, 59, 60, 61, 62, 63}
258 #define CONFIG_SYS_NAND_ECCSIZE 256 257 #define CONFIG_SYS_NAND_ECCSIZE 256
259 #define CONFIG_SYS_NAND_ECCBYTES 3 258 #define CONFIG_SYS_NAND_ECCBYTES 3
260 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 259 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
261 260
262 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 261 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
263 262
264 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 263 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
265 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 264 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
266 265
267 #define CONFIG_OF_LIBFDT 266 #define CONFIG_OF_LIBFDT
268 #define CONFIG_FIT 267 #define CONFIG_FIT
269 #define CONFIG_CMD_UBI 268 #define CONFIG_CMD_UBI
270 #define CONFIG_CMD_UBIFS 269 #define CONFIG_CMD_UBIFS
271 #define CONFIG_RBTREE 270 #define CONFIG_RBTREE
272 #define CONFIG_LZO 271 #define CONFIG_LZO
273 #define CONFIG_MTD_PARTITIONS 272 #define CONFIG_MTD_PARTITIONS
274 #define CONFIG_MTD_DEVICE 273 #define CONFIG_MTD_DEVICE
275 #define CONFIG_CMD_MTDPARTS 274 #define CONFIG_CMD_MTDPARTS
276 275
277 /* Setup MTD for NAND on the SOM */ 276 /* Setup MTD for NAND on the SOM */
278 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 277 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
279 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 278 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
280 "1m(u-boot),256k(env1)," \ 279 "1m(u-boot),256k(env1)," \
281 "256k(env2),6m(kernel),-(rootfs)" 280 "256k(env2),6m(kernel),-(rootfs)"
282 281
283 #define CONFIG_TAM3517_SETTINGS \ 282 #define CONFIG_TAM3517_SETTINGS \
284 "netdev=eth0\0" \ 283 "netdev=eth0\0" \
285 "nandargs=setenv bootargs root=${nandroot} " \ 284 "nandargs=setenv bootargs root=${nandroot} " \
286 "rootfstype=${nandrootfstype}\0" \ 285 "rootfstype=${nandrootfstype}\0" \
287 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 286 "nfsargs=setenv bootargs root=/dev/nfs rw " \
288 "nfsroot=${serverip}:${rootpath}\0" \ 287 "nfsroot=${serverip}:${rootpath}\0" \
289 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 288 "ramargs=setenv bootargs root=/dev/ram rw\0" \
290 "addip_sta=setenv bootargs ${bootargs} " \ 289 "addip_sta=setenv bootargs ${bootargs} " \
291 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 290 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
292 ":${hostname}:${netdev}:off panic=1\0" \ 291 ":${hostname}:${netdev}:off panic=1\0" \
293 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 292 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
294 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 293 "addip=if test -n ${ipdyn};then run addip_dyn;" \
295 "else run addip_sta;fi\0" \ 294 "else run addip_sta;fi\0" \
296 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 295 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
297 "addtty=setenv bootargs ${bootargs}" \ 296 "addtty=setenv bootargs ${bootargs}" \
298 " console=ttyO0,${baudrate}\0" \ 297 " console=ttyO0,${baudrate}\0" \
299 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 298 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
300 "loadaddr=82000000\0" \ 299 "loadaddr=82000000\0" \
301 "kernel_addr_r=82000000\0" \ 300 "kernel_addr_r=82000000\0" \
302 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 301 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
303 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 302 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
304 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 303 "flash_self=run ramargs addip addtty addmtd addmisc;" \
305 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 304 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
306 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 305 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
307 "bootm ${kernel_addr}\0" \ 306 "bootm ${kernel_addr}\0" \
308 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 307 "nandboot=run nandargs addip addtty addmtd addmisc;" \
309 "nand read ${kernel_addr_r} kernel\0" \ 308 "nand read ${kernel_addr_r} kernel\0" \
310 "bootm ${kernel_addr_r}\0" \ 309 "bootm ${kernel_addr_r}\0" \
311 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 310 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
312 "run nfsargs addip addtty addmtd addmisc;" \ 311 "run nfsargs addip addtty addmtd addmisc;" \
313 "bootm ${kernel_addr_r}\0" \ 312 "bootm ${kernel_addr_r}\0" \
314 "net_self=if run net_self_load;then " \ 313 "net_self=if run net_self_load;then " \
315 "run ramargs addip addtty addmtd addmisc;" \ 314 "run ramargs addip addtty addmtd addmisc;" \
316 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 315 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
317 "else echo Images not loades;fi\0" \ 316 "else echo Images not loades;fi\0" \
318 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 317 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
319 "load=tftp ${loadaddr} ${u-boot}\0" \ 318 "load=tftp ${loadaddr} ${u-boot}\0" \
320 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 319 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
321 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 320 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
322 "uboot_addr=0x80000\0" \ 321 "uboot_addr=0x80000\0" \
323 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 322 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
324 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 323 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
325 "updatemlo=nandecc hw;nand erase 0 20000;" \ 324 "updatemlo=nandecc hw;nand erase 0 20000;" \
326 "nand write ${loadaddr} 0 20000\0" \ 325 "nand write ${loadaddr} 0 20000\0" \
327 "upd=if run load;then echo Updating u-boot;if run update;" \ 326 "upd=if run load;then echo Updating u-boot;if run update;" \
328 "then echo U-Boot updated;" \ 327 "then echo U-Boot updated;" \
329 "else echo Error updating u-boot !;" \ 328 "else echo Error updating u-boot !;" \
330 "echo Board without bootloader !!;" \ 329 "echo Board without bootloader !!;" \
331 "fi;" \ 330 "fi;" \
332 "else echo U-Boot not downloaded..exiting;fi\0" \ 331 "else echo U-Boot not downloaded..exiting;fi\0" \
333 332
334 333
335 /* 334 /*
336 * this is common code for all TAM3517 boards. 335 * this is common code for all TAM3517 boards.
337 * MAC address is stored from manufacturer in 336 * MAC address is stored from manufacturer in
338 * I2C EEPROM 337 * I2C EEPROM
339 */ 338 */
340 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 339 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
341 /* 340 /*
342 * The I2C EEPROM on the TAM3517 contains 341 * The I2C EEPROM on the TAM3517 contains
343 * mac address and production data 342 * mac address and production data
344 */ 343 */
345 struct tam3517_module_info { 344 struct tam3517_module_info {
346 char customer[48]; 345 char customer[48];
347 char product[48]; 346 char product[48];
348 347
349 /* 348 /*
350 * bit 0~47 : sequence number 349 * bit 0~47 : sequence number
351 * bit 48~55 : week of year, from 0. 350 * bit 48~55 : week of year, from 0.
352 * bit 56~63 : year 351 * bit 56~63 : year
353 */ 352 */
354 unsigned long long sequence_number; 353 unsigned long long sequence_number;
355 354
356 /* 355 /*
357 * bit 0~7 : revision fixed 356 * bit 0~7 : revision fixed
358 * bit 8~15 : revision major 357 * bit 8~15 : revision major
359 * bit 16~31 : TNxxx 358 * bit 16~31 : TNxxx
360 */ 359 */
361 unsigned int revision; 360 unsigned int revision;
362 unsigned char eth_addr[4][8]; 361 unsigned char eth_addr[4][8];
363 unsigned char _rev[100]; 362 unsigned char _rev[100];
364 }; 363 };
365 364
366 #define TAM3517_READ_EEPROM(info, ret) \ 365 #define TAM3517_READ_EEPROM(info, ret) \
367 do { \ 366 do { \
368 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 367 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
369 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 368 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
370 (void *)info, sizeof(*info))) \ 369 (void *)info, sizeof(*info))) \
371 ret = 1; \ 370 ret = 1; \
372 else \ 371 else \
373 ret = 0; \ 372 ret = 0; \
374 } while (0) 373 } while (0)
375 374
376 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 375 #define TAM3517_READ_MAC_FROM_EEPROM(info) \
377 do { \ 376 do { \
378 char buf[80], ethname[20]; \ 377 char buf[80], ethname[20]; \
379 int i; \ 378 int i; \
380 memset(buf, 0, sizeof(buf)); \ 379 memset(buf, 0, sizeof(buf)); \
381 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 380 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
382 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 381 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
383 (info)->eth_addr[i][5], \ 382 (info)->eth_addr[i][5], \
384 (info)->eth_addr[i][4], \ 383 (info)->eth_addr[i][4], \
385 (info)->eth_addr[i][3], \ 384 (info)->eth_addr[i][3], \
386 (info)->eth_addr[i][2], \ 385 (info)->eth_addr[i][2], \
387 (info)->eth_addr[i][1], \ 386 (info)->eth_addr[i][1], \
388 (info)->eth_addr[i][0]); \ 387 (info)->eth_addr[i][0]); \
389 \ 388 \
390 if (i) \ 389 if (i) \
391 sprintf(ethname, "eth%daddr", i); \ 390 sprintf(ethname, "eth%daddr", i); \
392 else \ 391 else \
393 sprintf(ethname, "ethaddr"); \ 392 sprintf(ethname, "ethaddr"); \
394 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 393 printf("Setting %s from EEPROM with %s\n", ethname, buf);\
395 setenv(ethname, buf); \ 394 setenv(ethname, buf); \
396 } \ 395 } \
397 } while (0) 396 } while (0)
398 397
399 /* The following macros are taken from Technexion's documentation */ 398 /* The following macros are taken from Technexion's documentation */
400 #define TAM3517_sequence_number(info) \ 399 #define TAM3517_sequence_number(info) \
401 ((info)->sequence_number % 0x1000000000000LL) 400 ((info)->sequence_number % 0x1000000000000LL)
402 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 401 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
403 #define TAM3517_year(info) ((info)->sequence_number >> 56) 402 #define TAM3517_year(info) ((info)->sequence_number >> 56)
404 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 403 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
405 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 404 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
406 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 405 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
407 406
408 #define TAM3517_PRINT_SOM_INFO(info) \ 407 #define TAM3517_PRINT_SOM_INFO(info) \
409 do { \ 408 do { \
410 printf("Vendor:%s\n", (info)->customer); \ 409 printf("Vendor:%s\n", (info)->customer); \
411 printf("SOM: %s\n", (info)->product); \ 410 printf("SOM: %s\n", (info)->product); \
412 printf("SeqNr: %02llu%02llu%012llu\n", \ 411 printf("SeqNr: %02llu%02llu%012llu\n", \
413 TAM3517_year(info), \ 412 TAM3517_year(info), \
414 TAM3517_week_of_year(info), \ 413 TAM3517_week_of_year(info), \
415 TAM3517_sequence_number(info)); \ 414 TAM3517_sequence_number(info)); \
416 printf("Rev: TN%u %u.%u\n", \ 415 printf("Rev: TN%u %u.%u\n", \
417 TAM3517_revision_tn(info), \ 416 TAM3517_revision_tn(info), \
418 TAM3517_revision_major(info), \ 417 TAM3517_revision_major(info), \
419 TAM3517_revision_fixed(info)); \ 418 TAM3517_revision_fixed(info)); \
420 } while (0) 419 } while (0)
421 420
422 #endif 421 #endif
423 422
424 #endif /* __TAM3517_H */ 423 #endif /* __TAM3517_H */
425 424
include/configs/tao3530.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * Configuration settings for the TechNexion TAO-3530 SOM 2 * Configuration settings for the TechNexion TAO-3530 SOM
3 * equipped on Thunder baseboard. 3 * equipped on Thunder baseboard.
4 * 4 *
5 * Edward Lin <linuxfae@technexion.com> 5 * Edward Lin <linuxfae@technexion.com>
6 * Tapani Utriainen <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com>
7 * 7 *
8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
9 * 9 *
10 * SPDX-License-Identifier: GPL-2.0+ 10 * SPDX-License-Identifier: GPL-2.0+
11 */ 11 */
12 12
13 #ifndef __CONFIG_H 13 #ifndef __CONFIG_H
14 #define __CONFIG_H 14 #define __CONFIG_H
15 15
16 /* 16 /*
17 * High Level Configuration Options 17 * High Level Configuration Options
18 */ 18 */
19 #define CONFIG_OMAP /* in a TI OMAP core */ 19 #define CONFIG_OMAP /* in a TI OMAP core */
20 20
21 #define CONFIG_OMAP_GPIO 21 #define CONFIG_OMAP_GPIO
22 #define CONFIG_OMAP_COMMON 22 #define CONFIG_OMAP_COMMON
23 #define CONFIG_SYS_GENERIC_BOARD 23 #define CONFIG_SYS_GENERIC_BOARD
24 24
25 #define MACH_TYPE_OMAP3_TAO3530 2836 25 #define MACH_TYPE_OMAP3_TAO3530 2836
26 26
27 #define CONFIG_SDRC /* Has an SDRC controller */ 27 #define CONFIG_SDRC /* Has an SDRC controller */
28 28
29 #include <asm/arch/cpu.h> /* get chip and board defs */ 29 #include <asm/arch/cpu.h> /* get chip and board defs */
30 #include <asm/arch/omap3.h> 30 #include <asm/arch/omap3.h>
31 31
32 /* 32 /*
33 * Display CPU and Board information 33 * Display CPU and Board information
34 */ 34 */
35 #define CONFIG_DISPLAY_CPUINFO 35 #define CONFIG_DISPLAY_CPUINFO
36 #define CONFIG_DISPLAY_BOARDINFO 36 #define CONFIG_DISPLAY_BOARDINFO
37 37
38 /* Clock Defines */ 38 /* Clock Defines */
39 #define V_OSCK 26000000 /* Clock output from T2 */ 39 #define V_OSCK 26000000 /* Clock output from T2 */
40 #define V_SCLK (V_OSCK >> 1) 40 #define V_SCLK (V_OSCK >> 1)
41 41
42 #define CONFIG_MISC_INIT_R 42 #define CONFIG_MISC_INIT_R
43 43
44 #define CONFIG_OF_LIBFDT 44 #define CONFIG_OF_LIBFDT
45 45
46 #define CONFIG_CMDLINE_TAG 46 #define CONFIG_CMDLINE_TAG
47 #define CONFIG_SETUP_MEMORY_TAGS 47 #define CONFIG_SETUP_MEMORY_TAGS
48 #define CONFIG_INITRD_TAG 48 #define CONFIG_INITRD_TAG
49 #define CONFIG_REVISION_TAG 49 #define CONFIG_REVISION_TAG
50 50
51 /* 51 /*
52 * Size of malloc() pool 52 * Size of malloc() pool
53 */ 53 */
54 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 54 #define CONFIG_SYS_MALLOC_LEN (4 << 20)
55 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 55 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
56 56
57 /* 57 /*
58 * Hardware drivers 58 * Hardware drivers
59 */ 59 */
60 60
61 /* 61 /*
62 * NS16550 Configuration 62 * NS16550 Configuration
63 */ 63 */
64 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 64 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
65 65
66 #define CONFIG_SYS_NS16550 66 #define CONFIG_SYS_NS16550
67 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
69 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 69 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
70 70
71 /* 71 /*
72 * select serial console configuration 72 * select serial console configuration
73 */ 73 */
74 #define CONFIG_CONS_INDEX 3 74 #define CONFIG_CONS_INDEX 3
75 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
76 76
77 /* allow to overwrite serial and ethaddr */ 77 /* allow to overwrite serial and ethaddr */
78 #define CONFIG_ENV_OVERWRITE 78 #define CONFIG_ENV_OVERWRITE
79 #define CONFIG_BAUDRATE 115200 79 #define CONFIG_BAUDRATE 115200
80 #define CONFIG_GENERIC_MMC 80 #define CONFIG_GENERIC_MMC
81 #define CONFIG_MMC 81 #define CONFIG_MMC
82 #define CONFIG_OMAP_HSMMC 82 #define CONFIG_OMAP_HSMMC
83 #define CONFIG_DOS_PARTITION 83 #define CONFIG_DOS_PARTITION
84 84
85 /* GPIO banks */ 85 /* GPIO banks */
86 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 86 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
87 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 87 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
88 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 88 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
89 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 89 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
90 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 90 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
91 91
92 /* commands to include */ 92 /* commands to include */
93 #include <config_cmd_default.h> 93 #include <config_cmd_default.h>
94 94
95 #define CONFIG_CMD_CACHE 95 #define CONFIG_CMD_CACHE
96 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 96 #define CONFIG_CMD_EXT2 /* EXT2 Support */
97 #define CONFIG_CMD_FAT /* FAT support */ 97 #define CONFIG_CMD_FAT /* FAT support */
98 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 98 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
99 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 99 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
100 #define MTDIDS_DEFAULT "nand0=nand" 100 #define MTDIDS_DEFAULT "nand0=nand"
101 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 101 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
102 "1920k(u-boot),128k(u-boot-env),"\ 102 "1920k(u-boot),128k(u-boot-env),"\
103 "4m(kernel),-(fs)" 103 "4m(kernel),-(fs)"
104 104
105 #define CONFIG_CMD_I2C /* I2C serial bus support */ 105 #define CONFIG_CMD_I2C /* I2C serial bus support */
106 #define CONFIG_CMD_MMC /* MMC support */ 106 #define CONFIG_CMD_MMC /* MMC support */
107 #define CONFIG_CMD_NAND /* NAND support */ 107 #define CONFIG_CMD_NAND /* NAND support */
108 #define CONFIG_CMD_DHCP 108 #define CONFIG_CMD_DHCP
109 #define CONFIG_CMD_PING 109 #define CONFIG_CMD_PING
110 110
111 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 111 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
112 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 112 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
113 #undef CONFIG_CMD_IMI /* iminfo */ 113 #undef CONFIG_CMD_IMI /* iminfo */
114 #undef CONFIG_CMD_IMLS /* List all found images */ 114 #undef CONFIG_CMD_IMLS /* List all found images */
115 115
116 #define CONFIG_SYS_NO_FLASH 116 #define CONFIG_SYS_NO_FLASH
117 #define CONFIG_SYS_I2C 117 #define CONFIG_SYS_I2C
118 #define CONFIG_SYS_I2C_OMAP34XX 118 #define CONFIG_SYS_I2C_OMAP34XX
119 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 119 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
120 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 120 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
121 #define CONFIG_I2C_MULTI_BUS 121 #define CONFIG_I2C_MULTI_BUS
122 122
123 /* 123 /*
124 * TWL4030 124 * TWL4030
125 */ 125 */
126 #define CONFIG_TWL4030_POWER 126 #define CONFIG_TWL4030_POWER
127 #define CONFIG_TWL4030_LED 127 #define CONFIG_TWL4030_LED
128 128
129 /* 129 /*
130 * Board NAND Info. 130 * Board NAND Info.
131 */ 131 */
132 #define CONFIG_SYS_NAND_QUIET_TEST 132 #define CONFIG_SYS_NAND_QUIET_TEST
133 #define CONFIG_NAND_OMAP_GPMC 133 #define CONFIG_NAND_OMAP_GPMC
134 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 134 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
135 /* to access nand */ 135 /* to access nand */
136 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 136 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
137 /* to access nand at */ 137 /* to access nand at */
138 /* CS0 */ 138 /* CS0 */
139 139
140 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 140 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
141 /* devices */ 141 /* devices */
142 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 142 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
143 /* Environment information */ 143 /* Environment information */
144 #define CONFIG_BOOTDELAY 3 144 #define CONFIG_BOOTDELAY 3
145 145
146 #define CONFIG_EXTRA_ENV_SETTINGS \ 146 #define CONFIG_EXTRA_ENV_SETTINGS \
147 "loadaddr=0x82000000\0" \ 147 "loadaddr=0x82000000\0" \
148 "console=ttyO2,115200n8\0" \ 148 "console=ttyO2,115200n8\0" \
149 "mpurate=600\0" \ 149 "mpurate=600\0" \
150 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 150 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
151 "tv_mode=omapfb.mode=tv:ntsc\0" \ 151 "tv_mode=omapfb.mode=tv:ntsc\0" \
152 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 152 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
153 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 153 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
154 "extra_options= \0" \ 154 "extra_options= \0" \
155 "mmcdev=0\0" \ 155 "mmcdev=0\0" \
156 "mmcroot=/dev/mmcblk0p2 rw\0" \ 156 "mmcroot=/dev/mmcblk0p2 rw\0" \
157 "mmcrootfstype=ext3 rootwait\0" \ 157 "mmcrootfstype=ext3 rootwait\0" \
158 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 158 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
159 "nandrootfstype=ubifs\0" \ 159 "nandrootfstype=ubifs\0" \
160 "mmcargs=setenv bootargs console=${console} " \ 160 "mmcargs=setenv bootargs console=${console} " \
161 "mpurate=${mpurate} " \ 161 "mpurate=${mpurate} " \
162 "${video_mode} " \ 162 "${video_mode} " \
163 "root=${mmcroot} " \ 163 "root=${mmcroot} " \
164 "rootfstype=${mmcrootfstype} " \ 164 "rootfstype=${mmcrootfstype} " \
165 "${extra_options}\0" \ 165 "${extra_options}\0" \
166 "nandargs=setenv bootargs console=${console} " \ 166 "nandargs=setenv bootargs console=${console} " \
167 "mpurate=${mpurate} " \ 167 "mpurate=${mpurate} " \
168 "${video_mode} " \ 168 "${video_mode} " \
169 "${network_setting} " \ 169 "${network_setting} " \
170 "root=${nandroot} " \ 170 "root=${nandroot} " \
171 "rootfstype=${nandrootfstype} "\ 171 "rootfstype=${nandrootfstype} "\
172 "${extra_options}\0" \ 172 "${extra_options}\0" \
173 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 173 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
174 "bootscript=echo Running bootscript from mmc ...; " \ 174 "bootscript=echo Running bootscript from mmc ...; " \
175 "source ${loadaddr}\0" \ 175 "source ${loadaddr}\0" \
176 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 176 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
177 "mmcboot=echo Booting from mmc ...; " \ 177 "mmcboot=echo Booting from mmc ...; " \
178 "run mmcargs; " \ 178 "run mmcargs; " \
179 "bootm ${loadaddr}\0" \ 179 "bootm ${loadaddr}\0" \
180 "nandboot=echo Booting from nand ...; " \ 180 "nandboot=echo Booting from nand ...; " \
181 "run nandargs; " \ 181 "run nandargs; " \
182 "nand read ${loadaddr} 280000 400000; " \ 182 "nand read ${loadaddr} 280000 400000; " \
183 "bootm ${loadaddr}\0" \ 183 "bootm ${loadaddr}\0" \
184 184
185 #define CONFIG_BOOTCOMMAND \ 185 #define CONFIG_BOOTCOMMAND \
186 "if mmc rescan ${mmcdev}; then " \ 186 "if mmc rescan ${mmcdev}; then " \
187 "if run loadbootscript; then " \ 187 "if run loadbootscript; then " \
188 "run bootscript; " \ 188 "run bootscript; " \
189 "else " \ 189 "else " \
190 "if run loaduimage; then " \ 190 "if run loaduimage; then " \
191 "run mmcboot; " \ 191 "run mmcboot; " \
192 "else run nandboot; " \ 192 "else run nandboot; " \
193 "fi; " \ 193 "fi; " \
194 "fi; " \ 194 "fi; " \
195 "else run nandboot; fi" 195 "else run nandboot; fi"
196 196
197 /* 197 /*
198 * Miscellaneous configurable options 198 * Miscellaneous configurable options
199 */ 199 */
200 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 200 #define CONFIG_SYS_LONGHELP /* undef to save memory */
201 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 201 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
202 #define CONFIG_SYS_PROMPT "TAO-3530 # " 202 #define CONFIG_SYS_PROMPT "TAO-3530 # "
203 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 203 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
204 204
205 /* turn on command-line edit/hist/auto */ 205 /* turn on command-line edit/hist/auto */
206 #define CONFIG_CMDLINE_EDITING 206 #define CONFIG_CMDLINE_EDITING
207 #define CONFIG_COMMAND_HISTORY 207 #define CONFIG_COMMAND_HISTORY
208 #define CONFIG_AUTO_COMPLETE 208 #define CONFIG_AUTO_COMPLETE
209 209
210 /* Print Buffer Size */ 210 /* Print Buffer Size */
211 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 211 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
212 sizeof(CONFIG_SYS_PROMPT) + 16) 212 sizeof(CONFIG_SYS_PROMPT) + 16)
213 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 213 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
214 /* Boot Argument Buffer Size */ 214 /* Boot Argument Buffer Size */
215 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 215 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
216 216
217 #define CONFIG_SYS_ALT_MEMTEST 1 217 #define CONFIG_SYS_ALT_MEMTEST 1
218 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 218 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
219 /* defaults */ 219 /* defaults */
220 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 220 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
221 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 221 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
222 222
223 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 223 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
224 /* load address */ 224 /* load address */
225 #define CONFIG_SYS_TEXT_BASE 0x80008000 225 #define CONFIG_SYS_TEXT_BASE 0x80008000
226 226
227 /* 227 /*
228 * OMAP3 has 12 GP timers, they can be driven by the system clock 228 * OMAP3 has 12 GP timers, they can be driven by the system clock
229 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 229 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
230 * This rate is divided by a local divisor. 230 * This rate is divided by a local divisor.
231 */ 231 */
232 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 232 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
233 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 233 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
234 234
235 /* 235 /*
236 * Stack sizes 236 * Stack sizes
237 * 237 *
238 * The stack sizes are set up in start.S using the settings below 238 * The stack sizes are set up in start.S using the settings below
239 */ 239 */
240 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 240 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
241 241
242 /* 242 /*
243 * Physical Memory Map 243 * Physical Memory Map
244 */ 244 */
245 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 245 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
246 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 246 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
247 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 247 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
248 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 248 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
249 249
250 /* 250 /*
251 * FLASH and environment organization 251 * FLASH and environment organization
252 */ 252 */
253 253
254 /* **** PISMO SUPPORT *** */ 254 /* **** PISMO SUPPORT *** */
255 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 255 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
256 #define CONFIG_SYS_FLASH_BASE NAND_BASE 256 #define CONFIG_SYS_FLASH_BASE NAND_BASE
257 257
258 /* Monitor at start of flash */ 258 /* Monitor at start of flash */
259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
260 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 260 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
261 261
262 #define CONFIG_ENV_IS_IN_NAND 1 262 #define CONFIG_ENV_IS_IN_NAND 1
263 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 263 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
264 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 264 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
265 265
266 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 266 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
267 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 267 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
268 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 268 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
269 269
270 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 270 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
271 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 271 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
272 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 272 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
273 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 273 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
274 CONFIG_SYS_INIT_RAM_SIZE - \ 274 CONFIG_SYS_INIT_RAM_SIZE - \
275 GENERATED_GBL_DATA_SIZE) 275 GENERATED_GBL_DATA_SIZE)
276 276
277 #define CONFIG_OMAP3_SPI 277 #define CONFIG_OMAP3_SPI
278 278
279 /* 279 /*
280 * USB 280 * USB
281 * 281 *
282 * Currently only EHCI is enabled, the MUSB OTG controller 282 * Currently only EHCI is enabled, the MUSB OTG controller
283 * is not enabled. 283 * is not enabled.
284 */ 284 */
285 285
286 /* USB EHCI */ 286 /* USB EHCI */
287 #define CONFIG_CMD_USB 287 #define CONFIG_CMD_USB
288 #define CONFIG_USB_EHCI 288 #define CONFIG_USB_EHCI
289 #define CONFIG_USB_EHCI_OMAP 289 #define CONFIG_USB_EHCI_OMAP
290 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 290 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
291 291
292 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 292 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
293 #define CONFIG_USB_HOST_ETHER 293 #define CONFIG_USB_HOST_ETHER
294 #define CONFIG_USB_ETHER_SMSC95XX 294 #define CONFIG_USB_ETHER_SMSC95XX
295 295
296 #define CONFIG_USB_ETHER 296 #define CONFIG_USB_ETHER
297 #define CONFIG_USB_ETHER_RNDIS 297 #define CONFIG_USB_ETHER_RNDIS
298 #define CONFIG_USB_STORAGE 298 #define CONFIG_USB_STORAGE
299 #define CONGIG_CMD_STORAGE 299 #define CONGIG_CMD_STORAGE
300 300
301 /* Defines for SPL */ 301 /* Defines for SPL */
302 #define CONFIG_SPL_FRAMEWORK 302 #define CONFIG_SPL_FRAMEWORK
303 #define CONFIG_SPL_NAND_SIMPLE 303 #define CONFIG_SPL_NAND_SIMPLE
304 304
305 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 305 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
306 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 306 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
307 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 307 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
308 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 308 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
309 309
310 #define CONFIG_SPL_BOARD_INIT 310 #define CONFIG_SPL_BOARD_INIT
311 #define CONFIG_SPL_LIBCOMMON_SUPPORT 311 #define CONFIG_SPL_LIBCOMMON_SUPPORT
312 #define CONFIG_SPL_LIBDISK_SUPPORT 312 #define CONFIG_SPL_LIBDISK_SUPPORT
313 #define CONFIG_SPL_I2C_SUPPORT 313 #define CONFIG_SPL_I2C_SUPPORT
314 #define CONFIG_SPL_LIBGENERIC_SUPPORT 314 #define CONFIG_SPL_LIBGENERIC_SUPPORT
315 #define CONFIG_SPL_MMC_SUPPORT 315 #define CONFIG_SPL_MMC_SUPPORT
316 #define CONFIG_SPL_FAT_SUPPORT 316 #define CONFIG_SPL_FAT_SUPPORT
317 #define CONFIG_SPL_SERIAL_SUPPORT 317 #define CONFIG_SPL_SERIAL_SUPPORT
318 #define CONFIG_SPL_NAND_SUPPORT 318 #define CONFIG_SPL_NAND_SUPPORT
319 #define CONFIG_SPL_NAND_BASE 319 #define CONFIG_SPL_NAND_BASE
320 #define CONFIG_SPL_NAND_DRIVERS 320 #define CONFIG_SPL_NAND_DRIVERS
321 #define CONFIG_SPL_NAND_ECC 321 #define CONFIG_SPL_NAND_ECC
322 #define CONFIG_SPL_GPIO_SUPPORT 322 #define CONFIG_SPL_GPIO_SUPPORT
323 #define CONFIG_SPL_POWER_SUPPORT 323 #define CONFIG_SPL_POWER_SUPPORT
324 #define CONFIG_SPL_OMAP3_ID_NAND 324 #define CONFIG_SPL_OMAP3_ID_NAND
325 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 325 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
326 326
327 /* NAND boot config */ 327 /* NAND boot config */
328 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 328 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
329 #define CONFIG_SYS_NAND_PAGE_COUNT 64 329 #define CONFIG_SYS_NAND_PAGE_COUNT 64
330 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 330 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
331 #define CONFIG_SYS_NAND_OOBSIZE 64 331 #define CONFIG_SYS_NAND_OOBSIZE 64
332 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 332 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
333 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 333 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
334 /* 334 /*
335 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 335 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
336 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 336 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
337 */ 337 */
338 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 338 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
339 10, 11, 12, 13 } 339 10, 11, 12, 13 }
340 #define CONFIG_SYS_NAND_ECCSIZE 512 340 #define CONFIG_SYS_NAND_ECCSIZE 512
341 #define CONFIG_SYS_NAND_ECCBYTES 3 341 #define CONFIG_SYS_NAND_ECCBYTES 3
342 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 342 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
343 343
344 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 344 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
345 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 345 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
346 346
347 #define CONFIG_SPL_TEXT_BASE 0x40200800 347 #define CONFIG_SPL_TEXT_BASE 0x40200800
348 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 348 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
349 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
350 349
351 /* 350 /*
352 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 351 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
353 * older x-loader implementations. And move the BSS area so that it 352 * older x-loader implementations. And move the BSS area so that it
354 * doesn't overlap with TEXT_BASE. 353 * doesn't overlap with TEXT_BASE.
355 */ 354 */
356 #define CONFIG_SYS_TEXT_BASE 0x80008000 355 #define CONFIG_SYS_TEXT_BASE 0x80008000
357 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 356 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
358 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 357 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
359 358
360 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 359 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
361 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 360 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
362 361
363 #endif /* __CONFIG_H */ 362 #endif /* __CONFIG_H */
364 363
include/configs/ti814x_evm.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * ti814x_evm.h 2 * ti814x_evm.h
3 * 3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as 7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2. 8 * published by the Free Software Foundation version 2.
9 * 9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty 11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 #ifndef __CONFIG_TI814X_EVM_H 16 #ifndef __CONFIG_TI814X_EVM_H
17 #define __CONFIG_TI814X_EVM_H 17 #define __CONFIG_TI814X_EVM_H
18 18
19 #define CONFIG_TI81XX 19 #define CONFIG_TI81XX
20 #define CONFIG_TI814X 20 #define CONFIG_TI814X
21 #define CONFIG_SYS_NO_FLASH 21 #define CONFIG_SYS_NO_FLASH
22 #define CONFIG_OMAP 22 #define CONFIG_OMAP
23 #define CONFIG_OMAP_COMMON 23 #define CONFIG_OMAP_COMMON
24 24
25 #include <asm/arch/omap.h> 25 #include <asm/arch/omap.h>
26 26
27 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 27 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
28 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 28 #define CONFIG_SYS_MALLOC_LEN (1024 << 10)
29 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 29 #define CONFIG_SYS_LONGHELP /* undef to save memory */
30 #define CONFIG_SYS_HUSH_PARSER /* Use HUSH for command parsing */ 30 #define CONFIG_SYS_HUSH_PARSER /* Use HUSH for command parsing */
31 #define CONFIG_SYS_PROMPT "U-Boot# " 31 #define CONFIG_SYS_PROMPT "U-Boot# "
32 #define CONFIG_SYS_NO_FLASH 32 #define CONFIG_SYS_NO_FLASH
33 #define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM 33 #define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM
34 34
35 #define CONFIG_OF_LIBFDT 35 #define CONFIG_OF_LIBFDT
36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
37 #define CONFIG_SETUP_MEMORY_TAGS 37 #define CONFIG_SETUP_MEMORY_TAGS
38 #define CONFIG_INITRD_TAG /* for ramdisk support */ 38 #define CONFIG_INITRD_TAG /* for ramdisk support */
39 39
40 /* commands to include */ 40 /* commands to include */
41 # include <config_cmd_default.h> 41 # include <config_cmd_default.h>
42 42
43 #define CONFIG_CMD_ASKENV 43 #define CONFIG_CMD_ASKENV
44 #define CONFIG_VERSION_VARIABLE 44 #define CONFIG_VERSION_VARIABLE
45 45
46 #define CONFIG_BOOTDELAY 1 /* negative for no autoboot */ 46 #define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
47 #define CONFIG_ENV_VARS_UBOOT_CONFIG 47 #define CONFIG_ENV_VARS_UBOOT_CONFIG
48 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 48 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
49 #define CONFIG_EXTRA_ENV_SETTINGS \ 49 #define CONFIG_EXTRA_ENV_SETTINGS \
50 "loadaddr=0x80200000\0" \ 50 "loadaddr=0x80200000\0" \
51 "fdtaddr=0x80F80000\0" \ 51 "fdtaddr=0x80F80000\0" \
52 "rdaddr=0x81000000\0" \ 52 "rdaddr=0x81000000\0" \
53 "bootfile=/boot/uImage\0" \ 53 "bootfile=/boot/uImage\0" \
54 "fdtfile=\0" \ 54 "fdtfile=\0" \
55 "console=ttyO0,115200n8\0" \ 55 "console=ttyO0,115200n8\0" \
56 "optargs=\0" \ 56 "optargs=\0" \
57 "mmcdev=0\0" \ 57 "mmcdev=0\0" \
58 "mmcroot=/dev/mmcblk0p2 ro\0" \ 58 "mmcroot=/dev/mmcblk0p2 ro\0" \
59 "mmcrootfstype=ext4 rootwait\0" \ 59 "mmcrootfstype=ext4 rootwait\0" \
60 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ 60 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
61 "ramrootfstype=ext2\0" \ 61 "ramrootfstype=ext2\0" \
62 "mmcargs=setenv bootargs console=${console} " \ 62 "mmcargs=setenv bootargs console=${console} " \
63 "${optargs} " \ 63 "${optargs} " \
64 "root=${mmcroot} " \ 64 "root=${mmcroot} " \
65 "rootfstype=${mmcrootfstype}\0" \ 65 "rootfstype=${mmcrootfstype}\0" \
66 "bootenv=uEnv.txt\0" \ 66 "bootenv=uEnv.txt\0" \
67 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ 67 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
68 "importbootenv=echo Importing environment from mmc ...; " \ 68 "importbootenv=echo Importing environment from mmc ...; " \
69 "env import -t $loadaddr $filesize\0" \ 69 "env import -t $loadaddr $filesize\0" \
70 "ramargs=setenv bootargs console=${console} " \ 70 "ramargs=setenv bootargs console=${console} " \
71 "${optargs} " \ 71 "${optargs} " \
72 "root=${ramroot} " \ 72 "root=${ramroot} " \
73 "rootfstype=${ramrootfstype}\0" \ 73 "rootfstype=${ramrootfstype}\0" \
74 "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ 74 "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
75 "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ 75 "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
76 "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ 76 "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
77 "mmcboot=echo Booting from mmc ...; " \ 77 "mmcboot=echo Booting from mmc ...; " \
78 "run mmcargs; " \ 78 "run mmcargs; " \
79 "bootm ${loadaddr}\0" \ 79 "bootm ${loadaddr}\0" \
80 "ramboot=echo Booting from ramdisk ...; " \ 80 "ramboot=echo Booting from ramdisk ...; " \
81 "run ramargs; " \ 81 "run ramargs; " \
82 "bootm ${loadaddr}\0" \ 82 "bootm ${loadaddr}\0" \
83 "fdtfile=ti814x-evm.dtb\0" \ 83 "fdtfile=ti814x-evm.dtb\0" \
84 84
85 #define CONFIG_BOOTCOMMAND \ 85 #define CONFIG_BOOTCOMMAND \
86 "mmc dev ${mmcdev}; if mmc rescan; then " \ 86 "mmc dev ${mmcdev}; if mmc rescan; then " \
87 "echo SD/MMC found on device ${mmcdev};" \ 87 "echo SD/MMC found on device ${mmcdev};" \
88 "if run loadbootenv; then " \ 88 "if run loadbootenv; then " \
89 "echo Loaded environment from ${bootenv};" \ 89 "echo Loaded environment from ${bootenv};" \
90 "run importbootenv;" \ 90 "run importbootenv;" \
91 "fi;" \ 91 "fi;" \
92 "if test -n $uenvcmd; then " \ 92 "if test -n $uenvcmd; then " \
93 "echo Running uenvcmd ...;" \ 93 "echo Running uenvcmd ...;" \
94 "run uenvcmd;" \ 94 "run uenvcmd;" \
95 "fi;" \ 95 "fi;" \
96 "if run loaduimage; then " \ 96 "if run loaduimage; then " \
97 "run mmcboot;" \ 97 "run mmcboot;" \
98 "fi;" \ 98 "fi;" \
99 "fi;" \ 99 "fi;" \
100 100
101 /* Clock Defines */ 101 /* Clock Defines */
102 #define V_OSCK 24000000 /* Clock output from T2 */ 102 #define V_OSCK 24000000 /* Clock output from T2 */
103 #define V_SCLK (V_OSCK >> 1) 103 #define V_SCLK (V_OSCK >> 1)
104 104
105 #define CONFIG_CMD_ECHO 105 #define CONFIG_CMD_ECHO
106 106
107 /* max number of command args */ 107 /* max number of command args */
108 #define CONFIG_SYS_MAXARGS 16 108 #define CONFIG_SYS_MAXARGS 16
109 109
110 /* Console I/O Buffer Size */ 110 /* Console I/O Buffer Size */
111 #define CONFIG_SYS_CBSIZE 512 111 #define CONFIG_SYS_CBSIZE 512
112 112
113 /* Print Buffer Size */ 113 /* Print Buffer Size */
114 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 114 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
115 + sizeof(CONFIG_SYS_PROMPT) + 16) 115 + sizeof(CONFIG_SYS_PROMPT) + 16)
116 116
117 /* Boot Argument Buffer Size */ 117 /* Boot Argument Buffer Size */
118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
119 119
120 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 120 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
121 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ 121 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
122 + PHYS_DRAM_1_SIZE - (8 << 12)) 122 + PHYS_DRAM_1_SIZE - (8 << 12))
123 123
124 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ 124 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */
125 125
126 #define CONFIG_OMAP_GPIO 126 #define CONFIG_OMAP_GPIO
127 #define CONFIG_MMC 127 #define CONFIG_MMC
128 #define CONFIG_GENERIC_MMC 128 #define CONFIG_GENERIC_MMC
129 #define CONFIG_OMAP_HSMMC 129 #define CONFIG_OMAP_HSMMC
130 #define CONFIG_CMD_MMC 130 #define CONFIG_CMD_MMC
131 #define CONFIG_DOS_PARTITION 131 #define CONFIG_DOS_PARTITION
132 #define CONFIG_CMD_FAT 132 #define CONFIG_CMD_FAT
133 #define CONFIG_CMD_EXT2 133 #define CONFIG_CMD_EXT2
134 134
135 /** 135 /**
136 * Physical Memory Map 136 * Physical Memory Map
137 */ 137 */
138 #define CONFIG_NR_DRAM_BANKS 1 /* 1 banks of DRAM */ 138 #define CONFIG_NR_DRAM_BANKS 1 /* 1 banks of DRAM */
139 #define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ 139 #define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */
140 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ 140 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */
141 141
142 #define CONFIG_SYS_SDRAM_BASE 0x80000000 142 #define CONFIG_SYS_SDRAM_BASE 0x80000000
143 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 143 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
144 GENERATED_GBL_DATA_SIZE) 144 GENERATED_GBL_DATA_SIZE)
145 145
146 /** 146 /**
147 * Platform/Board specific defs 147 * Platform/Board specific defs
148 */ 148 */
149 #define CONFIG_SYS_TIMERBASE 0x4802E000 149 #define CONFIG_SYS_TIMERBASE 0x4802E000
150 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 150 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
151 151
152 /* NS16550 Configuration */ 152 /* NS16550 Configuration */
153 #define CONFIG_SYS_NS16550 153 #define CONFIG_SYS_NS16550
154 #define CONFIG_SYS_NS16550_SERIAL 154 #define CONFIG_SYS_NS16550_SERIAL
155 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 155 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
156 #define CONFIG_SYS_NS16550_CLK (48000000) 156 #define CONFIG_SYS_NS16550_CLK (48000000)
157 #define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ 157 #define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
158 158
159 #define CONFIG_BAUDRATE 115200 159 #define CONFIG_BAUDRATE 115200
160 160
161 /* CPU */ 161 /* CPU */
162 #define CONFIG_ARCH_CPU_INIT 162 #define CONFIG_ARCH_CPU_INIT
163 163
164 #define CONFIG_ENV_OVERWRITE 164 #define CONFIG_ENV_OVERWRITE
165 #define CONFIG_CONS_INDEX 1 165 #define CONFIG_CONS_INDEX 1
166 #define CONFIG_SYS_CONSOLE_INFO_QUIET 166 #define CONFIG_SYS_CONSOLE_INFO_QUIET
167 167
168 #define CONFIG_ENV_IS_NOWHERE 168 #define CONFIG_ENV_IS_NOWHERE
169 169
170 /* Defines for SPL */ 170 /* Defines for SPL */
171 #define CONFIG_SPL_FRAMEWORK 171 #define CONFIG_SPL_FRAMEWORK
172 #define CONFIG_SPL_TEXT_BASE 0x40300000 172 #define CONFIG_SPL_TEXT_BASE 0x40300000
173 #define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) 173 #define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
174 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
175 174
176 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 175 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
177 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 176 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
178 177
179 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 178 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
180 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 179 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
181 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 180 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
182 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 181 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
183 #define CONFIG_SPL_MMC_SUPPORT 182 #define CONFIG_SPL_MMC_SUPPORT
184 #define CONFIG_SPL_FAT_SUPPORT 183 #define CONFIG_SPL_FAT_SUPPORT
185 184
186 #define CONFIG_SPL_LIBCOMMON_SUPPORT 185 #define CONFIG_SPL_LIBCOMMON_SUPPORT
187 #define CONFIG_SPL_LIBDISK_SUPPORT 186 #define CONFIG_SPL_LIBDISK_SUPPORT
188 #define CONFIG_SPL_LIBGENERIC_SUPPORT 187 #define CONFIG_SPL_LIBGENERIC_SUPPORT
189 #define CONFIG_SPL_SERIAL_SUPPORT 188 #define CONFIG_SPL_SERIAL_SUPPORT
190 #define CONFIG_SPL_GPIO_SUPPORT 189 #define CONFIG_SPL_GPIO_SUPPORT
191 #define CONFIG_SPL_YMODEM_SUPPORT 190 #define CONFIG_SPL_YMODEM_SUPPORT
192 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 191 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
193 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 192 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
194 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 193 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
195 194
196 #define CONFIG_SPL_BOARD_INIT 195 #define CONFIG_SPL_BOARD_INIT
197 196
198 /* 197 /*
199 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 198 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
200 * 64 bytes before this address should be set aside for u-boot.img's 199 * 64 bytes before this address should be set aside for u-boot.img's
201 * header. That is 0x800FFFC0--0x80800000 should not be used for any 200 * header. That is 0x800FFFC0--0x80800000 should not be used for any
202 * other needs. 201 * other needs.
203 */ 202 */
204 #define CONFIG_SYS_TEXT_BASE 0x80800000 203 #define CONFIG_SYS_TEXT_BASE 0x80800000
205 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 204 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
206 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 205 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
207 206
208 /* 207 /*
209 * Since SPL did pll and ddr initialization for us, 208 * Since SPL did pll and ddr initialization for us,
210 * we don't need to do it twice. 209 * we don't need to do it twice.
211 */ 210 */
212 #ifndef CONFIG_SPL_BUILD 211 #ifndef CONFIG_SPL_BUILD
213 #define CONFIG_SKIP_LOWLEVEL_INIT 212 #define CONFIG_SKIP_LOWLEVEL_INIT
214 #endif 213 #endif
215 214
216 /* Unsupported features */ 215 /* Unsupported features */
217 #undef CONFIG_USE_IRQ 216 #undef CONFIG_USE_IRQ
218 217
219 /* Ethernet */ 218 /* Ethernet */
220 #define CONFIG_CMD_NET 219 #define CONFIG_CMD_NET
221 #define CONFIG_CMD_DHCP 220 #define CONFIG_CMD_DHCP
222 #define CONFIG_CMD_PING 221 #define CONFIG_CMD_PING
223 #define CONFIG_CMD_MII 222 #define CONFIG_CMD_MII
224 #define CONFIG_DRIVER_TI_CPSW 223 #define CONFIG_DRIVER_TI_CPSW
225 #define CONFIG_MII 224 #define CONFIG_MII
226 #define CONFIG_BOOTP_DNS 225 #define CONFIG_BOOTP_DNS
227 #define CONFIG_BOOTP_DNS2 226 #define CONFIG_BOOTP_DNS2
228 #define CONFIG_BOOTP_SEND_HOSTNAME 227 #define CONFIG_BOOTP_SEND_HOSTNAME
229 #define CONFIG_BOOTP_GATEWAY 228 #define CONFIG_BOOTP_GATEWAY
230 #define CONFIG_BOOTP_SUBNETMASK 229 #define CONFIG_BOOTP_SUBNETMASK
231 #define CONFIG_NET_RETRY_COUNT 10 230 #define CONFIG_NET_RETRY_COUNT 10
232 #define CONFIG_NET_MULTI 231 #define CONFIG_NET_MULTI
233 #define CONFIG_PHY_GIGE 232 #define CONFIG_PHY_GIGE
234 #define CONFIG_PHYLIB 233 #define CONFIG_PHYLIB
235 #define CONFIG_PHY_ET1011C 234 #define CONFIG_PHY_ET1011C
236 #define CONFIG_PHY_ET1011C_TX_CLK_FIX 235 #define CONFIG_PHY_ET1011C_TX_CLK_FIX
237 236
238 #endif /* ! __CONFIG_TI814X_EVM_H */ 237 #endif /* ! __CONFIG_TI814X_EVM_H */
239 238
include/configs/ti816x_evm.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * ti816x_evm.h 2 * ti816x_evm.h
3 * 3 *
4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5 * Antoine Tenart, <atenart@adeneo-embedded.com> 5 * Antoine Tenart, <atenart@adeneo-embedded.com>
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #ifndef __CONFIG_TI816X_EVM_H 10 #ifndef __CONFIG_TI816X_EVM_H
11 #define __CONFIG_TI816X_EVM_H 11 #define __CONFIG_TI816X_EVM_H
12 12
13 #define CONFIG_TI81XX 13 #define CONFIG_TI81XX
14 #define CONFIG_TI816X 14 #define CONFIG_TI816X
15 #define CONFIG_SYS_NO_FLASH 15 #define CONFIG_SYS_NO_FLASH
16 #define CONFIG_OMAP 16 #define CONFIG_OMAP
17 #define CONFIG_OMAP_COMMON 17 #define CONFIG_OMAP_COMMON
18 18
19 #define CONFIG_ARCH_CPU_INIT 19 #define CONFIG_ARCH_CPU_INIT
20 20
21 #include <asm/arch/omap.h> 21 #include <asm/arch/omap.h>
22 22
23 #define CONFIG_ENV_SIZE 0x2000 23 #define CONFIG_ENV_SIZE 0x2000
24 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) 24 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
25 #define CONFIG_SYS_LONGHELP /* undef save memory */ 25 #define CONFIG_SYS_LONGHELP /* undef save memory */
26 #define CONFIG_SYS_HUSH_PARSER 26 #define CONFIG_SYS_HUSH_PARSER
27 #define CONFIG_SYS_PROMPT "u-boot/ti816x# " 27 #define CONFIG_SYS_PROMPT "u-boot/ti816x# "
28 #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM 28 #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
29 29
30 #define CONFIG_OF_LIBFDT 30 #define CONFIG_OF_LIBFDT
31 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 31 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
32 #define CONFIG_SETUP_MEMORY_TAGS 32 #define CONFIG_SETUP_MEMORY_TAGS
33 #define CONFIG_INITRD_TAG /* required for ramdisk support */ 33 #define CONFIG_INITRD_TAG /* required for ramdisk support */
34 34
35 #include <config_cmd_default.h> /* u-boot default commands */ 35 #include <config_cmd_default.h> /* u-boot default commands */
36 36
37 #define CONFIG_VERSION_VARIABLE 37 #define CONFIG_VERSION_VARIABLE
38 #define CONFIG_DISPLAY_CPUINFO 38 #define CONFIG_DISPLAY_CPUINFO
39 39
40 #define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */ 40 #define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */
41 #define CONFIG_EXTRA_ENV_SETTINGS \ 41 #define CONFIG_EXTRA_ENV_SETTINGS \
42 "loadaddr=0x81000000\0" \ 42 "loadaddr=0x81000000\0" \
43 43
44 #define CONFIG_BOOTCOMMAND \ 44 #define CONFIG_BOOTCOMMAND \
45 "mmc rescan;" \ 45 "mmc rescan;" \
46 "fatload mmc 0 ${loadaddr} uImage;" \ 46 "fatload mmc 0 ${loadaddr} uImage;" \
47 "bootm ${loadaddr}" \ 47 "bootm ${loadaddr}" \
48 48
49 #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" 49 #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
50 50
51 /* Clock Defines */ 51 /* Clock Defines */
52 #define V_OSCK 24000000 /* Clock output from T2 */ 52 #define V_OSCK 24000000 /* Clock output from T2 */
53 #define V_SCLK (V_OSCK >> 1) 53 #define V_SCLK (V_OSCK >> 1)
54 54
55 #define CONFIG_SYS_MAXARGS 32 55 #define CONFIG_SYS_MAXARGS 32
56 #define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ 56 #define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
57 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 57 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
58 + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ 58 + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ 59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
60 60
61 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ 61 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
62 62
63 #define CONFIG_CMD_ASKEN 63 #define CONFIG_CMD_ASKEN
64 #define CONFIG_CMD_ECHO 64 #define CONFIG_CMD_ECHO
65 #define CONFIG_OMAP_GPIO 65 #define CONFIG_OMAP_GPIO
66 #define CONFIG_MMC 66 #define CONFIG_MMC
67 #define CONFIG_GENERIC_MMC 67 #define CONFIG_GENERIC_MMC
68 #define CONFIG_OMAP_HSMMC 68 #define CONFIG_OMAP_HSMMC
69 #define CONFIG_CMD_MMC 69 #define CONFIG_CMD_MMC
70 #define CONFIG_DOS_PARTITION 70 #define CONFIG_DOS_PARTITION
71 #define CONFIG_CMD_FAT 71 #define CONFIG_CMD_FAT
72 #define CONFIG_CMD_EXT2 72 #define CONFIG_CMD_EXT2
73 73
74 #define CONFIG_FS_FAT 74 #define CONFIG_FS_FAT
75 75
76 /* 76 /*
77 * Only one of the following two options (DDR3/DDR2) should be enabled 77 * Only one of the following two options (DDR3/DDR2) should be enabled
78 * CONFIG_TI816X_EVM_DDR2 78 * CONFIG_TI816X_EVM_DDR2
79 * CONFIG_TI816X_EVM_DDR3 79 * CONFIG_TI816X_EVM_DDR3
80 */ 80 */
81 #define CONFIG_TI816X_EVM_DDR3 81 #define CONFIG_TI816X_EVM_DDR3
82 82
83 /* 83 /*
84 * Supported values: 400, 531, 675 or 796 MHz 84 * Supported values: 400, 531, 675 or 796 MHz
85 */ 85 */
86 #define CONFIG_TI816X_DDR_PLL_796 86 #define CONFIG_TI816X_DDR_PLL_796
87 87
88 #define CONFIG_TI816X_USE_EMIF0 1 88 #define CONFIG_TI816X_USE_EMIF0 1
89 #define CONFIG_TI816X_USE_EMIF1 1 89 #define CONFIG_TI816X_USE_EMIF1 1
90 90
91 91
92 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ 92 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
93 #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ 93 #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
94 #define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ 94 #define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
95 #define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ 95 #define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
96 #define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ 96 #define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
97 97
98 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ 98 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
99 #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 99 #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
100 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 100 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
101 GENERATED_GBL_DATA_SIZE) 101 GENERATED_GBL_DATA_SIZE)
102 102
103 /** 103 /**
104 * Platform/Board specific defs 104 * Platform/Board specific defs
105 */ 105 */
106 #define CONFIG_SYS_CLK_FREQ 27000000 106 #define CONFIG_SYS_CLK_FREQ 27000000
107 #define CONFIG_SYS_TIMERBASE 0x4802E000 107 #define CONFIG_SYS_TIMERBASE 0x4802E000
108 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 108 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
109 109
110 #undef CONFIG_NAND_OMAP_GPMC 110 #undef CONFIG_NAND_OMAP_GPMC
111 111
112 /* 112 /*
113 * NS16550 Configuration 113 * NS16550 Configuration
114 */ 114 */
115 #define CONFIG_SYS_NS16550 115 #define CONFIG_SYS_NS16550
116 #define CONFIG_SYS_NS16550_SERIAL 116 #define CONFIG_SYS_NS16550_SERIAL
117 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 117 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
118 #define CONFIG_SYS_NS16550_CLK (48000000) 118 #define CONFIG_SYS_NS16550_CLK (48000000)
119 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ 119 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
120 120
121 #define CONFIG_BAUDRATE 115200 121 #define CONFIG_BAUDRATE 115200
122 122
123 /* allow overwriting serial config and ethaddr */ 123 /* allow overwriting serial config and ethaddr */
124 #define CONFIG_ENV_OVERWRITE 124 #define CONFIG_ENV_OVERWRITE
125 125
126 #define CONFIG_SERIAL1 126 #define CONFIG_SERIAL1
127 #define CONFIG_SERIAL2 127 #define CONFIG_SERIAL2
128 #define CONFIG_SERIAL3 128 #define CONFIG_SERIAL3
129 #define CONFIG_CONS_INDEX 1 129 #define CONFIG_CONS_INDEX 1
130 #define CONFIG_SYS_CONSOLE_INFO_QUIET 130 #define CONFIG_SYS_CONSOLE_INFO_QUIET
131 131
132 #define CONFIG_ENV_IS_NOWHERE 132 #define CONFIG_ENV_IS_NOWHERE
133 133
134 /* SPL */ 134 /* SPL */
135 /* Defines for SPL */ 135 /* Defines for SPL */
136 #define CONFIG_SPL_FRAMEWORK 136 #define CONFIG_SPL_FRAMEWORK
137 #define CONFIG_SPL_TEXT_BASE 0x40400000 137 #define CONFIG_SPL_TEXT_BASE 0x40400000
138 #define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) 138 #define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
139 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
140 139
141 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 140 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
142 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 141 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
143 142
144 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 143 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
145 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 144 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
146 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 145 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
147 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 146 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
148 #define CONFIG_SPL_MMC_SUPPORT 147 #define CONFIG_SPL_MMC_SUPPORT
149 #define CONFIG_SPL_FAT_SUPPORT 148 #define CONFIG_SPL_FAT_SUPPORT
150 149
151 #define CONFIG_SPL_LIBCOMMON_SUPPORT 150 #define CONFIG_SPL_LIBCOMMON_SUPPORT
152 #define CONFIG_SPL_LIBDISK_SUPPORT 151 #define CONFIG_SPL_LIBDISK_SUPPORT
153 #define CONFIG_SPL_LIBGENERIC_SUPPORT 152 #define CONFIG_SPL_LIBGENERIC_SUPPORT
154 #define CONFIG_SPL_SERIAL_SUPPORT 153 #define CONFIG_SPL_SERIAL_SUPPORT
155 #define CONFIG_SPL_GPIO_SUPPORT 154 #define CONFIG_SPL_GPIO_SUPPORT
156 #define CONFIG_SPL_YMODEM_SUPPORT 155 #define CONFIG_SPL_YMODEM_SUPPORT
157 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 156 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
158 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 157 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
159 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 158 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
160 159
161 #define CONFIG_SPL_BOARD_INIT 160 #define CONFIG_SPL_BOARD_INIT
162 161
163 #define CONFIG_SYS_TEXT_BASE 0x80800000 162 #define CONFIG_SYS_TEXT_BASE 0x80800000
164 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 163 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
165 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 164 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
166 165
167 /* Since SPL did pll and ddr initialization for us, 166 /* Since SPL did pll and ddr initialization for us,
168 * we don't need to do it twice. 167 * we don't need to do it twice.
169 */ 168 */
170 #ifndef CONFIG_SPL_BUILD 169 #ifndef CONFIG_SPL_BUILD
171 #define CONFIG_SKIP_LOWLEVEL_INIT 170 #define CONFIG_SKIP_LOWLEVEL_INIT
172 #endif 171 #endif
173 172
174 /* Unsupported features */ 173 /* Unsupported features */
175 #undef CONFIG_USE_IRQ 174 #undef CONFIG_USE_IRQ
176 175
177 #endif 176 #endif
178 177
include/configs/ti_armv7_common.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * ti_armv7_common.h 2 * ti_armv7_common.h
3 * 3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 * 7 *
8 * The various ARMv7 SoCs from TI all share a number of IP blocks when 8 * The various ARMv7 SoCs from TI all share a number of IP blocks when
9 * implementing a given feature. Rather than define these in every 9 * implementing a given feature. Rather than define these in every
10 * board or even SoC common file, we define a common file to be re-used 10 * board or even SoC common file, we define a common file to be re-used
11 * in all cases. While technically true that some of these details are 11 * in all cases. While technically true that some of these details are
12 * configurable at the board design, they are common throughout SoC 12 * configurable at the board design, they are common throughout SoC
13 * reference platforms as well as custom designs and become de facto 13 * reference platforms as well as custom designs and become de facto
14 * standards. 14 * standards.
15 */ 15 */
16 16
17 #ifndef __CONFIG_TI_ARMV7_COMMON_H__ 17 #ifndef __CONFIG_TI_ARMV7_COMMON_H__
18 #define __CONFIG_TI_ARMV7_COMMON_H__ 18 #define __CONFIG_TI_ARMV7_COMMON_H__
19 19
20 /* Common define for many platforms. */ 20 /* Common define for many platforms. */
21 #define CONFIG_OMAP 21 #define CONFIG_OMAP
22 #define CONFIG_OMAP_COMMON 22 #define CONFIG_OMAP_COMMON
23 #define CONFIG_SYS_GENERIC_BOARD 23 #define CONFIG_SYS_GENERIC_BOARD
24 24
25 /* 25 /*
26 * We typically do not contain NOR flash. In the cases where we do, we 26 * We typically do not contain NOR flash. In the cases where we do, we
27 * undefine this later. 27 * undefine this later.
28 */ 28 */
29 #define CONFIG_SYS_NO_FLASH 29 #define CONFIG_SYS_NO_FLASH
30 30
31 /* Support both device trees and ATAGs. */ 31 /* Support both device trees and ATAGs. */
32 #define CONFIG_OF_LIBFDT 32 #define CONFIG_OF_LIBFDT
33 #define CONFIG_CMDLINE_TAG 33 #define CONFIG_CMDLINE_TAG
34 #define CONFIG_SETUP_MEMORY_TAGS 34 #define CONFIG_SETUP_MEMORY_TAGS
35 #define CONFIG_INITRD_TAG 35 #define CONFIG_INITRD_TAG
36 36
37 /* 37 /*
38 * Our DDR memory always starts at 0x80000000 and U-Boot shall have 38 * Our DDR memory always starts at 0x80000000 and U-Boot shall have
39 * relocated itself to higher in memory by the time this value is used. 39 * relocated itself to higher in memory by the time this value is used.
40 * However, set this to a 32MB offset to allow for easier Linux kernel 40 * However, set this to a 32MB offset to allow for easier Linux kernel
41 * booting as the default is often used as the kernel load address. 41 * booting as the default is often used as the kernel load address.
42 */ 42 */
43 #define CONFIG_SYS_LOAD_ADDR 0x82000000 43 #define CONFIG_SYS_LOAD_ADDR 0x82000000
44 44
45 /* 45 /*
46 * We setup defaults based on constraints from the Linux kernel, which should 46 * We setup defaults based on constraints from the Linux kernel, which should
47 * also be safe elsewhere. We have the default load at 32MB into DDR (for 47 * also be safe elsewhere. We have the default load at 32MB into DDR (for
48 * the kernel), FDT above 128MB (the maximum location for the end of the 48 * the kernel), FDT above 128MB (the maximum location for the end of the
49 * kernel), and the ramdisk 512KB above that (allowing for hopefully never 49 * kernel), and the ramdisk 512KB above that (allowing for hopefully never
50 * seen large trees). We say all of this must be within the first 256MB 50 * seen large trees). We say all of this must be within the first 256MB
51 * as that will normally be within the kernel lowmem and thus visible via 51 * as that will normally be within the kernel lowmem and thus visible via
52 * bootm_size and we only run on platforms with 256MB or more of memory. 52 * bootm_size and we only run on platforms with 256MB or more of memory.
53 */ 53 */
54 #define DEFAULT_LINUX_BOOT_ENV \ 54 #define DEFAULT_LINUX_BOOT_ENV \
55 "loadaddr=0x82000000\0" \ 55 "loadaddr=0x82000000\0" \
56 "kernel_addr_r=0x82000000\0" \ 56 "kernel_addr_r=0x82000000\0" \
57 "fdtaddr=0x88000000\0" \ 57 "fdtaddr=0x88000000\0" \
58 "fdt_addr_r=0x88000000\0" \ 58 "fdt_addr_r=0x88000000\0" \
59 "rdaddr=0x88080000\0" \ 59 "rdaddr=0x88080000\0" \
60 "ramdisk_addr_r=0x88080000\0" \ 60 "ramdisk_addr_r=0x88080000\0" \
61 "bootm_size=0x10000000\0" 61 "bootm_size=0x10000000\0"
62 62
63 /* 63 /*
64 * Default to a quick boot delay. 64 * Default to a quick boot delay.
65 */ 65 */
66 #define CONFIG_BOOTDELAY 1 66 #define CONFIG_BOOTDELAY 1
67 67
68 /* 68 /*
69 * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, 69 * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
70 * we say (for simplicity) that we have 1 bank, always, even when 70 * we say (for simplicity) that we have 1 bank, always, even when
71 * we have more. We always start at 0x80000000, and we place the 71 * we have more. We always start at 0x80000000, and we place the
72 * initial stack pointer in our SRAM. Otherwise, we can define 72 * initial stack pointer in our SRAM. Otherwise, we can define
73 * CONFIG_NR_DRAM_BANKS before including this file. 73 * CONFIG_NR_DRAM_BANKS before including this file.
74 */ 74 */
75 #ifndef CONFIG_NR_DRAM_BANKS 75 #ifndef CONFIG_NR_DRAM_BANKS
76 #define CONFIG_NR_DRAM_BANKS 1 76 #define CONFIG_NR_DRAM_BANKS 1
77 #endif 77 #endif
78 #define CONFIG_SYS_SDRAM_BASE 0x80000000 78 #define CONFIG_SYS_SDRAM_BASE 0x80000000
79 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 79 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
80 GENERATED_GBL_DATA_SIZE) 80 GENERATED_GBL_DATA_SIZE)
81 81
82 /* Timer information. */ 82 /* Timer information. */
83 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 83 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
84 84
85 /* I2C IP block */ 85 /* I2C IP block */
86 #define CONFIG_I2C 86 #define CONFIG_I2C
87 #define CONFIG_CMD_I2C 87 #define CONFIG_CMD_I2C
88 #define CONFIG_SYS_I2C 88 #define CONFIG_SYS_I2C
89 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 89 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
90 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 90 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
91 #define CONFIG_SYS_I2C_OMAP24XX 91 #define CONFIG_SYS_I2C_OMAP24XX
92 92
93 /* MMC/SD IP block */ 93 /* MMC/SD IP block */
94 #define CONFIG_MMC 94 #define CONFIG_MMC
95 #define CONFIG_GENERIC_MMC 95 #define CONFIG_GENERIC_MMC
96 #define CONFIG_OMAP_HSMMC 96 #define CONFIG_OMAP_HSMMC
97 #define CONFIG_CMD_MMC 97 #define CONFIG_CMD_MMC
98 98
99 /* McSPI IP block */ 99 /* McSPI IP block */
100 #define CONFIG_SPI 100 #define CONFIG_SPI
101 #define CONFIG_OMAP3_SPI 101 #define CONFIG_OMAP3_SPI
102 #define CONFIG_CMD_SPI 102 #define CONFIG_CMD_SPI
103 103
104 /* GPIO block */ 104 /* GPIO block */
105 #define CONFIG_OMAP_GPIO 105 #define CONFIG_OMAP_GPIO
106 #define CONFIG_CMD_GPIO 106 #define CONFIG_CMD_GPIO
107 107
108 /* 108 /*
109 * GPMC NAND block. We support 1 device and the physical address to 109 * GPMC NAND block. We support 1 device and the physical address to
110 * access CS0 at is 0x8000000. 110 * access CS0 at is 0x8000000.
111 */ 111 */
112 #ifdef CONFIG_NAND 112 #ifdef CONFIG_NAND
113 #define CONFIG_NAND_OMAP_GPMC 113 #define CONFIG_NAND_OMAP_GPMC
114 #ifndef CONFIG_SYS_NAND_BASE 114 #ifndef CONFIG_SYS_NAND_BASE
115 #define CONFIG_SYS_NAND_BASE 0x8000000 115 #define CONFIG_SYS_NAND_BASE 0x8000000
116 #endif 116 #endif
117 #define CONFIG_SYS_MAX_NAND_DEVICE 1 117 #define CONFIG_SYS_MAX_NAND_DEVICE 1
118 #define CONFIG_CMD_NAND 118 #define CONFIG_CMD_NAND
119 #endif 119 #endif
120 120
121 /* 121 /*
122 * The following are general good-enough settings for U-Boot. We set a 122 * The following are general good-enough settings for U-Boot. We set a
123 * large malloc pool as we generally have a lot of DDR, and we opt for 123 * large malloc pool as we generally have a lot of DDR, and we opt for
124 * function over binary size in the main portion of U-Boot as this is 124 * function over binary size in the main portion of U-Boot as this is
125 * generally easily constrained later if needed. We enable the config 125 * generally easily constrained later if needed. We enable the config
126 * options that give us information in the environment about what board 126 * options that give us information in the environment about what board
127 * we are on so we do not need to rely on the command prompt. We set a 127 * we are on so we do not need to rely on the command prompt. We set a
128 * console baudrate of 115200 and use the default baud rate table. 128 * console baudrate of 115200 and use the default baud rate table.
129 */ 129 */
130 #define CONFIG_SYS_MALLOC_LEN (16 << 20) 130 #define CONFIG_SYS_MALLOC_LEN (16 << 20)
131 #define CONFIG_SYS_HUSH_PARSER 131 #define CONFIG_SYS_HUSH_PARSER
132 #define CONFIG_SYS_PROMPT "U-Boot# " 132 #define CONFIG_SYS_PROMPT "U-Boot# "
133 #define CONFIG_SYS_CONSOLE_INFO_QUIET 133 #define CONFIG_SYS_CONSOLE_INFO_QUIET
134 #define CONFIG_BAUDRATE 115200 134 #define CONFIG_BAUDRATE 115200
135 #define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ 135 #define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */
136 #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ 136 #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
137 137
138 /* As stated above, the following choices are optional. */ 138 /* As stated above, the following choices are optional. */
139 #define CONFIG_SYS_LONGHELP 139 #define CONFIG_SYS_LONGHELP
140 #define CONFIG_AUTO_COMPLETE 140 #define CONFIG_AUTO_COMPLETE
141 #define CONFIG_CMDLINE_EDITING 141 #define CONFIG_CMDLINE_EDITING
142 #define CONFIG_VERSION_VARIABLE 142 #define CONFIG_VERSION_VARIABLE
143 143
144 /* We set the max number of command args high to avoid HUSH bugs. */ 144 /* We set the max number of command args high to avoid HUSH bugs. */
145 #define CONFIG_SYS_MAXARGS 64 145 #define CONFIG_SYS_MAXARGS 64
146 146
147 /* Console I/O Buffer Size */ 147 /* Console I/O Buffer Size */
148 #define CONFIG_SYS_CBSIZE 512 148 #define CONFIG_SYS_CBSIZE 512
149 /* Print Buffer Size */ 149 /* Print Buffer Size */
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
151 + sizeof(CONFIG_SYS_PROMPT) + 16) 151 + sizeof(CONFIG_SYS_PROMPT) + 16)
152 /* Boot Argument Buffer Size */ 152 /* Boot Argument Buffer Size */
153 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 153 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
154 154
155 /* 155 /*
156 * When we have SPI, NOR or NAND flash we expect to be making use of 156 * When we have SPI, NOR or NAND flash we expect to be making use of
157 * mtdparts, both for ease of use in U-Boot and for passing information 157 * mtdparts, both for ease of use in U-Boot and for passing information
158 * on to the Linux kernel. 158 * on to the Linux kernel.
159 */ 159 */
160 #if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) 160 #if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND)
161 #define CONFIG_MTD_DEVICE /* Required for mtdparts */ 161 #define CONFIG_MTD_DEVICE /* Required for mtdparts */
162 #define CONFIG_CMD_MTDPARTS 162 #define CONFIG_CMD_MTDPARTS
163 #endif 163 #endif
164 164
165 /* 165 /*
166 * For commands to use, we take the default list and add a few other 166 * For commands to use, we take the default list and add a few other
167 * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH 167 * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
168 * prior to this include, in order to skip a few commands. When we do 168 * prior to this include, in order to skip a few commands. When we do
169 * have flash, if we expect these commands they must be enabled in that 169 * have flash, if we expect these commands they must be enabled in that
170 * config. If desired, a specific list of desired commands can be used 170 * config. If desired, a specific list of desired commands can be used
171 * instead. 171 * instead.
172 */ 172 */
173 #include <config_cmd_default.h> 173 #include <config_cmd_default.h>
174 #define CONFIG_CMD_ASKENV 174 #define CONFIG_CMD_ASKENV
175 #define CONFIG_CMD_ECHO 175 #define CONFIG_CMD_ECHO
176 #define CONFIG_CMD_BOOTZ 176 #define CONFIG_CMD_BOOTZ
177 #define CONFIG_SUPPORT_RAW_INITRD 177 #define CONFIG_SUPPORT_RAW_INITRD
178 178
179 /* 179 /*
180 * Common filesystems support. When we have removable storage we 180 * Common filesystems support. When we have removable storage we
181 * enabled a number of useful commands and support. 181 * enabled a number of useful commands and support.
182 */ 182 */
183 #if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) 183 #if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
184 #define CONFIG_DOS_PARTITION 184 #define CONFIG_DOS_PARTITION
185 #define CONFIG_CMD_FAT 185 #define CONFIG_CMD_FAT
186 #define CONFIG_FAT_WRITE 186 #define CONFIG_FAT_WRITE
187 #define CONFIG_CMD_EXT2 187 #define CONFIG_CMD_EXT2
188 #define CONFIG_CMD_EXT4 188 #define CONFIG_CMD_EXT4
189 #define CONFIG_CMD_FS_GENERIC 189 #define CONFIG_CMD_FS_GENERIC
190 #define CONFIG_PARTITION_UUIDS 190 #define CONFIG_PARTITION_UUIDS
191 #define CONFIG_CMD_PART 191 #define CONFIG_CMD_PART
192 #endif 192 #endif
193 193
194 /* 194 /*
195 * Our platforms make use of SPL to initalize the hardware (primarily 195 * Our platforms make use of SPL to initalize the hardware (primarily
196 * memory) enough for full U-Boot to be loaded. We also support Falcon 196 * memory) enough for full U-Boot to be loaded. We also support Falcon
197 * Mode so that the Linux kernel can be booted directly from SPL 197 * Mode so that the Linux kernel can be booted directly from SPL
198 * instead, if desired. We make use of the general SPL framework found 198 * instead, if desired. We make use of the general SPL framework found
199 * under common/spl/. Given our generally common memory map, we set a 199 * under common/spl/. Given our generally common memory map, we set a
200 * number of related defaults and sizes here. 200 * number of related defaults and sizes here.
201 */ 201 */
202 #if !defined(CONFIG_NOR_BOOT) && \ 202 #if !defined(CONFIG_NOR_BOOT) && \
203 !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX)) 203 !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
204 #define CONFIG_SPL_FRAMEWORK 204 #define CONFIG_SPL_FRAMEWORK
205 #define CONFIG_SPL_OS_BOOT 205 #define CONFIG_SPL_OS_BOOT
206 206
207 /* 207 /*
208 * Place the image at the start of the ROM defined image space (per 208 * Place the image at the start of the ROM defined image space (per
209 * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined 209 * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined
210 * downloaded image area. We initalize DRAM as soon as we can so that 210 * downloaded image area. We initalize DRAM as soon as we can so that
211 * we can place stack, malloc and BSS there. We load U-Boot itself into 211 * we can place stack, malloc and BSS there. We load U-Boot itself into
212 * memory at 0x80800000 for legacy reasons (to not conflict with older 212 * memory at 0x80800000 for legacy reasons (to not conflict with older
213 * SPLs). We have our BSS be placed 2MiB after this, to allow for the 213 * SPLs). We have our BSS be placed 2MiB after this, to allow for the
214 * default Linux kernel address of 0x80008000 to work with most sized 214 * default Linux kernel address of 0x80008000 to work with most sized
215 * kernels, in the Falcon Mode case. We have the SPL malloc pool at the 215 * kernels, in the Falcon Mode case. We have the SPL malloc pool at the
216 * end of the BSS area. We place our stack at 32MiB after the start of 216 * end of the BSS area. We suggest that the stack be placed at 32MiB after
217 * DRAM to allow room for all of the above. 217 * the start of DRAM to allow room for all of the above (handled in Kconfig).
218 */ 218 */
219 #define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20))
220 #ifndef CONFIG_SYS_TEXT_BASE 219 #ifndef CONFIG_SYS_TEXT_BASE
221 #define CONFIG_SYS_TEXT_BASE 0x80800000 220 #define CONFIG_SYS_TEXT_BASE 0x80800000
222 #endif 221 #endif
223 #ifndef CONFIG_SPL_BSS_START_ADDR 222 #ifndef CONFIG_SPL_BSS_START_ADDR
224 #define CONFIG_SPL_BSS_START_ADDR 0x80a00000 223 #define CONFIG_SPL_BSS_START_ADDR 0x80a00000
225 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 224 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
226 #endif 225 #endif
227 #ifndef CONFIG_SYS_SPL_MALLOC_START 226 #ifndef CONFIG_SYS_SPL_MALLOC_START
228 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 227 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
229 CONFIG_SPL_BSS_MAX_SIZE) 228 CONFIG_SPL_BSS_MAX_SIZE)
230 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 229 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
231 #endif 230 #endif
232 231
233 /* RAW SD card / eMMC locations. */ 232 /* RAW SD card / eMMC locations. */
234 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 233 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
235 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 234 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
236 235
237 /* FAT sd card locations. */ 236 /* FAT sd card locations. */
238 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 237 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
239 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 238 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
240 239
241 #ifdef CONFIG_SPL_OS_BOOT 240 #ifdef CONFIG_SPL_OS_BOOT
242 /* FAT */ 241 /* FAT */
243 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 242 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
244 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 243 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
245 244
246 /* RAW SD card / eMMC */ 245 /* RAW SD card / eMMC */
247 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 246 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
248 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 247 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
249 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 248 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
250 249
251 /* spl export command */ 250 /* spl export command */
252 #define CONFIG_CMD_SPL 251 #define CONFIG_CMD_SPL
253 #endif 252 #endif
254 253
255 #ifdef CONFIG_MMC 254 #ifdef CONFIG_MMC
256 #define CONFIG_SPL_LIBDISK_SUPPORT 255 #define CONFIG_SPL_LIBDISK_SUPPORT
257 #define CONFIG_SPL_MMC_SUPPORT 256 #define CONFIG_SPL_MMC_SUPPORT
258 #define CONFIG_SPL_FAT_SUPPORT 257 #define CONFIG_SPL_FAT_SUPPORT
259 #endif 258 #endif
260 259
261 /* General parts of the framework, required. */ 260 /* General parts of the framework, required. */
262 #define CONFIG_SPL_I2C_SUPPORT 261 #define CONFIG_SPL_I2C_SUPPORT
263 #define CONFIG_SPL_LIBCOMMON_SUPPORT 262 #define CONFIG_SPL_LIBCOMMON_SUPPORT
264 #define CONFIG_SPL_LIBGENERIC_SUPPORT 263 #define CONFIG_SPL_LIBGENERIC_SUPPORT
265 #define CONFIG_SPL_SERIAL_SUPPORT 264 #define CONFIG_SPL_SERIAL_SUPPORT
266 #define CONFIG_SPL_GPIO_SUPPORT 265 #define CONFIG_SPL_GPIO_SUPPORT
267 #define CONFIG_SPL_BOARD_INIT 266 #define CONFIG_SPL_BOARD_INIT
268 267
269 #ifdef CONFIG_NAND 268 #ifdef CONFIG_NAND
270 #define CONFIG_SPL_NAND_SUPPORT 269 #define CONFIG_SPL_NAND_SUPPORT
271 #define CONFIG_SPL_NAND_BASE 270 #define CONFIG_SPL_NAND_BASE
272 #define CONFIG_SPL_NAND_DRIVERS 271 #define CONFIG_SPL_NAND_DRIVERS
273 #define CONFIG_SPL_NAND_ECC 272 #define CONFIG_SPL_NAND_ECC
274 #define CONFIG_SPL_MTD_SUPPORT 273 #define CONFIG_SPL_MTD_SUPPORT
275 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 274 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
276 #endif 275 #endif
277 #endif /* !CONFIG_NOR_BOOT */ 276 #endif /* !CONFIG_NOR_BOOT */
278 277
279 #endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ 278 #endif /* __CONFIG_TI_ARMV7_COMMON_H__ */
280 279
include/configs/tricorder.h
Diff comments   View file @ 7ae8350
1 /* 1 /*
2 * (C) Copyright 2006-2008 2 * (C) Copyright 2006-2008
3 * Texas Instruments. 3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * 6 *
7 * (C) Copyright 2012 7 * (C) Copyright 2012
8 * Corscience GmbH & Co. KG 8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de> 9 * Thomas Weber <weber@corscience.de>
10 * 10 *
11 * Configuration settings for the Tricorder board. 11 * Configuration settings for the Tricorder board.
12 * 12 *
13 * SPDX-License-Identifier: GPL-2.0+ 13 * SPDX-License-Identifier: GPL-2.0+
14 */ 14 */
15 15
16 #ifndef __CONFIG_H 16 #ifndef __CONFIG_H
17 #define __CONFIG_H 17 #define __CONFIG_H
18 18
19 /* High Level Configuration Options */ 19 /* High Level Configuration Options */
20 #define CONFIG_OMAP /* in a TI OMAP core */ 20 #define CONFIG_OMAP /* in a TI OMAP core */
21 #define CONFIG_OMAP_COMMON 21 #define CONFIG_OMAP_COMMON
22 22
23 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER 23 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
24 /* 24 /*
25 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 25 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
26 * 64 bytes before this address should be set aside for u-boot.img's 26 * 64 bytes before this address should be set aside for u-boot.img's
27 * header. That is 0x800FFFC0--0x80100000 should not be used for any 27 * header. That is 0x800FFFC0--0x80100000 should not be used for any
28 * other needs. 28 * other needs.
29 */ 29 */
30 #define CONFIG_SYS_TEXT_BASE 0x80100000 30 #define CONFIG_SYS_TEXT_BASE 0x80100000
31 31
32 #define CONFIG_SDRC /* The chip has SDRC controller */ 32 #define CONFIG_SDRC /* The chip has SDRC controller */
33 33
34 #include <asm/arch/cpu.h> /* get chip and board defs */ 34 #include <asm/arch/cpu.h> /* get chip and board defs */
35 #include <asm/arch/omap3.h> 35 #include <asm/arch/omap3.h>
36 36
37 #define CONFIG_SYS_GENERIC_BOARD 37 #define CONFIG_SYS_GENERIC_BOARD
38 38
39 /* Display CPU and Board information */ 39 /* Display CPU and Board information */
40 #define CONFIG_DISPLAY_CPUINFO 40 #define CONFIG_DISPLAY_CPUINFO
41 #define CONFIG_DISPLAY_BOARDINFO 41 #define CONFIG_DISPLAY_BOARDINFO
42 42
43 #define CONFIG_SILENT_CONSOLE 43 #define CONFIG_SILENT_CONSOLE
44 #define CONFIG_ZERO_BOOTDELAY_CHECK 44 #define CONFIG_ZERO_BOOTDELAY_CHECK
45 45
46 /* Clock Defines */ 46 /* Clock Defines */
47 #define V_OSCK 26000000 /* Clock output from T2 */ 47 #define V_OSCK 26000000 /* Clock output from T2 */
48 #define V_SCLK (V_OSCK >> 1) 48 #define V_SCLK (V_OSCK >> 1)
49 49
50 #define CONFIG_MISC_INIT_R 50 #define CONFIG_MISC_INIT_R
51 51
52 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 52 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
53 #define CONFIG_SETUP_MEMORY_TAGS 53 #define CONFIG_SETUP_MEMORY_TAGS
54 #define CONFIG_INITRD_TAG 54 #define CONFIG_INITRD_TAG
55 #define CONFIG_REVISION_TAG 55 #define CONFIG_REVISION_TAG
56 56
57 #define CONFIG_OF_LIBFDT 57 #define CONFIG_OF_LIBFDT
58 58
59 /* Size of malloc() pool */ 59 /* Size of malloc() pool */
60 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 60 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
61 61
62 /* Hardware drivers */ 62 /* Hardware drivers */
63 63
64 /* GPIO support */ 64 /* GPIO support */
65 #define CONFIG_OMAP_GPIO 65 #define CONFIG_OMAP_GPIO
66 66
67 /* GPIO banks */ 67 /* GPIO banks */
68 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ 68 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */
69 69
70 /* LED support */ 70 /* LED support */
71 #define CONFIG_STATUS_LED 71 #define CONFIG_STATUS_LED
72 #define CONFIG_BOARD_SPECIFIC_LED 72 #define CONFIG_BOARD_SPECIFIC_LED
73 #define CONFIG_CMD_LED /* LED command */ 73 #define CONFIG_CMD_LED /* LED command */
74 #define STATUS_LED_BIT (1 << 0) 74 #define STATUS_LED_BIT (1 << 0)
75 #define STATUS_LED_STATE STATUS_LED_ON 75 #define STATUS_LED_STATE STATUS_LED_ON
76 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 76 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
77 #define STATUS_LED_BIT1 (1 << 1) 77 #define STATUS_LED_BIT1 (1 << 1)
78 #define STATUS_LED_STATE1 STATUS_LED_ON 78 #define STATUS_LED_STATE1 STATUS_LED_ON
79 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 79 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
80 #define STATUS_LED_BIT2 (1 << 2) 80 #define STATUS_LED_BIT2 (1 << 2)
81 #define STATUS_LED_STATE2 STATUS_LED_ON 81 #define STATUS_LED_STATE2 STATUS_LED_ON
82 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) 82 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
83 83
84 /* NS16550 Configuration */ 84 /* NS16550 Configuration */
85 #define CONFIG_SYS_NS16550 85 #define CONFIG_SYS_NS16550
86 #define CONFIG_SYS_NS16550_SERIAL 86 #define CONFIG_SYS_NS16550_SERIAL
87 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 87 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
88 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 88 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
89 89
90 /* select serial console configuration */ 90 /* select serial console configuration */
91 #define CONFIG_CONS_INDEX 3 91 #define CONFIG_CONS_INDEX 3
92 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 92 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
93 #define CONFIG_SERIAL3 3 93 #define CONFIG_SERIAL3 3
94 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_BAUDRATE 115200
95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
96 115200} 96 115200}
97 97
98 /* MMC */ 98 /* MMC */
99 #define CONFIG_GENERIC_MMC 99 #define CONFIG_GENERIC_MMC
100 #define CONFIG_MMC 100 #define CONFIG_MMC
101 #define CONFIG_OMAP_HSMMC 101 #define CONFIG_OMAP_HSMMC
102 #define CONFIG_DOS_PARTITION 102 #define CONFIG_DOS_PARTITION
103 103
104 /* I2C */ 104 /* I2C */
105 #define CONFIG_SYS_I2C 105 #define CONFIG_SYS_I2C
106 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 106 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
107 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 107 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
108 #define CONFIG_SYS_I2C_OMAP34XX 108 #define CONFIG_SYS_I2C_OMAP34XX
109 109
110 110
111 /* EEPROM */ 111 /* EEPROM */
112 #define CONFIG_SYS_I2C_MULTI_EEPROMS 112 #define CONFIG_SYS_I2C_MULTI_EEPROMS
113 #define CONFIG_CMD_EEPROM 113 #define CONFIG_CMD_EEPROM
114 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 114 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
115 #define CONFIG_SYS_EEPROM_BUS_NUM 1 115 #define CONFIG_SYS_EEPROM_BUS_NUM 1
116 116
117 /* TWL4030 */ 117 /* TWL4030 */
118 #define CONFIG_TWL4030_POWER 118 #define CONFIG_TWL4030_POWER
119 #define CONFIG_TWL4030_LED 119 #define CONFIG_TWL4030_LED
120 120
121 /* Board NAND Info */ 121 /* Board NAND Info */
122 #define CONFIG_SYS_NO_FLASH /* no NOR flash */ 122 #define CONFIG_SYS_NO_FLASH /* no NOR flash */
123 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 123 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
124 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 124 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
125 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 125 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
126 "128k(SPL)," \ 126 "128k(SPL)," \
127 "1m(u-boot)," \ 127 "1m(u-boot)," \
128 "384k(u-boot-env1)," \ 128 "384k(u-boot-env1)," \
129 "1152k(mtdoops)," \ 129 "1152k(mtdoops)," \
130 "384k(u-boot-env2)," \ 130 "384k(u-boot-env2)," \
131 "5m(kernel)," \ 131 "5m(kernel)," \
132 "2m(fdt)," \ 132 "2m(fdt)," \
133 "-(ubi)" 133 "-(ubi)"
134 134
135 #define CONFIG_NAND_OMAP_GPMC 135 #define CONFIG_NAND_OMAP_GPMC
136 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 136 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
137 /* to access nand */ 137 /* to access nand */
138 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 138 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
139 /* to access nand at */ 139 /* to access nand at */
140 /* CS0 */ 140 /* CS0 */
141 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 141 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
142 /* devices */ 142 /* devices */
143 #define CONFIG_BCH 143 #define CONFIG_BCH
144 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 144 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
145 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 145 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
146 146
147 /* commands to include */ 147 /* commands to include */
148 #include <config_cmd_default.h> 148 #include <config_cmd_default.h>
149 149
150 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 150 #define CONFIG_CMD_EXT2 /* EXT2 Support */
151 #define CONFIG_CMD_FAT /* FAT support */ 151 #define CONFIG_CMD_FAT /* FAT support */
152 #define CONFIG_CMD_I2C /* I2C serial bus support */ 152 #define CONFIG_CMD_I2C /* I2C serial bus support */
153 #define CONFIG_CMD_MMC /* MMC support */ 153 #define CONFIG_CMD_MMC /* MMC support */
154 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 154 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
155 #define CONFIG_CMD_NAND /* NAND support */ 155 #define CONFIG_CMD_NAND /* NAND support */
156 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 156 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
157 #define CONFIG_CMD_UBI /* UBI commands */ 157 #define CONFIG_CMD_UBI /* UBI commands */
158 #define CONFIG_CMD_UBIFS /* UBIFS commands */ 158 #define CONFIG_CMD_UBIFS /* UBIFS commands */
159 #define CONFIG_LZO /* LZO is needed for UBIFS */ 159 #define CONFIG_LZO /* LZO is needed for UBIFS */
160 160
161 #undef CONFIG_CMD_NET 161 #undef CONFIG_CMD_NET
162 #undef CONFIG_CMD_NFS 162 #undef CONFIG_CMD_NFS
163 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 163 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
164 #undef CONFIG_CMD_IMI /* iminfo */ 164 #undef CONFIG_CMD_IMI /* iminfo */
165 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ 165 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
166 166
167 /* needed for ubi */ 167 /* needed for ubi */
168 #define CONFIG_RBTREE 168 #define CONFIG_RBTREE
169 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 169 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
170 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_MTD_PARTITIONS
171 171
172 /* Environment information (this is the common part) */ 172 /* Environment information (this is the common part) */
173 173
174 #define CONFIG_BOOTDELAY 0 174 #define CONFIG_BOOTDELAY 0
175 175
176 /* hang() the board on panic() */ 176 /* hang() the board on panic() */
177 #define CONFIG_PANIC_HANG 177 #define CONFIG_PANIC_HANG
178 178
179 /* environment placement (for NAND), is different for FLASHCARD but does not 179 /* environment placement (for NAND), is different for FLASHCARD but does not
180 * harm there */ 180 * harm there */
181 #define CONFIG_ENV_OFFSET 0x120000 /* env start */ 181 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
182 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ 182 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
183 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ 183 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
184 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ 184 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
185 185
186 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend 186 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
187 * value can not be used here! */ 187 * value can not be used here! */
188 #define CONFIG_LOADADDR 0x82000000 188 #define CONFIG_LOADADDR 0x82000000
189 189
190 #define CONFIG_COMMON_ENV_SETTINGS \ 190 #define CONFIG_COMMON_ENV_SETTINGS \
191 "console=ttyO2,115200n8\0" \ 191 "console=ttyO2,115200n8\0" \
192 "mmcdev=0\0" \ 192 "mmcdev=0\0" \
193 "vram=3M\0" \ 193 "vram=3M\0" \
194 "defaultdisplay=lcd\0" \ 194 "defaultdisplay=lcd\0" \
195 "kernelopts=mtdoops.mtddev=3\0" \ 195 "kernelopts=mtdoops.mtddev=3\0" \
196 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 196 "mtdparts=" MTDPARTS_DEFAULT "\0" \
197 "mtdids=" MTDIDS_DEFAULT "\0" \ 197 "mtdids=" MTDIDS_DEFAULT "\0" \
198 "commonargs=" \ 198 "commonargs=" \
199 "setenv bootargs console=${console} " \ 199 "setenv bootargs console=${console} " \
200 "${mtdparts} " \ 200 "${mtdparts} " \
201 "${kernelopts} " \ 201 "${kernelopts} " \
202 "vt.global_cursor_default=0 " \ 202 "vt.global_cursor_default=0 " \
203 "vram=${vram} " \ 203 "vram=${vram} " \
204 "omapdss.def_disp=${defaultdisplay}\0" 204 "omapdss.def_disp=${defaultdisplay}\0"
205 205
206 #define CONFIG_BOOTCOMMAND "run autoboot" 206 #define CONFIG_BOOTCOMMAND "run autoboot"
207 207
208 /* specific environment settings for different use cases 208 /* specific environment settings for different use cases
209 * FLASHCARD: used to run a rdimage from sdcard to program the device 209 * FLASHCARD: used to run a rdimage from sdcard to program the device
210 * 'NORMAL': used to boot kernel from sdcard, nand, ... 210 * 'NORMAL': used to boot kernel from sdcard, nand, ...
211 * 211 *
212 * The main aim for the FLASHCARD skin is to have an embedded environment 212 * The main aim for the FLASHCARD skin is to have an embedded environment
213 * which will not be influenced by any data already on the device. 213 * which will not be influenced by any data already on the device.
214 */ 214 */
215 #ifdef CONFIG_FLASHCARD 215 #ifdef CONFIG_FLASHCARD
216 216
217 #define CONFIG_ENV_IS_NOWHERE 217 #define CONFIG_ENV_IS_NOWHERE
218 218
219 /* the rdaddr is 16 MiB before the loadaddr */ 219 /* the rdaddr is 16 MiB before the loadaddr */
220 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" 220 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
221 221
222 #define CONFIG_EXTRA_ENV_SETTINGS \ 222 #define CONFIG_EXTRA_ENV_SETTINGS \
223 CONFIG_COMMON_ENV_SETTINGS \ 223 CONFIG_COMMON_ENV_SETTINGS \
224 CONFIG_ENV_RDADDR \ 224 CONFIG_ENV_RDADDR \
225 "autoboot=" \ 225 "autoboot=" \
226 "run commonargs; " \ 226 "run commonargs; " \
227 "setenv bootargs ${bootargs} " \ 227 "setenv bootargs ${bootargs} " \
228 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ 228 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
229 "rdinit=/sbin/init; " \ 229 "rdinit=/sbin/init; " \
230 "mmc dev ${mmcdev}; mmc rescan; " \ 230 "mmc dev ${mmcdev}; mmc rescan; " \
231 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ 231 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
232 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ 232 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
233 "bootm ${loadaddr} ${rdaddr}\0" 233 "bootm ${loadaddr} ${rdaddr}\0"
234 234
235 #else /* CONFIG_FLASHCARD */ 235 #else /* CONFIG_FLASHCARD */
236 236
237 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ 237 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
238 238
239 #define CONFIG_ENV_IS_IN_NAND 239 #define CONFIG_ENV_IS_IN_NAND
240 240
241 #define CONFIG_EXTRA_ENV_SETTINGS \ 241 #define CONFIG_EXTRA_ENV_SETTINGS \
242 CONFIG_COMMON_ENV_SETTINGS \ 242 CONFIG_COMMON_ENV_SETTINGS \
243 "mmcargs=" \ 243 "mmcargs=" \
244 "run commonargs; " \ 244 "run commonargs; " \
245 "setenv bootargs ${bootargs} " \ 245 "setenv bootargs ${bootargs} " \
246 "root=/dev/mmcblk0p2 " \ 246 "root=/dev/mmcblk0p2 " \
247 "rootwait " \ 247 "rootwait " \
248 "rw\0" \ 248 "rw\0" \
249 "nandargs=" \ 249 "nandargs=" \
250 "run commonargs; " \ 250 "run commonargs; " \
251 "setenv bootargs ${bootargs} " \ 251 "setenv bootargs ${bootargs} " \
252 "root=ubi0:root " \ 252 "root=ubi0:root " \
253 "ubi.mtd=7 " \ 253 "ubi.mtd=7 " \
254 "rootfstype=ubifs " \ 254 "rootfstype=ubifs " \
255 "ro\0" \ 255 "ro\0" \
256 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 256 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
257 "bootscript=echo Running bootscript from mmc ...; " \ 257 "bootscript=echo Running bootscript from mmc ...; " \
258 "source ${loadaddr}\0" \ 258 "source ${loadaddr}\0" \
259 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 259 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
260 "mmcboot=echo Booting from mmc ...; " \ 260 "mmcboot=echo Booting from mmc ...; " \
261 "run mmcargs; " \ 261 "run mmcargs; " \
262 "bootm ${loadaddr}\0" \ 262 "bootm ${loadaddr}\0" \
263 "loaduimage_ubi=ubi part ubi; " \ 263 "loaduimage_ubi=ubi part ubi; " \
264 "ubifsmount ubi:root; " \ 264 "ubifsmount ubi:root; " \
265 "ubifsload ${loadaddr} /boot/uImage\0" \ 265 "ubifsload ${loadaddr} /boot/uImage\0" \
266 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ 266 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
267 "nandboot=echo Booting from nand ...; " \ 267 "nandboot=echo Booting from nand ...; " \
268 "run nandargs; " \ 268 "run nandargs; " \
269 "run loaduimage_nand; " \ 269 "run loaduimage_nand; " \
270 "bootm ${loadaddr}\0" \ 270 "bootm ${loadaddr}\0" \
271 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 271 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
272 "if run loadbootscript; then " \ 272 "if run loadbootscript; then " \
273 "run bootscript; " \ 273 "run bootscript; " \
274 "else " \ 274 "else " \
275 "if run loaduimage; then " \ 275 "if run loaduimage; then " \
276 "run mmcboot; " \ 276 "run mmcboot; " \
277 "else run nandboot; " \ 277 "else run nandboot; " \
278 "fi; " \ 278 "fi; " \
279 "fi; " \ 279 "fi; " \
280 "else run nandboot; fi\0" 280 "else run nandboot; fi\0"
281 281
282 #endif /* CONFIG_FLASHCARD */ 282 #endif /* CONFIG_FLASHCARD */
283 283
284 /* Miscellaneous configurable options */ 284 /* Miscellaneous configurable options */
285 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 285 #define CONFIG_SYS_LONGHELP /* undef to save memory */
286 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 286 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
287 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */ 287 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */
288 #define CONFIG_AUTO_COMPLETE 288 #define CONFIG_AUTO_COMPLETE
289 #define CONFIG_SYS_PROMPT "OMAP3 Tricorder # " 289 #define CONFIG_SYS_PROMPT "OMAP3 Tricorder # "
290 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 290 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
291 /* Print Buffer Size */ 291 /* Print Buffer Size */
292 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 292 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
293 sizeof(CONFIG_SYS_PROMPT) + 16) 293 sizeof(CONFIG_SYS_PROMPT) + 16)
294 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 294 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
295 295
296 /* Boot Argument Buffer Size */ 296 /* Boot Argument Buffer Size */
297 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 297 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
298 298
299 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) 299 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
300 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 300 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
301 0x07000000) /* 112 MB */ 301 0x07000000) /* 112 MB */
302 302
303 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 303 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
304 304
305 /* 305 /*
306 * OMAP3 has 12 GP timers, they can be driven by the system clock 306 * OMAP3 has 12 GP timers, they can be driven by the system clock
307 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 307 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
308 * This rate is divided by a local divisor. 308 * This rate is divided by a local divisor.
309 */ 309 */
310 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 310 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
311 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 311 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
312 312
313 /* Physical Memory Map */ 313 /* Physical Memory Map */
314 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 314 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
315 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 315 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
316 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 316 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
317 317
318 /* NAND and environment organization */ 318 /* NAND and environment organization */
319 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 319 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
320 320
321 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 321 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
322 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 322 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
323 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 323 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
324 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 324 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
325 CONFIG_SYS_INIT_RAM_SIZE - \ 325 CONFIG_SYS_INIT_RAM_SIZE - \
326 GENERATED_GBL_DATA_SIZE) 326 GENERATED_GBL_DATA_SIZE)
327 327
328 /* SRAM config */ 328 /* SRAM config */
329 #define CONFIG_SYS_SRAM_START 0x40200000 329 #define CONFIG_SYS_SRAM_START 0x40200000
330 #define CONFIG_SYS_SRAM_SIZE 0x10000 330 #define CONFIG_SYS_SRAM_SIZE 0x10000
331 331
332 /* Defines for SPL */ 332 /* Defines for SPL */
333 #define CONFIG_SPL_FRAMEWORK 333 #define CONFIG_SPL_FRAMEWORK
334 #define CONFIG_SPL_NAND_SIMPLE 334 #define CONFIG_SPL_NAND_SIMPLE
335 335
336 #define CONFIG_SPL_BOARD_INIT 336 #define CONFIG_SPL_BOARD_INIT
337 #define CONFIG_SPL_GPIO_SUPPORT 337 #define CONFIG_SPL_GPIO_SUPPORT
338 #define CONFIG_SPL_LIBCOMMON_SUPPORT 338 #define CONFIG_SPL_LIBCOMMON_SUPPORT
339 #define CONFIG_SPL_LIBDISK_SUPPORT 339 #define CONFIG_SPL_LIBDISK_SUPPORT
340 #define CONFIG_SPL_I2C_SUPPORT 340 #define CONFIG_SPL_I2C_SUPPORT
341 #define CONFIG_SPL_LIBGENERIC_SUPPORT 341 #define CONFIG_SPL_LIBGENERIC_SUPPORT
342 #define CONFIG_SPL_SERIAL_SUPPORT 342 #define CONFIG_SPL_SERIAL_SUPPORT
343 #define CONFIG_SPL_POWER_SUPPORT 343 #define CONFIG_SPL_POWER_SUPPORT
344 #define CONFIG_SPL_NAND_SUPPORT 344 #define CONFIG_SPL_NAND_SUPPORT
345 #define CONFIG_SPL_NAND_BASE 345 #define CONFIG_SPL_NAND_BASE
346 #define CONFIG_SPL_NAND_DRIVERS 346 #define CONFIG_SPL_NAND_DRIVERS
347 #define CONFIG_SPL_NAND_ECC 347 #define CONFIG_SPL_NAND_ECC
348 #define CONFIG_SPL_MMC_SUPPORT 348 #define CONFIG_SPL_MMC_SUPPORT
349 #define CONFIG_SPL_FAT_SUPPORT 349 #define CONFIG_SPL_FAT_SUPPORT
350 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 350 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
351 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 351 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
352 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 352 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
353 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 353 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
354 354
355 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 355 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
356 #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ 356 #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */
357 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
358 357
359 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ 358 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
360 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 359 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
361 360
362 /* NAND boot config */ 361 /* NAND boot config */
363 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 362 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
364 #define CONFIG_SYS_NAND_PAGE_COUNT 64 363 #define CONFIG_SYS_NAND_PAGE_COUNT 64
365 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 364 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
366 #define CONFIG_SYS_NAND_OOBSIZE 64 365 #define CONFIG_SYS_NAND_OOBSIZE 64
367 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 366 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
368 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 367 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
369 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 368 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
370 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 369 13, 14, 16, 17, 18, 19, 20, 21, 22, \
371 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 370 23, 24, 25, 26, 27, 28, 30, 31, 32, \
372 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 371 33, 34, 35, 36, 37, 38, 39, 40, 41, \
373 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 372 42, 44, 45, 46, 47, 48, 49, 50, 51, \
374 52, 53, 54, 55, 56} 373 52, 53, 54, 55, 56}
375 374
376 #define CONFIG_SYS_NAND_ECCSIZE 512 375 #define CONFIG_SYS_NAND_ECCSIZE 512
377 #define CONFIG_SYS_NAND_ECCBYTES 13 376 #define CONFIG_SYS_NAND_ECCBYTES 13
378 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 377 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
379 378
380 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 379 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
381 380
382 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 381 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
383 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 382 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
384 383
385 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 384 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
386 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 385 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
387 386
388 #define CONFIG_SYS_ALT_MEMTEST 387 #define CONFIG_SYS_ALT_MEMTEST
389 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 388 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
390 #endif /* __CONFIG_H */ 389 #endif /* __CONFIG_H */
391 390