Eric Lee / smarc-uboot | Embedian Git Server

Commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124

Authored by Detlev Zundel 2009-03-30 06:31:34 +0800

Committed by Wolfgang Denk 2009-03-30 15:41:28 +0800

Exists in master and in 54 other branches

inka4x0: Add hardware diagnosis functions for inka4x0

This patch adds advanced diagnosis functions for the inka4x0 board.

Signed-off-by: Andreas Pfefferle <ap@denx.de>
Signed-off-by: Detlev Zundel <dzu@denx.de>

Showing 5 changed files with 546 additions and 4 deletions Inline Diff

board/inka4x0/Makefile
board/inka4x0/inka4x0.c
board/inka4x0/inkadiag.c
include/configs/inka4x0.h
include/ns16550.h

board/inka4x0/Makefile

Diff comments View file @ 7b5611c

board/inka4x0/inka4x0.c

Diff comments View file @ 7b5611c

 /*
- * (C) Copyright 2003-2004
+ * (C) Copyright 2008-2009
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
  *
+ * (C) Copyright 2009
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
  * (C) Copyright 2004
  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  *
  * (C) Copyright 2004
  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  *
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <mpc5xxx.h>
 #include <pci.h>
 #if defined(CONFIG_DDR_MT46V16M16)
 #include "mt46v16m16-75.h"
 #elif defined(CONFIG_SDR_MT48LC16M16A2)
 #include "mt48lc16m16a2-75.h"
 #elif defined(CONFIG_DDR_MT46V32M16)
 #include "mt46v32m16.h"
 #elif defined(CONFIG_DDR_HYB25D512160BF)
 #include "hyb25d512160bf.h"
 #elif defined(CONFIG_DDR_K4H511638C)
 #include "k4h511638c.h"
 #else
 #error "INKA4x0 SDRAM: invalid chip type specified!"
 #endif
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
 	/* unlock mode register */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
 	__asm__ volatile ("sync");
 	/* precharge all banks */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 	__asm__ volatile ("sync");
 #if SDRAM_DDR
 	/* set mode register: extended mode */
 	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
 	__asm__ volatile ("sync");
 	/* set mode register: reset DLL */
 	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
 	__asm__ volatile ("sync");
 #endif
 	/* precharge all banks */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 	__asm__ volatile ("sync");
 	/* auto refresh */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
 	__asm__ volatile ("sync");
 	/* set mode register */
 	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
 	__asm__ volatile ("sync");
 	/* normal operation */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 	__asm__ volatile ("sync");
 }
 #endif
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
  *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
 #ifndef CONFIG_SYS_RAMBOOT
 	long test1, test2;
 	/* setup SDRAM chip selects */
 	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
 	__asm__ volatile ("sync");
 	/* setup config registers */
 	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 	__asm__ volatile ("sync");
 #if SDRAM_DDR
 	/* set tap delay */
 	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 	__asm__ volatile ("sync");
 #endif
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
 	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	sdram_start(1);
 	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
 	} else {
 		dramsize = test2;
 	}
 	/* memory smaller than 1MB is impossible */
 	if (dramsize < (1 << 20)) {
 		dramsize = 0;
 	}
 	/* set SDRAM CS0 size according to the amount of RAM found */
 	if (dramsize > 0) {
 		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
 			__builtin_ffs(dramsize >> 20) - 1;
 	} else {
 		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 	}
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 #else /* CONFIG_SYS_RAMBOOT */
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 	if (dramsize >= 0x13) {
 		dramsize = (1 << (dramsize - 0x13)) << 20;
 	} else {
 		dramsize = 0;
 	}
 #endif /* CONFIG_SYS_RAMBOOT */
 	return dramsize;
 }
 int checkboard (void)
 {
 	puts ("Board: INKA 4X0\n");
 	return 0;
 }
 void flash_preinit(void)
 {
 	/*
 	 * Now, when we are in RAM, enable flash write
 	 * access for detection process.
 	 * Note that CS_BOOT cannot be cleared when
 	 * executing in flash.
 	 */
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+int misc_init_r (void) {
+	extern int inkadiag_init_r (void);
+	/*
+	 * The command table used for the subcommands of inkadiag
+	 * needs to be relocated manually.
+	 */
+	return inkadiag_init_r();
 }
 int misc_init_f (void)
 {
 	char tmp[10];
 	int i, br;
 	i = getenv_r("brightness", tmp, sizeof(tmp));
 	br = (i > 0)
 		? (int) simple_strtoul (tmp, NULL, 10)
 		: CONFIG_SYS_BRIGHTNESS;
 	if (br > 255)
 		br = 255;
 	/* Initialize GPIO output pins.
 	 */
 	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
 	*(vu_long *)MPC5XXX_GPT0_ENABLE =
 	*(vu_long *)MPC5XXX_GPT1_ENABLE =
 	*(vu_long *)MPC5XXX_GPT2_ENABLE =
 	*(vu_long *)MPC5XXX_GPT3_ENABLE =
 	*(vu_long *)MPC5XXX_GPT4_ENABLE =
 	*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
 	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
 	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
 	*(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
 	*(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
 	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
 	/* Configure PSC3_6,7 as GPIO output */
 	*(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
 	*(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
 	/* Configure PSC3_8 as GPIO output, no interrupt */
 	*(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
 	*(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
 	*(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
 	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
 	*(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
 	*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
 	/* Set LR mirror bit because it is low-active */
 	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O    |= GPIO_WKUP_7;
 	/*
 	 * Reset Coral-P graphics controller
 	 */
 	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
 	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC3_9;
 	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC3_9;
 	return 0;
 }
 #ifdef	CONFIG_PCI
 static struct pci_controller hose;
 extern void pci_mpc5xxx_init(struct pci_controller *);
 void pci_init_board(void)
 {
 	pci_mpc5xxx_init(&hose);
 }
 #endif
 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 void init_ide_reset (void)
 {
 	debug ("init_ide_reset\n");
 	/* Configure PSC1_4 as GPIO output for ATA reset */
 	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 	/* Deassert reset */
 	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
 }
 void ide_set_reset (int idereset)
 {
 	debug ("ide_reset(%d)\n", idereset);
 	if (idereset) {
 		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
 		/* Make a delay. MPC5200 spec says 25 usec min */
 		udelay(500000);
 	} else {
 		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 	}
 }
 #endif

board/inka4x0/inkadiag.c

Diff comments View file @ 7b5611c

File was created	1	/*
	2	* (C) Copyright 2008, 2009 Andreas Pfefferle,
	3	* DENX Software Engineering, ap@denx.de.
	4	* (C) Copyright 2009 Detlev Zundel,
	5	* DENX Software Engineering, dzu@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <asm/io.h>
	27	#include <common.h>
	28	#include <config.h>
	29	#include <mpc5xxx.h>
	30	#include <pci.h>
	31
	32	#include <command.h>
	33
	34	/* This is needed for the includes in ns16550.h */
	35	#define CONFIG_SYS_NS16550_REG_SIZE 1
	36	#include <ns16550.h>
	37
	38	#define GPIO_BASE ((u_char *)CONFIG_SYS_CS3_START)
	39
	40	#define DIGIN_TOUCHSCR_MASK 0x00003000 /* Inputs 12-13 */
	41	#define DIGIN_KEYB_MASK 0x00010000 /* Input 16 */
	42
	43	#define DIGIN_DRAWER_SW1 0x00400000 /* Input 22 */
	44	#define DIGIN_DRAWER_SW2 0x00800000 /* Input 23 */
	45
	46	#define DIGIO_LED0 0x00000001 /* Output 0 */
	47	#define DIGIO_LED1 0x00000002 /* Output 1 */
	48	#define DIGIO_LED2 0x00000004 /* Output 2 */
	49	#define DIGIO_LED3 0x00000008 /* Output 3 */
	50	#define DIGIO_LED4 0x00000010 /* Output 4 */
	51	#define DIGIO_LED5 0x00000020 /* Output 5 */
	52
	53	#define DIGIO_DRAWER1 0x00000100 /* Output 8 */
	54	#define DIGIO_DRAWER2 0x00000200 /* Output 9 */
	55
	56	#define SERIAL_PORT_BASE ((u_char *)CONFIG_SYS_CS2_START)
	57
	58	#define PSC_OP1_RTS 0x01
	59	#define PSC_OP0_RTS 0x01
	60
	61	/*
	62	* Table with supported baudrates (defined in inka4x0.h)
	63	*/
	64	static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
	65	#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
	66
	67	static unsigned int inka_digin_get_input(void)
	68	{
	69	return in_8(GPIO_BASE + 0) << 0 \| in_8(GPIO_BASE + 1) << 8 \|
	70	in_8(GPIO_BASE + 2) << 16 \| in_8(GPIO_BASE + 3) << 24;
	71	}
	72
	73	#define LED_HIGH(NUM) \
	74	do { \
	75	setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
	76	} while (0)
	77
	78	#define LED_LOW(NUM) \
	79	do { \
	80	clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
	81	} while (0)
	82
	83	#define CHECK_LED(NUM) \
	84	do { \
	85	if (state & (1 << NUM)) { \
	86	LED_HIGH(NUM); \
	87	} else { \
	88	LED_LOW(NUM); \
	89	} \
	90	} while (0)
	91
	92	static void inka_digio_set_output(unsigned int state, int which)
	93	{
	94	volatile struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	95
	96	if (which == 0) {
	97	/* other */
	98	CHECK_LED(0);
	99	CHECK_LED(1);
	100	CHECK_LED(2);
	101	CHECK_LED(3);
	102	CHECK_LED(4);
	103	CHECK_LED(5);
	104	} else {
	105	if (which == 1) {
	106	/* drawer1 */
	107	if (state) {
	108	clrbits_be32(&gpio->simple_dvo, 0x1000);
	109	udelay(1);
	110	setbits_be32(&gpio->simple_dvo, 0x1000);
	111	} else {
	112	setbits_be32(&gpio->simple_dvo, 0x1000);
	113	udelay(1);
	114	clrbits_be32(&gpio->simple_dvo, 0x1000);
	115	}
	116	}
	117	if (which == 2) {
	118	/* drawer 2 */
	119	if (state) {
	120	clrbits_be32(&gpio->simple_dvo, 0x2000);
	121	udelay(1);
	122	setbits_be32(&gpio->simple_dvo, 0x2000);
	123	} else {
	124	setbits_be32(&gpio->simple_dvo, 0x2000);
	125	udelay(1);
	126	clrbits_be32(&gpio->simple_dvo, 0x2000);
	127	}
	128	}
	129	}
	130	udelay(1);
	131	}
	132
	133	static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc,
	134	char *argv[]) {
	135	unsigned int state, val;
	136
	137	switch (argc) {
	138	case 3:
	139	/* Write a value */
	140	val = simple_strtol(argv[2], NULL, 16);
	141
	142	if (strcmp(argv[1], "drawer1") == 0) {
	143	inka_digio_set_output(val, 1);
	144	} else if (strcmp(argv[1], "drawer2") == 0) {
	145	inka_digio_set_output(val, 2);
	146	} else if (strcmp(argv[1], "other") == 0)
	147	inka_digio_set_output(val, 0);
	148	else {
	149	printf("Invalid argument: %s\n", argv[1]);
	150	return -1;
	151	}
	152	/* fall through */
	153	case 2:
	154	/* Read a value */
	155	state = inka_digin_get_input();
	156
	157	if (strcmp(argv[1], "drawer1") == 0) {
	158	val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1);
	159	} else if (strcmp(argv[1], "drawer2") == 0) {
	160	val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1);
	161	} else if (strcmp(argv[1], "other") == 0) {
	162	val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1))
	163	\| (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2);
	164	} else {
	165	printf("Invalid argument: %s\n", argv[1]);
	166	return -1;
	167	}
	168	printf("exit code: 0x%X\n", val);
	169	return 0;
	170	default:
	171	cmd_usage(cmdtp);
	172	break;
	173	}
	174
	175	return -1;
	176	}
	177
	178	DECLARE_GLOBAL_DATA_PTR;
	179
	180	static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate)
	181	{
	182	unsigned long baseclk;
	183	int div;
	184
	185	/* reset PSC */
	186	out_8(&psc->command, PSC_SEL_MODE_REG_1);
	187
	188	/* select clock sources */
	189
	190	out_be16(&psc->psc_clock_select, 0);
	191	baseclk = (gd->ipb_clk + 16) / 32;
	192
	193	/* switch to UART mode */
	194	out_be32(&psc->sicr, 0);
	195
	196	/* configure parity, bit length and so on */
	197
	198	out_8(&psc->mode, PSC_MODE_8_BITS \| PSC_MODE_PARNONE);
	199	out_8(&psc->mode, PSC_MODE_ONE_STOP);
	200
	201	/* set up UART divisor */
	202	div = (baseclk + (baudrate / 2)) / baudrate;
	203	out_8(&psc->ctur, (div >> 8) & 0xff);
	204	out_8(&psc->ctlr, div & 0xff);
	205
	206	/* disable all interrupts */
	207	out_be16(&psc->psc_imr, 0);
	208
	209	/* reset and enable Rx/Tx */
	210	out_8(&psc->command, PSC_RST_RX);
	211	out_8(&psc->command, PSC_RST_TX);
	212	out_8(&psc->command, PSC_RX_ENABLE \| PSC_TX_ENABLE);
	213
	214	return 0;
	215	}
	216
	217	static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c)
	218	{
	219	/* Wait 1 second for last character to go. */
	220	int i = 0;
	221
	222	while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10))
	223	udelay(10);
	224	psc->psc_buffer_8 = c;
	225
	226	}
	227
	228	static int ser_getc(volatile struct mpc5xxx_psc *psc)
	229	{
	230	/* Wait for a character to arrive. */
	231	int i = 0;
	232
	233	while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10))
	234	udelay(10);
	235
	236	return in_8(&psc->psc_buffer_8);
	237	}
	238
	239	static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
	240	char *argv[]) {
	241	volatile struct NS16550 *uart;
	242	volatile struct mpc5xxx_psc *psc;
	243	unsigned int num, mode;
	244	int combrd, baudrate, i, j, len;
	245	int address;
	246
	247	if (argc < 5) {
	248	cmd_usage(cmdtp);
	249	return 1;
	250	}
	251
	252	argc--;
	253	argv++;
	254
	255	num = simple_strtol(argv[0], NULL, 0);
	256	if (num < 0 \|\| num > 11) {
	257	printf("invalid argument for num: %d\n", num);
	258	return -1;
	259	}
	260
	261	mode = simple_strtol(argv[1], NULL, 0);
	262
	263	combrd = 0;
	264	baudrate = simple_strtoul(argv[2], NULL, 10);
	265	for (i=0; i<N_BAUDRATES; ++i) {
	266	if (baudrate == baudrate_table[i])
	267	break;
	268	}
	269	if (i == N_BAUDRATES) {
	270	printf("## Baudrate %d bps not supported\n",
	271	baudrate);
	272	return 1;
	273	}
	274	combrd = 115200 / baudrate;
	275
	276	uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3));
	277
	278	printf("Testing uart %d.\n\n", num);
	279
	280	if ((num >= 0) && (num <= 7)) {
	281	if (mode & 1) {
	282	/* turn on 'loopback' mode */
	283	out_8(&uart->mcr, MCR_LOOP);
	284	} else {
	285	/*
	286	* establish the UART's operational parameters
	287	* set DLAB=1, so rbr accesses DLL
	288	*/
	289	out_8(&uart->lcr, LCR_DLAB);
	290	/* set baudrate */
	291	out_8(&uart->rbr, combrd);
	292	/* set data-format: 8-N-1 */
	293	out_8(&uart->lcr, LCR_WLS_8);
	294	}
	295
	296	if (mode & 2) {
	297	/* set request to send */
	298	out_8(&uart->mcr, MCR_RTS);
	299	udelay(10);
	300	/* check clear to send */
	301	if ((in_8(&uart->msr) & MSR_CTS) == 0x00)
	302	return -1;
	303	}
	304	if (mode & 4) {
	305	/* set data terminal ready */
	306	out_8(&uart->mcr, MCR_DTR);
	307	udelay(10);
	308	/* check data set ready and carrier detect */
	309	if ((in_8(&uart->msr) & (MSR_DSR \| MSR_DCD))
	310	!= (MSR_DSR \| MSR_DCD))
	311	return -1;
	312	}
	313
	314	/* write each message-character, read it back, and display it */
	315	for (i = 0, len = strlen(argv[3]); i < len; ++i) {
	316	j = 0;
	317	while ((in_8(&uart->lsr) & LSR_THRE) == 0x00) {
	318	if (j++ > CONFIG_SYS_HZ)
	319	break;
	320	udelay(10);
	321	}
	322	out_8(&uart->rbr, argv[3][i]);
	323	j = 0;
	324	while ((in_8(&uart->lsr) & LSR_DR) == 0x00) {
	325	if (j++ > CONFIG_SYS_HZ)
	326	break;
	327	udelay(10);
	328	}
	329	printf("%c", in_8(&uart->rbr));
	330	}
	331	printf("\n\n");
	332	out_8(&uart->mcr, 0x00);
	333	} else {
	334	address = 0;
	335
	336	switch (num) {
	337	case 8:
	338	address = MPC5XXX_PSC6;
	339	break;
	340	case 9:
	341	address = MPC5XXX_PSC3;
	342	break;
	343	case 10:
	344	address = MPC5XXX_PSC2;
	345	break;
	346	case 11:
	347	address = MPC5XXX_PSC1;
	348	break;
	349	}
	350	psc = (struct mpc5xxx_psc *)address;
	351	ser_init(psc, simple_strtol(argv[2], NULL, 0));
	352	if (mode & 2) {
	353	/* set request to send */
	354	out_8(&psc->op0, PSC_OP0_RTS);
	355	udelay(10);
	356	/* check clear to send */
	357	if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0)
	358	return -1;
	359	}
	360	len = strlen(argv[3]);
	361	for (i = 0; i < len; ++i) {
	362	ser_putc(psc, argv[3][i]);
	363	printf("%c", ser_getc(psc));
	364	}
	365	printf("\n\n");
	366	}
	367	return 0;
	368	}
	369
	370	#define BUZZER_GPT (MPC5XXX_GPT + 0x60) /* GPT6 */
	371	static void buzzer_turn_on(unsigned int freq)
	372	{
	373	volatile struct mpc5xxx_gpt gpt = (struct mpc5xxx_gpt )(BUZZER_GPT);
	374
	375	const u32 prescale = gd->ipb_clk / freq / 128;
	376	const u32 count = 128;
	377	const u32 width = 64;
	378
	379	gpt->cir = (prescale << 16) \| count;
	380	gpt->pwmcr = width << 16;
	381	gpt->emsr = 3; /* Timer enabled for PWM */
	382	}
	383
	384	static void buzzer_turn_off(void)
	385	{
	386	volatile struct mpc5xxx_gpt gpt = (struct mpc5xxx_gpt )(BUZZER_GPT);
	387
	388	gpt->emsr = 0;
	389	}
	390
	391	static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
	392	char *argv[]) {
	393
	394	unsigned int period, freq;
	395	int prev, i;
	396
	397	if (argc != 3) {
	398	cmd_usage(cmdtp);
	399	return 1;
	400	}
	401
	402	argc--;
	403	argv++;
	404
	405	period = simple_strtol(argv[0], NULL, 0);
	406	if (!period)
	407	printf("Zero period is senseless\n");
	408	argc--;
	409	argv++;
	410
	411	freq = simple_strtol(argv[0], NULL, 0);
	412	/* avoid zero prescale in buzzer_turn_on() */
	413	if (freq > gd->ipb_clk / 128) {
	414	printf("%dHz exceeds maximum (%ldHz)\n", freq,
	415	gd->ipb_clk / 128);
	416	} else if (!freq)
	417	printf("Zero frequency is senseless\n");
	418	else
	419	buzzer_turn_on(freq);
	420
	421	clear_ctrlc();
	422	prev = disable_ctrlc(0);
	423
	424	printf("Buzzing for %d ms. Type ^C to abort!\n\n", period);
	425
	426	i = 0;
	427	while (!ctrlc() && (i++ < CONFIG_SYS_HZ))
	428	udelay(period);
	429
	430	clear_ctrlc();
	431	disable_ctrlc(prev);
	432
	433	buzzer_turn_off();
	434
	435	return 0;
	436	}
	437
	438	static int do_inkadiag_help(cmd_tbl_t cmdtp, int flag, int argc, char argv[]);
	439
	440	cmd_tbl_t cmd_inkadiag_sub[] = {
	441	U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input",
	442	"<drawer1\|drawer2\|other> [value] - get or set specified signal\n"),
	443	U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port",
	444	"<num> <mode> <baudrate> <msg> - test uart num [0..11] in mode\n"
	445	"and baudrate with msg\n"),
	446	U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer",
	447	"<period> <freq> - turn buzzer on for period ms with freq hz\n"),
	448	U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help",
	449	"[command] - get help for command\n"),
	450	};
	451
	452	static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag,
	453	int argc, char *argv[]) {
	454	extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items,
	455	cmd_tbl_t *cmdtp, int flag,
	456	int argc, char *argv[]);
	457	/* do_help prints command name - we prepend inkadiag to our subcommands! */
	458	#ifdef CONFIG_SYS_LONGHELP
	459	puts ("inkadiag ");
	460	#endif
	461	return _do_help(&cmd_inkadiag_sub[0],
	462	ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv);
	463	}
	464
	465	static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc,
	466	char *argv[]) {
	467	cmd_tbl_t *c;
	468
	469	c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub));
	470
	471	if (c) {
	472	argc--;
	473	argv++;
	474	return c->cmd(c, flag, argc, argv);
	475	} else {
	476	/* Unrecognized command */
	477	cmd_usage(cmdtp);
	478	return 1;
	479	}
	480	}
	481
	482	U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag,
	483	"inkadiag - inka diagnosis\n",
	484	"[inkadiag what ...]\n"
	485	" - perform a diagnosis on inka hardware\n"
	486	"'inkadiag' performs hardware tests.\n\n");
	487
	488	/* Relocate the command table function pointers when running in RAM */
	489	int inkadiag_init_r (void) {
	490	cmd_tbl_t *cmdtp;
	491
	492	for (cmdtp = &cmd_inkadiag_sub[0]; cmdtp !=
	493	&cmd_inkadiag_sub[ARRAY_SIZE(cmd_inkadiag_sub)]; cmdtp++) {
	494	ulong addr;
	495
	496	addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
	497	cmdtp->cmd = (int ()(struct cmd_tbl_s , int, int, char *[]))addr;
	498
	499	addr = (ulong)(cmdtp->name) + gd->reloc_off;
	500	cmdtp->name = (char *)addr;
	501
	502	if (cmdtp->usage) {
	503	addr = (ulong)(cmdtp->usage) + gd->reloc_off;
	504	cmdtp->usage = (char *)addr;
	505	}
	506	#ifdef CONFIG_SYS_LONGHELP
	507	if (cmdtp->help) {
	508	addr = (ulong)(cmdtp->help) + gd->reloc_off;
	509	cmdtp->help = (char *)addr;
	510	}
	511	#endif
	512	}
	513	return 0;
	514	}
	515

include/configs/inka4x0.h

Diff comments View file @ 7b5611c

 /*
  * (C) Copyright 2003-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  * (easy to change)
  */
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
 #define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
 #define CONFIG_INKA4X0		1	/* INKA4x0 board			*/
 #define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 #define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
+#define CONFIG_MISC_INIT_R	1	/* Use misc_init_r()			*/
 #define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
 /*
  * Serial console configuration
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
  * 0x50000000 - 0x50ffffff - PCI IO Space
  */
 #define CONFIG_PCI		1
 #define CONFIG_PCI_PNP		1
 #define CONFIG_PCI_SCAN_SHOW	1
 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
 #define CONFIG_PCI_MEM_BUS	0x40000000
 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
 #define CONFIG_PCI_MEM_SIZE	0x10000000
 #define CONFIG_PCI_IO_BUS	0x50000000
 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE	0x01000000
 #define CONFIG_SYS_XLB_PIPELINING	1
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
 #if (TEXT_BASE == 0xFFE00000)		/* Boot low */
 #   define CONFIG_SYS_LOWBOOT		1
 #endif
 /*
  * Autobooting
  */
 #define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 #undef	CONFIG_BOOTARGS
 #define	CONFIG_ETHADDR		00:a0:a4:03:00:00
 #define	CONFIG_OVERWRITE_ETHADDR_ONCE
 #define	CONFIG_IPADDR		192.168.100.2
 #define	CONFIG_SERVERIP		192.168.100.1
 #define	CONFIG_NETMASK		255.255.255.0
 #define HOSTNAME		inka4x0
 #define CONFIG_BOOTFILE		/tftpboot/inka4x0/uImage
 #define	CONFIG_ROOTPATH		/opt/eldk/ppc_6xx
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addcons=setenv bootargs ${bootargs} "				\
 		"console=ttyS0,${baudrate}\0"				\
 	"flash_nfs=run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr}\0"				\
 	"net_nfs=tftp 200000 ${bootfile};"				\
 		"run nfsargs addip addcons;bootm\0"			\
 	"enable_disp=mw.l 100000 04000000 1;"				\
 		"cp.l 100000 f0000b20 1;"				\
 		"cp.l 100000 f0000b28 1\0"				\
 	"ideargs=setenv bootargs root=/dev/hda1 rw\0"			\
 	"ide_boot=ext2load ide 0:1 200000 uImage;"			\
 		"run ideargs addip addcons enable_disp;bootm\0"		\
 	"brightness=255\0"						\
 	""
 #define CONFIG_BOOTCOMMAND	"run ide_boot"
 /*
  * IPB Bus clocking configuration.
  */
 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 /*
  * Flash configuration
  */
 #define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1
 #define CONFIG_SYS_FLASH_BASE		0xffe00000
 #define CONFIG_SYS_FLASH_SIZE		0x00200000
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 /*
  * Memory map
  */
 #define CONFIG_SYS_MBAR		0xF0000000
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 /*
  * SDRAM controller configuration
  */
 #undef CONFIG_SDR_MT48LC16M16A2
 #undef CONFIG_DDR_MT46V16M16
 #undef CONFIG_DDR_MT46V32M16
 #undef CONFIG_DDR_HYB25D512160BF
 #define CONFIG_DDR_K4H511638C
 /* Use ON-Chip SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
 #define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
 #define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #   define CONFIG_SYS_RAMBOOT		1
 #endif
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
 #define CONFIG_MPC5xxx_FEC_MII100
 /*
  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
 #define CONFIG_MII
 /*
  * GPIO configuration
  *
  * use CS1 as gpio_wkup_6 output
  *	Bit 0 (mask: 0x80000000): 0
  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
  *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
  *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
  *	      EEPROM
  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
  * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
  *	011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
  */
 #define CONFIG_SYS_GPS_PORT_CONFIG	0x01001004
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 /* Enable an alternate, more extensive memory test */
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 #define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 /*
  * Enable loopw command.
  */
 #define CONFIG_LOOPW
 /*
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
 #define CONFIG_SYS_HID0_INIT		0
 #define CONFIG_SYS_HID0_FINAL		0
 #endif
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
 #define CONFIG_SYS_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
 #define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 /* 32Mbit SRAM @0x30000000 */
 #define CONFIG_SYS_CS1_START		0x30000000
 #define CONFIG_SYS_CS1_SIZE		0x00400000
 #define CONFIG_SYS_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */
 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 #define CONFIG_SYS_CS2_START		0x80000000
 #define CONFIG_SYS_CS2_SIZE		0x0001000
 #define CONFIG_SYS_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */
 /* GPIO in @0x30400000 */
 #define CONFIG_SYS_CS3_START		0x30400000
 #define CONFIG_SYS_CS3_SIZE		0x00100000
 #define CONFIG_SYS_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */
 #define CONFIG_SYS_CS_BURST		0x00000000
 #define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 /*-----------------------------------------------------------------------
  * USB stuff
  *-----------------------------------------------------------------------
  */
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_CLOCK	0x00015555
 #define CONFIG_USB_CONFIG	0x00001000
 #define CONFIG_USB_STORAGE
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff Supports IDE harddisk
  *-----------------------------------------------------------------------
  */
 #undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
 #undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #define	CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 #define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
 #define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 #define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 #define CONFIG_SYS_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 #define CONFIG_SYS_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
 #define CONFIG_SYS_ATA_STRIDE          4	/* Interval between registers	*/
 #define CONFIG_ATAPI            1
 #define CONFIG_SYS_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */
 #endif /* __CONFIG_H */

include/ns16550.h

Diff comments View file @ 7b5611c

 /*
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)
  * modified slightly to
  * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions
  * added prototypes for ns16550.c
  * reduced no of com ports to 2
  * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
  *
  * added support for port on 64-bit bus
  * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
  */
 #if (CONFIG_SYS_NS16550_REG_SIZE == 1)
 struct NS16550 {
 	unsigned char rbr;		/* 0 */
 	unsigned char ier;		/* 1 */
 	unsigned char fcr;		/* 2 */
 	unsigned char lcr;		/* 3 */
 	unsigned char mcr;		/* 4 */
 	unsigned char lsr;		/* 5 */
 	unsigned char msr;		/* 6 */
 	unsigned char scr;		/* 7 */
 #if defined(CONFIG_OMAP730)
 	unsigned char mdr1;		/* 8 */
 	unsigned char reg9;		/* 9 */
 	unsigned char regA;		/* A */
 	unsigned char regB;		/* B */
 	unsigned char regC;		/* C */
 	unsigned char regD;		/* D */
 	unsigned char regE;		/* E */
 	unsigned char regF;		/* F */
 	unsigned char reg10;		/* 10 */
 	unsigned char ssr;		/* 11*/
 #endif
 } __attribute__ ((packed));
 #elif (CONFIG_SYS_NS16550_REG_SIZE == 2)
 struct NS16550 {
 	unsigned short rbr;		/* 0 */
 	unsigned short ier;		/* 1 */
 	unsigned short fcr;		/* 2 */
 	unsigned short lcr;		/* 3 */
 	unsigned short mcr;		/* 4 */
 	unsigned short lsr;		/* 5 */
 	unsigned short msr;		/* 6 */
 	unsigned short scr;		/* 7 */
 } __attribute__ ((packed));
 #elif (CONFIG_SYS_NS16550_REG_SIZE == 4)
 struct NS16550 {
 	unsigned long rbr;		/* 0 r  */
 	unsigned long ier;		/* 1 rw */
 	unsigned long fcr;		/* 2 w  */
 	unsigned long lcr;		/* 3 rw */
 	unsigned long mcr;		/* 4 rw */
 	unsigned long lsr;		/* 5 r  */
 	unsigned long msr;		/* 6 r  */
 	unsigned long scr;		/* 7 rw */
 }; /* No need to pack an already aligned struct */
 #elif (CONFIG_SYS_NS16550_REG_SIZE == -4)
 struct NS16550 {
 	unsigned char rbr;		/* 0 */
 	int pad1:24;
 	unsigned char ier;		/* 1 */
 	int pad2:24;
 	unsigned char fcr;		/* 2 */
 	int pad3:24;
 	unsigned char lcr;		/* 3 */
 	int pad4:24;
 	unsigned char mcr;		/* 4 */
 	int pad5:24;
 	unsigned char lsr;		/* 5 */
 	int pad6:24;
 	unsigned char msr;		/* 6 */
 	int pad7:24;
 	unsigned char scr;		/* 7 */
 	int pad8:24;
 #if defined(CONFIG_OMAP)
 	unsigned char mdr1;		/* mode select reset TL16C750*/
 #endif
 #ifdef CONFIG_OMAP1510
 	int pad9:24;
 	unsigned long pad[10];
 	unsigned char osc_12m_sel;
 	int pad10:24;
 #endif
 } __attribute__ ((packed));
 #elif (CONFIG_SYS_NS16550_REG_SIZE == -8)
 struct NS16550 {
 	unsigned char rbr;		/* 0 */
 	unsigned char pad0[7];
 	unsigned char ier;		/* 1 */
 	unsigned char pad1[7];
 	unsigned char fcr;		/* 2 */
 	unsigned char pad2[7];
 	unsigned char lcr;		/* 3 */
 	unsigned char pad3[7];
 	unsigned char mcr;		/* 4 */
 	unsigned char pad4[7];
 	unsigned char lsr;		/* 5 */
 	unsigned char pad5[7];
 	unsigned char msr;		/* 6 */
 	unsigned char pad6[7];
 	unsigned char scr;		/* 7 */
 	unsigned char pad7[7];
 } __attribute__ ((packed));
 #else
 #error "Please define NS16550 registers size."
 #endif
 #define thr rbr
 #define iir fcr
 #define dll rbr
 #define dlm ier
 typedef volatile struct NS16550 *NS16550_t;
 #define FCR_FIFO_EN     0x01		/* Fifo enable */
 #define FCR_RXSR        0x02		/* Receiver soft reset */
 #define FCR_TXSR        0x04		/* Transmitter soft reset */
 #define MCR_DTR         0x01
 #define MCR_RTS         0x02
 #define MCR_DMA_EN      0x04
 #define MCR_TX_DFR      0x08
+#define MCR_LOOP	0x10		/* Enable loopback test mode */
 #define LCR_WLS_MSK	0x03		/* character length select mask */
 #define LCR_WLS_5	0x00		/* 5 bit character length */
 #define LCR_WLS_6	0x01		/* 6 bit character length */
 #define LCR_WLS_7	0x02		/* 7 bit character length */
 #define LCR_WLS_8	0x03		/* 8 bit character length */
 #define LCR_STB		0x04		/* Number of stop Bits, off = 1, on = 1.5 or 2) */
 #define LCR_PEN		0x08		/* Parity eneble */
 #define LCR_EPS		0x10		/* Even Parity Select */
 #define LCR_STKP	0x20		/* Stick Parity */
 #define LCR_SBRK	0x40		/* Set Break */
 #define LCR_BKSE	0x80		/* Bank select enable */
+#define LCR_DLAB	0x80		/* Divisor latch access bit */
 #define LSR_DR		0x01		/* Data ready */
 #define LSR_OE		0x02		/* Overrun */
 #define LSR_PE		0x04		/* Parity error */
 #define LSR_FE		0x08		/* Framing error */
 #define LSR_BI		0x10		/* Break */
 #define LSR_THRE	0x20		/* Xmit holding register empty */
 #define LSR_TEMT	0x40		/* Xmitter empty */
 #define LSR_ERR		0x80		/* Error */
+#define MSR_DCD		0x80		/* Data Carrier Detect */
+#define MSR_RI		0x40		/* Ring Indicator */
+#define MSR_DSR		0x20		/* Data Set Ready */
+#define MSR_CTS		0x10		/* Clear to Send */
+#define MSR_DDCD	0x08		/* Delta DCD */
+#define MSR_TERI	0x04		/* Trailing edge ring indicator */
+#define MSR_DDSR	0x02		/* Delta DSR */
+#define MSR_DCTS	0x01		/* Delta CTS */
 #ifdef CONFIG_OMAP1510
 #define OSC_12M_SEL	0x01		/* selects 6.5 * current clk div */
 #endif
 /* useful defaults for LCR */
 #define LCR_8N1		0x03
 void	NS16550_init   (NS16550_t com_port, int baud_divisor);
 void	NS16550_putc   (NS16550_t com_port, char c);
 char	NS16550_getc   (NS16550_t com_port);
 int	NS16550_tstc   (NS16550_t com_port);
 void	NS16550_reinit (NS16550_t com_port, int baud_divisor);

1	#	1	#
2	# (C) Copyright 2003-2006	2	# (C) Copyright 2003-2009
3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	#	4	#
5	# See file CREDITS for list of people who contributed to this	5	# See file CREDITS for list of people who contributed to this
6	# project.	6	# project.
7	#	7	#
8	# This program is free software; you can redistribute it and/or	8	# This program is free software; you can redistribute it and/or
9	# modify it under the terms of the GNU General Public License as	9	# modify it under the terms of the GNU General Public License as
10	# published by the Free Software Foundation; either version 2 of	10	# published by the Free Software Foundation; either version 2 of
11	# the License, or (at your option) any later version.	11	# the License, or (at your option) any later version.
12	#	12	#
13	# This program is distributed in the hope that it will be useful,	13	# This program is distributed in the hope that it will be useful,
14	# but WITHOUT ANY WARRANTY; without even the implied warranty of	14	# but WITHOUT ANY WARRANTY; without even the implied warranty of
15	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	# GNU General Public License for more details.	16	# GNU General Public License for more details.
17	#	17	#
18	# You should have received a copy of the GNU General Public License	18	# You should have received a copy of the GNU General Public License
19	# along with this program; if not, write to the Free Software	19	# along with this program; if not, write to the Free Software
20	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,	20	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21	# MA 02111-1307 USA	21	# MA 02111-1307 USA
22	#	22	#
23		23
24	include $(TOPDIR)/config.mk	24	include $(TOPDIR)/config.mk
25		25
26	LIB = $(obj)lib$(BOARD).a	26	LIB = $(obj)lib$(BOARD).a
27		27
28	COBJS := $(BOARD).o	28	COBJS := $(BOARD).o inkadiag.o
29		29
30	SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)	30	SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
31	OBJS := $(addprefix $(obj),$(COBJS))	31	OBJS := $(addprefix $(obj),$(COBJS))
32	SOBJS := $(addprefix $(obj),$(SOBJS))	32	SOBJS := $(addprefix $(obj),$(SOBJS))
33		33
34	$(LIB): $(obj).depend $(OBJS)	34	$(LIB): $(obj).depend $(OBJS)
35	$(AR) $(ARFLAGS) $@ $(OBJS)	35	$(AR) $(ARFLAGS) $@ $(OBJS)
36		36
37	clean:	37	clean:
38	rm -f $(SOBJS) $(OBJS)	38	rm -f $(SOBJS) $(OBJS)
39		39
40	distclean: clean	40	distclean: clean
41	rm -f $(LIB) core *.bak $(obj).depend	41	rm -f $(LIB) core *.bak $(obj).depend
42		42
43	#########################################################################	43	#########################################################################
44		44
45	# defines $(obj).depend target	45	# defines $(obj).depend target
46	include $(SRCTREE)/rules.mk	46	include $(SRCTREE)/rules.mk
47		47
48	sinclude $(obj).depend	48	sinclude $(obj).depend
49		49
50	#########################################################################	50	#########################################################################
51		51