Eric Lee / smarc-uboot

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Commit 7c7dd84b4b5cc90022fdd342d8714925af6ebb4f

Authored by Peng Fan
1 parent 5ba6e8b3c1
Exists in smarc-imx_v2015.04_4.1.15_1.0.0_ga and in 1 other branch imx_v2015.04_4.1.15_1.0.0_ga

MLK-12563: imx: mx6ul evk: fix LCD_nPWREN setting 

Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3.
If LCD_nPWREN is high, output is 2.4V which is not correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit b54bb7111af62a19a8aa930f8bbcf03f9515b863)

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
Diff comments   View file @ 7c7dd84
1 /* 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <asm/arch/clock.h> 7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h> 8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h> 10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6-pins.h> 11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/sys_proto.h>
13 #include <asm/gpio.h> 13 #include <asm/gpio.h>
14 #include <asm/imx-common/iomux-v3.h> 14 #include <asm/imx-common/iomux-v3.h>
15 #include <asm/imx-common/boot_mode.h> 15 #include <asm/imx-common/boot_mode.h>
16 #include <asm/imx-common/mxc_i2c.h> 16 #include <asm/imx-common/mxc_i2c.h>
17 #include <asm/io.h> 17 #include <asm/io.h>
18 #include <common.h> 18 #include <common.h>
19 #include <fsl_esdhc.h> 19 #include <fsl_esdhc.h>
20 #include <i2c.h> 20 #include <i2c.h>
21 #include <linux/sizes.h> 21 #include <linux/sizes.h>
22 #include <linux/fb.h> 22 #include <linux/fb.h>
23 #include <miiphy.h> 23 #include <miiphy.h>
24 #include <mmc.h> 24 #include <mmc.h>
25 #include <mxsfb.h> 25 #include <mxsfb.h>
26 #include <netdev.h> 26 #include <netdev.h>
27 #include <usb.h> 27 #include <usb.h>
28 #include <usb/ehci-fsl.h> 28 #include <usb/ehci-fsl.h>
29 29
30 #ifdef CONFIG_POWER 30 #ifdef CONFIG_POWER
31 #include <power/pmic.h> 31 #include <power/pmic.h>
32 #include <power/pfuze300_pmic.h> 32 #include <power/pfuze300_pmic.h>
33 #include "../common/pfuze.h" 33 #include "../common/pfuze.h"
34 #endif 34 #endif
35 35
36 #ifdef CONFIG_FSL_FASTBOOT 36 #ifdef CONFIG_FSL_FASTBOOT
37 #include <fsl_fastboot.h> 37 #include <fsl_fastboot.h>
38 #ifdef CONFIG_ANDROID_RECOVERY 38 #ifdef CONFIG_ANDROID_RECOVERY
39 #include <recovery.h> 39 #include <recovery.h>
40 #endif 40 #endif
41 #endif /*CONFIG_FSL_FASTBOOT*/ 41 #endif /*CONFIG_FSL_FASTBOOT*/
42 42
43 43
44 DECLARE_GLOBAL_DATA_PTR; 44 DECLARE_GLOBAL_DATA_PTR;
45 45
46 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 46 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49 49
50 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 50 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
51 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 51 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
52 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 52 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53 53
54 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 54 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
55 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ 55 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
56 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 56 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
57 57
58 58
59 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 59 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
60 PAD_CTL_SPEED_HIGH | \ 60 PAD_CTL_SPEED_HIGH | \
61 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 61 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
62 62
63 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 63 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
64 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 64 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
65 65
66 66
67 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 67 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
68 68
69 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 69 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
70 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 70 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
71 71
72 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 72 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
73 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 73 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
74 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 74 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
75 PAD_CTL_ODE) 75 PAD_CTL_ODE)
76 76
77 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 77 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
78 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 78 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
79 79
80 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) 80 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
81 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ 81 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
82 PAD_CTL_SRE_FAST) 82 PAD_CTL_SRE_FAST)
83 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) 83 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
84 84
85 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 85 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
86 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 86 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
87 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 87 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
88 88
89 #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 89 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
90 PAD_CTL_SPEED_MED | \ 90 PAD_CTL_SPEED_MED | \
91 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 91 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
92 92
93 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 93 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
94 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 94 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
95 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 95 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
96 96
97 #define IOX_SDI IMX_GPIO_NR(5, 10) 97 #define IOX_SDI IMX_GPIO_NR(5, 10)
98 #define IOX_STCP IMX_GPIO_NR(5, 7) 98 #define IOX_STCP IMX_GPIO_NR(5, 7)
99 #define IOX_SHCP IMX_GPIO_NR(5, 11) 99 #define IOX_SHCP IMX_GPIO_NR(5, 11)
100 #define IOX_OE IMX_GPIO_NR(5, 8) 100 #define IOX_OE IMX_GPIO_NR(5, 8)
101 101
102 static iomux_v3_cfg_t const iox_pads[] = { 102 static iomux_v3_cfg_t const iox_pads[] = {
103 /* IOX_SDI */ 103 /* IOX_SDI */
104 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 104 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
105 /* IOX_SHCP */ 105 /* IOX_SHCP */
106 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 106 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
107 /* IOX_STCP */ 107 /* IOX_STCP */
108 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 108 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
109 /* IOX_nOE */ 109 /* IOX_nOE */
110 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 110 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
111 }; 111 };
112 112
113 /* 113 /*
114 * HDMI_nRST --> Q0 114 * HDMI_nRST --> Q0
115 * ENET1_nRST --> Q1 115 * ENET1_nRST --> Q1
116 * ENET2_nRST --> Q2 116 * ENET2_nRST --> Q2
117 * CAN1_2_STBY --> Q3 117 * CAN1_2_STBY --> Q3
118 * BT_nPWD --> Q4 118 * BT_nPWD --> Q4
119 * CSI_RST --> Q5 119 * CSI_RST --> Q5
120 * CSI_PWDN --> Q6 120 * CSI_PWDN --> Q6
121 * LCD_nPWREN --> Q7 121 * LCD_nPWREN --> Q7
122 */ 122 */
123 enum qn { 123 enum qn {
124 HDMI_nRST, 124 HDMI_nRST,
125 ENET1_nRST, 125 ENET1_nRST,
126 ENET2_nRST, 126 ENET2_nRST,
127 CAN1_2_STBY, 127 CAN1_2_STBY,
128 BT_nPWD, 128 BT_nPWD,
129 CSI_RST, 129 CSI_RST,
130 CSI_PWDN, 130 CSI_PWDN,
131 LCD_nPWREN, 131 LCD_nPWREN,
132 }; 132 };
133 133
134 enum qn_func { 134 enum qn_func {
135 qn_reset, 135 qn_reset,
136 qn_enable, 136 qn_enable,
137 qn_disable, 137 qn_disable,
138 }; 138 };
139 139
140 enum qn_level { 140 enum qn_level {
141 qn_low = 0, 141 qn_low = 0,
142 qn_high = 1, 142 qn_high = 1,
143 }; 143 };
144 144
145 static enum qn_level seq[3][2] = { 145 static enum qn_level seq[3][2] = {
146 {0, 1}, {1, 1}, {0, 0} 146 {0, 1}, {1, 1}, {0, 0}
147 }; 147 };
148 148
149 static enum qn_func qn_output[8] = { 149 static enum qn_func qn_output[8] = {
150 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, qn_disable, 150 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, qn_disable,
151 qn_enable 151 qn_disable
152 }; 152 };
153 153
154 void iox74lv_init(void) 154 void iox74lv_init(void)
155 { 155 {
156 int i; 156 int i;
157 157
158 gpio_direction_output(IOX_OE, 0); 158 gpio_direction_output(IOX_OE, 0);
159 159
160 for (i = 7; i >= 0; i--) { 160 for (i = 7; i >= 0; i--) {
161 gpio_direction_output(IOX_SHCP, 0); 161 gpio_direction_output(IOX_SHCP, 0);
162 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 162 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
163 udelay(500); 163 udelay(500);
164 gpio_direction_output(IOX_SHCP, 1); 164 gpio_direction_output(IOX_SHCP, 1);
165 udelay(500); 165 udelay(500);
166 } 166 }
167 167
168 gpio_direction_output(IOX_STCP, 0); 168 gpio_direction_output(IOX_STCP, 0);
169 udelay(500); 169 udelay(500);
170 /* 170 /*
171 * shift register will be output to pins 171 * shift register will be output to pins
172 */ 172 */
173 gpio_direction_output(IOX_STCP, 1); 173 gpio_direction_output(IOX_STCP, 1);
174 174
175 for (i = 7; i >= 0; i--) { 175 for (i = 7; i >= 0; i--) {
176 gpio_direction_output(IOX_SHCP, 0); 176 gpio_direction_output(IOX_SHCP, 0);
177 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 177 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
178 udelay(500); 178 udelay(500);
179 gpio_direction_output(IOX_SHCP, 1); 179 gpio_direction_output(IOX_SHCP, 1);
180 udelay(500); 180 udelay(500);
181 } 181 }
182 gpio_direction_output(IOX_STCP, 0); 182 gpio_direction_output(IOX_STCP, 0);
183 udelay(500); 183 udelay(500);
184 /* 184 /*
185 * shift register will be output to pins 185 * shift register will be output to pins
186 */ 186 */
187 gpio_direction_output(IOX_STCP, 1); 187 gpio_direction_output(IOX_STCP, 1);
188 }; 188 };
189 189
190 void iox74lv_set(int index) 190 void iox74lv_set(int index)
191 { 191 {
192 int i; 192 int i;
193 193
194 for (i = 7; i >= 0; i--) { 194 for (i = 7; i >= 0; i--) {
195 gpio_direction_output(IOX_SHCP, 0); 195 gpio_direction_output(IOX_SHCP, 0);
196 196
197 if (i == index) 197 if (i == index)
198 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 198 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
199 else 199 else
200 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 200 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
201 udelay(500); 201 udelay(500);
202 gpio_direction_output(IOX_SHCP, 1); 202 gpio_direction_output(IOX_SHCP, 1);
203 udelay(500); 203 udelay(500);
204 } 204 }
205 205
206 gpio_direction_output(IOX_STCP, 0); 206 gpio_direction_output(IOX_STCP, 0);
207 udelay(500); 207 udelay(500);
208 /* 208 /*
209 * shift register will be output to pins 209 * shift register will be output to pins
210 */ 210 */
211 gpio_direction_output(IOX_STCP, 1); 211 gpio_direction_output(IOX_STCP, 1);
212 212
213 for (i = 7; i >= 0; i--) { 213 for (i = 7; i >= 0; i--) {
214 gpio_direction_output(IOX_SHCP, 0); 214 gpio_direction_output(IOX_SHCP, 0);
215 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 215 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
216 udelay(500); 216 udelay(500);
217 gpio_direction_output(IOX_SHCP, 1); 217 gpio_direction_output(IOX_SHCP, 1);
218 udelay(500); 218 udelay(500);
219 } 219 }
220 220
221 gpio_direction_output(IOX_STCP, 0); 221 gpio_direction_output(IOX_STCP, 0);
222 udelay(500); 222 udelay(500);
223 /* 223 /*
224 * shift register will be output to pins 224 * shift register will be output to pins
225 */ 225 */
226 gpio_direction_output(IOX_STCP, 1); 226 gpio_direction_output(IOX_STCP, 1);
227 }; 227 };
228 228
229 229
230 230
231 #ifdef CONFIG_SYS_I2C_MXC 231 #ifdef CONFIG_SYS_I2C_MXC
232 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 232 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
233 /* I2C1 for PMIC and EEPROM */ 233 /* I2C1 for PMIC and EEPROM */
234 struct i2c_pads_info i2c_pad_info1 = { 234 struct i2c_pads_info i2c_pad_info1 = {
235 .scl = { 235 .scl = {
236 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, 236 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
237 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, 237 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
238 .gp = IMX_GPIO_NR(1, 28), 238 .gp = IMX_GPIO_NR(1, 28),
239 }, 239 },
240 .sda = { 240 .sda = {
241 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, 241 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
242 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, 242 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
243 .gp = IMX_GPIO_NR(1, 29), 243 .gp = IMX_GPIO_NR(1, 29),
244 }, 244 },
245 }; 245 };
246 #endif 246 #endif
247 247
248 int dram_init(void) 248 int dram_init(void)
249 { 249 {
250 gd->ram_size = PHYS_SDRAM_SIZE; 250 gd->ram_size = PHYS_SDRAM_SIZE;
251 251
252 return 0; 252 return 0;
253 } 253 }
254 254
255 static iomux_v3_cfg_t const uart1_pads[] = { 255 static iomux_v3_cfg_t const uart1_pads[] = {
256 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 256 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
257 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 257 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
258 }; 258 };
259 259
260 static iomux_v3_cfg_t const usdhc1_pads[] = { 260 static iomux_v3_cfg_t const usdhc1_pads[] = {
261 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 261 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
262 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 262 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
263 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 263 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
264 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 264 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
265 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 265 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
266 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 266 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
267 267
268 /* VSELECT */ 268 /* VSELECT */
269 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), 269 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
270 /* CD */ 270 /* CD */
271 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 271 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
272 /* RST_B */ 272 /* RST_B */
273 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 273 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
274 }; 274 };
275 275
276 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) 276 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
277 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { 277 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
278 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 278 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
279 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 279 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
280 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 280 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
281 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 281 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
282 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 282 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
283 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 283 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
284 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 284 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
285 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 285 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
286 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 286 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
287 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 287 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
288 288
289 /* 289 /*
290 * RST_B 290 * RST_B
291 */ 291 */
292 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 292 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
293 }; 293 };
294 #else 294 #else
295 static iomux_v3_cfg_t const usdhc2_pads[] = { 295 static iomux_v3_cfg_t const usdhc2_pads[] = {
296 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 296 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
297 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 297 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
298 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 298 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
299 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 299 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
300 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 300 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
301 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 301 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
302 }; 302 };
303 303
304 static iomux_v3_cfg_t const usdhc2_cd_pads[] = { 304 static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
305 305
306 /* The evk board uses DAT3 to detect CD card plugin, in u-boot we mux the pin to 306 /* The evk board uses DAT3 to detect CD card plugin, in u-boot we mux the pin to
307 * GPIO when doing board_mmc_getcd. 307 * GPIO when doing board_mmc_getcd.
308 */ 308 */
309 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), 309 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
310 }; 310 };
311 311
312 static iomux_v3_cfg_t const usdhc2_dat3_pads[] = { 312 static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
313 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), 313 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
314 }; 314 };
315 315
316 316
317 #endif 317 #endif
318 318
319 #ifdef CONFIG_SYS_USE_NAND 319 #ifdef CONFIG_SYS_USE_NAND
320 static iomux_v3_cfg_t const nand_pads[] = { 320 static iomux_v3_cfg_t const nand_pads[] = {
321 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 321 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
322 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 322 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
323 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 323 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
324 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 324 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
325 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 325 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
326 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 326 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
327 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 327 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
328 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 328 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
329 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 329 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
330 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 330 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
331 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 331 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
332 MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 332 MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
333 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 333 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
334 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 334 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
335 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 335 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
336 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 336 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
337 MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 337 MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
338 }; 338 };
339 339
340 static void setup_gpmi_nand(void) 340 static void setup_gpmi_nand(void)
341 { 341 {
342 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 342 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
343 343
344 /* config gpmi nand iomux */ 344 /* config gpmi nand iomux */
345 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); 345 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
346 346
347 clrbits_le32(&mxc_ccm->CCGR4, 347 clrbits_le32(&mxc_ccm->CCGR4,
348 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 348 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
349 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 349 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
350 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 350 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
351 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 351 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
352 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); 352 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
353 353
354 /* 354 /*
355 * config gpmi and bch clock to 100 MHz 355 * config gpmi and bch clock to 100 MHz
356 * bch/gpmi select PLL2 PFD2 400M 356 * bch/gpmi select PLL2 PFD2 400M
357 * 100M = 400M / 4 357 * 100M = 400M / 4
358 */ 358 */
359 clrbits_le32(&mxc_ccm->cscmr1, 359 clrbits_le32(&mxc_ccm->cscmr1,
360 MXC_CCM_CSCMR1_BCH_CLK_SEL | 360 MXC_CCM_CSCMR1_BCH_CLK_SEL |
361 MXC_CCM_CSCMR1_GPMI_CLK_SEL); 361 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
362 clrsetbits_le32(&mxc_ccm->cscdr1, 362 clrsetbits_le32(&mxc_ccm->cscdr1,
363 MXC_CCM_CSCDR1_BCH_PODF_MASK | 363 MXC_CCM_CSCDR1_BCH_PODF_MASK |
364 MXC_CCM_CSCDR1_GPMI_PODF_MASK, 364 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
365 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | 365 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
366 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); 366 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
367 367
368 /* enable gpmi and bch clock gating */ 368 /* enable gpmi and bch clock gating */
369 setbits_le32(&mxc_ccm->CCGR4, 369 setbits_le32(&mxc_ccm->CCGR4,
370 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 370 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
371 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 371 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
372 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 372 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
373 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 373 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
374 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); 374 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
375 375
376 /* enable apbh clock gating */ 376 /* enable apbh clock gating */
377 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 377 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
378 } 378 }
379 #endif 379 #endif
380 380
381 #ifdef CONFIG_FEC_MXC 381 #ifdef CONFIG_FEC_MXC
382 /* 382 /*
383 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only 383 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
384 * be used for ENET1 or ENET2, cannot be used for both. 384 * be used for ENET1 or ENET2, cannot be used for both.
385 */ 385 */
386 static iomux_v3_cfg_t const fec1_pads[] = { 386 static iomux_v3_cfg_t const fec1_pads[] = {
387 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 387 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
388 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 388 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
389 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 389 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
390 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 390 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
391 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 391 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
392 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 392 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
393 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 393 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
394 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 394 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
395 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 395 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
396 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 396 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
397 }; 397 };
398 398
399 static iomux_v3_cfg_t const fec2_pads[] = { 399 static iomux_v3_cfg_t const fec2_pads[] = {
400 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 400 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
401 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 401 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
402 402
403 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 403 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
404 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 404 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
405 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 405 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
406 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 406 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
407 407
408 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 408 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
409 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 409 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
410 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 410 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
411 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 411 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
412 }; 412 };
413 413
414 static void setup_iomux_fec(int fec_id) 414 static void setup_iomux_fec(int fec_id)
415 { 415 {
416 if (fec_id == 0) 416 if (fec_id == 0)
417 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 417 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
418 else 418 else
419 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); 419 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
420 } 420 }
421 #endif 421 #endif
422 422
423 static void setup_iomux_uart(void) 423 static void setup_iomux_uart(void)
424 { 424 {
425 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 425 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
426 } 426 }
427 427
428 #ifdef CONFIG_FSL_QSPI 428 #ifdef CONFIG_FSL_QSPI
429 429
430 #define QSPI_PAD_CTRL1 \ 430 #define QSPI_PAD_CTRL1 \
431 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ 431 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
432 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) 432 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
433 433
434 static iomux_v3_cfg_t const quadspi_pads[] = { 434 static iomux_v3_cfg_t const quadspi_pads[] = {
435 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 435 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
436 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 436 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
437 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 437 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
438 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 438 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
439 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 439 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
440 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 440 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
441 }; 441 };
442 442
443 int board_qspi_init(void) 443 int board_qspi_init(void)
444 { 444 {
445 /* Set the iomux */ 445 /* Set the iomux */
446 imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); 446 imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
447 447
448 /* Set the clock */ 448 /* Set the clock */
449 enable_qspi_clk(0); 449 enable_qspi_clk(0);
450 450
451 return 0; 451 return 0;
452 } 452 }
453 #endif 453 #endif
454 454
455 #ifdef CONFIG_FSL_ESDHC 455 #ifdef CONFIG_FSL_ESDHC
456 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 456 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
457 {USDHC1_BASE_ADDR, 0, 4}, 457 {USDHC1_BASE_ADDR, 0, 4},
458 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) 458 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
459 {USDHC2_BASE_ADDR, 0, 8}, 459 {USDHC2_BASE_ADDR, 0, 8},
460 #else 460 #else
461 {USDHC2_BASE_ADDR, 0, 4}, 461 {USDHC2_BASE_ADDR, 0, 4},
462 #endif 462 #endif
463 }; 463 };
464 464
465 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) 465 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
466 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) 466 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
467 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) 467 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
468 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) 468 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
469 469
470 int mmc_get_env_devno(void) 470 int mmc_get_env_devno(void)
471 { 471 {
472 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); 472 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
473 int dev_no; 473 int dev_no;
474 u32 bootsel; 474 u32 bootsel;
475 475
476 bootsel = (soc_sbmr & 0x000000FF) >> 6 ; 476 bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
477 477
478 /* If not boot from sd/mmc, use default value */ 478 /* If not boot from sd/mmc, use default value */
479 if (bootsel != 1) 479 if (bootsel != 1)
480 return CONFIG_SYS_MMC_ENV_DEV; 480 return CONFIG_SYS_MMC_ENV_DEV;
481 481
482 /* BOOT_CFG2[3] and BOOT_CFG2[4] */ 482 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
483 dev_no = (soc_sbmr & 0x00001800) >> 11; 483 dev_no = (soc_sbmr & 0x00001800) >> 11;
484 484
485 if (dev_no == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) 485 if (dev_no == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
486 dev_no = 0; 486 dev_no = 0;
487 487
488 return dev_no; 488 return dev_no;
489 } 489 }
490 490
491 int mmc_map_to_kernel_blk(int dev_no) 491 int mmc_map_to_kernel_blk(int dev_no)
492 { 492 {
493 if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) 493 if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
494 dev_no = 1; 494 dev_no = 1;
495 495
496 return dev_no; 496 return dev_no;
497 } 497 }
498 498
499 int board_mmc_getcd(struct mmc *mmc) 499 int board_mmc_getcd(struct mmc *mmc)
500 { 500 {
501 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 501 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
502 int ret = 0; 502 int ret = 0;
503 503
504 switch (cfg->esdhc_base) { 504 switch (cfg->esdhc_base) {
505 case USDHC1_BASE_ADDR: 505 case USDHC1_BASE_ADDR:
506 ret = !gpio_get_value(USDHC1_CD_GPIO); 506 ret = !gpio_get_value(USDHC1_CD_GPIO);
507 break; 507 break;
508 case USDHC2_BASE_ADDR: 508 case USDHC2_BASE_ADDR:
509 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) 509 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
510 ret = 1; 510 ret = 1;
511 #else 511 #else
512 imx_iomux_v3_setup_multiple_pads( 512 imx_iomux_v3_setup_multiple_pads(
513 usdhc2_cd_pads, ARRAY_SIZE(usdhc2_cd_pads)); 513 usdhc2_cd_pads, ARRAY_SIZE(usdhc2_cd_pads));
514 gpio_direction_input(USDHC2_CD_GPIO); 514 gpio_direction_input(USDHC2_CD_GPIO);
515 515
516 /* Since it is the DAT3 pin, this pin is pulled to a low voltage if no card */ 516 /* Since it is the DAT3 pin, this pin is pulled to a low voltage if no card */
517 ret = gpio_get_value(USDHC2_CD_GPIO); 517 ret = gpio_get_value(USDHC2_CD_GPIO);
518 518
519 imx_iomux_v3_setup_multiple_pads( 519 imx_iomux_v3_setup_multiple_pads(
520 usdhc2_dat3_pads, ARRAY_SIZE(usdhc2_dat3_pads)); 520 usdhc2_dat3_pads, ARRAY_SIZE(usdhc2_dat3_pads));
521 #endif 521 #endif
522 break; 522 break;
523 } 523 }
524 524
525 return ret; 525 return ret;
526 526
527 } 527 }
528 528
529 int board_mmc_init(bd_t *bis) 529 int board_mmc_init(bd_t *bis)
530 { 530 {
531 int i, ret; 531 int i, ret;
532 532
533 /* 533 /*
534 * According to the board_mmc_init() the following map is done: 534 * According to the board_mmc_init() the following map is done:
535 * (U-boot device node) (Physical Port) 535 * (U-boot device node) (Physical Port)
536 * mmc0 USDHC1 536 * mmc0 USDHC1
537 * mmc1 USDHC2 537 * mmc1 USDHC2
538 */ 538 */
539 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 539 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
540 switch (i) { 540 switch (i) {
541 case 0: 541 case 0:
542 imx_iomux_v3_setup_multiple_pads( 542 imx_iomux_v3_setup_multiple_pads(
543 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 543 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
544 gpio_direction_input(USDHC1_CD_GPIO); 544 gpio_direction_input(USDHC1_CD_GPIO);
545 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 545 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
546 546
547 gpio_direction_output(USDHC1_PWR_GPIO, 0); 547 gpio_direction_output(USDHC1_PWR_GPIO, 0);
548 udelay(500); 548 udelay(500);
549 gpio_direction_output(USDHC1_PWR_GPIO, 1); 549 gpio_direction_output(USDHC1_PWR_GPIO, 1);
550 break; 550 break;
551 case 1: 551 case 1:
552 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) 552 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
553 imx_iomux_v3_setup_multiple_pads( 553 imx_iomux_v3_setup_multiple_pads(
554 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); 554 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
555 #else 555 #else
556 imx_iomux_v3_setup_multiple_pads( 556 imx_iomux_v3_setup_multiple_pads(
557 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 557 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
558 #endif 558 #endif
559 gpio_direction_output(USDHC2_PWR_GPIO, 0); 559 gpio_direction_output(USDHC2_PWR_GPIO, 0);
560 udelay(500); 560 udelay(500);
561 gpio_direction_output(USDHC2_PWR_GPIO, 1); 561 gpio_direction_output(USDHC2_PWR_GPIO, 1);
562 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 562 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
563 break; 563 break;
564 default: 564 default:
565 printf("Warning: you configured more USDHC controllers" 565 printf("Warning: you configured more USDHC controllers"
566 "(%d) than supported by the board\n", i + 1); 566 "(%d) than supported by the board\n", i + 1);
567 return -EINVAL; 567 return -EINVAL;
568 } 568 }
569 569
570 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 570 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
571 if (ret) { 571 if (ret) {
572 printf("Warning: failed to initialize mmc dev %d\n", i); 572 printf("Warning: failed to initialize mmc dev %d\n", i);
573 } 573 }
574 } 574 }
575 575
576 return 0; 576 return 0;
577 } 577 }
578 578
579 int check_mmc_autodetect(void) 579 int check_mmc_autodetect(void)
580 { 580 {
581 char *autodetect_str = getenv("mmcautodetect"); 581 char *autodetect_str = getenv("mmcautodetect");
582 582
583 if ((autodetect_str != NULL) && 583 if ((autodetect_str != NULL) &&
584 (strcmp(autodetect_str, "yes") == 0)) { 584 (strcmp(autodetect_str, "yes") == 0)) {
585 return 1; 585 return 1;
586 } 586 }
587 587
588 return 0; 588 return 0;
589 } 589 }
590 590
591 void board_late_mmc_init(void) 591 void board_late_mmc_init(void)
592 { 592 {
593 char cmd[32]; 593 char cmd[32];
594 char mmcblk[32]; 594 char mmcblk[32];
595 u32 dev_no = mmc_get_env_devno(); 595 u32 dev_no = mmc_get_env_devno();
596 596
597 if (!check_mmc_autodetect()) 597 if (!check_mmc_autodetect())
598 return; 598 return;
599 599
600 setenv_ulong("mmcdev", dev_no); 600 setenv_ulong("mmcdev", dev_no);
601 601
602 /* Set mmcblk env */ 602 /* Set mmcblk env */
603 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", 603 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
604 mmc_map_to_kernel_blk(dev_no)); 604 mmc_map_to_kernel_blk(dev_no));
605 setenv("mmcroot", mmcblk); 605 setenv("mmcroot", mmcblk);
606 606
607 sprintf(cmd, "mmc dev %d", dev_no); 607 sprintf(cmd, "mmc dev %d", dev_no);
608 run_command(cmd, 0); 608 run_command(cmd, 0);
609 } 609 }
610 #endif 610 #endif
611 611
612 #ifdef CONFIG_VIDEO_MXS 612 #ifdef CONFIG_VIDEO_MXS
613 static iomux_v3_cfg_t const lcd_pads[] = { 613 static iomux_v3_cfg_t const lcd_pads[] = {
614 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 614 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
615 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 615 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
616 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 616 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
617 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 617 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
618 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), 618 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
619 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), 619 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
620 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), 620 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
621 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), 621 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
622 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), 622 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
623 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), 623 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
624 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), 624 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
625 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), 625 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
626 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), 626 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
627 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), 627 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
628 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 628 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
629 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 629 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
630 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 630 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
631 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 631 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
632 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 632 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
633 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 633 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
634 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 634 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
635 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 635 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
636 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 636 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
637 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 637 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
638 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 638 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
639 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 639 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
640 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 640 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
641 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 641 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
642 642
643 /* LCD_RST */ 643 /* LCD_RST */
644 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 644 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
645 645
646 /* 646 /*
647 * Use GPIO for Brightness adjustment, duty cycle = period. 647 * Use GPIO for Brightness adjustment, duty cycle = period.
648 */ 648 */
649 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 649 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
650 }; 650 };
651 651
652 struct lcd_panel_info_t { 652 struct lcd_panel_info_t {
653 unsigned int lcdif_base_addr; 653 unsigned int lcdif_base_addr;
654 int depth; 654 int depth;
655 void (*enable)(struct lcd_panel_info_t const *dev); 655 void (*enable)(struct lcd_panel_info_t const *dev);
656 struct fb_videomode mode; 656 struct fb_videomode mode;
657 }; 657 };
658 658
659 void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev) 659 void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
660 { 660 {
661 enable_lcdif_clock(dev->lcdif_base_addr); 661 enable_lcdif_clock(dev->lcdif_base_addr);
662 662
663 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 663 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
664 664
665 /* Reset the LCD */ 665 /* Reset the LCD */
666 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); 666 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
667 udelay(500); 667 udelay(500);
668 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); 668 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
669 669
670 /* Set Brightness to high */ 670 /* Set Brightness to high */
671 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); 671 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
672 } 672 }
673 673
674 static struct lcd_panel_info_t const displays[] = {{ 674 static struct lcd_panel_info_t const displays[] = {{
675 .lcdif_base_addr = LCDIF1_BASE_ADDR, 675 .lcdif_base_addr = LCDIF1_BASE_ADDR,
676 .depth = 24, 676 .depth = 24,
677 .enable = do_enable_parallel_lcd, 677 .enable = do_enable_parallel_lcd,
678 .mode = { 678 .mode = {
679 .name = "TFT43AB", 679 .name = "TFT43AB",
680 .xres = 480, 680 .xres = 480,
681 .yres = 272, 681 .yres = 272,
682 .pixclock = 108695, 682 .pixclock = 108695,
683 .left_margin = 8, 683 .left_margin = 8,
684 .right_margin = 4, 684 .right_margin = 4,
685 .upper_margin = 2, 685 .upper_margin = 2,
686 .lower_margin = 4, 686 .lower_margin = 4,
687 .hsync_len = 41, 687 .hsync_len = 41,
688 .vsync_len = 10, 688 .vsync_len = 10,
689 .sync = 0, 689 .sync = 0,
690 .vmode = FB_VMODE_NONINTERLACED 690 .vmode = FB_VMODE_NONINTERLACED
691 } } }; 691 } } };
692 692
693 int board_video_skip(void) 693 int board_video_skip(void)
694 { 694 {
695 int i; 695 int i;
696 int ret; 696 int ret;
697 char const *panel = getenv("panel"); 697 char const *panel = getenv("panel");
698 if (!panel) { 698 if (!panel) {
699 panel = displays[0].mode.name; 699 panel = displays[0].mode.name;
700 printf("No panel detected: default to %s\n", panel); 700 printf("No panel detected: default to %s\n", panel);
701 i = 0; 701 i = 0;
702 } else { 702 } else {
703 for (i = 0; i < ARRAY_SIZE(displays); i++) { 703 for (i = 0; i < ARRAY_SIZE(displays); i++) {
704 if (!strcmp(panel, displays[i].mode.name)) 704 if (!strcmp(panel, displays[i].mode.name))
705 break; 705 break;
706 } 706 }
707 } 707 }
708 if (i < ARRAY_SIZE(displays)) { 708 if (i < ARRAY_SIZE(displays)) {
709 ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth, 709 ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
710 displays[i].lcdif_base_addr); 710 displays[i].lcdif_base_addr);
711 if (!ret) { 711 if (!ret) {
712 if (displays[i].enable) 712 if (displays[i].enable)
713 displays[i].enable(displays+i); 713 displays[i].enable(displays+i);
714 printf("Display: %s (%ux%u)\n", 714 printf("Display: %s (%ux%u)\n",
715 displays[i].mode.name, 715 displays[i].mode.name,
716 displays[i].mode.xres, 716 displays[i].mode.xres,
717 displays[i].mode.yres); 717 displays[i].mode.yres);
718 } else 718 } else
719 printf("LCD %s cannot be configured: %d\n", 719 printf("LCD %s cannot be configured: %d\n",
720 displays[i].mode.name, ret); 720 displays[i].mode.name, ret);
721 } else { 721 } else {
722 printf("unsupported panel %s\n", panel); 722 printf("unsupported panel %s\n", panel);
723 return -EINVAL; 723 return -EINVAL;
724 } 724 }
725 725
726 return 0; 726 return 0;
727 } 727 }
728 #endif 728 #endif
729 729
730 #ifdef CONFIG_FEC_MXC 730 #ifdef CONFIG_FEC_MXC
731 int board_eth_init(bd_t *bis) 731 int board_eth_init(bd_t *bis)
732 { 732 {
733 int ret; 733 int ret;
734 734
735 setup_iomux_fec(CONFIG_FEC_ENET_DEV); 735 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
736 736
737 ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, 737 ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
738 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 738 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
739 if (ret) 739 if (ret)
740 printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); 740 printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
741 741
742 return 0; 742 return 0;
743 } 743 }
744 744
745 static int setup_fec(int fec_id) 745 static int setup_fec(int fec_id)
746 { 746 {
747 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 747 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
748 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 748 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
749 int ret; 749 int ret;
750 750
751 if (0 == fec_id) { 751 if (0 == fec_id) {
752 if (check_module_fused(MX6_MODULE_ENET1)) 752 if (check_module_fused(MX6_MODULE_ENET1))
753 return -1; 753 return -1;
754 754
755 /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ 755 /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
756 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 756 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
757 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 757 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
758 } else { 758 } else {
759 if (check_module_fused(MX6_MODULE_ENET2)) 759 if (check_module_fused(MX6_MODULE_ENET2))
760 return -1; 760 return -1;
761 761
762 /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/ 762 /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/
763 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 763 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
764 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 764 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
765 } 765 }
766 766
767 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); 767 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
768 if (ret) 768 if (ret)
769 return ret; 769 return ret;
770 770
771 enable_enet_clk(1); 771 enable_enet_clk(1);
772 772
773 return 0; 773 return 0;
774 } 774 }
775 775
776 int board_phy_config(struct phy_device *phydev) 776 int board_phy_config(struct phy_device *phydev)
777 { 777 {
778 778
779 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 779 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
780 780
781 if (phydev->drv->config) 781 if (phydev->drv->config)
782 phydev->drv->config(phydev); 782 phydev->drv->config(phydev);
783 783
784 return 0; 784 return 0;
785 } 785 }
786 #endif 786 #endif
787 787
788 #ifdef CONFIG_USB_EHCI_MX6 788 #ifdef CONFIG_USB_EHCI_MX6
789 #define USB_OTHERREGS_OFFSET 0x800 789 #define USB_OTHERREGS_OFFSET 0x800
790 #define UCTRL_PWR_POL (1 << 9) 790 #define UCTRL_PWR_POL (1 << 9)
791 791
792 static iomux_v3_cfg_t const usb_otg_pads[] = { 792 static iomux_v3_cfg_t const usb_otg_pads[] = {
793 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), 793 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
794 }; 794 };
795 795
796 /* At default the 3v3 enables the MIC2026 for VBUS power */ 796 /* At default the 3v3 enables the MIC2026 for VBUS power */
797 static void setup_usb(void) 797 static void setup_usb(void)
798 { 798 {
799 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 799 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
800 ARRAY_SIZE(usb_otg_pads)); 800 ARRAY_SIZE(usb_otg_pads));
801 } 801 }
802 802
803 int board_usb_phy_mode(int port) 803 int board_usb_phy_mode(int port)
804 { 804 {
805 if (port == 1) 805 if (port == 1)
806 return USB_INIT_HOST; 806 return USB_INIT_HOST;
807 else 807 else
808 return usb_phy_mode(port); 808 return usb_phy_mode(port);
809 } 809 }
810 810
811 int board_ehci_hcd_init(int port) 811 int board_ehci_hcd_init(int port)
812 { 812 {
813 u32 *usbnc_usb_ctrl; 813 u32 *usbnc_usb_ctrl;
814 814
815 if (port > 1) 815 if (port > 1)
816 return -EINVAL; 816 return -EINVAL;
817 817
818 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 818 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
819 port * 4); 819 port * 4);
820 820
821 /* Set Power polarity */ 821 /* Set Power polarity */
822 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 822 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
823 823
824 return 0; 824 return 0;
825 } 825 }
826 #endif 826 #endif
827 827
828 int board_early_init_f(void) 828 int board_early_init_f(void)
829 { 829 {
830 setup_iomux_uart(); 830 setup_iomux_uart();
831 831
832 return 0; 832 return 0;
833 } 833 }
834 834
835 #ifdef CONFIG_POWER 835 #ifdef CONFIG_POWER
836 #define I2C_PMIC 0 836 #define I2C_PMIC 0
837 static struct pmic *pfuze; 837 static struct pmic *pfuze;
838 int power_init_board(void) 838 int power_init_board(void)
839 { 839 {
840 int ret; 840 int ret;
841 unsigned int reg, rev_id; 841 unsigned int reg, rev_id;
842 842
843 ret = power_pfuze300_init(I2C_PMIC); 843 ret = power_pfuze300_init(I2C_PMIC);
844 if (ret) 844 if (ret)
845 return ret; 845 return ret;
846 846
847 pfuze = pmic_get("PFUZE300"); 847 pfuze = pmic_get("PFUZE300");
848 ret = pmic_probe(pfuze); 848 ret = pmic_probe(pfuze);
849 if (ret) 849 if (ret)
850 return ret; 850 return ret;
851 851
852 pmic_reg_read(pfuze, PFUZE300_DEVICEID, &reg); 852 pmic_reg_read(pfuze, PFUZE300_DEVICEID, &reg);
853 pmic_reg_read(pfuze, PFUZE300_REVID, &rev_id); 853 pmic_reg_read(pfuze, PFUZE300_REVID, &rev_id);
854 printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 854 printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
855 855
856 /* disable Low Power Mode during standby mode */ 856 /* disable Low Power Mode during standby mode */
857 pmic_reg_read(pfuze, PFUZE300_LDOGCTL, &reg); 857 pmic_reg_read(pfuze, PFUZE300_LDOGCTL, &reg);
858 reg |= 0x1; 858 reg |= 0x1;
859 pmic_reg_write(pfuze, PFUZE300_LDOGCTL, reg); 859 pmic_reg_write(pfuze, PFUZE300_LDOGCTL, reg);
860 860
861 /* SW1B step ramp up time from 2us to 4us/25mV */ 861 /* SW1B step ramp up time from 2us to 4us/25mV */
862 reg = 0x40; 862 reg = 0x40;
863 pmic_reg_write(pfuze, PFUZE300_SW1BCONF, reg); 863 pmic_reg_write(pfuze, PFUZE300_SW1BCONF, reg);
864 864
865 /* SW1B mode to APS/PFM */ 865 /* SW1B mode to APS/PFM */
866 reg = 0xc; 866 reg = 0xc;
867 pmic_reg_write(pfuze, PFUZE300_SW1BMODE, reg); 867 pmic_reg_write(pfuze, PFUZE300_SW1BMODE, reg);
868 868
869 /* SW1B standby voltage set to 0.975V */ 869 /* SW1B standby voltage set to 0.975V */
870 reg = 0xb; 870 reg = 0xb;
871 pmic_reg_write(pfuze, PFUZE300_SW1BSTBY, reg); 871 pmic_reg_write(pfuze, PFUZE300_SW1BSTBY, reg);
872 872
873 return 0; 873 return 0;
874 } 874 }
875 875
876 #ifdef CONFIG_LDO_BYPASS_CHECK 876 #ifdef CONFIG_LDO_BYPASS_CHECK
877 void ldo_mode_set(int ldo_bypass) 877 void ldo_mode_set(int ldo_bypass)
878 { 878 {
879 unsigned int value; 879 unsigned int value;
880 u32 vddarm; 880 u32 vddarm;
881 881
882 struct pmic *p = pfuze; 882 struct pmic *p = pfuze;
883 883
884 if (!p) { 884 if (!p) {
885 printf("No PMIC found!\n"); 885 printf("No PMIC found!\n");
886 return; 886 return;
887 } 887 }
888 888
889 /* switch to ldo_bypass mode */ 889 /* switch to ldo_bypass mode */
890 if (ldo_bypass) { 890 if (ldo_bypass) {
891 prep_anatop_bypass(); 891 prep_anatop_bypass();
892 /* decrease VDDARM to 1.275V */ 892 /* decrease VDDARM to 1.275V */
893 pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value); 893 pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
894 value &= ~0x1f; 894 value &= ~0x1f;
895 value |= PFUZE300_SW1AB_SETP(1275); 895 value |= PFUZE300_SW1AB_SETP(1275);
896 pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value); 896 pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
897 897
898 set_anatop_bypass(1); 898 set_anatop_bypass(1);
899 vddarm = PFUZE300_SW1AB_SETP(1175); 899 vddarm = PFUZE300_SW1AB_SETP(1175);
900 900
901 pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value); 901 pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
902 value &= ~0x1f; 902 value &= ~0x1f;
903 value |= vddarm; 903 value |= vddarm;
904 pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value); 904 pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
905 905
906 finish_anatop_bypass(); 906 finish_anatop_bypass();
907 907
908 printf("switch to ldo_bypass mode!\n"); 908 printf("switch to ldo_bypass mode!\n");
909 } 909 }
910 } 910 }
911 #endif 911 #endif
912 #endif 912 #endif
913 913
914 int board_init(void) 914 int board_init(void)
915 { 915 {
916 /* Address of boot parameters */ 916 /* Address of boot parameters */
917 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 917 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
918 918
919 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 919 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
920 920
921 iox74lv_init(); 921 iox74lv_init();
922 922
923 #ifdef CONFIG_SYS_I2C_MXC 923 #ifdef CONFIG_SYS_I2C_MXC
924 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 924 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
925 #endif 925 #endif
926 926
927 #ifdef CONFIG_FEC_MXC 927 #ifdef CONFIG_FEC_MXC
928 setup_fec(CONFIG_FEC_ENET_DEV); 928 setup_fec(CONFIG_FEC_ENET_DEV);
929 #endif 929 #endif
930 930
931 #ifdef CONFIG_SYS_USE_NAND 931 #ifdef CONFIG_SYS_USE_NAND
932 setup_gpmi_nand(); 932 setup_gpmi_nand();
933 #endif 933 #endif
934 934
935 #ifdef CONFIG_USB_EHCI_MX6 935 #ifdef CONFIG_USB_EHCI_MX6
936 setup_usb(); 936 setup_usb();
937 #endif 937 #endif
938 938
939 #ifdef CONFIG_FSL_QSPI 939 #ifdef CONFIG_FSL_QSPI
940 board_qspi_init(); 940 board_qspi_init();
941 #endif 941 #endif
942 942
943 return 0; 943 return 0;
944 } 944 }
945 945
946 #ifdef CONFIG_CMD_BMODE 946 #ifdef CONFIG_CMD_BMODE
947 static const struct boot_mode board_boot_modes[] = { 947 static const struct boot_mode board_boot_modes[] = {
948 /* 4 bit bus width */ 948 /* 4 bit bus width */
949 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, 949 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
950 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 950 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
951 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, 951 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
952 {NULL, 0}, 952 {NULL, 0},
953 }; 953 };
954 #endif 954 #endif
955 955
956 int board_late_init(void) 956 int board_late_init(void)
957 { 957 {
958 #ifdef CONFIG_CMD_BMODE 958 #ifdef CONFIG_CMD_BMODE
959 add_board_boot_modes(board_boot_modes); 959 add_board_boot_modes(board_boot_modes);
960 #endif 960 #endif
961 961
962 #ifdef CONFIG_ENV_IS_IN_MMC 962 #ifdef CONFIG_ENV_IS_IN_MMC
963 board_late_mmc_init(); 963 board_late_mmc_init();
964 #endif 964 #endif
965 965
966 set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); 966 set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
967 967
968 return 0; 968 return 0;
969 } 969 }
970 970
971 u32 get_board_rev(void) 971 u32 get_board_rev(void)
972 { 972 {
973 return get_cpu_rev(); 973 return get_cpu_rev();
974 } 974 }
975 975
976 int checkboard(void) 976 int checkboard(void)
977 { 977 {
978 #if defined(CONFIG_MX6UL_9X9_LPDDR2) 978 #if defined(CONFIG_MX6UL_9X9_LPDDR2)
979 puts("Board: MX6UL 9x9 EVK\n"); 979 puts("Board: MX6UL 9x9 EVK\n");
980 #else 980 #else
981 puts("Board: MX6UL 14x14 EVK\n"); 981 puts("Board: MX6UL 14x14 EVK\n");
982 #endif 982 #endif
983 983
984 return 0; 984 return 0;
985 } 985 }
986 986
987 #ifdef CONFIG_FSL_FASTBOOT 987 #ifdef CONFIG_FSL_FASTBOOT
988 988
989 void board_fastboot_setup(void) 989 void board_fastboot_setup(void)
990 { 990 {
991 switch (get_boot_device()) { 991 switch (get_boot_device()) {
992 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 992 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
993 case SD1_BOOT: 993 case SD1_BOOT:
994 case MMC1_BOOT: 994 case MMC1_BOOT:
995 if (!getenv("fastboot_dev")) 995 if (!getenv("fastboot_dev"))
996 setenv("fastboot_dev", "mmc0"); 996 setenv("fastboot_dev", "mmc0");
997 if (!getenv("bootcmd")) 997 if (!getenv("bootcmd"))
998 setenv("bootcmd", "boota mmc0"); 998 setenv("bootcmd", "boota mmc0");
999 break; 999 break;
1000 case SD2_BOOT: 1000 case SD2_BOOT:
1001 case MMC2_BOOT: 1001 case MMC2_BOOT:
1002 if (!getenv("fastboot_dev")) 1002 if (!getenv("fastboot_dev"))
1003 setenv("fastboot_dev", "mmc1"); 1003 setenv("fastboot_dev", "mmc1");
1004 if (!getenv("bootcmd")) 1004 if (!getenv("bootcmd"))
1005 setenv("bootcmd", "boota mmc1"); 1005 setenv("bootcmd", "boota mmc1");
1006 break; 1006 break;
1007 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 1007 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
1008 #if defined(CONFIG_FASTBOOT_STORAGE_NAND) 1008 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
1009 case NAND_BOOT: 1009 case NAND_BOOT:
1010 if (!getenv("fastboot_dev")) 1010 if (!getenv("fastboot_dev"))
1011 setenv("fastboot_dev", "nand"); 1011 setenv("fastboot_dev", "nand");
1012 if (!getenv("fbparts")) 1012 if (!getenv("fbparts"))
1013 setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS); 1013 setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS);
1014 if (!getenv("bootcmd")) 1014 if (!getenv("bootcmd"))
1015 setenv("bootcmd", 1015 setenv("bootcmd",
1016 "nand read ${loadaddr} ${boot_nand_offset} " 1016 "nand read ${loadaddr} ${boot_nand_offset} "
1017 "${boot_nand_size};boota ${loadaddr}"); 1017 "${boot_nand_size};boota ${loadaddr}");
1018 break; 1018 break;
1019 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/ 1019 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
1020 1020
1021 default: 1021 default:
1022 printf("unsupported boot devices\n"); 1022 printf("unsupported boot devices\n");
1023 break; 1023 break;
1024 } 1024 }
1025 } 1025 }
1026 1026
1027 #ifdef CONFIG_ANDROID_RECOVERY 1027 #ifdef CONFIG_ANDROID_RECOVERY
1028 int check_recovery_cmd_file(void) 1028 int check_recovery_cmd_file(void)
1029 { 1029 {
1030 int recovery_mode = 0; 1030 int recovery_mode = 0;
1031 1031
1032 recovery_mode = recovery_check_and_clean_flag(); 1032 recovery_mode = recovery_check_and_clean_flag();
1033 1033
1034 return recovery_mode; 1034 return recovery_mode;
1035 } 1035 }
1036 1036
1037 void board_recovery_setup(void) 1037 void board_recovery_setup(void)
1038 { 1038 {
1039 int bootdev = get_boot_device(); 1039 int bootdev = get_boot_device();
1040 1040
1041 switch (bootdev) { 1041 switch (bootdev) {
1042 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 1042 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
1043 case SD1_BOOT: 1043 case SD1_BOOT:
1044 case MMC1_BOOT: 1044 case MMC1_BOOT:
1045 if (!getenv("bootcmd_android_recovery")) 1045 if (!getenv("bootcmd_android_recovery"))
1046 setenv("bootcmd_android_recovery", "boota mmc0 recovery"); 1046 setenv("bootcmd_android_recovery", "boota mmc0 recovery");
1047 break; 1047 break;
1048 case SD2_BOOT: 1048 case SD2_BOOT:
1049 case MMC2_BOOT: 1049 case MMC2_BOOT:
1050 if (!getenv("bootcmd_android_recovery")) 1050 if (!getenv("bootcmd_android_recovery"))
1051 setenv("bootcmd_android_recovery", "boota mmc1 recovery"); 1051 setenv("bootcmd_android_recovery", "boota mmc1 recovery");
1052 break; 1052 break;
1053 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 1053 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
1054 #if defined(CONFIG_FASTBOOT_STORAGE_NAND) 1054 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
1055 case NAND_BOOT: 1055 case NAND_BOOT:
1056 if (!getenv("bootcmd_android_recovery")) 1056 if (!getenv("bootcmd_android_recovery"))
1057 setenv("bootcmd_android_recovery", 1057 setenv("bootcmd_android_recovery",
1058 "nand read ${loadaddr} ${recovery_nand_offset} " 1058 "nand read ${loadaddr} ${recovery_nand_offset} "
1059 "${recovery_nand_size};boota ${loadaddr}"); 1059 "${recovery_nand_size};boota ${loadaddr}");
1060 break; 1060 break;
1061 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/ 1061 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
1062 1062
1063 default: 1063 default:
1064 printf("Unsupported bootup device for recovery: dev: %d\n", 1064 printf("Unsupported bootup device for recovery: dev: %d\n",
1065 bootdev); 1065 bootdev);
1066 return; 1066 return;
1067 } 1067 }
1068 1068
1069 printf("setup env for recovery..\n"); 1069 printf("setup env for recovery..\n");
1070 setenv("bootcmd", "run bootcmd_android_recovery"); 1070 setenv("bootcmd", "run bootcmd_android_recovery");
1071 } 1071 }
1072 #endif /*CONFIG_ANDROID_RECOVERY*/ 1072 #endif /*CONFIG_ANDROID_RECOVERY*/
1073 1073
1074 #endif /*CONFIG_FSL_FASTBOOT*/ 1074 #endif /*CONFIG_FSL_FASTBOOT*/
1075 1075