Eric Lee / smarc-uboot

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Commit 7d751d661afa526f4433bafa4ce8fe49bc310bdc

Authored by Nikita Kiryanov
Committed by Tom Rini
1 parent 43e568c4ae
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: am437x: cm-t43: update parameters for raw mmc boot 

Update U-Boot offset and size for raw mmc boot.

Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>

Showing 1 changed file with 4 additions and 0 deletions Inline Diff

include/configs/cm_t43.h
Diff comments   View file @ 7d751d6
1 /* 1 /*
2 * cm_t43.h 2 * cm_t43.h
3 * 3 *
4 * Copyright (C) 2015 Compulab, Ltd. 4 * Copyright (C) 2015 Compulab, Ltd.
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef __CONFIG_CM_T43_H 9 #ifndef __CONFIG_CM_T43_H
10 #define __CONFIG_CM_T43_H 10 #define __CONFIG_CM_T43_H
11 11
12 #define CONFIG_AM43XX 12 #define CONFIG_AM43XX
13 #define CONFIG_CM_T43 13 #define CONFIG_CM_T43
14 #define CONFIG_ARCH_CPU_INIT 14 #define CONFIG_ARCH_CPU_INIT
15 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ 15 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
16 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 16 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
17 17
18 #include <asm/arch/omap.h> 18 #include <asm/arch/omap.h>
19 19
20 /* Serial support */ 20 /* Serial support */
21 #define CONFIG_SYS_NS16550_SERIAL 21 #define CONFIG_SYS_NS16550_SERIAL
22 #define CONFIG_SYS_NS16550_CLK 48000000 22 #define CONFIG_SYS_NS16550_CLK 48000000
23 #define CONFIG_SYS_NS16550_COM1 0x44e09000 23 #define CONFIG_SYS_NS16550_COM1 0x44e09000
24 #ifdef CONFIG_SPL_BUILD 24 #ifdef CONFIG_SPL_BUILD
25 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 25 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
26 #endif 26 #endif
27 27
28 /* NAND support */ 28 /* NAND support */
29 #define CONFIG_NAND 29 #define CONFIG_NAND
30 #define CONFIG_NAND_OMAP_ELM 30 #define CONFIG_NAND_OMAP_ELM
31 #define CONFIG_SYS_NAND_ONFI_DETECTION 31 #define CONFIG_SYS_NAND_ONFI_DETECTION
32 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 32 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
33 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 33 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
34 #define CONFIG_SYS_NAND_OOBSIZE 64 34 #define CONFIG_SYS_NAND_OOBSIZE 64
35 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 35 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
36 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 36 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
37 #define CONFIG_SYS_NAND_ECCSIZE 512 37 #define CONFIG_SYS_NAND_ECCSIZE 512
38 #define CONFIG_SYS_NAND_ECCBYTES 14 38 #define CONFIG_SYS_NAND_ECCBYTES 14
39 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 39 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
40 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 40 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
41 CONFIG_SYS_NAND_PAGE_SIZE) 41 CONFIG_SYS_NAND_PAGE_SIZE)
42 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 42 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
43 10, 11, 12, 13, 14, 15, 16, 17, \ 43 10, 11, 12, 13, 14, 15, 16, 17, \
44 18, 19, 20, 21, 22, 23, 24, 25, \ 44 18, 19, 20, 21, 22, 23, 24, 25, \
45 26, 27, 28, 29, 30, 31, 32, 33, \ 45 26, 27, 28, 29, 30, 31, 32, 33, \
46 34, 35, 36, 37, 38, 39, 40, 41, \ 46 34, 35, 36, 37, 38, 39, 40, 41, \
47 42, 43, 44, 45, 46, 47, 48, 49, \ 47 42, 43, 44, 45, 46, 47, 48, 49, \
48 50, 51, 52, 53, 54, 55, 56, 57, } 48 50, 51, 52, 53, 54, 55, 56, 57, }
49 49
50 /* CPSW Ethernet support */ 50 /* CPSW Ethernet support */
51 #define CONFIG_DRIVER_TI_CPSW 51 #define CONFIG_DRIVER_TI_CPSW
52 #define CONFIG_MII 52 #define CONFIG_MII
53 #define CONFIG_BOOTP_DEFAULT 53 #define CONFIG_BOOTP_DEFAULT
54 #define CONFIG_BOOTP_SEND_HOSTNAME 54 #define CONFIG_BOOTP_SEND_HOSTNAME
55 #define CONFIG_BOOTP_GATEWAY 55 #define CONFIG_BOOTP_GATEWAY
56 #define CONFIG_NET_MULTI 56 #define CONFIG_NET_MULTI
57 #define CONFIG_PHY_GIGE 57 #define CONFIG_PHY_GIGE
58 #define CONFIG_PHY_ATHEROS 58 #define CONFIG_PHY_ATHEROS
59 #define CONFIG_PHYLIB 59 #define CONFIG_PHYLIB
60 #define CONFIG_SYS_RX_ETH_BUFFER 64 60 #define CONFIG_SYS_RX_ETH_BUFFER 64
61 61
62 /* USB support */ 62 /* USB support */
63 #define CONFIG_USB_HOST 63 #define CONFIG_USB_HOST
64 #define CONFIG_USB_XHCI 64 #define CONFIG_USB_XHCI
65 #define CONFIG_USB_XHCI_OMAP 65 #define CONFIG_USB_XHCI_OMAP
66 #define CONFIG_USB_XHCI_DWC3 66 #define CONFIG_USB_XHCI_DWC3
67 #define CONFIG_USB_STORAGE 67 #define CONFIG_USB_STORAGE
68 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 68 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
69 #define CONFIG_OMAP_USB_PHY 69 #define CONFIG_OMAP_USB_PHY
70 #define CONFIG_AM437X_USB2PHY2_HOST 70 #define CONFIG_AM437X_USB2PHY2_HOST
71 71
72 /* SPI Flash support */ 72 /* SPI Flash support */
73 #define CONFIG_TI_SPI_MMAP 73 #define CONFIG_TI_SPI_MMAP
74 #define CONFIG_SF_DEFAULT_SPEED 48000000 74 #define CONFIG_SF_DEFAULT_SPEED 48000000
75 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 75 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
76 76
77 /* Power */ 77 /* Power */
78 #define CONFIG_POWER 78 #define CONFIG_POWER
79 #define CONFIG_POWER_I2C 79 #define CONFIG_POWER_I2C
80 #define CONFIG_POWER_TPS65218 80 #define CONFIG_POWER_TPS65218
81 81
82 /* Enabling L2 Cache */ 82 /* Enabling L2 Cache */
83 #define CONFIG_SYS_L2_PL310 83 #define CONFIG_SYS_L2_PL310
84 #define CONFIG_SYS_PL310_BASE 0x48242000 84 #define CONFIG_SYS_PL310_BASE 0x48242000
85 #define CONFIG_SYS_CACHELINE_SIZE 32 85 #define CONFIG_SYS_CACHELINE_SIZE 32
86 86
87 /* 87 /*
88 * Since SPL did pll and ddr initialization for us, 88 * Since SPL did pll and ddr initialization for us,
89 * we don't need to do it twice. 89 * we don't need to do it twice.
90 */ 90 */
91 #if !defined(CONFIG_SPL_BUILD) 91 #if !defined(CONFIG_SPL_BUILD)
92 #define CONFIG_SKIP_LOWLEVEL_INIT 92 #define CONFIG_SKIP_LOWLEVEL_INIT
93 #endif 93 #endif
94 94
95 #define CONFIG_HSMMC2_8BIT 95 #define CONFIG_HSMMC2_8BIT
96 96
97 #include <configs/ti_armv7_omap.h> 97 #include <configs/ti_armv7_omap.h>
98 #undef CONFIG_SPL_OS_BOOT 98 #undef CONFIG_SPL_OS_BOOT
99 #undef CONFIG_SPL_GPIO_SUPPORT 99 #undef CONFIG_SPL_GPIO_SUPPORT
100 #undef CONFIG_SPL_NAND_SUPPORT 100 #undef CONFIG_SPL_NAND_SUPPORT
101 #undef CONFIG_BOOTDELAY 101 #undef CONFIG_BOOTDELAY
102 #undef CONFIG_SYS_MONITOR_LEN
103 #undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
102 #include <config_distro_defaults.h> 104 #include <config_distro_defaults.h>
103 #define CONFIG_ZERO_BOOTDELAY_CHECK 105 #define CONFIG_ZERO_BOOTDELAY_CHECK
104 #undef CONFIG_CMD_IMLS 106 #undef CONFIG_CMD_IMLS
105 107
106 #define CONFIG_ENV_SIZE (16 * 1024) 108 #define CONFIG_ENV_SIZE (16 * 1024)
107 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 109 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
108 110
109 #define V_OSCK 24000000 /* Clock output from T2 */ 111 #define V_OSCK 24000000 /* Clock output from T2 */
110 #define V_SCLK (V_OSCK) 112 #define V_SCLK (V_OSCK)
111 113
112 #define CONFIG_ENV_IS_IN_SPI_FLASH 114 #define CONFIG_ENV_IS_IN_SPI_FLASH
113 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 115 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
114 #define CONFIG_ENV_OFFSET (768 * 1024) 116 #define CONFIG_ENV_OFFSET (768 * 1024)
115 #define CONFIG_ENV_SPI_MAX_HZ 48000000 117 #define CONFIG_ENV_SPI_MAX_HZ 48000000
116 118
117 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 119 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
118 120
119 /* Enhance our eMMC support / experience. */ 121 /* Enhance our eMMC support / experience. */
120 #define CONFIG_CMD_GPT 122 #define CONFIG_CMD_GPT
121 #define CONFIG_EFI_PARTITION 123 #define CONFIG_EFI_PARTITION
122 124
123 #define CONFIG_EXTRA_ENV_SETTINGS \ 125 #define CONFIG_EXTRA_ENV_SETTINGS \
124 "loadaddr=0x80200000\0" \ 126 "loadaddr=0x80200000\0" \
125 "fdtaddr=0x81200000\0" \ 127 "fdtaddr=0x81200000\0" \
126 "bootm_size=0x8000000\0" \ 128 "bootm_size=0x8000000\0" \
127 "autoload=no\0" \ 129 "autoload=no\0" \
128 "console=ttyO0,115200n8\0" \ 130 "console=ttyO0,115200n8\0" \
129 "fdtfile=am437x-sb-som-t43.dtb\0" \ 131 "fdtfile=am437x-sb-som-t43.dtb\0" \
130 "kernel=zImage-cm-t43\0" \ 132 "kernel=zImage-cm-t43\0" \
131 "bootscr=bootscr.img\0" \ 133 "bootscr=bootscr.img\0" \
132 "emmcroot=/dev/mmcblk0p2 rw\0" \ 134 "emmcroot=/dev/mmcblk0p2 rw\0" \
133 "emmcrootfstype=ext4 rootwait\0" \ 135 "emmcrootfstype=ext4 rootwait\0" \
134 "emmcargs=setenv bootargs console=${console} " \ 136 "emmcargs=setenv bootargs console=${console} " \
135 "root=${emmcroot} " \ 137 "root=${emmcroot} " \
136 "rootfstype=${emmcrootfstype}\0" \ 138 "rootfstype=${emmcrootfstype}\0" \
137 "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \ 139 "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
138 "bootscript=echo Running bootscript from mmc ...; " \ 140 "bootscript=echo Running bootscript from mmc ...; " \
139 "source ${loadaddr}\0" \ 141 "source ${loadaddr}\0" \
140 "emmcboot=echo Booting from emmc ... && " \ 142 "emmcboot=echo Booting from emmc ... && " \
141 "run emmcargs && " \ 143 "run emmcargs && " \
142 "load mmc 1 ${loadaddr} ${kernel} && " \ 144 "load mmc 1 ${loadaddr} ${kernel} && " \
143 "load mmc 1 ${fdtaddr} ${fdtfile} && " \ 145 "load mmc 1 ${fdtaddr} ${fdtfile} && " \
144 "bootz ${loadaddr} - ${fdtaddr}\0" 146 "bootz ${loadaddr} - ${fdtaddr}\0"
145 147
146 #define CONFIG_BOOTCOMMAND \ 148 #define CONFIG_BOOTCOMMAND \
147 "mmc dev 0; " \ 149 "mmc dev 0; " \
148 "if mmc rescan; then " \ 150 "if mmc rescan; then " \
149 "if run loadbootscript; then " \ 151 "if run loadbootscript; then " \
150 "run bootscript; " \ 152 "run bootscript; " \
151 "fi; " \ 153 "fi; " \
152 "fi; " \ 154 "fi; " \
153 "mmc dev 1; " \ 155 "mmc dev 1; " \
154 "if mmc rescan; then " \ 156 "if mmc rescan; then " \
155 "run emmcboot; " \ 157 "run emmcboot; " \
156 "fi;" 158 "fi;"
157 159
158 160
159 #define CONFIG_CONS_INDEX 1 161 #define CONFIG_CONS_INDEX 1
160 162
161 /* SPL defines. */ 163 /* SPL defines. */
162 #define CONFIG_SPL_TEXT_BASE 0x40300350 164 #define CONFIG_SPL_TEXT_BASE 0x40300350
163 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 165 #define CONFIG_SPL_MAX_SIZE (64 * 1024)
164 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) 166 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
165 #define CONFIG_SPL_POWER_SUPPORT 167 #define CONFIG_SPL_POWER_SUPPORT
166 #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) 168 #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
169 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
170 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x480
167 #define CONFIG_SPL_SPI_SUPPORT 171 #define CONFIG_SPL_SPI_SUPPORT
168 #define CONFIG_SPL_SPI_FLASH_SUPPORT 172 #define CONFIG_SPL_SPI_FLASH_SUPPORT
169 #define CONFIG_SPL_SPI_LOAD 173 #define CONFIG_SPL_SPI_LOAD
170 #define CONFIG_SPL_I2C_SUPPORT 174 #define CONFIG_SPL_I2C_SUPPORT
171 #define CONFIG_SPL_POWER_SUPPORT 175 #define CONFIG_SPL_POWER_SUPPORT
172 176
173 #endif /* __CONFIG_CM_T43_H */ 177 #endif /* __CONFIG_CM_T43_H */
174 178