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Commit 83d1b3876695c4f21faff2b731d9ef83f38ed208

Authored by Jean-Christophe PLAGNIOL-VILLARD
Committed by Jon Loeliger
1 parent b6f29c84c2
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mpc86xx: Fix implicit declaration of functions 'init_laws' and 'disable_law' 

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Showing 1 changed file with 1 additions and 0 deletions Inline Diff

cpu/mpc86xx/cpu_init.c
Diff comments   View file @ 83d1b38
1 /* 1 /*
2 * Copyright 2004 Freescale Semiconductor. 2 * Copyright 2004 Freescale Semiconductor.
3 * Jeff Brown 3 * Jeff Brown
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 * 5 *
6 * See file CREDITS for list of people who contributed to this 6 * See file CREDITS for list of people who contributed to this
7 * project. 7 * project.
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of 11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version. 12 * the License, or (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA 22 * MA 02111-1307 USA
23 */ 23 */
24 24
25 /* 25 /*
26 * cpu_init.c - low level cpu init 26 * cpu_init.c - low level cpu init
27 */ 27 */
28 28
29 #include <common.h> 29 #include <common.h>
30 #include <mpc86xx.h> 30 #include <mpc86xx.h>
31 #include <asm/fsl_law.h>
31 32
32 DECLARE_GLOBAL_DATA_PTR; 33 DECLARE_GLOBAL_DATA_PTR;
33 34
34 /* 35 /*
35 * Breathe some life into the CPU... 36 * Breathe some life into the CPU...
36 * 37 *
37 * Set up the memory map 38 * Set up the memory map
38 * initialize a bunch of registers 39 * initialize a bunch of registers
39 */ 40 */
40 41
41 void cpu_init_f(void) 42 void cpu_init_f(void)
42 { 43 {
43 volatile immap_t *immap = (immap_t *)CFG_IMMR; 44 volatile immap_t *immap = (immap_t *)CFG_IMMR;
44 volatile ccsr_lbc_t *memctl = &immap->im_lbc; 45 volatile ccsr_lbc_t *memctl = &immap->im_lbc;
45 46
46 /* Pointer is writable since we allocated a register for it */ 47 /* Pointer is writable since we allocated a register for it */
47 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); 48 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
48 49
49 /* Clear initial global data */ 50 /* Clear initial global data */
50 memset ((void *) gd, 0, sizeof (gd_t)); 51 memset ((void *) gd, 0, sizeof (gd_t));
51 52
52 #ifdef CONFIG_FSL_LAW 53 #ifdef CONFIG_FSL_LAW
53 init_laws(); 54 init_laws();
54 #endif 55 #endif
55 56
56 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary 57 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
57 * addresses - these have to be modified later when FLASH size 58 * addresses - these have to be modified later when FLASH size
58 * has been determined 59 * has been determined
59 */ 60 */
60 61
61 #if defined(CFG_OR0_REMAP) 62 #if defined(CFG_OR0_REMAP)
62 memctl->or0 = CFG_OR0_REMAP; 63 memctl->or0 = CFG_OR0_REMAP;
63 #endif 64 #endif
64 #if defined(CFG_OR1_REMAP) 65 #if defined(CFG_OR1_REMAP)
65 memctl->or1 = CFG_OR1_REMAP; 66 memctl->or1 = CFG_OR1_REMAP;
66 #endif 67 #endif
67 68
68 /* now restrict to preliminary range */ 69 /* now restrict to preliminary range */
69 #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) 70 #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
70 memctl->br0 = CFG_BR0_PRELIM; 71 memctl->br0 = CFG_BR0_PRELIM;
71 memctl->or0 = CFG_OR0_PRELIM; 72 memctl->or0 = CFG_OR0_PRELIM;
72 #endif 73 #endif
73 74
74 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) 75 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
75 memctl->or1 = CFG_OR1_PRELIM; 76 memctl->or1 = CFG_OR1_PRELIM;
76 memctl->br1 = CFG_BR1_PRELIM; 77 memctl->br1 = CFG_BR1_PRELIM;
77 #endif 78 #endif
78 79
79 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) 80 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
80 memctl->or2 = CFG_OR2_PRELIM; 81 memctl->or2 = CFG_OR2_PRELIM;
81 memctl->br2 = CFG_BR2_PRELIM; 82 memctl->br2 = CFG_BR2_PRELIM;
82 #endif 83 #endif
83 84
84 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) 85 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
85 memctl->or3 = CFG_OR3_PRELIM; 86 memctl->or3 = CFG_OR3_PRELIM;
86 memctl->br3 = CFG_BR3_PRELIM; 87 memctl->br3 = CFG_BR3_PRELIM;
87 #endif 88 #endif
88 89
89 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) 90 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
90 memctl->or4 = CFG_OR4_PRELIM; 91 memctl->or4 = CFG_OR4_PRELIM;
91 memctl->br4 = CFG_BR4_PRELIM; 92 memctl->br4 = CFG_BR4_PRELIM;
92 #endif 93 #endif
93 94
94 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) 95 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
95 memctl->or5 = CFG_OR5_PRELIM; 96 memctl->or5 = CFG_OR5_PRELIM;
96 memctl->br5 = CFG_BR5_PRELIM; 97 memctl->br5 = CFG_BR5_PRELIM;
97 #endif 98 #endif
98 99
99 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) 100 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
100 memctl->or6 = CFG_OR6_PRELIM; 101 memctl->or6 = CFG_OR6_PRELIM;
101 memctl->br6 = CFG_BR6_PRELIM; 102 memctl->br6 = CFG_BR6_PRELIM;
102 #endif 103 #endif
103 104
104 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) 105 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
105 memctl->or7 = CFG_OR7_PRELIM; 106 memctl->or7 = CFG_OR7_PRELIM;
106 memctl->br7 = CFG_BR7_PRELIM; 107 memctl->br7 = CFG_BR7_PRELIM;
107 #endif 108 #endif
108 109
109 /* enable the timebase bit in HID0 */ 110 /* enable the timebase bit in HID0 */
110 set_hid0(get_hid0() | 0x4000000); 111 set_hid0(get_hid0() | 0x4000000);
111 112
112 /* enable EMCP, SYNCBE | ABE bits in HID1 */ 113 /* enable EMCP, SYNCBE | ABE bits in HID1 */
113 set_hid1(get_hid1() | 0x80000C00); 114 set_hid1(get_hid1() | 0x80000C00);
114 } 115 }
115 116
116 /* 117 /*
117 * initialize higher level parts of CPU like timers 118 * initialize higher level parts of CPU like timers
118 */ 119 */
119 int cpu_init_r(void) 120 int cpu_init_r(void)
120 { 121 {
121 #ifdef CONFIG_FSL_LAW 122 #ifdef CONFIG_FSL_LAW
122 disable_law(0); 123 disable_law(0);
123 #endif 124 #endif
124 return 0; 125 return 0;
125 } 126 }
126 127