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Commit 84295f2a202b6c062ec17e148e3418af0db795f5

Authored by Vignesh R
Committed by Tom Rini
1 parent 4d0fec0e69
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node 

Update the spi-max-frequency property of m25p80 flash slave to match
that of TI QSPI controller node, so that QSPI operations happen at
maximum supported frequency of 76.8MHz.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

Showing 2 changed files with 2 additions and 2 deletions Inline Diff

arch/arm/dts/dra7-evm.dts
Diff comments   View file @ 84295f2
1 /* 1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "dra74x.dtsi" 10 #include "dra74x.dtsi"
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 12
13 / { 13 / {
14 model = "TI DRA742"; 14 model = "TI DRA742";
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; 15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
16 16
17 chosen { 17 chosen {
18 stdout-path = &uart1; 18 stdout-path = &uart1;
19 tick-timer = &timer2; 19 tick-timer = &timer2;
20 }; 20 };
21 21
22 memory { 22 memory {
23 device_type = "memory"; 23 device_type = "memory";
24 reg = <0x80000000 0x60000000>; /* 1536 MB */ 24 reg = <0x80000000 0x60000000>; /* 1536 MB */
25 }; 25 };
26 26
27 evm_3v3_sd: fixedregulator-sd { 27 evm_3v3_sd: fixedregulator-sd {
28 compatible = "regulator-fixed"; 28 compatible = "regulator-fixed";
29 regulator-name = "evm_3v3_sd"; 29 regulator-name = "evm_3v3_sd";
30 regulator-min-microvolt = <3300000>; 30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>; 31 regulator-max-microvolt = <3300000>;
32 enable-active-high; 32 enable-active-high;
33 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 33 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
34 }; 34 };
35 35
36 mmc2_3v3: fixedregulator-mmc2 { 36 mmc2_3v3: fixedregulator-mmc2 {
37 compatible = "regulator-fixed"; 37 compatible = "regulator-fixed";
38 regulator-name = "mmc2_3v3"; 38 regulator-name = "mmc2_3v3";
39 regulator-min-microvolt = <3300000>; 39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>;
41 }; 41 };
42 42
43 extcon_usb1: extcon_usb1 { 43 extcon_usb1: extcon_usb1 {
44 compatible = "linux,extcon-usb-gpio"; 44 compatible = "linux,extcon-usb-gpio";
45 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 45 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
46 }; 46 };
47 47
48 extcon_usb2: extcon_usb2 { 48 extcon_usb2: extcon_usb2 {
49 compatible = "linux,extcon-usb-gpio"; 49 compatible = "linux,extcon-usb-gpio";
50 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 50 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
51 }; 51 };
52 52
53 vtt_fixed: fixedregulator-vtt { 53 vtt_fixed: fixedregulator-vtt {
54 compatible = "regulator-fixed"; 54 compatible = "regulator-fixed";
55 regulator-name = "vtt_fixed"; 55 regulator-name = "vtt_fixed";
56 regulator-min-microvolt = <1350000>; 56 regulator-min-microvolt = <1350000>;
57 regulator-max-microvolt = <1350000>; 57 regulator-max-microvolt = <1350000>;
58 regulator-always-on; 58 regulator-always-on;
59 regulator-boot-on; 59 regulator-boot-on;
60 enable-active-high; 60 enable-active-high;
61 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; 61 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
62 }; 62 };
63 }; 63 };
64 64
65 &dra7_pmx_core { 65 &dra7_pmx_core {
66 pinctrl-names = "default"; 66 pinctrl-names = "default";
67 pinctrl-0 = <&vtt_pin>; 67 pinctrl-0 = <&vtt_pin>;
68 68
69 vtt_pin: pinmux_vtt_pin { 69 vtt_pin: pinmux_vtt_pin {
70 pinctrl-single,pins = < 70 pinctrl-single,pins = <
71 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ 71 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
72 >; 72 >;
73 }; 73 };
74 74
75 i2c1_pins: pinmux_i2c1_pins { 75 i2c1_pins: pinmux_i2c1_pins {
76 pinctrl-single,pins = < 76 pinctrl-single,pins = <
77 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ 77 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
78 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ 78 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
79 >; 79 >;
80 }; 80 };
81 81
82 i2c2_pins: pinmux_i2c2_pins { 82 i2c2_pins: pinmux_i2c2_pins {
83 pinctrl-single,pins = < 83 pinctrl-single,pins = <
84 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ 84 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
85 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ 85 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
86 >; 86 >;
87 }; 87 };
88 88
89 i2c3_pins: pinmux_i2c3_pins { 89 i2c3_pins: pinmux_i2c3_pins {
90 pinctrl-single,pins = < 90 pinctrl-single,pins = <
91 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ 91 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
92 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ 92 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
93 >; 93 >;
94 }; 94 };
95 95
96 mcspi1_pins: pinmux_mcspi1_pins { 96 mcspi1_pins: pinmux_mcspi1_pins {
97 pinctrl-single,pins = < 97 pinctrl-single,pins = <
98 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */ 98 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
99 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */ 99 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
100 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */ 100 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
101 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ 101 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
102 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ 102 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
103 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ 103 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
104 >; 104 >;
105 }; 105 };
106 106
107 mcspi2_pins: pinmux_mcspi2_pins { 107 mcspi2_pins: pinmux_mcspi2_pins {
108 pinctrl-single,pins = < 108 pinctrl-single,pins = <
109 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ 109 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
110 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 110 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
111 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ 111 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
112 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ 112 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
113 >; 113 >;
114 }; 114 };
115 115
116 uart1_pins: pinmux_uart1_pins { 116 uart1_pins: pinmux_uart1_pins {
117 pinctrl-single,pins = < 117 pinctrl-single,pins = <
118 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ 118 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
119 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ 119 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
120 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ 120 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
121 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ 121 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
122 >; 122 >;
123 }; 123 };
124 124
125 uart2_pins: pinmux_uart2_pins { 125 uart2_pins: pinmux_uart2_pins {
126 pinctrl-single,pins = < 126 pinctrl-single,pins = <
127 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ 127 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
128 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ 128 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
129 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ 129 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
130 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ 130 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
131 >; 131 >;
132 }; 132 };
133 133
134 uart3_pins: pinmux_uart3_pins { 134 uart3_pins: pinmux_uart3_pins {
135 pinctrl-single,pins = < 135 pinctrl-single,pins = <
136 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ 136 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
137 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ 137 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
138 >; 138 >;
139 }; 139 };
140 140
141 qspi1_pins: pinmux_qspi1_pins { 141 qspi1_pins: pinmux_qspi1_pins {
142 pinctrl-single,pins = < 142 pinctrl-single,pins = <
143 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ 143 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
144 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ 144 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
145 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ 145 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
146 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ 146 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
147 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ 147 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
148 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ 148 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
149 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ 149 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
150 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ 150 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
151 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ 151 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
152 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ 152 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
153 >; 153 >;
154 }; 154 };
155 155
156 usb1_pins: pinmux_usb1_pins { 156 usb1_pins: pinmux_usb1_pins {
157 pinctrl-single,pins = < 157 pinctrl-single,pins = <
158 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ 158 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
159 >; 159 >;
160 }; 160 };
161 161
162 usb2_pins: pinmux_usb2_pins { 162 usb2_pins: pinmux_usb2_pins {
163 pinctrl-single,pins = < 163 pinctrl-single,pins = <
164 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ 164 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
165 >; 165 >;
166 }; 166 };
167 167
168 nand_flash_x16: nand_flash_x16 { 168 nand_flash_x16: nand_flash_x16 {
169 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch 169 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
170 * So NAND flash requires following switch settings: 170 * So NAND flash requires following switch settings:
171 * SW5.9 (GPMC_WPN) = LOW 171 * SW5.9 (GPMC_WPN) = LOW
172 * SW5.1 (NAND_BOOTn) = HIGH */ 172 * SW5.1 (NAND_BOOTn) = HIGH */
173 pinctrl-single,pins = < 173 pinctrl-single,pins = <
174 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 174 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
175 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 175 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
176 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ 176 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
177 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ 177 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
178 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ 178 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
179 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ 179 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
180 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ 180 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
181 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ 181 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
182 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ 182 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
183 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ 183 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
184 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ 184 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
185 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ 185 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
186 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ 186 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
187 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ 187 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
188 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ 188 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
189 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ 189 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
190 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ 190 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
191 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ 191 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
192 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ 192 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
193 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ 193 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
194 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ 194 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
195 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ 195 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
196 >; 196 >;
197 }; 197 };
198 198
199 cpsw_default: cpsw_default { 199 cpsw_default: cpsw_default {
200 pinctrl-single,pins = < 200 pinctrl-single,pins = <
201 /* Slave 1 */ 201 /* Slave 1 */
202 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ 202 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
203 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ 203 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
204 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ 204 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
205 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ 205 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
206 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ 206 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
207 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ 207 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
208 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ 208 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
209 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ 209 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
210 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ 210 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
211 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ 211 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
212 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ 212 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
213 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ 213 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
214 214
215 /* Slave 2 */ 215 /* Slave 2 */
216 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ 216 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
217 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ 217 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
218 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ 218 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
219 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ 219 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
220 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ 220 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
221 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ 221 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
222 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ 222 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
223 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ 223 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
224 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ 224 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
225 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ 225 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
226 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ 226 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
227 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ 227 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
228 >; 228 >;
229 229
230 }; 230 };
231 231
232 cpsw_sleep: cpsw_sleep { 232 cpsw_sleep: cpsw_sleep {
233 pinctrl-single,pins = < 233 pinctrl-single,pins = <
234 /* Slave 1 */ 234 /* Slave 1 */
235 0x250 (MUX_MODE15) 235 0x250 (MUX_MODE15)
236 0x254 (MUX_MODE15) 236 0x254 (MUX_MODE15)
237 0x258 (MUX_MODE15) 237 0x258 (MUX_MODE15)
238 0x25c (MUX_MODE15) 238 0x25c (MUX_MODE15)
239 0x260 (MUX_MODE15) 239 0x260 (MUX_MODE15)
240 0x264 (MUX_MODE15) 240 0x264 (MUX_MODE15)
241 0x268 (MUX_MODE15) 241 0x268 (MUX_MODE15)
242 0x26c (MUX_MODE15) 242 0x26c (MUX_MODE15)
243 0x270 (MUX_MODE15) 243 0x270 (MUX_MODE15)
244 0x274 (MUX_MODE15) 244 0x274 (MUX_MODE15)
245 0x278 (MUX_MODE15) 245 0x278 (MUX_MODE15)
246 0x27c (MUX_MODE15) 246 0x27c (MUX_MODE15)
247 247
248 /* Slave 2 */ 248 /* Slave 2 */
249 0x198 (MUX_MODE15) 249 0x198 (MUX_MODE15)
250 0x19c (MUX_MODE15) 250 0x19c (MUX_MODE15)
251 0x1a0 (MUX_MODE15) 251 0x1a0 (MUX_MODE15)
252 0x1a4 (MUX_MODE15) 252 0x1a4 (MUX_MODE15)
253 0x1a8 (MUX_MODE15) 253 0x1a8 (MUX_MODE15)
254 0x1ac (MUX_MODE15) 254 0x1ac (MUX_MODE15)
255 0x1b0 (MUX_MODE15) 255 0x1b0 (MUX_MODE15)
256 0x1b4 (MUX_MODE15) 256 0x1b4 (MUX_MODE15)
257 0x1b8 (MUX_MODE15) 257 0x1b8 (MUX_MODE15)
258 0x1bc (MUX_MODE15) 258 0x1bc (MUX_MODE15)
259 0x1c0 (MUX_MODE15) 259 0x1c0 (MUX_MODE15)
260 0x1c4 (MUX_MODE15) 260 0x1c4 (MUX_MODE15)
261 >; 261 >;
262 }; 262 };
263 263
264 davinci_mdio_default: davinci_mdio_default { 264 davinci_mdio_default: davinci_mdio_default {
265 pinctrl-single,pins = < 265 pinctrl-single,pins = <
266 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ 266 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
267 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 267 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
268 >; 268 >;
269 }; 269 };
270 270
271 davinci_mdio_sleep: davinci_mdio_sleep { 271 davinci_mdio_sleep: davinci_mdio_sleep {
272 pinctrl-single,pins = < 272 pinctrl-single,pins = <
273 0x23c (MUX_MODE15) 273 0x23c (MUX_MODE15)
274 0x240 (MUX_MODE15) 274 0x240 (MUX_MODE15)
275 >; 275 >;
276 }; 276 };
277 277
278 dcan1_pins_default: dcan1_pins_default { 278 dcan1_pins_default: dcan1_pins_default {
279 pinctrl-single,pins = < 279 pinctrl-single,pins = <
280 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 280 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
281 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 281 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
282 >; 282 >;
283 }; 283 };
284 284
285 dcan1_pins_sleep: dcan1_pins_sleep { 285 dcan1_pins_sleep: dcan1_pins_sleep {
286 pinctrl-single,pins = < 286 pinctrl-single,pins = <
287 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 287 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
288 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ 288 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
289 >; 289 >;
290 }; 290 };
291 }; 291 };
292 292
293 &i2c1 { 293 &i2c1 {
294 status = "okay"; 294 status = "okay";
295 pinctrl-names = "default"; 295 pinctrl-names = "default";
296 pinctrl-0 = <&i2c1_pins>; 296 pinctrl-0 = <&i2c1_pins>;
297 clock-frequency = <400000>; 297 clock-frequency = <400000>;
298 298
299 tps659038: tps659038@58 { 299 tps659038: tps659038@58 {
300 compatible = "ti,tps659038"; 300 compatible = "ti,tps659038";
301 reg = <0x58>; 301 reg = <0x58>;
302 302
303 tps659038_pmic { 303 tps659038_pmic {
304 compatible = "ti,tps659038-pmic"; 304 compatible = "ti,tps659038-pmic";
305 305
306 regulators { 306 regulators {
307 smps123_reg: smps123 { 307 smps123_reg: smps123 {
308 /* VDD_MPU */ 308 /* VDD_MPU */
309 regulator-name = "smps123"; 309 regulator-name = "smps123";
310 regulator-min-microvolt = < 850000>; 310 regulator-min-microvolt = < 850000>;
311 regulator-max-microvolt = <1250000>; 311 regulator-max-microvolt = <1250000>;
312 regulator-always-on; 312 regulator-always-on;
313 regulator-boot-on; 313 regulator-boot-on;
314 }; 314 };
315 315
316 smps45_reg: smps45 { 316 smps45_reg: smps45 {
317 /* VDD_DSPEVE */ 317 /* VDD_DSPEVE */
318 regulator-name = "smps45"; 318 regulator-name = "smps45";
319 regulator-min-microvolt = < 850000>; 319 regulator-min-microvolt = < 850000>;
320 regulator-max-microvolt = <1150000>; 320 regulator-max-microvolt = <1150000>;
321 regulator-always-on; 321 regulator-always-on;
322 regulator-boot-on; 322 regulator-boot-on;
323 }; 323 };
324 324
325 smps6_reg: smps6 { 325 smps6_reg: smps6 {
326 /* VDD_GPU - over VDD_SMPS6 */ 326 /* VDD_GPU - over VDD_SMPS6 */
327 regulator-name = "smps6"; 327 regulator-name = "smps6";
328 regulator-min-microvolt = <850000>; 328 regulator-min-microvolt = <850000>;
329 regulator-max-microvolt = <1250000>; 329 regulator-max-microvolt = <1250000>;
330 regulator-always-on; 330 regulator-always-on;
331 regulator-boot-on; 331 regulator-boot-on;
332 }; 332 };
333 333
334 smps7_reg: smps7 { 334 smps7_reg: smps7 {
335 /* CORE_VDD */ 335 /* CORE_VDD */
336 regulator-name = "smps7"; 336 regulator-name = "smps7";
337 regulator-min-microvolt = <850000>; 337 regulator-min-microvolt = <850000>;
338 regulator-max-microvolt = <1060000>; 338 regulator-max-microvolt = <1060000>;
339 regulator-always-on; 339 regulator-always-on;
340 regulator-boot-on; 340 regulator-boot-on;
341 }; 341 };
342 342
343 smps8_reg: smps8 { 343 smps8_reg: smps8 {
344 /* VDD_IVAHD */ 344 /* VDD_IVAHD */
345 regulator-name = "smps8"; 345 regulator-name = "smps8";
346 regulator-min-microvolt = < 850000>; 346 regulator-min-microvolt = < 850000>;
347 regulator-max-microvolt = <1250000>; 347 regulator-max-microvolt = <1250000>;
348 regulator-always-on; 348 regulator-always-on;
349 regulator-boot-on; 349 regulator-boot-on;
350 }; 350 };
351 351
352 smps9_reg: smps9 { 352 smps9_reg: smps9 {
353 /* VDDS1V8 */ 353 /* VDDS1V8 */
354 regulator-name = "smps9"; 354 regulator-name = "smps9";
355 regulator-min-microvolt = <1800000>; 355 regulator-min-microvolt = <1800000>;
356 regulator-max-microvolt = <1800000>; 356 regulator-max-microvolt = <1800000>;
357 regulator-always-on; 357 regulator-always-on;
358 regulator-boot-on; 358 regulator-boot-on;
359 }; 359 };
360 360
361 ldo1_reg: ldo1 { 361 ldo1_reg: ldo1 {
362 /* LDO1_OUT --> SDIO */ 362 /* LDO1_OUT --> SDIO */
363 regulator-name = "ldo1"; 363 regulator-name = "ldo1";
364 regulator-min-microvolt = <1800000>; 364 regulator-min-microvolt = <1800000>;
365 regulator-max-microvolt = <3300000>; 365 regulator-max-microvolt = <3300000>;
366 regulator-boot-on; 366 regulator-boot-on;
367 }; 367 };
368 368
369 ldo2_reg: ldo2 { 369 ldo2_reg: ldo2 {
370 /* VDD_RTCIO */ 370 /* VDD_RTCIO */
371 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ 371 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
372 regulator-name = "ldo2"; 372 regulator-name = "ldo2";
373 regulator-min-microvolt = <3300000>; 373 regulator-min-microvolt = <3300000>;
374 regulator-max-microvolt = <3300000>; 374 regulator-max-microvolt = <3300000>;
375 regulator-always-on; 375 regulator-always-on;
376 regulator-boot-on; 376 regulator-boot-on;
377 }; 377 };
378 378
379 ldo3_reg: ldo3 { 379 ldo3_reg: ldo3 {
380 /* VDDA_1V8_PHY */ 380 /* VDDA_1V8_PHY */
381 regulator-name = "ldo3"; 381 regulator-name = "ldo3";
382 regulator-min-microvolt = <1800000>; 382 regulator-min-microvolt = <1800000>;
383 regulator-max-microvolt = <1800000>; 383 regulator-max-microvolt = <1800000>;
384 regulator-always-on; 384 regulator-always-on;
385 regulator-boot-on; 385 regulator-boot-on;
386 }; 386 };
387 387
388 ldo9_reg: ldo9 { 388 ldo9_reg: ldo9 {
389 /* VDD_RTC */ 389 /* VDD_RTC */
390 regulator-name = "ldo9"; 390 regulator-name = "ldo9";
391 regulator-min-microvolt = <1050000>; 391 regulator-min-microvolt = <1050000>;
392 regulator-max-microvolt = <1050000>; 392 regulator-max-microvolt = <1050000>;
393 regulator-always-on; 393 regulator-always-on;
394 regulator-boot-on; 394 regulator-boot-on;
395 }; 395 };
396 396
397 ldoln_reg: ldoln { 397 ldoln_reg: ldoln {
398 /* VDDA_1V8_PLL */ 398 /* VDDA_1V8_PLL */
399 regulator-name = "ldoln"; 399 regulator-name = "ldoln";
400 regulator-min-microvolt = <1800000>; 400 regulator-min-microvolt = <1800000>;
401 regulator-max-microvolt = <1800000>; 401 regulator-max-microvolt = <1800000>;
402 regulator-always-on; 402 regulator-always-on;
403 regulator-boot-on; 403 regulator-boot-on;
404 }; 404 };
405 405
406 ldousb_reg: ldousb { 406 ldousb_reg: ldousb {
407 /* VDDA_3V_USB: VDDA_USBHS33 */ 407 /* VDDA_3V_USB: VDDA_USBHS33 */
408 regulator-name = "ldousb"; 408 regulator-name = "ldousb";
409 regulator-min-microvolt = <3300000>; 409 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>; 410 regulator-max-microvolt = <3300000>;
411 regulator-boot-on; 411 regulator-boot-on;
412 }; 412 };
413 }; 413 };
414 }; 414 };
415 }; 415 };
416 416
417 pcf_gpio_21: gpio@21 { 417 pcf_gpio_21: gpio@21 {
418 compatible = "ti,pcf8575"; 418 compatible = "ti,pcf8575";
419 reg = <0x21>; 419 reg = <0x21>;
420 lines-initial-states = <0x1408>; 420 lines-initial-states = <0x1408>;
421 gpio-controller; 421 gpio-controller;
422 #gpio-cells = <2>; 422 #gpio-cells = <2>;
423 interrupt-parent = <&gpio6>; 423 interrupt-parent = <&gpio6>;
424 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 424 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
425 interrupt-controller; 425 interrupt-controller;
426 #interrupt-cells = <2>; 426 #interrupt-cells = <2>;
427 u-boot,i2c-offset-len = <0>; 427 u-boot,i2c-offset-len = <0>;
428 }; 428 };
429 429
430 }; 430 };
431 431
432 &i2c2 { 432 &i2c2 {
433 status = "okay"; 433 status = "okay";
434 pinctrl-names = "default"; 434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c2_pins>; 435 pinctrl-0 = <&i2c2_pins>;
436 clock-frequency = <400000>; 436 clock-frequency = <400000>;
437 }; 437 };
438 438
439 &i2c3 { 439 &i2c3 {
440 status = "okay"; 440 status = "okay";
441 pinctrl-names = "default"; 441 pinctrl-names = "default";
442 pinctrl-0 = <&i2c3_pins>; 442 pinctrl-0 = <&i2c3_pins>;
443 clock-frequency = <400000>; 443 clock-frequency = <400000>;
444 }; 444 };
445 445
446 &mcspi1 { 446 &mcspi1 {
447 status = "okay"; 447 status = "okay";
448 pinctrl-names = "default"; 448 pinctrl-names = "default";
449 pinctrl-0 = <&mcspi1_pins>; 449 pinctrl-0 = <&mcspi1_pins>;
450 }; 450 };
451 451
452 &mcspi2 { 452 &mcspi2 {
453 status = "okay"; 453 status = "okay";
454 pinctrl-names = "default"; 454 pinctrl-names = "default";
455 pinctrl-0 = <&mcspi2_pins>; 455 pinctrl-0 = <&mcspi2_pins>;
456 }; 456 };
457 457
458 &uart1 { 458 &uart1 {
459 status = "okay"; 459 status = "okay";
460 pinctrl-names = "default"; 460 pinctrl-names = "default";
461 pinctrl-0 = <&uart1_pins>; 461 pinctrl-0 = <&uart1_pins>;
462 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 462 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
463 <&dra7_pmx_core 0x3e0>; 463 <&dra7_pmx_core 0x3e0>;
464 }; 464 };
465 465
466 &uart2 { 466 &uart2 {
467 status = "okay"; 467 status = "okay";
468 pinctrl-names = "default"; 468 pinctrl-names = "default";
469 pinctrl-0 = <&uart2_pins>; 469 pinctrl-0 = <&uart2_pins>;
470 }; 470 };
471 471
472 &uart3 { 472 &uart3 {
473 status = "okay"; 473 status = "okay";
474 pinctrl-names = "default"; 474 pinctrl-names = "default";
475 pinctrl-0 = <&uart3_pins>; 475 pinctrl-0 = <&uart3_pins>;
476 }; 476 };
477 477
478 &mmc1 { 478 &mmc1 {
479 status = "okay"; 479 status = "okay";
480 vmmc-supply = <&evm_3v3_sd>; 480 vmmc-supply = <&evm_3v3_sd>;
481 vmmc_aux-supply = <&ldo1_reg>; 481 vmmc_aux-supply = <&ldo1_reg>;
482 bus-width = <4>; 482 bus-width = <4>;
483 /* 483 /*
484 * SDCD signal is not being used here - using the fact that GPIO mode 484 * SDCD signal is not being used here - using the fact that GPIO mode
485 * is always hardwired. 485 * is always hardwired.
486 */ 486 */
487 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 487 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
488 }; 488 };
489 489
490 &mmc2 { 490 &mmc2 {
491 status = "okay"; 491 status = "okay";
492 vmmc-supply = <&mmc2_3v3>; 492 vmmc-supply = <&mmc2_3v3>;
493 bus-width = <8>; 493 bus-width = <8>;
494 }; 494 };
495 495
496 &cpu0 { 496 &cpu0 {
497 cpu0-supply = <&smps123_reg>; 497 cpu0-supply = <&smps123_reg>;
498 }; 498 };
499 499
500 &qspi { 500 &qspi {
501 status = "okay"; 501 status = "okay";
502 pinctrl-names = "default"; 502 pinctrl-names = "default";
503 pinctrl-0 = <&qspi1_pins>; 503 pinctrl-0 = <&qspi1_pins>;
504 504
505 spi-max-frequency = <76800000>; 505 spi-max-frequency = <76800000>;
506 m25p80@0 { 506 m25p80@0 {
507 compatible = "s25fl256s1","spi-flash"; 507 compatible = "s25fl256s1","spi-flash";
508 spi-max-frequency = <64000000>; 508 spi-max-frequency = <76800000>;
509 reg = <0>; 509 reg = <0>;
510 spi-tx-bus-width = <1>; 510 spi-tx-bus-width = <1>;
511 spi-rx-bus-width = <4>; 511 spi-rx-bus-width = <4>;
512 #address-cells = <1>; 512 #address-cells = <1>;
513 #size-cells = <1>; 513 #size-cells = <1>;
514 514
515 /* MTD partition table. 515 /* MTD partition table.
516 * The ROM checks the first four physical blocks 516 * The ROM checks the first four physical blocks
517 * for a valid file to boot and the flash here is 517 * for a valid file to boot and the flash here is
518 * 64KiB block size. 518 * 64KiB block size.
519 */ 519 */
520 partition@0 { 520 partition@0 {
521 label = "QSPI.SPL"; 521 label = "QSPI.SPL";
522 reg = <0x00000000 0x000010000>; 522 reg = <0x00000000 0x000010000>;
523 }; 523 };
524 partition@1 { 524 partition@1 {
525 label = "QSPI.SPL.backup1"; 525 label = "QSPI.SPL.backup1";
526 reg = <0x00010000 0x00010000>; 526 reg = <0x00010000 0x00010000>;
527 }; 527 };
528 partition@2 { 528 partition@2 {
529 label = "QSPI.SPL.backup2"; 529 label = "QSPI.SPL.backup2";
530 reg = <0x00020000 0x00010000>; 530 reg = <0x00020000 0x00010000>;
531 }; 531 };
532 partition@3 { 532 partition@3 {
533 label = "QSPI.SPL.backup3"; 533 label = "QSPI.SPL.backup3";
534 reg = <0x00030000 0x00010000>; 534 reg = <0x00030000 0x00010000>;
535 }; 535 };
536 partition@4 { 536 partition@4 {
537 label = "QSPI.u-boot"; 537 label = "QSPI.u-boot";
538 reg = <0x00040000 0x00100000>; 538 reg = <0x00040000 0x00100000>;
539 }; 539 };
540 partition@5 { 540 partition@5 {
541 label = "QSPI.u-boot-spl-os"; 541 label = "QSPI.u-boot-spl-os";
542 reg = <0x00140000 0x00080000>; 542 reg = <0x00140000 0x00080000>;
543 }; 543 };
544 partition@6 { 544 partition@6 {
545 label = "QSPI.u-boot-env"; 545 label = "QSPI.u-boot-env";
546 reg = <0x001c0000 0x00010000>; 546 reg = <0x001c0000 0x00010000>;
547 }; 547 };
548 partition@7 { 548 partition@7 {
549 label = "QSPI.u-boot-env.backup1"; 549 label = "QSPI.u-boot-env.backup1";
550 reg = <0x001d0000 0x0010000>; 550 reg = <0x001d0000 0x0010000>;
551 }; 551 };
552 partition@8 { 552 partition@8 {
553 label = "QSPI.kernel"; 553 label = "QSPI.kernel";
554 reg = <0x001e0000 0x0800000>; 554 reg = <0x001e0000 0x0800000>;
555 }; 555 };
556 partition@9 { 556 partition@9 {
557 label = "QSPI.file-system"; 557 label = "QSPI.file-system";
558 reg = <0x009e0000 0x01620000>; 558 reg = <0x009e0000 0x01620000>;
559 }; 559 };
560 }; 560 };
561 }; 561 };
562 562
563 &omap_dwc3_1 { 563 &omap_dwc3_1 {
564 extcon = <&extcon_usb1>; 564 extcon = <&extcon_usb1>;
565 }; 565 };
566 566
567 &omap_dwc3_2 { 567 &omap_dwc3_2 {
568 extcon = <&extcon_usb2>; 568 extcon = <&extcon_usb2>;
569 }; 569 };
570 570
571 &usb1 { 571 &usb1 {
572 dr_mode = "peripheral"; 572 dr_mode = "peripheral";
573 pinctrl-names = "default"; 573 pinctrl-names = "default";
574 pinctrl-0 = <&usb1_pins>; 574 pinctrl-0 = <&usb1_pins>;
575 }; 575 };
576 576
577 &usb2 { 577 &usb2 {
578 dr_mode = "host"; 578 dr_mode = "host";
579 pinctrl-names = "default"; 579 pinctrl-names = "default";
580 pinctrl-0 = <&usb2_pins>; 580 pinctrl-0 = <&usb2_pins>;
581 }; 581 };
582 582
583 &elm { 583 &elm {
584 status = "okay"; 584 status = "okay";
585 }; 585 };
586 586
587 &gpmc { 587 &gpmc {
588 status = "okay"; 588 status = "okay";
589 pinctrl-names = "default"; 589 pinctrl-names = "default";
590 pinctrl-0 = <&nand_flash_x16>; 590 pinctrl-0 = <&nand_flash_x16>;
591 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 591 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
592 nand@0,0 { 592 nand@0,0 {
593 reg = <0 0 4>; /* device IO registers */ 593 reg = <0 0 4>; /* device IO registers */
594 ti,nand-ecc-opt = "bch8"; 594 ti,nand-ecc-opt = "bch8";
595 ti,elm-id = <&elm>; 595 ti,elm-id = <&elm>;
596 nand-bus-width = <16>; 596 nand-bus-width = <16>;
597 gpmc,device-width = <2>; 597 gpmc,device-width = <2>;
598 gpmc,sync-clk-ps = <0>; 598 gpmc,sync-clk-ps = <0>;
599 gpmc,cs-on-ns = <0>; 599 gpmc,cs-on-ns = <0>;
600 gpmc,cs-rd-off-ns = <80>; 600 gpmc,cs-rd-off-ns = <80>;
601 gpmc,cs-wr-off-ns = <80>; 601 gpmc,cs-wr-off-ns = <80>;
602 gpmc,adv-on-ns = <0>; 602 gpmc,adv-on-ns = <0>;
603 gpmc,adv-rd-off-ns = <60>; 603 gpmc,adv-rd-off-ns = <60>;
604 gpmc,adv-wr-off-ns = <60>; 604 gpmc,adv-wr-off-ns = <60>;
605 gpmc,we-on-ns = <10>; 605 gpmc,we-on-ns = <10>;
606 gpmc,we-off-ns = <50>; 606 gpmc,we-off-ns = <50>;
607 gpmc,oe-on-ns = <4>; 607 gpmc,oe-on-ns = <4>;
608 gpmc,oe-off-ns = <40>; 608 gpmc,oe-off-ns = <40>;
609 gpmc,access-ns = <40>; 609 gpmc,access-ns = <40>;
610 gpmc,wr-access-ns = <80>; 610 gpmc,wr-access-ns = <80>;
611 gpmc,rd-cycle-ns = <80>; 611 gpmc,rd-cycle-ns = <80>;
612 gpmc,wr-cycle-ns = <80>; 612 gpmc,wr-cycle-ns = <80>;
613 gpmc,bus-turnaround-ns = <0>; 613 gpmc,bus-turnaround-ns = <0>;
614 gpmc,cycle2cycle-delay-ns = <0>; 614 gpmc,cycle2cycle-delay-ns = <0>;
615 gpmc,clk-activation-ns = <0>; 615 gpmc,clk-activation-ns = <0>;
616 gpmc,wait-monitoring-ns = <0>; 616 gpmc,wait-monitoring-ns = <0>;
617 gpmc,wr-data-mux-bus-ns = <0>; 617 gpmc,wr-data-mux-bus-ns = <0>;
618 /* MTD partition table */ 618 /* MTD partition table */
619 /* All SPL-* partitions are sized to minimal length 619 /* All SPL-* partitions are sized to minimal length
620 * which can be independently programmable. For 620 * which can be independently programmable. For
621 * NAND flash this is equal to size of erase-block */ 621 * NAND flash this is equal to size of erase-block */
622 #address-cells = <1>; 622 #address-cells = <1>;
623 #size-cells = <1>; 623 #size-cells = <1>;
624 partition@0 { 624 partition@0 {
625 label = "NAND.SPL"; 625 label = "NAND.SPL";
626 reg = <0x00000000 0x000020000>; 626 reg = <0x00000000 0x000020000>;
627 }; 627 };
628 partition@1 { 628 partition@1 {
629 label = "NAND.SPL.backup1"; 629 label = "NAND.SPL.backup1";
630 reg = <0x00020000 0x00020000>; 630 reg = <0x00020000 0x00020000>;
631 }; 631 };
632 partition@2 { 632 partition@2 {
633 label = "NAND.SPL.backup2"; 633 label = "NAND.SPL.backup2";
634 reg = <0x00040000 0x00020000>; 634 reg = <0x00040000 0x00020000>;
635 }; 635 };
636 partition@3 { 636 partition@3 {
637 label = "NAND.SPL.backup3"; 637 label = "NAND.SPL.backup3";
638 reg = <0x00060000 0x00020000>; 638 reg = <0x00060000 0x00020000>;
639 }; 639 };
640 partition@4 { 640 partition@4 {
641 label = "NAND.u-boot-spl-os"; 641 label = "NAND.u-boot-spl-os";
642 reg = <0x00080000 0x00040000>; 642 reg = <0x00080000 0x00040000>;
643 }; 643 };
644 partition@5 { 644 partition@5 {
645 label = "NAND.u-boot"; 645 label = "NAND.u-boot";
646 reg = <0x000c0000 0x00100000>; 646 reg = <0x000c0000 0x00100000>;
647 }; 647 };
648 partition@6 { 648 partition@6 {
649 label = "NAND.u-boot-env"; 649 label = "NAND.u-boot-env";
650 reg = <0x001c0000 0x00020000>; 650 reg = <0x001c0000 0x00020000>;
651 }; 651 };
652 partition@7 { 652 partition@7 {
653 label = "NAND.u-boot-env.backup1"; 653 label = "NAND.u-boot-env.backup1";
654 reg = <0x001e0000 0x00020000>; 654 reg = <0x001e0000 0x00020000>;
655 }; 655 };
656 partition@8 { 656 partition@8 {
657 label = "NAND.kernel"; 657 label = "NAND.kernel";
658 reg = <0x00200000 0x00800000>; 658 reg = <0x00200000 0x00800000>;
659 }; 659 };
660 partition@9 { 660 partition@9 {
661 label = "NAND.file-system"; 661 label = "NAND.file-system";
662 reg = <0x00a00000 0x0f600000>; 662 reg = <0x00a00000 0x0f600000>;
663 }; 663 };
664 }; 664 };
665 }; 665 };
666 666
667 &usb2_phy1 { 667 &usb2_phy1 {
668 phy-supply = <&ldousb_reg>; 668 phy-supply = <&ldousb_reg>;
669 }; 669 };
670 670
671 &usb2_phy2 { 671 &usb2_phy2 {
672 phy-supply = <&ldousb_reg>; 672 phy-supply = <&ldousb_reg>;
673 }; 673 };
674 674
675 &gpio7 { 675 &gpio7 {
676 ti,no-reset-on-init; 676 ti,no-reset-on-init;
677 ti,no-idle-on-init; 677 ti,no-idle-on-init;
678 }; 678 };
679 679
680 &mac { 680 &mac {
681 status = "okay"; 681 status = "okay";
682 pinctrl-names = "default", "sleep"; 682 pinctrl-names = "default", "sleep";
683 pinctrl-0 = <&cpsw_default>; 683 pinctrl-0 = <&cpsw_default>;
684 pinctrl-1 = <&cpsw_sleep>; 684 pinctrl-1 = <&cpsw_sleep>;
685 dual_emac; 685 dual_emac;
686 }; 686 };
687 687
688 &cpsw_emac0 { 688 &cpsw_emac0 {
689 phy_id = <&davinci_mdio>, <2>; 689 phy_id = <&davinci_mdio>, <2>;
690 phy-mode = "rgmii"; 690 phy-mode = "rgmii";
691 dual_emac_res_vlan = <1>; 691 dual_emac_res_vlan = <1>;
692 }; 692 };
693 693
694 &cpsw_emac1 { 694 &cpsw_emac1 {
695 phy_id = <&davinci_mdio>, <3>; 695 phy_id = <&davinci_mdio>, <3>;
696 phy-mode = "rgmii"; 696 phy-mode = "rgmii";
697 dual_emac_res_vlan = <2>; 697 dual_emac_res_vlan = <2>;
698 }; 698 };
699 699
700 &davinci_mdio { 700 &davinci_mdio {
701 pinctrl-names = "default", "sleep"; 701 pinctrl-names = "default", "sleep";
702 pinctrl-0 = <&davinci_mdio_default>; 702 pinctrl-0 = <&davinci_mdio_default>;
703 pinctrl-1 = <&davinci_mdio_sleep>; 703 pinctrl-1 = <&davinci_mdio_sleep>;
704 }; 704 };
705 705
706 &dcan1 { 706 &dcan1 {
707 status = "ok"; 707 status = "ok";
708 pinctrl-names = "default", "sleep", "active"; 708 pinctrl-names = "default", "sleep", "active";
709 pinctrl-0 = <&dcan1_pins_sleep>; 709 pinctrl-0 = <&dcan1_pins_sleep>;
710 pinctrl-1 = <&dcan1_pins_sleep>; 710 pinctrl-1 = <&dcan1_pins_sleep>;
711 pinctrl-2 = <&dcan1_pins_default>; 711 pinctrl-2 = <&dcan1_pins_default>;
712 }; 712 };
713 713
arch/arm/dts/dra72-evm-common.dtsi
Diff comments   View file @ 84295f2
1 /* 1 /*
2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "dra72x.dtsi" 10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 12
13 / { 13 / {
14 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; 14 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
15 15
16 chosen { 16 chosen {
17 stdout-path = &uart1; 17 stdout-path = &uart1;
18 tick-timer = &timer2; 18 tick-timer = &timer2;
19 }; 19 };
20 20
21 aliases { 21 aliases {
22 display0 = &hdmi0; 22 display0 = &hdmi0;
23 }; 23 };
24 24
25 evm_3v3: fixedregulator-evm_3v3 { 25 evm_3v3: fixedregulator-evm_3v3 {
26 compatible = "regulator-fixed"; 26 compatible = "regulator-fixed";
27 regulator-name = "evm_3v3"; 27 regulator-name = "evm_3v3";
28 regulator-min-microvolt = <3300000>; 28 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <3300000>; 29 regulator-max-microvolt = <3300000>;
30 }; 30 };
31 31
32 extcon_usb1: extcon_usb1 { 32 extcon_usb1: extcon_usb1 {
33 compatible = "linux,extcon-usb-gpio"; 33 compatible = "linux,extcon-usb-gpio";
34 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 34 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
35 }; 35 };
36 36
37 extcon_usb2: extcon_usb2 { 37 extcon_usb2: extcon_usb2 {
38 compatible = "linux,extcon-usb-gpio"; 38 compatible = "linux,extcon-usb-gpio";
39 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 39 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
40 }; 40 };
41 41
42 hdmi0: connector { 42 hdmi0: connector {
43 compatible = "hdmi-connector"; 43 compatible = "hdmi-connector";
44 label = "hdmi"; 44 label = "hdmi";
45 45
46 type = "a"; 46 type = "a";
47 47
48 port { 48 port {
49 hdmi_connector_in: endpoint { 49 hdmi_connector_in: endpoint {
50 remote-endpoint = <&tpd12s015_out>; 50 remote-endpoint = <&tpd12s015_out>;
51 }; 51 };
52 }; 52 };
53 }; 53 };
54 54
55 tpd12s015: encoder { 55 tpd12s015: encoder {
56 compatible = "ti,tpd12s015"; 56 compatible = "ti,tpd12s015";
57 57
58 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ 58 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
59 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ 59 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
60 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ 60 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
61 61
62 ports { 62 ports {
63 #address-cells = <1>; 63 #address-cells = <1>;
64 #size-cells = <0>; 64 #size-cells = <0>;
65 65
66 port@0 { 66 port@0 {
67 reg = <0>; 67 reg = <0>;
68 68
69 tpd12s015_in: endpoint { 69 tpd12s015_in: endpoint {
70 remote-endpoint = <&hdmi_out>; 70 remote-endpoint = <&hdmi_out>;
71 }; 71 };
72 }; 72 };
73 73
74 port@1 { 74 port@1 {
75 reg = <1>; 75 reg = <1>;
76 76
77 tpd12s015_out: endpoint { 77 tpd12s015_out: endpoint {
78 remote-endpoint = <&hdmi_connector_in>; 78 remote-endpoint = <&hdmi_connector_in>;
79 }; 79 };
80 }; 80 };
81 }; 81 };
82 }; 82 };
83 }; 83 };
84 84
85 &dra7_pmx_core { 85 &dra7_pmx_core {
86 mmc1_pins_default: mmc1_pins_default { 86 mmc1_pins_default: mmc1_pins_default {
87 pinctrl-single,pins = < 87 pinctrl-single,pins = <
88 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 88 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
89 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 89 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
90 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 90 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
91 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 91 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
92 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 92 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
93 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 93 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
94 >; 94 >;
95 }; 95 };
96 96
97 mmc2_pins_default: mmc2_pins_default { 97 mmc2_pins_default: mmc2_pins_default {
98 pinctrl-single,pins = < 98 pinctrl-single,pins = <
99 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 99 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
100 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 100 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
101 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 101 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
102 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 102 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
103 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 103 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
104 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 104 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
105 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 105 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
106 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 106 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
107 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 107 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
108 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 108 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
109 >; 109 >;
110 }; 110 };
111 111
112 dcan1_pins_default: dcan1_pins_default { 112 dcan1_pins_default: dcan1_pins_default {
113 pinctrl-single,pins = < 113 pinctrl-single,pins = <
114 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 114 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
115 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 115 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
116 >; 116 >;
117 }; 117 };
118 118
119 dcan1_pins_sleep: dcan1_pins_sleep { 119 dcan1_pins_sleep: dcan1_pins_sleep {
120 pinctrl-single,pins = < 120 pinctrl-single,pins = <
121 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 121 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
122 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ 122 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
123 >; 123 >;
124 }; 124 };
125 }; 125 };
126 126
127 &i2c1 { 127 &i2c1 {
128 status = "okay"; 128 status = "okay";
129 clock-frequency = <400000>; 129 clock-frequency = <400000>;
130 130
131 tps65917: tps65917@58 { 131 tps65917: tps65917@58 {
132 compatible = "ti,tps65917"; 132 compatible = "ti,tps65917";
133 reg = <0x58>; 133 reg = <0x58>;
134 134
135 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ 135 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
136 interrupt-controller; 136 interrupt-controller;
137 #interrupt-cells = <2>; 137 #interrupt-cells = <2>;
138 138
139 ti,system-power-controller; 139 ti,system-power-controller;
140 140
141 tps65917_pmic { 141 tps65917_pmic {
142 compatible = "ti,tps65917-pmic"; 142 compatible = "ti,tps65917-pmic";
143 143
144 tps65917_regulators: regulators { 144 tps65917_regulators: regulators {
145 smps1_reg: smps1 { 145 smps1_reg: smps1 {
146 /* VDD_MPU */ 146 /* VDD_MPU */
147 regulator-name = "smps1"; 147 regulator-name = "smps1";
148 regulator-min-microvolt = <850000>; 148 regulator-min-microvolt = <850000>;
149 regulator-max-microvolt = <1250000>; 149 regulator-max-microvolt = <1250000>;
150 regulator-always-on; 150 regulator-always-on;
151 regulator-boot-on; 151 regulator-boot-on;
152 }; 152 };
153 153
154 smps2_reg: smps2 { 154 smps2_reg: smps2 {
155 /* VDD_CORE */ 155 /* VDD_CORE */
156 regulator-name = "smps2"; 156 regulator-name = "smps2";
157 regulator-min-microvolt = <850000>; 157 regulator-min-microvolt = <850000>;
158 regulator-max-microvolt = <1060000>; 158 regulator-max-microvolt = <1060000>;
159 regulator-boot-on; 159 regulator-boot-on;
160 regulator-always-on; 160 regulator-always-on;
161 }; 161 };
162 162
163 smps3_reg: smps3 { 163 smps3_reg: smps3 {
164 /* VDD_GPU IVA DSPEVE */ 164 /* VDD_GPU IVA DSPEVE */
165 regulator-name = "smps3"; 165 regulator-name = "smps3";
166 regulator-min-microvolt = <850000>; 166 regulator-min-microvolt = <850000>;
167 regulator-max-microvolt = <1250000>; 167 regulator-max-microvolt = <1250000>;
168 regulator-boot-on; 168 regulator-boot-on;
169 regulator-always-on; 169 regulator-always-on;
170 }; 170 };
171 171
172 smps4_reg: smps4 { 172 smps4_reg: smps4 {
173 /* VDDS1V8 */ 173 /* VDDS1V8 */
174 regulator-name = "smps4"; 174 regulator-name = "smps4";
175 regulator-min-microvolt = <1800000>; 175 regulator-min-microvolt = <1800000>;
176 regulator-max-microvolt = <1800000>; 176 regulator-max-microvolt = <1800000>;
177 regulator-always-on; 177 regulator-always-on;
178 regulator-boot-on; 178 regulator-boot-on;
179 }; 179 };
180 180
181 smps5_reg: smps5 { 181 smps5_reg: smps5 {
182 /* VDD_DDR */ 182 /* VDD_DDR */
183 regulator-name = "smps5"; 183 regulator-name = "smps5";
184 regulator-min-microvolt = <1350000>; 184 regulator-min-microvolt = <1350000>;
185 regulator-max-microvolt = <1350000>; 185 regulator-max-microvolt = <1350000>;
186 regulator-boot-on; 186 regulator-boot-on;
187 regulator-always-on; 187 regulator-always-on;
188 }; 188 };
189 189
190 ldo1_reg: ldo1 { 190 ldo1_reg: ldo1 {
191 /* LDO1_OUT --> SDIO */ 191 /* LDO1_OUT --> SDIO */
192 regulator-name = "ldo1"; 192 regulator-name = "ldo1";
193 regulator-min-microvolt = <1800000>; 193 regulator-min-microvolt = <1800000>;
194 regulator-max-microvolt = <3300000>; 194 regulator-max-microvolt = <3300000>;
195 regulator-always-on; 195 regulator-always-on;
196 regulator-boot-on; 196 regulator-boot-on;
197 regulator-allow-bypass; 197 regulator-allow-bypass;
198 }; 198 };
199 199
200 ldo3_reg: ldo3 { 200 ldo3_reg: ldo3 {
201 /* VDDA_1V8_PHY */ 201 /* VDDA_1V8_PHY */
202 regulator-name = "ldo3"; 202 regulator-name = "ldo3";
203 regulator-min-microvolt = <1800000>; 203 regulator-min-microvolt = <1800000>;
204 regulator-max-microvolt = <1800000>; 204 regulator-max-microvolt = <1800000>;
205 regulator-boot-on; 205 regulator-boot-on;
206 regulator-always-on; 206 regulator-always-on;
207 }; 207 };
208 208
209 ldo5_reg: ldo5 { 209 ldo5_reg: ldo5 {
210 /* VDDA_1V8_PLL */ 210 /* VDDA_1V8_PLL */
211 regulator-name = "ldo5"; 211 regulator-name = "ldo5";
212 regulator-min-microvolt = <1800000>; 212 regulator-min-microvolt = <1800000>;
213 regulator-max-microvolt = <1800000>; 213 regulator-max-microvolt = <1800000>;
214 regulator-always-on; 214 regulator-always-on;
215 regulator-boot-on; 215 regulator-boot-on;
216 }; 216 };
217 217
218 ldo4_reg: ldo4 { 218 ldo4_reg: ldo4 {
219 /* VDDA_3V_USB: VDDA_USBHS33 */ 219 /* VDDA_3V_USB: VDDA_USBHS33 */
220 regulator-name = "ldo4"; 220 regulator-name = "ldo4";
221 regulator-min-microvolt = <3300000>; 221 regulator-min-microvolt = <3300000>;
222 regulator-max-microvolt = <3300000>; 222 regulator-max-microvolt = <3300000>;
223 regulator-boot-on; 223 regulator-boot-on;
224 }; 224 };
225 }; 225 };
226 }; 226 };
227 227
228 tps65917_power_button { 228 tps65917_power_button {
229 compatible = "ti,palmas-pwrbutton"; 229 compatible = "ti,palmas-pwrbutton";
230 interrupt-parent = <&tps65917>; 230 interrupt-parent = <&tps65917>;
231 interrupts = <1 IRQ_TYPE_NONE>; 231 interrupts = <1 IRQ_TYPE_NONE>;
232 wakeup-source; 232 wakeup-source;
233 ti,palmas-long-press-seconds = <6>; 233 ti,palmas-long-press-seconds = <6>;
234 }; 234 };
235 }; 235 };
236 236
237 pcf_gpio_21: gpio@21 { 237 pcf_gpio_21: gpio@21 {
238 compatible = "ti,pcf8575"; 238 compatible = "ti,pcf8575";
239 u-boot,i2c-offset-len = <0>; 239 u-boot,i2c-offset-len = <0>;
240 reg = <0x21>; 240 reg = <0x21>;
241 lines-initial-states = <0x1408>; 241 lines-initial-states = <0x1408>;
242 gpio-controller; 242 gpio-controller;
243 #gpio-cells = <2>; 243 #gpio-cells = <2>;
244 244
245 interrupt-controller; 245 interrupt-controller;
246 #interrupt-cells = <2>; 246 #interrupt-cells = <2>;
247 }; 247 };
248 }; 248 };
249 249
250 &i2c5 { 250 &i2c5 {
251 status = "okay"; 251 status = "okay";
252 clock-frequency = <400000>; 252 clock-frequency = <400000>;
253 253
254 pcf_hdmi: pcf8575@26 { 254 pcf_hdmi: pcf8575@26 {
255 compatible = "nxp,pcf8575"; 255 compatible = "nxp,pcf8575";
256 u-boot,i2c-offset-len = <0>; 256 u-boot,i2c-offset-len = <0>;
257 reg = <0x26>; 257 reg = <0x26>;
258 gpio-controller; 258 gpio-controller;
259 #gpio-cells = <2>; 259 #gpio-cells = <2>;
260 /* 260 /*
261 * initial state is used here to keep the mdio interface 261 * initial state is used here to keep the mdio interface
262 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and 262 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
263 * VIN2_S0 driven high otherwise Ethernet stops working 263 * VIN2_S0 driven high otherwise Ethernet stops working
264 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 264 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
265 */ 265 */
266 lines-initial-states = <0x0f2b>; 266 lines-initial-states = <0x0f2b>;
267 267
268 p1 { 268 p1 {
269 /* vin6_sel_s0: high: VIN6, low: audio */ 269 /* vin6_sel_s0: high: VIN6, low: audio */
270 gpio-hog; 270 gpio-hog;
271 gpios = <1 GPIO_ACTIVE_HIGH>; 271 gpios = <1 GPIO_ACTIVE_HIGH>;
272 output-low; 272 output-low;
273 line-name = "vin6_sel_s0"; 273 line-name = "vin6_sel_s0";
274 }; 274 };
275 }; 275 };
276 }; 276 };
277 277
278 &uart1 { 278 &uart1 {
279 status = "okay"; 279 status = "okay";
280 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 280 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
281 <&dra7_pmx_core 0x3e0>; 281 <&dra7_pmx_core 0x3e0>;
282 }; 282 };
283 283
284 &elm { 284 &elm {
285 status = "okay"; 285 status = "okay";
286 }; 286 };
287 287
288 &gpmc { 288 &gpmc {
289 /* 289 /*
290 * For the existing IOdelay configuration via U-Boot we don't 290 * For the existing IOdelay configuration via U-Boot we don't
291 * support NAND on dra72-evm. Keep it disabled. Enabling it 291 * support NAND on dra72-evm. Keep it disabled. Enabling it
292 * requires a different configuration by U-Boot. 292 * requires a different configuration by U-Boot.
293 */ 293 */
294 status = "disabled"; 294 status = "disabled";
295 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 295 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
296 nand@0,0 { 296 nand@0,0 {
297 /* To use NAND, DIP switch SW5 must be set like so: 297 /* To use NAND, DIP switch SW5 must be set like so:
298 * SW5.1 (NAND_SELn) = ON (LOW) 298 * SW5.1 (NAND_SELn) = ON (LOW)
299 * SW5.9 (GPMC_WPN) = OFF (HIGH) 299 * SW5.9 (GPMC_WPN) = OFF (HIGH)
300 */ 300 */
301 compatible = "ti,omap2-nand"; 301 compatible = "ti,omap2-nand";
302 reg = <0 0 4>; /* device IO registers */ 302 reg = <0 0 4>; /* device IO registers */
303 interrupt-parent = <&gpmc>; 303 interrupt-parent = <&gpmc>;
304 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 304 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
305 <1 IRQ_TYPE_NONE>; /* termcount */ 305 <1 IRQ_TYPE_NONE>; /* termcount */
306 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */ 306 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */
307 ti,nand-ecc-opt = "bch8"; 307 ti,nand-ecc-opt = "bch8";
308 ti,elm-id = <&elm>; 308 ti,elm-id = <&elm>;
309 nand-bus-width = <16>; 309 nand-bus-width = <16>;
310 gpmc,device-width = <2>; 310 gpmc,device-width = <2>;
311 gpmc,sync-clk-ps = <0>; 311 gpmc,sync-clk-ps = <0>;
312 gpmc,cs-on-ns = <0>; 312 gpmc,cs-on-ns = <0>;
313 gpmc,cs-rd-off-ns = <80>; 313 gpmc,cs-rd-off-ns = <80>;
314 gpmc,cs-wr-off-ns = <80>; 314 gpmc,cs-wr-off-ns = <80>;
315 gpmc,adv-on-ns = <0>; 315 gpmc,adv-on-ns = <0>;
316 gpmc,adv-rd-off-ns = <60>; 316 gpmc,adv-rd-off-ns = <60>;
317 gpmc,adv-wr-off-ns = <60>; 317 gpmc,adv-wr-off-ns = <60>;
318 gpmc,we-on-ns = <10>; 318 gpmc,we-on-ns = <10>;
319 gpmc,we-off-ns = <50>; 319 gpmc,we-off-ns = <50>;
320 gpmc,oe-on-ns = <4>; 320 gpmc,oe-on-ns = <4>;
321 gpmc,oe-off-ns = <40>; 321 gpmc,oe-off-ns = <40>;
322 gpmc,access-ns = <40>; 322 gpmc,access-ns = <40>;
323 gpmc,wr-access-ns = <80>; 323 gpmc,wr-access-ns = <80>;
324 gpmc,rd-cycle-ns = <80>; 324 gpmc,rd-cycle-ns = <80>;
325 gpmc,wr-cycle-ns = <80>; 325 gpmc,wr-cycle-ns = <80>;
326 gpmc,bus-turnaround-ns = <0>; 326 gpmc,bus-turnaround-ns = <0>;
327 gpmc,cycle2cycle-delay-ns = <0>; 327 gpmc,cycle2cycle-delay-ns = <0>;
328 gpmc,clk-activation-ns = <0>; 328 gpmc,clk-activation-ns = <0>;
329 gpmc,wait-monitoring-ns = <0>; 329 gpmc,wait-monitoring-ns = <0>;
330 gpmc,wr-data-mux-bus-ns = <0>; 330 gpmc,wr-data-mux-bus-ns = <0>;
331 /* MTD partition table */ 331 /* MTD partition table */
332 /* All SPL-* partitions are sized to minimal length 332 /* All SPL-* partitions are sized to minimal length
333 * which can be independently programmable. For 333 * which can be independently programmable. For
334 * NAND flash this is equal to size of erase-block */ 334 * NAND flash this is equal to size of erase-block */
335 #address-cells = <1>; 335 #address-cells = <1>;
336 #size-cells = <1>; 336 #size-cells = <1>;
337 partition@0 { 337 partition@0 {
338 label = "NAND.SPL"; 338 label = "NAND.SPL";
339 reg = <0x00000000 0x000020000>; 339 reg = <0x00000000 0x000020000>;
340 }; 340 };
341 partition@1 { 341 partition@1 {
342 label = "NAND.SPL.backup1"; 342 label = "NAND.SPL.backup1";
343 reg = <0x00020000 0x00020000>; 343 reg = <0x00020000 0x00020000>;
344 }; 344 };
345 partition@2 { 345 partition@2 {
346 label = "NAND.SPL.backup2"; 346 label = "NAND.SPL.backup2";
347 reg = <0x00040000 0x00020000>; 347 reg = <0x00040000 0x00020000>;
348 }; 348 };
349 partition@3 { 349 partition@3 {
350 label = "NAND.SPL.backup3"; 350 label = "NAND.SPL.backup3";
351 reg = <0x00060000 0x00020000>; 351 reg = <0x00060000 0x00020000>;
352 }; 352 };
353 partition@4 { 353 partition@4 {
354 label = "NAND.u-boot-spl-os"; 354 label = "NAND.u-boot-spl-os";
355 reg = <0x00080000 0x00040000>; 355 reg = <0x00080000 0x00040000>;
356 }; 356 };
357 partition@5 { 357 partition@5 {
358 label = "NAND.u-boot"; 358 label = "NAND.u-boot";
359 reg = <0x000c0000 0x00100000>; 359 reg = <0x000c0000 0x00100000>;
360 }; 360 };
361 partition@6 { 361 partition@6 {
362 label = "NAND.u-boot-env"; 362 label = "NAND.u-boot-env";
363 reg = <0x001c0000 0x00020000>; 363 reg = <0x001c0000 0x00020000>;
364 }; 364 };
365 partition@7 { 365 partition@7 {
366 label = "NAND.u-boot-env.backup1"; 366 label = "NAND.u-boot-env.backup1";
367 reg = <0x001e0000 0x00020000>; 367 reg = <0x001e0000 0x00020000>;
368 }; 368 };
369 partition@8 { 369 partition@8 {
370 label = "NAND.kernel"; 370 label = "NAND.kernel";
371 reg = <0x00200000 0x00800000>; 371 reg = <0x00200000 0x00800000>;
372 }; 372 };
373 partition@9 { 373 partition@9 {
374 label = "NAND.file-system"; 374 label = "NAND.file-system";
375 reg = <0x00a00000 0x0f600000>; 375 reg = <0x00a00000 0x0f600000>;
376 }; 376 };
377 }; 377 };
378 }; 378 };
379 379
380 &usb2_phy1 { 380 &usb2_phy1 {
381 phy-supply = <&ldo4_reg>; 381 phy-supply = <&ldo4_reg>;
382 }; 382 };
383 383
384 &usb2_phy2 { 384 &usb2_phy2 {
385 phy-supply = <&ldo4_reg>; 385 phy-supply = <&ldo4_reg>;
386 }; 386 };
387 387
388 &omap_dwc3_1 { 388 &omap_dwc3_1 {
389 extcon = <&extcon_usb1>; 389 extcon = <&extcon_usb1>;
390 }; 390 };
391 391
392 &omap_dwc3_2 { 392 &omap_dwc3_2 {
393 extcon = <&extcon_usb2>; 393 extcon = <&extcon_usb2>;
394 }; 394 };
395 395
396 &usb1 { 396 &usb1 {
397 dr_mode = "otg"; 397 dr_mode = "otg";
398 }; 398 };
399 399
400 &usb2 { 400 &usb2 {
401 dr_mode = "host"; 401 dr_mode = "host";
402 }; 402 };
403 403
404 &mmc1 { 404 &mmc1 {
405 status = "okay"; 405 status = "okay";
406 pinctrl-names = "default"; 406 pinctrl-names = "default";
407 pinctrl-0 = <&mmc1_pins_default>; 407 pinctrl-0 = <&mmc1_pins_default>;
408 vmmc_aux-supply = <&ldo1_reg>; 408 vmmc_aux-supply = <&ldo1_reg>;
409 bus-width = <4>; 409 bus-width = <4>;
410 /* 410 /*
411 * SDCD signal is not being used here - using the fact that GPIO mode 411 * SDCD signal is not being used here - using the fact that GPIO mode
412 * is a viable alternative 412 * is a viable alternative
413 */ 413 */
414 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 414 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
415 max-frequency = <192000000>; 415 max-frequency = <192000000>;
416 }; 416 };
417 417
418 &mmc2 { 418 &mmc2 {
419 /* SW5-3 in ON position */ 419 /* SW5-3 in ON position */
420 status = "okay"; 420 status = "okay";
421 pinctrl-names = "default"; 421 pinctrl-names = "default";
422 pinctrl-0 = <&mmc2_pins_default>; 422 pinctrl-0 = <&mmc2_pins_default>;
423 423
424 vmmc-supply = <&evm_3v3>; 424 vmmc-supply = <&evm_3v3>;
425 bus-width = <8>; 425 bus-width = <8>;
426 ti,non-removable; 426 ti,non-removable;
427 max-frequency = <192000000>; 427 max-frequency = <192000000>;
428 }; 428 };
429 429
430 &mac { 430 &mac {
431 status = "okay"; 431 status = "okay";
432 }; 432 };
433 433
434 &dcan1 { 434 &dcan1 {
435 status = "ok"; 435 status = "ok";
436 }; 436 };
437 437
438 &qspi { 438 &qspi {
439 status = "okay"; 439 status = "okay";
440 440
441 spi-max-frequency = <76800000>; 441 spi-max-frequency = <76800000>;
442 m25p80@0 { 442 m25p80@0 {
443 compatible = "s25fl256s1", "spi-flash"; 443 compatible = "s25fl256s1", "spi-flash";
444 spi-max-frequency = <64000000>; 444 spi-max-frequency = <76800000>;
445 reg = <0>; 445 reg = <0>;
446 spi-tx-bus-width = <1>; 446 spi-tx-bus-width = <1>;
447 spi-rx-bus-width = <4>; 447 spi-rx-bus-width = <4>;
448 #address-cells = <1>; 448 #address-cells = <1>;
449 #size-cells = <1>; 449 #size-cells = <1>;
450 450
451 /* MTD partition table. 451 /* MTD partition table.
452 * The ROM checks the first four physical blocks 452 * The ROM checks the first four physical blocks
453 * for a valid file to boot and the flash here is 453 * for a valid file to boot and the flash here is
454 * 64KiB block size. 454 * 64KiB block size.
455 */ 455 */
456 partition@0 { 456 partition@0 {
457 label = "QSPI.SPL"; 457 label = "QSPI.SPL";
458 reg = <0x00000000 0x000010000>; 458 reg = <0x00000000 0x000010000>;
459 }; 459 };
460 partition@1 { 460 partition@1 {
461 label = "QSPI.SPL.backup1"; 461 label = "QSPI.SPL.backup1";
462 reg = <0x00010000 0x00010000>; 462 reg = <0x00010000 0x00010000>;
463 }; 463 };
464 partition@2 { 464 partition@2 {
465 label = "QSPI.SPL.backup2"; 465 label = "QSPI.SPL.backup2";
466 reg = <0x00020000 0x00010000>; 466 reg = <0x00020000 0x00010000>;
467 }; 467 };
468 partition@3 { 468 partition@3 {
469 label = "QSPI.SPL.backup3"; 469 label = "QSPI.SPL.backup3";
470 reg = <0x00030000 0x00010000>; 470 reg = <0x00030000 0x00010000>;
471 }; 471 };
472 partition@4 { 472 partition@4 {
473 label = "QSPI.u-boot"; 473 label = "QSPI.u-boot";
474 reg = <0x00040000 0x00100000>; 474 reg = <0x00040000 0x00100000>;
475 }; 475 };
476 partition@5 { 476 partition@5 {
477 label = "QSPI.u-boot-spl-os"; 477 label = "QSPI.u-boot-spl-os";
478 reg = <0x00140000 0x00080000>; 478 reg = <0x00140000 0x00080000>;
479 }; 479 };
480 partition@6 { 480 partition@6 {
481 label = "QSPI.u-boot-env"; 481 label = "QSPI.u-boot-env";
482 reg = <0x001c0000 0x00010000>; 482 reg = <0x001c0000 0x00010000>;
483 }; 483 };
484 partition@7 { 484 partition@7 {
485 label = "QSPI.u-boot-env.backup1"; 485 label = "QSPI.u-boot-env.backup1";
486 reg = <0x001d0000 0x0010000>; 486 reg = <0x001d0000 0x0010000>;
487 }; 487 };
488 partition@8 { 488 partition@8 {
489 label = "QSPI.kernel"; 489 label = "QSPI.kernel";
490 reg = <0x001e0000 0x0800000>; 490 reg = <0x001e0000 0x0800000>;
491 }; 491 };
492 partition@9 { 492 partition@9 {
493 label = "QSPI.file-system"; 493 label = "QSPI.file-system";
494 reg = <0x009e0000 0x01620000>; 494 reg = <0x009e0000 0x01620000>;
495 }; 495 };
496 }; 496 };
497 }; 497 };
498 498
499 &dss { 499 &dss {
500 status = "ok"; 500 status = "ok";
501 501
502 vdda_video-supply = <&ldo5_reg>; 502 vdda_video-supply = <&ldo5_reg>;
503 }; 503 };
504 504
505 &hdmi { 505 &hdmi {
506 status = "ok"; 506 status = "ok";
507 507
508 port { 508 port {
509 hdmi_out: endpoint { 509 hdmi_out: endpoint {
510 remote-endpoint = <&tpd12s015_in>; 510 remote-endpoint = <&tpd12s015_in>;
511 }; 511 };
512 }; 512 };
513 }; 513 };
514 514