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Commit 8701eceffdf77e2908d0b58add0dabc16edf6087

Authored by Scott Wood
Committed by Wolfgang Denk
1 parent 83863df04b
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

PQ2FADS: Enable PCI. 

PCI on PQ2FADS is very similar to PCI on MPC8272ADS.

Signed-off-by: Scott Wood <scottwood@freescale.com>

Showing 2 changed files with 15 additions and 4 deletions Inline Diff

1 /* 1 /*
2 * (C) Copyright 2003 2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * Copyright (c) 2005 MontaVista Software, Inc. 5 * Copyright (c) 2005 MontaVista Software, Inc.
6 * Vitaly Bordug <vbordug@ru.mvista.com> 6 * Vitaly Bordug <vbordug@ru.mvista.com>
7 * Added support for PCI bridge on MPC8272ADS 7 * Added support for PCI bridge on MPC8272ADS
8 * 8 *
9 * See file CREDITS for list of people who contributed to this 9 * See file CREDITS for list of people who contributed to this
10 * project. 10 * project.
11 * 11 *
12 * This program is free software; you can redistribute it and/or 12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as 13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of 14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version. 15 * the License, or (at your option) any later version.
16 * 16 *
17 * This program is distributed in the hope that it will be useful, 17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details. 20 * GNU General Public License for more details.
21 * 21 *
22 * You should have received a copy of the GNU General Public License 22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software 23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA 25 * MA 02111-1307 USA
26 */ 26 */
27 27
28 #include <common.h> 28 #include <common.h>
29 29
30 #ifdef CONFIG_PCI 30 #ifdef CONFIG_PCI
31 31
32 #include <pci.h> 32 #include <pci.h>
33 #include <mpc8260.h> 33 #include <mpc8260.h>
34 #include <asm/m8260_pci.h> 34 #include <asm/m8260_pci.h>
35 #include <asm/io.h> 35 #include <asm/io.h>
36 #ifdef CONFIG_OF_LIBFDT 36 #ifdef CONFIG_OF_LIBFDT
37 #include <libfdt.h> 37 #include <libfdt.h>
38 #include <fdt_support.h> 38 #include <fdt_support.h>
39 #endif 39 #endif
40 40
41 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 41 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
42 DECLARE_GLOBAL_DATA_PTR; 42 DECLARE_GLOBAL_DATA_PTR;
43 #endif 43 #endif
44 44
45 /* 45 /*
46 * Local->PCI map (from CPU) controlled by 46 * Local->PCI map (from CPU) controlled by
47 * MPC826x master window 47 * MPC826x master window
48 * 48 *
49 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0 49 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
50 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1 50 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
51 * 51 *
52 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1) 52 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
53 * PCI Mem with prefetch 53 * PCI Mem with prefetch
54 * 54 *
55 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2) 55 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
56 * PCI Mem w/o prefetch 56 * PCI Mem w/o prefetch
57 * 57 *
58 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3) 58 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
59 * 32-bit PCI IO 59 * 32-bit PCI IO
60 * 60 *
61 * PCI->Local map (from PCI) 61 * PCI->Local map (from PCI)
62 * MPC826x slave window controlled by 62 * MPC826x slave window controlled by
63 * 63 *
64 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1) 64 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
65 * MPC826x local memory 65 * MPC826x local memory
66 */ 66 */
67 67
68 /* 68 /*
69 * Slave window that allows PCI masters to access MPC826x local memory. 69 * Slave window that allows PCI masters to access MPC826x local memory.
70 * This window is set up using the first set of Inbound ATU registers 70 * This window is set up using the first set of Inbound ATU registers
71 */ 71 */
72 72
73 #ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL 73 #ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
74 #define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ 74 #define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
75 #else 75 #else
76 #define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL 76 #define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
77 #endif 77 #endif
78 78
79 #ifndef CONFIG_SYS_PCI_SLV_MEM_BUS 79 #ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
80 #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ 80 #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
81 #else 81 #else
82 #define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS 82 #define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
83 #endif 83 #endif
84 84
85 #ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB 85 #ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
86 #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ 86 #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
87 PICMR_PREFETCH_EN) 87 PICMR_PREFETCH_EN)
88 #else 88 #else
89 #define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB 89 #define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
90 #endif 90 #endif
91 91
92 /* 92 /*
93 * These are the windows that allow the CPU to access PCI address space. 93 * These are the windows that allow the CPU to access PCI address space.
94 * All three PCI master windows, which allow the CPU to access PCI 94 * All three PCI master windows, which allow the CPU to access PCI
95 * prefetch, non prefetch, and IO space (see below), must all fit within 95 * prefetch, non prefetch, and IO space (see below), must all fit within
96 * these windows. 96 * these windows.
97 */ 97 */
98 98
99 /* PCIBR0 */ 99 /* PCIBR0 */
100 #ifndef CONFIG_SYS_PCI_MSTR0_LOCAL 100 #ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
101 #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ 101 #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
102 #else 102 #else
103 #define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL 103 #define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
104 #endif 104 #endif
105 105
106 #ifndef CONFIG_SYS_PCIMSK0_MASK 106 #ifndef CONFIG_SYS_PCIMSK0_MASK
107 #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ 107 #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
108 #else 108 #else
109 #define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK 109 #define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK
110 #endif 110 #endif
111 111
112 /* PCIBR1 */ 112 /* PCIBR1 */
113 #ifndef CONFIG_SYS_PCI_MSTR1_LOCAL 113 #ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
114 #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ 114 #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
115 #else 115 #else
116 #define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL 116 #define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL
117 #endif 117 #endif
118 118
119 #ifndef CONFIG_SYS_PCIMSK1_MASK 119 #ifndef CONFIG_SYS_PCIMSK1_MASK
120 #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ 120 #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
121 #else 121 #else
122 #define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK 122 #define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK
123 #endif 123 #endif
124 124
125 /* 125 /*
126 * Master window that allows the CPU to access PCI Memory (prefetch). 126 * Master window that allows the CPU to access PCI Memory (prefetch).
127 * This window will be setup with the first set of Outbound ATU registers 127 * This window will be setup with the first set of Outbound ATU registers
128 * in the bridge. 128 * in the bridge.
129 */ 129 */
130 130
131 #ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL 131 #ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
132 #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ 132 #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
133 #else 133 #else
134 #define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL 134 #define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
135 #endif 135 #endif
136 136
137 #ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS 137 #ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
138 #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ 138 #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
139 #else 139 #else
140 #define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS 140 #define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
141 #endif 141 #endif
142 142
143 #ifndef CONFIG_SYS_CPU_PCI_MEM_START 143 #ifndef CONFIG_SYS_CPU_PCI_MEM_START
144 #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL 144 #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
145 #else 145 #else
146 #define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START 146 #define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
147 #endif 147 #endif
148 148
149 #ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE 149 #ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
150 #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ 150 #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
151 #else 151 #else
152 #define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE 152 #define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
153 #endif 153 #endif
154 154
155 #ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB 155 #ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
156 #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) 156 #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
157 #else 157 #else
158 #define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB 158 #define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
159 #endif 159 #endif
160 160
161 /* 161 /*
162 * Master window that allows the CPU to access PCI Memory (non-prefetch). 162 * Master window that allows the CPU to access PCI Memory (non-prefetch).
163 * This window will be setup with the second set of Outbound ATU registers 163 * This window will be setup with the second set of Outbound ATU registers
164 * in the bridge. 164 * in the bridge.
165 */ 165 */
166 166
167 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 167 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
168 #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ 168 #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
169 #else 169 #else
170 #define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 170 #define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
171 #endif 171 #endif
172 172
173 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS 173 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
174 #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ 174 #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
175 #else 175 #else
176 #define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS 176 #define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
177 #endif 177 #endif
178 178
179 #ifndef CONFIG_SYS_CPU_PCI_MEMIO_START 179 #ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
180 #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL 180 #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
181 #else 181 #else
182 #define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START 182 #define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
183 #endif 183 #endif
184 184
185 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 185 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
186 #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ 186 #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
187 #else 187 #else
188 #define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 188 #define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
189 #endif 189 #endif
190 190
191 #ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB 191 #ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
192 #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) 192 #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
193 #else 193 #else
194 #define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB 194 #define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
195 #endif 195 #endif
196 196
197 /* 197 /*
198 * Master window that allows the CPU to access PCI IO space. 198 * Master window that allows the CPU to access PCI IO space.
199 * This window will be setup with the third set of Outbound ATU registers 199 * This window will be setup with the third set of Outbound ATU registers
200 * in the bridge. 200 * in the bridge.
201 */ 201 */
202 202
203 #ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL 203 #ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
204 #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ 204 #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
205 #else 205 #else
206 #define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL 206 #define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
207 #endif 207 #endif
208 208
209 #ifndef CONFIG_SYS_PCI_MSTR_IO_BUS 209 #ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
210 #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ 210 #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
211 #else 211 #else
212 #define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS 212 #define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
213 #endif 213 #endif
214 214
215 #ifndef CONFIG_SYS_CPU_PCI_IO_START 215 #ifndef CONFIG_SYS_CPU_PCI_IO_START
216 #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL 216 #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
217 #else 217 #else
218 #define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START 218 #define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
219 #endif 219 #endif
220 220
221 #ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE 221 #ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
222 #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ 222 #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
223 #else 223 #else
224 #define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE 224 #define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
225 #endif 225 #endif
226 226
227 #ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB 227 #ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
228 #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) 228 #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
229 #else 229 #else
230 #define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB 230 #define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
231 #endif 231 #endif
232 232
233 /* PCI bus configuration registers. 233 /* PCI bus configuration registers.
234 */ 234 */
235 235
236 #define PCI_CLASS_BRIDGE_CTLR 0x06 236 #define PCI_CLASS_BRIDGE_CTLR 0x06
237 237
238 238
239 static inline void pci_outl (u32 addr, u32 data) 239 static inline void pci_outl (u32 addr, u32 data)
240 { 240 {
241 *(volatile u32 *) addr = cpu_to_le32 (data); 241 *(volatile u32 *) addr = cpu_to_le32 (data);
242 } 242 }
243 243
244 void pci_mpc8250_init (struct pci_controller *hose) 244 void pci_mpc8250_init (struct pci_controller *hose)
245 { 245 {
246 u16 tempShort; 246 u16 tempShort;
247 247
248 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 248 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
249 pci_dev_t host_devno = PCI_BDF (0, 0, 0); 249 pci_dev_t host_devno = PCI_BDF (0, 0, 0);
250 250
251 pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG, 251 pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
252 CONFIG_SYS_IMMR + PCI_CFG_DATA_REG); 252 CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);
253 253
254 /* 254 /*
255 * Setting required to enable local bus for PCI (SIUMCR [LBPC]). 255 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
256 */ 256 */
257 #ifdef CONFIG_MPC8266ADS 257 #ifdef CONFIG_MPC8266ADS
258 immap->im_siu_conf.sc_siumcr = 258 immap->im_siu_conf.sc_siumcr =
259 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) 259 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
260 | SIUMCR_LBPC01; 260 | SIUMCR_LBPC01;
261 #elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
262 /* nothing to do for this board here */
261 #elif defined CONFIG_MPC8272 263 #elif defined CONFIG_MPC8272
262 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & 264 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
263 ~SIUMCR_BBD & 265 ~SIUMCR_BBD &
264 ~SIUMCR_ESE & 266 ~SIUMCR_ESE &
265 ~SIUMCR_PBSE & 267 ~SIUMCR_PBSE &
266 ~SIUMCR_CDIS & 268 ~SIUMCR_CDIS &
267 ~SIUMCR_DPPC11 & 269 ~SIUMCR_DPPC11 &
268 ~SIUMCR_L2CPC11 & 270 ~SIUMCR_L2CPC11 &
269 ~SIUMCR_LBPC11 & 271 ~SIUMCR_LBPC11 &
270 ~SIUMCR_APPC11 & 272 ~SIUMCR_APPC11 &
271 ~SIUMCR_CS10PC11 & 273 ~SIUMCR_CS10PC11 &
272 ~SIUMCR_BCTLC11 & 274 ~SIUMCR_BCTLC11 &
273 ~SIUMCR_MMR11) 275 ~SIUMCR_MMR11)
274 | SIUMCR_DPPC11 276 | SIUMCR_DPPC11
275 | SIUMCR_L2CPC01 277 | SIUMCR_L2CPC01
276 | SIUMCR_LBPC00 278 | SIUMCR_LBPC00
277 | SIUMCR_APPC10 279 | SIUMCR_APPC10
278 | SIUMCR_CS10PC00 280 | SIUMCR_CS10PC00
279 | SIUMCR_BCTLC00 281 | SIUMCR_BCTLC00
280 | SIUMCR_MMR11; 282 | SIUMCR_MMR11;
281 #elif defined(CONFIG_TQM8272) 283 #elif defined(CONFIG_TQM8272)
282 /* nothing to do for this Board here */ 284 /* nothing to do for this Board here */
283 #else 285 #else
284 /* 286 /*
285 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), 287 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
286 * and local bus for PCI (SIUMCR [LBPC]). 288 * and local bus for PCI (SIUMCR [LBPC]).
287 */ 289 */
288 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & 290 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
289 ~SIUMCR_LBPC11 & 291 ~SIUMCR_LBPC11 &
290 ~SIUMCR_CS10PC11 & 292 ~SIUMCR_CS10PC11 &
291 ~SIUMCR_LBPC11) | 293 ~SIUMCR_LBPC11) |
292 SIUMCR_LBPC01 | 294 SIUMCR_LBPC01 |
293 SIUMCR_CS10PC01 | 295 SIUMCR_CS10PC01 |
294 SIUMCR_APPC10; 296 SIUMCR_APPC10;
295 #endif 297 #endif
296 298
297 /* Make PCI lowest priority */ 299 /* Make PCI lowest priority */
298 /* Each 4 bits is a device bus request and the MS 4bits 300 /* Each 4 bits is a device bus request and the MS 4bits
299 is highest priority */ 301 is highest priority */
300 /* Bus 4bit value 302 /* Bus 4bit value
301 --- ---------- 303 --- ----------
302 CPM high 0b0000 304 CPM high 0b0000
303 CPM middle 0b0001 305 CPM middle 0b0001
304 CPM low 0b0010 306 CPM low 0b0010
305 PCI reguest 0b0011 307 PCI reguest 0b0011
306 Reserved 0b0100 308 Reserved 0b0100
307 Reserved 0b0101 309 Reserved 0b0101
308 Internal Core 0b0110 310 Internal Core 0b0110
309 External Master 1 0b0111 311 External Master 1 0b0111
310 External Master 2 0b1000 312 External Master 2 0b1000
311 External Master 3 0b1001 313 External Master 3 0b1001
312 The rest are reserved */ 314 The rest are reserved */
313 immap->im_siu_conf.sc_ppc_alrh = 0x61207893; 315 immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
314 316
315 /* Park bus on core while modifying PCI Bus accesses */ 317 /* Park bus on core while modifying PCI Bus accesses */
316 immap->im_siu_conf.sc_ppc_acr = 0x6; 318 immap->im_siu_conf.sc_ppc_acr = 0x6;
317 319
318 /* 320 /*
319 * Set up master windows that allow the CPU to access PCI space. These 321 * Set up master windows that allow the CPU to access PCI space. These
320 * windows are set up using the two SIU PCIBR registers. 322 * windows are set up using the two SIU PCIBR registers.
321 */ 323 */
322 immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; 324 immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
323 immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; 325 immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
324 326
325 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 327 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
326 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK; 328 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
327 immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE; 329 immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
328 #endif 330 #endif
329 331
330 /* Release PCI RST (by default the PCI RST signal is held low) */ 332 /* Release PCI RST (by default the PCI RST signal is held low) */
331 immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); 333 immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
332 334
333 /* give it some time */ 335 /* give it some time */
334 { 336 {
335 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 337 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
336 /* Give the PCI cards more time to initialize before query 338 /* Give the PCI cards more time to initialize before query
337 This might be good for other boards also 339 This might be good for other boards also
338 */ 340 */
339 int i; 341 int i;
340 342
341 for (i = 0; i < 1000; ++i) 343 for (i = 0; i < 1000; ++i)
342 #endif 344 #endif
343 udelay (1000); 345 udelay (1000);
344 } 346 }
345 347
346 /* 348 /*
347 * Set up master window that allows the CPU to access PCI Memory (prefetch) 349 * Set up master window that allows the CPU to access PCI Memory (prefetch)
348 * space. This window is set up using the first set of Outbound ATU registers. 350 * space. This window is set up using the first set of Outbound ATU registers.
349 */ 351 */
350 immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */ 352 immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
351 immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ 353 immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
352 immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */ 354 immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
353 355
354 /* 356 /*
355 * Set up master window that allows the CPU to access PCI Memory (non-prefetch) 357 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
356 * space. This window is set up using the second set of Outbound ATU registers. 358 * space. This window is set up using the second set of Outbound ATU registers.
357 */ 359 */
358 immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ 360 immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
359 immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ 361 immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
360 immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */ 362 immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
361 363
362 /* 364 /*
363 * Set up master window that allows the CPU to access PCI IO space. This window 365 * Set up master window that allows the CPU to access PCI IO space. This window
364 * is set up using the third set of Outbound ATU registers. 366 * is set up using the third set of Outbound ATU registers.
365 */ 367 */
366 immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */ 368 immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
367 immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */ 369 immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
368 immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */ 370 immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
369 371
370 /* 372 /*
371 * Set up slave window that allows PCI masters to access MPC826x local memory. 373 * Set up slave window that allows PCI masters to access MPC826x local memory.
372 * This window is set up using the first set of Inbound ATU registers 374 * This window is set up using the first set of Inbound ATU registers
373 */ 375 */
374 immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */ 376 immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
375 immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */ 377 immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
376 immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ 378 immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
377 379
378 /* See above for description - puts PCI request as highest priority */ 380 /* See above for description - puts PCI request as highest priority */
379 #ifdef CONFIG_MPC8272 381 #ifdef CONFIG_MPC8272
380 immap->im_siu_conf.sc_ppc_alrh = 0x01236745; 382 immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
381 #else 383 #else
382 immap->im_siu_conf.sc_ppc_alrh = 0x03124567; 384 immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
383 #endif 385 #endif
384 386
385 /* Park the bus on the PCI */ 387 /* Park the bus on the PCI */
386 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; 388 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
387 389
388 /* Host mode - specify the bridge as a host-PCI bridge */ 390 /* Host mode - specify the bridge as a host-PCI bridge */
389 391
390 pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE, 392 pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
391 PCI_CLASS_BRIDGE_CTLR); 393 PCI_CLASS_BRIDGE_CTLR);
392 394
393 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ 395 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
394 pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort); 396 pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
395 pci_hose_write_config_word (hose, host_devno, PCI_COMMAND, 397 pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
396 tempShort | PCI_COMMAND_MASTER | 398 tempShort | PCI_COMMAND_MASTER |
397 PCI_COMMAND_MEMORY); 399 PCI_COMMAND_MEMORY);
398 400
399 /* do some bridge init, should be done on all 8260 based bridges */ 401 /* do some bridge init, should be done on all 8260 based bridges */
400 pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, 402 pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
401 0x08); 403 0x08);
402 pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, 404 pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
403 0xF8); 405 0xF8);
404 406
405 hose->first_busno = 0; 407 hose->first_busno = 0;
406 hose->last_busno = 0xff; 408 hose->last_busno = 0xff;
407 409
408 /* System memory space */ 410 /* System memory space */
409 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 411 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
410 pci_set_region (hose->regions + 0, 412 pci_set_region (hose->regions + 0,
411 PCI_SLV_MEM_BUS, 413 PCI_SLV_MEM_BUS,
412 PCI_SLV_MEM_LOCAL, 414 PCI_SLV_MEM_LOCAL,
413 gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 415 gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
414 #else 416 #else
415 pci_set_region (hose->regions + 0, 417 pci_set_region (hose->regions + 0,
416 CONFIG_SYS_SDRAM_BASE, 418 CONFIG_SYS_SDRAM_BASE,
417 CONFIG_SYS_SDRAM_BASE, 419 CONFIG_SYS_SDRAM_BASE,
418 0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 420 0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
419 #endif 421 #endif
420 422
421 /* PCI memory space */ 423 /* PCI memory space */
422 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 424 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
423 pci_set_region (hose->regions + 1, 425 pci_set_region (hose->regions + 1,
424 PCI_MSTR_MEMIO_BUS, 426 PCI_MSTR_MEMIO_BUS,
425 PCI_MSTR_MEMIO_LOCAL, 427 PCI_MSTR_MEMIO_LOCAL,
426 PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM); 428 PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
427 #else 429 #else
428 pci_set_region (hose->regions + 1, 430 pci_set_region (hose->regions + 1,
429 PCI_MSTR_MEM_BUS, 431 PCI_MSTR_MEM_BUS,
430 PCI_MSTR_MEM_LOCAL, 432 PCI_MSTR_MEM_LOCAL,
431 PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); 433 PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
432 #endif 434 #endif
433 435
434 /* PCI I/O space */ 436 /* PCI I/O space */
435 pci_set_region (hose->regions + 2, 437 pci_set_region (hose->regions + 2,
436 PCI_MSTR_IO_BUS, 438 PCI_MSTR_IO_BUS,
437 PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO); 439 PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
438 440
439 hose->region_count = 3; 441 hose->region_count = 3;
440 442
441 pci_register_hose (hose); 443 pci_register_hose (hose);
442 /* Mask off master abort machine checks */ 444 /* Mask off master abort machine checks */
443 immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP); 445 immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
444 eieio (); 446 eieio ();
445 447
446 hose->last_busno = pci_hose_scan (hose); 448 hose->last_busno = pci_hose_scan (hose);
447 449
448 450
449 /* clear the error in the error status register */ 451 /* clear the error in the error status register */
450 immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); 452 immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
451 453
452 /* unmask master abort machine checks */ 454 /* unmask master abort machine checks */
453 immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); 455 immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
454 } 456 }
455 457
456 #if defined(CONFIG_OF_LIBFDT) 458 #if defined(CONFIG_OF_LIBFDT)
457 void ft_pci_setup(void *blob, bd_t *bd) 459 void ft_pci_setup(void *blob, bd_t *bd)
458 { 460 {
459 do_fixup_by_prop_u32(blob, "device_type", "pci", 4, 461 do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
460 "clock-frequency", gd->pci_clk, 1); 462 "clock-frequency", gd->pci_clk, 1);
461 } 463 }
462 #endif 464 #endif
463 465
464 #endif /* CONFIG_PCI */ 466 #endif /* CONFIG_PCI */
465 467
include/configs/MPC8260ADS.h
Diff comments   View file @ 8701ece
1 /* 1 /*
2 * (C) Copyright 2001 2 * (C) Copyright 2001
3 * Stuart Hughes <stuarth@lineo.com> 3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other 4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual. 5 * U-Boot config files, and some that I found in the mpc8260ads manual.
6 * 6 *
7 * Note: my board is a PILOT rev. 7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. 8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
9 * 9 *
10 * (C) Copyright 2003-2004 Arabella Software Ltd. 10 * (C) Copyright 2003-2004 Arabella Software Ltd.
11 * Yuli Barcohen <yuli@arabellasw.com> 11 * Yuli Barcohen <yuli@arabellasw.com>
12 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2. 12 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
13 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. 13 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
14 * Ported to MPC8272ADS board. 14 * Ported to MPC8272ADS board.
15 * 15 *
16 * Copyright (c) 2005 MontaVista Software, Inc. 16 * Copyright (c) 2005 MontaVista Software, Inc.
17 * Vitaly Bordug <vbordug@ru.mvista.com> 17 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI bridge on MPC8272ADS 18 * Added support for PCI bridge on MPC8272ADS
19 * 19 *
20 * See file CREDITS for list of people who contributed to this 20 * See file CREDITS for list of people who contributed to this
21 * project. 21 * project.
22 * 22 *
23 * This program is free software; you can redistribute it and/or 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as 24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of 25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version. 26 * the License, or (at your option) any later version.
27 * 27 *
28 * This program is distributed in the hope that it will be useful, 28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details. 31 * GNU General Public License for more details.
32 * 32 *
33 * You should have received a copy of the GNU General Public License 33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software 34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 * MA 02111-1307 USA 36 * MA 02111-1307 USA
37 */ 37 */
38 38
39 #ifndef __CONFIG_H 39 #ifndef __CONFIG_H
40 #define __CONFIG_H 40 #define __CONFIG_H
41 41
42 /* 42 /*
43 * High Level Configuration Options 43 * High Level Configuration Options
44 * (easy to change) 44 * (easy to change)
45 */ 45 */
46 46
47 #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */ 47 #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
48 48
49 #define CONFIG_CPM2 1 /* Has a CPM2 */ 49 #define CONFIG_CPM2 1 /* Has a CPM2 */
50 50
51 /* 51 /*
52 * Figure out if we are booting low via flash HRCW or high via the BCSR. 52 * Figure out if we are booting low via flash HRCW or high via the BCSR.
53 */ 53 */
54 #if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ 54 #if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
55 # define CONFIG_SYS_LOWBOOT 1 55 # define CONFIG_SYS_LOWBOOT 1
56 #endif 56 #endif
57 57
58 /* ADS flavours */ 58 /* ADS flavours */
59 #define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */ 59 #define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
60 #define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */ 60 #define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
61 #define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */ 61 #define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
62 #define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */ 62 #define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
63 63
64 #ifndef CONFIG_ADSTYPE 64 #ifndef CONFIG_ADSTYPE
65 #define CONFIG_ADSTYPE CONFIG_SYS_8260ADS 65 #define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
66 #endif /* CONFIG_ADSTYPE */ 66 #endif /* CONFIG_ADSTYPE */
67 67
68 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS 68 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
69 #define CONFIG_MPC8272 1 69 #define CONFIG_MPC8272 1
70 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
71 /*
72 * Actually MPC8275, but the code is littered with ifdefs that
73 * apply to both, or which use this ifdef to assume board-specific
74 * details. :-(
75 */
76 #define CONFIG_MPC8272 1
70 #else 77 #else
71 #define CONFIG_MPC8260 1 78 #define CONFIG_MPC8260 1
72 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ 79 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
73 80
74 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 81 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
75 82
76 /* allow serial and ethaddr to be overwritten */ 83 /* allow serial and ethaddr to be overwritten */
77 #define CONFIG_ENV_OVERWRITE 84 #define CONFIG_ENV_OVERWRITE
78 85
79 /* 86 /*
80 * select serial console configuration 87 * select serial console configuration
81 * 88 *
82 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 89 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
83 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 90 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
84 * for SCC). 91 * for SCC).
85 * 92 *
86 * if CONFIG_CONS_NONE is defined, then the serial console routines must 93 * if CONFIG_CONS_NONE is defined, then the serial console routines must
87 * defined elsewhere (for example, on the cogent platform, there are serial 94 * defined elsewhere (for example, on the cogent platform, there are serial
88 * ports on the motherboard which are used for the serial console - see 95 * ports on the motherboard which are used for the serial console - see
89 * cogent/cma101/serial.[ch]). 96 * cogent/cma101/serial.[ch]).
90 */ 97 */
91 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ 98 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
92 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 99 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
93 #undef CONFIG_CONS_NONE /* define if console on something else */ 100 #undef CONFIG_CONS_NONE /* define if console on something else */
94 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 101 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
95 102
96 /* 103 /*
97 * select ethernet configuration 104 * select ethernet configuration
98 * 105 *
99 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 106 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
100 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 107 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
101 * for FCC) 108 * for FCC)
102 * 109 *
103 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 110 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
104 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 111 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
105 */ 112 */
106 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 113 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
107 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 114 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
108 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 115 #undef CONFIG_ETHER_NONE /* define if ether on something else */
109 116
110 #ifdef CONFIG_ETHER_ON_FCC 117 #ifdef CONFIG_ETHER_ON_FCC
111 118
112 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ 119 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
113 120
114 #if CONFIG_ETHER_INDEX == 1 121 #if CONFIG_ETHER_INDEX == 1
115 122
116 # define CONFIG_SYS_PHY_ADDR 0 123 # define CONFIG_SYS_PHY_ADDR 0
117 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) 124 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
118 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) 125 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
119 126
120 #elif CONFIG_ETHER_INDEX == 2 127 #elif CONFIG_ETHER_INDEX == 2
121 128
122 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */ 129 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
123 # define CONFIG_SYS_PHY_ADDR 3 130 # define CONFIG_SYS_PHY_ADDR 3
124 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16) 131 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
125 #else /* RxCLK is CLK13, TxCLK is CLK14 */ 132 #else /* RxCLK is CLK13, TxCLK is CLK14 */
126 # define CONFIG_SYS_PHY_ADDR 0 133 # define CONFIG_SYS_PHY_ADDR 0
127 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 134 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
128 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ 135 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
129 136
130 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 137 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
131 138
132 #endif /* CONFIG_ETHER_INDEX */ 139 #endif /* CONFIG_ETHER_INDEX */
133 140
134 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */ 141 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
135 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */ 142 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
136 143
137 #define CONFIG_MII /* MII PHY management */ 144 #define CONFIG_MII /* MII PHY management */
138 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 145 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
139 /* 146 /*
140 * GPIO pins used for bit-banged MII communications 147 * GPIO pins used for bit-banged MII communications
141 */ 148 */
142 #define MDIO_PORT 2 /* Port C */ 149 #define MDIO_PORT 2 /* Port C */
143 150
144 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS 151 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
145 #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */ 152 #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
146 #define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */ 153 #define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
147 #else 154 #else
148 #define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */ 155 #define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
149 #define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */ 156 #define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
150 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ 157 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
151 158
152 #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) 159 #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
153 #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) 160 #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
154 #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) 161 #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
155 162
156 #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ 163 #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
157 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN 164 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
158 165
159 #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ 166 #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
160 else iop->pdat &= ~CONFIG_SYS_MDC_PIN 167 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
161 168
162 #define MIIDELAY udelay(1) 169 #define MIIDELAY udelay(1)
163 170
164 #endif /* CONFIG_ETHER_ON_FCC */ 171 #endif /* CONFIG_ETHER_ON_FCC */
165 172
166 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS 173 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
167 #undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */ 174 #undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
168 #else 175 #else
169 #define CONFIG_HARD_I2C 1 /* To enable I2C support */ 176 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
170 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ 177 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
171 #define CONFIG_SYS_I2C_SLAVE 0x7F 178 #define CONFIG_SYS_I2C_SLAVE 0x7F
172 179
173 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) 180 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
174 #define CONFIG_SPD_ADDR 0x50 181 #define CONFIG_SPD_ADDR 0x50
175 #endif 182 #endif
176 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */ 183 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
177 184
178 /*PCI*/ 185 /*PCI*/
179 #ifdef CONFIG_MPC8272 186 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
180 #define CONFIG_PCI 187 #define CONFIG_PCI
181 #define CONFIG_PCI_PNP 188 #define CONFIG_PCI_PNP
182 #define CONFIG_PCI_BOOTDELAY 0 189 #define CONFIG_PCI_BOOTDELAY 0
183 #define CONFIG_PCI_SCAN_SHOW 190 #define CONFIG_PCI_SCAN_SHOW
184 #endif 191 #endif
185 192
186 #ifndef CONFIG_SDRAM_PBI 193 #ifndef CONFIG_SDRAM_PBI
187 #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ 194 #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
188 #endif 195 #endif
189 196
190 #ifndef CONFIG_8260_CLKIN 197 #ifndef CONFIG_8260_CLKIN
191 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS 198 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
192 #define CONFIG_8260_CLKIN 100000000 /* in Hz */ 199 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
193 #else 200 #else
194 #define CONFIG_8260_CLKIN 66000000 /* in Hz */ 201 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
195 #endif 202 #endif
196 #endif 203 #endif
197 204
198 #define CONFIG_BAUDRATE 115200 205 #define CONFIG_BAUDRATE 115200
199 206
200 #define CONFIG_OF_LIBFDT 1 207 #define CONFIG_OF_LIBFDT 1
201 #define CONFIG_OF_BOARD_SETUP 1 208 #define CONFIG_OF_BOARD_SETUP 1
202 #if defined(CONFIG_OF_LIBFDT) 209 #if defined(CONFIG_OF_LIBFDT)
203 #define OF_CPU "cpu@0" 210 #define OF_CPU "cpu@0"
204 #define OF_TBCLK (bd->bi_busfreq / 4) 211 #define OF_TBCLK (bd->bi_busfreq / 4)
205 #endif 212 #endif
206 213
207 /* 214 /*
208 * BOOTP options 215 * BOOTP options
209 */ 216 */
210 #define CONFIG_BOOTP_BOOTFILESIZE 217 #define CONFIG_BOOTP_BOOTFILESIZE
211 #define CONFIG_BOOTP_BOOTPATH 218 #define CONFIG_BOOTP_BOOTPATH
212 #define CONFIG_BOOTP_GATEWAY 219 #define CONFIG_BOOTP_GATEWAY
213 #define CONFIG_BOOTP_HOSTNAME 220 #define CONFIG_BOOTP_HOSTNAME
214 221
215 222
216 /* 223 /*
217 * Command line configuration. 224 * Command line configuration.
218 */ 225 */
219 #include <config_cmd_default.h> 226 #include <config_cmd_default.h>
220 227
221 #define CONFIG_CMD_ASKENV 228 #define CONFIG_CMD_ASKENV
222 #define CONFIG_CMD_CACHE 229 #define CONFIG_CMD_CACHE
223 #define CONFIG_CMD_CDP 230 #define CONFIG_CMD_CDP
224 #define CONFIG_CMD_DHCP 231 #define CONFIG_CMD_DHCP
225 #define CONFIG_CMD_DIAG 232 #define CONFIG_CMD_DIAG
226 #define CONFIG_CMD_I2C 233 #define CONFIG_CMD_I2C
227 #define CONFIG_CMD_IMMAP 234 #define CONFIG_CMD_IMMAP
228 #define CONFIG_CMD_IRQ 235 #define CONFIG_CMD_IRQ
229 #define CONFIG_CMD_JFFS2 236 #define CONFIG_CMD_JFFS2
230 #define CONFIG_CMD_MII 237 #define CONFIG_CMD_MII
231 #define CONFIG_CMD_PCI 238 #define CONFIG_CMD_PCI
232 #define CONFIG_CMD_PING 239 #define CONFIG_CMD_PING
233 #define CONFIG_CMD_PORTIO 240 #define CONFIG_CMD_PORTIO
234 #define CONFIG_CMD_REGINFO 241 #define CONFIG_CMD_REGINFO
235 #define CONFIG_CMD_SAVES 242 #define CONFIG_CMD_SAVES
236 #define CONFIG_CMD_SDRAM 243 #define CONFIG_CMD_SDRAM
237 244
238 #undef CONFIG_CMD_XIMG 245 #undef CONFIG_CMD_XIMG
239 246
240 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS 247 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
241 #undef CONFIG_CMD_SDRAM 248 #undef CONFIG_CMD_SDRAM
242 #undef CONFIG_CMD_I2C 249 #undef CONFIG_CMD_I2C
243 250
244 #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS 251 #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
245 #undef CONFIG_CMD_SDRAM 252 #undef CONFIG_CMD_SDRAM
246 #undef CONFIG_CMD_I2C 253 #undef CONFIG_CMD_I2C
247 #undef CONFIG_CMD_PCI
248 254
249 #else 255 #else
250 #undef CONFIG_CMD_PCI 256 #undef CONFIG_CMD_PCI
251 257
252 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */ 258 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
253 259
254 260
255 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 261 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
256 #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ 262 #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
257 #define CONFIG_BOOTARGS "root=/dev/mtdblock2" 263 #define CONFIG_BOOTARGS "root=/dev/mtdblock2"
258 264
259 #if defined(CONFIG_CMD_KGDB) 265 #if defined(CONFIG_CMD_KGDB)
260 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ 266 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
261 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ 267 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
262 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ 268 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
263 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ 269 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
264 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ 270 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
265 #endif 271 #endif
266 272
267 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ 273 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
268 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ 274 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
269 275
270 /* 276 /*
271 * Miscellaneous configurable options 277 * Miscellaneous configurable options
272 */ 278 */
273 #define CONFIG_SYS_HUSH_PARSER 279 #define CONFIG_SYS_HUSH_PARSER
274 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 280 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
275 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 281 #define CONFIG_SYS_LONGHELP /* undef to save memory */
276 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 282 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
277 #if defined(CONFIG_CMD_KGDB) 283 #if defined(CONFIG_CMD_KGDB)
278 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 284 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
279 #else 285 #else
280 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 286 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
281 #endif 287 #endif
282 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 288 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
283 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 289 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
284 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 290 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
285 291
286 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 292 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
287 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 293 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
288 294
289 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ 295 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
290 296
291 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 297 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
292 298
293 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 299 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
294 300
295 #define CONFIG_SYS_FLASH_BASE 0xff800000 301 #define CONFIG_SYS_FLASH_BASE 0xff800000
296 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 302 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
297 #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */ 303 #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
298 #define CONFIG_SYS_FLASH_SIZE 8 304 #define CONFIG_SYS_FLASH_SIZE 8
299 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ 305 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
300 #define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ 306 #define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
301 #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ 307 #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
302 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ 308 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
303 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 309 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
304 310
305 /* 311 /*
306 * JFFS2 partitions 312 * JFFS2 partitions
307 * 313 *
308 * Note: fake mtd_id used, no linux mtd map file 314 * Note: fake mtd_id used, no linux mtd map file
309 */ 315 */
310 #define MTDIDS_DEFAULT "nor0=mpc8260ads-0" 316 #define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
311 #define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)" 317 #define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
312 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS 318 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
313 319
314 /* this is stuff came out of the Motorola docs */ 320 /* this is stuff came out of the Motorola docs */
315 #ifndef CONFIG_SYS_LOWBOOT 321 #ifndef CONFIG_SYS_LOWBOOT
316 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 322 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
317 #endif 323 #endif
318 324
319 #define CONFIG_SYS_IMMR 0xF0000000 325 #define CONFIG_SYS_IMMR 0xF0000000
320 #define CONFIG_SYS_BCSR 0xF4500000 326 #define CONFIG_SYS_BCSR 0xF4500000
321 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS 327 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
322 #define CONFIG_SYS_PCI_INT 0xF8200000 328 #define CONFIG_SYS_PCI_INT 0xF8200000
323 #endif 329 #endif
324 #define CONFIG_SYS_SDRAM_BASE 0x00000000 330 #define CONFIG_SYS_SDRAM_BASE 0x00000000
325 #define CONFIG_SYS_LSDRAM_BASE 0xFD000000 331 #define CONFIG_SYS_LSDRAM_BASE 0xFD000000
326 332
327 #define RS232EN_1 0x02000002 333 #define RS232EN_1 0x02000002
328 #define RS232EN_2 0x01000001 334 #define RS232EN_2 0x01000001
329 #define FETHIEN1 0x08000008 335 #define FETHIEN1 0x08000008
330 #define FETH1_RST 0x04000004 336 #define FETH1_RST 0x04000004
331 #define FETHIEN2 0x10000000 337 #define FETHIEN2 0x10000000
332 #define FETH2_RST 0x08000000 338 #define FETH2_RST 0x08000000
333 #define BCSR_PCI_MODE 0x01000000 339 #define BCSR_PCI_MODE 0x01000000
334 340
335 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 341 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
336 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ 342 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
337 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 343 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
338 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 344 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
339 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 345 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
340 346
341 #ifdef CONFIG_SYS_LOWBOOT 347 #ifdef CONFIG_SYS_LOWBOOT
342 /* PQ2FADS flash HRCW = 0x0EB4B645 */ 348 /* PQ2FADS flash HRCW = 0x0EB4B645 */
343 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ 349 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
344 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\ 350 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
345 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ 351 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
346 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ 352 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
347 ) 353 )
348 #else 354 #else
349 /* PQ2FADS BCSR HRCW = 0x0CB23645 */ 355 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
350 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ 356 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
351 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ 357 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
352 ( HRCW_BMS | HRCW_APPC10 ) |\ 358 ( HRCW_BMS | HRCW_APPC10 ) |\
353 ( HRCW_MODCK_H0101 ) \ 359 ( HRCW_MODCK_H0101 ) \
354 ) 360 )
355 #endif 361 #endif
356 /* no slaves */ 362 /* no slaves */
357 #define CONFIG_SYS_HRCW_SLAVE1 0 363 #define CONFIG_SYS_HRCW_SLAVE1 0
358 #define CONFIG_SYS_HRCW_SLAVE2 0 364 #define CONFIG_SYS_HRCW_SLAVE2 0
359 #define CONFIG_SYS_HRCW_SLAVE3 0 365 #define CONFIG_SYS_HRCW_SLAVE3 0
360 #define CONFIG_SYS_HRCW_SLAVE4 0 366 #define CONFIG_SYS_HRCW_SLAVE4 0
361 #define CONFIG_SYS_HRCW_SLAVE5 0 367 #define CONFIG_SYS_HRCW_SLAVE5 0
362 #define CONFIG_SYS_HRCW_SLAVE6 0 368 #define CONFIG_SYS_HRCW_SLAVE6 0
363 #define CONFIG_SYS_HRCW_SLAVE7 0 369 #define CONFIG_SYS_HRCW_SLAVE7 0
364 370
365 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 371 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
366 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 372 #define BOOTFLAG_WARM 0x02 /* Software reboot */
367 373
368 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE 374 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
369 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 375 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
370 # define CONFIG_SYS_RAMBOOT 376 # define CONFIG_SYS_RAMBOOT
371 #endif 377 #endif
372 378
373 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 379 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
374 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 380 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
375 381
376 #ifdef CONFIG_BZIP2 382 #ifdef CONFIG_BZIP2
377 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ 383 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
378 #else 384 #else
379 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ 385 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
380 #endif /* CONFIG_BZIP2 */ 386 #endif /* CONFIG_BZIP2 */
381 387
382 #ifndef CONFIG_SYS_RAMBOOT 388 #ifndef CONFIG_SYS_RAMBOOT
383 # define CONFIG_ENV_IS_IN_FLASH 1 389 # define CONFIG_ENV_IS_IN_FLASH 1
384 # define CONFIG_ENV_SECT_SIZE 0x40000 390 # define CONFIG_ENV_SECT_SIZE 0x40000
385 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE) 391 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
386 #else 392 #else
387 # define CONFIG_ENV_IS_IN_NVRAM 1 393 # define CONFIG_ENV_IS_IN_NVRAM 1
388 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 394 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
389 # define CONFIG_ENV_SIZE 0x200 395 # define CONFIG_ENV_SIZE 0x200
390 #endif /* CONFIG_SYS_RAMBOOT */ 396 #endif /* CONFIG_SYS_RAMBOOT */
391 397
392 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 398 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
393 #if defined(CONFIG_CMD_KGDB) 399 #if defined(CONFIG_CMD_KGDB)
394 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 400 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
395 #endif 401 #endif
396 402
397 #define CONFIG_SYS_HID0_INIT 0 403 #define CONFIG_SYS_HID0_INIT 0
398 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) 404 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
399 405
400 #define CONFIG_SYS_HID2 0 406 #define CONFIG_SYS_HID2 0
401 407
402 #define CONFIG_SYS_SYPCR 0xFFFFFFC3 408 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
403 #define CONFIG_SYS_BCR 0x100C0000 409 #define CONFIG_SYS_BCR 0x100C0000
404 #define CONFIG_SYS_SIUMCR 0x0A200000 410 #define CONFIG_SYS_SIUMCR 0x0A200000
405 #define CONFIG_SYS_SCCR SCCR_DFBRG01 411 #define CONFIG_SYS_SCCR SCCR_DFBRG01
406 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801) 412 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
407 #define CONFIG_SYS_OR0_PRELIM 0xFF800876 413 #define CONFIG_SYS_OR0_PRELIM 0xFF800876
408 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801) 414 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
409 #define CONFIG_SYS_OR1_PRELIM 0xFFFF8010 415 #define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
410 416
411 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ 417 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
412 418
413 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS 419 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
414 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ 420 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
415 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8010 421 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
422 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
423 #define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
424 #define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
416 #endif 425 #endif
417 426
418 #define CONFIG_SYS_RMR RMR_CSRE 427 #define CONFIG_SYS_RMR RMR_CSRE
419 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 428 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
420 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 429 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
421 #define CONFIG_SYS_RCCR 0 430 #define CONFIG_SYS_RCCR 0
422 431
423 #if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS) 432 #if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
424 #undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */ 433 #undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
425 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */ 434 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
426 435
427 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS 436 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
428 #define CONFIG_SYS_OR2 0xFE002EC0 437 #define CONFIG_SYS_OR2 0xFE002EC0
429 #define CONFIG_SYS_PSDMR 0x824B36A3 438 #define CONFIG_SYS_PSDMR 0x824B36A3
430 #define CONFIG_SYS_PSRT 0x13 439 #define CONFIG_SYS_PSRT 0x13
431 #define CONFIG_SYS_LSDMR 0x828737A3 440 #define CONFIG_SYS_LSDMR 0x828737A3
432 #define CONFIG_SYS_LSRT 0x13 441 #define CONFIG_SYS_LSRT 0x13
433 #define CONFIG_SYS_MPTPR 0x2800 442 #define CONFIG_SYS_MPTPR 0x2800
434 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS 443 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
435 #define CONFIG_SYS_OR2 0xFC002CC0 444 #define CONFIG_SYS_OR2 0xFC002CC0
436 #define CONFIG_SYS_PSDMR 0x834E24A3 445 #define CONFIG_SYS_PSDMR 0x834E24A3
437 #define CONFIG_SYS_PSRT 0x13 446 #define CONFIG_SYS_PSRT 0x13
438 #define CONFIG_SYS_MPTPR 0x2800 447 #define CONFIG_SYS_MPTPR 0x2800
439 #else 448 #else
440 #define CONFIG_SYS_OR2 0xFF000CA0 449 #define CONFIG_SYS_OR2 0xFF000CA0
441 #define CONFIG_SYS_PSDMR 0x016EB452 450 #define CONFIG_SYS_PSDMR 0x016EB452
442 #define CONFIG_SYS_PSRT 0x21 451 #define CONFIG_SYS_PSRT 0x21
443 #define CONFIG_SYS_LSDMR 0x0086A522 452 #define CONFIG_SYS_LSDMR 0x0086A522
444 #define CONFIG_SYS_LSRT 0x21 453 #define CONFIG_SYS_LSRT 0x21
445 #define CONFIG_SYS_MPTPR 0x1900 454 #define CONFIG_SYS_MPTPR 0x1900
446 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ 455 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
447 456
448 #define CONFIG_SYS_RESET_ADDRESS 0x04400000 457 #define CONFIG_SYS_RESET_ADDRESS 0x04400000
449 458
450 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS 459 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
451 460
452 /* PCI Memory map (if different from default map */ 461 /* PCI Memory map (if different from default map */
453 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ 462 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
454 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ 463 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
455 #define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ 464 #define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
456 PICMR_PREFETCH_EN) 465 PICMR_PREFETCH_EN)
457 466
458 /* 467 /*
459 * These are the windows that allow the CPU to access PCI address space. 468 * These are the windows that allow the CPU to access PCI address space.
460 * All three PCI master windows, which allow the CPU to access PCI 469 * All three PCI master windows, which allow the CPU to access PCI
461 * prefetch, non prefetch, and IO space (see below), must all fit within 470 * prefetch, non prefetch, and IO space (see below), must all fit within
462 * these windows. 471 * these windows.
463 */ 472 */
464 473
465 /* 474 /*
466 * Master window that allows the CPU to access PCI Memory (prefetch). 475 * Master window that allows the CPU to access PCI Memory (prefetch).
467 * This window will be setup with the second set of Outbound ATU registers 476 * This window will be setup with the second set of Outbound ATU registers
468 * in the bridge. 477 * in the bridge.
469 */ 478 */
470 479
471 #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ 480 #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
472 #define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ 481 #define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
473 #define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL 482 #define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
474 #define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ 483 #define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
475 #define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) 484 #define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
476 485
477 /* 486 /*
478 * Master window that allows the CPU to access PCI Memory (non-prefetch). 487 * Master window that allows the CPU to access PCI Memory (non-prefetch).
479 * This window will be setup with the second set of Outbound ATU registers 488 * This window will be setup with the second set of Outbound ATU registers
480 * in the bridge. 489 * in the bridge.
481 */ 490 */
482 491
483 #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ 492 #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
484 #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ 493 #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
485 #define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL 494 #define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
486 #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ 495 #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
487 #define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) 496 #define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
488 497
489 /* 498 /*
490 * Master window that allows the CPU to access PCI IO space. 499 * Master window that allows the CPU to access PCI IO space.
491 * This window will be setup with the first set of Outbound ATU registers 500 * This window will be setup with the first set of Outbound ATU registers
492 * in the bridge. 501 * in the bridge.
493 */ 502 */
494 503
495 #define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ 504 #define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
496 #define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ 505 #define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
497 #define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL 506 #define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
498 #define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ 507 #define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
499 #define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) 508 #define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
500 509
501 510
502 /* PCIBR0 - for PCI IO*/ 511 /* PCIBR0 - for PCI IO*/
503 #define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */ 512 #define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
504 #define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ 513 #define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
505 /* PCIBR1 - prefetch and non-prefetch regions joined together */ 514 /* PCIBR1 - prefetch and non-prefetch regions joined together */
506 #define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL 515 #define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
507 #define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U) 516 #define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
508 517
509 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ 518 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
510 519
511 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS 520 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
512 #define CONFIG_HAS_ETH1 521 #define CONFIG_HAS_ETH1
513 #endif 522 #endif
514 523
515 #endif /* __CONFIG_H */ 524 #endif /* __CONFIG_H */