Eric Lee / smarc-uboot

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Commit 87a19df5e462f1f63e8a6d2973c7fb9e95284d04

Authored by Ji Luo
1 parent 2aa4163329
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MA-14511 AIY: Change the GPU reserved memory to 32M 

Reserve 32M memory for GPU on AIY 1G DDR board.

Change-Id: I566a4a027982c8d4e41f280162f2f3cd67f1f5cd
Signed-off-by: Ji Luo <ji.luo@nxp.com>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

board/freescale/imx8mq_aiy/imx8m_aiy.c
Diff comments   View file @ 87a19df
1 /* 1 /*
2 * Copyright 2016 Freescale Semiconductor, Inc. 2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017-2019 NXP 3 * Copyright 2017-2019 NXP
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <malloc.h> 9 #include <malloc.h>
10 #include <errno.h> 10 #include <errno.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <miiphy.h> 12 #include <miiphy.h>
13 #include <netdev.h> 13 #include <netdev.h>
14 #include <asm/mach-imx/iomux-v3.h> 14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm-generic/gpio.h> 15 #include <asm-generic/gpio.h>
16 #include <fsl_esdhc.h> 16 #include <fsl_esdhc.h>
17 #include <mmc.h> 17 #include <mmc.h>
18 #include <asm/arch/imx8mq_pins.h> 18 #include <asm/arch/imx8mq_pins.h>
19 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/gpio.h> 20 #include <asm/mach-imx/gpio.h>
21 #include <asm/mach-imx/mxc_i2c.h> 21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/arch/clock.h> 22 #include <asm/arch/clock.h>
23 #include <spl.h> 23 #include <spl.h>
24 #include <power/pmic.h> 24 #include <power/pmic.h>
25 #include <usb.h> 25 #include <usb.h>
26 #include <dwc3-uboot.h> 26 #include <dwc3-uboot.h>
27 #include <dm.h> 27 #include <dm.h>
28 #include <i2c.h> 28 #include <i2c.h>
29 29
30 DECLARE_GLOBAL_DATA_PTR; 30 DECLARE_GLOBAL_DATA_PTR;
31 31
32 #define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) 32 #define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
33 33
34 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) 34 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
35 35
36 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 36 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
37 37
38 static iomux_v3_cfg_t const wdog_pads[] = { 38 static iomux_v3_cfg_t const wdog_pads[] = {
39 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), 39 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
40 }; 40 };
41 41
42 #ifdef CONFIG_FSL_QSPI 42 #ifdef CONFIG_FSL_QSPI
43 static iomux_v3_cfg_t const qspi_pads[] = { 43 static iomux_v3_cfg_t const qspi_pads[] = {
44 IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), 44 IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
45 IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), 45 IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
46 46
47 IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 47 IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
48 IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 48 IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
49 IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 49 IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
50 IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 50 IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
51 }; 51 };
52 52
53 int board_qspi_init(void) 53 int board_qspi_init(void)
54 { 54 {
55 imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); 55 imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
56 56
57 set_clk_qspi(); 57 set_clk_qspi();
58 58
59 return 0; 59 return 0;
60 } 60 }
61 #endif 61 #endif
62 62
63 static iomux_v3_cfg_t const uart_pads[] = { 63 static iomux_v3_cfg_t const uart_pads[] = {
64 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 64 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 65 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
66 }; 66 };
67 67
68 int board_early_init_f(void) 68 int board_early_init_f(void)
69 { 69 {
70 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 70 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
71 71
72 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 72 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
73 73
74 set_wdog_reset(wdog); 74 set_wdog_reset(wdog);
75 75
76 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 76 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
77 77
78 return 0; 78 return 0;
79 } 79 }
80 80
81 #ifdef CONFIG_BOARD_POSTCLK_INIT 81 #ifdef CONFIG_BOARD_POSTCLK_INIT
82 int board_postclk_init(void) 82 int board_postclk_init(void)
83 { 83 {
84 /* TODO */ 84 /* TODO */
85 return 0; 85 return 0;
86 } 86 }
87 #endif 87 #endif
88 88
89 /* layout of baseboard id */ 89 /* layout of baseboard id */
90 #define IMX8MQ_GPIO3_IO24 IMX_GPIO_NR(3, 24) //board_id[2]:2 90 #define IMX8MQ_GPIO3_IO24 IMX_GPIO_NR(3, 24) //board_id[2]:2
91 #define IMX8MQ_GPIO3_IO22 IMX_GPIO_NR(3, 22) //board_id[2]:1 91 #define IMX8MQ_GPIO3_IO22 IMX_GPIO_NR(3, 22) //board_id[2]:1
92 #define IMX8MQ_GPIO3_IO19 IMX_GPIO_NR(3, 19) //board_id[2]:0 92 #define IMX8MQ_GPIO3_IO19 IMX_GPIO_NR(3, 19) //board_id[2]:0
93 93
94 /* GPIO port description */ 94 /* GPIO port description */
95 static unsigned long imx8m_gpio_ports[] = { 95 static unsigned long imx8m_gpio_ports[] = {
96 [0] = GPIO1_BASE_ADDR, 96 [0] = GPIO1_BASE_ADDR,
97 [1] = GPIO2_BASE_ADDR, 97 [1] = GPIO2_BASE_ADDR,
98 [2] = GPIO3_BASE_ADDR, 98 [2] = GPIO3_BASE_ADDR,
99 [3] = GPIO4_BASE_ADDR, 99 [3] = GPIO4_BASE_ADDR,
100 [4] = GPIO5_BASE_ADDR, 100 [4] = GPIO5_BASE_ADDR,
101 }; 101 };
102 102
103 /* use legacy gpio operations before device model is ready. */ 103 /* use legacy gpio operations before device model is ready. */
104 static int gpio_direction_input_legacy(unsigned int gpio) 104 static int gpio_direction_input_legacy(unsigned int gpio)
105 { 105 {
106 unsigned int port; 106 unsigned int port;
107 struct gpio_regs *regs; 107 struct gpio_regs *regs;
108 u32 l; 108 u32 l;
109 109
110 port = gpio/32; 110 port = gpio/32;
111 111
112 gpio &= 0x1f; 112 gpio &= 0x1f;
113 113
114 regs = (struct gpio_regs *)imx8m_gpio_ports[port]; 114 regs = (struct gpio_regs *)imx8m_gpio_ports[port];
115 115
116 l = readl(&regs->gpio_dir); 116 l = readl(&regs->gpio_dir);
117 /* set direction as input. */ 117 /* set direction as input. */
118 l &= ~(1 << gpio); 118 l &= ~(1 << gpio);
119 writel(l, &regs->gpio_dir); 119 writel(l, &regs->gpio_dir);
120 120
121 return 0; 121 return 0;
122 } 122 }
123 123
124 static int gpio_get_value_legacy(unsigned gpio) 124 static int gpio_get_value_legacy(unsigned gpio)
125 { 125 {
126 unsigned int port; 126 unsigned int port;
127 struct gpio_regs *regs; 127 struct gpio_regs *regs;
128 u32 val; 128 u32 val;
129 129
130 port = gpio/32; 130 port = gpio/32;
131 131
132 gpio &= 0x1f; 132 gpio &= 0x1f;
133 133
134 regs = (struct gpio_regs *)imx8m_gpio_ports[port]; 134 regs = (struct gpio_regs *)imx8m_gpio_ports[port];
135 135
136 val = (readl(&regs->gpio_dr) >> gpio) & 0x01; 136 val = (readl(&regs->gpio_dr) >> gpio) & 0x01;
137 137
138 return val; 138 return val;
139 } 139 }
140 140
141 int get_imx8m_baseboard_id(void) 141 int get_imx8m_baseboard_id(void)
142 { 142 {
143 int i = 0, value = 0; 143 int i = 0, value = 0;
144 int baseboard_id; 144 int baseboard_id;
145 int pin[3]; 145 int pin[3];
146 146
147 /* initialize the pin array */ 147 /* initialize the pin array */
148 pin[0] = IMX8MQ_GPIO3_IO19; 148 pin[0] = IMX8MQ_GPIO3_IO19;
149 pin[1] = IMX8MQ_GPIO3_IO22; 149 pin[1] = IMX8MQ_GPIO3_IO22;
150 pin[2] = IMX8MQ_GPIO3_IO24; 150 pin[2] = IMX8MQ_GPIO3_IO24;
151 151
152 /* Set gpio direction as input and get the input value */ 152 /* Set gpio direction as input and get the input value */
153 baseboard_id = 0; 153 baseboard_id = 0;
154 for (i = 0; i < 3; i++) { 154 for (i = 0; i < 3; i++) {
155 gpio_direction_input_legacy(pin[i]); 155 gpio_direction_input_legacy(pin[i]);
156 if ((value = gpio_get_value_legacy(pin[i])) < 0) { 156 if ((value = gpio_get_value_legacy(pin[i])) < 0) {
157 printf("Error! Read gpio port: %d failed!\n", pin[i]); 157 printf("Error! Read gpio port: %d failed!\n", pin[i]);
158 return -1; 158 return -1;
159 } else 159 } else
160 baseboard_id |= ((value & 0x01) << i); 160 baseboard_id |= ((value & 0x01) << i);
161 } 161 }
162 162
163 return baseboard_id; 163 return baseboard_id;
164 } 164 }
165 #ifdef CONFIG_IMX_TRUSTY_OS 165 #ifdef CONFIG_IMX_TRUSTY_OS
166 int get_tee_load(ulong *load) 166 int get_tee_load(ulong *load)
167 { 167 {
168 int board_id; 168 int board_id;
169 169
170 board_id = get_imx8m_baseboard_id(); 170 board_id = get_imx8m_baseboard_id();
171 /* load TEE to the last 32M of DDR */ 171 /* load TEE to the last 32M of DDR */
172 if ((board_id == AIY_MICRON_1G) || 172 if ((board_id == AIY_MICRON_1G) ||
173 (board_id == AIY_HYNIX_1G)) { 173 (board_id == AIY_HYNIX_1G)) {
174 /* for 1G DDR board */ 174 /* for 1G DDR board */
175 *load = (ulong)TEE_LOAD_ADDR_1G; 175 *load = (ulong)TEE_LOAD_ADDR_1G;
176 } else { 176 } else {
177 /* for 3G DDR board */ 177 /* for 3G DDR board */
178 *load = (ulong)TEE_LOAD_ADDR_3G; 178 *load = (ulong)TEE_LOAD_ADDR_3G;
179 } 179 }
180 180
181 return 0; 181 return 0;
182 } 182 }
183 #endif 183 #endif
184 184
185 int dram_init(void) 185 int dram_init(void)
186 { 186 {
187 int baseboard_id; 187 int baseboard_id;
188 uint32_t ddr_size = 0; 188 uint32_t ddr_size = 0;
189 /* different boards have different DDR type, distinguish the DDR 189 /* different boards have different DDR type, distinguish the DDR
190 * type by board id. 190 * type by board id.
191 */ 191 */
192 baseboard_id = get_imx8m_baseboard_id(); 192 baseboard_id = get_imx8m_baseboard_id();
193 if ((baseboard_id == AIY_MICRON_1G) || 193 if ((baseboard_id == AIY_MICRON_1G) ||
194 (baseboard_id == AIY_HYNIX_1G)) { 194 (baseboard_id == AIY_HYNIX_1G)) {
195 /* 1G DDR size */ 195 /* 1G DDR size */
196 ddr_size = 0x40000000; 196 ddr_size = 0x40000000;
197 } else{ 197 } else{
198 /* Default to use 3G DDR size */ 198 /* Default to use 3G DDR size */
199 ddr_size = 0xc0000000; 199 ddr_size = 0xc0000000;
200 } 200 }
201 201
202 /* rom_pointer[1] contains the size of TEE occupies */ 202 /* rom_pointer[1] contains the size of TEE occupies */
203 if (rom_pointer[1]) 203 if (rom_pointer[1])
204 gd->ram_size = ddr_size - rom_pointer[1]; 204 gd->ram_size = ddr_size - rom_pointer[1];
205 else 205 else
206 gd->ram_size = ddr_size; 206 gd->ram_size = ddr_size;
207 207
208 return 0; 208 return 0;
209 } 209 }
210 210
211 #ifdef CONFIG_OF_BOARD_SETUP 211 #ifdef CONFIG_OF_BOARD_SETUP
212 int ft_board_setup(void *blob, bd_t *bd) 212 int ft_board_setup(void *blob, bd_t *bd)
213 { 213 {
214 return 0; 214 return 0;
215 } 215 }
216 #endif 216 #endif
217 217
218 #ifdef CONFIG_FEC_MXC 218 #ifdef CONFIG_FEC_MXC
219 #define FEC_RST_PAD IMX_GPIO_NR(1, 9) 219 #define FEC_RST_PAD IMX_GPIO_NR(1, 9)
220 static iomux_v3_cfg_t const fec1_rst_pads[] = { 220 static iomux_v3_cfg_t const fec1_rst_pads[] = {
221 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), 221 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
222 }; 222 };
223 223
224 static void setup_iomux_fec(void) 224 static void setup_iomux_fec(void)
225 { 225 {
226 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, 226 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
227 ARRAY_SIZE(fec1_rst_pads)); 227 ARRAY_SIZE(fec1_rst_pads));
228 228
229 gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); 229 gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
230 gpio_direction_output(IMX_GPIO_NR(1, 9), 0); 230 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
231 udelay(500); 231 udelay(500);
232 gpio_direction_output(IMX_GPIO_NR(1, 9), 1); 232 gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
233 } 233 }
234 234
235 static int setup_fec(void) 235 static int setup_fec(void)
236 { 236 {
237 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 237 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
238 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 238 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
239 239
240 setup_iomux_fec(); 240 setup_iomux_fec();
241 241
242 /* Use 125M anatop REF_CLK1 for ENET1, not from external */ 242 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
243 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 243 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
244 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); 244 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
245 return set_clk_enet(ENET_125MHZ); 245 return set_clk_enet(ENET_125MHZ);
246 } 246 }
247 247
248 248
249 int board_phy_config(struct phy_device *phydev) 249 int board_phy_config(struct phy_device *phydev)
250 { 250 {
251 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 251 /* enable rgmii rxc skew and phy mode select to RGMII copper */
252 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 252 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
253 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 253 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
254 254
255 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 255 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
256 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 256 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
257 257
258 if (phydev->drv->config) 258 if (phydev->drv->config)
259 phydev->drv->config(phydev); 259 phydev->drv->config(phydev);
260 return 0; 260 return 0;
261 } 261 }
262 #endif 262 #endif
263 263
264 #ifdef CONFIG_USB_DWC3 264 #ifdef CONFIG_USB_DWC3
265 265
266 #define USB_PHY_CTRL0 0xF0040 266 #define USB_PHY_CTRL0 0xF0040
267 #define USB_PHY_CTRL0_REF_SSP_EN BIT(2) 267 #define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
268 268
269 #define USB_PHY_CTRL1 0xF0044 269 #define USB_PHY_CTRL1 0xF0044
270 #define USB_PHY_CTRL1_RESET BIT(0) 270 #define USB_PHY_CTRL1_RESET BIT(0)
271 #define USB_PHY_CTRL1_COMMONONN BIT(1) 271 #define USB_PHY_CTRL1_COMMONONN BIT(1)
272 #define USB_PHY_CTRL1_ATERESET BIT(3) 272 #define USB_PHY_CTRL1_ATERESET BIT(3)
273 #define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) 273 #define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
274 #define USB_PHY_CTRL1_VDATDETENB0 BIT(20) 274 #define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
275 275
276 #define USB_PHY_CTRL2 0xF0048 276 #define USB_PHY_CTRL2 0xF0048
277 #define USB_PHY_CTRL2_TXENABLEN0 BIT(8) 277 #define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
278 278
279 #define PTN5150A_BUS 2 279 #define PTN5150A_BUS 2
280 #define PTN5150A_ADDR 0x3D 280 #define PTN5150A_ADDR 0x3D
281 #define PTN5150A_CONTROL 0x2 281 #define PTN5150A_CONTROL 0x2
282 #define PTN5150A_CONTROL_PORT_MASK 0x6 282 #define PTN5150A_CONTROL_PORT_MASK 0x6
283 283
284 static struct dwc3_device dwc3_device_data = { 284 static struct dwc3_device dwc3_device_data = {
285 #ifdef CONFIG_SPL_BUILD 285 #ifdef CONFIG_SPL_BUILD
286 .maximum_speed = USB_SPEED_HIGH, 286 .maximum_speed = USB_SPEED_HIGH,
287 #else 287 #else
288 .maximum_speed = USB_SPEED_SUPER, 288 .maximum_speed = USB_SPEED_SUPER,
289 #endif 289 #endif
290 .base = USB1_BASE_ADDR, 290 .base = USB1_BASE_ADDR,
291 .dr_mode = USB_DR_MODE_PERIPHERAL, 291 .dr_mode = USB_DR_MODE_PERIPHERAL,
292 .index = 0, 292 .index = 0,
293 .power_down_scale = 2, 293 .power_down_scale = 2,
294 }; 294 };
295 295
296 int usb_gadget_handle_interrupts(void) 296 int usb_gadget_handle_interrupts(void)
297 { 297 {
298 dwc3_uboot_handle_interrupt(0); 298 dwc3_uboot_handle_interrupt(0);
299 return 0; 299 return 0;
300 } 300 }
301 301
302 static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) 302 static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
303 { 303 {
304 u32 RegData; 304 u32 RegData;
305 305
306 RegData = readl(dwc3->base + USB_PHY_CTRL1); 306 RegData = readl(dwc3->base + USB_PHY_CTRL1);
307 RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | 307 RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
308 USB_PHY_CTRL1_COMMONONN); 308 USB_PHY_CTRL1_COMMONONN);
309 RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; 309 RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
310 writel(RegData, dwc3->base + USB_PHY_CTRL1); 310 writel(RegData, dwc3->base + USB_PHY_CTRL1);
311 311
312 RegData = readl(dwc3->base + USB_PHY_CTRL0); 312 RegData = readl(dwc3->base + USB_PHY_CTRL0);
313 RegData |= USB_PHY_CTRL0_REF_SSP_EN; 313 RegData |= USB_PHY_CTRL0_REF_SSP_EN;
314 writel(RegData, dwc3->base + USB_PHY_CTRL0); 314 writel(RegData, dwc3->base + USB_PHY_CTRL0);
315 315
316 RegData = readl(dwc3->base + USB_PHY_CTRL2); 316 RegData = readl(dwc3->base + USB_PHY_CTRL2);
317 RegData |= USB_PHY_CTRL2_TXENABLEN0; 317 RegData |= USB_PHY_CTRL2_TXENABLEN0;
318 writel(RegData, dwc3->base + USB_PHY_CTRL2); 318 writel(RegData, dwc3->base + USB_PHY_CTRL2);
319 319
320 RegData = readl(dwc3->base + USB_PHY_CTRL1); 320 RegData = readl(dwc3->base + USB_PHY_CTRL1);
321 RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); 321 RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
322 writel(RegData, dwc3->base + USB_PHY_CTRL1); 322 writel(RegData, dwc3->base + USB_PHY_CTRL1);
323 } 323 }
324 324
325 #ifndef CONFIG_SPL_BUILD 325 #ifndef CONFIG_SPL_BUILD
326 static void configure_cc_switch() { 326 static void configure_cc_switch() {
327 uint8_t value; 327 uint8_t value;
328 int ret; 328 int ret;
329 struct udevice *bus, *dev; 329 struct udevice *bus, *dev;
330 330
331 ret = uclass_get_device_by_seq(UCLASS_I2C, PTN5150A_BUS, &bus); 331 ret = uclass_get_device_by_seq(UCLASS_I2C, PTN5150A_BUS, &bus);
332 if (ret) { 332 if (ret) {
333 printf("%s: No bus %d\n", __func__, PTN5150A_BUS); 333 printf("%s: No bus %d\n", __func__, PTN5150A_BUS);
334 return; 334 return;
335 } 335 }
336 336
337 ret = dm_i2c_probe(bus, PTN5150A_ADDR, 0, &dev); 337 ret = dm_i2c_probe(bus, PTN5150A_ADDR, 0, &dev);
338 if (ret) { 338 if (ret) {
339 printf("%s: Can't find device id=0x%x, on bus %d\n", 339 printf("%s: Can't find device id=0x%x, on bus %d\n",
340 __func__, PTN5150A_ADDR, PTN5150A_BUS); 340 __func__, PTN5150A_ADDR, PTN5150A_BUS);
341 return; 341 return;
342 } 342 }
343 343
344 if (dm_i2c_read(dev, PTN5150A_CONTROL, &value, 1)) { 344 if (dm_i2c_read(dev, PTN5150A_CONTROL, &value, 1)) {
345 printf("Unable to configure USB switch"); 345 printf("Unable to configure USB switch");
346 return; 346 return;
347 } 347 }
348 348
349 value &= ~PTN5150A_CONTROL_PORT_MASK; 349 value &= ~PTN5150A_CONTROL_PORT_MASK;
350 if (dm_i2c_write(dev, PTN5150A_CONTROL, &value, 1)) { 350 if (dm_i2c_write(dev, PTN5150A_CONTROL, &value, 1)) {
351 printf("Unable to configure USB switch"); 351 printf("Unable to configure USB switch");
352 return; 352 return;
353 } 353 }
354 printf("Configured USB Switch for UFP\n"); 354 printf("Configured USB Switch for UFP\n");
355 } 355 }
356 #endif 356 #endif
357 #endif 357 #endif
358 358
359 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) 359 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
360 int board_usb_init(int index, enum usb_init_type init) 360 int board_usb_init(int index, enum usb_init_type init)
361 { 361 {
362 imx8m_usb_power(index, true); 362 imx8m_usb_power(index, true);
363 363
364 #ifndef CONFIG_SPL_BUILD 364 #ifndef CONFIG_SPL_BUILD
365 /* Explicitly set USB switch to UFP (device) to ensure proper 365 /* Explicitly set USB switch to UFP (device) to ensure proper
366 *fastboot operation on type-C ports. */ 366 *fastboot operation on type-C ports. */
367 configure_cc_switch(); 367 configure_cc_switch();
368 #endif 368 #endif
369 369
370 if (index == 0 && init == USB_INIT_DEVICE) { 370 if (index == 0 && init == USB_INIT_DEVICE) {
371 dwc3_nxp_usb_phy_init(&dwc3_device_data); 371 dwc3_nxp_usb_phy_init(&dwc3_device_data);
372 return dwc3_uboot_init(&dwc3_device_data); 372 return dwc3_uboot_init(&dwc3_device_data);
373 } 373 }
374 374
375 return 0; 375 return 0;
376 } 376 }
377 377
378 int board_usb_cleanup(int index, enum usb_init_type init) 378 int board_usb_cleanup(int index, enum usb_init_type init)
379 { 379 {
380 if (index == 0 && init == USB_INIT_DEVICE) { 380 if (index == 0 && init == USB_INIT_DEVICE) {
381 dwc3_uboot_exit(index); 381 dwc3_uboot_exit(index);
382 } 382 }
383 383
384 imx8m_usb_power(index, false); 384 imx8m_usb_power(index, false);
385 385
386 return 0; 386 return 0;
387 } 387 }
388 #endif 388 #endif
389 389
390 int board_init(void) 390 int board_init(void)
391 { 391 {
392 board_qspi_init(); 392 board_qspi_init();
393 393
394 #ifdef CONFIG_FEC_MXC 394 #ifdef CONFIG_FEC_MXC
395 setup_fec(); 395 setup_fec();
396 #endif 396 #endif
397 397
398 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) 398 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
399 init_usb_clk(); 399 init_usb_clk();
400 #endif 400 #endif
401 return 0; 401 return 0;
402 } 402 }
403 403
404 int board_mmc_get_env_dev(int devno) 404 int board_mmc_get_env_dev(int devno)
405 { 405 {
406 return devno; 406 return devno;
407 } 407 }
408 408
409 int board_late_init(void) 409 int board_late_init(void)
410 { 410 {
411 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 411 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
412 env_set("board_name", "Phanbell"); 412 env_set("board_name", "Phanbell");
413 env_set("board_rev", "iMX8MQ"); 413 env_set("board_rev", "iMX8MQ");
414 #endif 414 #endif
415 415
416 #ifdef CONFIG_ENV_IS_IN_MMC 416 #ifdef CONFIG_ENV_IS_IN_MMC
417 board_late_mmc_env_init(); 417 board_late_mmc_env_init();
418 #endif 418 #endif
419 int baseboard_id; 419 int baseboard_id;
420 baseboard_id = get_imx8m_baseboard_id(); 420 baseboard_id = get_imx8m_baseboard_id();
421 if ((baseboard_id == AIY_MICRON_1G) || 421 if ((baseboard_id == AIY_MICRON_1G) ||
422 (baseboard_id == AIY_HYNIX_1G)) { 422 (baseboard_id == AIY_HYNIX_1G)) {
423 /* 1G DDR size */ 423 /* 1G DDR size */
424 env_set("bootargs_ram_capacity", "cma=296M galcore.contiguousSize=8388608"); 424 env_set("bootargs_ram_capacity", "cma=296M galcore.contiguousSize=33554432");
425 } else { 425 } else {
426 /* 3G DDR size */ 426 /* 3G DDR size */
427 env_set("bootargs_ram_capacity", "cma=384M"); 427 env_set("bootargs_ram_capacity", "cma=384M");
428 } 428 }
429 429
430 return 0; 430 return 0;
431 } 431 }
432 432
433 #ifdef CONFIG_FSL_FASTBOOT 433 #ifdef CONFIG_FSL_FASTBOOT
434 #ifdef CONFIG_ANDROID_RECOVERY 434 #ifdef CONFIG_ANDROID_RECOVERY
435 int is_recovery_key_pressing(void) 435 int is_recovery_key_pressing(void)
436 { 436 {
437 return 0; /*TODO*/ 437 return 0; /*TODO*/
438 } 438 }
439 #endif /*CONFIG_ANDROID_RECOVERY*/ 439 #endif /*CONFIG_ANDROID_RECOVERY*/
440 #endif /*CONFIG_FSL_FASTBOOT*/ 440 #endif /*CONFIG_FSL_FASTBOOT*/
441 441