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Commit 8a573022c38da9ecc749acbc60556a8e8bd41996

Authored by Andrew Gabbasov
Committed by Pantelis Antoniou
1 parent fb823981c5
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mmc: fsl_esdhc: add controller reset in case of data related errors too 

The controller reset is performed now if command error occurs.
This commit adds the reset for the case of data related errors too.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>

Showing 1 changed file with 36 additions and 27 deletions Inline Diff

drivers/mmc/fsl_esdhc.c
Diff comments   View file @ 8a57302
1 /* 1 /*
2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
3 * Andy Fleming 3 * Andy Fleming
4 * 4 *
5 * Based vaguely on the pxa mmc code: 5 * Based vaguely on the pxa mmc code:
6 * (C) Copyright 2003 6 * (C) Copyright 2003
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8 * 8 *
9 * SPDX-License-Identifier: GPL-2.0+ 9 * SPDX-License-Identifier: GPL-2.0+
10 */ 10 */
11 11
12 #include <config.h> 12 #include <config.h>
13 #include <common.h> 13 #include <common.h>
14 #include <command.h> 14 #include <command.h>
15 #include <hwconfig.h> 15 #include <hwconfig.h>
16 #include <mmc.h> 16 #include <mmc.h>
17 #include <part.h> 17 #include <part.h>
18 #include <malloc.h> 18 #include <malloc.h>
19 #include <mmc.h> 19 #include <mmc.h>
20 #include <fsl_esdhc.h> 20 #include <fsl_esdhc.h>
21 #include <fdt_support.h> 21 #include <fdt_support.h>
22 #include <asm/io.h> 22 #include <asm/io.h>
23 23
24 DECLARE_GLOBAL_DATA_PTR; 24 DECLARE_GLOBAL_DATA_PTR;
25 25
26 struct fsl_esdhc { 26 struct fsl_esdhc {
27 uint dsaddr; /* SDMA system address register */ 27 uint dsaddr; /* SDMA system address register */
28 uint blkattr; /* Block attributes register */ 28 uint blkattr; /* Block attributes register */
29 uint cmdarg; /* Command argument register */ 29 uint cmdarg; /* Command argument register */
30 uint xfertyp; /* Transfer type register */ 30 uint xfertyp; /* Transfer type register */
31 uint cmdrsp0; /* Command response 0 register */ 31 uint cmdrsp0; /* Command response 0 register */
32 uint cmdrsp1; /* Command response 1 register */ 32 uint cmdrsp1; /* Command response 1 register */
33 uint cmdrsp2; /* Command response 2 register */ 33 uint cmdrsp2; /* Command response 2 register */
34 uint cmdrsp3; /* Command response 3 register */ 34 uint cmdrsp3; /* Command response 3 register */
35 uint datport; /* Buffer data port register */ 35 uint datport; /* Buffer data port register */
36 uint prsstat; /* Present state register */ 36 uint prsstat; /* Present state register */
37 uint proctl; /* Protocol control register */ 37 uint proctl; /* Protocol control register */
38 uint sysctl; /* System Control Register */ 38 uint sysctl; /* System Control Register */
39 uint irqstat; /* Interrupt status register */ 39 uint irqstat; /* Interrupt status register */
40 uint irqstaten; /* Interrupt status enable register */ 40 uint irqstaten; /* Interrupt status enable register */
41 uint irqsigen; /* Interrupt signal enable register */ 41 uint irqsigen; /* Interrupt signal enable register */
42 uint autoc12err; /* Auto CMD error status register */ 42 uint autoc12err; /* Auto CMD error status register */
43 uint hostcapblt; /* Host controller capabilities register */ 43 uint hostcapblt; /* Host controller capabilities register */
44 uint wml; /* Watermark level register */ 44 uint wml; /* Watermark level register */
45 uint mixctrl; /* For USDHC */ 45 uint mixctrl; /* For USDHC */
46 char reserved1[4]; /* reserved */ 46 char reserved1[4]; /* reserved */
47 uint fevt; /* Force event register */ 47 uint fevt; /* Force event register */
48 uint admaes; /* ADMA error status register */ 48 uint admaes; /* ADMA error status register */
49 uint adsaddr; /* ADMA system address register */ 49 uint adsaddr; /* ADMA system address register */
50 char reserved2[160]; /* reserved */ 50 char reserved2[160]; /* reserved */
51 uint hostver; /* Host controller version register */ 51 uint hostver; /* Host controller version register */
52 char reserved3[4]; /* reserved */ 52 char reserved3[4]; /* reserved */
53 uint dmaerraddr; /* DMA error address register */ 53 uint dmaerraddr; /* DMA error address register */
54 char reserved4[4]; /* reserved */ 54 char reserved4[4]; /* reserved */
55 uint dmaerrattr; /* DMA error attribute register */ 55 uint dmaerrattr; /* DMA error attribute register */
56 char reserved5[4]; /* reserved */ 56 char reserved5[4]; /* reserved */
57 uint hostcapblt2; /* Host controller capabilities register 2 */ 57 uint hostcapblt2; /* Host controller capabilities register 2 */
58 char reserved6[8]; /* reserved */ 58 char reserved6[8]; /* reserved */
59 uint tcr; /* Tuning control register */ 59 uint tcr; /* Tuning control register */
60 char reserved7[28]; /* reserved */ 60 char reserved7[28]; /* reserved */
61 uint sddirctl; /* SD direction control register */ 61 uint sddirctl; /* SD direction control register */
62 char reserved8[712]; /* reserved */ 62 char reserved8[712]; /* reserved */
63 uint scr; /* eSDHC control register */ 63 uint scr; /* eSDHC control register */
64 }; 64 };
65 65
66 /* Return the XFERTYP flags for a given command and data packet */ 66 /* Return the XFERTYP flags for a given command and data packet */
67 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 67 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
68 { 68 {
69 uint xfertyp = 0; 69 uint xfertyp = 0;
70 70
71 if (data) { 71 if (data) {
72 xfertyp |= XFERTYP_DPSEL; 72 xfertyp |= XFERTYP_DPSEL;
73 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 73 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
74 xfertyp |= XFERTYP_DMAEN; 74 xfertyp |= XFERTYP_DMAEN;
75 #endif 75 #endif
76 if (data->blocks > 1) { 76 if (data->blocks > 1) {
77 xfertyp |= XFERTYP_MSBSEL; 77 xfertyp |= XFERTYP_MSBSEL;
78 xfertyp |= XFERTYP_BCEN; 78 xfertyp |= XFERTYP_BCEN;
79 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 79 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
80 xfertyp |= XFERTYP_AC12EN; 80 xfertyp |= XFERTYP_AC12EN;
81 #endif 81 #endif
82 } 82 }
83 83
84 if (data->flags & MMC_DATA_READ) 84 if (data->flags & MMC_DATA_READ)
85 xfertyp |= XFERTYP_DTDSEL; 85 xfertyp |= XFERTYP_DTDSEL;
86 } 86 }
87 87
88 if (cmd->resp_type & MMC_RSP_CRC) 88 if (cmd->resp_type & MMC_RSP_CRC)
89 xfertyp |= XFERTYP_CCCEN; 89 xfertyp |= XFERTYP_CCCEN;
90 if (cmd->resp_type & MMC_RSP_OPCODE) 90 if (cmd->resp_type & MMC_RSP_OPCODE)
91 xfertyp |= XFERTYP_CICEN; 91 xfertyp |= XFERTYP_CICEN;
92 if (cmd->resp_type & MMC_RSP_136) 92 if (cmd->resp_type & MMC_RSP_136)
93 xfertyp |= XFERTYP_RSPTYP_136; 93 xfertyp |= XFERTYP_RSPTYP_136;
94 else if (cmd->resp_type & MMC_RSP_BUSY) 94 else if (cmd->resp_type & MMC_RSP_BUSY)
95 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 95 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
96 else if (cmd->resp_type & MMC_RSP_PRESENT) 96 else if (cmd->resp_type & MMC_RSP_PRESENT)
97 xfertyp |= XFERTYP_RSPTYP_48; 97 xfertyp |= XFERTYP_RSPTYP_48;
98 98
99 #if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) 99 #if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
100 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 100 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
101 xfertyp |= XFERTYP_CMDTYP_ABORT; 101 xfertyp |= XFERTYP_CMDTYP_ABORT;
102 #endif 102 #endif
103 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 103 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
104 } 104 }
105 105
106 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 106 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
107 /* 107 /*
108 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 108 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
109 */ 109 */
110 static void 110 static void
111 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 111 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
112 { 112 {
113 struct fsl_esdhc_cfg *cfg = mmc->priv; 113 struct fsl_esdhc_cfg *cfg = mmc->priv;
114 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 114 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
115 uint blocks; 115 uint blocks;
116 char *buffer; 116 char *buffer;
117 uint databuf; 117 uint databuf;
118 uint size; 118 uint size;
119 uint irqstat; 119 uint irqstat;
120 uint timeout; 120 uint timeout;
121 121
122 if (data->flags & MMC_DATA_READ) { 122 if (data->flags & MMC_DATA_READ) {
123 blocks = data->blocks; 123 blocks = data->blocks;
124 buffer = data->dest; 124 buffer = data->dest;
125 while (blocks) { 125 while (blocks) {
126 timeout = PIO_TIMEOUT; 126 timeout = PIO_TIMEOUT;
127 size = data->blocksize; 127 size = data->blocksize;
128 irqstat = esdhc_read32(&regs->irqstat); 128 irqstat = esdhc_read32(&regs->irqstat);
129 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN) 129 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
130 && --timeout); 130 && --timeout);
131 if (timeout <= 0) { 131 if (timeout <= 0) {
132 printf("\nData Read Failed in PIO Mode."); 132 printf("\nData Read Failed in PIO Mode.");
133 return; 133 return;
134 } 134 }
135 while (size && (!(irqstat & IRQSTAT_TC))) { 135 while (size && (!(irqstat & IRQSTAT_TC))) {
136 udelay(100); /* Wait before last byte transfer complete */ 136 udelay(100); /* Wait before last byte transfer complete */
137 irqstat = esdhc_read32(&regs->irqstat); 137 irqstat = esdhc_read32(&regs->irqstat);
138 databuf = in_le32(&regs->datport); 138 databuf = in_le32(&regs->datport);
139 *((uint *)buffer) = databuf; 139 *((uint *)buffer) = databuf;
140 buffer += 4; 140 buffer += 4;
141 size -= 4; 141 size -= 4;
142 } 142 }
143 blocks--; 143 blocks--;
144 } 144 }
145 } else { 145 } else {
146 blocks = data->blocks; 146 blocks = data->blocks;
147 buffer = (char *)data->src; 147 buffer = (char *)data->src;
148 while (blocks) { 148 while (blocks) {
149 timeout = PIO_TIMEOUT; 149 timeout = PIO_TIMEOUT;
150 size = data->blocksize; 150 size = data->blocksize;
151 irqstat = esdhc_read32(&regs->irqstat); 151 irqstat = esdhc_read32(&regs->irqstat);
152 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN) 152 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
153 && --timeout); 153 && --timeout);
154 if (timeout <= 0) { 154 if (timeout <= 0) {
155 printf("\nData Write Failed in PIO Mode."); 155 printf("\nData Write Failed in PIO Mode.");
156 return; 156 return;
157 } 157 }
158 while (size && (!(irqstat & IRQSTAT_TC))) { 158 while (size && (!(irqstat & IRQSTAT_TC))) {
159 udelay(100); /* Wait before last byte transfer complete */ 159 udelay(100); /* Wait before last byte transfer complete */
160 databuf = *((uint *)buffer); 160 databuf = *((uint *)buffer);
161 buffer += 4; 161 buffer += 4;
162 size -= 4; 162 size -= 4;
163 irqstat = esdhc_read32(&regs->irqstat); 163 irqstat = esdhc_read32(&regs->irqstat);
164 out_le32(&regs->datport, databuf); 164 out_le32(&regs->datport, databuf);
165 } 165 }
166 blocks--; 166 blocks--;
167 } 167 }
168 } 168 }
169 } 169 }
170 #endif 170 #endif
171 171
172 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 172 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
173 { 173 {
174 int timeout; 174 int timeout;
175 struct fsl_esdhc_cfg *cfg = mmc->priv; 175 struct fsl_esdhc_cfg *cfg = mmc->priv;
176 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 176 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
177 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 177 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
178 uint wml_value; 178 uint wml_value;
179 179
180 wml_value = data->blocksize/4; 180 wml_value = data->blocksize/4;
181 181
182 if (data->flags & MMC_DATA_READ) { 182 if (data->flags & MMC_DATA_READ) {
183 if (wml_value > WML_RD_WML_MAX) 183 if (wml_value > WML_RD_WML_MAX)
184 wml_value = WML_RD_WML_MAX_VAL; 184 wml_value = WML_RD_WML_MAX_VAL;
185 185
186 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value); 186 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
187 esdhc_write32(&regs->dsaddr, (u32)data->dest); 187 esdhc_write32(&regs->dsaddr, (u32)data->dest);
188 } else { 188 } else {
189 flush_dcache_range((ulong)data->src, 189 flush_dcache_range((ulong)data->src,
190 (ulong)data->src+data->blocks 190 (ulong)data->src+data->blocks
191 *data->blocksize); 191 *data->blocksize);
192 192
193 if (wml_value > WML_WR_WML_MAX) 193 if (wml_value > WML_WR_WML_MAX)
194 wml_value = WML_WR_WML_MAX_VAL; 194 wml_value = WML_WR_WML_MAX_VAL;
195 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) { 195 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
196 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 196 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
197 return TIMEOUT; 197 return TIMEOUT;
198 } 198 }
199 199
200 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK, 200 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
201 wml_value << 16); 201 wml_value << 16);
202 esdhc_write32(&regs->dsaddr, (u32)data->src); 202 esdhc_write32(&regs->dsaddr, (u32)data->src);
203 } 203 }
204 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 204 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
205 if (!(data->flags & MMC_DATA_READ)) { 205 if (!(data->flags & MMC_DATA_READ)) {
206 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) { 206 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
207 printf("\nThe SD card is locked. " 207 printf("\nThe SD card is locked. "
208 "Can not write to a locked card.\n\n"); 208 "Can not write to a locked card.\n\n");
209 return TIMEOUT; 209 return TIMEOUT;
210 } 210 }
211 esdhc_write32(&regs->dsaddr, (u32)data->src); 211 esdhc_write32(&regs->dsaddr, (u32)data->src);
212 } else 212 } else
213 esdhc_write32(&regs->dsaddr, (u32)data->dest); 213 esdhc_write32(&regs->dsaddr, (u32)data->dest);
214 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 214 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
215 215
216 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize); 216 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
217 217
218 /* Calculate the timeout period for data transactions */ 218 /* Calculate the timeout period for data transactions */
219 /* 219 /*
220 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 220 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
221 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 221 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
222 * So, Number of SD Clock cycles for 0.25sec should be minimum 222 * So, Number of SD Clock cycles for 0.25sec should be minimum
223 * (SD Clock/sec * 0.25 sec) SD Clock cycles 223 * (SD Clock/sec * 0.25 sec) SD Clock cycles
224 * = (mmc->clock * 1/4) SD Clock cycles 224 * = (mmc->clock * 1/4) SD Clock cycles
225 * As 1) >= 2) 225 * As 1) >= 2)
226 * => (2^(timeout+13)) >= mmc->clock * 1/4 226 * => (2^(timeout+13)) >= mmc->clock * 1/4
227 * Taking log2 both the sides 227 * Taking log2 both the sides
228 * => timeout + 13 >= log2(mmc->clock/4) 228 * => timeout + 13 >= log2(mmc->clock/4)
229 * Rounding up to next power of 2 229 * Rounding up to next power of 2
230 * => timeout + 13 = log2(mmc->clock/4) + 1 230 * => timeout + 13 = log2(mmc->clock/4) + 1
231 * => timeout + 13 = fls(mmc->clock/4) 231 * => timeout + 13 = fls(mmc->clock/4)
232 */ 232 */
233 timeout = fls(mmc->clock/4); 233 timeout = fls(mmc->clock/4);
234 timeout -= 13; 234 timeout -= 13;
235 235
236 if (timeout > 14) 236 if (timeout > 14)
237 timeout = 14; 237 timeout = 14;
238 238
239 if (timeout < 0) 239 if (timeout < 0)
240 timeout = 0; 240 timeout = 0;
241 241
242 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 242 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
243 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 243 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
244 timeout++; 244 timeout++;
245 #endif 245 #endif
246 246
247 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 247 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
248 248
249 return 0; 249 return 0;
250 } 250 }
251 251
252 static void check_and_invalidate_dcache_range 252 static void check_and_invalidate_dcache_range
253 (struct mmc_cmd *cmd, 253 (struct mmc_cmd *cmd,
254 struct mmc_data *data) { 254 struct mmc_data *data) {
255 unsigned start = (unsigned)data->dest ; 255 unsigned start = (unsigned)data->dest ;
256 unsigned size = roundup(ARCH_DMA_MINALIGN, 256 unsigned size = roundup(ARCH_DMA_MINALIGN,
257 data->blocks*data->blocksize); 257 data->blocks*data->blocksize);
258 unsigned end = start+size ; 258 unsigned end = start+size ;
259 invalidate_dcache_range(start, end); 259 invalidate_dcache_range(start, end);
260 } 260 }
261 /* 261 /*
262 * Sends a command out on the bus. Takes the mmc pointer, 262 * Sends a command out on the bus. Takes the mmc pointer,
263 * a command pointer, and an optional data pointer. 263 * a command pointer, and an optional data pointer.
264 */ 264 */
265 static int 265 static int
266 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 266 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
267 { 267 {
268 int err = 0;
268 uint xfertyp; 269 uint xfertyp;
269 uint irqstat; 270 uint irqstat;
270 struct fsl_esdhc_cfg *cfg = mmc->priv; 271 struct fsl_esdhc_cfg *cfg = mmc->priv;
271 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 272 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
272 273
273 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 274 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
274 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 275 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
275 return 0; 276 return 0;
276 #endif 277 #endif
277 278
278 esdhc_write32(&regs->irqstat, -1); 279 esdhc_write32(&regs->irqstat, -1);
279 280
280 sync(); 281 sync();
281 282
282 /* Wait for the bus to be idle */ 283 /* Wait for the bus to be idle */
283 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) || 284 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
284 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB)) 285 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
285 ; 286 ;
286 287
287 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA) 288 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
288 ; 289 ;
289 290
290 /* Wait at least 8 SD clock cycles before the next command */ 291 /* Wait at least 8 SD clock cycles before the next command */
291 /* 292 /*
292 * Note: This is way more than 8 cycles, but 1ms seems to 293 * Note: This is way more than 8 cycles, but 1ms seems to
293 * resolve timing issues with some cards 294 * resolve timing issues with some cards
294 */ 295 */
295 udelay(1000); 296 udelay(1000);
296 297
297 /* Set up for a data transfer if we have one */ 298 /* Set up for a data transfer if we have one */
298 if (data) { 299 if (data) {
299 int err;
300
301 err = esdhc_setup_data(mmc, data); 300 err = esdhc_setup_data(mmc, data);
302 if(err) 301 if(err)
303 return err; 302 return err;
304 } 303 }
305 304
306 /* Figure out the transfer arguments */ 305 /* Figure out the transfer arguments */
307 xfertyp = esdhc_xfertyp(cmd, data); 306 xfertyp = esdhc_xfertyp(cmd, data);
308 307
309 /* Mask all irqs */ 308 /* Mask all irqs */
310 esdhc_write32(&regs->irqsigen, 0); 309 esdhc_write32(&regs->irqsigen, 0);
311 310
312 /* Send the command */ 311 /* Send the command */
313 esdhc_write32(&regs->cmdarg, cmd->cmdarg); 312 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
314 #if defined(CONFIG_FSL_USDHC) 313 #if defined(CONFIG_FSL_USDHC)
315 esdhc_write32(&regs->mixctrl, 314 esdhc_write32(&regs->mixctrl,
316 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); 315 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
317 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000); 316 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
318 #else 317 #else
319 esdhc_write32(&regs->xfertyp, xfertyp); 318 esdhc_write32(&regs->xfertyp, xfertyp);
320 #endif 319 #endif
321 320
322 /* Wait for the command to complete */ 321 /* Wait for the command to complete */
323 while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 322 while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
324 ; 323 ;
325 324
326 irqstat = esdhc_read32(&regs->irqstat); 325 irqstat = esdhc_read32(&regs->irqstat);
327 326
328 /* Reset CMD and DATA portions on error */ 327 if (irqstat & CMD_ERR) {
329 if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { 328 err = COMM_ERR;
330 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) | 329 goto out;
331 SYSCTL_RSTC); 330 }
332 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
333 ;
334 331
335 if (data) { 332 if (irqstat & IRQSTAT_CTOE) {
336 esdhc_write32(&regs->sysctl, 333 err = TIMEOUT;
337 esdhc_read32(&regs->sysctl) | 334 goto out;
338 SYSCTL_RSTD);
339 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
340 ;
341 }
342 } 335 }
343 336
344 if (irqstat & CMD_ERR)
345 return COMM_ERR;
346
347 if (irqstat & IRQSTAT_CTOE)
348 return TIMEOUT;
349
350 /* Workaround for ESDHC errata ENGcm03648 */ 337 /* Workaround for ESDHC errata ENGcm03648 */
351 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 338 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
352 int timeout = 2500; 339 int timeout = 2500;
353 340
354 /* Poll on DATA0 line for cmd with busy signal for 250 ms */ 341 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
355 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) & 342 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
356 PRSSTAT_DAT0)) { 343 PRSSTAT_DAT0)) {
357 udelay(100); 344 udelay(100);
358 timeout--; 345 timeout--;
359 } 346 }
360 347
361 if (timeout <= 0) { 348 if (timeout <= 0) {
362 printf("Timeout waiting for DAT0 to go high!\n"); 349 printf("Timeout waiting for DAT0 to go high!\n");
363 return TIMEOUT; 350 err = TIMEOUT;
351 goto out;
364 } 352 }
365 } 353 }
366 354
367 /* Copy the response to the response buffer */ 355 /* Copy the response to the response buffer */
368 if (cmd->resp_type & MMC_RSP_136) { 356 if (cmd->resp_type & MMC_RSP_136) {
369 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 357 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
370 358
371 cmdrsp3 = esdhc_read32(&regs->cmdrsp3); 359 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
372 cmdrsp2 = esdhc_read32(&regs->cmdrsp2); 360 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
373 cmdrsp1 = esdhc_read32(&regs->cmdrsp1); 361 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
374 cmdrsp0 = esdhc_read32(&regs->cmdrsp0); 362 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
375 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 363 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
376 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 364 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
377 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 365 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
378 cmd->response[3] = (cmdrsp0 << 8); 366 cmd->response[3] = (cmdrsp0 << 8);
379 } else 367 } else
380 cmd->response[0] = esdhc_read32(&regs->cmdrsp0); 368 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
381 369
382 /* Wait until all of the blocks are transferred */ 370 /* Wait until all of the blocks are transferred */
383 if (data) { 371 if (data) {
384 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 372 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
385 esdhc_pio_read_write(mmc, data); 373 esdhc_pio_read_write(mmc, data);
386 #else 374 #else
387 do { 375 do {
388 irqstat = esdhc_read32(&regs->irqstat); 376 irqstat = esdhc_read32(&regs->irqstat);
389 377
390 if (irqstat & IRQSTAT_DTOE) 378 if (irqstat & IRQSTAT_DTOE) {
391 return TIMEOUT; 379 err = TIMEOUT;
380 goto out;
381 }
392 382
393 if (irqstat & DATA_ERR) 383 if (irqstat & DATA_ERR) {
394 return COMM_ERR; 384 err = COMM_ERR;
385 goto out;
386 }
395 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 387 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
396 #endif 388 #endif
397 if (data->flags & MMC_DATA_READ) 389 if (data->flags & MMC_DATA_READ)
398 check_and_invalidate_dcache_range(cmd, data); 390 check_and_invalidate_dcache_range(cmd, data);
399 } 391 }
400 392
393 out:
394 /* Reset CMD and DATA portions on error */
395 if (err) {
396 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
397 SYSCTL_RSTC);
398 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
399 ;
400
401 if (data) {
402 esdhc_write32(&regs->sysctl,
403 esdhc_read32(&regs->sysctl) |
404 SYSCTL_RSTD);
405 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
406 ;
407 }
408 }
409
401 esdhc_write32(&regs->irqstat, -1); 410 esdhc_write32(&regs->irqstat, -1);
402 411
403 return 0; 412 return err;
404 } 413 }
405 414
406 static void set_sysctl(struct mmc *mmc, uint clock) 415 static void set_sysctl(struct mmc *mmc, uint clock)
407 { 416 {
408 int div, pre_div; 417 int div, pre_div;
409 struct fsl_esdhc_cfg *cfg = mmc->priv; 418 struct fsl_esdhc_cfg *cfg = mmc->priv;
410 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 419 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
411 int sdhc_clk = cfg->sdhc_clk; 420 int sdhc_clk = cfg->sdhc_clk;
412 uint clk; 421 uint clk;
413 422
414 if (clock < mmc->cfg->f_min) 423 if (clock < mmc->cfg->f_min)
415 clock = mmc->cfg->f_min; 424 clock = mmc->cfg->f_min;
416 425
417 if (sdhc_clk / 16 > clock) { 426 if (sdhc_clk / 16 > clock) {
418 for (pre_div = 2; pre_div < 256; pre_div *= 2) 427 for (pre_div = 2; pre_div < 256; pre_div *= 2)
419 if ((sdhc_clk / pre_div) <= (clock * 16)) 428 if ((sdhc_clk / pre_div) <= (clock * 16))
420 break; 429 break;
421 } else 430 } else
422 pre_div = 2; 431 pre_div = 2;
423 432
424 for (div = 1; div <= 16; div++) 433 for (div = 1; div <= 16; div++)
425 if ((sdhc_clk / (div * pre_div)) <= clock) 434 if ((sdhc_clk / (div * pre_div)) <= clock)
426 break; 435 break;
427 436
428 pre_div >>= 1; 437 pre_div >>= 1;
429 div -= 1; 438 div -= 1;
430 439
431 clk = (pre_div << 8) | (div << 4); 440 clk = (pre_div << 8) | (div << 4);
432 441
433 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); 442 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
434 443
435 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk); 444 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
436 445
437 udelay(10000); 446 udelay(10000);
438 447
439 clk = SYSCTL_PEREN | SYSCTL_CKEN; 448 clk = SYSCTL_PEREN | SYSCTL_CKEN;
440 449
441 esdhc_setbits32(&regs->sysctl, clk); 450 esdhc_setbits32(&regs->sysctl, clk);
442 } 451 }
443 452
444 static void esdhc_set_ios(struct mmc *mmc) 453 static void esdhc_set_ios(struct mmc *mmc)
445 { 454 {
446 struct fsl_esdhc_cfg *cfg = mmc->priv; 455 struct fsl_esdhc_cfg *cfg = mmc->priv;
447 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 456 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
448 457
449 /* Set the clock speed */ 458 /* Set the clock speed */
450 set_sysctl(mmc, mmc->clock); 459 set_sysctl(mmc, mmc->clock);
451 460
452 /* Set the bus width */ 461 /* Set the bus width */
453 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 462 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
454 463
455 if (mmc->bus_width == 4) 464 if (mmc->bus_width == 4)
456 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4); 465 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
457 else if (mmc->bus_width == 8) 466 else if (mmc->bus_width == 8)
458 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8); 467 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
459 468
460 } 469 }
461 470
462 static int esdhc_init(struct mmc *mmc) 471 static int esdhc_init(struct mmc *mmc)
463 { 472 {
464 struct fsl_esdhc_cfg *cfg = mmc->priv; 473 struct fsl_esdhc_cfg *cfg = mmc->priv;
465 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 474 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
466 int timeout = 1000; 475 int timeout = 1000;
467 476
468 /* Reset the entire host controller */ 477 /* Reset the entire host controller */
469 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA); 478 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
470 479
471 /* Wait until the controller is available */ 480 /* Wait until the controller is available */
472 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout) 481 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
473 udelay(1000); 482 udelay(1000);
474 483
475 #ifndef ARCH_MXC 484 #ifndef ARCH_MXC
476 /* Enable cache snooping */ 485 /* Enable cache snooping */
477 esdhc_write32(&regs->scr, 0x00000040); 486 esdhc_write32(&regs->scr, 0x00000040);
478 #endif 487 #endif
479 488
480 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 489 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
481 490
482 /* Set the initial clock speed */ 491 /* Set the initial clock speed */
483 mmc_set_clock(mmc, 400000); 492 mmc_set_clock(mmc, 400000);
484 493
485 /* Disable the BRR and BWR bits in IRQSTAT */ 494 /* Disable the BRR and BWR bits in IRQSTAT */
486 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 495 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
487 496
488 /* Put the PROCTL reg back to the default */ 497 /* Put the PROCTL reg back to the default */
489 esdhc_write32(&regs->proctl, PROCTL_INIT); 498 esdhc_write32(&regs->proctl, PROCTL_INIT);
490 499
491 /* Set timout to the maximum value */ 500 /* Set timout to the maximum value */
492 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 501 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
493 502
494 return 0; 503 return 0;
495 } 504 }
496 505
497 static int esdhc_getcd(struct mmc *mmc) 506 static int esdhc_getcd(struct mmc *mmc)
498 { 507 {
499 struct fsl_esdhc_cfg *cfg = mmc->priv; 508 struct fsl_esdhc_cfg *cfg = mmc->priv;
500 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 509 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
501 int timeout = 1000; 510 int timeout = 1000;
502 511
503 #ifdef CONFIG_ESDHC_DETECT_QUIRK 512 #ifdef CONFIG_ESDHC_DETECT_QUIRK
504 if (CONFIG_ESDHC_DETECT_QUIRK) 513 if (CONFIG_ESDHC_DETECT_QUIRK)
505 return 1; 514 return 1;
506 #endif 515 #endif
507 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout) 516 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
508 udelay(1000); 517 udelay(1000);
509 518
510 return timeout > 0; 519 return timeout > 0;
511 } 520 }
512 521
513 static void esdhc_reset(struct fsl_esdhc *regs) 522 static void esdhc_reset(struct fsl_esdhc *regs)
514 { 523 {
515 unsigned long timeout = 100; /* wait max 100 ms */ 524 unsigned long timeout = 100; /* wait max 100 ms */
516 525
517 /* reset the controller */ 526 /* reset the controller */
518 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA); 527 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
519 528
520 /* hardware clears the bit when it is done */ 529 /* hardware clears the bit when it is done */
521 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout) 530 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
522 udelay(1000); 531 udelay(1000);
523 if (!timeout) 532 if (!timeout)
524 printf("MMC/SD: Reset never completed.\n"); 533 printf("MMC/SD: Reset never completed.\n");
525 } 534 }
526 535
527 static const struct mmc_ops esdhc_ops = { 536 static const struct mmc_ops esdhc_ops = {
528 .send_cmd = esdhc_send_cmd, 537 .send_cmd = esdhc_send_cmd,
529 .set_ios = esdhc_set_ios, 538 .set_ios = esdhc_set_ios,
530 .init = esdhc_init, 539 .init = esdhc_init,
531 .getcd = esdhc_getcd, 540 .getcd = esdhc_getcd,
532 }; 541 };
533 542
534 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 543 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
535 { 544 {
536 struct fsl_esdhc *regs; 545 struct fsl_esdhc *regs;
537 struct mmc *mmc; 546 struct mmc *mmc;
538 u32 caps, voltage_caps; 547 u32 caps, voltage_caps;
539 548
540 if (!cfg) 549 if (!cfg)
541 return -1; 550 return -1;
542 551
543 regs = (struct fsl_esdhc *)cfg->esdhc_base; 552 regs = (struct fsl_esdhc *)cfg->esdhc_base;
544 553
545 /* First reset the eSDHC controller */ 554 /* First reset the eSDHC controller */
546 esdhc_reset(regs); 555 esdhc_reset(regs);
547 556
548 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 557 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
549 | SYSCTL_IPGEN | SYSCTL_CKEN); 558 | SYSCTL_IPGEN | SYSCTL_CKEN);
550 559
551 memset(&cfg->cfg, 0, sizeof(cfg->cfg)); 560 memset(&cfg->cfg, 0, sizeof(cfg->cfg));
552 561
553 voltage_caps = 0; 562 voltage_caps = 0;
554 caps = regs->hostcapblt; 563 caps = regs->hostcapblt;
555 564
556 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 565 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
557 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 566 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
558 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 567 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
559 #endif 568 #endif
560 569
561 /* T4240 host controller capabilities register should have VS33 bit */ 570 /* T4240 host controller capabilities register should have VS33 bit */
562 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 571 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
563 caps = caps | ESDHC_HOSTCAPBLT_VS33; 572 caps = caps | ESDHC_HOSTCAPBLT_VS33;
564 #endif 573 #endif
565 574
566 if (caps & ESDHC_HOSTCAPBLT_VS18) 575 if (caps & ESDHC_HOSTCAPBLT_VS18)
567 voltage_caps |= MMC_VDD_165_195; 576 voltage_caps |= MMC_VDD_165_195;
568 if (caps & ESDHC_HOSTCAPBLT_VS30) 577 if (caps & ESDHC_HOSTCAPBLT_VS30)
569 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 578 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
570 if (caps & ESDHC_HOSTCAPBLT_VS33) 579 if (caps & ESDHC_HOSTCAPBLT_VS33)
571 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 580 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
572 581
573 cfg->cfg.name = "FSL_SDHC"; 582 cfg->cfg.name = "FSL_SDHC";
574 cfg->cfg.ops = &esdhc_ops; 583 cfg->cfg.ops = &esdhc_ops;
575 #ifdef CONFIG_SYS_SD_VOLTAGE 584 #ifdef CONFIG_SYS_SD_VOLTAGE
576 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 585 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
577 #else 586 #else
578 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 587 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
579 #endif 588 #endif
580 if ((cfg->cfg.voltages & voltage_caps) == 0) { 589 if ((cfg->cfg.voltages & voltage_caps) == 0) {
581 printf("voltage not supported by controller\n"); 590 printf("voltage not supported by controller\n");
582 return -1; 591 return -1;
583 } 592 }
584 593
585 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; 594 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
586 595
587 if (cfg->max_bus_width > 0) { 596 if (cfg->max_bus_width > 0) {
588 if (cfg->max_bus_width < 8) 597 if (cfg->max_bus_width < 8)
589 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 598 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
590 if (cfg->max_bus_width < 4) 599 if (cfg->max_bus_width < 4)
591 cfg->cfg.host_caps &= ~MMC_MODE_4BIT; 600 cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
592 } 601 }
593 602
594 if (caps & ESDHC_HOSTCAPBLT_HSS) 603 if (caps & ESDHC_HOSTCAPBLT_HSS)
595 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 604 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
596 605
597 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 606 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
598 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 607 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
599 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 608 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
600 #endif 609 #endif
601 610
602 cfg->cfg.f_min = 400000; 611 cfg->cfg.f_min = 400000;
603 cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000); 612 cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000);
604 613
605 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 614 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
606 615
607 mmc = mmc_create(&cfg->cfg, cfg); 616 mmc = mmc_create(&cfg->cfg, cfg);
608 if (mmc == NULL) 617 if (mmc == NULL)
609 return -1; 618 return -1;
610 619
611 return 0; 620 return 0;
612 } 621 }
613 622
614 int fsl_esdhc_mmc_init(bd_t *bis) 623 int fsl_esdhc_mmc_init(bd_t *bis)
615 { 624 {
616 struct fsl_esdhc_cfg *cfg; 625 struct fsl_esdhc_cfg *cfg;
617 626
618 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 627 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
619 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 628 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
620 cfg->sdhc_clk = gd->arch.sdhc_clk; 629 cfg->sdhc_clk = gd->arch.sdhc_clk;
621 return fsl_esdhc_initialize(bis, cfg); 630 return fsl_esdhc_initialize(bis, cfg);
622 } 631 }
623 632
624 #ifdef CONFIG_OF_LIBFDT 633 #ifdef CONFIG_OF_LIBFDT
625 void fdt_fixup_esdhc(void *blob, bd_t *bd) 634 void fdt_fixup_esdhc(void *blob, bd_t *bd)
626 { 635 {
627 const char *compat = "fsl,esdhc"; 636 const char *compat = "fsl,esdhc";
628 637
629 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 638 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
630 if (!hwconfig("esdhc")) { 639 if (!hwconfig("esdhc")) {