Commit 8cdf030f2c12d26ea555708175540916a3ac9090
1 parent
df339c7bdb
Exists in
smarc-rel_imx_4.1.15_2.0.0_ga
MLK-12848: mx6ull_14x14_ddr3_arm2: add new TSC config
Due to TSC pin conflict with I2C1 bus, and PMIC is this I2C1 bus's slave, this patch add new TSC config for i.mx6ull_14x14_ddr3_arm2 board, disable PMIC and ldo bypass check. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Showing 2 changed files with 21 additions and 0 deletions Inline Diff
configs/mx6ull_14x14_ddr3_arm2_tsc_defconfig
| File was created | 1 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg,MX6ULL_DDR3_ARM2_TSC_REWORK" | |
| 2 | CONFIG_ARM=y | ||
| 3 | CONFIG_ARCH_MX6=y | ||
| 4 | CONFIG_TARGET_MX6ULL_DDR3_ARM2=y | ||
| 5 | CONFIG_CMD_GPIO=y | ||
| 6 |
include/configs/mx6ull_ddr3_arm2.h
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2016 Freescale Semiconductor, Inc. | 2 | * Copyright (C) 2016 Freescale Semiconductor, Inc. |
| 3 | * | 3 | * |
| 4 | * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. | 4 | * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. |
| 5 | * | 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ | 7 | */ |
| 8 | #ifndef __MX6ULL_DDR3_ARM2_CONFIG_H | 8 | #ifndef __MX6ULL_DDR3_ARM2_CONFIG_H |
| 9 | #define __MX6ULL_DDR3_ARM2_CONFIG_H | 9 | #define __MX6ULL_DDR3_ARM2_CONFIG_H |
| 10 | 10 | ||
| 11 | #define CONFIG_DEFAULT_FDT_FILE "imx6ull-14x14-ddr3-arm2.dtb" | 11 | #define CONFIG_DEFAULT_FDT_FILE "imx6ull-14x14-ddr3-arm2.dtb" |
| 12 | 12 | ||
| 13 | #ifdef CONFIG_SYS_BOOT_QSPI | 13 | #ifdef CONFIG_SYS_BOOT_QSPI |
| 14 | #define CONFIG_SYS_USE_QSPI | 14 | #define CONFIG_SYS_USE_QSPI |
| 15 | #define CONFIG_ENV_IS_IN_SPI_FLASH | 15 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 16 | #elif defined CONFIG_SYS_BOOT_SPINOR | 16 | #elif defined CONFIG_SYS_BOOT_SPINOR |
| 17 | #define CONFIG_SYS_USE_SPINOR | 17 | #define CONFIG_SYS_USE_SPINOR |
| 18 | #define CONFIG_ENV_IS_IN_SPI_FLASH | 18 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 19 | #elif defined CONFIG_SYS_BOOT_NAND | 19 | #elif defined CONFIG_SYS_BOOT_NAND |
| 20 | #define CONFIG_SYS_USE_NAND | 20 | #define CONFIG_SYS_USE_NAND |
| 21 | #define CONFIG_ENV_IS_IN_NAND | 21 | #define CONFIG_ENV_IS_IN_NAND |
| 22 | #else | 22 | #else |
| 23 | #ifndef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK | 23 | #ifndef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK |
| 24 | #define CONFIG_SYS_USE_QSPI | 24 | #define CONFIG_SYS_USE_QSPI |
| 25 | #endif | 25 | #endif |
| 26 | #define CONFIG_ENV_IS_IN_MMC | 26 | #define CONFIG_ENV_IS_IN_MMC |
| 27 | #endif | 27 | #endif |
| 28 | 28 | ||
| 29 | #define CONFIG_VIDEO | 29 | #define CONFIG_VIDEO |
| 30 | #define CONFIG_FSL_USDHC | 30 | #define CONFIG_FSL_USDHC |
| 31 | #define CONFIG_BOOTARGS_CMA_SIZE "" | 31 | #define CONFIG_BOOTARGS_CMA_SIZE "" |
| 32 | 32 | ||
| 33 | #include "mx6ul_arm2.h" | 33 | #include "mx6ul_arm2.h" |
| 34 | 34 | ||
| 35 | #define CONFIG_IOMUX_LPSR | 35 | #define CONFIG_IOMUX_LPSR |
| 36 | 36 | ||
| 37 | #define PHYS_SDRAM_SIZE SZ_1G | 37 | #define PHYS_SDRAM_SIZE SZ_1G |
| 38 | 38 | ||
| 39 | /* | ||
| 40 | * TSC pins conflict with I2C1 bus, so after TSC | ||
| 41 | * hardware rework, need to disable i2c1 bus, also | ||
| 42 | * need to disable PMIC and ldo bypass check. | ||
| 43 | */ | ||
| 44 | #ifdef CONFIG_MX6ULL_DDR3_ARM2_TSC_REWORK | ||
| 45 | #undef CONFIG_LDO_BYPASS_CHECK | ||
| 46 | #undef CONFIG_SYS_I2C_MXC | ||
| 47 | #undef CONFIG_SYS_I2C | ||
| 48 | #undef CONFIG_CMD_I2C | ||
| 49 | #undef CONFIG_POWER_PFUZE100_I2C_ADDR | ||
| 50 | #undef CONFIG_POWER_PFUZE100 | ||
| 51 | #undef CONFIG_POWER_I2C | ||
| 52 | #undef CONFIG_POWER | ||
| 53 | #endif | ||
| 54 | |||
| 39 | #ifdef CONFIG_SYS_USE_SPINOR | 55 | #ifdef CONFIG_SYS_USE_SPINOR |
| 40 | #define CONFIG_CMD_SF | 56 | #define CONFIG_CMD_SF |
| 41 | #define CONFIG_SPI_FLASH | 57 | #define CONFIG_SPI_FLASH |
| 42 | #define CONFIG_SPI_FLASH_STMICRO | 58 | #define CONFIG_SPI_FLASH_STMICRO |
| 43 | #define CONFIG_MXC_SPI | 59 | #define CONFIG_MXC_SPI |
| 44 | #define CONFIG_SF_DEFAULT_BUS 0 | 60 | #define CONFIG_SF_DEFAULT_BUS 0 |
| 45 | #define CONFIG_SF_DEFAULT_SPEED 20000000 | 61 | #define CONFIG_SF_DEFAULT_SPEED 20000000 |
| 46 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) | 62 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) |
| 47 | #define CONFIG_SF_DEFAULT_CS 0 | 63 | #define CONFIG_SF_DEFAULT_CS 0 |
| 48 | #endif | 64 | #endif |
| 49 | 65 | ||
| 50 | #ifdef CONFIG_CMD_NET | 66 | #ifdef CONFIG_CMD_NET |
| 51 | #define CONFIG_CMD_PING | 67 | #define CONFIG_CMD_PING |
| 52 | #define CONFIG_CMD_DHCP | 68 | #define CONFIG_CMD_DHCP |
| 53 | #define CONFIG_CMD_MII | 69 | #define CONFIG_CMD_MII |
| 54 | #define CONFIG_FEC_MXC | 70 | #define CONFIG_FEC_MXC |
| 55 | #define CONFIG_MII | 71 | #define CONFIG_MII |
| 56 | #define CONFIG_FEC_ENET_DEV 1 | 72 | #define CONFIG_FEC_ENET_DEV 1 |
| 57 | 73 | ||
| 58 | #if (CONFIG_FEC_ENET_DEV == 0) | 74 | #if (CONFIG_FEC_ENET_DEV == 0) |
| 59 | #define IMX_FEC_BASE ENET_BASE_ADDR | 75 | #define IMX_FEC_BASE ENET_BASE_ADDR |
| 60 | #define CONFIG_FEC_MXC_PHYADDR 0x1 | 76 | #define CONFIG_FEC_MXC_PHYADDR 0x1 |
| 61 | #define CONFIG_FEC_XCV_TYPE RMII | 77 | #define CONFIG_FEC_XCV_TYPE RMII |
| 62 | #elif (CONFIG_FEC_ENET_DEV == 1) | 78 | #elif (CONFIG_FEC_ENET_DEV == 1) |
| 63 | #define IMX_FEC_BASE ENET2_BASE_ADDR | 79 | #define IMX_FEC_BASE ENET2_BASE_ADDR |
| 64 | #define CONFIG_FEC_MXC_PHYADDR 0x2 | 80 | #define CONFIG_FEC_MXC_PHYADDR 0x2 |
| 65 | #define CONFIG_FEC_XCV_TYPE MII100 | 81 | #define CONFIG_FEC_XCV_TYPE MII100 |
| 66 | #endif | 82 | #endif |
| 67 | #define CONFIG_ETHPRIME "FEC" | 83 | #define CONFIG_ETHPRIME "FEC" |
| 68 | 84 | ||
| 69 | #define CONFIG_PHYLIB | 85 | #define CONFIG_PHYLIB |
| 70 | #define CONFIG_PHY_MICREL | 86 | #define CONFIG_PHY_MICREL |
| 71 | #define CONFIG_FEC_DMA_MINALIGN 64 | 87 | #define CONFIG_FEC_DMA_MINALIGN 64 |
| 72 | #endif | 88 | #endif |
| 73 | 89 | ||
| 74 | #endif | 90 | #endif |
| 75 | 91 |