Eric Lee / smarc-uboot

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Commit 8ea9c15b8e3ad32bb6a2f0a4dbb3995ffa55f815

Authored by Hou Zhiqiang
Committed by Priyanka Jain
1 parent da46c77d7d
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

board: lx2160a: Don't program the GIC RD tables if failed to reserve memory 

Program the GIC redistributor tables only when succeeded to reserve memory
for them, otherwise kernel will lose the chance to program them using
allocated memory.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Showing 1 changed file with 4 additions and 2 deletions Inline Diff

board/freescale/lx2160a/lx2160a.c
Diff comments   View file @ 8ea9c15
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018-2020 NXP 3 * Copyright 2018-2020 NXP
4 */ 4 */
5 5
6 #include <common.h> 6 #include <common.h>
7 #include <clock_legacy.h> 7 #include <clock_legacy.h>
8 #include <dm.h> 8 #include <dm.h>
9 #include <dm/platform_data/serial_pl01x.h> 9 #include <dm/platform_data/serial_pl01x.h>
10 #include <i2c.h> 10 #include <i2c.h>
11 #include <malloc.h> 11 #include <malloc.h>
12 #include <errno.h> 12 #include <errno.h>
13 #include <netdev.h> 13 #include <netdev.h>
14 #include <fsl_ddr.h> 14 #include <fsl_ddr.h>
15 #include <fsl_sec.h> 15 #include <fsl_sec.h>
16 #include <asm/io.h> 16 #include <asm/io.h>
17 #include <fdt_support.h> 17 #include <fdt_support.h>
18 #include <linux/libfdt.h> 18 #include <linux/libfdt.h>
19 #include <linux/delay.h> 19 #include <linux/delay.h>
20 #include <fsl-mc/fsl_mc.h> 20 #include <fsl-mc/fsl_mc.h>
21 #include <env_internal.h> 21 #include <env_internal.h>
22 #include <efi_loader.h> 22 #include <efi_loader.h>
23 #include <asm/arch/mmu.h> 23 #include <asm/arch/mmu.h>
24 #include <hwconfig.h> 24 #include <hwconfig.h>
25 #include <asm/arch/clock.h> 25 #include <asm/arch/clock.h>
26 #include <asm/arch/config.h> 26 #include <asm/arch/config.h>
27 #include <asm/arch/fsl_serdes.h> 27 #include <asm/arch/fsl_serdes.h>
28 #include <asm/arch/soc.h> 28 #include <asm/arch/soc.h>
29 #include "../common/qixis.h" 29 #include "../common/qixis.h"
30 #include "../common/vid.h" 30 #include "../common/vid.h"
31 #include <fsl_immap.h> 31 #include <fsl_immap.h>
32 #include <asm/arch-fsl-layerscape/fsl_icid.h> 32 #include <asm/arch-fsl-layerscape/fsl_icid.h>
33 #include <asm/gic-v3.h> 33 #include <asm/gic-v3.h>
34 #include <cpu_func.h> 34 #include <cpu_func.h>
35 35
36 #ifdef CONFIG_EMC2305 36 #ifdef CONFIG_EMC2305
37 #include "../common/emc2305.h" 37 #include "../common/emc2305.h"
38 #endif 38 #endif
39 39
40 #define GIC_LPI_SIZE 0x200000 40 #define GIC_LPI_SIZE 0x200000
41 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 41 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
42 #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) 42 #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
43 #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) 43 #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
44 #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value) 44 #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
45 #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value) 45 #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
46 #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value) 46 #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
47 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value) 47 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
48 #define SDHC1_BASE_PMUX_DSPI 2 48 #define SDHC1_BASE_PMUX_DSPI 2
49 #define SDHC2_BASE_PMUX_DSPI 2 49 #define SDHC2_BASE_PMUX_DSPI 2
50 #define IIC5_PMUX_SPI3 3 50 #define IIC5_PMUX_SPI3 3
51 #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */ 51 #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
52 52
53 DECLARE_GLOBAL_DATA_PTR; 53 DECLARE_GLOBAL_DATA_PTR;
54 54
55 static struct pl01x_serial_platdata serial0 = { 55 static struct pl01x_serial_platdata serial0 = {
56 #if CONFIG_CONS_INDEX == 0 56 #if CONFIG_CONS_INDEX == 0
57 .base = CONFIG_SYS_SERIAL0, 57 .base = CONFIG_SYS_SERIAL0,
58 #elif CONFIG_CONS_INDEX == 1 58 #elif CONFIG_CONS_INDEX == 1
59 .base = CONFIG_SYS_SERIAL1, 59 .base = CONFIG_SYS_SERIAL1,
60 #else 60 #else
61 #error "Unsupported console index value." 61 #error "Unsupported console index value."
62 #endif 62 #endif
63 .type = TYPE_PL011, 63 .type = TYPE_PL011,
64 }; 64 };
65 65
66 U_BOOT_DEVICE(nxp_serial0) = { 66 U_BOOT_DEVICE(nxp_serial0) = {
67 .name = "serial_pl01x", 67 .name = "serial_pl01x",
68 .platdata = &serial0, 68 .platdata = &serial0,
69 }; 69 };
70 70
71 static struct pl01x_serial_platdata serial1 = { 71 static struct pl01x_serial_platdata serial1 = {
72 .base = CONFIG_SYS_SERIAL1, 72 .base = CONFIG_SYS_SERIAL1,
73 .type = TYPE_PL011, 73 .type = TYPE_PL011,
74 }; 74 };
75 75
76 U_BOOT_DEVICE(nxp_serial1) = { 76 U_BOOT_DEVICE(nxp_serial1) = {
77 .name = "serial_pl01x", 77 .name = "serial_pl01x",
78 .platdata = &serial1, 78 .platdata = &serial1,
79 }; 79 };
80 80
81 int select_i2c_ch_pca9547(u8 ch) 81 int select_i2c_ch_pca9547(u8 ch)
82 { 82 {
83 int ret; 83 int ret;
84 84
85 #ifndef CONFIG_DM_I2C 85 #ifndef CONFIG_DM_I2C
86 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 86 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
87 #else 87 #else
88 struct udevice *dev; 88 struct udevice *dev;
89 89
90 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); 90 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
91 if (!ret) 91 if (!ret)
92 ret = dm_i2c_write(dev, 0, &ch, 1); 92 ret = dm_i2c_write(dev, 0, &ch, 1);
93 #endif 93 #endif
94 if (ret) { 94 if (ret) {
95 puts("PCA: failed to select proper channel\n"); 95 puts("PCA: failed to select proper channel\n");
96 return ret; 96 return ret;
97 } 97 }
98 98
99 return 0; 99 return 0;
100 } 100 }
101 101
102 int select_i2c_ch_pca9547_sec(u8 ch) 102 int select_i2c_ch_pca9547_sec(u8 ch)
103 { 103 {
104 int ret; 104 int ret;
105 105
106 #ifndef CONFIG_DM_I2C 106 #ifndef CONFIG_DM_I2C
107 ret = i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &ch, 1); 107 ret = i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &ch, 1);
108 #else 108 #else
109 struct udevice *dev; 109 struct udevice *dev;
110 110
111 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_SEC, 1, &dev); 111 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_SEC, 1, &dev);
112 if (!ret) 112 if (!ret)
113 ret = dm_i2c_write(dev, 0, &ch, 1); 113 ret = dm_i2c_write(dev, 0, &ch, 1);
114 #endif 114 #endif
115 if (ret) { 115 if (ret) {
116 puts("PCA: failed to select proper channel\n"); 116 puts("PCA: failed to select proper channel\n");
117 return ret; 117 return ret;
118 } 118 }
119 119
120 return 0; 120 return 0;
121 } 121 }
122 122
123 static void uart_get_clock(void) 123 static void uart_get_clock(void)
124 { 124 {
125 serial0.clock = get_serial_clock(); 125 serial0.clock = get_serial_clock();
126 serial1.clock = get_serial_clock(); 126 serial1.clock = get_serial_clock();
127 } 127 }
128 128
129 int board_early_init_f(void) 129 int board_early_init_f(void)
130 { 130 {
131 #ifdef CONFIG_SYS_I2C_EARLY_INIT 131 #ifdef CONFIG_SYS_I2C_EARLY_INIT
132 i2c_early_init_f(); 132 i2c_early_init_f();
133 #endif 133 #endif
134 /* get required clock for UART IP */ 134 /* get required clock for UART IP */
135 uart_get_clock(); 135 uart_get_clock();
136 136
137 #ifdef CONFIG_EMC2305 137 #ifdef CONFIG_EMC2305
138 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305); 138 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
139 emc2305_init(I2C_EMC2305_ADDR); 139 emc2305_init(I2C_EMC2305_ADDR);
140 set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR); 140 set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
141 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 141 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
142 #endif 142 #endif
143 143
144 fsl_lsch3_early_init_f(); 144 fsl_lsch3_early_init_f();
145 return 0; 145 return 0;
146 } 146 }
147 147
148 #ifdef CONFIG_OF_BOARD_FIXUP 148 #ifdef CONFIG_OF_BOARD_FIXUP
149 int board_fix_fdt(void *fdt) 149 int board_fix_fdt(void *fdt)
150 { 150 {
151 char *reg_names, *reg_name; 151 char *reg_names, *reg_name;
152 int names_len, old_name_len, new_name_len, remaining_names_len; 152 int names_len, old_name_len, new_name_len, remaining_names_len;
153 struct str_map { 153 struct str_map {
154 char *old_str; 154 char *old_str;
155 char *new_str; 155 char *new_str;
156 } reg_names_map[] = { 156 } reg_names_map[] = {
157 { "ccsr", "dbi" }, 157 { "ccsr", "dbi" },
158 { "pf_ctrl", "ctrl" } 158 { "pf_ctrl", "ctrl" }
159 }; 159 };
160 int off = -1, i = 0; 160 int off = -1, i = 0;
161 161
162 if (IS_SVR_REV(get_svr(), 1, 0)) 162 if (IS_SVR_REV(get_svr(), 1, 0))
163 return 0; 163 return 0;
164 164
165 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie"); 165 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
166 while (off != -FDT_ERR_NOTFOUND) { 166 while (off != -FDT_ERR_NOTFOUND) {
167 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie", 167 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
168 strlen("fsl,ls-pcie") + 1); 168 strlen("fsl,ls-pcie") + 1);
169 169
170 reg_names = (char *)fdt_getprop(fdt, off, "reg-names", 170 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
171 &names_len); 171 &names_len);
172 if (!reg_names) 172 if (!reg_names)
173 continue; 173 continue;
174 174
175 reg_name = reg_names; 175 reg_name = reg_names;
176 remaining_names_len = names_len - (reg_name - reg_names); 176 remaining_names_len = names_len - (reg_name - reg_names);
177 i = 0; 177 i = 0;
178 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) { 178 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
179 old_name_len = strlen(reg_names_map[i].old_str); 179 old_name_len = strlen(reg_names_map[i].old_str);
180 new_name_len = strlen(reg_names_map[i].new_str); 180 new_name_len = strlen(reg_names_map[i].new_str);
181 if (memcmp(reg_name, reg_names_map[i].old_str, 181 if (memcmp(reg_name, reg_names_map[i].old_str,
182 old_name_len) == 0) { 182 old_name_len) == 0) {
183 /* first only leave required bytes for new_str 183 /* first only leave required bytes for new_str
184 * and copy rest of the string after it 184 * and copy rest of the string after it
185 */ 185 */
186 memcpy(reg_name + new_name_len, 186 memcpy(reg_name + new_name_len,
187 reg_name + old_name_len, 187 reg_name + old_name_len,
188 remaining_names_len - old_name_len); 188 remaining_names_len - old_name_len);
189 /* Now copy new_str */ 189 /* Now copy new_str */
190 memcpy(reg_name, reg_names_map[i].new_str, 190 memcpy(reg_name, reg_names_map[i].new_str,
191 new_name_len); 191 new_name_len);
192 names_len -= old_name_len; 192 names_len -= old_name_len;
193 names_len += new_name_len; 193 names_len += new_name_len;
194 i++; 194 i++;
195 } 195 }
196 196
197 reg_name = memchr(reg_name, '\0', remaining_names_len); 197 reg_name = memchr(reg_name, '\0', remaining_names_len);
198 if (!reg_name) 198 if (!reg_name)
199 break; 199 break;
200 200
201 reg_name += 1; 201 reg_name += 1;
202 202
203 remaining_names_len = names_len - 203 remaining_names_len = names_len -
204 (reg_name - reg_names); 204 (reg_name - reg_names);
205 } 205 }
206 206
207 fdt_setprop(fdt, off, "reg-names", reg_names, names_len); 207 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
208 off = fdt_node_offset_by_compatible(fdt, off, 208 off = fdt_node_offset_by_compatible(fdt, off,
209 "fsl,lx2160a-pcie"); 209 "fsl,lx2160a-pcie");
210 } 210 }
211 211
212 return 0; 212 return 0;
213 } 213 }
214 #endif 214 #endif
215 215
216 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 216 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
217 void esdhc_dspi_status_fixup(void *blob) 217 void esdhc_dspi_status_fixup(void *blob)
218 { 218 {
219 const char esdhc0_path[] = "/soc/esdhc@2140000"; 219 const char esdhc0_path[] = "/soc/esdhc@2140000";
220 const char esdhc1_path[] = "/soc/esdhc@2150000"; 220 const char esdhc1_path[] = "/soc/esdhc@2150000";
221 const char dspi0_path[] = "/soc/spi@2100000"; 221 const char dspi0_path[] = "/soc/spi@2100000";
222 const char dspi1_path[] = "/soc/spi@2110000"; 222 const char dspi1_path[] = "/soc/spi@2110000";
223 const char dspi2_path[] = "/soc/spi@2120000"; 223 const char dspi2_path[] = "/soc/spi@2120000";
224 224
225 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 225 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
226 u32 sdhc1_base_pmux; 226 u32 sdhc1_base_pmux;
227 u32 sdhc2_base_pmux; 227 u32 sdhc2_base_pmux;
228 u32 iic5_pmux; 228 u32 iic5_pmux;
229 229
230 /* Check RCW field sdhc1_base_pmux to enable/disable 230 /* Check RCW field sdhc1_base_pmux to enable/disable
231 * esdhc0/dspi0 DT node 231 * esdhc0/dspi0 DT node
232 */ 232 */
233 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 233 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
234 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; 234 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
235 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; 235 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
236 236
237 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { 237 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
238 do_fixup_by_path(blob, dspi0_path, "status", "okay", 238 do_fixup_by_path(blob, dspi0_path, "status", "okay",
239 sizeof("okay"), 1); 239 sizeof("okay"), 1);
240 do_fixup_by_path(blob, esdhc0_path, "status", "disabled", 240 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
241 sizeof("disabled"), 1); 241 sizeof("disabled"), 1);
242 } else { 242 } else {
243 do_fixup_by_path(blob, esdhc0_path, "status", "okay", 243 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
244 sizeof("okay"), 1); 244 sizeof("okay"), 1);
245 do_fixup_by_path(blob, dspi0_path, "status", "disabled", 245 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
246 sizeof("disabled"), 1); 246 sizeof("disabled"), 1);
247 } 247 }
248 248
249 /* Check RCW field sdhc2_base_pmux to enable/disable 249 /* Check RCW field sdhc2_base_pmux to enable/disable
250 * esdhc1/dspi1 DT node 250 * esdhc1/dspi1 DT node
251 */ 251 */
252 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) 252 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
253 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; 253 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
254 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; 254 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
255 255
256 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { 256 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
257 do_fixup_by_path(blob, dspi1_path, "status", "okay", 257 do_fixup_by_path(blob, dspi1_path, "status", "okay",
258 sizeof("okay"), 1); 258 sizeof("okay"), 1);
259 do_fixup_by_path(blob, esdhc1_path, "status", "disabled", 259 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
260 sizeof("disabled"), 1); 260 sizeof("disabled"), 1);
261 } else { 261 } else {
262 do_fixup_by_path(blob, esdhc1_path, "status", "okay", 262 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
263 sizeof("okay"), 1); 263 sizeof("okay"), 1);
264 do_fixup_by_path(blob, dspi1_path, "status", "disabled", 264 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
265 sizeof("disabled"), 1); 265 sizeof("disabled"), 1);
266 } 266 }
267 267
268 /* Check RCW field IIC5 to enable dspi2 DT node */ 268 /* Check RCW field IIC5 to enable dspi2 DT node */
269 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 269 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
270 & FSL_CHASSIS3_IIC5_PMUX_MASK; 270 & FSL_CHASSIS3_IIC5_PMUX_MASK;
271 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; 271 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
272 272
273 if (iic5_pmux == IIC5_PMUX_SPI3) 273 if (iic5_pmux == IIC5_PMUX_SPI3)
274 do_fixup_by_path(blob, dspi2_path, "status", "okay", 274 do_fixup_by_path(blob, dspi2_path, "status", "okay",
275 sizeof("okay"), 1); 275 sizeof("okay"), 1);
276 else 276 else
277 do_fixup_by_path(blob, dspi2_path, "status", "disabled", 277 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
278 sizeof("disabled"), 1); 278 sizeof("disabled"), 1);
279 } 279 }
280 #endif 280 #endif
281 281
282 int esdhc_status_fixup(void *blob, const char *compat) 282 int esdhc_status_fixup(void *blob, const char *compat)
283 { 283 {
284 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 284 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
285 /* Enable esdhc and dspi DT nodes based on RCW fields */ 285 /* Enable esdhc and dspi DT nodes based on RCW fields */
286 esdhc_dspi_status_fixup(blob); 286 esdhc_dspi_status_fixup(blob);
287 #else 287 #else
288 /* Enable both esdhc DT nodes for LX2160ARDB */ 288 /* Enable both esdhc DT nodes for LX2160ARDB */
289 do_fixup_by_compat(blob, compat, "status", "okay", 289 do_fixup_by_compat(blob, compat, "status", "okay",
290 sizeof("okay"), 1); 290 sizeof("okay"), 1);
291 #endif 291 #endif
292 return 0; 292 return 0;
293 } 293 }
294 294
295 #if defined(CONFIG_VID) 295 #if defined(CONFIG_VID)
296 int i2c_multiplexer_select_vid_channel(u8 channel) 296 int i2c_multiplexer_select_vid_channel(u8 channel)
297 { 297 {
298 return select_i2c_ch_pca9547(channel); 298 return select_i2c_ch_pca9547(channel);
299 } 299 }
300 300
301 int init_func_vid(void) 301 int init_func_vid(void)
302 { 302 {
303 int set_vid; 303 int set_vid;
304 304
305 if (IS_SVR_REV(get_svr(), 1, 0)) 305 if (IS_SVR_REV(get_svr(), 1, 0))
306 set_vid = adjust_vdd(800); 306 set_vid = adjust_vdd(800);
307 else 307 else
308 set_vid = adjust_vdd(0); 308 set_vid = adjust_vdd(0);
309 309
310 if (set_vid < 0) 310 if (set_vid < 0)
311 printf("core voltage not adjusted\n"); 311 printf("core voltage not adjusted\n");
312 312
313 return 0; 313 return 0;
314 } 314 }
315 #endif 315 #endif
316 316
317 int checkboard(void) 317 int checkboard(void)
318 { 318 {
319 enum boot_src src = get_boot_src(); 319 enum boot_src src = get_boot_src();
320 char buf[64]; 320 char buf[64];
321 u8 sw; 321 u8 sw;
322 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 322 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
323 int clock; 323 int clock;
324 static const char *const freq[] = {"100", "125", "156.25", 324 static const char *const freq[] = {"100", "125", "156.25",
325 "161.13", "322.26", "", "", "", 325 "161.13", "322.26", "", "", "",
326 "", "", "", "", "", "", "", 326 "", "", "", "", "", "", "",
327 "100 separate SSCG"}; 327 "100 separate SSCG"};
328 #endif 328 #endif
329 329
330 cpu_name(buf); 330 cpu_name(buf);
331 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 331 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
332 printf("Board: %s-QDS, ", buf); 332 printf("Board: %s-QDS, ", buf);
333 #else 333 #else
334 printf("Board: %s-RDB, ", buf); 334 printf("Board: %s-RDB, ", buf);
335 #endif 335 #endif
336 336
337 sw = QIXIS_READ(arch); 337 sw = QIXIS_READ(arch);
338 printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); 338 printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
339 339
340 if (src == BOOT_SOURCE_SD_MMC) { 340 if (src == BOOT_SOURCE_SD_MMC) {
341 puts("SD\n"); 341 puts("SD\n");
342 } else if (src == BOOT_SOURCE_SD_MMC2) { 342 } else if (src == BOOT_SOURCE_SD_MMC2) {
343 puts("eMMC\n"); 343 puts("eMMC\n");
344 } else { 344 } else {
345 sw = QIXIS_READ(brdcfg[0]); 345 sw = QIXIS_READ(brdcfg[0]);
346 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; 346 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
347 switch (sw) { 347 switch (sw) {
348 case 0: 348 case 0:
349 case 4: 349 case 4:
350 puts("FlexSPI DEV#0\n"); 350 puts("FlexSPI DEV#0\n");
351 break; 351 break;
352 case 1: 352 case 1:
353 puts("FlexSPI DEV#1\n"); 353 puts("FlexSPI DEV#1\n");
354 break; 354 break;
355 case 2: 355 case 2:
356 case 3: 356 case 3:
357 puts("FlexSPI EMU\n"); 357 puts("FlexSPI EMU\n");
358 break; 358 break;
359 default: 359 default:
360 printf("invalid setting, xmap: %d\n", sw); 360 printf("invalid setting, xmap: %d\n", sw);
361 break; 361 break;
362 } 362 }
363 } 363 }
364 #if defined(CONFIG_TARGET_LX2160ARDB) 364 #if defined(CONFIG_TARGET_LX2160ARDB)
365 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 365 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
366 366
367 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); 367 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
368 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); 368 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
369 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); 369 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
370 #else 370 #else
371 printf("FPGA: v%d (%s), build %d", 371 printf("FPGA: v%d (%s), build %d",
372 (int)QIXIS_READ(scver), qixis_read_tag(buf), 372 (int)QIXIS_READ(scver), qixis_read_tag(buf),
373 (int)qixis_read_minor()); 373 (int)qixis_read_minor());
374 /* the timestamp string contains "\n" at the end */ 374 /* the timestamp string contains "\n" at the end */
375 printf(" on %s", qixis_read_time(buf)); 375 printf(" on %s", qixis_read_time(buf));
376 376
377 puts("SERDES1 Reference : "); 377 puts("SERDES1 Reference : ");
378 sw = QIXIS_READ(brdcfg[2]); 378 sw = QIXIS_READ(brdcfg[2]);
379 clock = sw >> 4; 379 clock = sw >> 4;
380 printf("Clock1 = %sMHz ", freq[clock]); 380 printf("Clock1 = %sMHz ", freq[clock]);
381 #if defined(CONFIG_TARGET_LX2160AQDS) 381 #if defined(CONFIG_TARGET_LX2160AQDS)
382 clock = sw & 0x0f; 382 clock = sw & 0x0f;
383 printf("Clock2 = %sMHz", freq[clock]); 383 printf("Clock2 = %sMHz", freq[clock]);
384 #endif 384 #endif
385 sw = QIXIS_READ(brdcfg[3]); 385 sw = QIXIS_READ(brdcfg[3]);
386 puts("\nSERDES2 Reference : "); 386 puts("\nSERDES2 Reference : ");
387 clock = sw >> 4; 387 clock = sw >> 4;
388 printf("Clock1 = %sMHz ", freq[clock]); 388 printf("Clock1 = %sMHz ", freq[clock]);
389 clock = sw & 0x0f; 389 clock = sw & 0x0f;
390 printf("Clock2 = %sMHz\n", freq[clock]); 390 printf("Clock2 = %sMHz\n", freq[clock]);
391 #if defined(CONFIG_TARGET_LX2160AQDS) 391 #if defined(CONFIG_TARGET_LX2160AQDS)
392 sw = QIXIS_READ(brdcfg[12]); 392 sw = QIXIS_READ(brdcfg[12]);
393 puts("SERDES3 Reference : "); 393 puts("SERDES3 Reference : ");
394 clock = sw >> 4; 394 clock = sw >> 4;
395 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); 395 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
396 #endif 396 #endif
397 #endif 397 #endif
398 return 0; 398 return 0;
399 } 399 }
400 400
401 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 401 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
402 /* 402 /*
403 * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. 403 * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
404 */ 404 */
405 u8 qixis_esdhc_detect_quirk(void) 405 u8 qixis_esdhc_detect_quirk(void)
406 { 406 {
407 /* 407 /*
408 * SDHC1 Card ID: 408 * SDHC1 Card ID:
409 * Specifies the type of card installed in the SDHC1 adapter slot. 409 * Specifies the type of card installed in the SDHC1 adapter slot.
410 * 000= (reserved) 410 * 000= (reserved)
411 * 001= eMMC V4.5 adapter is installed. 411 * 001= eMMC V4.5 adapter is installed.
412 * 010= SD/MMC 3.3V adapter is installed. 412 * 010= SD/MMC 3.3V adapter is installed.
413 * 011= eMMC V4.4 adapter is installed. 413 * 011= eMMC V4.4 adapter is installed.
414 * 100= eMMC V5.0 adapter is installed. 414 * 100= eMMC V5.0 adapter is installed.
415 * 101= MMC card/Legacy (3.3V) adapter is installed. 415 * 101= MMC card/Legacy (3.3V) adapter is installed.
416 * 110= SDCard V2/V3 adapter installed. 416 * 110= SDCard V2/V3 adapter installed.
417 * 111= no adapter is installed. 417 * 111= no adapter is installed.
418 */ 418 */
419 return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) != 419 return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
420 QIXIS_ESDHC_NO_ADAPTER); 420 QIXIS_ESDHC_NO_ADAPTER);
421 } 421 }
422 422
423 static void esdhc_adapter_card_ident(void) 423 static void esdhc_adapter_card_ident(void)
424 { 424 {
425 u8 card_id, val; 425 u8 card_id, val;
426 426
427 val = QIXIS_READ(sdhc1); 427 val = QIXIS_READ(sdhc1);
428 card_id = val & QIXIS_SDID_MASK; 428 card_id = val & QIXIS_SDID_MASK;
429 429
430 switch (card_id) { 430 switch (card_id) {
431 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 431 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
432 /* Power cycle to card */ 432 /* Power cycle to card */
433 val &= ~QIXIS_SDHC1_S1V3; 433 val &= ~QIXIS_SDHC1_S1V3;
434 QIXIS_WRITE(sdhc1, val); 434 QIXIS_WRITE(sdhc1, val);
435 mdelay(1); 435 mdelay(1);
436 val |= QIXIS_SDHC1_S1V3; 436 val |= QIXIS_SDHC1_S1V3;
437 QIXIS_WRITE(sdhc1, val); 437 QIXIS_WRITE(sdhc1, val);
438 /* Route to SDHC1_VS */ 438 /* Route to SDHC1_VS */
439 val = QIXIS_READ(brdcfg[11]); 439 val = QIXIS_READ(brdcfg[11]);
440 val |= QIXIS_SDHC1_VS; 440 val |= QIXIS_SDHC1_VS;
441 QIXIS_WRITE(brdcfg[11], val); 441 QIXIS_WRITE(brdcfg[11], val);
442 break; 442 break;
443 default: 443 default:
444 break; 444 break;
445 } 445 }
446 } 446 }
447 447
448 int config_board_mux(void) 448 int config_board_mux(void)
449 { 449 {
450 u8 reg11, reg5, reg13; 450 u8 reg11, reg5, reg13;
451 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 451 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
452 u32 sdhc1_base_pmux; 452 u32 sdhc1_base_pmux;
453 u32 sdhc2_base_pmux; 453 u32 sdhc2_base_pmux;
454 u32 iic5_pmux; 454 u32 iic5_pmux;
455 455
456 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}. 456 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
457 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}. 457 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
458 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}. 458 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
459 * Qixis and remote systems are isolated from the I2C1 bus. 459 * Qixis and remote systems are isolated from the I2C1 bus.
460 * Processor connections are still available. 460 * Processor connections are still available.
461 * SPI2 CS2_B controls EN25S64 SPI memory device. 461 * SPI2 CS2_B controls EN25S64 SPI memory device.
462 * SPI3 CS2_B controls EN25S64 SPI memory device. 462 * SPI3 CS2_B controls EN25S64 SPI memory device.
463 * EC2 connects to PHY #2 using RGMII protocol. 463 * EC2 connects to PHY #2 using RGMII protocol.
464 * CLK_OUT connects to FPGA for clock measurement. 464 * CLK_OUT connects to FPGA for clock measurement.
465 */ 465 */
466 466
467 reg5 = QIXIS_READ(brdcfg[5]); 467 reg5 = QIXIS_READ(brdcfg[5]);
468 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40); 468 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
469 QIXIS_WRITE(brdcfg[5], reg5); 469 QIXIS_WRITE(brdcfg[5], reg5);
470 470
471 /* Check RCW field sdhc1_base_pmux 471 /* Check RCW field sdhc1_base_pmux
472 * esdhc0 : sdhc1_base_pmux = 0 472 * esdhc0 : sdhc1_base_pmux = 0
473 * dspi0 : sdhc1_base_pmux = 2 473 * dspi0 : sdhc1_base_pmux = 2
474 */ 474 */
475 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 475 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
476 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; 476 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
477 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; 477 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
478 478
479 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { 479 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
480 reg11 = QIXIS_READ(brdcfg[11]); 480 reg11 = QIXIS_READ(brdcfg[11]);
481 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40); 481 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
482 QIXIS_WRITE(brdcfg[11], reg11); 482 QIXIS_WRITE(brdcfg[11], reg11);
483 } else { 483 } else {
484 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot. 484 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
485 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot. 485 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
486 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot. 486 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
487 */ 487 */
488 reg11 = QIXIS_READ(brdcfg[11]); 488 reg11 = QIXIS_READ(brdcfg[11]);
489 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11); 489 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
490 QIXIS_WRITE(brdcfg[11], reg11); 490 QIXIS_WRITE(brdcfg[11], reg11);
491 } 491 }
492 492
493 /* Check RCW field sdhc2_base_pmux 493 /* Check RCW field sdhc2_base_pmux
494 * esdhc1 : sdhc2_base_pmux = 0 (default) 494 * esdhc1 : sdhc2_base_pmux = 0 (default)
495 * dspi1 : sdhc2_base_pmux = 2 495 * dspi1 : sdhc2_base_pmux = 2
496 */ 496 */
497 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) 497 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
498 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; 498 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
499 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; 499 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
500 500
501 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { 501 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
502 reg13 = QIXIS_READ(brdcfg[13]); 502 reg13 = QIXIS_READ(brdcfg[13]);
503 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01); 503 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
504 QIXIS_WRITE(brdcfg[13], reg13); 504 QIXIS_WRITE(brdcfg[13], reg13);
505 } else { 505 } else {
506 reg13 = QIXIS_READ(brdcfg[13]); 506 reg13 = QIXIS_READ(brdcfg[13]);
507 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00); 507 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
508 QIXIS_WRITE(brdcfg[13], reg13); 508 QIXIS_WRITE(brdcfg[13], reg13);
509 } 509 }
510 510
511 /* Check RCW field IIC5 to enable dspi2 DT nodei 511 /* Check RCW field IIC5 to enable dspi2 DT nodei
512 * dspi2: IIC5 = 3 512 * dspi2: IIC5 = 3
513 */ 513 */
514 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 514 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
515 & FSL_CHASSIS3_IIC5_PMUX_MASK; 515 & FSL_CHASSIS3_IIC5_PMUX_MASK;
516 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; 516 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
517 517
518 if (iic5_pmux == IIC5_PMUX_SPI3) { 518 if (iic5_pmux == IIC5_PMUX_SPI3) {
519 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */ 519 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
520 reg11 = QIXIS_READ(brdcfg[11]); 520 reg11 = QIXIS_READ(brdcfg[11]);
521 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10); 521 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
522 QIXIS_WRITE(brdcfg[11], reg11); 522 QIXIS_WRITE(brdcfg[11], reg11);
523 523
524 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere. 524 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
525 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }. 525 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
526 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}. 526 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
527 */ 527 */
528 reg11 = QIXIS_READ(brdcfg[11]); 528 reg11 = QIXIS_READ(brdcfg[11]);
529 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01); 529 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
530 QIXIS_WRITE(brdcfg[11], reg11); 530 QIXIS_WRITE(brdcfg[11], reg11);
531 } else { 531 } else {
532 /* 532 /*
533 * If {SDHC1_DAT4} has been configured to route to SDHC1_VS, 533 * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
534 * do not change it. 534 * do not change it.
535 * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot. 535 * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
536 */ 536 */
537 reg11 = QIXIS_READ(brdcfg[11]); 537 reg11 = QIXIS_READ(brdcfg[11]);
538 if ((reg11 & 0x30) != 0x30) { 538 if ((reg11 & 0x30) != 0x30) {
539 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00); 539 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
540 QIXIS_WRITE(brdcfg[11], reg11); 540 QIXIS_WRITE(brdcfg[11], reg11);
541 } 541 }
542 542
543 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot. 543 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
544 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot. 544 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
545 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot. 545 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
546 */ 546 */
547 reg11 = QIXIS_READ(brdcfg[11]); 547 reg11 = QIXIS_READ(brdcfg[11]);
548 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00); 548 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
549 QIXIS_WRITE(brdcfg[11], reg11); 549 QIXIS_WRITE(brdcfg[11], reg11);
550 } 550 }
551 551
552 return 0; 552 return 0;
553 } 553 }
554 554
555 int board_early_init_r(void) 555 int board_early_init_r(void)
556 { 556 {
557 esdhc_adapter_card_ident(); 557 esdhc_adapter_card_ident();
558 return 0; 558 return 0;
559 } 559 }
560 #elif defined(CONFIG_TARGET_LX2160ARDB) 560 #elif defined(CONFIG_TARGET_LX2160ARDB)
561 int config_board_mux(void) 561 int config_board_mux(void)
562 { 562 {
563 u8 brdcfg; 563 u8 brdcfg;
564 564
565 brdcfg = QIXIS_READ(brdcfg[4]); 565 brdcfg = QIXIS_READ(brdcfg[4]);
566 /* The BRDCFG4 register controls general board configuration. 566 /* The BRDCFG4 register controls general board configuration.
567 *|-------------------------------------------| 567 *|-------------------------------------------|
568 *|Field | Function | 568 *|Field | Function |
569 *|-------------------------------------------| 569 *|-------------------------------------------|
570 *|5 | CAN I/O Enable (net CFG_CAN_EN_B):| 570 *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
571 *|CAN_EN | 0= CAN transceivers are disabled. | 571 *|CAN_EN | 0= CAN transceivers are disabled. |
572 *| | 1= CAN transceivers are enabled. | 572 *| | 1= CAN transceivers are enabled. |
573 *|-------------------------------------------| 573 *|-------------------------------------------|
574 */ 574 */
575 brdcfg |= BIT_MASK(5); 575 brdcfg |= BIT_MASK(5);
576 QIXIS_WRITE(brdcfg[4], brdcfg); 576 QIXIS_WRITE(brdcfg[4], brdcfg);
577 577
578 return 0; 578 return 0;
579 } 579 }
580 #else 580 #else
581 int config_board_mux(void) 581 int config_board_mux(void)
582 { 582 {
583 return 0; 583 return 0;
584 } 584 }
585 #endif 585 #endif
586 586
587 unsigned long get_board_sys_clk(void) 587 unsigned long get_board_sys_clk(void)
588 { 588 {
589 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 589 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
590 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 590 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
591 591
592 switch (sysclk_conf & 0x03) { 592 switch (sysclk_conf & 0x03) {
593 case QIXIS_SYSCLK_100: 593 case QIXIS_SYSCLK_100:
594 return 100000000; 594 return 100000000;
595 case QIXIS_SYSCLK_125: 595 case QIXIS_SYSCLK_125:
596 return 125000000; 596 return 125000000;
597 case QIXIS_SYSCLK_133: 597 case QIXIS_SYSCLK_133:
598 return 133333333; 598 return 133333333;
599 } 599 }
600 return 100000000; 600 return 100000000;
601 #else 601 #else
602 return 100000000; 602 return 100000000;
603 #endif 603 #endif
604 } 604 }
605 605
606 unsigned long get_board_ddr_clk(void) 606 unsigned long get_board_ddr_clk(void)
607 { 607 {
608 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 608 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
609 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 609 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
610 610
611 switch ((ddrclk_conf & 0x30) >> 4) { 611 switch ((ddrclk_conf & 0x30) >> 4) {
612 case QIXIS_DDRCLK_100: 612 case QIXIS_DDRCLK_100:
613 return 100000000; 613 return 100000000;
614 case QIXIS_DDRCLK_125: 614 case QIXIS_DDRCLK_125:
615 return 125000000; 615 return 125000000;
616 case QIXIS_DDRCLK_133: 616 case QIXIS_DDRCLK_133:
617 return 133333333; 617 return 133333333;
618 } 618 }
619 return 100000000; 619 return 100000000;
620 #else 620 #else
621 return 100000000; 621 return 100000000;
622 #endif 622 #endif
623 } 623 }
624 624
625 int board_init(void) 625 int board_init(void)
626 { 626 {
627 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) 627 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
628 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 628 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
629 #endif 629 #endif
630 #ifdef CONFIG_ENV_IS_NOWHERE 630 #ifdef CONFIG_ENV_IS_NOWHERE
631 gd->env_addr = (ulong)&default_environment[0]; 631 gd->env_addr = (ulong)&default_environment[0];
632 #endif 632 #endif
633 633
634 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 634 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
635 635
636 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) 636 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
637 /* invert AQR107 IRQ pins polarity */ 637 /* invert AQR107 IRQ pins polarity */
638 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); 638 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
639 #endif 639 #endif
640 640
641 #ifdef CONFIG_FSL_CAAM 641 #ifdef CONFIG_FSL_CAAM
642 sec_init(); 642 sec_init();
643 #endif 643 #endif
644 644
645 return 0; 645 return 0;
646 } 646 }
647 647
648 void detail_board_ddr_info(void) 648 void detail_board_ddr_info(void)
649 { 649 {
650 int i; 650 int i;
651 u64 ddr_size = 0; 651 u64 ddr_size = 0;
652 652
653 puts("\nDDR "); 653 puts("\nDDR ");
654 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 654 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
655 ddr_size += gd->bd->bi_dram[i].size; 655 ddr_size += gd->bd->bi_dram[i].size;
656 print_size(ddr_size, ""); 656 print_size(ddr_size, "");
657 print_ddr_info(0); 657 print_ddr_info(0);
658 } 658 }
659 659
660 #ifdef CONFIG_MISC_INIT_R 660 #ifdef CONFIG_MISC_INIT_R
661 int misc_init_r(void) 661 int misc_init_r(void)
662 { 662 {
663 config_board_mux(); 663 config_board_mux();
664 664
665 return 0; 665 return 0;
666 } 666 }
667 #endif 667 #endif
668 668
669 #ifdef CONFIG_FSL_MC_ENET 669 #ifdef CONFIG_FSL_MC_ENET
670 extern int fdt_fixup_board_phy(void *fdt); 670 extern int fdt_fixup_board_phy(void *fdt);
671 671
672 void fdt_fixup_board_enet(void *fdt) 672 void fdt_fixup_board_enet(void *fdt)
673 { 673 {
674 int offset; 674 int offset;
675 675
676 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 676 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
677 677
678 if (offset < 0) 678 if (offset < 0)
679 offset = fdt_path_offset(fdt, "/fsl-mc"); 679 offset = fdt_path_offset(fdt, "/fsl-mc");
680 680
681 if (offset < 0) { 681 if (offset < 0) {
682 printf("%s: fsl-mc node not found in device tree (error %d)\n", 682 printf("%s: fsl-mc node not found in device tree (error %d)\n",
683 __func__, offset); 683 __func__, offset);
684 return; 684 return;
685 } 685 }
686 686
687 if (get_mc_boot_status() == 0 && 687 if (get_mc_boot_status() == 0 &&
688 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { 688 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
689 fdt_status_okay(fdt, offset); 689 fdt_status_okay(fdt, offset);
690 fdt_fixup_board_phy(fdt); 690 fdt_fixup_board_phy(fdt);
691 } else { 691 } else {
692 fdt_status_fail(fdt, offset); 692 fdt_status_fail(fdt, offset);
693 } 693 }
694 } 694 }
695 695
696 void board_quiesce_devices(void) 696 void board_quiesce_devices(void)
697 { 697 {
698 fsl_mc_ldpaa_exit(gd->bd); 698 fsl_mc_ldpaa_exit(gd->bd);
699 } 699 }
700 #endif 700 #endif
701 701
702 #ifdef CONFIG_GIC_V3_ITS 702 #ifdef CONFIG_GIC_V3_ITS
703 void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base) 703 void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
704 { 704 {
705 u32 phandle; 705 u32 phandle;
706 int err; 706 int err;
707 struct fdt_memory gic_lpi; 707 struct fdt_memory gic_lpi;
708 708
709 gic_lpi.start = gic_lpi_base; 709 gic_lpi.start = gic_lpi_base;
710 gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1; 710 gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
711 err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle); 711 err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
712 if (err < 0) 712 if (err < 0)
713 debug("failed to add reserved memory: %d\n", err); 713 debug("failed to add reserved memory: %d\n", err);
714 } 714 }
715 #endif 715 #endif
716 716
717 #ifdef CONFIG_OF_BOARD_SETUP 717 #ifdef CONFIG_OF_BOARD_SETUP
718 int ft_board_setup(void *blob, bd_t *bd) 718 int ft_board_setup(void *blob, bd_t *bd)
719 { 719 {
720 int i; 720 int i;
721 u16 mc_memory_bank = 0; 721 u16 mc_memory_bank = 0;
722 722
723 u64 *base; 723 u64 *base;
724 u64 *size; 724 u64 *size;
725 u64 mc_memory_base = 0; 725 u64 mc_memory_base = 0;
726 u64 mc_memory_size = 0; 726 u64 mc_memory_size = 0;
727 u16 total_memory_banks; 727 u16 total_memory_banks;
728 u64 gic_lpi_base; 728 u64 gic_lpi_base;
729 int ret;
729 730
730 ft_cpu_setup(blob, bd); 731 ft_cpu_setup(blob, bd);
731 732
732 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); 733 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
733 734
734 if (mc_memory_base != 0) 735 if (mc_memory_base != 0)
735 mc_memory_bank++; 736 mc_memory_bank++;
736 737
737 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; 738 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
738 739
739 base = calloc(total_memory_banks, sizeof(u64)); 740 base = calloc(total_memory_banks, sizeof(u64));
740 size = calloc(total_memory_banks, sizeof(u64)); 741 size = calloc(total_memory_banks, sizeof(u64));
741 742
742 /* fixup DT for the three GPP DDR banks */ 743 /* fixup DT for the three GPP DDR banks */
743 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 744 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
744 base[i] = gd->bd->bi_dram[i].start; 745 base[i] = gd->bd->bi_dram[i].start;
745 size[i] = gd->bd->bi_dram[i].size; 746 size[i] = gd->bd->bi_dram[i].size;
746 } 747 }
747 748
748 #ifdef CONFIG_GIC_V3_ITS 749 #ifdef CONFIG_GIC_V3_ITS
749 gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE; 750 gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
750 gic_lpi_tables_init(gic_lpi_base, cpu_numcores()); 751 ret = fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
751 fdt_fixup_gic_lpi_memory(blob, gic_lpi_base); 752 if (!ret && gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
753 debug("%s: failed to init gic-lpi-tables\n", __func__);
752 #endif 754 #endif
753 755
754 #ifdef CONFIG_RESV_RAM 756 #ifdef CONFIG_RESV_RAM
755 /* reduce size if reserved memory is within this bank */ 757 /* reduce size if reserved memory is within this bank */
756 if (gd->arch.resv_ram >= base[0] && 758 if (gd->arch.resv_ram >= base[0] &&
757 gd->arch.resv_ram < base[0] + size[0]) 759 gd->arch.resv_ram < base[0] + size[0])
758 size[0] = gd->arch.resv_ram - base[0]; 760 size[0] = gd->arch.resv_ram - base[0];
759 else if (gd->arch.resv_ram >= base[1] && 761 else if (gd->arch.resv_ram >= base[1] &&
760 gd->arch.resv_ram < base[1] + size[1]) 762 gd->arch.resv_ram < base[1] + size[1])
761 size[1] = gd->arch.resv_ram - base[1]; 763 size[1] = gd->arch.resv_ram - base[1];
762 else if (gd->arch.resv_ram >= base[2] && 764 else if (gd->arch.resv_ram >= base[2] &&
763 gd->arch.resv_ram < base[2] + size[2]) 765 gd->arch.resv_ram < base[2] + size[2])
764 size[2] = gd->arch.resv_ram - base[2]; 766 size[2] = gd->arch.resv_ram - base[2];
765 #endif 767 #endif
766 768
767 if (mc_memory_base != 0) { 769 if (mc_memory_base != 0) {
768 for (i = 0; i <= total_memory_banks; i++) { 770 for (i = 0; i <= total_memory_banks; i++) {
769 if (base[i] == 0 && size[i] == 0) { 771 if (base[i] == 0 && size[i] == 0) {
770 base[i] = mc_memory_base; 772 base[i] = mc_memory_base;
771 size[i] = mc_memory_size; 773 size[i] = mc_memory_size;
772 break; 774 break;
773 } 775 }
774 } 776 }
775 } 777 }
776 778
777 fdt_fixup_memory_banks(blob, base, size, total_memory_banks); 779 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
778 780
779 #ifdef CONFIG_USB 781 #ifdef CONFIG_USB
780 fsl_fdt_fixup_dr_usb(blob, bd); 782 fsl_fdt_fixup_dr_usb(blob, bd);
781 #endif 783 #endif
782 784
783 #ifdef CONFIG_FSL_MC_ENET 785 #ifdef CONFIG_FSL_MC_ENET
784 fdt_fsl_mc_fixup_iommu_map_entry(blob); 786 fdt_fsl_mc_fixup_iommu_map_entry(blob);
785 fdt_fixup_board_enet(blob); 787 fdt_fixup_board_enet(blob);
786 #endif 788 #endif
787 fdt_fixup_icid(blob); 789 fdt_fixup_icid(blob);
788 790
789 return 0; 791 return 0;
790 } 792 }
791 #endif 793 #endif
792 794
793 void qixis_dump_switch(void) 795 void qixis_dump_switch(void)
794 { 796 {
795 int i, nr_of_cfgsw; 797 int i, nr_of_cfgsw;
796 798
797 QIXIS_WRITE(cms[0], 0x00); 799 QIXIS_WRITE(cms[0], 0x00);
798 nr_of_cfgsw = QIXIS_READ(cms[1]); 800 nr_of_cfgsw = QIXIS_READ(cms[1]);
799 801
800 puts("DIP switch settings dump:\n"); 802 puts("DIP switch settings dump:\n");
801 for (i = 1; i <= nr_of_cfgsw; i++) { 803 for (i = 1; i <= nr_of_cfgsw; i++) {
802 QIXIS_WRITE(cms[0], i); 804 QIXIS_WRITE(cms[0], i);
803 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 805 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
804 } 806 }
805 } 807 }
806 808