Commit 90b079c8f989c0e949e2a275e77434aa4e16b8e0
Committed by
Tom Warren
1 parent
6c5be646b4
Exists in
master
and in
53 other branches
Tegra: fdt: tamonten: Add common tamonten.dtsi file from linux
Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Showing 4 changed files with 492 additions and 3 deletions Inline Diff
board/avionic-design/dts/tegra20-medcom-wide.dts
1 | /dts-v1/; | 1 | /dts-v1/; |
2 | 2 | ||
3 | #include "tegra20.dtsi" | 3 | #include "tegra20-tamonten.dtsi" |
4 | 4 | ||
5 | / { | 5 | / { |
6 | model = "Avionic Design Medcom-Wide"; | 6 | model = "Avionic Design Medcom-Wide"; |
7 | compatible = "ad,medcom-wide", "nvidia,tegra20"; | 7 | compatible = "ad,medcom-wide", "nvidia,tegra20"; |
8 | 8 | ||
9 | aliases { | 9 | aliases { |
10 | usb0 = "/usb@c5008000"; | 10 | usb0 = "/usb@c5008000"; |
11 | }; | 11 | }; |
12 | 12 | ||
13 | memory { | 13 | memory { |
14 | reg = <0x00000000 0x20000000>; | 14 | reg = <0x00000000 0x20000000>; |
15 | }; | 15 | }; |
16 | 16 | ||
17 | host1x { | 17 | host1x { |
18 | status = "okay"; | 18 | status = "okay"; |
19 | 19 | ||
20 | dc@54200000 { | 20 | dc@54200000 { |
21 | status = "okay"; | 21 | status = "okay"; |
22 | 22 | ||
23 | rgb { | 23 | rgb { |
24 | nvidia,panel = <&lcd_panel>; | 24 | nvidia,panel = <&lcd_panel>; |
25 | status = "okay"; | 25 | status = "okay"; |
26 | }; | 26 | }; |
27 | }; | 27 | }; |
28 | }; | 28 | }; |
29 | 29 | ||
30 | serial@70006300 { | 30 | serial@70006300 { |
31 | clock-frequency = <216000000>; | 31 | clock-frequency = <216000000>; |
32 | }; | 32 | }; |
33 | 33 | ||
34 | i2c@7000c000 { | 34 | i2c@7000c000 { |
35 | status = "disabled"; | 35 | status = "disabled"; |
36 | }; | 36 | }; |
37 | 37 | ||
38 | i2c@7000c400 { | 38 | i2c@7000c400 { |
39 | status = "disabled"; | 39 | status = "disabled"; |
40 | }; | 40 | }; |
41 | 41 | ||
42 | i2c@7000c500 { | 42 | i2c@7000c500 { |
43 | status = "disabled"; | 43 | status = "disabled"; |
44 | }; | 44 | }; |
45 | 45 | ||
46 | i2c@7000d000 { | 46 | i2c@7000d000 { |
47 | status = "disabled"; | 47 | status = "disabled"; |
48 | }; | 48 | }; |
49 | 49 | ||
50 | usb@c5000000 { | 50 | usb@c5000000 { |
51 | status = "disabled"; | 51 | status = "disabled"; |
52 | }; | 52 | }; |
53 | 53 | ||
54 | usb@c5004000 { | 54 | usb@c5004000 { |
55 | status = "disabled"; | 55 | status = "disabled"; |
56 | }; | 56 | }; |
57 | 57 | ||
58 | lcd_panel: panel { | 58 | lcd_panel: panel { |
59 | clock = <61715000>; | 59 | clock = <61715000>; |
60 | xres = <1366>; | 60 | xres = <1366>; |
61 | yres = <768>; | 61 | yres = <768>; |
62 | left-margin = <2>; | 62 | left-margin = <2>; |
63 | right-margin = <47>; | 63 | right-margin = <47>; |
64 | hsync-len = <136>; | 64 | hsync-len = <136>; |
65 | lower-margin = <21>; | 65 | lower-margin = <21>; |
66 | upper-margin = <11>; | 66 | upper-margin = <11>; |
67 | vsync-len = <4>; | 67 | vsync-len = <4>; |
68 | 68 | ||
69 | nvidia,bits-per-pixel = <16>; | 69 | nvidia,bits-per-pixel = <16>; |
70 | nvidia,pwm = <&pwm 0 500000>; | 70 | nvidia,pwm = <&pwm 0 500000>; |
71 | nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */ | 71 | nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */ |
72 | nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ | 72 | nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ |
73 | nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ | 73 | nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ |
74 | nvidia,panel-timings = <0 0 0 0>; | 74 | nvidia,panel-timings = <0 0 0 0>; |
75 | }; | 75 | }; |
76 | }; | 76 | }; |
77 | 77 |
board/avionic-design/dts/tegra20-plutux.dts
1 | /dts-v1/; | 1 | /dts-v1/; |
2 | 2 | ||
3 | #include "tegra20.dtsi" | 3 | #include "tegra20-tamonten.dtsi" |
4 | 4 | ||
5 | / { | 5 | / { |
6 | model = "Avionic Design Plutux"; | 6 | model = "Avionic Design Plutux"; |
7 | compatible = "ad,plutux", "nvidia,tegra20"; | 7 | compatible = "ad,plutux", "nvidia,tegra20"; |
8 | 8 | ||
9 | aliases { | 9 | aliases { |
10 | usb0 = "/usb@c5008000"; | 10 | usb0 = "/usb@c5008000"; |
11 | }; | 11 | }; |
12 | 12 | ||
13 | memory { | 13 | memory { |
14 | reg = <0x00000000 0x20000000>; | 14 | reg = <0x00000000 0x20000000>; |
15 | }; | 15 | }; |
16 | 16 | ||
17 | serial@70006300 { | 17 | serial@70006300 { |
18 | clock-frequency = <216000000>; | 18 | clock-frequency = <216000000>; |
19 | }; | 19 | }; |
20 | 20 | ||
21 | i2c@7000c000 { | 21 | i2c@7000c000 { |
22 | status = "disabled"; | 22 | status = "disabled"; |
23 | }; | 23 | }; |
24 | 24 | ||
25 | i2c@7000c400 { | 25 | i2c@7000c400 { |
26 | status = "disabled"; | 26 | status = "disabled"; |
27 | }; | 27 | }; |
28 | 28 | ||
29 | i2c@7000c500 { | 29 | i2c@7000c500 { |
30 | status = "disabled"; | 30 | status = "disabled"; |
31 | }; | 31 | }; |
32 | 32 | ||
33 | i2c@7000d000 { | 33 | i2c@7000d000 { |
34 | status = "disabled"; | 34 | status = "disabled"; |
35 | }; | 35 | }; |
36 | 36 | ||
37 | usb@c5000000 { | 37 | usb@c5000000 { |
38 | status = "disabled"; | 38 | status = "disabled"; |
39 | }; | 39 | }; |
40 | 40 | ||
41 | usb@c5004000 { | 41 | usb@c5004000 { |
42 | status = "disabled"; | 42 | status = "disabled"; |
43 | }; | 43 | }; |
44 | }; | 44 | }; |
45 | 45 |
board/avionic-design/dts/tegra20-tamonten.dtsi
File was created | 1 | #include "tegra20.dtsi" | |
2 | |||
3 | / { | ||
4 | model = "Avionic Design Tamonten SOM"; | ||
5 | compatible = "ad,tamonten", "nvidia,tegra20"; | ||
6 | |||
7 | memory { | ||
8 | reg = <0x00000000 0x20000000>; | ||
9 | }; | ||
10 | |||
11 | host1x { | ||
12 | hdmi { | ||
13 | vdd-supply = <&hdmi_vdd_reg>; | ||
14 | pll-supply = <&hdmi_pll_reg>; | ||
15 | |||
16 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | ||
17 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ | ||
18 | }; | ||
19 | }; | ||
20 | |||
21 | pinmux { | ||
22 | pinctrl-names = "default"; | ||
23 | pinctrl-0 = <&state_default>; | ||
24 | |||
25 | state_default: pinmux { | ||
26 | ata { | ||
27 | nvidia,pins = "ata"; | ||
28 | nvidia,function = "ide"; | ||
29 | }; | ||
30 | atb { | ||
31 | nvidia,pins = "atb", "gma", "gme"; | ||
32 | nvidia,function = "sdio4"; | ||
33 | }; | ||
34 | atc { | ||
35 | nvidia,pins = "atc"; | ||
36 | nvidia,function = "nand"; | ||
37 | }; | ||
38 | atd { | ||
39 | nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", | ||
40 | "spia", "spib", "spic"; | ||
41 | nvidia,function = "gmi"; | ||
42 | }; | ||
43 | cdev1 { | ||
44 | nvidia,pins = "cdev1"; | ||
45 | nvidia,function = "plla_out"; | ||
46 | }; | ||
47 | cdev2 { | ||
48 | nvidia,pins = "cdev2"; | ||
49 | nvidia,function = "pllp_out4"; | ||
50 | }; | ||
51 | crtp { | ||
52 | nvidia,pins = "crtp"; | ||
53 | nvidia,function = "crt"; | ||
54 | }; | ||
55 | csus { | ||
56 | nvidia,pins = "csus"; | ||
57 | nvidia,function = "vi_sensor_clk"; | ||
58 | }; | ||
59 | dap1 { | ||
60 | nvidia,pins = "dap1"; | ||
61 | nvidia,function = "dap1"; | ||
62 | }; | ||
63 | dap2 { | ||
64 | nvidia,pins = "dap2"; | ||
65 | nvidia,function = "dap2"; | ||
66 | }; | ||
67 | dap3 { | ||
68 | nvidia,pins = "dap3"; | ||
69 | nvidia,function = "dap3"; | ||
70 | }; | ||
71 | dap4 { | ||
72 | nvidia,pins = "dap4"; | ||
73 | nvidia,function = "dap4"; | ||
74 | }; | ||
75 | dta { | ||
76 | nvidia,pins = "dta", "dtd"; | ||
77 | nvidia,function = "sdio2"; | ||
78 | }; | ||
79 | dtb { | ||
80 | nvidia,pins = "dtb", "dtc", "dte"; | ||
81 | nvidia,function = "rsvd1"; | ||
82 | }; | ||
83 | dtf { | ||
84 | nvidia,pins = "dtf"; | ||
85 | nvidia,function = "i2c3"; | ||
86 | }; | ||
87 | gmc { | ||
88 | nvidia,pins = "gmc"; | ||
89 | nvidia,function = "uartd"; | ||
90 | }; | ||
91 | gpu7 { | ||
92 | nvidia,pins = "gpu7"; | ||
93 | nvidia,function = "rtck"; | ||
94 | }; | ||
95 | gpv { | ||
96 | nvidia,pins = "gpv", "slxa", "slxk"; | ||
97 | nvidia,function = "pcie"; | ||
98 | }; | ||
99 | hdint { | ||
100 | nvidia,pins = "hdint"; | ||
101 | nvidia,function = "hdmi"; | ||
102 | }; | ||
103 | i2cp { | ||
104 | nvidia,pins = "i2cp"; | ||
105 | nvidia,function = "i2cp"; | ||
106 | }; | ||
107 | irrx { | ||
108 | nvidia,pins = "irrx", "irtx"; | ||
109 | nvidia,function = "uarta"; | ||
110 | }; | ||
111 | kbca { | ||
112 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | ||
113 | "kbce", "kbcf"; | ||
114 | nvidia,function = "kbc"; | ||
115 | }; | ||
116 | lcsn { | ||
117 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", | ||
118 | "ld3", "ld4", "ld5", "ld6", "ld7", | ||
119 | "ld8", "ld9", "ld10", "ld11", "ld12", | ||
120 | "ld13", "ld14", "ld15", "ld16", "ld17", | ||
121 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", | ||
122 | "lhs", "lm0", "lm1", "lpp", "lpw0", | ||
123 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", | ||
124 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", | ||
125 | "lvs"; | ||
126 | nvidia,function = "displaya"; | ||
127 | }; | ||
128 | owc { | ||
129 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | ||
130 | nvidia,function = "rsvd2"; | ||
131 | }; | ||
132 | pmc { | ||
133 | nvidia,pins = "pmc"; | ||
134 | nvidia,function = "pwr_on"; | ||
135 | }; | ||
136 | rm { | ||
137 | nvidia,pins = "rm"; | ||
138 | nvidia,function = "i2c1"; | ||
139 | }; | ||
140 | sdb { | ||
141 | nvidia,pins = "sdb", "sdc", "sdd"; | ||
142 | nvidia,function = "pwm"; | ||
143 | }; | ||
144 | sdio1 { | ||
145 | nvidia,pins = "sdio1"; | ||
146 | nvidia,function = "sdio1"; | ||
147 | }; | ||
148 | slxc { | ||
149 | nvidia,pins = "slxc", "slxd"; | ||
150 | nvidia,function = "spdif"; | ||
151 | }; | ||
152 | spid { | ||
153 | nvidia,pins = "spid", "spie", "spif"; | ||
154 | nvidia,function = "spi1"; | ||
155 | }; | ||
156 | spig { | ||
157 | nvidia,pins = "spig", "spih"; | ||
158 | nvidia,function = "spi2_alt"; | ||
159 | }; | ||
160 | uaa { | ||
161 | nvidia,pins = "uaa", "uab", "uda"; | ||
162 | nvidia,function = "ulpi"; | ||
163 | }; | ||
164 | uad { | ||
165 | nvidia,pins = "uad"; | ||
166 | nvidia,function = "irda"; | ||
167 | }; | ||
168 | uca { | ||
169 | nvidia,pins = "uca", "ucb"; | ||
170 | nvidia,function = "uartc"; | ||
171 | }; | ||
172 | conf_ata { | ||
173 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", | ||
174 | "cdev1", "cdev2", "dap1", "dtb", "gma", | ||
175 | "gmb", "gmc", "gmd", "gme", "gpu7", | ||
176 | "gpv", "i2cp", "pta", "rm", "slxa", | ||
177 | "slxk", "spia", "spib", "uac"; | ||
178 | nvidia,pull = <0>; | ||
179 | nvidia,tristate = <0>; | ||
180 | }; | ||
181 | conf_ck32 { | ||
182 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | ||
183 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | ||
184 | nvidia,pull = <0>; | ||
185 | }; | ||
186 | conf_csus { | ||
187 | nvidia,pins = "csus", "spid", "spif"; | ||
188 | nvidia,pull = <1>; | ||
189 | nvidia,tristate = <1>; | ||
190 | }; | ||
191 | conf_crtp { | ||
192 | nvidia,pins = "crtp", "dap2", "dap3", "dap4", | ||
193 | "dtc", "dte", "dtf", "gpu", "sdio1", | ||
194 | "slxc", "slxd", "spdi", "spdo", "spig", | ||
195 | "uda"; | ||
196 | nvidia,pull = <0>; | ||
197 | nvidia,tristate = <1>; | ||
198 | }; | ||
199 | conf_ddc { | ||
200 | nvidia,pins = "ddc", "dta", "dtd", "kbca", | ||
201 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", | ||
202 | "sdc"; | ||
203 | nvidia,pull = <2>; | ||
204 | nvidia,tristate = <0>; | ||
205 | }; | ||
206 | conf_hdint { | ||
207 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | ||
208 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", | ||
209 | "lvp0", "owc", "sdb"; | ||
210 | nvidia,tristate = <1>; | ||
211 | }; | ||
212 | conf_irrx { | ||
213 | nvidia,pins = "irrx", "irtx", "sdd", "spic", | ||
214 | "spie", "spih", "uaa", "uab", "uad", | ||
215 | "uca", "ucb"; | ||
216 | nvidia,pull = <2>; | ||
217 | nvidia,tristate = <1>; | ||
218 | }; | ||
219 | conf_lc { | ||
220 | nvidia,pins = "lc", "ls"; | ||
221 | nvidia,pull = <2>; | ||
222 | }; | ||
223 | conf_ld0 { | ||
224 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | ||
225 | "ld5", "ld6", "ld7", "ld8", "ld9", | ||
226 | "ld10", "ld11", "ld12", "ld13", "ld14", | ||
227 | "ld15", "ld16", "ld17", "ldi", "lhp0", | ||
228 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | ||
229 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", | ||
230 | "lvs", "pmc"; | ||
231 | nvidia,tristate = <0>; | ||
232 | }; | ||
233 | conf_ld17_0 { | ||
234 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | ||
235 | "ld23_22"; | ||
236 | nvidia,pull = <1>; | ||
237 | }; | ||
238 | }; | ||
239 | |||
240 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | ||
241 | ddc { | ||
242 | nvidia,pins = "ddc"; | ||
243 | nvidia,function = "i2c2"; | ||
244 | }; | ||
245 | pta { | ||
246 | nvidia,pins = "pta"; | ||
247 | nvidia,function = "rsvd4"; | ||
248 | }; | ||
249 | }; | ||
250 | |||
251 | state_i2cmux_pta: pinmux_i2cmux_pta { | ||
252 | ddc { | ||
253 | nvidia,pins = "ddc"; | ||
254 | nvidia,function = "rsvd4"; | ||
255 | }; | ||
256 | pta { | ||
257 | nvidia,pins = "pta"; | ||
258 | nvidia,function = "i2c2"; | ||
259 | }; | ||
260 | }; | ||
261 | |||
262 | state_i2cmux_idle: pinmux_i2cmux_idle { | ||
263 | ddc { | ||
264 | nvidia,pins = "ddc"; | ||
265 | nvidia,function = "rsvd4"; | ||
266 | }; | ||
267 | pta { | ||
268 | nvidia,pins = "pta"; | ||
269 | nvidia,function = "rsvd4"; | ||
270 | }; | ||
271 | }; | ||
272 | }; | ||
273 | |||
274 | i2s@70002800 { | ||
275 | status = "okay"; | ||
276 | }; | ||
277 | |||
278 | serial@70006300 { | ||
279 | status = "okay"; | ||
280 | }; | ||
281 | |||
282 | i2c@7000c000 { | ||
283 | clock-frequency = <400000>; | ||
284 | status = "okay"; | ||
285 | }; | ||
286 | |||
287 | i2c@7000c400 { | ||
288 | clock-frequency = <100000>; | ||
289 | status = "okay"; | ||
290 | }; | ||
291 | |||
292 | i2cmux { | ||
293 | compatible = "i2c-mux-pinctrl"; | ||
294 | #address-cells = <1>; | ||
295 | #size-cells = <0>; | ||
296 | |||
297 | i2c-parent = <&{/i2c@7000c400}>; | ||
298 | |||
299 | pinctrl-names = "ddc", "pta", "idle"; | ||
300 | pinctrl-0 = <&state_i2cmux_ddc>; | ||
301 | pinctrl-1 = <&state_i2cmux_pta>; | ||
302 | pinctrl-2 = <&state_i2cmux_idle>; | ||
303 | |||
304 | hdmi_ddc: i2c@0 { | ||
305 | reg = <0>; | ||
306 | #address-cells = <1>; | ||
307 | #size-cells = <0>; | ||
308 | }; | ||
309 | |||
310 | i2c@1 { | ||
311 | reg = <1>; | ||
312 | #address-cells = <1>; | ||
313 | #size-cells = <0>; | ||
314 | }; | ||
315 | }; | ||
316 | |||
317 | i2c@7000d000 { | ||
318 | clock-frequency = <400000>; | ||
319 | status = "okay"; | ||
320 | |||
321 | pmic: tps6586x@34 { | ||
322 | compatible = "ti,tps6586x"; | ||
323 | reg = <0x34>; | ||
324 | interrupts = <0 86 0x4>; | ||
325 | |||
326 | ti,system-power-controller; | ||
327 | |||
328 | #gpio-cells = <2>; | ||
329 | gpio-controller; | ||
330 | |||
331 | sys-supply = <&vdd_5v0_reg>; | ||
332 | vin-sm0-supply = <&sys_reg>; | ||
333 | vin-sm1-supply = <&sys_reg>; | ||
334 | vin-sm2-supply = <&sys_reg>; | ||
335 | vinldo01-supply = <&sm2_reg>; | ||
336 | vinldo23-supply = <&sm2_reg>; | ||
337 | vinldo4-supply = <&sm2_reg>; | ||
338 | vinldo678-supply = <&sm2_reg>; | ||
339 | vinldo9-supply = <&sm2_reg>; | ||
340 | |||
341 | regulators { | ||
342 | sys_reg: sys { | ||
343 | regulator-name = "vdd_sys"; | ||
344 | regulator-always-on; | ||
345 | }; | ||
346 | |||
347 | sm0 { | ||
348 | regulator-name = "vdd_sys_sm0,vdd_core"; | ||
349 | regulator-min-microvolt = <1200000>; | ||
350 | regulator-max-microvolt = <1200000>; | ||
351 | regulator-always-on; | ||
352 | }; | ||
353 | |||
354 | sm1 { | ||
355 | regulator-name = "vdd_sys_sm1,vdd_cpu"; | ||
356 | regulator-min-microvolt = <1000000>; | ||
357 | regulator-max-microvolt = <1000000>; | ||
358 | regulator-always-on; | ||
359 | }; | ||
360 | |||
361 | sm2_reg: sm2 { | ||
362 | regulator-name = "vdd_sys_sm2,vin_ldo*"; | ||
363 | regulator-min-microvolt = <3700000>; | ||
364 | regulator-max-microvolt = <3700000>; | ||
365 | regulator-always-on; | ||
366 | }; | ||
367 | |||
368 | ldo0 { | ||
369 | regulator-name = "vdd_ldo0,vddio_pex_clk"; | ||
370 | regulator-min-microvolt = <3300000>; | ||
371 | regulator-max-microvolt = <3300000>; | ||
372 | }; | ||
373 | |||
374 | ldo1 { | ||
375 | regulator-name = "vdd_ldo1,avdd_pll*"; | ||
376 | regulator-min-microvolt = <1100000>; | ||
377 | regulator-max-microvolt = <1100000>; | ||
378 | regulator-always-on; | ||
379 | }; | ||
380 | |||
381 | ldo2 { | ||
382 | regulator-name = "vdd_ldo2,vdd_rtc"; | ||
383 | regulator-min-microvolt = <1200000>; | ||
384 | regulator-max-microvolt = <1200000>; | ||
385 | }; | ||
386 | |||
387 | ldo3 { | ||
388 | regulator-name = "vdd_ldo3,avdd_usb*"; | ||
389 | regulator-min-microvolt = <3300000>; | ||
390 | regulator-max-microvolt = <3300000>; | ||
391 | regulator-always-on; | ||
392 | }; | ||
393 | |||
394 | ldo4 { | ||
395 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; | ||
396 | regulator-min-microvolt = <1800000>; | ||
397 | regulator-max-microvolt = <1800000>; | ||
398 | regulator-always-on; | ||
399 | }; | ||
400 | |||
401 | ldo5 { | ||
402 | regulator-name = "vdd_ldo5,vcore_mmc"; | ||
403 | regulator-min-microvolt = <2850000>; | ||
404 | regulator-max-microvolt = <2850000>; | ||
405 | }; | ||
406 | |||
407 | ldo6 { | ||
408 | regulator-name = "vdd_ldo6,avdd_vdac"; | ||
409 | /* | ||
410 | * According to the Tegra 2 Automotive | ||
411 | * DataSheet, a typical value for this | ||
412 | * would be 2.8V, but the PMIC only | ||
413 | * supports 2.85V. | ||
414 | */ | ||
415 | regulator-min-microvolt = <2850000>; | ||
416 | regulator-max-microvolt = <2850000>; | ||
417 | }; | ||
418 | |||
419 | hdmi_vdd_reg: ldo7 { | ||
420 | regulator-name = "vdd_ldo7,avdd_hdmi"; | ||
421 | regulator-min-microvolt = <3300000>; | ||
422 | regulator-max-microvolt = <3300000>; | ||
423 | }; | ||
424 | |||
425 | hdmi_pll_reg: ldo8 { | ||
426 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; | ||
427 | regulator-min-microvolt = <1800000>; | ||
428 | regulator-max-microvolt = <1800000>; | ||
429 | }; | ||
430 | |||
431 | ldo9 { | ||
432 | regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; | ||
433 | /* | ||
434 | * According to the Tegra 2 Automotive | ||
435 | * DataSheet, a typical value for this | ||
436 | * would be 2.8V, but the PMIC only | ||
437 | * supports 2.85V. | ||
438 | */ | ||
439 | regulator-min-microvolt = <2850000>; | ||
440 | regulator-max-microvolt = <2850000>; | ||
441 | regulator-always-on; | ||
442 | }; | ||
443 | |||
444 | ldo_rtc { | ||
445 | regulator-name = "vdd_rtc_out"; | ||
446 | regulator-min-microvolt = <3300000>; | ||
447 | regulator-max-microvolt = <3300000>; | ||
448 | regulator-always-on; | ||
449 | }; | ||
450 | }; | ||
451 | }; | ||
452 | |||
453 | temperature-sensor@4c { | ||
454 | compatible = "onnn,nct1008"; | ||
455 | reg = <0x4c>; | ||
456 | }; | ||
457 | }; | ||
458 | |||
459 | pmc { | ||
460 | nvidia,invert-interrupt; | ||
461 | }; | ||
462 | |||
463 | usb@c5008000 { | ||
464 | status = "okay"; | ||
465 | }; | ||
466 | |||
467 | sdhci@c8000600 { | ||
468 | cd-gpios = <&gpio 58 1>; /* gpio PH2 */ | ||
469 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ | ||
470 | bus-width = <4>; | ||
471 | status = "okay"; | ||
472 | }; | ||
473 | |||
474 | regulators { | ||
475 | compatible = "simple-bus"; | ||
476 | |||
477 | #address-cells = <1>; | ||
478 | #size-cells = <0>; | ||
479 | |||
480 | vdd_5v0_reg: regulator@0 { | ||
481 | compatible = "regulator-fixed"; | ||
482 | reg = <0>; | ||
483 | regulator-name = "vdd_5v0"; | ||
484 | regulator-min-microvolt = <5000000>; | ||
485 | regulator-max-microvolt = <5000000>; | ||
486 | regulator-always-on; | ||
487 | }; | ||
488 | }; | ||
489 | }; | ||
490 |
board/avionic-design/dts/tegra20-tec.dts
1 | /dts-v1/; | 1 | /dts-v1/; |
2 | 2 | ||
3 | #include "tegra20.dtsi" | 3 | #include "tegra20-tamonten.dtsi" |
4 | 4 | ||
5 | / { | 5 | / { |
6 | model = "Avionic Design Tamonten Evaluation Carrier"; | 6 | model = "Avionic Design Tamonten Evaluation Carrier"; |
7 | compatible = "ad,tec", "nvidia,tegra20"; | 7 | compatible = "ad,tec", "nvidia,tegra20"; |
8 | 8 | ||
9 | aliases { | 9 | aliases { |
10 | usb0 = "/usb@c5008000"; | 10 | usb0 = "/usb@c5008000"; |
11 | }; | 11 | }; |
12 | 12 | ||
13 | memory { | 13 | memory { |
14 | reg = <0x00000000 0x20000000>; | 14 | reg = <0x00000000 0x20000000>; |
15 | }; | 15 | }; |
16 | 16 | ||
17 | host1x { | 17 | host1x { |
18 | status = "okay"; | 18 | status = "okay"; |
19 | 19 | ||
20 | dc@54200000 { | 20 | dc@54200000 { |
21 | status = "okay"; | 21 | status = "okay"; |
22 | 22 | ||
23 | rgb { | 23 | rgb { |
24 | nvidia,panel = <&lcd_panel>; | 24 | nvidia,panel = <&lcd_panel>; |
25 | status = "okay"; | 25 | status = "okay"; |
26 | }; | 26 | }; |
27 | }; | 27 | }; |
28 | }; | 28 | }; |
29 | 29 | ||
30 | serial@70006300 { | 30 | serial@70006300 { |
31 | clock-frequency = <216000000>; | 31 | clock-frequency = <216000000>; |
32 | }; | 32 | }; |
33 | 33 | ||
34 | nand-controller@70008000 { | 34 | nand-controller@70008000 { |
35 | nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ | 35 | nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ |
36 | nvidia,width = <8>; | 36 | nvidia,width = <8>; |
37 | nvidia,timing = <26 100 20 80 20 10 12 10 70>; | 37 | nvidia,timing = <26 100 20 80 20 10 12 10 70>; |
38 | 38 | ||
39 | nand@0 { | 39 | nand@0 { |
40 | reg = <0>; | 40 | reg = <0>; |
41 | compatible = "hynix,hy27uf4g2b", "nand-flash"; | 41 | compatible = "hynix,hy27uf4g2b", "nand-flash"; |
42 | }; | 42 | }; |
43 | }; | 43 | }; |
44 | 44 | ||
45 | i2c@7000c000 { | 45 | i2c@7000c000 { |
46 | status = "disabled"; | 46 | status = "disabled"; |
47 | }; | 47 | }; |
48 | 48 | ||
49 | i2c@7000c400 { | 49 | i2c@7000c400 { |
50 | status = "disabled"; | 50 | status = "disabled"; |
51 | }; | 51 | }; |
52 | 52 | ||
53 | i2c@7000c500 { | 53 | i2c@7000c500 { |
54 | status = "disabled"; | 54 | status = "disabled"; |
55 | }; | 55 | }; |
56 | 56 | ||
57 | i2c@7000d000 { | 57 | i2c@7000d000 { |
58 | status = "disabled"; | 58 | status = "disabled"; |
59 | }; | 59 | }; |
60 | 60 | ||
61 | usb@c5000000 { | 61 | usb@c5000000 { |
62 | status = "disabled"; | 62 | status = "disabled"; |
63 | }; | 63 | }; |
64 | 64 | ||
65 | usb@c5004000 { | 65 | usb@c5004000 { |
66 | status = "disabled"; | 66 | status = "disabled"; |
67 | }; | 67 | }; |
68 | 68 | ||
69 | lcd_panel: panel { | 69 | lcd_panel: panel { |
70 | clock = <33260000>; | 70 | clock = <33260000>; |
71 | xres = <800>; | 71 | xres = <800>; |
72 | yres = <480>; | 72 | yres = <480>; |
73 | left-margin = <120>; | 73 | left-margin = <120>; |
74 | right-margin = <120>; | 74 | right-margin = <120>; |
75 | hsync-len = <16>; | 75 | hsync-len = <16>; |
76 | lower-margin = <15>; | 76 | lower-margin = <15>; |
77 | upper-margin = <15>; | 77 | upper-margin = <15>; |
78 | vsync-len = <15>; | 78 | vsync-len = <15>; |
79 | 79 | ||
80 | nvidia,bits-per-pixel = <16>; | 80 | nvidia,bits-per-pixel = <16>; |
81 | nvidia,pwm = <&pwm 0 500000>; | 81 | nvidia,pwm = <&pwm 0 500000>; |
82 | nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */ | 82 | nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */ |
83 | nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ | 83 | nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ |
84 | nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ | 84 | nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ |
85 | nvidia,panel-timings = <0 0 0 0>; | 85 | nvidia,panel-timings = <0 0 0 0>; |
86 | }; | 86 | }; |
87 | }; | 87 | }; |
88 | 88 |