Eric Lee / smarc-uboot

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Commit 98d012292495fff1662b107e188bbbb17e32a0f7

Authored by Giuseppe Pagano
Committed by Stefano Babic
1 parent 164d984661
Exists in master and in 52 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

udoo: Add SATA support on uDoo Board. 

Add SATA support on uDoo Board.

Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>

Showing 2 changed files with 16 additions and 0 deletions Inline Diff

1 /* 1 /*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <asm/arch/clock.h> 9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h> 11 #include <asm/arch/iomux.h>
12 #include <malloc.h> 12 #include <malloc.h>
13 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/mx6-pins.h>
14 #include <asm/errno.h> 14 #include <asm/errno.h>
15 #include <asm/gpio.h> 15 #include <asm/gpio.h>
16 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/imx-common/sata.h>
17 #include <mmc.h> 18 #include <mmc.h>
18 #include <fsl_esdhc.h> 19 #include <fsl_esdhc.h>
19 #include <asm/arch/crm_regs.h> 20 #include <asm/arch/crm_regs.h>
20 #include <asm/io.h> 21 #include <asm/io.h>
21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/sys_proto.h>
22 #include <micrel.h> 23 #include <micrel.h>
23 #include <miiphy.h> 24 #include <miiphy.h>
24 #include <netdev.h> 25 #include <netdev.h>
25 26
26 DECLARE_GLOBAL_DATA_PTR; 27 DECLARE_GLOBAL_DATA_PTR;
27 28
28 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 29 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
29 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
30 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
31 32
32 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 33 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
33 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 34 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
34 35
35 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
36 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 37 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 39
39 #define WDT_EN IMX_GPIO_NR(5, 4) 40 #define WDT_EN IMX_GPIO_NR(5, 4)
40 #define WDT_TRG IMX_GPIO_NR(3, 19) 41 #define WDT_TRG IMX_GPIO_NR(3, 19)
41 42
42 int dram_init(void) 43 int dram_init(void)
43 { 44 {
44 gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; 45 gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
45 46
46 return 0; 47 return 0;
47 } 48 }
48 49
49 static iomux_v3_cfg_t const uart2_pads[] = { 50 static iomux_v3_cfg_t const uart2_pads[] = {
50 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 51 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
51 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 52 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
52 }; 53 };
53 54
54 static iomux_v3_cfg_t const usdhc3_pads[] = { 55 static iomux_v3_cfg_t const usdhc3_pads[] = {
55 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 56 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 57 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 58 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 59 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 60 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 61 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 }; 62 };
62 63
63 static iomux_v3_cfg_t const wdog_pads[] = { 64 static iomux_v3_cfg_t const wdog_pads[] = {
64 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 65 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
65 MX6_PAD_EIM_D19__GPIO3_IO19, 66 MX6_PAD_EIM_D19__GPIO3_IO19,
66 }; 67 };
67 68
68 int mx6_rgmii_rework(struct phy_device *phydev) 69 int mx6_rgmii_rework(struct phy_device *phydev)
69 { 70 {
70 /* 71 /*
71 * Bug: Apparently uDoo does not works with Gigabit switches... 72 * Bug: Apparently uDoo does not works with Gigabit switches...
72 * Limiting speed to 10/100Mbps, and setting master mode, seems to 73 * Limiting speed to 10/100Mbps, and setting master mode, seems to
73 * be the only way to have a successfull PHY auto negotiation. 74 * be the only way to have a successfull PHY auto negotiation.
74 * How to fix: Understand why Linux kernel do not have this issue. 75 * How to fix: Understand why Linux kernel do not have this issue.
75 */ 76 */
76 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); 77 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
77 78
78 /* control data pad skew - devaddr = 0x02, register = 0x04 */ 79 /* control data pad skew - devaddr = 0x02, register = 0x04 */
79 ksz9031_phy_extended_write(phydev, 0x02, 80 ksz9031_phy_extended_write(phydev, 0x02,
80 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 81 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
81 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 82 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
82 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ 83 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
83 ksz9031_phy_extended_write(phydev, 0x02, 84 ksz9031_phy_extended_write(phydev, 0x02,
84 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 85 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
85 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 86 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
86 /* tx data pad skew - devaddr = 0x02, register = 0x05 */ 87 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
87 ksz9031_phy_extended_write(phydev, 0x02, 88 ksz9031_phy_extended_write(phydev, 0x02,
88 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 89 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
89 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 90 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
90 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ 91 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
91 ksz9031_phy_extended_write(phydev, 0x02, 92 ksz9031_phy_extended_write(phydev, 0x02,
92 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 93 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
93 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); 94 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
94 return 0; 95 return 0;
95 } 96 }
96 97
97 static iomux_v3_cfg_t const enet_pads1[] = { 98 static iomux_v3_cfg_t const enet_pads1[] = {
98 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 99 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 100 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 101 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 102 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
102 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 103 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
103 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 104 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 105 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
106 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 107 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 108 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
108 /* RGMII reset */ 109 /* RGMII reset */
109 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 110 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
110 /* Ethernet power supply */ 111 /* Ethernet power supply */
111 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), 112 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
112 /* pin 32 - 1 - (MODE0) all */ 113 /* pin 32 - 1 - (MODE0) all */
113 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 114 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
114 /* pin 31 - 1 - (MODE1) all */ 115 /* pin 31 - 1 - (MODE1) all */
115 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 116 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
116 /* pin 28 - 1 - (MODE2) all */ 117 /* pin 28 - 1 - (MODE2) all */
117 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 118 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
118 /* pin 27 - 1 - (MODE3) all */ 119 /* pin 27 - 1 - (MODE3) all */
119 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 120 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
120 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 121 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
121 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), 122 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
122 }; 123 };
123 124
124 static iomux_v3_cfg_t const enet_pads2[] = { 125 static iomux_v3_cfg_t const enet_pads2[] = {
125 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 126 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
126 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 127 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
127 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 128 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
128 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 129 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
129 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 130 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
130 }; 131 };
131 132
132 static void setup_iomux_enet(void) 133 static void setup_iomux_enet(void)
133 { 134 {
134 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 135 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
135 udelay(20); 136 udelay(20);
136 gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */ 137 gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
137 138
138 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */ 139 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
139 140
140 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 141 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
141 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 142 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
142 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 143 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
143 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 144 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
144 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 145 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
145 udelay(1000); 146 udelay(1000);
146 147
147 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */ 148 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
148 149
149 /* Need 100ms delay to exit from reset. */ 150 /* Need 100ms delay to exit from reset. */
150 udelay(1000 * 100); 151 udelay(1000 * 100);
151 152
152 gpio_free(IMX_GPIO_NR(6, 24)); 153 gpio_free(IMX_GPIO_NR(6, 24));
153 gpio_free(IMX_GPIO_NR(6, 25)); 154 gpio_free(IMX_GPIO_NR(6, 25));
154 gpio_free(IMX_GPIO_NR(6, 27)); 155 gpio_free(IMX_GPIO_NR(6, 27));
155 gpio_free(IMX_GPIO_NR(6, 28)); 156 gpio_free(IMX_GPIO_NR(6, 28));
156 gpio_free(IMX_GPIO_NR(6, 29)); 157 gpio_free(IMX_GPIO_NR(6, 29));
157 158
158 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 159 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
159 } 160 }
160 161
161 static void setup_iomux_uart(void) 162 static void setup_iomux_uart(void)
162 { 163 {
163 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 164 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
164 } 165 }
165 166
166 static void setup_iomux_wdog(void) 167 static void setup_iomux_wdog(void)
167 { 168 {
168 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 169 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
169 gpio_direction_output(WDT_TRG, 0); 170 gpio_direction_output(WDT_TRG, 0);
170 gpio_direction_output(WDT_EN, 1); 171 gpio_direction_output(WDT_EN, 1);
171 gpio_direction_input(WDT_TRG); 172 gpio_direction_input(WDT_TRG);
172 } 173 }
173 174
174 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; 175 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
175 176
176 int board_mmc_getcd(struct mmc *mmc) 177 int board_mmc_getcd(struct mmc *mmc)
177 { 178 {
178 return 1; /* Always present */ 179 return 1; /* Always present */
179 } 180 }
180 181
181 int board_eth_init(bd_t *bis) 182 int board_eth_init(bd_t *bis)
182 { 183 {
183 uint32_t base = IMX_FEC_BASE; 184 uint32_t base = IMX_FEC_BASE;
184 struct mii_dev *bus = NULL; 185 struct mii_dev *bus = NULL;
185 struct phy_device *phydev = NULL; 186 struct phy_device *phydev = NULL;
186 int ret; 187 int ret;
187 188
188 setup_iomux_enet(); 189 setup_iomux_enet();
189 190
190 #ifdef CONFIG_FEC_MXC 191 #ifdef CONFIG_FEC_MXC
191 bus = fec_get_miibus(base, -1); 192 bus = fec_get_miibus(base, -1);
192 if (!bus) 193 if (!bus)
193 return 0; 194 return 0;
194 /* scan phy 4,5,6,7 */ 195 /* scan phy 4,5,6,7 */
195 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); 196 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
196 197
197 if (!phydev) { 198 if (!phydev) {
198 free(bus); 199 free(bus);
199 return 0; 200 return 0;
200 } 201 }
201 printf("using phy at %d\n", phydev->addr); 202 printf("using phy at %d\n", phydev->addr);
202 ret = fec_probe(bis, -1, base, bus, phydev); 203 ret = fec_probe(bis, -1, base, bus, phydev);
203 if (ret) { 204 if (ret) {
204 printf("FEC MXC: %s:failed\n", __func__); 205 printf("FEC MXC: %s:failed\n", __func__);
205 free(phydev); 206 free(phydev);
206 free(bus); 207 free(bus);
207 } 208 }
208 #endif 209 #endif
209 return 0; 210 return 0;
210 } 211 }
211 212
212 int board_mmc_init(bd_t *bis) 213 int board_mmc_init(bd_t *bis)
213 { 214 {
214 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 215 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
215 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 216 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
216 usdhc_cfg.max_bus_width = 4; 217 usdhc_cfg.max_bus_width = 4;
217 218
218 return fsl_esdhc_initialize(bis, &usdhc_cfg); 219 return fsl_esdhc_initialize(bis, &usdhc_cfg);
219 } 220 }
220 221
221 int board_early_init_f(void) 222 int board_early_init_f(void)
222 { 223 {
223 setup_iomux_wdog(); 224 setup_iomux_wdog();
224 setup_iomux_uart(); 225 setup_iomux_uart();
225 226
226 return 0; 227 return 0;
227 } 228 }
228 229
229 int board_phy_config(struct phy_device *phydev) 230 int board_phy_config(struct phy_device *phydev)
230 { 231 {
231 mx6_rgmii_rework(phydev); 232 mx6_rgmii_rework(phydev);
232 if (phydev->drv->config) 233 if (phydev->drv->config)
233 phydev->drv->config(phydev); 234 phydev->drv->config(phydev);
234 235
235 return 0; 236 return 0;
236 } 237 }
237 238
238 int board_init(void) 239 int board_init(void)
239 { 240 {
240 /* address of boot parameters */ 241 /* address of boot parameters */
241 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 242 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
242 243
244 #ifdef CONFIG_CMD_SATA
245 setup_sata();
246 #endif
243 return 0; 247 return 0;
244 } 248 }
245 249
246 int checkboard(void) 250 int checkboard(void)
247 { 251 {
248 puts("Board: Udoo\n"); 252 puts("Board: Udoo\n");
249 253
250 return 0; 254 return 0;
251 } 255 }
252 256
include/configs/udoo.h
Diff comments   View file @ 98d0122
1 /* 1 /*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * Configuration settings for Udoo board. 4 * Configuration settings for Udoo board.
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef __CONFIG_H 9 #ifndef __CONFIG_H
10 #define __CONFIG_H 10 #define __CONFIG_H
11 11
12 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/imx-regs.h>
13 #include <asm/imx-common/gpio.h> 13 #include <asm/imx-common/gpio.h>
14 #include <asm/sizes.h> 14 #include <asm/sizes.h>
15 15
16 #define CONFIG_MX6 16 #define CONFIG_MX6
17 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_CPUINFO
18 #define CONFIG_DISPLAY_BOARDINFO 18 #define CONFIG_DISPLAY_BOARDINFO
19 19
20 #define MACH_TYPE_UDOO 4800 20 #define MACH_TYPE_UDOO 4800
21 #define CONFIG_MACH_TYPE MACH_TYPE_UDOO 21 #define CONFIG_MACH_TYPE MACH_TYPE_UDOO
22 22
23 #define CONFIG_CMDLINE_TAG 23 #define CONFIG_CMDLINE_TAG
24 #define CONFIG_SETUP_MEMORY_TAGS 24 #define CONFIG_SETUP_MEMORY_TAGS
25 #define CONFIG_INITRD_TAG 25 #define CONFIG_INITRD_TAG
26 #define CONFIG_REVISION_TAG 26 #define CONFIG_REVISION_TAG
27 27
28 /* Size of malloc() pool */ 28 /* Size of malloc() pool */
29 #define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) 29 #define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
30 30
31 #define CONFIG_BOARD_EARLY_INIT_F 31 #define CONFIG_BOARD_EARLY_INIT_F
32 #define CONFIG_MXC_GPIO 32 #define CONFIG_MXC_GPIO
33 33
34 #define CONFIG_MXC_UART 34 #define CONFIG_MXC_UART
35 #define CONFIG_MXC_UART_BASE UART2_BASE 35 #define CONFIG_MXC_UART_BASE UART2_BASE
36 36
37 /* SATA Configs */
38
39 #define CONFIG_CMD_SATA
40 #ifdef CONFIG_CMD_SATA
41 #define CONFIG_DWC_AHSATA
42 #define CONFIG_SYS_SATA_MAX_DEVICE 1
43 #define CONFIG_DWC_AHSATA_PORT_ID 0
44 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
45 #define CONFIG_LBA48
46 #define CONFIG_LIBATA
47 #endif
48
37 /* Network support */ 49 /* Network support */
38 50
39 #define CONFIG_CMD_PING 51 #define CONFIG_CMD_PING
40 #define CONFIG_CMD_DHCP 52 #define CONFIG_CMD_DHCP
41 #define CONFIG_CMD_MII 53 #define CONFIG_CMD_MII
42 #define CONFIG_CMD_NET 54 #define CONFIG_CMD_NET
43 #define CONFIG_FEC_MXC 55 #define CONFIG_FEC_MXC
44 #define CONFIG_MII 56 #define CONFIG_MII
45 #define IMX_FEC_BASE ENET_BASE_ADDR 57 #define IMX_FEC_BASE ENET_BASE_ADDR
46 #define CONFIG_FEC_XCV_TYPE RGMII 58 #define CONFIG_FEC_XCV_TYPE RGMII
47 #define CONFIG_ETHPRIME "FEC" 59 #define CONFIG_ETHPRIME "FEC"
48 #define CONFIG_FEC_MXC_PHYADDR 6 60 #define CONFIG_FEC_MXC_PHYADDR 6
49 #define CONFIG_PHYLIB 61 #define CONFIG_PHYLIB
50 #define CONFIG_PHY_MICREL 62 #define CONFIG_PHY_MICREL
51 #define CONFIG_PHY_MICREL_KSZ9031 63 #define CONFIG_PHY_MICREL_KSZ9031
52 64
53 /* allow to overwrite serial and ethaddr */ 65 /* allow to overwrite serial and ethaddr */
54 #define CONFIG_ENV_OVERWRITE 66 #define CONFIG_ENV_OVERWRITE
55 #define CONFIG_CONS_INDEX 1 67 #define CONFIG_CONS_INDEX 1
56 #define CONFIG_BAUDRATE 115200 68 #define CONFIG_BAUDRATE 115200
57 69
58 /* Command definition */ 70 /* Command definition */
59 #include <config_cmd_default.h> 71 #include <config_cmd_default.h>
60 72
61 #undef CONFIG_CMD_IMLS 73 #undef CONFIG_CMD_IMLS
62 74
63 #define CONFIG_CMD_BMODE 75 #define CONFIG_CMD_BMODE
64 #define CONFIG_CMD_SETEXPR 76 #define CONFIG_CMD_SETEXPR
65 77
66 #define CONFIG_BOOTDELAY 3 78 #define CONFIG_BOOTDELAY 3
67 79
68 #define CONFIG_SYS_MEMTEST_START 0x10000000 80 #define CONFIG_SYS_MEMTEST_START 0x10000000
69 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) 81 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
70 #define CONFIG_LOADADDR 0x12000000 82 #define CONFIG_LOADADDR 0x12000000
71 #define CONFIG_SYS_TEXT_BASE 0x17800000 83 #define CONFIG_SYS_TEXT_BASE 0x17800000
72 84
73 /* MMC Configuration */ 85 /* MMC Configuration */
74 #define CONFIG_FSL_ESDHC 86 #define CONFIG_FSL_ESDHC
75 #define CONFIG_FSL_USDHC 87 #define CONFIG_FSL_USDHC
76 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 88 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
77 89
78 #define CONFIG_MMC 90 #define CONFIG_MMC
79 #define CONFIG_CMD_MMC 91 #define CONFIG_CMD_MMC
80 #define CONFIG_GENERIC_MMC 92 #define CONFIG_GENERIC_MMC
81 #define CONFIG_BOUNCE_BUFFER 93 #define CONFIG_BOUNCE_BUFFER
82 #define CONFIG_CMD_EXT2 94 #define CONFIG_CMD_EXT2
83 #define CONFIG_CMD_FAT 95 #define CONFIG_CMD_FAT
84 #define CONFIG_DOS_PARTITION 96 #define CONFIG_DOS_PARTITION
85 97
86 #define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb" 98 #define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb"
87 99
88 #define CONFIG_EXTRA_ENV_SETTINGS \ 100 #define CONFIG_EXTRA_ENV_SETTINGS \
89 "script=boot.scr\0" \ 101 "script=boot.scr\0" \
90 "uimage=uImage\0" \ 102 "uimage=uImage\0" \
91 "console=ttymxc1\0" \ 103 "console=ttymxc1\0" \
92 "splashpos=m,m\0" \ 104 "splashpos=m,m\0" \
93 "fdt_high=0xffffffff\0" \ 105 "fdt_high=0xffffffff\0" \
94 "initrd_high=0xffffffff\0" \ 106 "initrd_high=0xffffffff\0" \
95 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ 107 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
96 "fdt_addr=0x11000000\0" \ 108 "fdt_addr=0x11000000\0" \
97 "boot_fdt=try\0" \ 109 "boot_fdt=try\0" \
98 "ip_dyn=yes\0" \ 110 "ip_dyn=yes\0" \
99 "mmcdev=0\0" \ 111 "mmcdev=0\0" \
100 "mmcpart=1\0" \ 112 "mmcpart=1\0" \
101 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ 113 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
102 "update_sd_firmware_filename=u-boot.imx\0" \ 114 "update_sd_firmware_filename=u-boot.imx\0" \
103 "update_sd_firmware=" \ 115 "update_sd_firmware=" \
104 "if test ${ip_dyn} = yes; then " \ 116 "if test ${ip_dyn} = yes; then " \
105 "setenv get_cmd dhcp; " \ 117 "setenv get_cmd dhcp; " \
106 "else " \ 118 "else " \
107 "setenv get_cmd tftp; " \ 119 "setenv get_cmd tftp; " \
108 "fi; " \ 120 "fi; " \
109 "if mmc dev ${mmcdev}; then " \ 121 "if mmc dev ${mmcdev}; then " \
110 "if ${get_cmd} ${update_sd_firmware_filename}; then " \ 122 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
111 "setexpr fw_sz ${filesize} / 0x200; " \ 123 "setexpr fw_sz ${filesize} / 0x200; " \
112 "setexpr fw_sz ${fw_sz} + 1; " \ 124 "setexpr fw_sz ${fw_sz} + 1; " \
113 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ 125 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
114 "fi; " \ 126 "fi; " \
115 "fi\0" \ 127 "fi\0" \
116 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 128 "mmcargs=setenv bootargs console=${console},${baudrate} " \
117 "root=${mmcroot}\0" \ 129 "root=${mmcroot}\0" \
118 "loadbootscript=" \ 130 "loadbootscript=" \
119 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 131 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
120 "bootscript=echo Running bootscript from mmc ...; " \ 132 "bootscript=echo Running bootscript from mmc ...; " \
121 "source\0" \ 133 "source\0" \
122 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ 134 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
123 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 135 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
124 "mmcboot=echo Booting from mmc ...; " \ 136 "mmcboot=echo Booting from mmc ...; " \
125 "run mmcargs; " \ 137 "run mmcargs; " \
126 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 138 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
127 "if run loadfdt; then " \ 139 "if run loadfdt; then " \
128 "bootm ${loadaddr} - ${fdt_addr}; " \ 140 "bootm ${loadaddr} - ${fdt_addr}; " \
129 "else " \ 141 "else " \
130 "if test ${boot_fdt} = try; then " \ 142 "if test ${boot_fdt} = try; then " \
131 "bootm; " \ 143 "bootm; " \
132 "else " \ 144 "else " \
133 "echo WARN: Cannot load the DT; " \ 145 "echo WARN: Cannot load the DT; " \
134 "fi; " \ 146 "fi; " \
135 "fi; " \ 147 "fi; " \
136 "else " \ 148 "else " \
137 "bootm; " \ 149 "bootm; " \
138 "fi;\0" \ 150 "fi;\0" \
139 "netargs=setenv bootargs console=${console},${baudrate} " \ 151 "netargs=setenv bootargs console=${console},${baudrate} " \
140 "root=/dev/nfs " \ 152 "root=/dev/nfs " \
141 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 153 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
142 "netboot=echo Booting from net ...; " \ 154 "netboot=echo Booting from net ...; " \
143 "run netargs; " \ 155 "run netargs; " \
144 "if test ${ip_dyn} = yes; then " \ 156 "if test ${ip_dyn} = yes; then " \
145 "setenv get_cmd dhcp; " \ 157 "setenv get_cmd dhcp; " \
146 "else " \ 158 "else " \
147 "setenv get_cmd tftp; " \ 159 "setenv get_cmd tftp; " \
148 "fi; " \ 160 "fi; " \
149 "${get_cmd} ${uimage}; " \ 161 "${get_cmd} ${uimage}; " \
150 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 162 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
151 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 163 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
152 "bootm ${loadaddr} - ${fdt_addr}; " \ 164 "bootm ${loadaddr} - ${fdt_addr}; " \
153 "else " \ 165 "else " \
154 "if test ${boot_fdt} = try; then " \ 166 "if test ${boot_fdt} = try; then " \
155 "bootm; " \ 167 "bootm; " \
156 "else " \ 168 "else " \
157 "echo WARN: Cannot load the DT; " \ 169 "echo WARN: Cannot load the DT; " \
158 "fi; " \ 170 "fi; " \
159 "fi; " \ 171 "fi; " \
160 "else " \ 172 "else " \
161 "bootm; " \ 173 "bootm; " \
162 "fi;\0" 174 "fi;\0"
163 175
164 #define CONFIG_BOOTCOMMAND \ 176 #define CONFIG_BOOTCOMMAND \
165 "mmc dev ${mmcdev}; if mmc rescan; then " \ 177 "mmc dev ${mmcdev}; if mmc rescan; then " \
166 "if run loadbootscript; then " \ 178 "if run loadbootscript; then " \
167 "run bootscript; " \ 179 "run bootscript; " \
168 "else " \ 180 "else " \
169 "if run loaduimage; then " \ 181 "if run loaduimage; then " \
170 "run mmcboot; " \ 182 "run mmcboot; " \
171 "else run netboot; " \ 183 "else run netboot; " \
172 "fi; " \ 184 "fi; " \
173 "fi; " \ 185 "fi; " \
174 "else run netboot; fi" 186 "else run netboot; fi"
175 187
176 /* Miscellaneous configurable options */ 188 /* Miscellaneous configurable options */
177 #define CONFIG_SYS_LONGHELP 189 #define CONFIG_SYS_LONGHELP
178 #define CONFIG_SYS_HUSH_PARSER 190 #define CONFIG_SYS_HUSH_PARSER
179 #define CONFIG_SYS_PROMPT "=> " 191 #define CONFIG_SYS_PROMPT "=> "
180 #define CONFIG_AUTO_COMPLETE 192 #define CONFIG_AUTO_COMPLETE
181 #define CONFIG_SYS_CBSIZE 256 193 #define CONFIG_SYS_CBSIZE 256
182 194
183 /* Print Buffer Size */ 195 /* Print Buffer Size */
184 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 196 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
185 #define CONFIG_SYS_MAXARGS 16 197 #define CONFIG_SYS_MAXARGS 16
186 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 198 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
187 199
188 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 200 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
189 #define CONFIG_SYS_HZ 1000 201 #define CONFIG_SYS_HZ 1000
190 202
191 #define CONFIG_CMDLINE_EDITING 203 #define CONFIG_CMDLINE_EDITING
192 204
193 /* Physical Memory Map */ 205 /* Physical Memory Map */
194 #define CONFIG_NR_DRAM_BANKS 1 206 #define CONFIG_NR_DRAM_BANKS 1
195 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 207 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
196 208
197 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 209 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
198 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 210 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
199 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 211 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
200 212
201 #define CONFIG_SYS_INIT_SP_OFFSET \ 213 #define CONFIG_SYS_INIT_SP_OFFSET \
202 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 214 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
203 #define CONFIG_SYS_INIT_SP_ADDR \ 215 #define CONFIG_SYS_INIT_SP_ADDR \
204 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 216 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
205 217
206 /* FLASH and environment organization */ 218 /* FLASH and environment organization */
207 #define CONFIG_SYS_NO_FLASH 219 #define CONFIG_SYS_NO_FLASH
208 220
209 #define CONFIG_ENV_SIZE (8 * 1024) 221 #define CONFIG_ENV_SIZE (8 * 1024)
210 222
211 #define CONFIG_ENV_IS_IN_MMC 223 #define CONFIG_ENV_IS_IN_MMC
212 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 224 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
213 #define CONFIG_SYS_MMC_ENV_DEV 0 225 #define CONFIG_SYS_MMC_ENV_DEV 0
214 226
215 #define CONFIG_OF_LIBFDT 227 #define CONFIG_OF_LIBFDT
216 #define CONFIG_CMD_BOOTZ 228 #define CONFIG_CMD_BOOTZ
217 229
218 #ifndef CONFIG_SYS_DCACHE_OFF 230 #ifndef CONFIG_SYS_DCACHE_OFF
219 #define CONFIG_CMD_CACHE 231 #define CONFIG_CMD_CACHE
220 #endif 232 #endif
221 233
222 #endif /* __CONFIG_H * */ 234 #endif /* __CONFIG_H * */
223 235