Eric Lee / smarc-uboot | Embedian Git Server

Commit 9920d151c4b22540a937c4225020069c583a7fad

Authored by Tuomas Tynkkynen 2017-12-08 21:36:17 +0800

Committed by Tom Rini 2017-12-13 03:05:48 +0800

ata: Migrate CONFIG_FSL_SATA to Kconfig

Use 'imply' here liberally to avoid the combinatorial explosion of
defconfig changes in the PowerPC boards.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>

Showing 26 changed files with 24 additions and 20 deletions Inline Diff

arch/powerpc/cpu/mpc83xx/Kconfig
arch/powerpc/cpu/mpc85xx/Kconfig
configs/MPC8315ERDB_defconfig
configs/MPC837XERDB_defconfig
configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
configs/controlcenterd_36BIT_SDCARD_defconfig
drivers/ata/Kconfig
include/configs/MPC8315ERDB.h
include/configs/MPC837XEMDS.h
include/configs/MPC837XERDB.h
include/configs/MPC8536DS.h
include/configs/P1010RDB.h
include/configs/P1022DS.h
include/configs/P2041RDB.h
include/configs/T102xQDS.h
include/configs/T1040QDS.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240QDS.h
include/configs/T4240RDB.h
include/configs/controlcenterd.h
include/configs/corenet_ds.h
include/configs/cyrus.h
include/configs/t4qds.h
scripts/config_whitelist.txt

arch/powerpc/cpu/mpc83xx/Kconfig

Diff comments View file @ 9920d15

 menu "mpc83xx CPU"
 	depends on MPC83xx
 config SYS_CPU
 	default "mpc83xx"
 choice
 	prompt "Target select"
 	optional
 config TARGET_MPC8308_P1M
 	bool "Support mpc8308_p1m"
 config TARGET_SBC8349
 	bool "Support sbc8349"
 config TARGET_VE8313
 	bool "Support ve8313"
 config TARGET_VME8349
 	bool "Support vme8349"
 config TARGET_MPC8308RDB
 	bool "Support MPC8308RDB"
 	select SYS_FSL_ERRATUM_ESDHC111
 config TARGET_MPC8313ERDB
 	bool "Support MPC8313ERDB"
 	select SUPPORT_SPL
 	select BOARD_EARLY_INIT_F
 config TARGET_MPC8315ERDB
 	bool "Support MPC8315ERDB"
 	select BOARD_EARLY_INIT_F
 config TARGET_MPC8323ERDB
 	bool "Support MPC8323ERDB"
 config TARGET_MPC832XEMDS
 	bool "Support MPC832XEMDS"
 	select BOARD_EARLY_INIT_F
 config TARGET_MPC8349EMDS
 	bool "Support MPC8349EMDS"
 	select SYS_FSL_DDR
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_DDR_BE
 	select BOARD_EARLY_INIT_F
 config TARGET_MPC8349ITX
 	bool "Support MPC8349ITX"
 	imply CMD_IRQ
 config TARGET_MPC837XEMDS
 	bool "Support MPC837XEMDS"
 	select BOARD_EARLY_INIT_F
 	imply CMD_SATA
+	imply FSL_SATA
 config TARGET_MPC837XERDB
 	bool "Support MPC837XERDB"
 	select BOARD_EARLY_INIT_F
 config TARGET_IDS8313
 	bool "Support ids8313"
 	select DM
 config TARGET_KM8360
 	bool "Support km8360"
 	imply CMD_CRAMFS
 	imply CMD_DIAG
 	imply FS_CRAMFS
 config TARGET_SUVD3
 	bool "Support suvd3"
 	imply CMD_CRAMFS
 	imply FS_CRAMFS
 config TARGET_TUXX1
 	bool "Support tuxx1"
 	imply CMD_CRAMFS
 	imply FS_CRAMFS
 config TARGET_TQM834X
 	bool "Support TQM834x"
 config TARGET_HRCON
 	bool "Support hrcon"
 	select SYS_FSL_ERRATUM_ESDHC111
 config TARGET_STRIDER
 	bool "Support strider"
 	select SYS_FSL_ERRATUM_ESDHC111
 	imply CMD_PCA953X
 endchoice
 source "board/esd/vme8349/Kconfig"
 source "board/freescale/mpc8308rdb/Kconfig"
 source "board/freescale/mpc8313erdb/Kconfig"
 source "board/freescale/mpc8315erdb/Kconfig"
 source "board/freescale/mpc8323erdb/Kconfig"
 source "board/freescale/mpc832xemds/Kconfig"
 source "board/freescale/mpc8349emds/Kconfig"
 source "board/freescale/mpc8349itx/Kconfig"
 source "board/freescale/mpc837xemds/Kconfig"
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/ids/ids8313/Kconfig"
 source "board/keymile/km83xx/Kconfig"
 source "board/mpc8308_p1m/Kconfig"
 source "board/sbc8349/Kconfig"
 source "board/tqc/tqm834x/Kconfig"
 source "board/ve8313/Kconfig"
 source "board/gdsys/mpc8308/Kconfig"
 endmenu

arch/powerpc/cpu/mpc85xx/Kconfig

Diff comments View file @ 9920d15

 menu "mpc85xx CPU"
 	depends on MPC85xx
 config SYS_CPU
 	default "mpc85xx"
 config CMD_ERRATA
 	bool "Enable the 'errata' command"
 	depends on MPC85xx
 	default y
 	help
 	  This enables the 'errata' command which displays a list of errata
 	  work-arounds which are enabled for the current board.
 choice
 	prompt "Target select"
 	optional
 config TARGET_SBC8548
 	bool "Support sbc8548"
 	select ARCH_MPC8548
 config TARGET_SOCRATES
 	bool "Support socrates"
 	select ARCH_MPC8544
 config TARGET_B4420QDS
 	bool "Support B4420QDS"
 	select ARCH_B4420
 	select SUPPORT_SPL
 	select PHYS_64BIT
 config TARGET_B4860QDS
 	bool "Support B4860QDS"
 	select ARCH_B4860
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 config TARGET_BSC9131RDB
 	bool "Support BSC9131RDB"
 	select ARCH_BSC9131
 	select SUPPORT_SPL
 	select BOARD_EARLY_INIT_F
 config TARGET_BSC9132QDS
 	bool "Support BSC9132QDS"
 	select ARCH_BSC9132
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select BOARD_EARLY_INIT_F
 config TARGET_C29XPCIE
 	bool "Support C29XPCIE"
 	select ARCH_C29X
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select PHYS_64BIT
 config TARGET_P3041DS
 	bool "Support P3041DS"
 	select PHYS_64BIT
 	select ARCH_P3041
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
 config TARGET_P4080DS
 	bool "Support P4080DS"
 	select PHYS_64BIT
 	select ARCH_P4080
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
 config TARGET_P5020DS
 	bool "Support P5020DS"
 	select PHYS_64BIT
 	select ARCH_P5020
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
 config TARGET_P5040DS
 	bool "Support P5040DS"
 	select PHYS_64BIT
 	select ARCH_P5040
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
 config TARGET_MPC8536DS
 	bool "Support MPC8536DS"
 	select ARCH_MPC8536
 # Use DDR3 controller with DDR2 DIMMs on this board
 	select SYS_FSL_DDRC_GEN3
 	imply CMD_SATA
+	imply FSL_SATA
 config TARGET_MPC8541CDS
 	bool "Support MPC8541CDS"
 	select ARCH_MPC8541
 config TARGET_MPC8544DS
 	bool "Support MPC8544DS"
 	select ARCH_MPC8544
 config TARGET_MPC8548CDS
 	bool "Support MPC8548CDS"
 	select ARCH_MPC8548
 config TARGET_MPC8555CDS
 	bool "Support MPC8555CDS"
 	select ARCH_MPC8555
 config TARGET_MPC8568MDS
 	bool "Support MPC8568MDS"
 	select ARCH_MPC8568
 config TARGET_MPC8569MDS
 	bool "Support MPC8569MDS"
 	select ARCH_MPC8569
 config TARGET_MPC8572DS
 	bool "Support MPC8572DS"
 	select ARCH_MPC8572
 # Use DDR3 controller with DDR2 DIMMs on this board
 	select SYS_FSL_DDRC_GEN3
 	imply SCSI
 config TARGET_P1010RDB_PA
 	bool "Support P1010RDB_PA"
 	select ARCH_P1010
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	imply CMD_EEPROM
 	imply CMD_SATA
 config TARGET_P1010RDB_PB
 	bool "Support P1010RDB_PB"
 	select ARCH_P1010
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	imply CMD_EEPROM
 	imply CMD_SATA
 config TARGET_P1022DS
 	bool "Support P1022DS"
 	select ARCH_P1022
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	imply CMD_SATA
+	imply FSL_SATA
 config TARGET_P1023RDB
 	bool "Support P1023RDB"
 	select ARCH_P1023
 	imply CMD_EEPROM
 config TARGET_P1020MBG
 	bool "Support P1020MBG-PC"
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
 config TARGET_P1020RDB_PC
 	bool "Support P1020RDB-PC"
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
 config TARGET_P1020RDB_PD
 	bool "Support P1020RDB-PD"
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
 config TARGET_P1020UTM
 	bool "Support P1020UTM"
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
 config TARGET_P1021RDB
 	bool "Support P1021RDB"
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select ARCH_P1021
 	imply CMD_EEPROM
 	imply CMD_SATA
 config TARGET_P1024RDB
 	bool "Support P1024RDB"
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select ARCH_P1024
 	imply CMD_EEPROM
 	imply CMD_SATA
 config TARGET_P1025RDB
 	bool "Support P1025RDB"
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select ARCH_P1025
 	imply CMD_EEPROM
 	imply CMD_SATA
 	imply SATA_SIL
 config TARGET_P2020RDB
 	bool "Support P2020RDB-PC"
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select ARCH_P2020
 	imply CMD_EEPROM
 	imply CMD_SATA
 	imply SATA_SIL
 config TARGET_P1_TWR
 	bool "Support p1_twr"
 	select ARCH_P1025
 config TARGET_P2041RDB
 	bool "Support P2041RDB"
 	select ARCH_P2041
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply FSL_SATA
 config TARGET_QEMU_PPCE500
 	bool "Support qemu-ppce500"
 	select ARCH_QEMU_E500
 	select PHYS_64BIT
 config TARGET_T1024QDS
 	bool "Support T1024QDS"
 	select ARCH_T1024
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply FSL_SATA
 config TARGET_T1023RDB
 	bool "Support T1023RDB"
 	select ARCH_T1023
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_EEPROM
 config TARGET_T1024RDB
 	bool "Support T1024RDB"
 	select ARCH_T1024
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_EEPROM
 config TARGET_T1040QDS
 	bool "Support T1040QDS"
 	select ARCH_T1040
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select PHYS_64BIT
 	imply CMD_EEPROM
 	imply CMD_SATA
 config TARGET_T1040RDB
 	bool "Support T1040RDB"
 	select ARCH_T1040
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_T1040D4RDB
 	bool "Support T1040D4RDB"
 	select ARCH_T1040
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_T1042RDB
 	bool "Support T1042RDB"
 	select ARCH_T1042
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_T1042D4RDB
 	bool "Support T1042D4RDB"
 	select ARCH_T1042
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_T1042RDB_PI
 	bool "Support T1042RDB_PI"
 	select ARCH_T1042
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_T2080QDS
 	bool "Support T2080QDS"
 	select ARCH_T2080
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_T2080RDB
 	bool "Support T2080RDB"
 	select ARCH_T2080
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_T2081QDS
 	bool "Support T2081QDS"
 	select ARCH_T2081
 	select SUPPORT_SPL
 	select PHYS_64BIT
 config TARGET_T4160QDS
 	bool "Support T4160QDS"
 	select ARCH_T4160
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_T4160RDB
 	bool "Support T4160RDB"
 	select ARCH_T4160
 	select SUPPORT_SPL
 	select PHYS_64BIT
 config TARGET_T4240QDS
 	bool "Support T4240QDS"
 	select ARCH_T4240
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_T4240RDB
 	bool "Support T4240RDB"
 	select ARCH_T4240
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
 config TARGET_CONTROLCENTERD
 	bool "Support controlcenterd"
 	select ARCH_P1022
 config TARGET_KMP204X
 	bool "Support kmp204x"
 	select ARCH_P2041
 	select PHYS_64BIT
 	imply CMD_CRAMFS
 	imply FS_CRAMFS
 config TARGET_XPEDITE520X
 	bool "Support xpedite520x"
 	select ARCH_MPC8548
 config TARGET_XPEDITE537X
 	bool "Support xpedite537x"
 	select ARCH_MPC8572
 # Use DDR3 controller with DDR2 DIMMs on this board
 	select SYS_FSL_DDRC_GEN3
 config TARGET_XPEDITE550X
 	bool "Support xpedite550x"
 	select ARCH_P2020
 config TARGET_UCP1020
 	bool "Support uCP1020"
 	select ARCH_P1020
 	imply CMD_SATA
 config TARGET_CYRUS_P5020
 	bool "Support Varisys Cyrus P5020"
 	select ARCH_P5020
 	select PHYS_64BIT
 config TARGET_CYRUS_P5040
 	 bool "Support Varisys Cyrus P5040"
 	select ARCH_P5040
 	select PHYS_64BIT
 endchoice
 config ARCH_B4420
 	bool
 	select E500MC
 	select E6500
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A005871
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006384
 	select SYS_FSL_ERRATUM_A006475
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007075
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007212
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_EEPROM
 	imply CMD_NAND
 	imply CMD_REGINFO
 config ARCH_B4860
 	bool
 	select E500MC
 	select E6500
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A005871
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006384
 	select SYS_FSL_ERRATUM_A006475
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007075
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007212
 	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_EEPROM
 	imply CMD_NAND
 	imply CMD_REGINFO
 config ARCH_BSC9131
 	bool
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_44
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select FSL_IFC
 	imply CMD_EEPROM
 	imply CMD_NAND
 	imply CMD_REGINFO
 config ARCH_BSC9132
 	bool
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_46
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_A005434
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_I2C_A004447
 	select SYS_FSL_ERRATUM_IFC_A002769
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_IFC
 	imply CMD_EEPROM
 	imply CMD_MTDPARTS
 	imply CMD_NAND
 	imply CMD_PCI
 	imply CMD_REGINFO
 config ARCH_C29X
 	bool
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_46
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_6
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_IFC
 	imply CMD_NAND
 	imply CMD_PCI
 	imply CMD_REGINFO
 config ARCH_MPC8536
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_REGINFO
 config ARCH_MPC8540
 	bool
 	select FSL_LAW
 	select SYS_FSL_HAS_DDR1
 config ARCH_MPC8541
 	bool
 	select FSL_LAW
 	select SYS_FSL_HAS_DDR1
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 config ARCH_MPC8544
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 config ARCH_MPC8548
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_NMG_DDR120
 	select SYS_FSL_ERRATUM_NMG_LBC103
 	select SYS_FSL_ERRATUM_NMG_ETSEC129
 	select SYS_FSL_ERRATUM_I2C_A004447
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_DDR1
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	imply CMD_REGINFO
 config ARCH_MPC8555
 	bool
 	select FSL_LAW
 	select SYS_FSL_HAS_DDR1
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 config ARCH_MPC8560
 	bool
 	select FSL_LAW
 	select SYS_FSL_HAS_DDR1
 config ARCH_MPC8568
 	bool
 	select FSL_LAW
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 config ARCH_MPC8569
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select FSL_ELBC
 	imply CMD_NAND
 config ARCH_MPC8572
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_DDR_115
 	select SYS_FSL_ERRATUM_DDR111_DDR134
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 	imply CMD_NAND
 config ARCH_P1010
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_A006261
 	select SYS_FSL_ERRATUM_A007075
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_I2C_A004447
 	select SYS_FSL_ERRATUM_IFC_A002769
 	select SYS_FSL_ERRATUM_P1010_A003549
 	select SYS_FSL_ERRATUM_SEC_A003571
 	select SYS_FSL_ERRATUM_IFC_A003399
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_IFC
 	imply CMD_EEPROM
 	imply CMD_MTDPARTS
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_PCI
 	imply CMD_REGINFO
+	imply FSL_SATA
 config ARCH_P1011
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 config ARCH_P1020
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_PCI
 	imply CMD_REGINFO
 	imply SATA_SIL
 config ARCH_P1021
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 	imply CMD_REGINFO
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_REGINFO
 	imply SATA_SIL
 config ARCH_P1022
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_SATA_A001
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 config ARCH_P1023
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_I2C_A004447
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select FSL_ELBC
 config ARCH_P1024
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 	imply CMD_EEPROM
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_PCI
 	imply CMD_REGINFO
 	imply SATA_SIL
 config ARCH_P1025
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 	imply CMD_SATA
 	imply CMD_REGINFO
 config ARCH_P2020
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_ESDHC_A001
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_ELBC
 	imply CMD_EEPROM
 	imply CMD_NAND
 	imply CMD_REGINFO
 config ARCH_P2041
 	bool
 	select E500MC
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A004849
 	select SYS_FSL_ERRATUM_A006261
 	select SYS_FSL_ERRATUM_CPU_A003999
 	select SYS_FSL_ERRATUM_DDR_A003
 	select SYS_FSL_ERRATUM_DDR_A003474
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_I2C_A004447
 	select SYS_FSL_ERRATUM_NMG_CPU_A011
 	select SYS_FSL_ERRATUM_SRIO_A004034
 	select SYS_FSL_ERRATUM_USB14
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS1
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select FSL_ELBC
 	imply CMD_NAND
 config ARCH_P3041
 	bool
 	select E500MC
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_44
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A004849
 	select SYS_FSL_ERRATUM_A005812
 	select SYS_FSL_ERRATUM_A006261
 	select SYS_FSL_ERRATUM_CPU_A003999
 	select SYS_FSL_ERRATUM_DDR_A003
 	select SYS_FSL_ERRATUM_DDR_A003474
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_I2C_A004447
 	select SYS_FSL_ERRATUM_NMG_CPU_A011
 	select SYS_FSL_ERRATUM_SRIO_A004034
 	select SYS_FSL_ERRATUM_USB14
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS1
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select FSL_ELBC
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 config ARCH_P4080
 	bool
 	select E500MC
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_44
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A004580
 	select SYS_FSL_ERRATUM_A004849
 	select SYS_FSL_ERRATUM_A005812
 	select SYS_FSL_ERRATUM_A007075
 	select SYS_FSL_ERRATUM_CPC_A002
 	select SYS_FSL_ERRATUM_CPC_A003
 	select SYS_FSL_ERRATUM_CPU_A003999
 	select SYS_FSL_ERRATUM_DDR_A003
 	select SYS_FSL_ERRATUM_DDR_A003474
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_ESDHC13
 	select SYS_FSL_ERRATUM_ESDHC135
 	select SYS_FSL_ERRATUM_I2C_A004447
 	select SYS_FSL_ERRATUM_NMG_CPU_A011
 	select SYS_FSL_ERRATUM_SRIO_A004034
 	select SYS_P4080_ERRATUM_CPU22
 	select SYS_P4080_ERRATUM_PCIE_A003
 	select SYS_P4080_ERRATUM_SERDES8
 	select SYS_P4080_ERRATUM_SERDES9
 	select SYS_P4080_ERRATUM_SERDES_A001
 	select SYS_P4080_ERRATUM_SERDES_A005
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS1
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select FSL_ELBC
 	imply CMD_SATA
 	imply CMD_REGINFO
 	imply SATA_SIL
 config ARCH_P5020
 	bool
 	select E500MC
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_44
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A006261
 	select SYS_FSL_ERRATUM_DDR_A003
 	select SYS_FSL_ERRATUM_DDR_A003474
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_I2C_A004447
 	select SYS_FSL_ERRATUM_SRIO_A004034
 	select SYS_FSL_ERRATUM_USB14
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS1
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_ELBC
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 config ARCH_P5040
 	bool
 	select E500MC
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_44
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A004699
 	select SYS_FSL_ERRATUM_A005812
 	select SYS_FSL_ERRATUM_A006261
 	select SYS_FSL_ERRATUM_DDR_A003
 	select SYS_FSL_ERRATUM_DDR_A003474
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_USB14
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS1
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_ELBC
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 config ARCH_QEMU_E500
 	bool
 config ARCH_T1023
 	bool
 	select E500MC
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008378
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
 	select FSL_IFC
 	imply CMD_EEPROM
 	imply CMD_NAND
 	imply CMD_REGINFO
 config ARCH_T1024
 	bool
 	select E500MC
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008378
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
 	select FSL_IFC
 	imply CMD_EEPROM
 	imply CMD_NAND
 	imply CMD_MTDPARTS
 	imply CMD_REGINFO
 config ARCH_T1040
 	bool
 	select E500MC
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008044
 	select SYS_FSL_ERRATUM_A008378
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
 	select FSL_IFC
 	imply CMD_MTDPARTS
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 config ARCH_T1042
 	bool
 	select E500MC
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008044
 	select SYS_FSL_ERRATUM_A008378
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
 	select FSL_IFC
 	imply CMD_MTDPARTS
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 config ARCH_T2080
 	bool
 	select E500MC
 	select E6500
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007212
 	select SYS_FSL_ERRATUM_A007815
 	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_SATA
 	imply CMD_NAND
 	imply CMD_REGINFO
+	imply FSL_SATA
 config ARCH_T2081
 	bool
 	select E500MC
 	select E6500
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007212
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_NAND
 	imply CMD_REGINFO
 config ARCH_T4160
 	bool
 	select E500MC
 	select E6500
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A004468
 	select SYS_FSL_ERRATUM_A005871
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007798
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_SATA
 	imply CMD_NAND
 	imply CMD_REGINFO
+	imply FSL_SATA
 config ARCH_T4240
 	bool
 	select E500MC
 	select E6500
 	select FSL_LAW
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A004468
 	select SYS_FSL_ERRATUM_A005871
 	select SYS_FSL_ERRATUM_A006261
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007798
 	select SYS_FSL_ERRATUM_A007815
 	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_SATA
 	imply CMD_NAND
 	imply CMD_REGINFO
+	imply FSL_SATA
 config BOOKE
 	bool
 	default y
 config E500
 	bool
 	default y
 	help
 		Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 config E500MC
 	bool
 	imply CMD_PCI
 	help
 		Enble PowerPC E500MC core
 config E6500
 	bool
 	help
 		Enable PowerPC E6500 core
 config FSL_LAW
 	bool
 	help
 		Use Freescale common code for Local Access Window
 config SECURE_BOOT
 	bool	"Secure Boot"
 	help
 		Enable Freescale Secure Boot feature. Normally selected
 		by defconfig. If unsure, do not change.
 config MAX_CPUS
 	int "Maximum number of CPUs permitted for MPC85xx"
 	default 12 if ARCH_T4240
 	default 8 if ARCH_P4080 || \
 		     ARCH_T4160
 	default 4 if ARCH_B4860 || \
 		     ARCH_P2041 || \
 		     ARCH_P3041 || \
 		     ARCH_P5040 || \
 		     ARCH_T1040 || \
 		     ARCH_T1042 || \
 		     ARCH_T2080 || \
 		     ARCH_T2081
 	default 2 if ARCH_B4420 || \
 		     ARCH_BSC9132 || \
 		     ARCH_MPC8572 || \
 		     ARCH_P1020 || \
 		     ARCH_P1021 || \
 		     ARCH_P1022 || \
 		     ARCH_P1023 || \
 		     ARCH_P1024 || \
 		     ARCH_P1025 || \
 		     ARCH_P2020 || \
 		     ARCH_P5020 || \
 		     ARCH_T1023 || \
 		     ARCH_T1024
 	default 1
 	help
 	  Set this number to the maximum number of possible CPUs in the SoC.
 	  SoCs may have multiple clusters with each cluster may have multiple
 	  ports. If some ports are reserved but higher ports are used for
 	  cores, count the reserved ports. This will allocate enough memory
 	  in spin table to properly handle all cores.
 config SYS_CCSRBAR_DEFAULT
 	hex "Default CCSRBAR address"
 	default	0xff700000 if	ARCH_BSC9131	|| \
 				ARCH_BSC9132	|| \
 				ARCH_C29X	|| \
 				ARCH_MPC8536	|| \
 				ARCH_MPC8540	|| \
 				ARCH_MPC8541	|| \
 				ARCH_MPC8544	|| \
 				ARCH_MPC8548	|| \
 				ARCH_MPC8555	|| \
 				ARCH_MPC8560	|| \
 				ARCH_MPC8568	|| \
 				ARCH_MPC8569	|| \
 				ARCH_MPC8572	|| \
 				ARCH_P1010	|| \
 				ARCH_P1011	|| \
 				ARCH_P1020	|| \
 				ARCH_P1021	|| \
 				ARCH_P1022	|| \
 				ARCH_P1024	|| \
 				ARCH_P1025	|| \
 				ARCH_P2020
 	default 0xff600000 if	ARCH_P1023
 	default 0xfe000000 if	ARCH_B4420	|| \
 				ARCH_B4860	|| \
 				ARCH_P2041	|| \
 				ARCH_P3041	|| \
 				ARCH_P4080	|| \
 				ARCH_P5020	|| \
 				ARCH_P5040	|| \
 				ARCH_T1023	|| \
 				ARCH_T1024	|| \
 				ARCH_T1040	|| \
 				ARCH_T1042	|| \
 				ARCH_T2080	|| \
 				ARCH_T2081	|| \
 				ARCH_T4160	|| \
 				ARCH_T4240
 	default 0xe0000000 if ARCH_QEMU_E500
 	help
 		Default value of CCSRBAR comes from power-on-reset. It
 		is fixed on each SoC. Some SoCs can have different value
 		if changed by pre-boot regime. The value here must match
 		the current value in SoC. If not sure, do not change.
 config SYS_FSL_ERRATUM_A004468
 	bool
 config SYS_FSL_ERRATUM_A004477
 	bool
 config SYS_FSL_ERRATUM_A004508
 	bool
 config SYS_FSL_ERRATUM_A004580
 	bool
 config SYS_FSL_ERRATUM_A004699
 	bool
 config SYS_FSL_ERRATUM_A004849
 	bool
 config SYS_FSL_ERRATUM_A004510
 	bool
 config SYS_FSL_ERRATUM_A004510_SVR_REV
 	hex
 	depends on SYS_FSL_ERRATUM_A004510
 	default 0x20 if ARCH_P4080
 	default 0x10
 config SYS_FSL_ERRATUM_A004510_SVR_REV2
 	hex
 	depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
 	default 0x11
 config SYS_FSL_ERRATUM_A005125
 	bool
 config SYS_FSL_ERRATUM_A005434
 	bool
 config SYS_FSL_ERRATUM_A005812
 	bool
 config SYS_FSL_ERRATUM_A005871
 	bool
 config SYS_FSL_ERRATUM_A006261
 	bool
 config SYS_FSL_ERRATUM_A006379
 	bool
 config SYS_FSL_ERRATUM_A006384
 	bool
 config SYS_FSL_ERRATUM_A006475
 	bool
 config SYS_FSL_ERRATUM_A006593
 	bool
 config SYS_FSL_ERRATUM_A007075
 	bool
 config SYS_FSL_ERRATUM_A007186
 	bool
 config SYS_FSL_ERRATUM_A007212
 	bool
 config SYS_FSL_ERRATUM_A007815
 	bool
 config SYS_FSL_ERRATUM_A007798
 	bool
 config SYS_FSL_ERRATUM_A007907
 	bool
 config SYS_FSL_ERRATUM_A008044
 	bool
 config SYS_FSL_ERRATUM_CPC_A002
 	bool
 config SYS_FSL_ERRATUM_CPC_A003
 	bool
 config SYS_FSL_ERRATUM_CPU_A003999
 	bool
 config SYS_FSL_ERRATUM_ELBC_A001
 	bool
 config SYS_FSL_ERRATUM_I2C_A004447
 	bool
 config SYS_FSL_A004447_SVR_REV
 	hex
 	depends on SYS_FSL_ERRATUM_I2C_A004447
 	default 0x00 if ARCH_MPC8548
 	default 0x10 if ARCH_P1010
 	default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
 	default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
 config SYS_FSL_ERRATUM_IFC_A002769
 	bool
 config SYS_FSL_ERRATUM_IFC_A003399
 	bool
 config SYS_FSL_ERRATUM_NMG_CPU_A011
 	bool
 config SYS_FSL_ERRATUM_NMG_ETSEC129
 	bool
 config SYS_FSL_ERRATUM_NMG_LBC103
 	bool
 config SYS_FSL_ERRATUM_P1010_A003549
 	bool
 config SYS_FSL_ERRATUM_SATA_A001
 	bool
 config SYS_FSL_ERRATUM_SEC_A003571
 	bool
 config SYS_FSL_ERRATUM_SRIO_A004034
 	bool
 config SYS_FSL_ERRATUM_USB14
 	bool
 config SYS_P4080_ERRATUM_CPU22
 	bool
 config SYS_P4080_ERRATUM_PCIE_A003
 	bool
 config SYS_P4080_ERRATUM_SERDES8
 	bool
 config SYS_P4080_ERRATUM_SERDES9
 	bool
 config SYS_P4080_ERRATUM_SERDES_A001
 	bool
 config SYS_P4080_ERRATUM_SERDES_A005
 	bool
 config SYS_FSL_QORIQ_CHASSIS1
 	bool
 config SYS_FSL_QORIQ_CHASSIS2
 	bool
 config SYS_FSL_NUM_LAWS
 	int "Number of local access windows"
 	depends on FSL_LAW
 	default 32 if	ARCH_B4420	|| \
 			ARCH_B4860	|| \
 			ARCH_P2041	|| \
 			ARCH_P3041	|| \
 			ARCH_P4080	|| \
 			ARCH_P5020	|| \
 			ARCH_P5040	|| \
 			ARCH_T2080	|| \
 			ARCH_T2081	|| \
 			ARCH_T4160	|| \
 			ARCH_T4240
 	default 16 if	ARCH_T1023	|| \
 			ARCH_T1024	|| \
 			ARCH_T1040	|| \
 			ARCH_T1042
 	default 12 if	ARCH_BSC9131	|| \
 			ARCH_BSC9132	|| \
 			ARCH_C29X	|| \
 			ARCH_MPC8536	|| \
 			ARCH_MPC8572	|| \
 			ARCH_P1010	|| \
 			ARCH_P1011	|| \
 			ARCH_P1020	|| \
 			ARCH_P1021	|| \
 			ARCH_P1022	|| \
 			ARCH_P1023	|| \
 			ARCH_P1024	|| \
 			ARCH_P1025	|| \
 			ARCH_P2020
 	default 10 if	ARCH_MPC8544	|| \
 			ARCH_MPC8548	|| \
 			ARCH_MPC8568	|| \
 			ARCH_MPC8569
 	default 8 if	ARCH_MPC8540	|| \
 			ARCH_MPC8541	|| \
 			ARCH_MPC8555	|| \
 			ARCH_MPC8560
 	help
 		Number of local access windows. This is fixed per SoC.
 		If not sure, do not change.
 config SYS_FSL_THREADS_PER_CORE
 	int
 	default 2 if E6500
 	default 1
 config SYS_NUM_TLBCAMS
 	int "Number of TLB CAM entries"
 	default 64 if E500MC
 	default 16
 	help
 		Number of TLB CAM entries for Book-E chips. 64 for E500MC,
 		16 for other E500 SoCs.
 config SYS_PPC64
 	bool
 config SYS_PPC_E500_USE_DEBUG_TLB
 	bool
 config FSL_IFC
 	bool
 config FSL_ELBC
 	bool
 config SYS_PPC_E500_DEBUG_TLB
 	int "Temporary TLB entry for external debugger"
 	depends on SYS_PPC_E500_USE_DEBUG_TLB
 	default 0 if	ARCH_MPC8544 || ARCH_MPC8548
 	default 1 if	ARCH_MPC8536
 	default 2 if	ARCH_MPC8572	|| \
 			ARCH_P1011	|| \
 			ARCH_P1020	|| \
 			ARCH_P1021	|| \
 			ARCH_P1022	|| \
 			ARCH_P1024	|| \
 			ARCH_P1025	|| \
 			ARCH_P2020
 	default 3 if	ARCH_P1010	|| \
 			ARCH_BSC9132	|| \
 			ARCH_C29X
 	help
 		Select a temporary TLB entry to be used during boot to work
                 around limitations in e500v1 and e500v2 external debugger
                 support. This reduces the portions of the boot code where
                 breakpoints and single stepping do not work. The value of this
                 symbol should be set to the TLB1 entry to be used for this
                 purpose. If unsure, do not change.
 config SYS_FSL_IFC_CLK_DIV
 	int "Divider of platform clock"
 	depends on FSL_IFC
 	default 2 if	ARCH_B4420	|| \
 			ARCH_B4860	|| \
 			ARCH_T1024	|| \
 			ARCH_T1023	|| \
 			ARCH_T1040	|| \
 			ARCH_T1042	|| \
 			ARCH_T4160	|| \
 			ARCH_T4240
 	default 1
 	help
 		Defines divider of platform clock(clock input to
 		IFC controller).
 config SYS_FSL_LBC_CLK_DIV
 	int "Divider of platform clock"
 	depends on FSL_ELBC || ARCH_MPC8540 || \
 		ARCH_MPC8548 || ARCH_MPC8541 || \
 		ARCH_MPC8555 || ARCH_MPC8560 || \
 		ARCH_MPC8568
 	default 2 if	ARCH_P2041	|| \
 			ARCH_P3041	|| \
 			ARCH_P4080	|| \
 			ARCH_P5020	|| \
 			ARCH_P5040
 	default 1
 	help
 		Defines divider of platform clock(clock input to
 		eLBC controller).
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
 source "board/freescale/c29xpcie/Kconfig"
 source "board/freescale/corenet_ds/Kconfig"
 source "board/freescale/mpc8536ds/Kconfig"
 source "board/freescale/mpc8541cds/Kconfig"
 source "board/freescale/mpc8544ds/Kconfig"
 source "board/freescale/mpc8548cds/Kconfig"
 source "board/freescale/mpc8555cds/Kconfig"
 source "board/freescale/mpc8568mds/Kconfig"
 source "board/freescale/mpc8569mds/Kconfig"
 source "board/freescale/mpc8572ds/Kconfig"
 source "board/freescale/p1010rdb/Kconfig"
 source "board/freescale/p1022ds/Kconfig"
 source "board/freescale/p1023rdb/Kconfig"
 source "board/freescale/p1_p2_rdb_pc/Kconfig"
 source "board/freescale/p1_twr/Kconfig"
 source "board/freescale/p2041rdb/Kconfig"
 source "board/freescale/qemu-ppce500/Kconfig"
 source "board/freescale/t102xqds/Kconfig"
 source "board/freescale/t102xrdb/Kconfig"
 source "board/freescale/t1040qds/Kconfig"
 source "board/freescale/t104xrdb/Kconfig"
 source "board/freescale/t208xqds/Kconfig"
 source "board/freescale/t208xrdb/Kconfig"
 source "board/freescale/t4qds/Kconfig"
 source "board/freescale/t4rdb/Kconfig"
 source "board/gdsys/p1022/Kconfig"
 source "board/keymile/kmp204x/Kconfig"
 source "board/sbc8548/Kconfig"
 source "board/socrates/Kconfig"
 source "board/varisys/cyrus/Kconfig"
 source "board/xes/xpedite520x/Kconfig"
 source "board/xes/xpedite537x/Kconfig"
 source "board/xes/xpedite550x/Kconfig"
 source "board/Arcturus/ucp1020/Kconfig"
 endmenu

configs/MPC8315ERDB_defconfig

Diff comments View file @ 9920d15

 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8315ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=e0600000.flash"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
+CONFIG_FSL_SATA=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y

configs/MPC837XERDB_defconfig

Diff comments View file @ 9920d15

 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_FSL_SATA=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y

configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig

Diff comments View file @ 9920d15

 CONFIG_PPC=y
 CONFIG_IDENT_STRING=" controlcenterd 0.01"
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD,DEVELOP"
 CONFIG_BOOTDELAY=10
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_REGINFO=y
 CONFIG_CMD_EEPROM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SATA=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_TPM=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_FSL_SATA=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_TPM_AUTH_SESSIONS=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_TPM=y
 CONFIG_OF_LIBFDT=y

configs/controlcenterd_36BIT_SDCARD_defconfig

Diff comments View file @ 9920d15

 CONFIG_PPC=y
 CONFIG_IDENT_STRING=" controlcenterd 0.01"
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
 CONFIG_BOOTDELAY=10
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_REGINFO=y
 CONFIG_CMD_EEPROM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SATA=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_TPM=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_FSL_SATA=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_TPM_AUTH_SESSIONS=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_TPM=y
 CONFIG_OF_LIBFDT=y

drivers/ata/Kconfig

Diff comments View file @ 9920d15

 config AHCI
 	bool "Support SATA controllers with driver model"
 	depends on DM
 	help
 	  This enables a uclass for disk controllers in U-Boot. Various driver
 	  types can use this, such as AHCI/SATA. It does not provide any standard
 	  operations at present. The block device interface has not been converted
 	  to driver model.
 config SATA
 	bool "Support SATA controllers"
 	help
 	  This enables support for SATA (Serial Advanced Technology
 	  Attachment), a serial bus standard for connecting to hard drives and
 	  other storage devices.
 	  SATA replaces PATA (originally just ATA), which stands for Parallel AT
 	  Attachment, where AT refers to an IBM AT (Advanced Technology)
 	  computer released in 1984.
 	  See also CMD_SATA which provides command-line support.
 menu "SATA/SCSI device support"
 config AHCI_PCI
 	bool "Support for PCI-based AHCI controller"
 	depends on DM_SCSI
 	help
 	  Enables support for the PCI-based AHCI controller.
 config SATA_CEVA
 	bool "Ceva Sata controller"
 	depends on AHCI
 	depends on DM_SCSI
 	help
 	  This option enables Ceva Sata controller hard IP available on Xilinx
 	  ZynqMP. Support up to 2 external devices. Complient with SATA 3.1 and
 	  AHCI 1.3 specifications with hot-plug detect feature.
 config DWC_AHCI
 	bool "Enable Synopsys DWC AHCI driver support"
 	select SCSI_AHCI
 	select PHY
 	depends on DM_SCSI
 	help
 	  Enable this driver to support Sata devices through
 	  Synopsys DWC AHCI module.
+config FSL_SATA
+	bool "Enable Freescale SATA controller driver support"
+	help
+	  Enable this driver to support the SATA controller found in
+	  some Freescale PowerPC SoCs.
 config SATA_MV
 	bool "Enable Marvell SATA controller driver support"
 	help
 	  Enable this driver to support the SATA controller found in
 	  some Marvell SoCs.
 config SATA_SIL
 	bool "Enable Silicon Image SIL3131 / SIL3132 / SIL3124 SATA driver support"
 	help
 	  Enable this driver to support the SIL3131, SIL3132 and SIL3124
 	  SATA controllers.
 config SATA_SIL3114
 	bool "Enable Silicon Image SIL3114 SATA driver support"
 	help
 	  Enable this driver to support the SIL3114 SATA controllers.
 endmenu

include/configs/MPC8315ERDB.h

Diff comments View file @ 9920d15

 /*
  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xFE000000
 #endif
 #ifndef CONFIG_SYS_MONITOR_BASE
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_MPC831x		1 /* MPC831x CPU family */
 #define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
 #define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
 /*
  * System Clock Setup
  */
 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
 /*
  * Hardware Reset Configuration Word
  * if CLKIN is 66.66MHz, then
  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  */
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
 	HRCWL_SVCOD_DIV_2 |\
 	HRCWL_CSB_TO_CLKIN_2X1 |\
 	HRCWL_CORE_TO_CSB_3X1)
 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_TSEC1M_IN_RGMII |\
 	HRCWH_TSEC2M_IN_RGMII |\
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LALE_NORMAL)
 #ifdef CONFIG_NAND_SPL
 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 		       HRCWH_FROM_0XFFF00100 |\
 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
 		       HRCWH_RL_EXT_NAND)
 #else
 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 		       HRCWH_FROM_0X00000100 |\
 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
 		       HRCWH_RL_EXT_LEGACY)
 #endif
 /*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH		0x00000000
 #define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
 #define CONFIG_HWCONFIG
 /*
  * IMMR new address
  */
 #define CONFIG_SYS_IMMR		0xE0000000
 /*
  * Arbiter Setup
  */
 #define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
 #define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
 #define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
 				| DDRCDR_PZ_LOZ \
 				| DDRCDR_NZ_LOZ \
 				| DDRCDR_ODT \
 				| DDRCDR_Q_DRN)
 				/* 0x7b880001 */
 /*
  * Manually set up DDR parameters
  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  */
 #define CONFIG_SYS_DDR_SIZE		128 /* MB */
 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
 				| CSCONFIG_ODT_RD_NEVER \
 				| CSCONFIG_ODT_WR_ONLY_CURRENT \
 				| CSCONFIG_ROW_BIT_13 \
 				| CSCONFIG_COL_BIT_10)
 				/* 0x80010102 */
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
 				| (0 << TIMING_CFG0_WRT_SHIFT) \
 				| (0 << TIMING_CFG0_RRT_SHIFT) \
 				| (0 << TIMING_CFG0_WWT_SHIFT) \
 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 				/* 0x00220802 */
 #define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
 				| (6 << TIMING_CFG1_REFREC_SHIFT) \
 				| (2 << TIMING_CFG1_WRREC_SHIFT) \
 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
 				/* 0x27256222 */
 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 				| (4 << TIMING_CFG2_CPO_SHIFT) \
 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 				/* 0x121048c5 */
 #define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 				/* 0x03600100 */
 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 				| SDRAM_CFG_DBW_32)
 				/* 0x43080000 */
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
 #define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
 #define CONFIG_SYS_DDR_MODE2	0x00000000
 /*
  * Memory test
  */
 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x00140000
 /*
  * The reserved memory
  */
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
 /*
  * Initial RAM Base Address Setup
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /*
  * Local Bus Configuration & Clock Setup
  */
 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00040000
 #define CONFIG_FSL_ELBC		1
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */
 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
 					/* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
 					| BR_PS_16	/* 16 bit port */ \
 					| BR_MS_GPCM	/* MSEL = GPCM */ \
 					| BR_V)		/* valid */
 #define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 					| OR_UPM_XAM \
 					| OR_GPCM_CSNT \
 					| OR_GPCM_ACS_DIV2 \
 					| OR_GPCM_XACS \
 					| OR_GPCM_SCY_15 \
 					| OR_GPCM_TRLX_SET \
 					| OR_GPCM_EHTR_SET \
 					| OR_GPCM_EAD)
 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
 /* 127 64KB sectors and 8 8KB top sectors per device */
 #define CONFIG_SYS_MAX_FLASH_SECT	135
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
 /*
  * NAND Flash on the Local Bus
  */
 #ifdef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE		0xFFF00000
 #else
 #define CONFIG_SYS_NAND_BASE		0xE0600000
 #endif
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITION
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_NAND_FSL_ELBC		1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	16384
 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
 				| BR_PS_8		/* 8 bit port */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
 				| BR_V)			/* valid */
 #define CONFIG_SYS_NAND_OR_PRELIM	\
 				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
 				| OR_FCM_SCY_1 \
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR)
 				/* 0xFFFF8396 */
 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 	!defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef CONFIG_SYS_RAMBOOT
 #endif
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
 /*
  * Board info - revision and where boot from
  */
 #define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
 /*
  * Config on-board RTC
  */
 #define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
 #define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
 #define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE
 #define CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #define CONFIG_HAS_FSL_DR_USB
 #define CONFIG_SYS_SCCR_USBDRCM		3
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_PHY_TYPE	"utmi"
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 /*
  * TSEC
  */
 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 /*
  * TSEC ethernet configuration
  */
 #define CONFIG_MII		1 /* MII PHY management */
 #define CONFIG_TSEC1		1
 #define CONFIG_TSEC1_NAME	"eTSEC0"
 #define CONFIG_TSEC2		1
 #define CONFIG_TSEC2_NAME	"eTSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC2_FLAGS		TSEC_GIGABIT
 /* Options are: eTSEC[0-1] */
 #define CONFIG_ETHPRIME		"eTSEC1"
 /*
  * SATA
  */
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1_OFFSET	0x18000
 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2_OFFSET	0x19000
 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
 #endif
 /*
  * Environment
  */
 #if !defined(CONFIG_SYS_RAMBOOT)
 	#define CONFIG_ENV_ADDR		\
 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 #else
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 /*
  * Core HID Setup
  */
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
 				 HID0_ENABLE_INSTRUCTION_CACHE | \
 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 #define CONFIG_SYS_HID2		HID2_HBE
 /*
  * MMU Setup
  */
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR: cache cacheable */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
 				| BATU_BL_128M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
 				| BATU_BL_8M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
 				| BATU_BL_32M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 /* Stack in dcache: cacheable, no memory coherence */
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR \
 				| BATU_BL_128K \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 /* PCI MEM space: cacheable */
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 /* PCI MMIO space: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #define CONFIG_SYS_IBAT6L	0
 #define CONFIG_SYS_IBAT6U	0
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_IBAT7L	0
 #define CONFIG_SYS_IBAT7U	0
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #endif
 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"consoledev=ttyS0\0"						\
 	"ramdiskaddr=1000000\0"						\
 	"ramdiskfile=ramfs.83xx\0"					\
 	"fdtaddr=780000\0"						\
 	"fdtfile=mpc8315erdb.dtb\0"					\
 	"usb_phy_type=utmi\0"						\
 	""
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv bootargs root=/dev/nfs rw "				\
 		"nfsroot=$serverip:$rootpath "				\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
 							"$netdev:off "	\
 		"console=$consoledev,$baudrate $othbootargs;"		\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"setenv bootargs root=/dev/ram rw "				\
 		"console=$consoledev,$baudrate $othbootargs;"		\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 #endif	/* __CONFIG_H */

include/configs/MPC837XEMDS.h

Diff comments View file @ 9920d15

 /*
  * Copyright (C) 2007 Freescale Semiconductor, Inc.
  * Dave Liu <daveliu@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
 #define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
 /*
  * System Clock Setup
  */
 #ifdef CONFIG_PCISLAVE
 #define CONFIG_83XX_PCICLK	66000000 /* in HZ */
 #else
 #define CONFIG_83XX_CLKIN	66000000 /* in Hz */
 #endif
 #ifndef CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_CLK_FREQ	66000000
 #endif
 /*
  * Hardware Reset Configuration Word
  * if CLKIN is 66MHz, then
  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
  */
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_SVCOD_DIV_2 |\
 	HRCWL_CSB_TO_CLKIN_6X1 |\
 	HRCWL_CORE_TO_CSB_1_5X1)
 #ifdef CONFIG_PCISLAVE
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_AGENT |\
 	HRCWH_PCI1_ARBITER_DISABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0XFFF00100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_RL_EXT_LEGACY |\
 	HRCWH_TSEC1M_IN_RGMII |\
 	HRCWH_TSEC2M_IN_RGMII |\
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LDP_CLEAR)
 #else
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_RL_EXT_LEGACY |\
 	HRCWH_TSEC1M_IN_RGMII |\
 	HRCWH_TSEC2M_IN_RGMII |\
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LDP_CLEAR)
 #endif
 /* Arbiter Configuration Register */
 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth is 4 */
 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count is 4 */
 /* System Priority Control Register */
 #define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC1/2 emergency has highest priority */
 /*
  * IP blocks clock configuration
  */
 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
 #define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */
 /*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH		0x00000000
 #define CONFIG_SYS_SICRL		0x00000000
 /*
  * Output Buffer Impedance
  */
 #define CONFIG_SYS_OBIR		0x31100000
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_HWCONFIG
 /*
  * IMMR new address
  */
 #define CONFIG_SYS_IMMR		0xE0000000
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_DDRCDR_VALUE		(DDRCDR_DHC_EN \
 					| DDRCDR_ODT \
 					| DDRCDR_Q_DRN)
 					/* 0x80080001 */ /* ODT 150ohm on SoC */
 #undef CONFIG_DDR_ECC		/* support DDR ECC function */
 #undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
 #if defined(CONFIG_SPD_EEPROM)
 #define SPD_EEPROM_ADDRESS	0x51 /* I2C address of DDR SODIMM SPD */
 #else
 /*
  * Manually set up DDR parameters
  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
  */
 #define CONFIG_SYS_DDR_SIZE		512 /* MB */
 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000001f
 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
 			| CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
 			| CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
 			| CSCONFIG_ROW_BIT_14 \
 			| CSCONFIG_COL_BIT_10)
 			/* 0x80010202 */
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
 				| (0 << TIMING_CFG0_WRT_SHIFT) \
 				| (0 << TIMING_CFG0_RRT_SHIFT) \
 				| (0 << TIMING_CFG0_WWT_SHIFT) \
 				| (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 				/* 0x00620802 */
 #define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
 				| (13 << TIMING_CFG1_REFREC_SHIFT) \
 				| (3 << TIMING_CFG1_WRREC_SHIFT) \
 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
 				/* 0x3935d322 */
 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 				| (6 << TIMING_CFG2_CPO_SHIFT) \
 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 				| (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 				/* 0x131088c8 */
 #define CONFIG_SYS_DDR_INTERVAL	((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
 				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 				/* 0x03E00100 */
 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
 #define CONFIG_SYS_DDR_MODE	((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 				| (0x1432 << SDRAM_MODE_SD_SHIFT))
 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
 #define CONFIG_SYS_DDR_MODE2	0x00000000
 #endif
 /*
  * Memory test
  */
 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x00140000
 /*
  * The reserved memory
  */
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef CONFIG_SYS_RAMBOOT
 #endif
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
 /*
  * Initial RAM Base Address Setup
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /*
  * Local Bus Configuration & Clock Setup
  */
 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 #define CONFIG_FSL_ELBC		1
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI	/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
 #define CONFIG_SYS_FLASH_BASE	0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE	32 /* max FLASH size is 32M */
 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
 					/* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
 				| BR_PS_16	/* 16 bit port */ \
 				| BR_MS_GPCM	/* MSEL = GPCM */ \
 				| BR_V)		/* valid */
 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 				| OR_UPM_XAM \
 				| OR_GPCM_CSNT \
 				| OR_GPCM_ACS_DIV2 \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_15 \
 				| OR_GPCM_TRLX_SET \
 				| OR_GPCM_EHTR_SET \
 				| OR_GPCM_EAD)
 				/* 0xFE000FF7 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
 /*
  * BCSR on the Local Bus
  */
 #define CONFIG_SYS_BCSR		0xF8000000
 					/* Access window base at BCSR base */
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_BCSR \
 				| BR_PS_8 \
 				| BR_MS_GPCM \
 				| BR_V)
 				/* 0xF8000801 */
 #define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
 				| OR_GPCM_XAM \
 				| OR_GPCM_CSNT \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_15 \
 				| OR_GPCM_TRLX_SET \
 				| OR_GPCM_EHTR_SET \
 				| OR_GPCM_EAD)
 				/* 0xFFFFE9F7 */
 /*
  * NAND Flash on the Local Bus
  */
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_NAND_FSL_ELBC	1
 #define CONFIG_SYS_NAND_BASE	0xE0600000
 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE \
 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
 				| BR_PS_8		/* 8 bit port */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
 				| BR_V)			/* valid */
 #define CONFIG_SYS_OR3_PRELIM	(OR_AM_32KB \
 				| OR_FCM_BCTLD \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
 				| OR_FCM_SCY_1 \
 				| OR_FCM_RST \
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR)
 				/* 0xFFFF919E */
 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
 /*
  * Config on-board RTC
  */
 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
 #define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
 #define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #ifndef __ASSEMBLY__
 extern int board_pci_host_broken(void);
 #endif
 #define CONFIG_PCIE
 #define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
 #define CONFIG_HAS_FSL_DR_USB	1 /* fixup device tree for the DR USB */
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif /* CONFIG_PCI */
 /*
  * TSEC
  */
 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 /*
  * TSEC ethernet configuration
  */
 #define CONFIG_MII		1 /* MII PHY management */
 #define CONFIG_TSEC1		1
 #define CONFIG_TSEC1_NAME	"eTSEC0"
 #define CONFIG_TSEC2		1
 #define CONFIG_TSEC2_NAME	"eTSEC1"
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		3
 #define TSEC1_PHY_ADDR_SGMII	8
 #define TSEC2_PHY_ADDR_SGMII	4
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"eTSEC1"
 /* SERDES */
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1	0xe3000
 #define CONFIG_FSL_SERDES2	0xe3100
 /*
  * SATA
  */
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1_OFFSET	0x18000
 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2_OFFSET	0x19000
 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
 #endif
 /*
  * Environment
  */
 #ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_ADDR		\
 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 #else
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_PIN_MUX
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 /*
  * Core HID Setup
  */
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
 				 HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2		HID2_HBE
 /*
  * MMU Setup
  */
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR: cache cacheable */
 #define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR \
 				| BATU_BL_8M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 /* BCSR: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_BCSR \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_BCSR \
 				| BATU_BL_128K \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE \
 				| BATU_BL_32M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 /* Stack in dcache: cacheable, no memory coherence */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
 				| BATU_BL_128K \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else
 #define CONFIG_SYS_IBAT6L	(0)
 #define CONFIG_SYS_IBAT6U	(0)
 #define CONFIG_SYS_IBAT7L	(0)
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #endif
 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"consoledev=ttyS0\0"						\
 	"ramdiskaddr=1000000\0"						\
 	"ramdiskfile=ramfs.83xx\0"					\
 	"fdtaddr=780000\0"						\
 	"fdtfile=mpc8379_mds.dtb\0"					\
 	""
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv bootargs root=/dev/nfs rw "				\
 		"nfsroot=$serverip:$rootpath "				\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
 							"$netdev:off "	\
 		"console=$consoledev,$baudrate $othbootargs;"		\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"setenv bootargs root=/dev/ram rw "				\
 		"console=$consoledev,$baudrate $othbootargs;"		\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 #endif	/* __CONFIG_H */

include/configs/MPC837XERDB.h

Diff comments View file @ 9920d15

 /*
  * Copyright (C) 2007 Freescale Semiconductor, Inc.
  * Kevin Lam <kevin.lam@freescale.com>
  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
 #define CONFIG_MPC837XERDB	1
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /*
  * On-board devices
  */
 #define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
 #define CONFIG_VSC7385_ENET
 /*
  * System Clock Setup
  */
 #ifdef CONFIG_PCISLAVE
 #define CONFIG_83XX_PCICLK	66666667 /* in HZ */
 #else
 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
 #define CONFIG_PCIE
 #endif
 #ifndef CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
 #endif
 /*
  * Hardware Reset Configuration Word
  */
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_SVCOD_DIV_2 |\
 	HRCWL_CSB_TO_CLKIN_5X1 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #ifdef CONFIG_PCISLAVE
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_AGENT |\
 	HRCWH_PCI1_ARBITER_DISABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0XFFF00100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_RL_EXT_LEGACY |\
 	HRCWH_TSEC1M_IN_RGMII |\
 	HRCWH_TSEC2M_IN_RGMII |\
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LDP_CLEAR)
 #else
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_RL_EXT_LEGACY |\
 	HRCWH_TSEC1M_IN_RGMII |\
 	HRCWH_TSEC2M_IN_RGMII |\
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LDP_CLEAR)
 #endif
 /* System performance - define the value i.e. CONFIG_SYS_XXX
 */
 /* Arbiter Configuration Register */
 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
 /* System Priority Control Regsiter */
 #define CONFIG_SYS_SPCR_TSECEP	3	/* eTSEC1&2 emergency priority (0-3) */
 /* System Clock Configuration Register */
 #define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
 /*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH		0x08200000
 #define CONFIG_SYS_SICRL		0x00000000
 /*
  * Output Buffer Impedance
  */
 #define CONFIG_SYS_OBIR		0x30100000
 /*
  * IMMR new address
  */
 #define CONFIG_SYS_IMMR		0xE0000000
 /*
  * Device configurations
  */
 /* Vitesse 7385 */
 #ifdef CONFIG_VSC7385_ENET
 #define CONFIG_TSEC2
 /* The flash address and size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
 #define CONFIG_VSC7385_IMAGE_SIZE	8192
 #endif
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 #undef CONFIG_DDR_ECC		/* support DDR ECC function */
 #undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */
 /*
  * Manually set up DDR parameters
  */
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
 					| CSCONFIG_ODT_WR_ONLY_CURRENT \
 					| CSCONFIG_ROW_BIT_13 \
 					| CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
 				| (0 << TIMING_CFG0_WRT_SHIFT) \
 				| (0 << TIMING_CFG0_RRT_SHIFT) \
 				| (0 << TIMING_CFG0_WWT_SHIFT) \
 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 				/* 0x00260802 */ /* DDR400 */
 #define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
 				| (13 << TIMING_CFG1_REFREC_SHIFT) \
 				| (3 << TIMING_CFG1_WRREC_SHIFT) \
 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
 				/* 0x3937d322 */
 #define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 				| (5 << TIMING_CFG2_CPO_SHIFT) \
 				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 				| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 				/* 0x02984cc8 */
 #define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 				/* 0x06090100 */
 #if defined(CONFIG_DDR_2T_TIMING)
 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
 					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 					| SDRAM_CFG_32_BE \
 					| SDRAM_CFG_2T_EN)
 					/* 0x43088000 */
 #else
 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
 					| SDRAM_CFG_SDRAM_TYPE_DDR2)
 					/* 0x43000000 */
 #endif
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
 #define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 					| (0x0442 << SDRAM_MODE_SD_SHIFT))
 					/* 0x04400442 */ /* DDR400 */
 #define CONFIG_SYS_DDR_MODE2		0x00000000
 /*
  * Memory test
  */
 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x0ef70010
 /*
  * The reserved memory
  */
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
 /*
  * Initial RAM Base Address Setup
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /*
  * Local Bus Configuration & Clock Setup
  */
 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 #define CONFIG_FSL_ELBC		1
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
 					/* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
 				| BR_PS_16	/* 16 bit port */ \
 				| BR_MS_GPCM	/* MSEL = GPCM */ \
 				| BR_V)		/* valid */
 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_9 \
 				| OR_GPCM_EHTR_SET \
 				| OR_GPCM_EAD)
 				/* 0xFF800191 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 /*
  * NAND Flash on the Local Bus
  */
 #define CONFIG_SYS_NAND_BASE	0xE0600000
 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE \
 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
 				| BR_PS_8		/* 8 bit port */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
 				| BR_V)			/* valid */
 #define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
 				| OR_FCM_SCY_1 \
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR)
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
 /* Vitesse 7385 */
 #define CONFIG_SYS_VSC7385_BASE	0xF0000000
 #ifdef CONFIG_VSC7385_ENET
 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
 					| BR_PS_8 \
 					| BR_MS_GPCM \
 					| BR_V)
 					/* 0xF0000801 */
 #define CONFIG_SYS_OR2_PRELIM		(OR_AM_128KB \
 					| OR_GPCM_CSNT \
 					| OR_GPCM_XACS \
 					| OR_GPCM_SCY_15 \
 					| OR_GPCM_SETA \
 					| OR_GPCM_TRLX_SET \
 					| OR_GPCM_EHTR_SET \
 					| OR_GPCM_EAD)
 					/* 0xfffe09ff */
 					/* Access Base */
 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
 #endif
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE \
 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 /* SERDES */
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1	0xe3000
 #define CONFIG_FSL_SERDES2	0xe3100
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
 /*
  * Config on-board RTC
  */
 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
 #define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
 #define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif	/* CONFIG_PCI */
 /*
  * TSEC
  */
 #ifdef CONFIG_TSEC_ENET
 #define CONFIG_GMII			/* MII PHY management */
 #define CONFIG_TSEC1
 #ifdef CONFIG_TSEC1
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME		"TSEC0"
 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
 #define TSEC1_PHY_ADDR			2
 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX			0
 #endif
 #ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME		"TSEC1"
 #define CONFIG_SYS_TSEC2_OFFSET		0x25000
 #define TSEC2_PHY_ADDR			0x1c
 #define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_PHYIDX			0
 #endif
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC0"
 #endif
 /*
  * SATA
  */
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1_OFFSET	0x18000
 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2_OFFSET	0x19000
 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
 #endif
 /*
  * Environment
  */
 #ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_ADDR		\
 			(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K (one sector) for env */
 	#define CONFIG_ENV_SIZE		0x4000
 #else
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_PIN_MUX
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 /*
  * Core HID Setup
  */
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
 				| HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2		HID2_HBE
 /*
  * MMU Setup
  */
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR: cache cacheable */
 #define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR \
 				| BATU_BL_8M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 /* L2 Switch: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_VSC7385_BASE \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_VSC7385_BASE \
 				| BATU_BL_128K \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE \
 				| BATU_BL_32M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 /* Stack in dcache: cacheable, no memory coherence */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
 				| BATU_BL_128K \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS \
 				| BATL_PP_RW \
 				| BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS \
 				| BATL_PP_RW \
 				| BATL_CACHEINHIBIT \
 				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS \
 				| BATU_BL_256M \
 				| BATU_VS \
 				| BATU_VP)
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else
 #define CONFIG_SYS_IBAT6L	(0)
 #define CONFIG_SYS_IBAT6U	(0)
 #define CONFIG_SYS_IBAT7L	(0)
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_NETDEV		"eth1"
 #define CONFIG_HOSTNAME		mpc837x_rdb
 #define CONFIG_ROOTPATH		"/nfsroot"
 #define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
 #define CONFIG_BOOTFILE		"uImage"
 				/* U-Boot image on TFTP server */
 #define CONFIG_UBOOTPATH	"u-boot.bin"
 #define CONFIG_FDTFILE		"mpc8379_rdb.dtb"
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		800000
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"netdev=" CONFIG_NETDEV "\0"				\
 	"uboot=" CONFIG_UBOOTPATH "\0"					\
 	"tftpflash=tftp $loadaddr $uboot;"				\
 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
 			" +$filesize; "	\
 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
 			" +$filesize; "	\
 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
 			" $filesize; "	\
 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
 			" +$filesize; "	\
 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
 			" $filesize\0"	\
 	"fdtaddr=780000\0"						\
 	"fdtfile=" CONFIG_FDTFILE "\0"					\
 	"ramdiskaddr=1000000\0"						\
 	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
 	"console=ttyS0\0"						\
 	"setbootargs=setenv bootargs "					\
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
 							"$netdev:off "	\
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv rootdev /dev/nfs;"					\
 	"run setbootargs;"						\
 	"run setipargs;"						\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"setenv rootdev /dev/ram;"					\
 	"run setbootargs;"						\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #endif	/* __CONFIG_H */

include/configs/MPC8536DS.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /*
  * mpc8536ds board configuration file
  *
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include "../board/freescale/common/ics307_clk.h"
 #ifdef CONFIG_SDCARD
 #define CONFIG_RAMBOOT_SDCARD		1
 #define CONFIG_SYS_TEXT_BASE	0xf8f40000
 #define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
 #endif
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH		1
 #define CONFIG_SYS_TEXT_BASE	0xf8f40000
 #define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
 #endif
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef	CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #ifndef CONFIG_SYS_MONITOR_BASE
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 #define CONFIG_PCI1		1	/* Enable PCI controller 1 */
 #define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP			1
 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
 #endif
 #define CONFIG_SYS_MEMTEST_START 0x00010000	/* skip exception vectors */
 #define CONFIG_SYS_MEMTEST_END   0x1f000000	/* skip u-boot at top of RAM */
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  * Config the L2 Cache as L2 SRAM
  */
 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
 #else
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #endif
 #define CONFIG_SYS_L2_SIZE		(512 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 #if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 /* DDR Setup */
 #define CONFIG_VERY_BIG_RAM
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 #define CONFIG_SYS_SPD_BUS_NUM		1
 /* These are used when DDR doesn't use SPD. */
 #define CONFIG_SYS_SDRAM_SIZE		256	/* DDR is 256MB */
 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102 /* Enable, no interleaving */
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
 #define CONFIG_SYS_DDR_TIMING_1	0x3935d322
 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
 #define CONFIG_SYS_DDR_MODE_1		0x00480432
 #define CONFIG_SYS_DDR_MODE_2		0x00000000
 #define CONFIG_SYS_DDR_INTERVAL	0x06180100
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
 #define CONFIG_SYS_DDR_CONTROL	0xC3008000	/* Type = DDR2 */
 #define CONFIG_SYS_DDR_CONTROL2	0x04400010
 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
 #define CONFIG_SYS_DDR_SBE		0x00010000
 /* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif
 #undef CONFIG_CLOCKS_IN_MHZ
 /*
  * Memory map -- xxx -this is wrong, needs updating
  *
  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
  *
  * Localbus cacheable (TBD)
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
  * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
  * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 /*
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
 #else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 #define CONFIG_FLASH_BR_PRELIM \
 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
 #define CONFIG_SYS_BR1_PRELIM \
 		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 		 | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
 				      CONFIG_SYS_FLASH_BASE_PHYS }
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #else
 #undef CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_HWCONFIG			/* enable hwconfig */
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS	0xfffdf0000ull
 #else
 #define PIXIS_BASE_PHYS	PIXIS_BASE
 #endif
 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
 #define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
 #define PIXIS_PWR		0x5	/* PIXIS Power status register */
 #define PIXIS_AUX		0x6	/* Auxiliary 1 register */
 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
 #define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
 #define PIXIS_VCTL		0x10	/* VELA Control Register */
 #define PIXIS_VSTAT		0x11	/* VELA Status Register */
 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
 #define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
 #define PIXIS_VBOOT_LBMAP	0xe0	/* VBOOT - CFG_LBMAP */
 #define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
 #define PIXIS_VBOOT_LBMAP_NOR1	0x01	/* cfg_lbmap - boot from NOR 1 */
 #define PIXIS_VBOOT_LBMAP_NOR2	0x02	/* cfg_lbmap - boot from NOR 2 */
 #define PIXIS_VBOOT_LBMAP_NOR3	0x03	/* cfg_lbmap - boot from NOR 3 */
 #define PIXIS_VBOOT_LBMAP_PJET	0x04	/* cfg_lbmap - boot from projet */
 #define PIXIS_VBOOT_LBMAP_NAND	0x05	/* cfg_lbmap - boot from NAND */
 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
 #define PIXIS_VSYSCLK0		0x1A	/* VELA SYSCLK0 Register */
 #define PIXIS_VSYSCLK1		0x1B	/* VELA SYSCLK1 Register */
 #define PIXIS_VSYSCLK2		0x1C	/* VELA SYSCLK2 Register */
 #define PIXIS_VDDRCLK0		0x1D	/* VELA DDRCLK0 Register */
 #define PIXIS_VDDRCLK1		0x1E	/* VELA DDRCLK1 Register */
 #define PIXIS_VDDRCLK2		0x1F	/* VELA DDRCLK2 Register */
 #define PIXIS_VWATCH		0x24    /* Watchdog Register */
 #define PIXIS_LED		0x25    /* LED Register */
 #define PIXIS_SPD_SYSCLK	0x7	/* SYSCLK option */
 /* old pixis referenced names */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0x4e
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET \
 		(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
 #ifndef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE		0xffa00000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 #else
 #define CONFIG_SYS_NAND_BASE		0xfff00000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 #endif
 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 				CONFIG_SYS_NAND_BASE + 0x40000, \
 				CONFIG_SYS_NAND_BASE + 0x80000, \
 				CONFIG_SYS_NAND_BASE + 0xC0000}
 #define CONFIG_SYS_MAX_NAND_DEVICE	4
 #define CONFIG_NAND_FSL_ELBC	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 /* NAND boot: 4K NAND loader config */
 #define CONFIG_SYS_NAND_SPL_SIZE	0x1000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
 #define CONFIG_SYS_NAND_U_BOOT_START \
 		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
 #define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 /* NAND flash config */
 #define CONFIG_SYS_NAND_BR_PRELIM \
 		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 		| BR_PS_8		/* Port Size = 8 bit */ \
 		| BR_MS_FCM		/* MSEL = FCM */ \
 		| BR_V)			/* valid */
 #define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	/* length 256K */ \
 		| OR_FCM_PGS		/* Large Page*/ \
 		| OR_FCM_CSCT \
 		| OR_FCM_CST \
 		| OR_FCM_CHT \
 		| OR_FCM_SCY_1 \
 		| OR_FCM_TRLX \
 		| OR_FCM_EHTR)
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR4_PRELIM \
 		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 		| BR_PS_8		/* Port Size = 8 bit */ \
 		| BR_MS_FCM		/* MSEL = FCM */ \
 		| BR_V)			/* valid */
 #define CONFIG_SYS_OR4_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR5_PRELIM \
 		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 		| BR_PS_8		/* Port Size = 8 bit */ \
 		| BR_MS_FCM		/* MSEL = FCM */ \
 		| BR_V)			/* valid */
 #define CONFIG_SYS_OR5_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR6_PRELIM \
 		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 		| BR_PS_8		/* Port Size = 8 bit */ \
 		| BR_MS_FCM		/* MSEL = FCM */ \
 		| BR_V)			/* valid */
 #define CONFIG_SYS_OR6_PRELIM	CONFIG_SYS_NAND_OR_PRELIM	/* NAND Options */
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #ifdef CONFIG_NAND_SPL
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
 /*
  * I2C
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
 /*
  * I2C2 EEPROM
  */
 #define CONFIG_ID_EEPROM
 #ifdef CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #endif
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_BUS_NUM	1
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_HARD_SPI
 #if defined(CONFIG_SPI_FLASH)
 #define CONFIG_SF_DEFAULT_SPEED	10000000
 #define CONFIG_SF_DEFAULT_MODE	0
 #endif
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCI1_MEM_BUS		0xf0000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_IO_VIRT		0xffc00000
 #define CONFIG_SYS_PCI1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCI1_IO_PHYS		0xfffc00000ull
 #else
 #define CONFIG_SYS_PCI1_IO_PHYS		0xffc00000
 #endif
 #define CONFIG_SYS_PCI1_IO_SIZE		0x00010000	/* 64k */
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_NAME		"Slot 1"
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xf8000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc10000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x08000000	/* 128M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc10000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc10000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc10000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_NAME		"Slot 2"
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x98000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xf8000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc18000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0x98000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0x98000000
 #endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x08000000	/* 128M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc20000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 #define CONFIG_SYS_PCIE3_NAME		"Slot 3"
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc30000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc30000ull
 #else
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc30000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #if defined(CONFIG_PCI)
 /*PCIE video card used*/
 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE3_IO_VIRT
 /*PCI video card used*/
 /*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
 /* video */
 #if defined(CONFIG_VIDEO)
 #define CONFIG_BIOSEMU
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 #endif
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 #ifndef CONFIG_PCI_PNP
 	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
 	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
 #endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /* SATA */
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
 #endif
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC3"
 #define CONFIG_FSL_SGMII_RISER	1
 #define SGMII_RISER_PHY_OFFSET	0x1c
 #define TSEC1_PHY_ADDR		1	/* TSEC1 -> PHY1 */
 #define TSEC3_PHY_ADDR		0	/* TSEC3 -> PHY0 */
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define CONFIG_ETHPRIME		"eTSEC1"
 #endif	/* CONFIG_TSEC_ENET */
 /*
  * Environment
  */
 #if defined(CONFIG_SYS_RAMBOOT)
 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
 #define CONFIG_ENV_SPI_MAX_HZ	10000000
 #define CONFIG_ENV_SPI_MODE	0
 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
 #define CONFIG_ENV_OFFSET	0xF0000
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #elif defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV  0
 #else
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 #else
 	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 	#define CONFIG_ENV_SIZE		0x2000
 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 /*
  * USB
  */
 #define CONFIG_HAS_FSL_MPH_USB
 #ifdef CONFIG_HAS_FSL_MPH_USB
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #endif
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
 #define CONFIG_HAS_ETH3
 #endif
 #define CONFIG_IPADDR		192.168.1.254
 #define CONFIG_HOSTNAME		unknown
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
 #define CONFIG_SERVERIP		192.168.1.1
 #define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.255.0
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 "netdev=eth0\0"						\
 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
 "tftpflash=tftpboot $loadaddr $uboot; "			\
 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
 		" +$filesize; "	\
 	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
 		" +$filesize; "	\
 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
 		" $filesize; "	\
 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
 		" +$filesize; "	\
 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
 		" $filesize\0"	\
 "consoledev=ttyS0\0"				\
 "ramdiskaddr=2000000\0"			\
 "ramdiskfile=8536ds/ramdisk.uboot\0"		\
 "fdtaddr=1e00000\0"				\
 "fdtfile=8536ds/mpc8536ds.dtb\0"		\
 "bdev=sda3\0"					\
 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 #define CONFIG_HDBOOT				\
  "setenv bootargs root=/dev/$bdev rw "		\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "tftp $loadaddr $bootfile;"			\
  "tftp $fdtaddr $fdtfile;"			\
  "bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND		\
  "setenv bootargs root=/dev/nfs rw "	\
  "nfsroot=$serverip:$rootpath "		\
  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  "console=$consoledev,$baudrate $othbootargs;"	\
  "tftp $loadaddr $bootfile;"		\
  "tftp $fdtaddr $fdtfile;"		\
  "bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND		\
  "setenv bootargs root=/dev/ram rw "	\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "tftp $ramdiskaddr $ramdiskfile;"	\
  "tftp $loadaddr $bootfile;"		\
  "tftp $fdtaddr $fdtfile;"		\
  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 #endif	/* __CONFIG_H */

include/configs/P1010RDB.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /*
  * P010 RDB board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <asm/config_mpc85xx.h>
 #define CONFIG_NAND_FSL_IFC
 #ifdef CONFIG_SDCARD
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x11001000
 #define CONFIG_SPL_TEXT_BASE		0xD0001000
 #define CONFIG_SPL_PAD_TO		0x18000
 #define CONFIG_SPL_MAX_SIZE		(96 * 1024)
 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SPL_MMC_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
 #endif
 #ifdef CONFIG_SPIFLASH
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_SYS_TEXT_BASE		0x11000000
 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #else
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE			0x11001000
 #define CONFIG_SPL_TEXT_BASE			0xD0001000
 #define CONFIG_SPL_PAD_TO			0x18000
 #define CONFIG_SPL_MAX_SIZE			(96 * 1024)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SPL_SPI_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
 #endif
 #endif
 #ifdef CONFIG_NAND
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x00201000
 #define CONFIG_SPL_TEXT_BASE		0xFFFFE000
 #define CONFIG_SPL_MAX_SIZE		8192
 #define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
 #define CONFIG_SPL_RELOC_STACK		0x00100000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #else
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_NAND_INIT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
 #define CONFIG_SPL_TEXT_BASE		0xD0001000
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_NAND_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TEXT_BASE		0xff800000
 #define CONFIG_SPL_MAX_SIZE		8192
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	0xD0000000
 #define CONFIG_SYS_NAND_U_BOOT_START	0xD0000000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
 #endif
 #define CONFIG_SPL_PAD_TO	0x20000
 #define CONFIG_TPL_PAD_TO	0x20000
 #define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE	0x11001000
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 #endif
 #ifdef CONFIG_NAND_SECBOOT	/* NAND Boot */
 #define CONFIG_RAMBOOT_NAND
 #define CONFIG_SYS_TEXT_BASE		0x11000000
 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #endif
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE		0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 /* High Level Configuration Options */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 #if defined(CONFIG_PCI)
 #define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 /*
  * PCI Windows
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_NAME		"mini PCIe Slot"
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
 #endif
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #if defined(CONFIG_TARGET_P1010RDB_PA)
 #define CONFIG_SYS_PCIE2_NAME		"PCIe Slot"
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 #define CONFIG_SYS_PCIE2_NAME		"mini PCIe Slot"
 #endif
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif
 #define CONFIG_TSEC_ENET
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on P1010 RDB */
 #define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for P1010 RDB */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP			1
 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
 #endif
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
 #define CONFIG_PANIC_HANG		/* do not reset board on panic */
 /* DDR Setup */
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM		1
 #define SPD_EEPROM_ADDRESS		0x52
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #ifndef __ASSEMBLY__
 extern unsigned long get_sdram_size(void);
 #endif
 #define CONFIG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
 /* DDR3 Controller Settings */
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
 #define CONFIG_SYS_DDR_RCW_1		0x00000000
 #define CONFIG_SYS_DDR_RCW_2		0x00000000
 #define CONFIG_SYS_DDR_CONTROL		0xc70c0008      /* Type = DDR3  */
 #define CONFIG_SYS_DDR_CONTROL_2	0x24401000
 #define CONFIG_SYS_DDR_TIMING_4		0x00000001
 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
 #define CONFIG_SYS_DDR_TIMING_3_800	0x00030000
 #define CONFIG_SYS_DDR_TIMING_0_800	0x00110104
 #define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b8644
 #define CONFIG_SYS_DDR_TIMING_2_800	0x0FA888CF
 #define CONFIG_SYS_DDR_CLK_CTRL_800	0x03000000
 #define CONFIG_SYS_DDR_MODE_1_800	0x00441420
 #define CONFIG_SYS_DDR_MODE_2_800	0x00000000
 #define CONFIG_SYS_DDR_INTERVAL_800	0x0C300100
 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 /* settings for DDR3 at 667MT/s */
 #define CONFIG_SYS_DDR_TIMING_3_667		0x00010000
 #define CONFIG_SYS_DDR_TIMING_0_667		0x00110004
 #define CONFIG_SYS_DDR_TIMING_1_667		0x5d59e544
 #define CONFIG_SYS_DDR_TIMING_2_667		0x0FA890CD
 #define CONFIG_SYS_DDR_CLK_CTRL_667		0x03000000
 #define CONFIG_SYS_DDR_MODE_1_667		0x00441210
 #define CONFIG_SYS_DDR_MODE_2_667		0x00000000
 #define CONFIG_SYS_DDR_INTERVAL_667		0x0a280000
 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667	0x8675F608
 #define CONFIG_SYS_CCSRBAR			0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW		CONFIG_SYS_CCSRBAR
 /* Don't relocate CCSRBAR while in NAND_SPL */
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 /*
  * Memory map
  *
  * 0x0000_0000	0x3fff_ffff	DDR			1G cacheable
  * 0x8000_0000  0xbfff_ffff	PCI Express Mem		1.5G non-cacheable
  * 0xffc0_0000  0xffc3_ffff	PCI IO range		256k non-cacheable
  *
  * Localbus non-cacheable
  * 0xff80_0000	0xff8f_ffff	NAND Flash		1M non-cacheable
  * 0xffb0_0000	0xffbf_ffff	Board CPLD		1M non-cacheable
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 /*
  * IFC Definitions
  */
 /* NOR Flash on IFC */
 #define CONFIG_SYS_FLASH_BASE		0xee000000
 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 #define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(32*1024*1024)
 #define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(7)
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_FTIM0	FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5)
 #define CONFIG_SYS_NOR_FTIM1	FTIM1_NOR_TACO(0x1e) | \
 				FTIM1_NOR_TRAD_NOR(0x0f)
 #define CONFIG_SYS_NOR_FTIM2	FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWP(0x1c)
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 /* CFI for NOR Flash */
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 /* NAND Flash on IFC */
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITION
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 #if defined(CONFIG_TARGET_P1010RDB_PA)
 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_2	/* RAL = 2 Bytes */ \
 				| CSOR_NAND_PGS_512	/* Page Size = 512b */ \
 				| CSOR_NAND_SPRZ_16	/* Spare size = 16 */ \
 				| CSOR_NAND_PB(32))	/* 32 Pages Per Block */
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 				| CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 				| CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 				| CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 #endif
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #if defined(CONFIG_TARGET_P1010RDB_PA)
 /* NAND Flash Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
 					FTIM0_NAND_TWP(0x0C)   | \
 					FTIM0_NAND_TWCHT(0x04) | \
 					FTIM0_NAND_TWH(0x05)
 #define CONFIG_SYS_NAND_FTIM1		FTIM1_NAND_TADLE(0x1d) | \
 					FTIM1_NAND_TWBE(0x1d)  | \
 					FTIM1_NAND_TRR(0x07)   | \
 					FTIM1_NAND_TRP(0x0c)
 #define CONFIG_SYS_NAND_FTIM2		FTIM2_NAND_TRAD(0x0c) | \
 					FTIM2_NAND_TREH(0x05) | \
 					FTIM2_NAND_TWHRE(0x0f)
 #define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a)  | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3	0x0
 #endif
 #define CONFIG_SYS_NAND_DDR_LAW		11
 /* Set up IFC registers for boot location NOR/NAND */
 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 /* CPLD on IFC */
 #define CONFIG_SYS_CPLD_BASE		0xffb00000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_CPLD_BASE_PHYS	0xfffb00000ull
 #else
 #define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
 #endif
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK3		IFC_AMASK(64*1024)
 #define CONFIG_SYS_CSOR3		0x0
 /* CPLD Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 	defined(CONFIG_RAMBOOT_NAND)
 #define CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #else
 #undef CONFIG_SYS_RAMBOOT
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_A003399_NOR_WORKAROUND
 #endif
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
 						- GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
 /*
  * Config the L2 Cache as L2 SRAM
  */
 #if defined(CONFIG_SPL_BUILD)
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	0xD0001000
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(16 << 10)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(128 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 #elif defined(CONFIG_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	0xD0001000
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 #else
 #define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 #endif
 #endif
 #endif
 /* Serial Port */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
 #define I2C_PCA9557_ADDR1		0x18
 #define I2C_PCA9557_ADDR2		0x19
 #define I2C_PCA9557_BUS_NUM		0
 /* I2C EEPROM */
 #if defined(CONFIG_TARGET_P1010RDB_PB)
 #define CONFIG_ID_EEPROM
 #ifdef CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #endif
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define MAX_NUM_PORTS			9 /* for 128Bytes EEPROM */
 #endif
 /* enable read and write access to EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 /* RTC */
 #define CONFIG_RTC_PT7C4338
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 /*
  * SPI interface will not be available in case of NAND boot SPI CS0 will be
  * used for SLIC
  */
 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 /* eSPI - Enhanced SPI */
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_MII			/* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"eTSEC2"
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC3"
 #define TSEC1_PHY_ADDR		1
 #define TSEC2_PHY_ADDR		0
 #define TSEC3_PHY_ADDR		2
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define CONFIG_ETHPRIME		"eTSEC1"
 /* TBI PHY configuration for SGMII mode */
 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 		TBICR_PHY_RESET \
 		| TBICR_ANEG_ENABLE \
 		| TBICR_FULL_DUPLEX \
 		| TBICR_SPEED1_SET \
 		)
 #endif	/* CONFIG_TSEC_ENET */
 /* SATA */
-#define CONFIG_FSL_SATA
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif /* #ifdef CONFIG_FSL_SATA  */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 #define CONFIG_HAS_FSL_DR_USB
 #if defined(CONFIG_HAS_FSL_DR_USB)
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #endif
 #endif
 /*
  * Environment
  */
 #if defined(CONFIG_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
 #elif defined(CONFIG_SPIFLASH)
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
 #define CONFIG_ENV_SPI_MAX_HZ	10000000
 #define CONFIG_ENV_SPI_MODE	0
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #else
 #if defined(CONFIG_TARGET_P1010RDB_PA)
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 #define CONFIG_ENV_SIZE		(16 * 1024)
 #define CONFIG_ENV_RANGE	(32 * CONFIG_ENV_SIZE) /* new block size 512K */
 #endif
 #endif
 #define CONFIG_ENV_OFFSET	(1024 * 1024)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE			0x2000
 #else
 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 		 || defined(CONFIG_FSL_SATA)
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
 #endif
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"loadaddr=1000000\0"			\
 	"consoledev=ttyS0\0"				\
 	"ramdiskaddr=2000000\0"			\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
 	"fdtaddr=1e00000\0"				\
 	"fdtfile=p1010rdb.dtb\0"		\
 	"bdev=sda1\0"	\
 	"hwconfig=usb1:dr_mode=host,phy_type=utmi\0"	\
 	"othbootargs=ramdisk_size=600000\0" \
 	"usbfatboot=setenv bootargs root=/dev/ram rw "	\
 	"console=$consoledev,$baudrate $othbootargs; "	\
 	"usb start;"			\
 	"fatload usb 0:2 $loadaddr $bootfile;"		\
 	"fatload usb 0:2 $fdtaddr $fdtfile;"	\
 	"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
 	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
 	"console=$consoledev,$baudrate $othbootargs; "	\
 	"usb start;"			\
 	"ext2load usb 0:4 $loadaddr $bootfile;"		\
 	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
 	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
 	CONFIG_BOOTMODE
 #if defined(CONFIG_TARGET_P1010RDB_PA)
 #define CONFIG_BOOTMODE \
 	"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 	"mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 	"boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 	"mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 	"boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 	"mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 #define CONFIG_BOOTMODE \
 	"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 	"i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 	"boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 	"i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 	"boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 	"i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 	"boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 	"i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 	"boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 	"i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 #endif
 #define CONFIG_RAMBOOTCOMMAND		\
 	"setenv bootargs root=/dev/ram rw "	\
 	"console=$consoledev,$baudrate $othbootargs; "	\
 	"tftp $ramdiskaddr $ramdiskfile;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 #include <asm/fsl_secure_boot.h>
 #endif	/* __CONFIG_H */

include/configs/P1022DS.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2010-2012 Freescale Semiconductor, Inc.
  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  *          Timur Tabi <timur@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include "../board/freescale/common/ics307_clk.h"
 #ifdef CONFIG_SDCARD
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x11001000
 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
 #define CONFIG_SPL_PAD_TO		0x20000
 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SPL_MMC_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
 #endif
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x11001000
 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
 #define CONFIG_SPL_PAD_TO		0x20000
 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SPL_SPI_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
 #endif
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_SYS_NAND_MAX_ECCPOS	56
 #define CONFIG_SYS_NAND_MAX_OOBFREE	5
 #ifdef CONFIG_NAND
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_NAND_INIT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TEXT_BASE		0xff800000
 #define CONFIG_SPL_MAX_SIZE		4096
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
 #define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
 #endif
 #define CONFIG_SPL_PAD_TO		0x20000
 #define CONFIG_TPL_PAD_TO		0x20000
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x11001000
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 /* High Level Configuration Options */
 #define CONFIG_MP			/* support multiple processors */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3			/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE
 #define CONFIG_BTB
 #define CONFIG_SYS_MEMTEST_START	0x00000000
 #define CONFIG_SYS_MEMTEST_END		0x7fffffff
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
        SPL code*/
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 /* DDR Setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_VERY_BIG_RAM
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 /* I2C addresses of SPD EEPROMs */
 #define CONFIG_SYS_SPD_BUS_NUM		1
 #define SPD_EEPROM_ADDRESS		0x51	/* CTLR 0 DIMM 0 */
 /* These are used when DDR doesn't use SPD.  */
 #define CONFIG_SYS_SDRAM_SIZE		2048
 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
 #define CONFIG_SYS_DDR_CS1_BNDS		0x0040007F
 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80014202
 #define CONFIG_SYS_DDR_TIMING_3		0x00010000
 #define CONFIG_SYS_DDR_TIMING_0		0x40110104
 #define CONFIG_SYS_DDR_TIMING_1		0x5c5bd746
 #define CONFIG_SYS_DDR_TIMING_2		0x0fa8d4ca
 #define CONFIG_SYS_DDR_MODE_1		0x00441221
 #define CONFIG_SYS_DDR_MODE_2		0x00000000
 #define CONFIG_SYS_DDR_INTERVAL		0x0a280100
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
 #define CONFIG_SYS_DDR_CLK_CTRL		0x02800000
 #define CONFIG_SYS_DDR_CONTROL		0xc7000008
 #define CONFIG_SYS_DDR_CONTROL_2	0x24401041
 #define	CONFIG_SYS_DDR_TIMING_4		0x00220001
 #define	CONFIG_SYS_DDR_TIMING_5		0x02401400
 #define	CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8675f608
 /*
  * Memory map
  *
  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
  * 0x8000_0000	0xdfff_ffff	PCI Express Mem		1.5G non-cacheable
  * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
  *
  * Localbus cacheable (TBD)
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
  * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
  * 0xff80_0000	0xff80_7fff	NAND			32K non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 /*
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe8000000 /* start of FLASH 128M */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe8000000ull
 #else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 #define CONFIG_FLASH_BR_PRELIM  \
 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM	(OR_AM_128MB | 0xff7)
 #ifdef CONFIG_NAND
 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
 #define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
 #else
 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 #endif
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	1024
 #ifndef CONFIG_SYS_MONITOR_BASE
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 #endif
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 /* Nand Flash */
 #if defined(CONFIG_NAND_FSL_ELBC)
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 /* NAND flash config */
 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB	       /* length 256K */ \
 			       | OR_FCM_PGS	       /* Large Page*/ \
 			       | OR_FCM_CSCT \
 			       | OR_FCM_CST \
 			       | OR_FCM_CHT \
 			       | OR_FCM_SCY_1 \
 			       | OR_FCM_TRLX \
 			       | OR_FCM_EHTR)
 #ifdef CONFIG_NAND
 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #else
 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #endif
 #endif /* CONFIG_NAND_FSL_ELBC */
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 #define CONFIG_FSL_NGPIXIS
 #define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS		0xfffdf0000ull
 #else
 #define PIXIS_BASE_PHYS		PIXIS_BASE
 #endif
 #define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB | 0x6ff7)
 #define PIXIS_LBMAP_SWITCH	7
 #define PIXIS_LBMAP_MASK	0xF0
 #define PIXIS_LBMAP_ALTBANK	0x20
 #define PIXIS_SPD		0x07
 #define PIXIS_SPD_SYSCLK_MASK	0x07
 #define PIXIS_ELBC_SPI_MASK	0xc0
 #define PIXIS_SPI		0x80
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000 /* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 /*
  * Config the L2 Cache as L2 SRAM
 */
 #if defined(CONFIG_SPL_BUILD)
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 #elif defined(CONFIG_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 #else
 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 #endif
 #endif
 #endif
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 /* Video */
 #ifdef CONFIG_FSL_DIU_FB
 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 /*
  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  * disable empty flash sector detection, which is I/O-intensive.
  */
 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 #endif
 #ifndef CONFIG_FSL_DIU_FB
 #endif
 #ifdef CONFIG_ATI
 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
 #define CONFIG_BIOSEMU
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 #endif
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
 #define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
 /*
  * I2C2 EEPROM
  */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_BUS_NUM	1
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_HARD_SPI
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		0
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
 #else
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif
 /* SATA */
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
 #endif
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 #define CONFIG_TSEC_ENET
 #ifdef CONFIG_TSEC_ENET
 #define CONFIG_TSECV2
 #define CONFIG_MII			/* MII PHY management */
 #define CONFIG_TSEC1		1
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define CONFIG_TSEC2		1
 #define CONFIG_TSEC2_NAME	"eTSEC2"
 #define TSEC1_PHY_ADDR		1
 #define TSEC2_PHY_ADDR		2
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define CONFIG_ETHPRIME		"eTSEC1"
 #endif
 /*
  * Dynamic MTD Partition support with mtdparts
  */
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_FLASH_CFI_MTD
 /*
  * Environment
  */
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
 #define CONFIG_ENV_SPI_MAX_HZ	10000000
 #define CONFIG_ENV_SPI_MODE	0
 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #elif defined(CONFIG_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #else
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 #endif
 #define CONFIG_ENV_OFFSET	(1024 * 1024)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 /*
  * USB
  */
 #define CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #endif
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_HOSTNAME		p1022ds
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 #define CONFIG_LOADADDR		1000000
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 		"protect off $ubootaddr +$filesize && "		\
 		"erase $ubootaddr +$filesize && "		\
 		"cp.b $loadaddr $ubootaddr $filesize && "	\
 		"protect on $ubootaddr +$filesize && "		\
 		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
 	"fdtaddr=1e00000\0"	  			      	\
 	"fdtfile=p1022ds.dtb\0"	  				\
 	"bdev=sda3\0"		  			      	\
 	"hwconfig=esdhc;audclk:12\0"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv bootargs root=/dev/nfs rw "				\
 	"nfsroot=$serverip:$rootpath "					\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"setenv bootargs root=/dev/ram rw "				\
 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
 #endif

include/configs/P2041RDB.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /*
  * P2041 RDB board configuration file
  * Also supports P2040 RDB
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
 #endif
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MP			/* support multiple processors */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
 #define CONFIG_ENV_OVERWRITE
 #ifndef CONFIG_MTD_NOR_FLASH
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #if defined(CONFIG_SPIFLASH)
 	#define CONFIG_SYS_EXTRA_ENV_RELOC
 	#define CONFIG_ENV_SPI_BUS              0
 	#define CONFIG_ENV_SPI_CS               0
 	#define CONFIG_ENV_SPI_MAX_HZ           10000000
 	#define CONFIG_ENV_SPI_MODE             0
 	#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 	#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 	#define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
 	#define CONFIG_SYS_EXTRA_ENV_RELOC
 	#define CONFIG_FSL_FIXED_MMC_LOCATION
 	#define CONFIG_SYS_MMC_ENV_DEV          0
 	#define CONFIG_ENV_SIZE			0x2000
 	#define CONFIG_ENV_OFFSET		(512 * 1658)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_ADDR		0xffe20000
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_ENV_IS_NOWHERE)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
 			- CONFIG_ENV_SECT_SIZE)
 	#define CONFIG_ENV_SIZE		0x2000
 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #endif
 #define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
 		CONFIG_RAMBOOT_TEXT_BASE)
 #else
 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
 #endif
 #define CONFIG_SYS_L3_SIZE		(1024 << 10)
 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 #endif
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x52
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 /*
  * Local Bus Definitions
  */
 /* Set the local bus clock 1/8 of platform clock */
 #define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
 /*
  * This board doesn't have a promjet connector.
  * However, it uses commone corenet board LAW and TLB.
  * It is necessary to use the same start address with proper offset.
  */
 #define CONFIG_SYS_FLASH_BASE		0xe0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
 #else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 #define CONFIG_SYS_FLASH_BR_PRELIM \
 		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 		BR_PS_16 | BR_V)
 #define CONFIG_SYS_FLASH_OR_PRELIM \
 		((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 		 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 #define CONFIG_FSL_CPLD
 #define CPLD_BASE		0xffdf0000	/* CPLD registers */
 #ifdef CONFIG_PHYS_64BIT
 #define CPLD_BASE_PHYS		0xfffdf0000ull
 #else
 #define CPLD_BASE_PHYS		CPLD_BASE
 #endif
 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
 #define PIXIS_LBMAP_SWITCH	7
 #define PIXIS_LBMAP_MASK	0xf0
 #define PIXIS_LBMAP_SHIFT	4
 #define PIXIS_LBMAP_ALTBANK	0x40
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_NAND_FSL_ELBC
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
 #define CONFIG_SYS_NAND_BASE		0xffa00000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 /* NAND flash config */
 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
 			       | OR_FCM_PGS	       /* Large Page*/ \
 			       | OR_FCM_CSCT \
 			       | OR_FCM_CST \
 			       | OR_FCM_CHT \
 			       | OR_FCM_SCY_1 \
 			       | OR_FCM_TRLX \
 			       | OR_FCM_EHTR)
 #ifdef CONFIG_NAND
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #else
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #endif
 #else
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #endif /* CONFIG_NAND_FSL_ELBC */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
 /*
  * RapidIO
  */
 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #else
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
 #endif
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
 /* slave core release by master*/
 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 /*
  * SRIO_PCIE_BOOT - SLAVE
  */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
 #else
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
 #endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #else
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 /* Qman/Bman */
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #else
 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
 #else
 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
  * in two corenet boards, slave's ucode could be stored in master's memory
  * space, the address can be mapped from slave TLB->slave LAW->
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_TERANETICS
 #endif
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /* SATA */
 #define CONFIG_FSL_SATA_V2
 #ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_FSL_SATA
 #define CONFIG_LIBATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x2
 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x3
 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x4
 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1
 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x0
 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR	0x1c
 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR	0x1d
 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR	0x1e
 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR	0x1f
 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	0
 #define CONFIG_SYS_TBIPA_VALUE	8
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * Command line configuration.
  */
 /*
 * USB
 */
 #define CONFIG_HAS_FSL_DR_USB
 #define CONFIG_HAS_FSL_MPH_USB
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define __USB_PHY_TYPE	utmi
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
 	"bank_intlv=cs0_cs1\0"					\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
 	"usb_dr_mode=host\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=p2041rdb/ramdisk.uboot\0"			\
 	"fdtaddr=1e00000\0"					\
 	"fdtfile=p2041rdb/p2041rdb.dtb\0"			\
 	"bdev=sda3\0"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 #include <asm/fsl_secure_boot.h>
 #endif	/* __CONFIG_H */

include/configs/T102xQDS.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 /*
  * T1024/T1023 QDS board configuration file
  */
 #ifndef __T1024QDS_H
 #define __T1024QDS_H
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MP			/* support multiple processors */
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP		1
 #define CONFIG_SYS_NUM_ADDR_MAP	64	/* number of TLB1 entries */
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_DEEP_SLEEP
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x00201000
 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
 #define CONFIG_SPL_PAD_TO		0x40000
 #define CONFIG_SPL_MAX_SIZE		0x28000
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_SKIP_RELOCATE
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 #ifdef CONFIG_NAND
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
 #define CONFIG_SPL_NAND_BOOT
 #endif
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
 #define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
 #define CONFIG_SPL_SPI_BOOT
 #endif
 #ifdef CONFIG_SDCARD
 #define CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
 #define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
 #define CONFIG_SPL_MMC_BOOT
 #endif
 #endif /* CONFIG_RAMBOOT_PBL */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 /* PCIe Boot - Master */
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 #else
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 #endif
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS	 0x3ffe00000ull
 #else
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 #endif
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 /* slave core release by master*/
 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 /* PCIe Boot - Slave */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 /* Set 1M boot space for PCIe boot */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_CS		0
 #define CONFIG_ENV_SPI_MAX_HZ		10000000
 #define CONFIG_ENV_SPI_MODE		0
 #define CONFIG_ENV_SIZE			0x2000		/* 8KB */
 #define CONFIG_ENV_OFFSET		0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE		0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 0x800)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_ADDR		0xffe20000
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_ENV_IS_NOWHERE)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_SYS_MEMTEST_START	0x00200000 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define CONFIG_SYS_L3_SIZE		(256 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 #endif
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 #endif
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x51
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
 #define QIXIS_BASE		0xffdf0000
 #ifdef CONFIG_PHYS_64BIT
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 #else
 #define QIXIS_BASE_PHYS		QIXIS_BASE
 #endif
 #define QIXIS_LBMAP_SWITCH		0x06
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
 #define QIXIS_RST_CTL_RESET		0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define	QIXIS_RST_FORCE_MEM		0x01
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
 #define CONFIG_SYS_CSOR3	0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 #endif
 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
 				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3		0x0
 #define CONFIG_SYS_NAND_DDR_LAW		11
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #endif
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 /* Serial Port */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 /* Video */
 #ifdef CONFIG_ARCH_T1024		/* no DIU on T1023 */
 #define CONFIG_FSL_DIU_FB
 #ifdef CONFIG_FSL_DIU_FB
 #define CONFIG_FSL_DIU_CH7301
 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 /*
  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  * disable empty flash sector detection, which is I/O-intensive.
  */
 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 #endif
 #endif
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_SPEED	50000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
 #define I2C_MUX_PCA_ADDR		0x77
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 #define I2C_RETIMER_ADDR		0x18
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
 #define I2C_MUX_CH_DIU		0xC
 #define I2C_MUX_CH5		0xD
 #define I2C_MUX_CH7		0xF
 /* LDI/DVI Encoder for display */
 #define CONFIG_SYS_I2C_LDI_ADDR	 0x38
 #define CONFIG_SYS_I2C_DVI_ADDR	 0x75
 /*
  * RTC configuration
  */
 #define RTC
 #define CONFIG_RTC_DS3231	1
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 /*
  * eSPI - Enhanced SPI
  */
 #ifndef CONFIG_SPL_BUILD
 #endif
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED	 10000000
 #define CONFIG_SF_DEFAULT_MODE	  0
 /*
  * General PCIe
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
 #define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0x90000000
 #endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #else
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /*
  *SATA
  */
 #define CONFIG_FSL_SATA_V2
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	1
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 /*
  * USB
  */
 #define CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
 /*
  * SDHC
  */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #else
 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #else
 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_QE
 #define CONFIG_U_QE
 /* Default address of microcode for the Linux FMan driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #define CONFIG_SYS_QE_FW_ADDR	0x130000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
 #define CONFIG_SYS_QE_FW_ADDR		(512 * 0x920)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_SYS_QE_FW_ADDR		(12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
  * in two corenet boards, slave's ucode could be stored in master's memory
  * space, the address can be mapped from slave TLB->slave LAW->
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #define CONFIG_SYS_QE_FW_ADDR		0xEFE00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_TERANETICS
 #define RGMII_PHY1_ADDR		0x1
 #define RGMII_PHY2_ADDR		0x2
 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC4"
 #endif
 /*
  * Dynamic MTD Partition support with mtdparts
  */
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_FLASH_CFI_MTD
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
 #define CONFIG_LOADADDR		1000000 /* default location for tftp, bootm */
 #define __USB_PHY_TYPE		utmi
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 	"ramdiskfile=t1024qds/ramdisk.uboot\0"			\
 	"fdtfile=t1024qds/t1024qds.dtb\0"			\
 	"netdev=eth0\0"						\
 	"video-mode=fslfb:1024x768-32@60,monitor=dvi\0"		\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"fdtaddr=d00000\0"					\
 	"bdev=sda3\0"
 #define CONFIG_LINUX					\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"setenv ramdiskaddr 0x02000000;"		\
 	"setenv fdtaddr 0x00c00000;"			\
 	"setenv loadaddr 0x1000000;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_BOOTCOMMAND	CONFIG_LINUX
 #include <asm/fsl_secure_boot.h>
 #endif	/* __T1024QDS_H */

include/configs/T1040QDS.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * T1040 QDS board configuration file
  */
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
 #endif
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MP			/* support multiple processors */
 /* support deep sleep */
 #define CONFIG_DEEP_SLEEP
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_PCIE4			/* PCIE controller 4 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_ENV_OVERWRITE
 #ifndef CONFIG_MTD_NOR_FLASH
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #ifdef CONFIG_MTD_NOR_FLASH
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SPI_BUS              0
 #define CONFIG_ENV_SPI_CS               0
 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 #define CONFIG_ENV_SPI_MODE             0
 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 1658)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #else /* CONFIG_MTD_NOR_FLASH */
 #define CONFIG_ENV_SIZE                0x2000
 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
 #endif
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_ENABLE_36BIT_PHYS
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_DDR_SPD
 #define CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x51
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /*
  * TDM Definition
  */
 #define T1040_TDM_QUIRK_CCSR_BASE	0xfe000000
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
 #define QIXIS_BASE		0xffdf0000
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 #define QIXIS_LBMAP_SWITCH		0x06
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
 #define QIXIS_RST_CTL_RESET		0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define	QIXIS_RST_FORCE_MEM		0x01
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
 #define CONFIG_SYS_CSOR3	0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
 				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3		0x0
 #define CONFIG_SYS_NAND_DDR_LAW		11
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 /* Video */
 #define CONFIG_FSL_DIU_FB
 #ifdef CONFIG_FSL_DIU_FB
 #define CONFIG_FSL_DIU_CH7301
 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 /*
  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  * disable empty flash sector detection, which is I/O-intensive.
  */
 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 #endif
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C2_SPEED	50000
 #define CONFIG_SYS_FSL_I2C3_SPEED	50000
 #define CONFIG_SYS_FSL_I2C4_SPEED	50000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C3_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C4_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
 #define CONFIG_SYS_FSL_I2C3_OFFSET	0x119000
 #define CONFIG_SYS_FSL_I2C4_OFFSET	0x119100
 #define I2C_MUX_PCA_ADDR		0x77
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
 #define I2C_MUX_CH_DIU		0xC
 /* LDI/DVI Encoder for display */
 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 /*
  * RTC configuration
  */
 #define RTC
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
 #define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 4, Base address 203000 */
 #ifdef CONFIG_PCIE4
 #define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /* SATA */
 #define CONFIG_FSL_SATA_V2
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 /*
 * USB
 */
 #define CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
 #endif
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 #endif
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 #define CONFIG_QE
 #define CONFIG_U_QE
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #define CONFIG_SYS_QE_FW_ADDR		0xEFF10000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_TERANETICS
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x01
 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x02
 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #endif
 /* Enable VSC9953 L2 Switch driver */
 #define CONFIG_VSC9953
 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x14
 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x18
 /*
  * Dynamic MTD Partition support with mtdparts
  */
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_FLASH_CFI_MTD
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define __USB_PHY_TYPE	utmi
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:bank_intlv=auto;"			\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"video-mode=fslfb:1024x768-32@60,monitor=dvi\0"		\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t1040qds/ramdisk.uboot\0"			\
 	"fdtaddr=1e00000\0"					\
 	"fdtfile=t1040qds/t1040qds.dtb\0"			\
 	"bdev=sda3\0"
 #define CONFIG_LINUX                       \
 	"setenv bootargs root=/dev/ram rw "            \
 	"console=$consoledev,$baudrate $othbootargs;"  \
 	"setenv ramdiskaddr 0x02000000;"               \
 	"setenv fdtaddr 0x00c00000;"		       \
 	"setenv loadaddr 0x1000000;"		       \
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 #include <asm/fsl_secure_boot.h>
 #endif	/* __CONFIG_H */

include/configs/T104xRDB.h

Diff comments View file @ 9920d15

 /*
 + * Copyright 2014 Freescale Semiconductor, Inc.
 + *
 + * SPDX-License-Identifier:     GPL-2.0+
 + */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * T104x RDB board configuration file
  */
 #include <asm/config_mpc85xx.h>
 #ifdef CONFIG_RAMBOOT_PBL
 #ifndef CONFIG_SECURE_BOOT
 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
 #else
 #define CONFIG_SYS_FSL_PBL_PBI \
 		$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
 #endif
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x30001000
 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
 #define CONFIG_SPL_PAD_TO		0x40000
 #define CONFIG_SPL_MAX_SIZE		0x28000
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_SKIP_RELOCATE
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
 #ifdef CONFIG_NAND
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
 /*
  * HDR would be appended at end of image and copied to DDR along
  * with U-Boot image.
  */
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + \
 					 CONFIG_U_BOOT_HDR_SIZE)
 #else
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #endif
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
 #define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #ifdef CONFIG_TARGET_T1040RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1042RDB_PI
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1042RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1040D4RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1042D4RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
 #endif
 #define CONFIG_SPL_NAND_BOOT
 #endif
 #ifdef CONFIG_SPIFLASH
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #ifndef CONFIG_SPL_BUILD
 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #ifdef CONFIG_TARGET_T1040RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1042RDB_PI
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1042RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1040D4RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1042D4RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
 #endif
 #define CONFIG_SPL_SPI_BOOT
 #endif
 #ifdef CONFIG_SDCARD
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
 #define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #ifndef CONFIG_SPL_BUILD
 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #ifdef CONFIG_TARGET_T1040RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1042RDB_PI
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1042RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1040D4RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
 #endif
 #ifdef CONFIG_TARGET_T1042D4RDB
 #define CONFIG_SYS_FSL_PBL_RCW \
 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #endif
 #define CONFIG_SPL_MMC_BOOT
 #endif
 #endif
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MP			/* support multiple processors */
 /* support deep sleep */
 #define CONFIG_DEEP_SLEEP
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_PCIE4			/* PCIE controller 4 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_ENV_OVERWRITE
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 0x800)
 #elif defined(CONFIG_NAND)
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_RAMBOOT_NAND
 #define CONFIG_BOOTSCRIPT_COPY_RAM
 #endif
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	66666666
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_ENABLE_36BIT_PHYS
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
 /*
  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
  */
 #define CONFIG_SYS_INIT_L3_VADDR	0xFFFC0000
 #define CONFIG_SYS_L3_SIZE		256 << 10
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 #endif
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x51
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe8000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_NOR_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /*
  * TDM Definition
  */
 #define T1040_TDM_QUIRK_CCSR_BASE	0xfe000000
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
 /* CPLD on IFC */
 #define CPLD_LBMAP_MASK			0x3F
 #define CPLD_BANK_SEL_MASK		0x07
 #define CPLD_BANK_OVERRIDE		0x40
 #define CPLD_LBMAP_ALTBANK		0x44 /* BANK OR | BANK 4 */
 #define CPLD_LBMAP_DFLTBANK		0x40 /* BANK OR | BANK0 */
 #define CPLD_LBMAP_RESET		0xFF
 #define CPLD_LBMAP_SHIFT		0x03
 #if defined(CONFIG_TARGET_T1042RDB_PI)
 #define CPLD_DIU_SEL_DFP		0x80
 #elif defined(CONFIG_TARGET_T1042D4RDB)
 #define CPLD_DIU_SEL_DFP		0xc0
 #endif
 #if defined(CONFIG_TARGET_T1040D4RDB)
 #define CPLD_INT_MASK_ALL		0xFF
 #define CPLD_INT_MASK_THERM		0x80
 #define CPLD_INT_MASK_DVI_DFP		0x40
 #define CPLD_INT_MASK_QSGMII1		0x20
 #define CPLD_INT_MASK_QSGMII2		0x10
 #define CPLD_INT_MASK_SGMI1		0x08
 #define CPLD_INT_MASK_SGMI2		0x04
 #define CPLD_INT_MASK_TDMR1		0x02
 #define CPLD_INT_MASK_TDMR2		0x01
 #endif
 #define CONFIG_SYS_CPLD_BASE	0xffdf0000
 #define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 #define CONFIG_SYS_CSPR2_EXT	(0xf)
 #define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
 #define CONFIG_SYS_CSOR2	0x0
 /* CPLD Timing parameters for IFC CS2 */
 #define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3		0x0
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
 				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
 				| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3		0x0
 #define CONFIG_SYS_NAND_DDR_LAW		11
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 #if defined(CONFIG_NAND)
 #define CONFIG_A008044_WORKAROUND
 #endif
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 /* Video */
 #define CONFIG_FSL_DIU_FB
 #ifdef CONFIG_FSL_DIU_FB
 #define CONFIG_FSL_DIU_CH7301
 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 #endif
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C3_SPEED	400000
 #define CONFIG_SYS_FSL_I2C4_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C3_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C4_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
 #define CONFIG_SYS_FSL_I2C3_OFFSET	0x119000
 #define CONFIG_SYS_FSL_I2C4_OFFSET	0x119100
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
 #define I2C_MUX_CH_DEFAULT      0x8
 #if defined(CONFIG_TARGET_T1042RDB_PI)	|| \
 	defined(CONFIG_TARGET_T1040D4RDB)	|| \
 	defined(CONFIG_TARGET_T1042D4RDB)
 /* LDI/DVI Encoder for display */
 #define CONFIG_SYS_I2C_LDI_ADDR		0x38
 #define CONFIG_SYS_I2C_DVI_ADDR		0x75
 /*
  * RTC configuration
  */
 #define RTC
 #define CONFIG_RTC_DS1337               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 /*DVI encoder*/
 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 #endif
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 #define CONFIG_ENV_SPI_BUS              0
 #define CONFIG_ENV_SPI_CS               0
 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 #define CONFIG_ENV_SPI_MODE             0
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
 #define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #endif
 /* controller 4, Base address 203000 */
 #ifdef CONFIG_PCIE4
 #define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /* SATA */
 #define CONFIG_FSL_SATA_V2
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	1
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 /*
 * USB
 */
 #define CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 #endif
 #endif
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 #define CONFIG_QE
 #define CONFIG_U_QE
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_QE_FW_ADDR		0x130000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_QE_FW_ADDR		(512 * 0x920)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FW_ADDR		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_QE_FW_ADDR		0xEFF10000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #endif
 #ifdef CONFIG_FMAN_ENET
 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 #elif defined(CONFIG_TARGET_T1040D4RDB)
 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 #elif defined(CONFIG_TARGET_T1042D4RDB)
 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 #endif
 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 #else
 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 #endif
 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 #define CONFIG_VSC9953
 #ifdef CONFIG_TARGET_T1040RDB
 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x04
 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x08
 #else
 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x08
 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x0c
 #endif
 #endif
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC4"
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Dynamic MTD Partition support with mtdparts
  */
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_FLASH_CFI_MTD
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define __USB_PHY_TYPE	utmi
 #define RAMDISKFILE	"t104xrdb/ramdisk.uboot"
 #ifdef CONFIG_TARGET_T1040RDB
 #define FDTFILE		"t1040rdb/t1040rdb.dtb"
 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 #define FDTFILE		"t1042rdb_pi/t1042rdb_pi.dtb"
 #elif defined(CONFIG_TARGET_T1042RDB)
 #define FDTFILE		"t1042rdb/t1042rdb.dtb"
 #elif defined(CONFIG_TARGET_T1040D4RDB)
 #define FDTFILE		"t1042rdb/t1040d4rdb.dtb"
 #elif defined(CONFIG_TARGET_T1042D4RDB)
 #define FDTFILE		"t1042rdb/t1042d4rdb.dtb"
 #endif
 #ifdef CONFIG_FSL_DIU_FB
 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 #else
 #define DIU_ENVIRONMENT
 #endif
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"			\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 	"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"video-mode=" __stringify(DIU_ENVIRONMENT) "\0"		\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=" __stringify(RAMDISKFILE) "\0"		\
 	"fdtaddr=1e00000\0"					\
 	"fdtfile=" __stringify(FDTFILE) "\0"			\
 	"bdev=sda3\0"
 #define CONFIG_LINUX                       \
 	"setenv bootargs root=/dev/ram rw "            \
 	"console=$consoledev,$baudrate $othbootargs;"  \
 	"setenv ramdiskaddr 0x02000000;"               \
 	"setenv fdtaddr 0x00c00000;"		       \
 	"setenv loadaddr 0x1000000;"		       \
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 #include <asm/fsl_secure_boot.h>
 #endif	/* __CONFIG_H */

include/configs/T208xQDS.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2011-2013 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 /*
  * T2080/T2081 QDS board configuration file
  */
 #ifndef __T208xQDS_H
 #define __T208xQDS_H
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
 #if defined(CONFIG_ARCH_T2080)
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
 #define CONFIG_SRIO1		/* SRIO port 1 */
 #define CONFIG_SRIO2		/* SRIO port 2 */
 #elif defined(CONFIG_ARCH_T2081)
 #endif
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
 #define CONFIG_MP		/* support multiple processors */
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP 1
 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
 #endif
 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_ENV_OVERWRITE
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x00201000
 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
 #define CONFIG_SPL_PAD_TO		0x40000
 #define CONFIG_SPL_MAX_SIZE		0x28000
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_SKIP_RELOCATE
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 #ifdef CONFIG_NAND
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #if defined(CONFIG_ARCH_T2080)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
 #elif defined(CONFIG_ARCH_T2081)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
 #endif
 #define CONFIG_SPL_NAND_BOOT
 #endif
 #ifdef CONFIG_SPIFLASH
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #ifndef CONFIG_SPL_BUILD
 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #if defined(CONFIG_ARCH_T2080)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
 #elif defined(CONFIG_ARCH_T2081)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
 #endif
 #define CONFIG_SPL_SPI_BOOT
 #endif
 #ifdef CONFIG_SDCARD
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
 #define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #ifndef CONFIG_SPL_BUILD
 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #if defined(CONFIG_ARCH_T2080)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
 #elif defined(CONFIG_ARCH_T2081)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
 #endif
 #define CONFIG_SPL_MMC_BOOT
 #endif
 #endif /* CONFIG_RAMBOOT_PBL */
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BTB		/* toggle branch predition */
 #define CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
 #define CONFIG_ENV_SPI_MAX_HZ	10000000
 #define CONFIG_ENV_SPI_MODE	0
 #define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
 #define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_OFFSET	(512 * 0x800)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_OFFSET	(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_ADDR		0xffe20000
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_ENV_IS_NOWHERE)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
 /*
  * Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define CONFIG_SYS_L3_SIZE		(512 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 #endif
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
 #define CONFIG_SYS_DCSRBAR	0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 #define CONFIG_DDR_SPD
 #define CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 #define CTRL_INTLV_PREFERED	cacheline
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe0000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
 #define QIXIS_BASE			0xffdf0000
 #define QIXIS_LBMAP_SWITCH		6
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
 #define QIXIS_LBMAP_NAND		0x09
 #define QIXIS_LBMAP_SD			0x00
 #define QIXIS_RCW_SRC_NAND		0x104
 #define QIXIS_RCW_SRC_SD		0x040
 #define QIXIS_RST_CTL_RESET		0x83
 #define QIXIS_RST_FORCE_MEM		0x1
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
 #define CONFIG_SYS_CSOR3	0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)    | \
 					FTIM0_NAND_TWCHT(0x07)  | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)   | \
 					FTIM1_NAND_TRR(0x0e)    | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
 					FTIM2_NAND_TREH(0x0a)   | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3		0x0
 #define CONFIG_SYS_NAND_DDR_LAW		11
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 /*
  * I2C
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 #define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
 #define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
 #define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
 #define I2C_MUX_CH_DEFAULT	0x8
 #define I2C_MUX_CH_VOL_MONITOR 0xa
 /* Voltage monitor on channel 2*/
 #define I2C_VOL_MONITOR_ADDR           0x40
 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 #define CONFIG_VID_FLS_ENV		"t208xqds_vdd_mv"
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_VID
 #endif
 #define CONFIG_VOL_MONITOR_IR36021_SET
 #define CONFIG_VOL_MONITOR_IR36021_READ
 /* The lowest and highest voltage allowed for T208xQDS */
 #define VDD_MV_MIN			819
 #define VDD_MV_MAX			1212
 /*
  * RapidIO
  */
 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
 /* slave core release by master*/
 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 /*
  * SRIO_PCIE_BOOT - SLAVE
  */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 /*
  * eSPI - Enhanced SPI
  */
 #ifdef CONFIG_SPI_FLASH
 #ifndef CONFIG_SPL_BUILD
 #endif
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED	 10000000
 #define CONFIG_SF_DEFAULT_MODE	  0
 #endif
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
 #define CONFIG_PCIE4		/* PCIE controller 4 */
 #define CONFIG_FSL_PCIE_RESET
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_FSL_PCIE_RESET	   /* need PCIe reset errata */
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	18
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	18
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 #define CONFIG_SYS_PMAN
 #define CONFIG_SYS_DPAA_DCE
 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
 #define CONFIG_SYS_INTERLAKEN
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
  * in two corenet boards, slave's ucode could be stored in master's memory
  * space, the address can be mapped from slave TLB->slave LAW->
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_TERANETICS
 #define RGMII_PHY1_ADDR	0x1
 #define RGMII_PHY2_ADDR	0x2
 #define FM1_10GEC1_PHY_ADDR	  0x3
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC3"
 #endif
 /*
  * SATA
  */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 /*
  * USB
  */
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_HAS_FSL_DR_USB
 #endif
 /*
  * SDHC
  */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 #endif
 /*
  * Dynamic MTD Partition support with mtdparts
  */
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_FLASH_CFI_MTD
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH	 "/opt/nfsroot"
 #define CONFIG_BOOTFILE	 "uImage"
 #define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define __USB_PHY_TYPE		utmi
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:"					\
 	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
 	"bank_intlv=auto;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
 	"fdtaddr=1e00000\0"					\
 	"fdtfile=t2080qds/t2080qds.dtb\0"			\
 	"bdev=sda3\0"
 /*
  * For emulation this causes u-boot to jump to the start of the
  * proof point app code automatically
  */
 #define CONFIG_PROOF_POINTS				\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"cpu 1 release 0x29000000 - - -;"		\
 	"cpu 2 release 0x29000000 - - -;"		\
 	"cpu 3 release 0x29000000 - - -;"		\
 	"cpu 4 release 0x29000000 - - -;"		\
 	"cpu 5 release 0x29000000 - - -;"		\
 	"cpu 6 release 0x29000000 - - -;"		\
 	"cpu 7 release 0x29000000 - - -;"		\
 	"go 0x29000000"
 #define CONFIG_HVBOOT				\
 	"setenv bootargs config-addr=0x60000000; "	\
 	"bootm 0x01000000 - 0x00f00000"
 #define CONFIG_ALU				\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"cpu 1 release 0x01000000 - - -;"		\
 	"cpu 2 release 0x01000000 - - -;"		\
 	"cpu 3 release 0x01000000 - - -;"		\
 	"cpu 4 release 0x01000000 - - -;"		\
 	"cpu 5 release 0x01000000 - - -;"		\
 	"cpu 6 release 0x01000000 - - -;"		\
 	"cpu 7 release 0x01000000 - - -;"		\
 	"go 0x01000000"
 #define CONFIG_LINUX				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"setenv ramdiskaddr 0x02000000;"		\
 	"setenv fdtaddr 0x00c00000;"			\
 	"setenv loadaddr 0x1000000;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 #include <asm/fsl_secure_boot.h>
 #endif	/* __T208xQDS_H */

include/configs/T208xRDB.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 /*
  * T2080 RDB/PCIe board configuration file
  */
 #ifndef __T2080RDB_H
 #define __T2080RDB_H
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
 #define CONFIG_FSL_SATA_V2
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
 #define CONFIG_MP		/* support multiple processors */
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP 1
 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
 #endif
 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_ENV_OVERWRITE
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x00201000
 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
 #define CONFIG_SPL_PAD_TO		0x40000
 #define CONFIG_SPL_MAX_SIZE		0x28000
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_SKIP_RELOCATE
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 #ifdef CONFIG_NAND
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
 #define CONFIG_SPL_NAND_BOOT
 #endif
 #ifdef CONFIG_SPIFLASH
 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
 #define CONFIG_SPL_SPI_BOOT
 #endif
 #ifdef CONFIG_SDCARD
 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
 #define CONFIG_SPL_MMC_BOOT
 #endif
 #endif /* CONFIG_RAMBOOT_PBL */
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BTB		/* toggle branch predition */
 #define CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_SYS_MEMTEST_START	0x00200000 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
 #define CONFIG_ENV_SPI_MAX_HZ	10000000
 #define CONFIG_ENV_SPI_MODE	0
 #define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
 #define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_OFFSET	(512 * 0x800)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_OFFSET	(2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_ADDR		0xffe20000
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_ENV_IS_NOWHERE)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 #define CONFIG_SYS_CLK_FREQ	66660000
 #define CONFIG_DDR_CLK_FREQ	133330000
 /*
  * Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define CONFIG_SYS_L3_SIZE		(512 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 #endif
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
 #define CONFIG_SYS_DCSRBAR	0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_DDR_SPD
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 #define CTRL_INTLV_PREFERED	cacheline
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe8000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS }
 /* CPLD on IFC */
 #define CONFIG_SYS_CPLD_BASE	0xffdf0000
 #define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 #define CONFIG_SYS_CSPR2_EXT	(0xf)
 #define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
 #define CONFIG_SYS_CSOR2	0x0
 /* CPLD Timing parameters for IFC CS2 */
 #define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3		0x0
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)    | \
 					FTIM0_NAND_TWCHT(0x07)  | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)   | \
 					FTIM1_NAND_TRR(0x0e)    | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
 					FTIM2_NAND_TREH(0x0a)   | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3		0x0
 #define CONFIG_SYS_NAND_DDR_LAW		11
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 /*
  * I2C
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 #define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
 #define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
 #define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
 #define I2C_MUX_CH_DEFAULT	0x8
 #define I2C_MUX_CH_VOL_MONITOR	0xa
 #define CONFIG_VID_FLS_ENV		"t208xrdb_vdd_mv"
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_VID
 #endif
 #define CONFIG_VOL_MONITOR_IR36021_SET
 #define CONFIG_VOL_MONITOR_IR36021_READ
 /* The lowest and highest voltage allowed for T208xRDB */
 #define VDD_MV_MIN			819
 #define VDD_MV_MAX			1212
 /*
  * RapidIO
  */
 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
 /* slave core release by master*/
 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 /*
  * SRIO_PCIE_BOOT - SLAVE
  */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 /*
  * eSPI - Enhanced SPI
  */
 #ifdef CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED	 10000000
 #define CONFIG_SF_DEFAULT_MODE	  0
 #endif
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
 #define CONFIG_PCIE4		/* PCIE controller 4 */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	18
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	18
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 #define CONFIG_SYS_PMAN
 #define CONFIG_SYS_DPAA_DCE
 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
 #define CONFIG_SYS_INTERLAKEN
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR		0x110000
 #define CONFIG_CORTINA_FW_ADDR		0x120000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
 #define CONFIG_CORTINA_FW_ADDR		(512 * 0x8a0)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_CORTINA_FW_ADDR		(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
  * in two corenet boards, slave's ucode could be stored in master's memory
  * space, the address can be mapped from slave TLB->slave LAW->
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR		0xFFE00000
 #define CONFIG_CORTINA_FW_ADDR		0xFFE10000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #define CONFIG_CORTINA_FW_ADDR		0xEFE00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_AQUANTIA
 #define CONFIG_PHY_CORTINA
 #define CONFIG_PHY_REALTEK
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
 #define RGMII_PHY1_ADDR		0x01  /* RealTek RTL8211E */
 #define RGMII_PHY2_ADDR		0x02
 #define CORTINA_PHY_ADDR1	0x0c  /* Cortina CS4315 */
 #define CORTINA_PHY_ADDR2	0x0d
 #define FM1_10GEC3_PHY_ADDR	0x00  /* Aquantia AQ1202 10G Base-T */
 #define FM1_10GEC4_PHY_ADDR	0x01
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC3"
 #endif
 /*
  * SATA
  */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 /*
  * USB
  */
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_HAS_FSL_DR_USB
 #endif
 /*
  * SDHC
  */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 /*
  * Dynamic MTD Partition support with mtdparts
  */
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_FLASH_CFI_MTD
 #endif
 /*
  * Environment
  */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH	 "/opt/nfsroot"
 #define CONFIG_BOOTFILE	 "uImage"
 #define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define __USB_PHY_TYPE		utmi
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:"					\
 	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
 	"bank_intlv=auto;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t2080rdb/ramdisk.uboot\0"			\
 	"fdtaddr=1e00000\0"					\
 	"fdtfile=t2080rdb/t2080rdb.dtb\0"			\
 	"bdev=sda3\0"
 /*
  * For emulation this causes u-boot to jump to the start of the
  * proof point app code automatically
  */
 #define CONFIG_PROOF_POINTS				\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"cpu 1 release 0x29000000 - - -;"		\
 	"cpu 2 release 0x29000000 - - -;"		\
 	"cpu 3 release 0x29000000 - - -;"		\
 	"cpu 4 release 0x29000000 - - -;"		\
 	"cpu 5 release 0x29000000 - - -;"		\
 	"cpu 6 release 0x29000000 - - -;"		\
 	"cpu 7 release 0x29000000 - - -;"		\
 	"go 0x29000000"
 #define CONFIG_HVBOOT				\
 	"setenv bootargs config-addr=0x60000000; "	\
 	"bootm 0x01000000 - 0x00f00000"
 #define CONFIG_ALU				\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"cpu 1 release 0x01000000 - - -;"		\
 	"cpu 2 release 0x01000000 - - -;"		\
 	"cpu 3 release 0x01000000 - - -;"		\
 	"cpu 4 release 0x01000000 - - -;"		\
 	"cpu 5 release 0x01000000 - - -;"		\
 	"cpu 6 release 0x01000000 - - -;"		\
 	"cpu 7 release 0x01000000 - - -;"		\
 	"go 0x01000000"
 #define CONFIG_LINUX				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"setenv ramdiskaddr 0x02000000;"		\
 	"setenv fdtaddr 0x00c00000;"			\
 	"setenv loadaddr 0x1000000;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 #include <asm/fsl_secure_boot.h>
 #endif	/* __T2080RDB_H */

include/configs/T4240QDS.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /*
  * T4240 QDS board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE4
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
 #else
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x00201000
 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
 #define CONFIG_SPL_PAD_TO		0x40000
 #define CONFIG_SPL_MAX_SIZE		0x28000
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
 #ifdef	CONFIG_NAND
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
 #define CONFIG_SPL_NAND_BOOT
 #endif
 #ifdef	CONFIG_SDCARD
 #define	CONFIG_RESET_VECTOR_ADDRESS	0x200FFC
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST	0x00200000
 #define CONFIG_SYS_MMC_U_BOOT_START	0x00200000
 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #ifndef CONFIG_SPL_BUILD
 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
 #define CONFIG_SPL_MMC_BOOT
 #endif
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_SKIP_RELOCATE
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 #endif
 #endif /* CONFIG_RAMBOOT_PBL */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_DDR_ECC
 #include "t4qds.h"
 #ifndef CONFIG_MTD_NOR_FLASH
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SPI_BUS              0
 #define CONFIG_ENV_SPI_CS               0
 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 #define CONFIG_ENV_SPI_MODE             0
 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 0x800)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_ADDR		0xffe20000
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_ENV_IS_NOWHERE)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS3	0x53
 #define SPD_EEPROM_ADDRESS4	0x54
 #define SPD_EEPROM_ADDRESS5	0x55
 #define SPD_EEPROM_ADDRESS6	0x56
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
 #define QIXIS_BASE			0xffdf0000
 #define QIXIS_LBMAP_SWITCH		6
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
 #define QIXIS_RST_CTL_RESET		0x83
 #define QIXIS_RST_FORCE_MEM		0x1
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define QIXIS_BRDCFG5			0x55
 #define QIXIS_MUX_SDHC			2
 #define QIXIS_MUX_SDHC_WIDTH8		1
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
 #define CONFIG_SYS_CSOR3	0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
 				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3		0x0
 #define CONFIG_SYS_NAND_DDR_LAW		11
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 /* I2C */
 #define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
 #define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
 #define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
 #define I2C_MUX_CH_DEFAULT	0x8
 #define I2C_MUX_CH_VOL_MONITOR	0xa
 #define I2C_MUX_CH_VSC3316_FS	0xc
 #define I2C_MUX_CH_VSC3316_BS	0xd
 /* Voltage monitor on channel 2*/
 #define I2C_VOL_MONITOR_ADDR		0x40
 #define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
 #define I2C_VOL_MONITOR_BUS_V_OVF	0x1
 #define I2C_VOL_MONITOR_BUS_V_SHIFT	3
 /* VSC Crossbar switches */
 #define CONFIG_VSC_CROSSBAR
 #define VSC3316_FSM_TX_ADDR	0x70
 #define VSC3316_FSM_RX_ADDR	0x71
 /*
  * RapidIO
  */
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
 /* slave core release by master*/
 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 /*
  * SRIO_PCIE_BOOT - SLAVE
  */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	50
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	50
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 #define CONFIG_SYS_PMAN
 #define CONFIG_SYS_DPAA_DCE
 #define CONFIG_SYS_DPAA_RMAN
 #define CONFIG_SYS_INTERLAKEN
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
  * in two corenet boards, slave's ucode could be stored in master's memory
  * space, the address can be mapped from slave TLB->slave LAW->
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_TERANETICS
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 #define FM1_10GEC1_PHY_ADDR	0x0
 #define FM1_10GEC2_PHY_ADDR	0x1
 #define FM2_10GEC1_PHY_ADDR	0x2
 #define FM2_10GEC2_PHY_ADDR	0x3
 #endif
 /* SATA */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #endif
 /*
 * USB
 */
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_ESDHC_DETECT_QUIRK \
 	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
 	IS_SVR_REV(get_svr(), 1, 0))
 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
 	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 #endif
 #define __USB_PHY_TYPE	utmi
 /*
  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
  * interleaving. It can be cacheline, page, bank, superbank.
  * See doc/README.fsl-ddr for details.
  */
 #ifdef CONFIG_ARCH_T4240
 #define CTRL_INTLV_PREFERED 3way_4KB
 #else
 #define CTRL_INTLV_PREFERED cacheline
 #endif
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:"					\
 	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
 	"bank_intlv=auto;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t4240qds/ramdisk.uboot\0"			\
 	"fdtaddr=1e00000\0"					\
 	"fdtfile=t4240qds/t4240qds.dtb\0"				\
 	"bdev=sda3\0"
 #define CONFIG_HVBOOT				\
 	"setenv bootargs config-addr=0x60000000; "	\
 	"bootm 0x01000000 - 0x00f00000"
 #define CONFIG_ALU				\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"cpu 1 release 0x01000000 - - -;"		\
 	"cpu 2 release 0x01000000 - - -;"		\
 	"cpu 3 release 0x01000000 - - -;"		\
 	"cpu 4 release 0x01000000 - - -;"		\
 	"cpu 5 release 0x01000000 - - -;"		\
 	"cpu 6 release 0x01000000 - - -;"		\
 	"cpu 7 release 0x01000000 - - -;"		\
 	"go 0x01000000"
 #define CONFIG_LINUX				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"setenv ramdiskaddr 0x02000000;"		\
 	"setenv fdtaddr 0x00c00000;"			\
 	"setenv loadaddr 0x1000000;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 #include <asm/fsl_secure_boot.h>
 #endif	/* __CONFIG_H */

include/configs/T4240RDB.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /*
  * T4240 RDB board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE4
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
 #ifndef CONFIG_SDCARD
 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
 #else
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SYS_TEXT_BASE		0x00201000
 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
 #define CONFIG_SPL_PAD_TO		0x40000
 #define CONFIG_SPL_MAX_SIZE		0x28000
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
 #ifdef	CONFIG_SDCARD
 #define CONFIG_RESET_VECTOR_ADDRESS	0x200FFC
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST	0x00200000
 #define CONFIG_SYS_MMC_U_BOOT_START	0x00200000
 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
 #define CONFIG_SPL_MMC_BOOT
 #endif
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_SKIP_RELOCATE
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 #endif
 #endif /* CONFIG_RAMBOOT_PBL */
 #define CONFIG_DDR_ECC
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MP			/* support multiple processors */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_ENV_OVERWRITE
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BTB			/* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_ENABLE_36BIT_PHYS
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define CONFIG_SYS_L3_SIZE		(512 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 #endif
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 #define CONFIG_DDR_SPD
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /* SATA */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * Command line configuration.
  */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_HVBOOT					\
 	"setenv bootargs config-addr=0x60000000; "	\
 	"bootm 0x01000000 - 0x00f00000"
 #ifndef CONFIG_MTD_NOR_FLASH
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SPI_BUS              0
 #define CONFIG_ENV_SPI_CS               0
 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 #define CONFIG_ENV_SPI_MODE             0
 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 0x800)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_ENV_IS_NOWHERE)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #define CONFIG_SYS_CLK_FREQ	66666666
 #define CONFIG_DDR_CLK_FREQ	133333333
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS1	0x52
 #define SPD_EEPROM_ADDRESS2	0x54
 #define SPD_EEPROM_ADDRESS3	0x56
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
 				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
 				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
 				| CSOR_NAND_PB(128))	/*Page Per Block = 128*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
 #define CONFIG_SYS_NAND_FTIM3		0x0
 #define CONFIG_SYS_NAND_DDR_LAW		11
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
 /* CPLD on IFC */
 #define CONFIG_SYS_CPLD_BASE	0xffdf0000
 #define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
 #define CONFIG_SYS_CSOR3	0x0
 /* CPLD Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 /* I2C */
 #define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
 #define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
 #define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
 #define I2C_MUX_CH_DEFAULT	0x8
 #define I2C_MUX_CH_VOL_MONITOR	0xa
 #define I2C_MUX_CH_VSC3316_FS	0xc
 #define I2C_MUX_CH_VSC3316_BS	0xd
 /* Voltage monitor on channel 2*/
 #define I2C_VOL_MONITOR_ADDR		0x40
 #define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
 #define I2C_VOL_MONITOR_BUS_V_OVF	0x1
 #define I2C_VOL_MONITOR_BUS_V_SHIFT	3
 #define CONFIG_VID_FLS_ENV		"t4240rdb_vdd_mv"
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_VID
 #endif
 #define CONFIG_VOL_MONITOR_IR36021_SET
 #define CONFIG_VOL_MONITOR_IR36021_READ
 /* The lowest and highest voltage allowed for T4240RDB */
 #define VDD_MV_MIN			819
 #define VDD_MV_MAX			1212
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	50
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	50
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 #define CONFIG_SYS_PMAN
 #define CONFIG_SYS_DPAA_DCE
 #define CONFIG_SYS_DPAA_RMAN
 #define CONFIG_SYS_INTERLAKEN
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_CORTINA
 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 #define CONFIG_CORTINA_FW_ADDR		0xefe00000
 #define CONFIG_CORTINA_FW_LENGTH	0x40000
 #define CONFIG_PHY_TERANETICS
 #define SGMII_PHY_ADDR1 0x0
 #define SGMII_PHY_ADDR2 0x1
 #define SGMII_PHY_ADDR3 0x2
 #define SGMII_PHY_ADDR4 0x3
 #define SGMII_PHY_ADDR5 0x4
 #define SGMII_PHY_ADDR6 0x5
 #define SGMII_PHY_ADDR7 0x6
 #define SGMII_PHY_ADDR8 0x7
 #define FM1_10GEC1_PHY_ADDR	0x10
 #define FM1_10GEC2_PHY_ADDR	0x11
 #define FM2_10GEC1_PHY_ADDR	0x12
 #define FM2_10GEC2_PHY_ADDR	0x13
 #define CORTINA_PHY_ADDR1	FM1_10GEC1_PHY_ADDR
 #define CORTINA_PHY_ADDR2	FM1_10GEC2_PHY_ADDR
 #define CORTINA_PHY_ADDR3	FM2_10GEC1_PHY_ADDR
 #define CORTINA_PHY_ADDR4	FM2_10GEC2_PHY_ADDR
 #endif
 /* SATA */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #endif
 /*
 * USB
 */
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_HAS_FSL_DR_USB
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 #define __USB_PHY_TYPE	utmi
 /*
  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
  * interleaving. It can be cacheline, page, bank, superbank.
  * See doc/README.fsl-ddr for details.
  */
 #ifdef CONFIG_ARCH_T4240
 #define CTRL_INTLV_PREFERED 3way_4KB
 #else
 #define CTRL_INTLV_PREFERED cacheline
 #endif
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:"					\
 	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
 	"bank_intlv=auto;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t4240rdb/ramdisk.uboot\0"			\
 	"fdtaddr=1e00000\0"					\
 	"fdtfile=t4240rdb/t4240rdb.dtb\0"			\
 	"bdev=sda3\0"
 #define CONFIG_HVBOOT					\
 	"setenv bootargs config-addr=0x60000000; "	\
 	"bootm 0x01000000 - 0x00f00000"
 #define CONFIG_LINUX					\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"setenv ramdiskaddr 0x02000000;"		\
 	"setenv fdtaddr 0x00c00000;"			\
 	"setenv loadaddr 0x1000000;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 #include <asm/fsl_secure_boot.h>
 #endif	/* __CONFIG_H */

include/configs/controlcenterd.h

Diff comments View file @ 9920d15

 /*
  * (C) Copyright 2013
  * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  *
  * based on P1022DS.h
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #ifdef CONFIG_SDCARD
 #define CONFIG_RAMBOOT_SDCARD
 #endif
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH
 #endif
 /* High Level Configuration Options */
 #define CONFIG_CONTROLCENTERD
 #define CONFIG_MP			/* support multiple processors */
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
 #endif
 #define CONFIG_L2_CACHE
 #define CONFIG_BTB
 #define CONFIG_SYS_CLK_FREQ	66666600
 #define CONFIG_DDR_CLK_FREQ	66666600
 #define CONFIG_SYS_RAMBOOT
 #ifdef CONFIG_TRAILBLAZER
 #define CONFIG_SYS_TEXT_BASE		0xf8fc0000
 #define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 /*
  * Config the L2 Cache
  */
 #define CONFIG_SYS_INIT_L2_ADDR		0xf8fc0000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8fc0000ull
 #else
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #endif
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #else /* CONFIG_TRAILBLAZER */
 #define CONFIG_SYS_TEXT_BASE		0x11000000
 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #endif /* CONFIG_TRAILBLAZER */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 /*
  * Memory map
  *
  * 0x0000_0000	0x3fff_ffff	DDR			1G Cacheable
  * 0xc000_0000	0xdfff_ffff	PCI Express Mem		512M non-cacheable
  * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
  *
  * Localbus non-cacheable
  * 0xe000_0000	0xe00f_ffff	eLBC			1M non-cacheable
  * 0xf8fc0000	0xf8ff_ffff	L2 SRAM			256k Cacheable
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #ifdef CONFIG_TRAILBLAZER
 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
 #define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
 #else
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #endif
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR	(CONFIG_SYS_CCSRBAR+0xf200)
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_SDRAM_SIZE 1024
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_SYS_MEMTEST_START	0x00000000
 #define CONFIG_SYS_MEMTEST_END		0x3fffffff
 #ifdef CONFIG_TRAILBLAZER
 #define CONFIG_SPD_EEPROM
 #define SPD_EEPROM_ADDRESS 0x52
 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
 #endif
 /*
  * Local Bus Definitions
  */
 #define CONFIG_SYS_ELBC_BASE		0xe0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_ELBC_BASE_PHYS	0xfe0000000ull
 #else
 #define CONFIG_SYS_ELBC_BASE_PHYS	CONFIG_SYS_ELBC_BASE
 #endif
 #define CONFIG_UART_BR_PRELIM  \
 	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
 #define CONFIG_UART_OR_PRELIM	(OR_AM_32KB | 0xff7)
 #define CONFIG_SYS_BR0_PRELIM	0 /* CS0 was originally intended for FPGA */
 #define CONFIG_SYS_OR0_PRELIM	0 /* debugging, was never used */
 #define CONFIG_SYS_BR1_PRELIM	CONFIG_UART_BR_PRELIM
 #define CONFIG_SYS_OR1_PRELIM	CONFIG_UART_OR_PRELIM
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX		2
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 /*
  * I2C
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
 #ifndef CONFIG_TRAILBLAZER
 #endif
 #define CONFIG_PCA9698			/* NXP PCA9698 */
 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 #ifndef CONFIG_TRAILBLAZER
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_HARD_SPI
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		0
 #endif
 /*
  * MMC
  */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #ifndef CONFIG_TRAILBLAZER
 /*
  * Video
  */
 #define CONFIG_FSL_DIU_FB
 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /*
  * SATA
  */
 #define CONFIG_LIBATA
 #define CONFIG_LBA48
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 /*
  * Ethernet
  */
 #define CONFIG_TSEC_ENET
 #define CONFIG_TSECV2
 #define CONFIG_MII			/* MII PHY management */
 #define CONFIG_TSEC1		1
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define CONFIG_TSEC2		1
 #define CONFIG_TSEC2_NAME	"eTSEC2"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define CONFIG_ETHPRIME		"eTSEC1"
 /*
  * USB
  */
 #define CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif /* CONFIG_TRAILBLAZER */
 /*
  * Environment
  */
 #if defined(CONFIG_TRAILBLAZER)
 #define CONFIG_ENV_SIZE		0x2000		/* 8KB */
 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
 #define CONFIG_ENV_SPI_MAX_HZ	10000000
 #define CONFIG_ENV_SPI_MODE	0
 #define CONFIG_ENV_SIZE		0x2000		/* 8KB */
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #elif defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #endif
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 /*
  * Command line configuration.
  */
 #ifndef CONFIG_TRAILBLAZER
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #endif /* CONFIG_TRAILBLAZER */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #ifndef CONFIG_TRAILBLAZER
 /*
  * Board initialisation callbacks
  */
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 #else /* CONFIG_TRAILBLAZER */
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 #endif /* CONFIG_TRAILBLAZER */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Linux Memory map */
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 /*
  * Environment Configuration
  */
 #ifdef CONFIG_TRAILBLAZER
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"mp_holdoff=1\0"
 #else
 #define CONFIG_HOSTNAME		controlcenterd
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP */
 #define CONFIG_LOADADDR		1000000
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 		"protect off $ubootaddr +$filesize && "		\
 		"erase $ubootaddr +$filesize && "		\
 		"cp.b $loadaddr $ubootaddr $filesize && "	\
 		"protect on $ubootaddr +$filesize && "		\
 		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
 	"consoledev=ttyS1\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
 	"fdtaddr=1e00000\0"					\
 	"fdtfile=controlcenterd.dtb\0"				\
 	"bdev=sda3\0"
 /* these are used and NUL-terminated in env_default.h */
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv bootargs root=/dev/nfs rw "				\
 	"nfsroot=$serverip:$rootpath "					\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"setenv bootargs root=/dev/ram rw "				\
 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
 #endif /* CONFIG_TRAILBLAZER */
 #endif

include/configs/corenet_ds.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2009-2012 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /*
  * Corenet DS style board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include "../board/freescale/common/ics307_clk.h"
 #ifdef CONFIG_RAMBOOT_PBL
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #ifdef CONFIG_NAND
 #define CONFIG_RAMBOOT_NAND
 #endif
 #define CONFIG_BOOTSCRIPT_COPY_RAM
 #else
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
 #if defined(CONFIG_TARGET_P3041DS)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
 #elif defined(CONFIG_TARGET_P4080DS)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
 #elif defined(CONFIG_TARGET_P5020DS)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
 #elif defined(CONFIG_TARGET_P5040DS)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
 #endif
 #endif
 #endif
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MP			/* support multiple processors */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_ENV_OVERWRITE
 #ifndef CONFIG_MTD_NOR_FLASH
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SPI_BUS              0
 #define CONFIG_ENV_SPI_CS               0
 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 #define CONFIG_ENV_SPI_MODE             0
 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 1658)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_ADDR		0xffe20000
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_ENV_IS_NOWHERE)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #define CONFIG_BTB			/* toggle branch predition */
 #define	CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #endif
 #define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 #else
 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
 #endif
 #define CONFIG_SYS_L3_SIZE		(1024 << 10)
 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 #endif
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM	1
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 /*
  * Local Bus Definitions
  */
 /* Set the local bus clock 1/8 of platform clock */
 #define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* Start of PromJet */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
 #else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 #define CONFIG_SYS_FLASH_BR_PRELIM \
 		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 		 | BR_PS_16 | BR_V)
 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 					| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 #define CONFIG_SYS_BR1_PRELIM \
 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 #define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS		0xfffdf0000ull
 #else
 #define PIXIS_BASE_PHYS		PIXIS_BASE
 #endif
 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
 #define PIXIS_LBMAP_SWITCH	7
 #define PIXIS_LBMAP_MASK	0xf0
 #define PIXIS_LBMAP_SHIFT	4
 #define PIXIS_LBMAP_ALTBANK	0x40
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS 	45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
 #define CONFIG_SYS_NAND_BASE		0xffa00000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 /* NAND flash config */
 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
 			       | OR_FCM_PGS	       /* Large Page*/ \
 			       | OR_FCM_CSCT \
 			       | OR_FCM_CST \
 			       | OR_FCM_CHT \
 			       | OR_FCM_SCY_1 \
 			       | OR_FCM_TRLX \
 			       | OR_FCM_EHTR)
 #ifdef CONFIG_NAND
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #else
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #endif
 #else
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #endif /* CONFIG_NAND_FSL_ELBC */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
 /*
  * RapidIO
  */
 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #else
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
 #endif
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
 /* slave core release by master*/
 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 /*
  * SRIO_PCIE_BOOT - SLAVE
  */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 /*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
 #else
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
 #endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #else
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 /* Qman/Bman */
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #else
 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
 #else
 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
  * in two corenet boards, slave's ucode could be stored in master's memory
  * space, the address can be mapped from slave TLB->slave LAW->
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_TERANETICS
 #endif
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /* SATA */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1c
 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x1d
 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x1e
 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1f
 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4
 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR	0x1c
 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR	0x1d
 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR	0x1e
 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR	0x1f
 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR	0
 #define CONFIG_SYS_TBIPA_VALUE	8
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
 * USB
 */
 #define CONFIG_HAS_FSL_DR_USB
 #define CONFIG_HAS_FSL_MPH_USB
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #ifdef CONFIG_TARGET_P4080DS
 #define __USB_PHY_TYPE	ulpi
 #else
 #define __USB_PHY_TYPE	utmi
 #endif
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
 	"bank_intlv=cs0_cs1;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 	"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
 	"protect off $ubootaddr +$filesize && "			\
 	"erase $ubootaddr +$filesize && "			\
 	"cp.b $loadaddr $ubootaddr $filesize && "		\
 	"protect on $ubootaddr +$filesize && "			\
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=p4080ds/ramdisk.uboot\0"			\
 	"fdtaddr=1e00000\0"					\
 	"fdtfile=p4080ds/p4080ds.dtb\0"				\
 	"bdev=sda3\0"
 #define CONFIG_HDBOOT					\
 	"setenv bootargs root=/dev/$bdev rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $loadaddr $bootfile;"		\
 	"tftp $fdtaddr $fdtfile;"		\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftp $ramdiskaddr $ramdiskfile;"		\
 	"tftp $loadaddr $bootfile;"			\
 	"tftp $fdtaddr $fdtfile;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 #include <asm/fsl_secure_boot.h>
 #endif	/* __CONFIG_H */

include/configs/cyrus.h

Diff comments View file @ 9920d15

 /*
  * Based on corenet_ds.h
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define CONFIG_CYRUS
 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
 #error Must call Cyrus CONFIG with a specific CPU enabled.
 #endif
 #define CONFIG_SDCARD
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE3
 #define CONFIG_PCIE4
 #ifdef CONFIG_ARCH_P5020
 #define CONFIG_SYS_FSL_RAID_ENGINE
 #define CONFIG_SYS_DPAA_RMAN
 #endif
 #define CONFIG_SYS_DPAA_PME
 /*
  * Corenet DS style board configuration file
  */
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
 #if defined(CONFIG_ARCH_P5020)
 #define CONFIG_SYS_CLK_FREQ 133000000
 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
 #elif defined(CONFIG_ARCH_P5040)
 #define CONFIG_SYS_CLK_FREQ 100000000
 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
 #endif
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MP			/* support multiple processors */
 #define CONFIG_SYS_MMC_MAX_DEVICE     1
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_ENV_OVERWRITE
 #if defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 1658)
 #endif
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #define CONFIG_BTB			/* toggle branch predition */
 #define	CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_ENABLE_36BIT_PHYS
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #endif
 /* test POST memory test */
 #undef CONFIG_POST
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 #else
 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
 #endif
 #define CONFIG_SYS_L3_SIZE		(1024 << 10)
 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 #endif
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM	1
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 /*
  * Local Bus Definitions
  */
 #define CONFIG_SYS_LBC0_BASE		0xe0000000 /* Start of LBC Registers */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_LBC0_BASE_PHYS	0xfe0000000ull
 #else
 #define CONFIG_SYS_LBC0_BASE_PHYS	CONFIG_SYS_LBC0_BASE
 #endif
 #define CONFIG_SYS_LBC1_BASE		0xe1000000 /* Start of LBC Registers */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_LBC1_BASE_PHYS	0xfe1000000ull
 #else
 #define CONFIG_SYS_LBC1_BASE_PHYS	CONFIG_SYS_LBC1_BASE
 #endif
 /* Set the local bus clock 1/16 of platform clock */
 #define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_16 | LCRR_EADC_1)
 #define CONFIG_SYS_BR0_PRELIM \
 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_BR1_PRELIM \
 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR0_PRELIM	0xfff00010
 #define CONFIG_SYS_OR1_PRELIM	0xfff00010
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_FSL_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_FSL_I2C_SLAVE		0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET		0x118000
 #define CONFIG_SYS_FSL_I2C2_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_FSL_I2C2_SLAVE		0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET		0x118100
 #define CONFIG_SYS_FSL_I2C3_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_FSL_I2C3_SLAVE		0x7F
 #define CONFIG_SYS_FSL_I2C3_OFFSET		0x119000
 #define CONFIG_SYS_FSL_I2C4_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_FSL_I2C4_SLAVE		0x7F
 #define CONFIG_SYS_FSL_I2C4_OFFSET		0x119100
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_GENERIC_MAC
 #define CONFIG_SYS_I2C_MAC1_BUS 3
 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
 #define CONFIG_SYS_I2C_MAC2_BUS 0
 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
 #define CONFIG_RTC_MCP79411		1
 #define CONFIG_SYS_RTC_BUS_NUM		3
 #define CONFIG_SYS_I2C_RTC_ADDR		0x6f
 /*
  * eSPI - Enhanced SPI
  */
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
 #else
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
 #endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #else
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 /* Qman/Bman */
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #else
 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 					 CONFIG_SYS_BMAN_CENA_SIZE)
 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
 #define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
 #else
 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 					  CONFIG_SYS_QMAN_CENA_SIZE)
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
 #define CONFIG_SYS_DPAA_FMAN
 /* Default address of microcode for the Linux Fman driver */
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #endif
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /* SATA */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_TBIPA_VALUE	8
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC4"
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * USB
  */
 #define CONFIG_HAS_FSL_DR_USB
 #define CONFIG_HAS_FSL_MPH_USB
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_EHCI_IS_TDI
  /* _VIA_CONTROL_EP  */
 #endif
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define __USB_PHY_TYPE	utmi
 #define	CONFIG_EXTRA_ENV_SETTINGS \
 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
 "bank_intlv=cs0_cs1;"					\
 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 "netdev=eth0\0"						\
 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
 "consoledev=ttyS0\0"					\
 "ramdiskaddr=2000000\0"					\
 "fdtaddr=1e00000\0"					\
 "bdev=sda3\0"
 #define CONFIG_HDBOOT					\
 "setenv bootargs root=/dev/$bdev rw "		\
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $loadaddr $bootfile;"			\
 "tftp $fdtaddr $fdtfile;"			\
 "bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND			\
 "setenv bootargs root=/dev/nfs rw "	\
 "nfsroot=$serverip:$rootpath "		\
 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND				\
 "setenv bootargs root=/dev/ram rw "		\
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $ramdiskaddr $ramdiskfile;"		\
 "tftp $loadaddr $bootfile;"			\
 "tftp $fdtaddr $fdtfile;"			\
 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 #include <asm/fsl_secure_boot.h>
 #ifdef CONFIG_SECURE_BOOT
 #endif
 #endif	/* __CONFIG_H */

include/configs/t4qds.h

Diff comments View file @ 9920d15

 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /*
  * Corenet DS style board configuration file
  */
 #ifndef __T4QDS_H
 #define __T4QDS_H
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MP			/* support multiple processors */
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
 #define CONFIG_ENV_OVERWRITE
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BTB			/* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 #define CONFIG_ENABLE_36BIT_PHYS
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define CONFIG_SYS_L3_SIZE		(512 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 #endif
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 #define CONFIG_DDR_SPD
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
 /*
  * RapidIO
  */
 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /* SATA */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #define CONFIG_LBA48
 #endif
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #endif
 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * Command line configuration.
  */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_HVBOOT				\
  "setenv bootargs config-addr=0x60000000; "	\
  "bootm 0x01000000 - 0x00f00000"
 #endif	/* __CONFIG_H */

scripts/config_whitelist.txt

Diff comments View file @ 9920d15

 CONFIG_16BIT
 CONFIG_33
 CONFIG_400MHZ_MODE
 CONFIG_64BIT_PHYS_ADDR
 CONFIG_66
 CONFIG_8349_CLKIN
 CONFIG_83XX
 CONFIG_83XX_CLKIN
 CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
 CONFIG_83XX_PCICLK
 CONFIG_83XX_PCI_STREAMING
 CONFIG_88F5182
 CONFIG_A003399_NOR_WORKAROUND
 CONFIG_A008044_WORKAROUND
 CONFIG_ACX517AKN
 CONFIG_ACX544AKN
 CONFIG_ADDRESS
 CONFIG_ADDR_AUTO_INCR_BIT
 CONFIG_ADDR_MAP
 CONFIG_ADNPESC1
 CONFIG_ADP_AG101P
 CONFIG_AEABI
 CONFIG_AEMIF_CNTRL_BASE
 CONFIG_ALTERA_SPI_IDLE_VAL
 CONFIG_ALTIVEC
 CONFIG_ALT_LB_ADDR
 CONFIG_ALU
 CONFIG_AM335X_LCD
 CONFIG_AM335X_USB0
 CONFIG_AM335X_USB0_MODE
 CONFIG_AM335X_USB1
 CONFIG_AM335X_USB1_MODE
 CONFIG_AM437X_USB2PHY2_HOST
 CONFIG_AMCORE
 CONFIG_ANDES_PCU
 CONFIG_ANDES_PCU_BASE
 CONFIG_AP325RXA
 CONFIG_APBH_DMA
 CONFIG_APBH_DMA_BURST
 CONFIG_APBH_DMA_BURST8
 CONFIG_APER_0_BASE
 CONFIG_APER_1_BASE
 CONFIG_APER_SIZE
 CONFIG_APUS_FAST_EXCEPT
 CONFIG_AP_SH4A_4A
 CONFIG_ARCH_ADPAG101P
 CONFIG_ARCH_CPU_INIT
 CONFIG_ARCH_CSB226
 CONFIG_ARCH_HAS_ILOG2_U32
 CONFIG_ARCH_HAS_ILOG2_U64
 CONFIG_ARCH_INNOKOM
 CONFIG_ARCH_KIRKWOOD
 CONFIG_ARCH_LUBBOCK
 CONFIG_ARCH_MAP_SYSMEM
 CONFIG_ARCH_OMAP4
 CONFIG_ARCH_ORION5X
 CONFIG_ARCH_PLEB
 CONFIG_ARCH_PXA_CERF
 CONFIG_ARCH_PXA_IDP
 CONFIG_ARCH_RMOBILE_BOARD_STRING
 CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
 CONFIG_ARCH_TEGRA
 CONFIG_ARCH_USE_BUILTIN_BSWAP
 CONFIG_ARC_MMU_VER
 CONFIG_ARC_SERIAL
 CONFIG_ARIES_M28_V10
 CONFIG_ARM926EJS
 CONFIG_ARMADA100
 CONFIG_ARMADA100_FEC
 CONFIG_ARMADA168
 CONFIG_ARMADA_39X
 CONFIG_ARMV7_PSCI_1_0
 CONFIG_ARMV7_SECURE_BASE
 CONFIG_ARMV7_SECURE_MAX_SIZE
 CONFIG_ARMV7_SECURE_RESERVE_SIZE
 CONFIG_ARMV8_SWITCH_TO_EL1
 CONFIG_ARM_ARCH_CP15_ERRATA
 CONFIG_ARM_DCC
 CONFIG_ARM_FREQ
 CONFIG_ARM_GIC_BASE_ADDRESS
 CONFIG_ARM_PL180_MMCI
 CONFIG_ARM_PL180_MMCI_BASE
 CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
 CONFIG_ARM_THUMB
 CONFIG_ARP_TIMEOUT
 CONFIG_ASTRO5373L
 CONFIG_ASTRO_COFDMDUOS2
 CONFIG_ASTRO_TWIN7S2
 CONFIG_ASTRO_V512
 CONFIG_ASTRO_V532
 CONFIG_ASTRO_V912
 CONFIG_AT91C_PQFP_UHPBUG
 CONFIG_AT91RESET_EXTRST
 CONFIG_AT91RM9200
 CONFIG_AT91RM9200EK
 CONFIG_AT91SAM9260EK
 CONFIG_AT91SAM9261EK
 CONFIG_AT91SAM9263EK
 CONFIG_AT91SAM9G10
 CONFIG_AT91SAM9G10EK
 CONFIG_AT91SAM9G20EK
 CONFIG_AT91SAM9G20EK_2MMC
 CONFIG_AT91SAM9G45EKES
 CONFIG_AT91SAM9G45_LCD_BASE
 CONFIG_AT91SAM9M10G45EK
 CONFIG_AT91SAM9RLEK
 CONFIG_AT91SAM9_WATCHDOG
 CONFIG_AT91_CAN
 CONFIG_AT91_EFLASH
 CONFIG_AT91_GPIO_PULLUP
 CONFIG_AT91_HW_WDT_TIMEOUT
 CONFIG_AT91_LED
 CONFIG_AT91_WANTS_COMMON_PHY
 CONFIG_ATAPI
 CONFIG_ATA_ACPI
 CONFIG_ATI
 CONFIG_ATI_RADEON_FB
 CONFIG_ATM
 CONFIG_ATMEL_LCD
 CONFIG_ATMEL_LCD_BGR555
 CONFIG_ATMEL_LCD_RGB565
 CONFIG_ATMEL_LEGACY
 CONFIG_ATMEL_MCI_8BIT
 CONFIG_ATMEL_NAND_HWECC
 CONFIG_ATMEL_NAND_HW_PMECC
 CONFIG_ATMEL_SPI0
 CONFIG_AT_TRANS
 CONFIG_AUTO_COMPLETE
 CONFIG_AUTO_ZRELADDR
 CONFIG_BACKSIDE_L2_CACHE
 CONFIG_BARIX_IPAM390
 CONFIG_BAT_PAIR
 CONFIG_BAT_RW
 CONFIG_BCH_CONST_M
 CONFIG_BCH_CONST_PARAMS
 CONFIG_BCH_CONST_T
 CONFIG_BCM2835_GPIO
 CONFIG_BCM283X_MU_SERIAL
 CONFIG_BIOSEMU
 CONFIG_BITBANGMII_MULTI
 CONFIG_BL1_OFFSET
 CONFIG_BL1_SIZE
 CONFIG_BL2_OFFSET
 CONFIG_BL2_SIZE
 CONFIG_BMP_16BPP
 CONFIG_BMP_24BPP
 CONFIG_BMP_32BPP
 CONFIG_BOARDDIR
 CONFIG_BOARDNAME
 CONFIG_BOARDNAME_LOCAL
 CONFIG_BOARD_AXM
 CONFIG_BOARD_COMMON
 CONFIG_BOARD_EARLY_INIT_R
 CONFIG_BOARD_ECC_SUPPORT
 CONFIG_BOARD_H2200
 CONFIG_BOARD_IS_OPENRD_BASE
 CONFIG_BOARD_IS_OPENRD_CLIENT
 CONFIG_BOARD_IS_OPENRD_ULTIMATE
 CONFIG_BOARD_NAME
 CONFIG_BOARD_POSTCLK_INIT
 CONFIG_BOARD_REVISION_TAG
 CONFIG_BOARD_SIZE_LIMIT
 CONFIG_BOARD_TAURUS
 CONFIG_BOARD_TYPES
 CONFIG_BOOGER
 CONFIG_BOOM
 CONFIG_BOOTBLOCK
 CONFIG_BOOTCOMMAND
 CONFIG_BOOTCOUNT_ALEN
 CONFIG_BOOTCOUNT_AM33XX
 CONFIG_BOOTCOUNT_ENV
 CONFIG_BOOTCOUNT_I2C
 CONFIG_BOOTCOUNT_LIMIT
 CONFIG_BOOTCOUNT_RAM
 CONFIG_BOOTFILE
 CONFIG_BOOTMAPSZ
 CONFIG_BOOTMODE
 CONFIG_BOOTM_LINUX
 CONFIG_BOOTM_NETBSD
 CONFIG_BOOTM_OPENRTOS
 CONFIG_BOOTM_OSE
 CONFIG_BOOTM_PLAN9
 CONFIG_BOOTM_RTEMS
 CONFIG_BOOTM_VXWORKS
 CONFIG_BOOTP_
 CONFIG_BOOTP_BOOTFILE
 CONFIG_BOOTP_BOOTFILESIZE
 CONFIG_BOOTP_BOOTPATH
 CONFIG_BOOTP_DEFAULT
 CONFIG_BOOTP_DHCP_REQUEST_DELAY
 CONFIG_BOOTP_DNS
 CONFIG_BOOTP_DNS2
 CONFIG_BOOTP_GATEWAY
 CONFIG_BOOTP_HOSTNAME
 CONFIG_BOOTP_ID_CACHE_SIZE
 CONFIG_BOOTP_MAY_FAIL
 CONFIG_BOOTP_NISDOMAIN
 CONFIG_BOOTP_NTPSERVER
 CONFIG_BOOTP_PXE
 CONFIG_BOOTP_RANDOM_DELAY
 CONFIG_BOOTP_SEND_HOSTNAME
 CONFIG_BOOTP_SERVERIP
 CONFIG_BOOTP_SUBNETMASK
 CONFIG_BOOTP_TIMEOFFSET
 CONFIG_BOOTP_VENDOREX
 CONFIG_BOOTROM_ERR_REG
 CONFIG_BOOTSCRIPT_ADDR
 CONFIG_BOOTSCRIPT_COPY_RAM
 CONFIG_BOOTSCRIPT_HDR_ADDR
 CONFIG_BOOTSCRIPT_KEY_HASH
 CONFIG_BOOT_DIR
 CONFIG_BOOT_MODE_BIT
 CONFIG_BOOT_OS_NET
 CONFIG_BOOT_PARAMS_ADDR
 CONFIG_BOOT_RETRY_MIN
 CONFIG_BOOT_RETRY_TIME
 CONFIG_BOUNCE_BUFFER
 CONFIG_BPTR_VIRT_ADDR
 CONFIG_BS_ADDR_DEVICE
 CONFIG_BS_ADDR_RAM
 CONFIG_BS_COPY_CMD
 CONFIG_BS_COPY_ENV
 CONFIG_BS_HDR_ADDR_DEVICE
 CONFIG_BS_HDR_ADDR_RAM
 CONFIG_BS_HDR_SIZE
 CONFIG_BS_SIZE
 CONFIG_BTB
 CONFIG_BUFNO_AUTO_INCR_BIT
 CONFIG_BUILD_ENVCRC
 CONFIG_BUILD_TARGET
 CONFIG_BUS_WIDTH
 CONFIG_BZIP2
 CONFIG_CADDY2
 CONFIG_CALXEDA_XGMAC
 CONFIG_CDP_APPLIANCE_VLAN_TYPE
 CONFIG_CDP_CAPABILITIES
 CONFIG_CDP_DEVICE_ID
 CONFIG_CDP_DEVICE_ID_PREFIX
 CONFIG_CDP_PLATFORM
 CONFIG_CDP_PORT_ID
 CONFIG_CDP_POWER_CONSUMPTION
 CONFIG_CDP_TRIGGER
 CONFIG_CDP_VERSION
 CONFIG_CFG_DATA_SECTOR
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 CONFIG_CF_DSPI
 CONFIG_CF_SBF
 CONFIG_CF_SPI
 CONFIG_CF_V2
 CONFIG_CF_V3
 CONFIG_CF_V4
 CONFIG_CF_V4E
 CONFIG_CHAIN_BOOT_CMD
 CONFIG_CHIP_SELECTS_PER_CTRL
 CONFIG_CHIP_SELECT_QUAD_CAPABLE
 CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
 CONFIG_CI_UDC_HAS_HOSTPC
 CONFIG_CLK0_DIV
 CONFIG_CLK0_EN
 CONFIG_CLK_1000_200_200
 CONFIG_CLK_1000_330_165
 CONFIG_CLK_1000_400_200
 CONFIG_CLK_800_330_165
 CONFIG_CLK_DEBUG
 CONFIG_CLOCKS
 CONFIG_CLOCKS_IN_MHZ
 CONFIG_CLOCK_SYNTHESIZER
 CONFIG_CM922T_XA10
 CONFIG_CMDLINE_EDITING
 CONFIG_CMDLINE_PS_SUPPORT
 CONFIG_CMDLINE_TAG
 CONFIG_CM_INIT
 CONFIG_CM_MULTIPLE_SSRAM
 CONFIG_CM_REMAP
 CONFIG_CM_SPD_DETECT
 CONFIG_CM_T335
 CONFIG_CM_T3517
 CONFIG_CM_T3X
 CONFIG_CM_T43
 CONFIG_CM_T54
 CONFIG_CM_TCRAM
 CONFIG_CNTL
 CONFIG_COLDFIRE
 CONFIG_COMMANDS
 CONFIG_COMMON_BOOT
 CONFIG_COMMON_ENV_MISC
 CONFIG_COMMON_ENV_SETTINGS
 CONFIG_COMMON_ENV_UBI
 CONFIG_COMPACT_FLASH
 CONFIG_COMPAT
 CONFIG_CONS_EXTC_PINSEL
 CONFIG_CONS_EXTC_RATE
 CONFIG_CONS_NONE
 CONFIG_CONS_ON_SCC
 CONFIG_CONS_SCIF0
 CONFIG_CONS_SCIF1
 CONFIG_CONS_SCIF2
 CONFIG_CONS_SCIF3
 CONFIG_CONS_SCIF4
 CONFIG_CONS_SCIF5
 CONFIG_CONS_SCIF7
 CONFIG_CONTROL
 CONFIG_CONTROLCENTERD
 CONFIG_CON_ROT
 CONFIG_CORTINA_FW_ADDR
 CONFIG_CORTINA_FW_LENGTH
 CONFIG_CPLD_BR_PRELIM
 CONFIG_CPLD_OR_PRELIM
 CONFIG_CPM2
 CONFIG_CPUAT91
 CONFIG_CPU_ARCHS34
 CONFIG_CPU_ARMV8
 CONFIG_CPU_CAVIUM_OCTEON
 CONFIG_CPU_FREQ_HZ
 CONFIG_CPU_HAS_LLSC
 CONFIG_CPU_HAS_PREFETCH
 CONFIG_CPU_HAS_SMARTMIPS
 CONFIG_CPU_HAS_SR_RB
 CONFIG_CPU_HAS_WB
 CONFIG_CPU_LITTLE_ENDIAN
 CONFIG_CPU_MICROMIPS
 CONFIG_CPU_MIPSR2
 CONFIG_CPU_MONAHANS
 CONFIG_CPU_PXA25X
 CONFIG_CPU_PXA26X
 CONFIG_CPU_PXA27X
 CONFIG_CPU_PXA300
 CONFIG_CPU_R8000
 CONFIG_CPU_SH7203
 CONFIG_CPU_SH7264
 CONFIG_CPU_SH7269
 CONFIG_CPU_SH7706
 CONFIG_CPU_SH7720
 CONFIG_CPU_SH7722
 CONFIG_CPU_SH7723
 CONFIG_CPU_SH7724
 CONFIG_CPU_SH7734
 CONFIG_CPU_SH7750
 CONFIG_CPU_SH7751
 CONFIG_CPU_SH7752
 CONFIG_CPU_SH7753
 CONFIG_CPU_SH7757
 CONFIG_CPU_SH7763
 CONFIG_CPU_SH7780
 CONFIG_CPU_SH7785
 CONFIG_CPU_SH_TYPE_R
 CONFIG_CPU_TYPE_R
 CONFIG_CPU_VR41XX
 CONFIG_CQSPI_DECODER
 CONFIG_CQSPI_REF_CLK
 CONFIG_CRC32
 CONFIG_CS8900
 CONFIG_CS8900_BASE
 CONFIG_CS8900_BUS16
 CONFIG_CS8900_BUS32
 CONFIG_CSF_SIZE
 CONFIG_CTL_JTAG
 CONFIG_CTL_TBE
 CONFIG_CUSTOMER_BOARD_SUPPORT
 CONFIG_CYRUS
 CONFIG_D2NET_V2
 CONFIG_DA850_AM18X_EVM
 CONFIG_DA850_EVM_MAX_CPU_CLK
 CONFIG_DA850_LOWLEVEL
 CONFIG_DA8XX_GPIO
 CONFIG_DAVINCI_SPI
 CONFIG_DBAU1000
 CONFIG_DBAU1X00
 CONFIG_DBGU
 CONFIG_DBG_MONITOR
 CONFIG_DB_784MP_GP
 CONFIG_DCACHE
 CONFIG_DCACHE_OFF
 CONFIG_DCFG_ADDR
 CONFIG_DDR_
 CONFIG_DDR_2HCLK
 CONFIG_DDR_2T_TIMING
 CONFIG_DDR_32BIT
 CONFIG_DDR_64BIT
 CONFIG_DDR_CLK_FREQ
 CONFIG_DDR_DEFAULT_CL
 CONFIG_DDR_ECC
 CONFIG_DDR_ECC_CMD
 CONFIG_DDR_ECC_ENABLE
 CONFIG_DDR_ECC_INIT_VIA_DMA
 CONFIG_DDR_FIXED_SIZE
 CONFIG_DDR_HCLK
 CONFIG_DDR_II
 CONFIG_DDR_LOG_LEVEL
 CONFIG_DDR_MB
 CONFIG_DDR_MT47H128M8
 CONFIG_DDR_MT47H32M16
 CONFIG_DDR_MT47H64M16
 CONFIG_DDR_PLL2
 CONFIG_DDR_SPD
 CONFIG_DEBUG
 CONFIG_DEBUG_FS
 CONFIG_DEBUG_LED
 CONFIG_DEBUG_LOCK_ALLOC
 CONFIG_DEBUG_SECTION_MISMATCH
 CONFIG_DEBUG_SEMIHOSTING
 CONFIG_DEBUG_UART_LINFLEXUART
 CONFIG_DEBUG_WRITECOUNT
 CONFIG_DEEP_SLEEP
 CONFIG_DEFAULT
 CONFIG_DEFAULT_CONSOLE
 CONFIG_DEFAULT_IMMR
 CONFIG_DEFAULT_SPI_BUS
 CONFIG_DEFAULT_SPI_MODE
 CONFIG_DEF_HWCONFIG
 CONFIG_DELAY_ENVIRONMENT
 CONFIG_DESIGNWARE_ETH
 CONFIG_DESIGNWARE_WATCHDOG
 CONFIG_DEVELOP
 CONFIG_DEVICE_TREE_LIST
 CONFIG_DEV_USB_PHY_BASE
 CONFIG_DFU_ALT
 CONFIG_DFU_ALT_BOOT_EMMC
 CONFIG_DFU_ALT_BOOT_SD
 CONFIG_DFU_ALT_SYSTEM
 CONFIG_DFU_ENV_SETTINGS
 CONFIG_DHCP_MIN_EXT_LEN
 CONFIG_DIALOG_POWER
 CONFIG_DIMM_SLOTS_PER_CTLR
 CONFIG_DIRECT_NOR_BOOT
 CONFIG_DISABLE_CONSOLE
 CONFIG_DISABLE_IMAGE_LEGACY
 CONFIG_DISCONTIGMEM
 CONFIG_DISCOVER_PHY
 CONFIG_DISPLAY_AER_xxxx
 CONFIG_DISPLAY_BOARDINFO_LATE
 CONFIG_DLVISION_10G
 CONFIG_DM9000_BASE
 CONFIG_DM9000_BYTE_SWAPPED
 CONFIG_DM9000_DEBUG
 CONFIG_DM9000_NO_SROM
 CONFIG_DM9000_USE_16BIT
 CONFIG_DMA_COHERENT
 CONFIG_DMA_COHERENT_SIZE
 CONFIG_DMA_LPC32XX
 CONFIG_DMA_NONCOHERENT
 CONFIG_DMA_REQ_BIT
 CONFIG_DNET_AUTONEG_TIMEOUT
 CONFIG_DP_DDR_CTRL
 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
 CONFIG_DP_DDR_NUM_CTRLS
 CONFIG_DRAM_2G
 CONFIG_DRAM_TIMINGS_
 CONFIG_DRIVER_AT91EMAC
 CONFIG_DRIVER_AT91EMAC_PHYADDR
 CONFIG_DRIVER_AT91EMAC_QUIET
 CONFIG_DRIVER_AX88796L
 CONFIG_DRIVER_DM9000
 CONFIG_DRIVER_EP93XX_MAC
 CONFIG_DRIVER_ETHER
 CONFIG_DRIVER_NE2000
 CONFIG_DRIVER_NE2000_BASE
 CONFIG_DRIVER_NE2000_CCR
 CONFIG_DRIVER_NE2000_VAL
 CONFIG_DRIVER_SMC911X_BASE
 CONFIG_DRIVER_TI_CPSW
 CONFIG_DRIVER_TI_EMAC
 CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
 CONFIG_DRIVER_TI_EMAC_USE_RMII
 CONFIG_DRIVER_TI_KEYSTONE_NET
 CONFIG_DRIVE_MMC
 CONFIG_DRIVE_SATA
 CONFIG_DRIVE_TYPES
 CONFIG_DRIVE_USB
 CONFIG_DSP_CLUSTER_START
 CONFIG_DUOVERO
 CONFIG_DV_USBPHY_CTL
 CONFIG_DWC2_DFLT_SPEED_FULL
 CONFIG_DWC2_DMA_BURST_SIZE
 CONFIG_DWC2_DMA_ENABLE
 CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE
 CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE
 CONFIG_DWC2_HOST_RX_FIFO_SIZE
 CONFIG_DWC2_I2C_ENABLE
 CONFIG_DWC2_IC_USB_CAP
 CONFIG_DWC2_MAX_CHANNELS
 CONFIG_DWC2_MAX_PACKET_COUNT
 CONFIG_DWC2_MAX_TRANSFER_SIZE
 CONFIG_DWC2_PHY_TYPE
 CONFIG_DWC2_PHY_ULPI_DDR
 CONFIG_DWC2_PHY_ULPI_EXT_VBUS
 CONFIG_DWC2_THR_CTL
 CONFIG_DWC2_TS_DLINE
 CONFIG_DWC2_TX_THR_LENGTH
 CONFIG_DWC2_ULPI_FS_LS
 CONFIG_DWC2_UTMI_WIDTH
 CONFIG_DWCDDR21MCTL
 CONFIG_DWCDDR21MCTL_BASE
 CONFIG_DWC_AHSATA
 CONFIG_DWC_AHSATA_BASE_ADDR
 CONFIG_DWC_AHSATA_PORT_ID
 CONFIG_DW_ALTDESCRIPTOR
 CONFIG_DW_AXI_BURST_LEN
 CONFIG_DW_GMAC_DEFAULT_DMA_PBL
 CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
 CONFIG_DW_SERIAL
 CONFIG_DW_UDC
 CONFIG_DW_WDT_BASE
 CONFIG_DW_WDT_CLOCK_KHZ
 CONFIG_DYNAMIC_MMC_DEVNO
 CONFIG_E1000_NO_NVM
 CONFIG_E300
 CONFIG_E5500
 CONFIG_ECC
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 CONFIG_ECC_MODE_MASK
 CONFIG_ECC_MODE_SHIFT
 CONFIG_ECC_SRAM_ADDR_MASK
 CONFIG_ECC_SRAM_ADDR_SHIFT
 CONFIG_ECC_SRAM_REQ_BIT
 CONFIG_ECOVEC
 CONFIG_ECOVEC_ROMIMAGE_ADDR
 CONFIG_EDB9301
 CONFIG_EDB9302
 CONFIG_EDB9302A
 CONFIG_EDB9307
 CONFIG_EDB9307A
 CONFIG_EDB9312
 CONFIG_EDB9315
 CONFIG_EDB9315A
 CONFIG_EDB93XX_INDUSTRIAL
 CONFIG_EDB93XX_SDCS0
 CONFIG_EDB93XX_SDCS1
 CONFIG_EDB93XX_SDCS2
 CONFIG_EDB93XX_SDCS3
 CONFIG_EEPRO100
 CONFIG_EEPRO100_SROM_WRITE
 CONFIG_EFLASH_PROTSECTORS
 CONFIG_EHCI_DESC_BIG_ENDIAN
 CONFIG_EHCI_HCD_INIT_AFTER_RESET
 CONFIG_EHCI_IS_TDI
 CONFIG_EHCI_MMIO_BIG_ENDIAN
 CONFIG_EHCI_MXS_PORT0
 CONFIG_EHCI_MXS_PORT1
 CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 CONFIG_EMMC_BOOT
 CONFIG_EMU
 CONFIG_ENABLE_36BIT_PHYS
 CONFIG_ENABLE_MMU
 CONFIG_ENABLE_MUST_CHECK
 CONFIG_ENABLE_WARN_DEPRECATED
 CONFIG_ENC_SILENTLINK
 CONFIG_ENV_ACCESS_IGNORE_FORCE
 CONFIG_ENV_ADDR
 CONFIG_ENV_ADDR_FLEX
 CONFIG_ENV_ADDR_REDUND
 CONFIG_ENV_BASE
 CONFIG_ENV_CALLBACK_LIST_DEFAULT
 CONFIG_ENV_CALLBACK_LIST_STATIC
 CONFIG_ENV_COMMON_BOOT
 CONFIG_ENV_EEPROM_IS_ON_I2C
 CONFIG_ENV_FIT_UCBOOT
 CONFIG_ENV_FLAGS_LIST_DEFAULT
 CONFIG_ENV_FLAGS_LIST_STATIC
 CONFIG_ENV_FLASHBOOT
 CONFIG_ENV_IS_EMBEDDED
 CONFIG_ENV_IS_IN_
 CONFIG_ENV_MAX_ENTRIES
 CONFIG_ENV_MIN_ENTRIES
 CONFIG_ENV_OFFSET_OOB
 CONFIG_ENV_OFFSET_REDUND
 CONFIG_ENV_OVERWRITE
 CONFIG_ENV_RANGE
 CONFIG_ENV_RDADDR
 CONFIG_ENV_REFLASH
 CONFIG_ENV_SECT_SIZE
 CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS
 CONFIG_ENV_SETTINGS_NAND_V1
 CONFIG_ENV_SETTINGS_NAND_V2
 CONFIG_ENV_SETTINGS_V1
 CONFIG_ENV_SETTINGS_V2
 CONFIG_ENV_SIZE_FLEX
 CONFIG_ENV_SIZE_REDUND
 CONFIG_ENV_SPI_BASE
 CONFIG_ENV_SPI_BUS
 CONFIG_ENV_SPI_CS
 CONFIG_ENV_SPI_MAX_HZ
 CONFIG_ENV_SPI_MODE
 CONFIG_ENV_SROM_BANK
 CONFIG_ENV_TOTAL_SIZE
 CONFIG_ENV_UBIFS_OPTION
 CONFIG_ENV_UBI_MTD
 CONFIG_ENV_UBI_VOLUME_REDUND
 CONFIG_ENV_VARS_UBOOT_CONFIG
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 CONFIG_ENV_VERSION
 CONFIG_EP9301
 CONFIG_EP9302
 CONFIG_EP9307
 CONFIG_EP9312
 CONFIG_EP9315
 CONFIG_EP93XX
 CONFIG_EP93XX_NO_FLASH_CFG
 CONFIG_EPH_POWER_EN
 CONFIG_EPOLL
 CONFIG_ESBC_ADDR_64BIT
 CONFIG_ESBC_HDR_LS
 CONFIG_ESDHC_DETECT_8_BIT_QUIRK
 CONFIG_ESDHC_DETECT_QUIRK
 CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1
 CONFIG_ESDHC_HC_BLK_ADDR
 CONFIG_ESPRESSO7420
 CONFIG_ESPT
 CONFIG_ET1100_BASE
 CONFIG_ETH1ADDR
 CONFIG_ETH2ADDR
 CONFIG_ETHADDR
 CONFIG_ETHBASE
 CONFIG_ETHER_INDEX
 CONFIG_ETHER_NONE
 CONFIG_ETHER_ON_FCC
 CONFIG_ETHER_ON_FCC1
 CONFIG_ETHER_ON_FCC2
 CONFIG_ETHER_ON_FCC3
 CONFIG_ETHPRIME
 CONFIG_ETH_BUFSIZE
 CONFIG_ETH_RXSIZE
 CONFIG_EXT4_WRITE
 CONFIG_EXTRA_BOOTARGS
 CONFIG_EXTRA_CLOCK
 CONFIG_EXTRA_ENV
 CONFIG_EXTRA_ENV_BOARD_SETTINGS
 CONFIG_EXTRA_ENV_ITB
 CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS
 CONFIG_EXTRA_ENV_SETTINGS
 CONFIG_EXTRA_ENV_SETTINGS_COMMON
 CONFIG_EXTRA_ENV_UNLOCK
 CONFIG_EXTRA_ENV_USBTTY
 CONFIG_EXT_AHB2AHB_BASE
 CONFIG_EXT_AHBAPBBRG_BASE
 CONFIG_EXT_AHBPCIBRG_BASE
 CONFIG_EXT_AHBSLAVE01_BASE
 CONFIG_EXT_AHBSLAVE02_BASE
 CONFIG_EXT_PHY
 CONFIG_EXT_USB_HOST_BASE
 CONFIG_EXYNOS4
 CONFIG_EXYNOS4210
 CONFIG_EXYNOS5
 CONFIG_EXYNOS5250
 CONFIG_EXYNOS5420
 CONFIG_EXYNOS5800
 CONFIG_EXYNOS5_DT
 CONFIG_EXYNOS7420
 CONFIG_EXYNOS_ACE_SHA
 CONFIG_EXYNOS_DP
 CONFIG_EXYNOS_FB
 CONFIG_EXYNOS_MIPI_DSIM
 CONFIG_EXYNOS_RELOCATE_CODE_BASE
 CONFIG_EXYNOS_SPL
 CONFIG_EXYNOS_TMU
 CONFIG_FACTORYSET
 CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE
 CONFIG_FASTBOOT_FLASH_NAND_TRIMFFS
 CONFIG_FAST_FLASH_BIT
 CONFIG_FB_ADDR
 CONFIG_FB_BACKLIGHT
 CONFIG_FB_DEFERRED_IO
 CONFIG_FDT1_ENV_ADDR
 CONFIG_FDT2_ENV_ADDR
 CONFIG_FDTADDR
 CONFIG_FDTFILE
 CONFIG_FEATURE_CLEAN_UP
 CONFIG_FEATURE_COMMAND_EDITING
 CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN
 CONFIG_FEATURE_SH_EXTRA_QUIET
 CONFIG_FEATURE_SH_FANCY_PROMPT
 CONFIG_FEATURE_SH_STANDALONE_SHELL
 CONFIG_FEC_ENET_DEV
 CONFIG_FEC_FIXED_SPEED
 CONFIG_FEC_MXC_25M_REF_CLK
 CONFIG_FEC_MXC_PHYADDR
 CONFIG_FEC_MXC_SWAP_PACKET
 CONFIG_FEC_XCV_TYPE
 CONFIG_FEROCEON
 CONFIG_FEROCEON_88FR131
 CONFIG_FFUART
 CONFIG_FILE
 CONFIG_FIRMWARE_OFFSET
 CONFIG_FIRMWARE_SIZE
 CONFIG_FIXED_PHY
 CONFIG_FIXED_PHY_ADDR
 CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 CONFIG_FLASHBOOTCOMMAND
 CONFIG_FLASHCARD
 CONFIG_FLASH_16BIT
 CONFIG_FLASH_BASE
 CONFIG_FLASH_BR_PRELIM
 CONFIG_FLASH_CFI_DRIVER
 CONFIG_FLASH_CFI_LEGACY
 CONFIG_FLASH_CFI_MTD
 CONFIG_FLASH_END
 CONFIG_FLASH_NOT_MEM_MAPPED
 CONFIG_FLASH_OR_PRELIM
 CONFIG_FLASH_PNOR
 CONFIG_FLASH_SECTOR_SIZE
 CONFIG_FLASH_SHOW_PROGRESS
 CONFIG_FLASH_SPANSION_S29WS_N
 CONFIG_FLASH_VERIFY
 CONFIG_FMAN_ENET
 CONFIG_FM_PLAT_CLK_DIV
 CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
 CONFIG_FORMIKE
 CONFIG_FPGA_COUNT
 CONFIG_FPGA_DELAY
 CONFIG_FPGA_SPARTAN3
 CONFIG_FPGA_STRATIX_V
 CONFIG_FPGA_ZYNQPL
 CONFIG_FSLDMAFEC
 CONFIG_FSL_CADMUS
 CONFIG_FSL_CORENET
 CONFIG_FSL_CPLD
 CONFIG_FSL_DCU_SII9022A
 CONFIG_FSL_DDR_BIST
 CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 CONFIG_FSL_DDR_INTERACTIVE
 CONFIG_FSL_DDR_SYNC_REFRESH
 CONFIG_FSL_DEEP_SLEEP
 CONFIG_FSL_DEVICE_DISABLE
 CONFIG_FSL_DIU_CH7301
 CONFIG_FSL_DIU_FB
 CONFIG_FSL_DMA
 CONFIG_FSL_DSPI1
 CONFIG_FSL_ESDHC
 CONFIG_FSL_ESDHC_ADAPTER_IDENT
 CONFIG_FSL_ESDHC_PIN_MUX
 CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 CONFIG_FSL_FIXED_MMC_LOCATION
 CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
 CONFIG_FSL_I2C_CUSTOM_DFSR
 CONFIG_FSL_I2C_CUSTOM_FDR
 CONFIG_FSL_IIM
 CONFIG_FSL_ISBC_KEY_EXT
 CONFIG_FSL_LAYERSCAPE
 CONFIG_FSL_LBC
 CONFIG_FSL_LINFLEXUART
 CONFIG_FSL_MC9SDZ60
 CONFIG_FSL_MEMAC
 CONFIG_FSL_NGPIXIS
 CONFIG_FSL_PCIE_DISABLE_ASPM
 CONFIG_FSL_PCIE_RESET
 CONFIG_FSL_PCI_INIT
 CONFIG_FSL_PIXIS
 CONFIG_FSL_PMIC_BITLEN
 CONFIG_FSL_PMIC_BUS
 CONFIG_FSL_PMIC_CLK
 CONFIG_FSL_PMIC_CS
 CONFIG_FSL_PMIC_MODE
 CONFIG_FSL_QIXIS
 CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 CONFIG_FSL_QIXIS_V2
-CONFIG_FSL_SATA
 CONFIG_FSL_SATA_V2
 CONFIG_FSL_SDHC_V2_3
 CONFIG_FSL_SDRAM_TYPE
 CONFIG_FSL_SERDES
 CONFIG_FSL_SERDES1
 CONFIG_FSL_SERDES2
 CONFIG_FSL_SGMII_RISER
 CONFIG_FSL_SPI_INTERFACE
 CONFIG_FSL_TBCLK_EXTRA_DIV
 CONFIG_FSL_TRUST_ARCH_v1
 CONFIG_FSL_TZASC_400
 CONFIG_FSL_TZPC_BP147
 CONFIG_FSL_USDHC
 CONFIG_FSL_VIA
 CONFIG_FSMC_NAND_BASE
 CONFIG_FSMTDBLK
 CONFIG_FSNOTIFY
 CONFIG_FS_EXT4
 CONFIG_FS_POSIX_ACL
 CONFIG_FTAHBC020S
 CONFIG_FTAHBC020S_BASE
 CONFIG_FTAPBBRG020S_01_BASE
 CONFIG_FTCFC010_BASE
 CONFIG_FTDMAC020_BASE
 CONFIG_FTGMAC100_BASE
 CONFIG_FTGMAC100_EGIGA
 CONFIG_FTGPIO010_BASE
 CONFIG_FTIDE020S_BASE
 CONFIG_FTIIC010_BASE
 CONFIG_FTINTC010_BASE
 CONFIG_FTLCDC100_BASE
 CONFIG_FTMAC100_BASE
 CONFIG_FTMAC110_BASE
 CONFIG_FTPCI100_BASE
 CONFIG_FTPCI100_IO_SIZE
 CONFIG_FTPCI100_MEM_BASE
 CONFIG_FTPCI100_MEM_SIZE
 CONFIG_FTPMU010
 CONFIG_FTPMU010_BASE
 CONFIG_FTPMU010_POWER
 CONFIG_FTPWM010_BASE
 CONFIG_FTRACE_MCOUNT_RECORD
 CONFIG_FTRTC010_BASE
 CONFIG_FTRTC010_EXTCLK
 CONFIG_FTRTC010_PCLK
 CONFIG_FTSDC010
 CONFIG_FTSDC010_BASE
 CONFIG_FTSDC010_BASE_LIST
 CONFIG_FTSDC010_NUMBER
 CONFIG_FTSDC010_SDIO
 CONFIG_FTSDMC021
 CONFIG_FTSDMC021_BASE
 CONFIG_FTSMC020
 CONFIG_FTSMC020_BASE
 CONFIG_FTSSP010_01_BASE
 CONFIG_FTSSP010_02_BASE
 CONFIG_FTTMR010_BASE
 CONFIG_FTTMR010_EXT_CLK
 CONFIG_FTUART010_01_BASE
 CONFIG_FTUART010_02_BASE
 CONFIG_FTUART010_03_BASE
 CONFIG_FTWDT010_BASE
 CONFIG_FTWDT010_WATCHDOG
 CONFIG_FZOTG266HD0A_BASE
 CONFIG_GATEWAYIP
 CONFIG_GCOV_KERNEL
 CONFIG_GCOV_PROFILE_ALL
 CONFIG_GICV2
 CONFIG_GICV3
 CONFIG_GLOBAL_DATA_NOT_REG10
 CONFIG_GLOBAL_TIMER
 CONFIG_GMII
 CONFIG_GOOD_SESH4
 CONFIG_GPCNTRL
 CONFIG_GPIO
 CONFIG_GPIO_ENABLE_SPI_FLASH
 CONFIG_GPIO_LED_INVERTED_TABLE
 CONFIG_GPIO_LED_STUBS
 CONFIG_GREEN_LED
 CONFIG_GURNARD_FPGA
 CONFIG_GURNARD_SPLASH
 CONFIG_GZIP
 CONFIG_GZIP_COMPRESSED
 CONFIG_GZIP_COMPRESS_DEF_SZ
 CONFIG_G_DNL_THOR_PRODUCT_NUM
 CONFIG_G_DNL_THOR_VENDOR_NUM
 CONFIG_G_DNL_UMS_PRODUCT_NUM
 CONFIG_G_DNL_UMS_VENDOR_NUM
 CONFIG_H264_FREQ
 CONFIG_H8300
 CONFIG_HARD_SPI
 CONFIG_HAS_ETH0
 CONFIG_HAS_ETH1
 CONFIG_HAS_ETH2
 CONFIG_HAS_ETH3
 CONFIG_HAS_ETH4
 CONFIG_HAS_ETH5
 CONFIG_HAS_ETH7
 CONFIG_HAS_FEC
 CONFIG_HAS_FSL_DR_USB
 CONFIG_HAS_FSL_MPH_USB
 CONFIG_HAS_POST
 CONFIG_HCLK_FREQ
 CONFIG_HDBOOT
 CONFIG_HDMI_ENCODER_I2C_ADDR
 CONFIG_HETROGENOUS_CLUSTERS
 CONFIG_HIDE_LOGO_VERSION
 CONFIG_HIGH_BATS
 CONFIG_HIKEY_GPIO
 CONFIG_HIS_DRIVER
 CONFIG_HITACHI_SX14
 CONFIG_HOSTNAME
 CONFIG_HOST_MAX_DEVICES
 CONFIG_HOTPLUG
 CONFIG_HPS_ALTERAGRP_DBGATCLK
 CONFIG_HPS_ALTERAGRP_MAINCLK
 CONFIG_HPS_ALTERAGRP_MPUCLK
 CONFIG_HPS_CLK_CAN0_HZ
 CONFIG_HPS_CLK_CAN1_HZ
 CONFIG_HPS_CLK_EMAC0_HZ
 CONFIG_HPS_CLK_EMAC1_HZ
 CONFIG_HPS_CLK_F2S_PER_REF_HZ
 CONFIG_HPS_CLK_F2S_SDR_REF_HZ
 CONFIG_HPS_CLK_GPIODB_HZ
 CONFIG_HPS_CLK_L4_MP_HZ
 CONFIG_HPS_CLK_L4_SP_HZ
 CONFIG_HPS_CLK_MAINVCO_HZ
 CONFIG_HPS_CLK_NAND_HZ
 CONFIG_HPS_CLK_OSC1_HZ
 CONFIG_HPS_CLK_OSC2_HZ
 CONFIG_HPS_CLK_PERVCO_HZ
 CONFIG_HPS_CLK_QSPI_HZ
 CONFIG_HPS_CLK_SDMMC_HZ
 CONFIG_HPS_CLK_SDRVCO_HZ
 CONFIG_HPS_CLK_SPIM_HZ
 CONFIG_HPS_CLK_USBCLK_HZ
 CONFIG_HPS_DBCTRL_STAYOSC1
 CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
 CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH
 CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH
 CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT
 CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT
 CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK
 CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK
 CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP
 CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP
 CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT
 CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK
 CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK
 CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK
 CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK
 CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT
 CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
 CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT
 CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK
 CONFIG_HPS_MAINPLLGRP_VCO_DENOM
 CONFIG_HPS_MAINPLLGRP_VCO_NUMER
 CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK
 CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK
 CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK
 CONFIG_HPS_PERPLLGRP_DIV_USBCLK
 CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT
 CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT
 CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK
 CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT
 CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT
 CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT
 CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT
 CONFIG_HPS_PERPLLGRP_SRC_NAND
 CONFIG_HPS_PERPLLGRP_SRC_QSPI
 CONFIG_HPS_PERPLLGRP_SRC_SDMMC
 CONFIG_HPS_PERPLLGRP_VCO_DENOM
 CONFIG_HPS_PERPLLGRP_VCO_NUMER
 CONFIG_HPS_PERPLLGRP_VCO_PSRC
 CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT
 CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE
 CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT
 CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE
 CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT
 CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE
 CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT
 CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE
 CONFIG_HPS_SDRPLLGRP_VCO_DENOM
 CONFIG_HPS_SDRPLLGRP_VCO_NUMER
 CONFIG_HPS_SDRPLLGRP_VCO_SSRC
 CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR
 CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP
 CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH
 CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT
 CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH
 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS
 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS
 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS
 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS
 CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH
 CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH
 CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN
 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ
 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
 CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
 CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED
 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED
 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED
 CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
 CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES
 CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36
 CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0
 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32
 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46
 CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0
 CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN
 CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP
 CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
 CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
 CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
 CONFIG_HP_CLK_FREQ
 CONFIG_HRCON
 CONFIG_HRCON_DH
 CONFIG_HRCON_FANS
 CONFIG_HSMMC2_8BIT
 CONFIG_HUSH_INIT_VAR
 CONFIG_HVBOOT
 CONFIG_HWCONFIG
 CONFIG_HW_ENV_SETTINGS
 CONFIG_I2C
 CONFIG_I2C_CHIPADDRESS
 CONFIG_I2C_CMD_TREE
 CONFIG_I2C_ENV_EEPROM_BUS
 CONFIG_I2C_FPGA
 CONFIG_I2C_GSC
 CONFIG_I2C_MAC_OFFSET
 CONFIG_I2C_MBB_TIMEOUT
 CONFIG_I2C_MULTI_BUS
 CONFIG_I2C_MV
 CONFIG_I2C_MVTWSI
 CONFIG_I2C_MVTWSI_BASE
 CONFIG_I2C_MVTWSI_BASE0
 CONFIG_I2C_MVTWSI_BASE1
 CONFIG_I2C_MVTWSI_BASE2
 CONFIG_I2C_MVTWSI_BASE3
 CONFIG_I2C_MVTWSI_BASE4
 CONFIG_I2C_MVTWSI_BASE5
 CONFIG_I2C_REPEATED_START
 CONFIG_I2C_RTC_ADDR
 CONFIG_I2C_TIMEOUT
 CONFIG_ICACHE
 CONFIG_ICS307_REFCLK_HZ
 CONFIG_IDE_PCMCIA
 CONFIG_IDE_PREINIT
 CONFIG_IDE_RESET
 CONFIG_IDE_SWAP_IO
 CONFIG_IDS8313
 CONFIG_IDT8T49N222A
 CONFIG_ID_EEPROM
 CONFIG_IMA
 CONFIG_IMAGE_FORMAT_LEGACY
 CONFIG_IMX
 CONFIG_IMX6_PWM_PER_CLK
 CONFIG_IMX_HDMI
 CONFIG_IMX_NAND
 CONFIG_IMX_OTP
 CONFIG_IMX_VIDEO_SKIP
 CONFIG_IMX_WATCHDOG
 CONFIG_INETSPACE_V2
 CONFIG_INITRD_TAG
 CONFIG_INIT_CRITICAL
 CONFIG_INIT_IGNORE_ERROR
 CONFIG_INI_ALLOW_MULTILINE
 CONFIG_INI_CASE_INSENSITIVE
 CONFIG_INI_MAX_LINE
 CONFIG_INI_MAX_NAME
 CONFIG_INI_MAX_SECTION
 CONFIG_INTEGRITY
 CONFIG_INTERRUPTS
 CONFIG_IO
 CONFIG_IO64
 CONFIG_IOCON
 CONFIG_IODELAY_RECALIBRATION
 CONFIG_IOMUX_LPSR
 CONFIG_IOMUX_SHARE_CONF_REG
 CONFIG_IOS
 CONFIG_IO_TRACE
 CONFIG_IPADDR
 CONFIG_IPADDR1
 CONFIG_IPADDR2
 CONFIG_IPAM390_GPIO_BOOTMODE
 CONFIG_IPAM390_GPIO_LED_GREEN
 CONFIG_IPAM390_GPIO_LED_RED
 CONFIG_IPROC
 CONFIG_IP_DEFRAG
 CONFIG_IRAM_BASE
 CONFIG_IRAM_END
 CONFIG_IRAM_SIZE
 CONFIG_IRAM_STACK
 CONFIG_IRAM_TOP
 CONFIG_IRDA_BASE
 CONFIG_IS_BUILTIN
 CONFIG_IS_ENABLED
 CONFIG_IS_MODULE
 CONFIG_JFFS2_CMDLINE
 CONFIG_JFFS2_DEV
 CONFIG_JFFS2_LZO
 CONFIG_JFFS2_NAND
 CONFIG_JFFS2_PART_OFFSET
 CONFIG_JFFS2_PART_SIZE
 CONFIG_JFFS2_SUMMARY
 CONFIG_JRSTARTR_JR0
 CONFIG_JTAG_CONSOLE
 CONFIG_KASAN
 CONFIG_KCLK_DIS
 CONFIG_KEEP_SERVERADDR
 CONFIG_KERNEL_OFFSET
 CONFIG_KEYBOARD
 CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE
 CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE
 CONFIG_KEYSTONE_RBL_NAND
 CONFIG_KEY_REVOCATION
 CONFIG_KGDB_BAUDRATE
 CONFIG_KGDB_SER_INDEX
 CONFIG_KIRKWOOD_EGIGA_INIT
 CONFIG_KIRKWOOD_GPIO
 CONFIG_KIRKWOOD_PCIE_INIT
 CONFIG_KIRKWOOD_RGMII_PAD_1V8
 CONFIG_KIRKWOOD_SPI
 CONFIG_KIRQ_EN
 CONFIG_KM8321
 CONFIG_KMCOGE4
 CONFIG_KMCOGE5NE
 CONFIG_KMETER1
 CONFIG_KMLION1
 CONFIG_KMOPTI2
 CONFIG_KMP204X
 CONFIG_KMSUPX5
 CONFIG_KMTEGR1
 CONFIG_KMTEPR2
 CONFIG_KMVECT1
 CONFIG_KM_BOARD_EXTRA_ENV
 CONFIG_KM_BOARD_NAME
 CONFIG_KM_COGE5UN
 CONFIG_KM_COMMON_ETH_INIT
 CONFIG_KM_CONSOLE_TTY
 CONFIG_KM_CRAMFS_ADDR
 CONFIG_KM_DEF_ARCH
 CONFIG_KM_DEF_BOOT_ARGS_CPU
 CONFIG_KM_DEF_ENV
 CONFIG_KM_DEF_ENV_BOOTARGS
 CONFIG_KM_DEF_ENV_BOOTPARAMS
 CONFIG_KM_DEF_ENV_BOOTTARGETS
 CONFIG_KM_DEF_ENV_CONSTANTS
 CONFIG_KM_DEF_ENV_CPU
 CONFIG_KM_DEF_ENV_FLASH_BOOT
 CONFIG_KM_DEF_NETDEV
 CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
 CONFIG_KM_DISABLE_PCI
 CONFIG_KM_DISABLE_PCIE
 CONFIG_KM_ECC_MODE
 CONFIG_KM_ENV_IS_IN_SPI_NOR
 CONFIG_KM_FDT_ADDR
 CONFIG_KM_FPGA_CONFIG
 CONFIG_KM_IVM_BUS
 CONFIG_KM_KERNEL_ADDR
 CONFIG_KM_KIRKWOOD
 CONFIG_KM_KIRKWOOD_128M16
 CONFIG_KM_KIRKWOOD_PCI
 CONFIG_KM_MGCOGE3UN
 CONFIG_KM_MVEXTSW_ADDR
 CONFIG_KM_NEW_ENV
 CONFIG_KM_NUSA
 CONFIG_KM_PHRAM
 CONFIG_KM_PIGGY4_88E6061
 CONFIG_KM_PIGGY4_88E6352
 CONFIG_KM_PNVRAM
 CONFIG_KM_PORTL2
 CONFIG_KM_RESERVED_PRAM
 CONFIG_KM_ROOTFSSIZE
 CONFIG_KM_SUGP1
 CONFIG_KM_SUV31
 CONFIG_KM_UBI_LINUX_MTD
 CONFIG_KM_UBI_PARTITION_NAME_APP
 CONFIG_KM_UBI_PARTITION_NAME_BOOT
 CONFIG_KM_UBI_PART_BOOT_OPTS
 CONFIG_KM_UIMAGE_NAME
 CONFIG_KM_UPDATE_UBOOT
 CONFIG_KONA
 CONFIG_KONA_GPIO
 CONFIG_KONA_RESET_S
 CONFIG_KPROBES
 CONFIG_KS8851_MLL
 CONFIG_KS8851_MLL_BASEADDR
 CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE
 CONFIG_KSNAV_NETCP_PDMA_RX_BASE
 CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM
 CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE
 CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM
 CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE
 CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE
 CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE
 CONFIG_KSNAV_NETCP_PDMA_TX_BASE
 CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM
 CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE
 CONFIG_KSNAV_PKTDMA_NETCP
 CONFIG_KSNAV_QM_BASE_ADDRESS
 CONFIG_KSNAV_QM_CONF_BASE
 CONFIG_KSNAV_QM_DESC_SETUP_BASE
 CONFIG_KSNAV_QM_INTD_CONF_BASE
 CONFIG_KSNAV_QM_LINK_RAM_BASE
 CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE
 CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE
 CONFIG_KSNAV_QM_PDSP1_CMD_BASE
 CONFIG_KSNAV_QM_PDSP1_CTRL_BASE
 CONFIG_KSNAV_QM_PDSP1_IRAM_BASE
 CONFIG_KSNAV_QM_QPOOL_NUM
 CONFIG_KSNAV_QM_QUEUE_STATUS_BASE
 CONFIG_KSNAV_QM_REGION_NUM
 CONFIG_KSNAV_QM_STATUS_RAM_BASE
 CONFIG_KSNET_CPSW_NUM_PORTS
 CONFIG_KSNET_MAC_ID_BASE
 CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
 CONFIG_KSNET_NETCP_BASE
 CONFIG_KSNET_NETCP_V1_0
 CONFIG_KSNET_NETCP_V1_5
 CONFIG_KSNET_SERDES_LANES_PER_SGMII
 CONFIG_KSNET_SERDES_SGMII2_BASE
 CONFIG_KSNET_SERDES_SGMII_BASE
 CONFIG_KVM_GUEST
 CONFIG_KW88F6192
 CONFIG_KW88F6281
 CONFIG_KW88F6702
 CONFIG_KZM_A9_GT
 CONFIG_L1_INIT_RAM
 CONFIG_L2_CACHE
 CONFIG_LAN91C96_USE_32_BIT
 CONFIG_LAST_STAGE_INIT
 CONFIG_LAYERSCAPE_NS_ACCESS
 CONFIG_LBA48
 CONFIG_LBDAF
 CONFIG_LCD_ALIGNMENT
 CONFIG_LCD_BMP_RLE8
 CONFIG_LCD_DT_SIMPLEFB
 CONFIG_LCD_INFO
 CONFIG_LCD_INFO_BELOW_LOGO
 CONFIG_LCD_IN_PSRAM
 CONFIG_LCD_LOGO
 CONFIG_LCD_MENU
 CONFIG_LCD_ROTATION
 CONFIG_LD9040
 CONFIG_LEGACY
 CONFIG_LEGACY_BOOTCMD_ENV
 CONFIG_LG4573
 CONFIG_LG4573_BUS
 CONFIG_LG4573_CS
 CONFIG_LIBATA
 CONFIG_LIB_HW_RAND
 CONFIG_LIB_UUID
 CONFIG_LINUX
 CONFIG_LINUX_RESET_VEC
 CONFIG_LITTLETON_LCD
 CONFIG_LMB
 CONFIG_LMS283GF05
 CONFIG_LOADADDR
 CONFIG_LOADCMD
 CONFIG_LOADS_ECHO
 CONFIG_LOWPOWER_ADDR
 CONFIG_LOWPOWER_FLAG
 CONFIG_LOW_MCFCLK
 CONFIG_LPC32XX_ETH
 CONFIG_LPC32XX_ETH_BUFS_BASE
 CONFIG_LPC32XX_HSUART
 CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY
 CONFIG_LPC32XX_NAND_MLC_NAND_TA
 CONFIG_LPC32XX_NAND_MLC_RD_HIGH
 CONFIG_LPC32XX_NAND_MLC_RD_LOW
 CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY
 CONFIG_LPC32XX_NAND_MLC_WR_HIGH
 CONFIG_LPC32XX_NAND_MLC_WR_LOW
 CONFIG_LPC32XX_NAND_SLC_RDR_CLKS
 CONFIG_LPC32XX_NAND_SLC_RHOLD
 CONFIG_LPC32XX_NAND_SLC_RSETUP
 CONFIG_LPC32XX_NAND_SLC_RWIDTH
 CONFIG_LPC32XX_NAND_SLC_WDR_CLKS
 CONFIG_LPC32XX_NAND_SLC_WHOLD
 CONFIG_LPC32XX_NAND_SLC_WSETUP
 CONFIG_LPC32XX_NAND_SLC_WWIDTH
 CONFIG_LPC32XX_SDRAM_
 CONFIG_LPC32XX_SPL
 CONFIG_LPC32XX_SSP
 CONFIG_LPC32XX_SSP_TIMEOUT
 CONFIG_LPC_BASE
 CONFIG_LPC_IO_BASE
 CONFIG_LPUART
 CONFIG_LPUART_32B_REG
 CONFIG_LQ038J7DH53
 CONFIG_LS102XA_STREAM_ID
 CONFIG_LSCHLV2
 CONFIG_LSXHL
 CONFIG_LYNXKDI
 CONFIG_M41T94_SPI_CS
 CONFIG_M520x
 CONFIG_M52277EVB
 CONFIG_M5253DEMO
 CONFIG_M5253EVBE
 CONFIG_M5275EVB
 CONFIG_M5301x
 CONFIG_M54418TWR
 CONFIG_M54451EVB
 CONFIG_M54455EVB
 CONFIG_MACB0_PHY
 CONFIG_MACB1_PHY
 CONFIG_MACB2_PHY
 CONFIG_MACB3_PHY
 CONFIG_MACB_SEARCH_PHY
 CONFIG_MACH_ASPENITE
 CONFIG_MACH_DAVINCI_CALIMAIN
 CONFIG_MACH_DAVINCI_DA850_EVM
 CONFIG_MACH_DOCKSTAR
 CONFIG_MACH_EDMINIV2
 CONFIG_MACH_GOFLEXHOME
 CONFIG_MACH_GONI
 CONFIG_MACH_GURUPLUG
 CONFIG_MACH_KM_KIRKWOOD
 CONFIG_MACH_OMAPL138_LCDK
 CONFIG_MACH_OPENRD_BASE
 CONFIG_MACH_SHEEVAPLUG
 CONFIG_MACH_SPECIFIC
 CONFIG_MACH_TYPE
 CONFIG_MACH_TYPE_COMPAT_REV
 CONFIG_MACRESET_TIMEOUT
 CONFIG_MALLOC_F_ADDR
 CONFIG_MALTA
 CONFIG_MARCO_MEMSET
 CONFIG_MARUBUN_PCCARD
 CONFIG_MARVELL
 CONFIG_MARVELL_GPIO
 CONFIG_MARVELL_MFP
 CONFIG_MASK_AER_AO
 CONFIG_MAX_DSP_CPUS
 CONFIG_MAX_FPGA_DEVICES
 CONFIG_MAX_MEM_MAPPED
 CONFIG_MAX_PKT
 CONFIG_MAX_RAM_BANK_SIZE
 CONFIG_MCAST_TFTP
 CONFIG_MCF5249
 CONFIG_MCF5253
 CONFIG_MCFFEC
 CONFIG_MCFPIT
 CONFIG_MCFRTC
 CONFIG_MCFTMR
 CONFIG_MCFUART
 CONFIG_MCLK_DIS
 CONFIG_MDIO_TIMEOUT
 CONFIG_MEMSIZE
 CONFIG_MEMSIZE_IN_BYTES
 CONFIG_MEMSIZE_MASK
 CONFIG_MEM_HOLE_16M
 CONFIG_MEM_INIT_VALUE
 CONFIG_MEM_REMAP
 CONFIG_MENUKEY
 CONFIG_MENUPROMPT
 CONFIG_MENU_SHOW
 CONFIG_MFG_ENV_SETTINGS
 CONFIG_MIGO_R
 CONFIG_MII
 CONFIG_MIIM_ADDRESS
 CONFIG_MII_DEFAULT_TSEC
 CONFIG_MII_INIT
 CONFIG_MII_SUPPRESS_PREAMBLE
 CONFIG_MIPS_HUGE_TLB_SUPPORT
 CONFIG_MIPS_MT_FPAFF
 CONFIG_MIRQ_EN
 CONFIG_MISC_COMMON
 CONFIG_MISC_INIT_F
 CONFIG_MISC_INIT_R
 CONFIG_MIU_1BIT_INTERLEAVED
 CONFIG_MIU_2BIT_21_7_INTERLEAVED
 CONFIG_MIU_2BIT_INTERLEAVED
 CONFIG_MIU_LINEAR
 CONFIG_MK_edb9301
 CONFIG_MK_edb9315a
 CONFIG_MMCBOOTCOMMAND
 CONFIG_MMCROOT
 CONFIG_MMC_DEFAULT_DEV
 CONFIG_MMC_RPMB_TRACE
 CONFIG_MMC_SPI
 CONFIG_MMC_SPI_BUS
 CONFIG_MMC_SPI_CRC_ON
 CONFIG_MMC_SPI_CS
 CONFIG_MMC_SPI_MODE
 CONFIG_MMC_SPI_SPEED
 CONFIG_MMC_SUNXI_SLOT
 CONFIG_MMC_TRACE
 CONFIG_MMU
 CONFIG_MODVERSIONS
 CONFIG_MONITOR_IS_IN_RAM
 CONFIG_MP
 CONFIG_MPC8308
 CONFIG_MPC8308RDB
 CONFIG_MPC8308_P1M
 CONFIG_MPC8309
 CONFIG_MPC830x
 CONFIG_MPC8313
 CONFIG_MPC8313ERDB
 CONFIG_MPC8315
 CONFIG_MPC8315ERDB
 CONFIG_MPC831x
 CONFIG_MPC832XEMDS
 CONFIG_MPC832x
 CONFIG_MPC8349
 CONFIG_MPC8349EMDS
 CONFIG_MPC8349ITX
 CONFIG_MPC8349ITXGP
 CONFIG_MPC834x
 CONFIG_MPC8360
 CONFIG_MPC837XEMDS
 CONFIG_MPC837XERDB
 CONFIG_MPC837x
 CONFIG_MPC83XX_GPIO
 CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
 CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
 CONFIG_MPC83XX_GPIO_0_INIT_VALUE
 CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION
 CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN
 CONFIG_MPC83XX_GPIO_1_INIT_VALUE
 CONFIG_MPC83XX_PCI2
 CONFIG_MPC85XX_FEC
 CONFIG_MPC85XX_FEC_NAME
 CONFIG_MPC85XX_PCI2
 CONFIG_MPC8XXX_SPI
 CONFIG_MPC8xxx_DISABLE_BPTR
 CONFIG_MPLL_FREQ
 CONFIG_MPR2
 CONFIG_MP_CLK_FREQ
 CONFIG_MS7720SE
 CONFIG_MS7722SE
 CONFIG_MS7750SE
 CONFIG_MSHC_FREQ
 CONFIG_MTD_CONCAT
 CONFIG_MTD_DEVICE
 CONFIG_MTD_ECC_SOFT
 CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
 CONFIG_MTD_NAND_ECC_SMC
 CONFIG_MTD_NAND_MUSEUM_IDS
 CONFIG_MTD_NAND_VERIFY_WRITE
 CONFIG_MTD_ONENAND_VERIFY_WRITE
 CONFIG_MTD_PARTITION
 CONFIG_MTD_PARTITIONS
 CONFIG_MTD_UBI_BEB_RESERVE
 CONFIG_MTD_UBI_BLOCK
 CONFIG_MTD_UBI_DEBUG
 CONFIG_MTD_UBI_DEBUG_MSG
 CONFIG_MTD_UBI_DEBUG_MSG_BLD
 CONFIG_MTD_UBI_DEBUG_MSG_EBA
 CONFIG_MTD_UBI_DEBUG_MSG_IO
 CONFIG_MTD_UBI_DEBUG_MSG_WL
 CONFIG_MTD_UBI_DEBUG_PARANOID
 CONFIG_MTD_UBI_GLUEBI
 CONFIG_MTD_UBI_MODULE
 CONFIG_MULTI_CS
 CONFIG_MUSB_HOST
 CONFIG_MVEBU_MMC
 CONFIG_MVGBE
 CONFIG_MVGBE_PORTS
 CONFIG_MVMFP_V2
 CONFIG_MVS
 CONFIG_MVSATA_IDE
 CONFIG_MVSATA_IDE_USE_PORT0
 CONFIG_MVSATA_IDE_USE_PORT1
 CONFIG_MV_ETH_RXQ
 CONFIG_MV_I2C_NUM
 CONFIG_MV_I2C_REG
 CONFIG_MX23
 CONFIG_MX25
 CONFIG_MX25_CLK32
 CONFIG_MX25_HCLK_FREQ
 CONFIG_MX27
 CONFIG_MX27_CLK32
 CONFIG_MX27_TIMER_HIGH_PRECISION
 CONFIG_MX28
 CONFIG_MX28_FEC_MAC_IN_OCOTP
 CONFIG_MX31
 CONFIG_MX31_CLK32
 CONFIG_MX31_HCLK_FREQ
 CONFIG_MX35
 CONFIG_MX35_CLK32
 CONFIG_MX35_HCLK_FREQ
 CONFIG_MX6DL_LPDDR2
 CONFIG_MX6DQ_LPDDR2
 CONFIG_MX6SX_SABRESD_REVA
 CONFIG_MX6UL_14X14_EVK_EMMC_REWORK
 CONFIG_MXC_EPDC
 CONFIG_MXC_GPIO
 CONFIG_MXC_GPT_HCLK
 CONFIG_MXC_MCI_REGS_BASE
 CONFIG_MXC_NAND_HWECC
 CONFIG_MXC_NAND_IP_REGS_BASE
 CONFIG_MXC_NAND_REGS_BASE
 CONFIG_MXC_SPI
 CONFIG_MXC_UART_BASE
 CONFIG_MXC_USB_FLAGS
 CONFIG_MXC_USB_PORT
 CONFIG_MXC_USB_PORTSC
 CONFIG_MXS
 CONFIG_MXS_AUART
 CONFIG_MXS_AUART_BASE
 CONFIG_MXS_GPIO
 CONFIG_MXS_OCOTP
 CONFIG_MXS_SPI
 CONFIG_MX_CYCLIC
 CONFIG_MY_OPTION
 CONFIG_NANDFLASH_SIZE
 CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 CONFIG_NAND_ACTL
 CONFIG_NAND_ATMEL
 CONFIG_NAND_CS_INIT
 CONFIG_NAND_DATA_REG
 CONFIG_NAND_DAVINCI
 CONFIG_NAND_DENALI_ECC_SIZE
 CONFIG_NAND_ECC_BCH
 CONFIG_NAND_ENV_DST
 CONFIG_NAND_FSL_ELBC
 CONFIG_NAND_FSL_IFC
 CONFIG_NAND_FSL_NFC
 CONFIG_NAND_FSMC
 CONFIG_NAND_KIRKWOOD
 CONFIG_NAND_KMETER1
 CONFIG_NAND_LPC32XX_MLC
 CONFIG_NAND_LPC32XX_SLC
 CONFIG_NAND_MODE_REG
 CONFIG_NAND_MXC_V1_1
 CONFIG_NAND_NDFC
 CONFIG_NAND_OMAP_ECCSCHEME
 CONFIG_NAND_OMAP_GPMC_WSCFG
 CONFIG_NAND_SECBOOT
 CONFIG_NAND_SPL
 CONFIG_NAND_U_BOOT
 CONFIG_NATSEMI
 CONFIG_NCEL2C100_BASE
 CONFIG_NCEMIC100_BASE
 CONFIG_NDS_DLM1_BASE
 CONFIG_NDS_DLM2_BASE
 CONFIG_NEEDS_MANUAL_RELOC
 CONFIG_NEO
 CONFIG_NET2BIG_V2
 CONFIG_NETCONSOLE_BUFFER_SIZE
 CONFIG_NETDEV
 CONFIG_NETMASK
 CONFIG_NETSPACE_LITE_V2
 CONFIG_NETSPACE_MAX_V2
 CONFIG_NETSPACE_MINI_V2
 CONFIG_NETSPACE_V2
 CONFIG_NET_MAXDEFRAG
 CONFIG_NET_MULTI
 CONFIG_NET_RETRY_COUNT
 CONFIG_NEVER_ASSERT_ODT_TO_CPU
 CONFIG_NFC_FREQ
 CONFIG_NFSBOOTCOMMAND
 CONFIG_NFS_TIMEOUT
 CONFIG_NOBQFMAN
 CONFIG_NON_SECURE
 CONFIG_NORBOOT
 CONFIG_NORFLASH_PS32BIT
 CONFIG_NO_ETH
 CONFIG_NO_RELOCATION
 CONFIG_NO_WAIT
 CONFIG_NR_CPUS
 CONFIG_NR_DRAM_BANKS
 CONFIG_NR_DRAM_BANKS_MAX
 CONFIG_NR_DRAM_POPULATED
 CONFIG_NS16550_MIN_FUNCTIONS
 CONFIG_NS8382X
 CONFIG_NS87308
 CONFIG_NUM_DSP_CPUS
 CONFIG_NUM_PAMU
 CONFIG_ODROID_REV_AIN
 CONFIG_OFF_PADCONF
 CONFIG_OF_
 CONFIG_OF_SPI
 CONFIG_OF_SPI_FLASH
 CONFIG_OF_STDOUT_PATH
 CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
 CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
 CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
 CONFIG_OMAP_USB2PHY2_HOST
 CONFIG_OMAP_USB3PHY1_HOST
 CONFIG_OMAP_USB_PHY
 CONFIG_ORIGEN
 CONFIG_OS1_ENV_ADDR
 CONFIG_OS2_ENV_ADDR
 CONFIG_OTHBOOTARGS
 CONFIG_OVERWRITE_ETHADDR_ONCE
 CONFIG_PAGE_CNT_MASK
 CONFIG_PAGE_CNT_SHIFT
 CONFIG_PALMAS_AUDPWR
 CONFIG_PALMAS_POWER
 CONFIG_PALMAS_SMPS7_FPWM
 CONFIG_PALMAS_USB_SS_PWR
 CONFIG_PANIC_HANG
 CONFIG_PARAVIRT
 CONFIG_PB1000
 CONFIG_PB1100
 CONFIG_PB1500
 CONFIG_PB1X00
 CONFIG_PCA953X
 CONFIG_PCA9698
 CONFIG_PCI1
 CONFIG_PCI2
 CONFIG_PCIAUTO_SKIP_HOST_BRIDGE
 CONFIG_PCIE
 CONFIG_PCIE1
 CONFIG_PCIE2
 CONFIG_PCIE3
 CONFIG_PCIE4
 CONFIG_PCIE_IMX
 CONFIG_PCIE_IMX_PERST_GPIO
 CONFIG_PCIE_IMX_POWER_GPIO
 CONFIG_PCISLAVE
 CONFIG_PCIX_CHECK
 CONFIG_PCI_33M
 CONFIG_PCI_66M
 CONFIG_PCI_BOOTDELAY
 CONFIG_PCI_CLK_FREQ
 CONFIG_PCI_CONFIG_HOST_BRIDGE
 CONFIG_PCI_EHCI_DEVICE
 CONFIG_PCI_EHCI_DEVNO
 CONFIG_PCI_ENUM_ONLY
 CONFIG_PCI_FIXUP_DEV
 CONFIG_PCI_GT64120
 CONFIG_PCI_INDIRECT_BRIDGE
 CONFIG_PCI_IO_BUS
 CONFIG_PCI_IO_PHYS
 CONFIG_PCI_IO_SIZE
 CONFIG_PCI_MEM_BUS
 CONFIG_PCI_MEM_PHYS
 CONFIG_PCI_MEM_SIZE
 CONFIG_PCI_MSC01
 CONFIG_PCI_MVEBU
 CONFIG_PCI_NOSCAN
 CONFIG_PCI_OHCI
 CONFIG_PCI_OHCI_DEVNO
 CONFIG_PCI_PREF_BUS
 CONFIG_PCI_PREF_PHYS
 CONFIG_PCI_PREF_SIZE
 CONFIG_PCI_SCAN_SHOW
 CONFIG_PCI_SKIP_HOST_BRIDGE
 CONFIG_PCI_SYS_BUS
 CONFIG_PCI_SYS_PHYS
 CONFIG_PCI_SYS_SIZE
 CONFIG_PCMCIA
 CONFIG_PCMCIA_SLOT_A
 CONFIG_PCMCIA_SLOT_B
 CONFIG_PCNET
 CONFIG_PCNET_79C973
 CONFIG_PCNET_79C975
 CONFIG_PEN_ADDR_BIG_ENDIAN
 CONFIG_PERIF1_FREQ
 CONFIG_PERIF2_FREQ
 CONFIG_PERIF3_FREQ
 CONFIG_PERIF4_FREQ
 CONFIG_PHYSMEM
 CONFIG_PHY_ADDR
 CONFIG_PHY_BASE_ADR
 CONFIG_PHY_BCM5421S
 CONFIG_PHY_ET1011C_TX_CLK_FIX
 CONFIG_PHY_ID
 CONFIG_PHY_INTERFACE_MODE
 CONFIG_PHY_IRAM_BASE
 CONFIG_PHY_M88E1111
 CONFIG_PHY_MAX_ADDR
 CONFIG_PHY_MODE_NEED_CHANGE
 CONFIG_PHY_RESET
 CONFIG_PHY_RESET_DELAY
 CONFIG_PICOSAM
 CONFIG_PIGGY_MAC_ADRESS_OFFSET
 CONFIG_PIXIS_BRDCFG0_SPI
 CONFIG_PIXIS_BRDCFG0_USB2
 CONFIG_PIXIS_BRDCFG1_AUDCLK_11
 CONFIG_PIXIS_BRDCFG1_AUDCLK_12
 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK
 CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK
 CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI
 CONFIG_PIXIS_BRDCFG1_TDM
 CONFIG_PIXIS_SGMII_CMD
 CONFIG_PL010_SERIAL
 CONFIG_PL011_CLOCK
 CONFIG_PL011_SERIAL
 CONFIG_PL011_SERIAL_RLCR
 CONFIG_PL01X_SERIAL
 CONFIG_PL01x_PORTS
 CONFIG_PLATFORM_ENV_SETTINGS
 CONFIG_PLATINUM_BOARD
 CONFIG_PLATINUM_CPU
 CONFIG_PLATINUM_PICON
 CONFIG_PLATINUM_PROJECT
 CONFIG_PLATINUM_TITANIUM
 CONFIG_PLL1_CLK_FREQ
 CONFIG_PLL1_DIV2_CLK_FREQ
 CONFIG_PM
 CONFIG_PM9261
 CONFIG_PM9263
 CONFIG_PM9G45
 CONFIG_PMC_BR_PRELIM
 CONFIG_PMC_OR_PRELIM
 CONFIG_PMECC_CAP
 CONFIG_PMECC_SECTOR_SIZE
 CONFIG_PME_PLAT_CLK_DIV
 CONFIG_PMU
 CONFIG_PMW_BASE
 CONFIG_PM_SLEEP
 CONFIG_POST
 CONFIG_POSTBOOTMENU
 CONFIG_POST_ALT_LIST
 CONFIG_POST_BSPEC1
 CONFIG_POST_BSPEC2
 CONFIG_POST_BSPEC3
 CONFIG_POST_BSPEC4
 CONFIG_POST_BSPEC5
 CONFIG_POST_EXTERNAL_WORD_FUNCS
 CONFIG_POST_SKIP_ENV_FLAGS
 CONFIG_POST_STD_LIST
 CONFIG_POST_UART
 CONFIG_POST_WATCHDOG
 CONFIG_POWER
 CONFIG_POWER_FSL
 CONFIG_POWER_FSL_MC13892
 CONFIG_POWER_FSL_MC34704
 CONFIG_POWER_HI6553
 CONFIG_POWER_I2C
 CONFIG_POWER_LTC3676
 CONFIG_POWER_LTC3676_I2C_ADDR
 CONFIG_POWER_MAX77696
 CONFIG_POWER_MAX77696_I2C_ADDR
 CONFIG_POWER_PFUZE100
 CONFIG_POWER_PFUZE100_I2C_ADDR
 CONFIG_POWER_PFUZE3000
 CONFIG_POWER_PFUZE3000_I2C_ADDR
 CONFIG_POWER_SPI
 CONFIG_POWER_TPS62362
 CONFIG_POWER_TPS65090_EC
 CONFIG_POWER_TPS65217
 CONFIG_POWER_TPS65218
 CONFIG_POWER_TPS65910
 CONFIG_PPC64BRIDGE
 CONFIG_PPC_CLUSTER_START
 CONFIG_PPC_SPINTABLE_COMPATIBLE
 CONFIG_PQ_MDS_PIB
 CONFIG_PQ_MDS_PIB_ATM
 CONFIG_PRAM
 CONFIG_PREBOOT
 CONFIG_PRINTK
 CONFIG_PROC_FS
 CONFIG_PROFILE_ALL_BRANCHES
 CONFIG_PROFILING
 CONFIG_PROG_FDT1
 CONFIG_PROG_FDT2
 CONFIG_PROG_OS1
 CONFIG_PROG_OS2
 CONFIG_PROG_UBOOT1
 CONFIG_PROG_UBOOT2
 CONFIG_PROOF_POINTS
 CONFIG_PRPMC_PCI_ALIAS
 CONFIG_PS2KBD
 CONFIG_PS2MULT
 CONFIG_PS2MULT_DELAY
 CONFIG_PS2SERIAL
 CONFIG_PSRAM_SCFG
 CONFIG_PWM
 CONFIG_PWM_IMX
 CONFIG_PXA_LCD
 CONFIG_PXA_MMC_GENERIC
 CONFIG_PXA_PWR_I2C
 CONFIG_PXA_STD_I2C
 CONFIG_PXA_VGA
 CONFIG_PXA_VIDEO
 CONFIG_P_CLK_FREQ
 CONFIG_QBMAN_CLK_DIV
 CONFIG_QE
 CONFIG_QEMU_MIPS
 CONFIG_QIXIS_I2C_ACCESS
 CONFIG_QSPI
 CONFIG_QSPI_QUAD_SUPPORT
 CONFIG_QSPI_SEL_GPIO
 CONFIG_QUOTA
 CONFIG_R0P7734
 CONFIG_R2DPLUS
 CONFIG_R7780MP
 CONFIG_R8A66597_BASE_ADDR
 CONFIG_R8A66597_ENDIAN
 CONFIG_R8A66597_LDRV
 CONFIG_R8A66597_XTAL
 CONFIG_R8A7740
 CONFIG_R8A7790
 CONFIG_R8A7791
 CONFIG_R8A7792
 CONFIG_R8A7793
 CONFIG_R8A7794
 CONFIG_RAMBOOT
 CONFIG_RAMBOOTCOMMAND
 CONFIG_RAMBOOTCOMMAND_TFTP
 CONFIG_RAMBOOT_NAND
 CONFIG_RAMBOOT_PBL
 CONFIG_RAMBOOT_SDCARD
 CONFIG_RAMBOOT_SPIFLASH
 CONFIG_RAMBOOT_TEXT_BASE
 CONFIG_RAMDISKFILE
 CONFIG_RAMDISK_ADDR
 CONFIG_RAMDISK_BOOT
 CONFIG_RAM_BOOT
 CONFIG_RAM_BOOT_PHYS
 CONFIG_RCAR_BOARD_STRING
 CONFIG_RD_LVL
 CONFIG_REALMODE_DEBUG
 CONFIG_RED_LED
 CONFIG_REFCLK_FREQ
 CONFIG_REG
 CONFIG_REG_0
 CONFIG_REG_1_BASE
 CONFIG_REG_2
 CONFIG_REG_3
 CONFIG_REG_8
 CONFIG_REG_APER_SIZE
 CONFIG_REMAKE_ELF
 CONFIG_REQ
 CONFIG_RESERVED_01_BASE
 CONFIG_RESERVED_02_BASE
 CONFIG_RESERVED_03_BASE
 CONFIG_RESERVED_04_BASE
 CONFIG_RESET
 CONFIG_RESET_PHY_R
 CONFIG_RESET_TO_RETRY
 CONFIG_RESET_VECTOR_ADDRESS
 CONFIG_RESTORE_FLASH
 CONFIG_RES_BLOCK_SIZE
 CONFIG_REV1
 CONFIG_REV3
 CONFIG_REVISION_TAG
 CONFIG_RFSPART
 CONFIG_RIO
 CONFIG_RMII
 CONFIG_RMOBILE_BOARD_STRING
 CONFIG_RMSTP0_ENA
 CONFIG_RMSTP10_ENA
 CONFIG_RMSTP11_ENA
 CONFIG_RMSTP1_ENA
 CONFIG_RMSTP2_ENA
 CONFIG_RMSTP3_ENA
 CONFIG_RMSTP4_ENA
 CONFIG_RMSTP5_ENA
 CONFIG_RMSTP6_ENA
 CONFIG_RMSTP7_ENA
 CONFIG_RMSTP8_ENA
 CONFIG_RMSTP9_ENA
 CONFIG_ROCKCHIP_CHIP_TAG
 CONFIG_ROCKCHIP_MAX_INIT_SIZE
 CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
 CONFIG_ROCKCHIP_USB2_PHY
 CONFIG_ROM_STUBS
 CONFIG_ROOTFS_OFFSET
 CONFIG_ROOTPATH
 CONFIG_RSK7203
 CONFIG_RSK7264
 CONFIG_RSK7269
 CONFIG_RTC_DS1337
 CONFIG_RTC_DS1337_NOOSC
 CONFIG_RTC_DS1338
 CONFIG_RTC_DS1339_TCR_VAL
 CONFIG_RTC_DS1374
 CONFIG_RTC_DS1388
 CONFIG_RTC_DS1388_TCR_VAL
 CONFIG_RTC_DS3231
 CONFIG_RTC_FTRTC010
 CONFIG_RTC_IMXDI
 CONFIG_RTC_INTERNAL
 CONFIG_RTC_M41T11
 CONFIG_RTC_M41T60
 CONFIG_RTC_M41T62
 CONFIG_RTC_MC13XXX
 CONFIG_RTC_MC146818
 CONFIG_RTC_MCFRRTC
 CONFIG_RTC_MCP79411
 CONFIG_RTC_MV
 CONFIG_RTC_MXS
 CONFIG_RTC_PCF8563
 CONFIG_RTC_PT7C4338
 CONFIG_RTC_RX8025
 CONFIG_RUN_FROM_DDR0
 CONFIG_RUN_FROM_DDR1
 CONFIG_RUN_FROM_IRAM_ONLY
 CONFIG_RX_DESCR_NUM
 CONFIG_S32V234
 CONFIG_S5P
 CONFIG_S5PC100
 CONFIG_S5PC110
 CONFIG_S5P_PA_SYSRAM
 CONFIG_S6E63D6
 CONFIG_S6E8AX0
 CONFIG_SABRELITE
 CONFIG_SAMA5D3_LCD_BASE
 CONFIG_SAMSUNG
 CONFIG_SAMSUNG_ONENAND
 CONFIG_SANDBOX_ARCH
 CONFIG_SANDBOX_BIG_ENDIAN
 CONFIG_SANDBOX_SDL
 CONFIG_SANDBOX_SPI_MAX_BUS
 CONFIG_SANDBOX_SPI_MAX_CS
 CONFIG_SAR2_REG
 CONFIG_SAR_REG
 CONFIG_SATA1
 CONFIG_SATA2
 CONFIG_SATA_ULI5288
 CONFIG_SBC8349
 CONFIG_SBC8548
 CONFIG_SBC8641D
 CONFIG_SCF0403_LCD
 CONFIG_SCIF
 CONFIG_SCIF_A
 CONFIG_SCIF_EXT_CLOCK
 CONFIG_SCIF_USE_EXT_CLK
 CONFIG_SCSI_AHCI
 CONFIG_SCSI_AHCI_PLAT
 CONFIG_SCSI_DEV_LIST
 CONFIG_SC_TIMER_CLK
 CONFIG_SDCARD
 CONFIG_SDRAM_OFFSET_FOR_RT
 CONFIG_SD_BOOT_QSPI
 CONFIG_SECBOOT
 CONFIG_SECURE_BL1_ONLY
 CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
 CONFIG_SECURITY
 CONFIG_SEC_DEQ_TIMEOUT
 CONFIG_SEC_FW_SIZE
 CONFIG_SERIAL0
 CONFIG_SERIAL1
 CONFIG_SERIAL2
 CONFIG_SERIAL3
 CONFIG_SERIAL_BOOT
 CONFIG_SERIAL_FLASH
 CONFIG_SERIAL_HW_FLOW_CONTROL
 CONFIG_SERIAL_MULTI
 CONFIG_SERIAL_SOFTWARE_FIFO
 CONFIG_SERIAL_TAG
 CONFIG_SERIRQ_CONTINUOUS_MODE
 CONFIG_SERVERIP
 CONFIG_SETUP_INITRD_TAG
 CONFIG_SETUP_MEMORY_TAGS
 CONFIG_SET_BIST
 CONFIG_SET_BOOTARGS
 CONFIG_SET_DFU_ALT_BUF_LEN
 CONFIG_SET_DFU_ALT_INFO
 CONFIG_SFIO
 CONFIG_SF_DATAFLASH
 CONFIG_SF_DEFAULT_BUS
 CONFIG_SF_DEFAULT_CS
 CONFIG_SF_DEFAULT_MODE
 CONFIG_SF_DEFAULT_SPEED
 CONFIG_SGI_IP28
 CONFIG_SH4_PCI
 CONFIG_SH73A0
 CONFIG_SH7751_PCI
 CONFIG_SH7752EVB
 CONFIG_SH7753EVB
 CONFIG_SH7757LCR
 CONFIG_SH7757LCR_DDR_ECC
 CONFIG_SH7763RDP
 CONFIG_SH7780_PCI
 CONFIG_SH7780_PCI_BAR
 CONFIG_SH7780_PCI_LAR
 CONFIG_SH7780_PCI_LSR
 CONFIG_SH7785LCR
 CONFIG_SHARP_LM8V31
 CONFIG_SHARP_LQ035Q7DH06
 CONFIG_SHEEVA_88SV131
 CONFIG_SHEEVA_88SV331xV5
 CONFIG_SHELL
 CONFIG_SHMIN
 CONFIG_SHOW_ACTIVITY
 CONFIG_SHOW_BOOT_PROGRESS
 CONFIG_SH_CMT_CLK_FREQ
 CONFIG_SH_DSP
 CONFIG_SH_ETHER
 CONFIG_SH_ETHER_ALIGNE_SIZE
 CONFIG_SH_ETHER_BASE_ADDR
 CONFIG_SH_ETHER_CACHE_INVALIDATE
 CONFIG_SH_ETHER_CACHE_WRITEBACK
 CONFIG_SH_ETHER_PHY_ADDR
 CONFIG_SH_ETHER_PHY_MODE
 CONFIG_SH_ETHER_SH7734_MII
 CONFIG_SH_ETHER_USE_GETHER
 CONFIG_SH_ETHER_USE_PORT
 CONFIG_SH_GPIO_PFC
 CONFIG_SH_I2C_8BIT
 CONFIG_SH_I2C_CLOCK
 CONFIG_SH_I2C_DATA_HIGH
 CONFIG_SH_I2C_DATA_LOW
 CONFIG_SH_MMCIF
 CONFIG_SH_MMCIF_ADDR
 CONFIG_SH_MMCIF_CLK
 CONFIG_SH_QSPI
 CONFIG_SH_QSPI_BASE
 CONFIG_SH_SCIF_CLK_FREQ
 CONFIG_SH_SDHI_FREQ
 CONFIG_SH_SDRAM_OFFSET
 CONFIG_SH_SPI
 CONFIG_SH_SPI_BASE
 CONFIG_SH_TMU_CLK_FREQ
 CONFIG_SIEMENS_DRACO
 CONFIG_SIEMENS_MACH_TYPE
 CONFIG_SIEMENS_PXM2
 CONFIG_SIEMENS_RUT
 CONFIG_SIMU
 CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
 CONFIG_SKIP_LOWLEVEL_INIT
 CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 CONFIG_SKIP_TRUNOFF_WATCHDOG
 CONFIG_SLIC
 CONFIG_SLTTMR
 CONFIG_SMC91111
 CONFIG_SMC91111_BASE
 CONFIG_SMC91111_EXT_PHY
 CONFIG_SMC_AUTONEG_TIMEOUT
 CONFIG_SMC_USE_32_BIT
 CONFIG_SMC_USE_IOFUNCS
 CONFIG_SMDK5420
 CONFIG_SMDKC100
 CONFIG_SMDKV310
 CONFIG_SMP_PEN_ADDR
 CONFIG_SMSC_LPC47M
 CONFIG_SMSC_SIO1007
 CONFIG_SMSTP0_ENA
 CONFIG_SMSTP10_ENA
 CONFIG_SMSTP11_ENA
 CONFIG_SMSTP1_ENA
 CONFIG_SMSTP2_ENA
 CONFIG_SMSTP3_ENA
 CONFIG_SMSTP4_ENA
 CONFIG_SMSTP5_ENA
 CONFIG_SMSTP6_ENA
 CONFIG_SMSTP7_ENA
 CONFIG_SMSTP8_ENA
 CONFIG_SMSTP9_ENA
 CONFIG_SOCFPGA_VIRTUAL_TARGET
 CONFIG_SOCRATES
 CONFIG_SOC_AU1000
 CONFIG_SOC_AU1100
 CONFIG_SOC_AU1500
 CONFIG_SOC_AU1550
 CONFIG_SOC_AU1X00
 CONFIG_SOC_DA850
 CONFIG_SOC_DA8XX
 CONFIG_SOC_DM355
 CONFIG_SOC_DM365
 CONFIG_SOC_DM644X
 CONFIG_SOC_DM646X
 CONFIG_SOC_K2E
 CONFIG_SOC_K2G
 CONFIG_SOC_K2HK
 CONFIG_SOC_K2L
 CONFIG_SOC_KEYSTONE
 CONFIG_SOC_OMAP3430
 CONFIG_SOFT_I2C_GPIO_SCL
 CONFIG_SOFT_I2C_GPIO_SDA
 CONFIG_SOFT_I2C_READ_REPEATED_START
 CONFIG_SOURCE
 CONFIG_SPARSE_RCU_POINTER
 CONFIG_SPD_EEPROM
 CONFIG_SPEAR300
 CONFIG_SPEAR310
 CONFIG_SPEAR320
 CONFIG_SPEAR3XX
 CONFIG_SPEAR600
 CONFIG_SPEAR_BOOTSTRAPCFG
 CONFIG_SPEAR_BOOTSTRAPMASK
 CONFIG_SPEAR_BOOTSTRAPSHFT
 CONFIG_SPEAR_EMI
 CONFIG_SPEAR_EMIBASE
 CONFIG_SPEAR_ETHBASE
 CONFIG_SPEAR_GPIO
 CONFIG_SPEAR_HZ
 CONFIG_SPEAR_HZ_CLOCK
 CONFIG_SPEAR_MISCBASE
 CONFIG_SPEAR_MPMCBASE
 CONFIG_SPEAR_MPMCREGS
 CONFIG_SPEAR_NORNAND16BOOT
 CONFIG_SPEAR_NORNAND8BOOT
 CONFIG_SPEAR_NORNANDBOOT
 CONFIG_SPEAR_ONLYSNORBOOT
 CONFIG_SPEAR_RASBASE
 CONFIG_SPEAR_SYSCNTLBASE
 CONFIG_SPEAR_TIMERBASE
 CONFIG_SPEAR_UART48M
 CONFIG_SPEAR_UARTCLKMSK
 CONFIG_SPEAR_USBBOOT
 CONFIG_SPEAR_USBTTY
 CONFIG_SPI
 CONFIG_SPI_ADDR
 CONFIG_SPI_BOOTING
 CONFIG_SPI_CS_IS_VALID
 CONFIG_SPI_DATAFLASH_WRITE_VERIFY
 CONFIG_SPI_FLASH_ISSI
 CONFIG_SPI_FLASH_QUAD
 CONFIG_SPI_FLASH_SIZE
 CONFIG_SPI_HALF_DUPLEX
 CONFIG_SPI_IDLE_VAL
 CONFIG_SPI_LENGTH
 CONFIG_SPI_N25Q256A_RESET
 CONFIG_SPLASHIMAGE_GUARD
 CONFIG_SPLASH_SCREEN
 CONFIG_SPLASH_SCREEN_ALIGN
 CONFIG_SPLASH_SOURCE
 CONFIG_SPLL_FREQ
 CONFIG_SPL_
 CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 CONFIG_SPL_ATMEL_SIZE
 CONFIG_SPL_BOARD_LOAD_IMAGE
 CONFIG_SPL_BOOTROM_SAVE
 CONFIG_SPL_BOOT_DEVICE
 CONFIG_SPL_BSS_MAX_SIZE
 CONFIG_SPL_BSS_START_ADDR
 CONFIG_SPL_CMT
 CONFIG_SPL_CMT_DEBUG
 CONFIG_SPL_COMMON_INIT_DDR
 CONFIG_SPL_CONSOLE
 CONFIG_SPL_ETH_DEVICE
 CONFIG_SPL_FLUSH_IMAGE
 CONFIG_SPL_FRAMEWORK
 CONFIG_SPL_FSL_PBL
 CONFIG_SPL_FS_LOAD_ARGS_NAME
 CONFIG_SPL_FS_LOAD_KERNEL_NAME
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
 CONFIG_SPL_GD_ADDR
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 CONFIG_SPL_INIT_MINIMAL
 CONFIG_SPL_JR0_LIODN_NS
 CONFIG_SPL_JR0_LIODN_S
 CONFIG_SPL_LOAD_FIT_ADDRESS
 CONFIG_SPL_MAX_FOOTPRINT
 CONFIG_SPL_MAX_PEB_SIZE
 CONFIG_SPL_MAX_SIZE
 CONFIG_SPL_MMC_BOOT
 CONFIG_SPL_MMC_LOAD
 CONFIG_SPL_MMC_MINIMAL
 CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
 CONFIG_SPL_MXS_PSWITCH_WAIT
 CONFIG_SPL_NAND_BASE
 CONFIG_SPL_NAND_BOOT
 CONFIG_SPL_NAND_DRIVERS
 CONFIG_SPL_NAND_ECC
 CONFIG_SPL_NAND_INIT
 CONFIG_SPL_NAND_LOAD
 CONFIG_SPL_NAND_MINIMAL
 CONFIG_SPL_NAND_RAW_ONLY
 CONFIG_SPL_NAND_SOFTECC
 CONFIG_SPL_NAND_WORKSPACE
 CONFIG_SPL_NO_CPU_SUPPORT_CODE
 CONFIG_SPL_PAD_TO
 CONFIG_SPL_PANIC_ON_RAW_IMAGE
 CONFIG_SPL_PBL_PAD
 CONFIG_SPL_PPAACT_ADDR
 CONFIG_SPL_RELOC_MALLOC_ADDR
 CONFIG_SPL_RELOC_MALLOC_SIZE
 CONFIG_SPL_RELOC_STACK
 CONFIG_SPL_RELOC_STACK_SIZE
 CONFIG_SPL_RELOC_TEXT_BASE
 CONFIG_SPL_SATA_BOOT_DEVICE
 CONFIG_SPL_SIZE
 CONFIG_SPL_SKIP_RELOCATE
 CONFIG_SPL_SPAACT_ADDR
 CONFIG_SPL_SPI_BOOT
 CONFIG_SPL_SPI_FLASH_MINIMAL
 CONFIG_SPL_SPI_LOAD
 CONFIG_SPL_STACK
 CONFIG_SPL_STACK_ADDR
 CONFIG_SPL_STACK_SIZE
 CONFIG_SPL_START_S_PATH
 CONFIG_SPL_TARGET
 CONFIG_SPL_TEXT_BASE
 CONFIG_SPL_UBI
 CONFIG_SPL_UBI_INFO_ADDR
 CONFIG_SPL_UBI_LEB_START
 CONFIG_SPL_UBI_LOAD_ARGS_ID
 CONFIG_SPL_UBI_LOAD_KERNEL_ID
 CONFIG_SPL_UBI_LOAD_MONITOR_ID
 CONFIG_SPL_UBI_MAX_PEBS
 CONFIG_SPL_UBI_MAX_PEB_SIZE
 CONFIG_SPL_UBI_MAX_VOL_LEBS
 CONFIG_SPL_UBI_PEB_OFFSET
 CONFIG_SPL_UBI_VID_OFFSET
 CONFIG_SPL_UBI_VOL_IDS
 CONFIG_SPL_UBOOT_KEY_HASH
 CONFIG_SRAM_BASE
 CONFIG_SRAM_SIZE
 CONFIG_SRIO1
 CONFIG_SRIO2
 CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1
 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2
 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
 CONFIG_SRIO_PCIE_BOOT_MASTER
 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK
 CONFIG_SRIO_PCIE_BOOT_SLAVE
 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
 CONFIG_SSD_BR_PRELIM
 CONFIG_SSD_OR_PRELIM
 CONFIG_SSE2
 CONFIG_SSI1_FREQ
 CONFIG_SSI2_FREQ
 CONFIG_SSP1_BASE
 CONFIG_SSP2_BASE
 CONFIG_SSP3_BASE
 CONFIG_STACKBASE
 CONFIG_STANDALONE_LOAD_ADDR
 CONFIG_STATIC_BOARD_REV
 CONFIG_STATIC_RELA
 CONFIG_STD_DEVICES_SETTINGS
 CONFIG_STM32F4DISCOVERY
 CONFIG_STM32_FLASH
 CONFIG_STM32_GPIO
 CONFIG_STM32_HSE_HZ
 CONFIG_STM32_HZ
 CONFIG_STM32_SERIAL
 CONFIG_STMARK2
 CONFIG_STRIDER
 CONFIG_STRIDER_CON
 CONFIG_STRIDER_CON_DP
 CONFIG_STRIDER_CPU
 CONFIG_STRIDER_CPU_DP
 CONFIG_STRIDER_FANS
 CONFIG_STUART
 CONFIG_STV0991
 CONFIG_STV0991_HZ
 CONFIG_STV0991_HZ_CLOCK
 CONFIG_ST_SMI
 CONFIG_SUNXI_AHCI
 CONFIG_SUNXI_EMAC
 CONFIG_SUNXI_GPIO
 CONFIG_SUNXI_MAX_FB_SIZE
 CONFIG_SUNXI_USB_PHYS
 CONFIG_SUPERH_ON_CHIP_R8A66597
 CONFIG_SUPPORT_EMMC_BOOT
 CONFIG_SUPPORT_EMMC_RPMB
 CONFIG_SUPPORT_RAW_INITRD
 CONFIG_SUPPORT_VFAT
 CONFIG_SUVD3
 CONFIG_SXNI855T
 CONFIG_SYSCOUNTER_TIMER
 CONFIG_SYSFLAGS_ADDR
 CONFIG_SYSFS
 CONFIG_SYSMGR_ISWGRP_HANDOFF
 CONFIG_SYSTEMACE
 CONFIG_SYS_33MHZ
 CONFIG_SYS_64BIT
 CONFIG_SYS_64BIT_LBA
 CONFIG_SYS_64BIT_VSPRINTF
 CONFIG_SYS_66MHZ
 CONFIG_SYS_8313ERDB_BROKEN_PMC
 CONFIG_SYS_83XX_DDR_USES_CS0
 CONFIG_SYS_ACR_APARK
 CONFIG_SYS_ACR_PARKM
 CONFIG_SYS_ACR_PIPE_DEP
 CONFIG_SYS_ACR_RPTCNT
 CONFIG_SYS_ADDRESS_MAP_A
 CONFIG_SYS_ADV7611_I2C
 CONFIG_SYS_ALT_BOOT
 CONFIG_SYS_ALT_FLASH
 CONFIG_SYS_ALT_MEMTEST
 CONFIG_SYS_AMASK0
 CONFIG_SYS_AMASK0_FINAL
 CONFIG_SYS_AMASK1
 CONFIG_SYS_AMASK1_FINAL
 CONFIG_SYS_AMASK2
 CONFIG_SYS_AMASK2_FINAL
 CONFIG_SYS_AMASK3
 CONFIG_SYS_AMASK3_FINAL
 CONFIG_SYS_AMASK4
 CONFIG_SYS_AMASK5
 CONFIG_SYS_AMASK6
 CONFIG_SYS_AMASK7
 CONFIG_SYS_APP1_BASE
 CONFIG_SYS_APP1_SIZE
 CONFIG_SYS_APP2_BASE
 CONFIG_SYS_APP2_SIZE
 CONFIG_SYS_ARCH_TIMER
 CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 CONFIG_SYS_AT91_CPU_NAME
 CONFIG_SYS_AT91_MAIN_CLOCK
 CONFIG_SYS_AT91_PLLA
 CONFIG_SYS_AT91_PLLB
 CONFIG_SYS_AT91_SLOW_CLOCK
 CONFIG_SYS_ATA_ALT_OFFSET
 CONFIG_SYS_ATA_BASE_ADDR
 CONFIG_SYS_ATA_DATA_OFFSET
 CONFIG_SYS_ATA_IDE0_OFFSET
 CONFIG_SYS_ATA_IDE1_OFFSET
 CONFIG_SYS_ATA_PORT_ADDR
 CONFIG_SYS_ATA_REG_OFFSET
 CONFIG_SYS_ATA_STRIDE
 CONFIG_SYS_ATI_REV_A11
 CONFIG_SYS_ATI_REV_A12
 CONFIG_SYS_ATI_REV_A13
 CONFIG_SYS_ATI_REV_ID_MASK
 CONFIG_SYS_ATMEL_BASE
 CONFIG_SYS_ATMEL_BOOT
 CONFIG_SYS_ATMEL_CPU_NAME
 CONFIG_SYS_ATMEL_REGION
 CONFIG_SYS_ATMEL_SECT
 CONFIG_SYS_ATMEL_SECTSZ
 CONFIG_SYS_ATMEL_TOTALSECT
 CONFIG_SYS_AUTOLOAD
 CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 CONFIG_SYS_AUXCORE_BOOTDATA
 CONFIG_SYS_BARGSIZE
 CONFIG_SYS_BAUDRATE_TABLE
 CONFIG_SYS_BCSR
 CONFIG_SYS_BCSR_ADDR
 CONFIG_SYS_BCSR_BASE
 CONFIG_SYS_BCSR_BASE_PHYS
 CONFIG_SYS_BCSR_SIZE
 CONFIG_SYS_BD_REV
 CONFIG_SYS_BFTIC3_BASE
 CONFIG_SYS_BFTIC3_SIZE
 CONFIG_SYS_BITBANG_PHY_PORT
 CONFIG_SYS_BITBANG_PHY_PORTS
 CONFIG_SYS_BLACK_IN_WRITE
 CONFIG_SYS_BMAN_CENA_BASE
 CONFIG_SYS_BMAN_CENA_SIZE
 CONFIG_SYS_BMAN_CINH_BASE
 CONFIG_SYS_BMAN_CINH_SIZE
 CONFIG_SYS_BMAN_MEM_BASE
 CONFIG_SYS_BMAN_MEM_PHYS
 CONFIG_SYS_BMAN_MEM_SIZE
 CONFIG_SYS_BMAN_NUM_PORTALS
 CONFIG_SYS_BMAN_SP_CENA_SIZE
 CONFIG_SYS_BMAN_SP_CINH_SIZE
 CONFIG_SYS_BMAN_SWP_ISDR_REG
 CONFIG_SYS_BOARD_NAME
 CONFIG_SYS_BOARD_OMAP3_HA
 CONFIG_SYS_BOARD_VERSION
 CONFIG_SYS_BOOK3E_HV
 CONFIG_SYS_BOOTCOUNT_ADDR
 CONFIG_SYS_BOOTCOUNT_BE
 CONFIG_SYS_BOOTCOUNT_LE
 CONFIG_SYS_BOOTCOUNT_SINGLEWORD
 CONFIG_SYS_BOOTFILE_PREFIX
 CONFIG_SYS_BOOTMAPSZ
 CONFIG_SYS_BOOTM_LEN
 CONFIG_SYS_BOOTPARAMS_LEN
 CONFIG_SYS_BOOTSZ
 CONFIG_SYS_BOOT_BLOCK
 CONFIG_SYS_BOOT_GET_CMDLINE
 CONFIG_SYS_BOOT_GET_KBD
 CONFIG_SYS_BOOT_RAMDISK_HIGH
 CONFIG_SYS_BR0_64M
 CONFIG_SYS_BR0_8M
 CONFIG_SYS_BR6_64M
 CONFIG_SYS_BR6_8M
 CONFIG_SYS_BUSCLK
 CONFIG_SYS_CACHELINE_SHIFT
 CONFIG_SYS_CACHE_ACR0
 CONFIG_SYS_CACHE_ACR1
 CONFIG_SYS_CACHE_ACR2
 CONFIG_SYS_CACHE_ACR3
 CONFIG_SYS_CACHE_ACR4
 CONFIG_SYS_CACHE_ACR5
 CONFIG_SYS_CACHE_ACR6
 CONFIG_SYS_CACHE_ACR7
 CONFIG_SYS_CACHE_DCACR
 CONFIG_SYS_CACHE_ICACR
 CONFIG_SYS_CACHE_STASHING
 CONFIG_SYS_CADMUS_BASE_REG
 CONFIG_SYS_CBSIZE
 CONFIG_SYS_CCCR
 CONFIG_SYS_CCSRBAR
 CONFIG_SYS_CCSRBAR_PHYS
 CONFIG_SYS_CCSRBAR_PHYS_HIGH
 CONFIG_SYS_CCSRBAR_PHYS_LOW
 CONFIG_SYS_CCSR_DEFAULT_DBATL
 CONFIG_SYS_CCSR_DEFAULT_DBATU
 CONFIG_SYS_CCSR_DEFAULT_IBATL
 CONFIG_SYS_CCSR_DEFAULT_IBATU
 CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 CONFIG_SYS_CFI_FLASH_CONFIG_REGS
 CONFIG_SYS_CFI_FLASH_STATUS_POLL
 CONFIG_SYS_CF_BASE
 CONFIG_SYS_CF_INTC_REG1
 CONFIG_SYS_CH7301_I2C
 CONFIG_SYS_CKEN
 CONFIG_SYS_CLK
 CONFIG_SYS_CLKTL_CBCDR
 CONFIG_SYS_CLK_100
 CONFIG_SYS_CLK_100_DDR_100
 CONFIG_SYS_CLK_100_DDR_133
 CONFIG_SYS_CLK_DIV
 CONFIG_SYS_CLK_FREQ_C100
 CONFIG_SYS_CLK_FREQ_C110
 CONFIG_SYS_CMD_CONFIGURE
 CONFIG_SYS_CMD_EL
 CONFIG_SYS_CMD_IAS
 CONFIG_SYS_CMD_INT
 CONFIG_SYS_CMD_SUSPEND
 CONFIG_SYS_CMXFCR_MASK1
 CONFIG_SYS_CMXFCR_MASK2
 CONFIG_SYS_CMXFCR_MASK3
 CONFIG_SYS_CMXFCR_VALUE1
 CONFIG_SYS_CMXFCR_VALUE2
 CONFIG_SYS_CMXFCR_VALUE3
 CONFIG_SYS_CORE_SRAM
 CONFIG_SYS_CORE_SRAM_SIZE
 CONFIG_SYS_CORTEX_R4
 CONFIG_SYS_CORTINA_FW_IN_MMC
 CONFIG_SYS_CORTINA_FW_IN_NAND
 CONFIG_SYS_CORTINA_FW_IN_NOR
 CONFIG_SYS_CORTINA_FW_IN_REMOTE
 CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 CONFIG_SYS_CPC_REINIT_F
 CONFIG_SYS_CPLD_AMASK
 CONFIG_SYS_CPLD_BASE
 CONFIG_SYS_CPLD_BASE_PHYS
 CONFIG_SYS_CPLD_CSOR
 CONFIG_SYS_CPLD_CSPR
 CONFIG_SYS_CPLD_CSPR_EXT
 CONFIG_SYS_CPLD_FTIM0
 CONFIG_SYS_CPLD_FTIM1
 CONFIG_SYS_CPLD_FTIM2
 CONFIG_SYS_CPLD_FTIM3
 CONFIG_SYS_CPLD_SIZE
 CONFIG_SYS_CPMFCR_RAMTYPE
 CONFIG_SYS_CPM_INTERRUPT
 CONFIG_SYS_CPRI
 CONFIG_SYS_CPRI_CLK
 CONFIG_SYS_CPUSPEED
 CONFIG_SYS_CPU_CLK
 CONFIG_SYS_CS0_BASE
 CONFIG_SYS_CS0_CTRL
 CONFIG_SYS_CS0_FTIM0
 CONFIG_SYS_CS0_FTIM1
 CONFIG_SYS_CS0_FTIM2
 CONFIG_SYS_CS0_FTIM3
 CONFIG_SYS_CS0_MASK
 CONFIG_SYS_CS0_SIZE
 CONFIG_SYS_CS1_BASE
 CONFIG_SYS_CS1_CTRL
 CONFIG_SYS_CS1_FLASH_BASE
 CONFIG_SYS_CS1_FTIM0
 CONFIG_SYS_CS1_FTIM1
 CONFIG_SYS_CS1_FTIM2
 CONFIG_SYS_CS1_FTIM3
 CONFIG_SYS_CS1_MASK
 CONFIG_SYS_CS2_BASE
 CONFIG_SYS_CS2_CTRL
 CONFIG_SYS_CS2_FLASH_BASE
 CONFIG_SYS_CS2_FTIM0
 CONFIG_SYS_CS2_FTIM1
 CONFIG_SYS_CS2_FTIM2
 CONFIG_SYS_CS2_FTIM3
 CONFIG_SYS_CS2_MASK
 CONFIG_SYS_CS3_BASE
 CONFIG_SYS_CS3_CTRL
 CONFIG_SYS_CS3_FLASH_BASE
 CONFIG_SYS_CS3_FTIM0
 CONFIG_SYS_CS3_FTIM1
 CONFIG_SYS_CS3_FTIM2
 CONFIG_SYS_CS3_FTIM3
 CONFIG_SYS_CS3_MASK
 CONFIG_SYS_CS4_BASE
 CONFIG_SYS_CS4_CTRL
 CONFIG_SYS_CS4_FLASH_BASE
 CONFIG_SYS_CS4_FTIM0
 CONFIG_SYS_CS4_FTIM1
 CONFIG_SYS_CS4_FTIM2
 CONFIG_SYS_CS4_FTIM3
 CONFIG_SYS_CS4_MASK
 CONFIG_SYS_CS5_BASE
 CONFIG_SYS_CS5_CTRL
 CONFIG_SYS_CS5_FLASH_BASE
 CONFIG_SYS_CS5_FTIM0
 CONFIG_SYS_CS5_FTIM1
 CONFIG_SYS_CS5_FTIM2
 CONFIG_SYS_CS5_FTIM3
 CONFIG_SYS_CS5_MASK
 CONFIG_SYS_CS6_BASE
 CONFIG_SYS_CS6_CTRL
 CONFIG_SYS_CS6_FTIM0
 CONFIG_SYS_CS6_FTIM1
 CONFIG_SYS_CS6_FTIM2
 CONFIG_SYS_CS6_FTIM3
 CONFIG_SYS_CS6_MASK
 CONFIG_SYS_CS7_BASE
 CONFIG_SYS_CS7_CTRL
 CONFIG_SYS_CS7_FTIM0
 CONFIG_SYS_CS7_FTIM1
 CONFIG_SYS_CS7_FTIM2
 CONFIG_SYS_CS7_FTIM3
 CONFIG_SYS_CS7_MASK
 CONFIG_SYS_CSOR0
 CONFIG_SYS_CSOR0_EXT
 CONFIG_SYS_CSOR1
 CONFIG_SYS_CSOR1_EXT
 CONFIG_SYS_CSOR2
 CONFIG_SYS_CSOR2_EXT
 CONFIG_SYS_CSOR3
 CONFIG_SYS_CSOR3_EXT
 CONFIG_SYS_CSOR4
 CONFIG_SYS_CSOR4_EXT
 CONFIG_SYS_CSOR5
 CONFIG_SYS_CSOR5_EXT
 CONFIG_SYS_CSOR6
 CONFIG_SYS_CSOR6_EXT
 CONFIG_SYS_CSOR7
 CONFIG_SYS_CSOR7_EXT
 CONFIG_SYS_CSPR0
 CONFIG_SYS_CSPR0_EXT
 CONFIG_SYS_CSPR0_FINAL
 CONFIG_SYS_CSPR1
 CONFIG_SYS_CSPR1_EXT
 CONFIG_SYS_CSPR1_FINAL
 CONFIG_SYS_CSPR2
 CONFIG_SYS_CSPR2_EXT
 CONFIG_SYS_CSPR2_FINAL
 CONFIG_SYS_CSPR3
 CONFIG_SYS_CSPR3_EXT
 CONFIG_SYS_CSPR3_FINAL
 CONFIG_SYS_CSPR4
 CONFIG_SYS_CSPR4_EXT
 CONFIG_SYS_CSPR5
 CONFIG_SYS_CSPR5_EXT
 CONFIG_SYS_CSPR6
 CONFIG_SYS_CSPR6_EXT
 CONFIG_SYS_CSPR7
 CONFIG_SYS_CSPR7_EXT
 CONFIG_SYS_DA850_CS2CFG
 CONFIG_SYS_DA850_CS3CFG
 CONFIG_SYS_DA850_DDR2_DDRPHYCR
 CONFIG_SYS_DA850_DDR2_PBBPR
 CONFIG_SYS_DA850_DDR2_SDBCR
 CONFIG_SYS_DA850_DDR2_SDBCR2
 CONFIG_SYS_DA850_DDR2_SDRCR
 CONFIG_SYS_DA850_DDR2_SDTIMR
 CONFIG_SYS_DA850_DDR2_SDTIMR2
 CONFIG_SYS_DA850_PLL0_PLLDIV1
 CONFIG_SYS_DA850_PLL0_PLLDIV2
 CONFIG_SYS_DA850_PLL0_PLLDIV3
 CONFIG_SYS_DA850_PLL0_PLLDIV4
 CONFIG_SYS_DA850_PLL0_PLLDIV5
 CONFIG_SYS_DA850_PLL0_PLLDIV6
 CONFIG_SYS_DA850_PLL0_PLLDIV7
 CONFIG_SYS_DA850_PLL0_PLLM
 CONFIG_SYS_DA850_PLL0_POSTDIV
 CONFIG_SYS_DA850_PLL0_PREDIV
 CONFIG_SYS_DA850_PLL1_PLLDIV1
 CONFIG_SYS_DA850_PLL1_PLLDIV2
 CONFIG_SYS_DA850_PLL1_PLLDIV3
 CONFIG_SYS_DA850_PLL1_PLLM
 CONFIG_SYS_DA850_PLL1_POSTDIV
 CONFIG_SYS_DA850_SYSCFG_SUSPSRC
 CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
 CONFIG_SYS_DAVINCI_I2C_SLAVE
 CONFIG_SYS_DAVINCI_I2C_SLAVE1
 CONFIG_SYS_DAVINCI_I2C_SLAVE2
 CONFIG_SYS_DAVINCI_I2C_SPEED
 CONFIG_SYS_DAVINCI_I2C_SPEED1
 CONFIG_SYS_DAVINCI_I2C_SPEED2
 CONFIG_SYS_DBAT
 CONFIG_SYS_DBAT0L
 CONFIG_SYS_DBAT0U
 CONFIG_SYS_DBAT1L
 CONFIG_SYS_DBAT1U
 CONFIG_SYS_DBAT2L
 CONFIG_SYS_DBAT2U
 CONFIG_SYS_DBAT3L
 CONFIG_SYS_DBAT3U
 CONFIG_SYS_DBAT4L
 CONFIG_SYS_DBAT4U
 CONFIG_SYS_DBAT5L
 CONFIG_SYS_DBAT5U
 CONFIG_SYS_DBAT6L
 CONFIG_SYS_DBAT6L_EARLY
 CONFIG_SYS_DBAT6U
 CONFIG_SYS_DBAT6U_EARLY
 CONFIG_SYS_DBAT7L
 CONFIG_SYS_DBAT7U
 CONFIG_SYS_DCACHE_INV
 CONFIG_SYS_DCSRBAR
 CONFIG_SYS_DCSRBAR_PHYS
 CONFIG_SYS_DCSR_COP_CCP_ADDR
 CONFIG_SYS_DCSR_DCFG_ADDR
 CONFIG_SYS_DCSR_DCFG_OFFSET
 CONFIG_SYS_DCU_ADDR
 CONFIG_SYS_DDR1_CS0_BNDS
 CONFIG_SYS_DDR2_CFG_1A
 CONFIG_SYS_DDR2_CFG_1B
 CONFIG_SYS_DDR2_CFG_2
 CONFIG_SYS_DDR2_CLK_CTRL
 CONFIG_SYS_DDR2_CS0_BNDS
 CONFIG_SYS_DDR2_CS0_CONFIG
 CONFIG_SYS_DDR2_CS1_BNDS
 CONFIG_SYS_DDR2_CS1_CONFIG
 CONFIG_SYS_DDR2_CS2_BNDS
 CONFIG_SYS_DDR2_CS2_CONFIG
 CONFIG_SYS_DDR2_CS3_BNDS
 CONFIG_SYS_DDR2_CS3_CONFIG
 CONFIG_SYS_DDR2_DATA_INIT
 CONFIG_SYS_DDR2_EXT_REFRESH
 CONFIG_SYS_DDR2_INTERVAL
 CONFIG_SYS_DDR2_MODE_1
 CONFIG_SYS_DDR2_MODE_2
 CONFIG_SYS_DDR2_MODE_CTL
 CONFIG_SYS_DDR2_TIMING_0
 CONFIG_SYS_DDR2_TIMING_1
 CONFIG_SYS_DDR2_TIMING_2
 CONFIG_SYS_DDRCDR
 CONFIG_SYS_DDRCDR_VALUE
 CONFIG_SYS_DDRD
 CONFIG_SYS_DDRTC
 CONFIG_SYS_DDRUA
 CONFIG_SYS_DDR_BASE
 CONFIG_SYS_DDR_BLOCK1_SIZE
 CONFIG_SYS_DDR_BLOCK2_BASE
 CONFIG_SYS_DDR_CDR_1
 CONFIG_SYS_DDR_CDR_2
 CONFIG_SYS_DDR_CFG_1A
 CONFIG_SYS_DDR_CFG_1B
 CONFIG_SYS_DDR_CFG_2
 CONFIG_SYS_DDR_CLKSEL
 CONFIG_SYS_DDR_CLK_CNTL
 CONFIG_SYS_DDR_CLK_CONTROL
 CONFIG_SYS_DDR_CLK_CTRL
 CONFIG_SYS_DDR_CLK_CTRL_1000
 CONFIG_SYS_DDR_CLK_CTRL_1200
 CONFIG_SYS_DDR_CLK_CTRL_1333
 CONFIG_SYS_DDR_CLK_CTRL_667
 CONFIG_SYS_DDR_CLK_CTRL_800
 CONFIG_SYS_DDR_CLK_CTRL_900
 CONFIG_SYS_DDR_CONFIG
 CONFIG_SYS_DDR_CONFIG_2
 CONFIG_SYS_DDR_CONFIG_256
 CONFIG_SYS_DDR_CONTROL
 CONFIG_SYS_DDR_CONTROL2
 CONFIG_SYS_DDR_CONTROL_1333
 CONFIG_SYS_DDR_CONTROL_2
 CONFIG_SYS_DDR_CONTROL_2_1333
 CONFIG_SYS_DDR_CONTROL_2_800
 CONFIG_SYS_DDR_CONTROL_800
 CONFIG_SYS_DDR_CPO
 CONFIG_SYS_DDR_CS0_BNDS
 CONFIG_SYS_DDR_CS0_CONFIG
 CONFIG_SYS_DDR_CS0_CONFIG_1333
 CONFIG_SYS_DDR_CS0_CONFIG_2
 CONFIG_SYS_DDR_CS0_CONFIG_800
 CONFIG_SYS_DDR_CS1_BNDS
 CONFIG_SYS_DDR_CS1_CONFIG
 CONFIG_SYS_DDR_CS1_CONFIG_2
 CONFIG_SYS_DDR_CS2_BNDS
 CONFIG_SYS_DDR_CS2_CONFIG
 CONFIG_SYS_DDR_CS3_BNDS
 CONFIG_SYS_DDR_CS3_CONFIG
 CONFIG_SYS_DDR_DATA_INIT
 CONFIG_SYS_DDR_ERR_DIS
 CONFIG_SYS_DDR_ERR_INT_EN
 CONFIG_SYS_DDR_INIT_ADDR
 CONFIG_SYS_DDR_INIT_EXT_ADDR
 CONFIG_SYS_DDR_INTERVAL
 CONFIG_SYS_DDR_INTERVAL_1000
 CONFIG_SYS_DDR_INTERVAL_1200
 CONFIG_SYS_DDR_INTERVAL_1333
 CONFIG_SYS_DDR_INTERVAL_667
 CONFIG_SYS_DDR_INTERVAL_800
 CONFIG_SYS_DDR_INTERVAL_900
 CONFIG_SYS_DDR_MODE
 CONFIG_SYS_DDR_MODE2
 CONFIG_SYS_DDR_MODE_1
 CONFIG_SYS_DDR_MODE_1_1000
 CONFIG_SYS_DDR_MODE_1_1200
 CONFIG_SYS_DDR_MODE_1_1333
 CONFIG_SYS_DDR_MODE_1_667
 CONFIG_SYS_DDR_MODE_1_800
 CONFIG_SYS_DDR_MODE_1_900
 CONFIG_SYS_DDR_MODE_2
 CONFIG_SYS_DDR_MODE_2_1000
 CONFIG_SYS_DDR_MODE_2_1200
 CONFIG_SYS_DDR_MODE_2_1333
 CONFIG_SYS_DDR_MODE_2_667
 CONFIG_SYS_DDR_MODE_2_800
 CONFIG_SYS_DDR_MODE_2_900
 CONFIG_SYS_DDR_MODE_CONTROL
 CONFIG_SYS_DDR_MODE_CTL
 CONFIG_SYS_DDR_MODE_WEAK
 CONFIG_SYS_DDR_OCD_CTRL
 CONFIG_SYS_DDR_OCD_STATUS
 CONFIG_SYS_DDR_RAW_TIMING
 CONFIG_SYS_DDR_RCW_1
 CONFIG_SYS_DDR_RCW_2
 CONFIG_SYS_DDR_SBE
 CONFIG_SYS_DDR_SDRAM_BASE
 CONFIG_SYS_DDR_SDRAM_BASE2
 CONFIG_SYS_DDR_SDRAM_CFG
 CONFIG_SYS_DDR_SDRAM_CFG2
 CONFIG_SYS_DDR_SDRAM_CFG_2
 CONFIG_SYS_DDR_SDRAM_CLK_CNTL
 CONFIG_SYS_DDR_SDRAM_INTERVAL
 CONFIG_SYS_DDR_SDRAM_MODE
 CONFIG_SYS_DDR_SDRAM_MODE_2
 CONFIG_SYS_DDR_SIZE
 CONFIG_SYS_DDR_SR_CNTR
 CONFIG_SYS_DDR_TIMING_0
 CONFIG_SYS_DDR_TIMING_0_1000
 CONFIG_SYS_DDR_TIMING_0_1200
 CONFIG_SYS_DDR_TIMING_0_1333
 CONFIG_SYS_DDR_TIMING_0_667
 CONFIG_SYS_DDR_TIMING_0_800
 CONFIG_SYS_DDR_TIMING_0_900
 CONFIG_SYS_DDR_TIMING_1
 CONFIG_SYS_DDR_TIMING_1_1000
 CONFIG_SYS_DDR_TIMING_1_1200
 CONFIG_SYS_DDR_TIMING_1_1333
 CONFIG_SYS_DDR_TIMING_1_667
 CONFIG_SYS_DDR_TIMING_1_800
 CONFIG_SYS_DDR_TIMING_1_900
 CONFIG_SYS_DDR_TIMING_2
 CONFIG_SYS_DDR_TIMING_2_1000
 CONFIG_SYS_DDR_TIMING_2_1200
 CONFIG_SYS_DDR_TIMING_2_1333
 CONFIG_SYS_DDR_TIMING_2_667
 CONFIG_SYS_DDR_TIMING_2_800
 CONFIG_SYS_DDR_TIMING_2_900
 CONFIG_SYS_DDR_TIMING_3
 CONFIG_SYS_DDR_TIMING_3_1000
 CONFIG_SYS_DDR_TIMING_3_1200
 CONFIG_SYS_DDR_TIMING_3_1333
 CONFIG_SYS_DDR_TIMING_3_667
 CONFIG_SYS_DDR_TIMING_3_800
 CONFIG_SYS_DDR_TIMING_3_900
 CONFIG_SYS_DDR_TIMING_4
 CONFIG_SYS_DDR_TIMING_4_1333
 CONFIG_SYS_DDR_TIMING_4_800
 CONFIG_SYS_DDR_TIMING_5
 CONFIG_SYS_DDR_TIMING_5_1333
 CONFIG_SYS_DDR_TIMING_5_800
 CONFIG_SYS_DDR_WRITE_DATA_DELAY
 CONFIG_SYS_DDR_WRLVL_CNTL
 CONFIG_SYS_DDR_WRLVL_CONTROL
 CONFIG_SYS_DDR_WRLVL_CONTROL_1333
 CONFIG_SYS_DDR_WRLVL_CONTROL_667
 CONFIG_SYS_DDR_WRLVL_CONTROL_800
 CONFIG_SYS_DDR_ZQ_CNTL
 CONFIG_SYS_DDR_ZQ_CONTROL
 CONFIG_SYS_DEBUG
 CONFIG_SYS_DEBUG_SERVER_FW_ADDR
 CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 CONFIG_SYS_DEFAULT_VIDEO_MODE
 CONFIG_SYS_DEF_EEPROM_ADDR
 CONFIG_SYS_DEVICE_NULLDEV
 CONFIG_SYS_DFU_DATA_BUF_SIZE
 CONFIG_SYS_DFU_MAX_FILE_SIZE
 CONFIG_SYS_DIAG_ADDR
 CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
 CONFIG_SYS_DIMM_SLOTS_PER_CTLR
 CONFIG_SYS_DIRECT_FLASH_NFS
 CONFIG_SYS_DIRECT_FLASH_TFTP
 CONFIG_SYS_DISCOVER_PHY
 CONFIG_SYS_DIU_ADDR
 CONFIG_SYS_DM36x_PINMUX0
 CONFIG_SYS_DM36x_PINMUX1
 CONFIG_SYS_DM36x_PINMUX2
 CONFIG_SYS_DM36x_PINMUX3
 CONFIG_SYS_DM36x_PINMUX4
 CONFIG_SYS_DM36x_PLL1_PREDIV
 CONFIG_SYS_DM36x_PLL2_PREDIV
 CONFIG_SYS_DMA_USE_INTSRAM
 CONFIG_SYS_DP501_BASE
 CONFIG_SYS_DP501_DIFFERENTIAL
 CONFIG_SYS_DP501_I2C
 CONFIG_SYS_DP501_VCAPCTRL0
 CONFIG_SYS_DPAA_DCE
 CONFIG_SYS_DPAA_FMAN
 CONFIG_SYS_DPAA_PME
 CONFIG_SYS_DPAA_QBMAN
 CONFIG_SYS_DPAA_RMAN
 CONFIG_SYS_DP_DDR_BASE
 CONFIG_SYS_DP_DDR_BASE_PHY
 CONFIG_SYS_DRAMSZ
 CONFIG_SYS_DRAMSZ1
 CONFIG_SYS_DRAM_BASE
 CONFIG_SYS_DRAM_SIZE
 CONFIG_SYS_DRAM_TEST
 CONFIG_SYS_DSPI_CS0
 CONFIG_SYS_DSPI_CS2
 CONFIG_SYS_DSPI_CTAR0
 CONFIG_SYS_DSPI_CTAR1
 CONFIG_SYS_DSPI_CTAR2
 CONFIG_SYS_DSPI_CTAR3
 CONFIG_SYS_DSPI_CTAR4
 CONFIG_SYS_DSPI_CTAR5
 CONFIG_SYS_DSPI_CTAR6
 CONFIG_SYS_DSPI_CTAR7
 CONFIG_SYS_DV_CLKMODE
 CONFIG_SYS_DV_NOR_BOOT_CFG
 CONFIG_SYS_EBI_CFGR_VAL
 CONFIG_SYS_EBI_CSA_VAL
 CONFIG_SYS_EEPROM_BASE
 CONFIG_SYS_EEPROM_BUS_NUM
 CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 CONFIG_SYS_EEPROM_WREN
 CONFIG_SYS_EHCI_USB1_ADDR
 CONFIG_SYS_ELBC_BASE
 CONFIG_SYS_ELBC_BASE_PHYS
 CONFIG_SYS_ELO3_DMA3
 CONFIG_SYS_EMAC_TI_CLKDIV
 CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 CONFIG_SYS_ENABLE_PADS_ALL
 CONFIG_SYS_ENET_BD_BASE
 CONFIG_SYS_ENV_ADDR
 CONFIG_SYS_ENV_SECT_SIZE
 CONFIG_SYS_EPLD_BASE
 CONFIG_SYS_ETHOC_BASE
 CONFIG_SYS_ETHOC_BUFFER_ADDR
 CONFIG_SYS_ETVPE_CLK
 CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 CONFIG_SYS_EXTRA_ENV_RELOC
 CONFIG_SYS_FAST_CLK
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 CONFIG_SYS_FAULT_MII_ADDR
 CONFIG_SYS_FCC_PSMR
 CONFIG_SYS_FDC_DRIVE_NUMBER
 CONFIG_SYS_FDC_HW_INIT
 CONFIG_SYS_FDT_ADDR
 CONFIG_SYS_FDT_BASE
 CONFIG_SYS_FDT_LOAD_ADDR
 CONFIG_SYS_FDT_PAD
 CONFIG_SYS_FDT_SIZE
 CONFIG_SYS_FEC0_IOBASE
 CONFIG_SYS_FEC0_MIIBASE
 CONFIG_SYS_FEC0_PHYADDR
 CONFIG_SYS_FEC0_PINMUX
 CONFIG_SYS_FEC1_IOBASE
 CONFIG_SYS_FEC1_MIIBASE
 CONFIG_SYS_FEC1_PHYADDR
 CONFIG_SYS_FEC1_PINMUX
 CONFIG_SYS_FECI2C
 CONFIG_SYS_FEC_BUF_USE_SRAM
 CONFIG_SYS_FEC_FULL_MII
 CONFIG_SYS_FEC_NO_SHARED_PHY
 CONFIG_SYS_FIFO_BASE
 CONFIG_SYS_FIXED_PHY_ADDR
 CONFIG_SYS_FIXED_PHY_PORT
 CONFIG_SYS_FIXED_PHY_PORTS
 CONFIG_SYS_FLASH0
 CONFIG_SYS_FLASH0_BASE
 CONFIG_SYS_FLASH1
 CONFIG_SYS_FLASH1_BASE
 CONFIG_SYS_FLASH1_BASE_PHYS
 CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
 CONFIG_SYS_FLASHBOOT
 CONFIG_SYS_FLASH_ADDR_BASE
 CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 CONFIG_SYS_FLASH_AUTOPROTECT_LIST
 CONFIG_SYS_FLASH_BANKS_LIST
 CONFIG_SYS_FLASH_BANKS_SIZES
 CONFIG_SYS_FLASH_BANK_SIZE
 CONFIG_SYS_FLASH_BASE
 CONFIG_SYS_FLASH_BASE0
 CONFIG_SYS_FLASH_BASE1
 CONFIG_SYS_FLASH_BASE2
 CONFIG_SYS_FLASH_BASE_PHYS
 CONFIG_SYS_FLASH_BASE_PHYS_EARLY
 CONFIG_SYS_FLASH_BASE_PHYS_LOW
 CONFIG_SYS_FLASH_BR_PRELIM
 CONFIG_SYS_FLASH_CFI
 CONFIG_SYS_FLASH_CFI_AMD_RESET
 CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
 CONFIG_SYS_FLASH_CFI_NONBLOCK
 CONFIG_SYS_FLASH_CFI_WIDTH
 CONFIG_SYS_FLASH_CHECKSUM
 CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE
 CONFIG_SYS_FLASH_EMPTY_INFO
 CONFIG_SYS_FLASH_ERASE_TOUT
 CONFIG_SYS_FLASH_LEGACY_256Kx8
 CONFIG_SYS_FLASH_LEGACY_512Kx16
 CONFIG_SYS_FLASH_LEGACY_512Kx8
 CONFIG_SYS_FLASH_LOCK_TOUT
 CONFIG_SYS_FLASH_OR_PRELIM
 CONFIG_SYS_FLASH_PARMSECT_SZ
 CONFIG_SYS_FLASH_PROTECTION
 CONFIG_SYS_FLASH_QUIET_TEST
 CONFIG_SYS_FLASH_SECT_SIZE
 CONFIG_SYS_FLASH_SECT_SZ
 CONFIG_SYS_FLASH_SIZE
 CONFIG_SYS_FLASH_UNLOCK_TOUT
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE
 CONFIG_SYS_FLASH_WRITE_TOUT
 CONFIG_SYS_FLYCNFG_VAL
 CONFIG_SYS_FM1_10GEC1_PHY_ADDR
 CONFIG_SYS_FM1_10GEC2_PHY_ADDR
 CONFIG_SYS_FM1_CLK
 CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR
 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC2_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC3_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC_MDIO_ADDR
 CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR
 CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR
 CONFIG_SYS_FM1_QSGMII11_PHY_ADDR
 CONFIG_SYS_FM1_QSGMII21_PHY_ADDR
 CONFIG_SYS_FM1_TGEC_MDIO_ADDR
 CONFIG_SYS_FM2_10GEC1_PHY_ADDR
 CONFIG_SYS_FM2_CLK
 CONFIG_SYS_FM2_DTSEC1_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC2_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC3_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC4_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC_MDIO_ADDR
 CONFIG_SYS_FM2_TGEC_MDIO_ADDR
 CONFIG_SYS_FMAN_FW_ADDR
 CONFIG_SYS_FMAN_V3
 CONFIG_SYS_FM_MURAM_SIZE
 CONFIG_SYS_FORM_3U_CPCI
 CONFIG_SYS_FORM_3U_VPX
 CONFIG_SYS_FORM_6U_CPCI
 CONFIG_SYS_FORM_6U_VPX
 CONFIG_SYS_FORM_AMC
 CONFIG_SYS_FORM_ATCA_AMC
 CONFIG_SYS_FORM_ATCA_PMC
 CONFIG_SYS_FORM_CUSTOM
 CONFIG_SYS_FORM_PCI
 CONFIG_SYS_FORM_PCI_EXPRESS
 CONFIG_SYS_FORM_PMC
 CONFIG_SYS_FORM_PMC_XMC
 CONFIG_SYS_FORM_VME
 CONFIG_SYS_FORM_XMC
 CONFIG_SYS_FPGA0_BASE
 CONFIG_SYS_FPGA0_SIZE
 CONFIG_SYS_FPGAREG_DATE
 CONFIG_SYS_FPGAREG_DIPSW
 CONFIG_SYS_FPGAREG_FREQ
 CONFIG_SYS_FPGAREG_RESET
 CONFIG_SYS_FPGAREG_RESET_CODE
 CONFIG_SYS_FPGA_AMASK
 CONFIG_SYS_FPGA_BASE
 CONFIG_SYS_FPGA_BASE_PHYS
 CONFIG_SYS_FPGA_CHECK_BUSY
 CONFIG_SYS_FPGA_CHECK_CTRLC
 CONFIG_SYS_FPGA_CHECK_ERROR
 CONFIG_SYS_FPGA_COUNT
 CONFIG_SYS_FPGA_CSOR
 CONFIG_SYS_FPGA_CSPR
 CONFIG_SYS_FPGA_CSPR_EXT
 CONFIG_SYS_FPGA_DONE
 CONFIG_SYS_FPGA_FTIM0
 CONFIG_SYS_FPGA_FTIM1
 CONFIG_SYS_FPGA_FTIM2
 CONFIG_SYS_FPGA_FTIM3
 CONFIG_SYS_FPGA_IS_PROTO
 CONFIG_SYS_FPGA_NO_RFL_HI
 CONFIG_SYS_FPGA_PROG
 CONFIG_SYS_FPGA_PROG_FEEDBACK
 CONFIG_SYS_FPGA_PROG_TIME
 CONFIG_SYS_FPGA_PTR
 CONFIG_SYS_FPGA_SIZE
 CONFIG_SYS_FPGA_WAIT
 CONFIG_SYS_FPGA_WAIT_BUSY
 CONFIG_SYS_FPGA_WAIT_CONFIG
 CONFIG_SYS_FPGA_WAIT_INIT
 CONFIG_SYS_FSL_AIOP1_BASE
 CONFIG_SYS_FSL_AIOP1_SIZE
 CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 CONFIG_SYS_FSL_BMAN_ADDR
 CONFIG_SYS_FSL_BMAN_OFFSET
 CONFIG_SYS_FSL_BOOTROM_BASE
 CONFIG_SYS_FSL_BOOTROM_SIZE
 CONFIG_SYS_FSL_CCSR_BASE
 CONFIG_SYS_FSL_CCSR_GUR_BE
 CONFIG_SYS_FSL_CCSR_GUR_LE
 CONFIG_SYS_FSL_CCSR_SCFG_BE
 CONFIG_SYS_FSL_CCSR_SCFG_LE
 CONFIG_SYS_FSL_CCSR_SIZE
 CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR
 CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR
 CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR
 CONFIG_SYS_FSL_CLK_ADDR
 CONFIG_SYS_FSL_CLUSTER_1_L2
 CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET
 CONFIG_SYS_FSL_CLUSTER_CLOCKS
 CONFIG_SYS_FSL_CORENET_CCM_ADDR
 CONFIG_SYS_FSL_CORENET_CCM_OFFSET
 CONFIG_SYS_FSL_CORENET_CLK_ADDR
 CONFIG_SYS_FSL_CORENET_CLK_OFFSET
 CONFIG_SYS_FSL_CORENET_PMAN
 CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET
 CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET
 CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET
 CONFIG_SYS_FSL_CORENET_PME_ADDR
 CONFIG_SYS_FSL_CORENET_PME_OFFSET
 CONFIG_SYS_FSL_CORENET_RCPM_ADDR
 CONFIG_SYS_FSL_CORENET_RCPM_OFFSET
 CONFIG_SYS_FSL_CORENET_RMAN_ADDR
 CONFIG_SYS_FSL_CORENET_RMAN_OFFSET
 CONFIG_SYS_FSL_CORENET_SERDES2_ADDR
 CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET
 CONFIG_SYS_FSL_CORENET_SERDES3_ADDR
 CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET
 CONFIG_SYS_FSL_CORENET_SERDES4_ADDR
 CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET
 CONFIG_SYS_FSL_CORENET_SERDES_ADDR
 CONFIG_SYS_FSL_CORENET_SERDES_OFFSET
 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 CONFIG_SYS_FSL_CORES_PER_CLUSTER
 CONFIG_SYS_FSL_CPC
 CONFIG_SYS_FSL_CPC_ADDR
 CONFIG_SYS_FSL_CPC_OFFSET
 CONFIG_SYS_FSL_CSU_ADDR
 CONFIG_SYS_FSL_DCFG_ADDR
 CONFIG_SYS_FSL_DCSR_BASE
 CONFIG_SYS_FSL_DCSR_DDR2_ADDR
 CONFIG_SYS_FSL_DCSR_DDR3_ADDR
 CONFIG_SYS_FSL_DCSR_DDR4_ADDR
 CONFIG_SYS_FSL_DCSR_DDR_ADDR
 CONFIG_SYS_FSL_DCSR_SIZE
 CONFIG_SYS_FSL_DCU_BE
 CONFIG_SYS_FSL_DCU_LE
 CONFIG_SYS_FSL_DDR2_ADDR
 CONFIG_SYS_FSL_DDR3L
 CONFIG_SYS_FSL_DDR3_ADDR
 CONFIG_SYS_FSL_DDR_ADDR
 CONFIG_SYS_FSL_DDR_EMU
 CONFIG_SYS_FSL_DDR_INTLV_256B
 CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
 CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
 CONFIG_SYS_FSL_DRAM_BASE1
 CONFIG_SYS_FSL_DRAM_BASE2
 CONFIG_SYS_FSL_DRAM_BASE3
 CONFIG_SYS_FSL_DRAM_SIZE1
 CONFIG_SYS_FSL_DRAM_SIZE2
 CONFIG_SYS_FSL_DRAM_SIZE3
 CONFIG_SYS_FSL_DSPI_BE
 CONFIG_SYS_FSL_DSP_CCSRBAR
 CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS
 CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
 CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
 CONFIG_SYS_FSL_DSP_DDR_ADDR
 CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
 CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
 CONFIG_SYS_FSL_ERRATUM_A008751
 CONFIG_SYS_FSL_ERRATUM_A_004934
 CONFIG_SYS_FSL_ESDHC_ADDR
 CONFIG_SYS_FSL_ESDHC_BE
 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 CONFIG_SYS_FSL_ESDHC_LE
 CONFIG_SYS_FSL_ESDHC_NUM
 CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
 CONFIG_SYS_FSL_ESDHC_USE_PIO
 CONFIG_SYS_FSL_FM
 CONFIG_SYS_FSL_FM1_ADDR
 CONFIG_SYS_FSL_FM1_DTSEC1_ADDR
 CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
 CONFIG_SYS_FSL_FM1_OFFSET
 CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET
 CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET
 CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
 CONFIG_SYS_FSL_FM2_ADDR
 CONFIG_SYS_FSL_FM2_OFFSET
 CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET
 CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET
 CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
 CONFIG_SYS_FSL_FMAN_ADDR
 CONFIG_SYS_FSL_GUTS_ADDR
 CONFIG_SYS_FSL_I2C
 CONFIG_SYS_FSL_I2C2_OFFSET
 CONFIG_SYS_FSL_I2C2_SLAVE
 CONFIG_SYS_FSL_I2C2_SPEED
 CONFIG_SYS_FSL_I2C3_OFFSET
 CONFIG_SYS_FSL_I2C3_SLAVE
 CONFIG_SYS_FSL_I2C3_SPEED
 CONFIG_SYS_FSL_I2C4_OFFSET
 CONFIG_SYS_FSL_I2C4_SLAVE
 CONFIG_SYS_FSL_I2C4_SPEED
 CONFIG_SYS_FSL_I2C_OFFSET
 CONFIG_SYS_FSL_I2C_SLAVE
 CONFIG_SYS_FSL_I2C_SPEED
 CONFIG_SYS_FSL_IFC_BASE
 CONFIG_SYS_FSL_IFC_BASE1
 CONFIG_SYS_FSL_IFC_BASE2
 CONFIG_SYS_FSL_IFC_BE
 CONFIG_SYS_FSL_IFC_LE
 CONFIG_SYS_FSL_IFC_SIZE
 CONFIG_SYS_FSL_IFC_SIZE1
 CONFIG_SYS_FSL_IFC_SIZE1_1
 CONFIG_SYS_FSL_IFC_SIZE2
 CONFIG_SYS_FSL_ISBC_VER
 CONFIG_SYS_FSL_JR0_ADDR
 CONFIG_SYS_FSL_JR0_OFFSET
 CONFIG_SYS_FSL_LS1_CLK_ADDR
 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
 CONFIG_SYS_FSL_MAX_NUM_OF_SEC
 CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
 CONFIG_SYS_FSL_MC_BASE
 CONFIG_SYS_FSL_MC_SIZE
 CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 CONFIG_SYS_FSL_NI_BASE
 CONFIG_SYS_FSL_NI_SIZE
 CONFIG_SYS_FSL_NO_SERDES
 CONFIG_SYS_FSL_NUM_CC_PLL
 CONFIG_SYS_FSL_NUM_CC_PLLS
 CONFIG_SYS_FSL_OCRAM_BASE
 CONFIG_SYS_FSL_OCRAM_SIZE
 CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 CONFIG_SYS_FSL_PAMU_OFFSET
 CONFIG_SYS_FSL_PBL_PBI
 CONFIG_SYS_FSL_PBL_RCW
 CONFIG_SYS_FSL_PCIE_COMPAT
 CONFIG_SYS_FSL_PCI_VER_3_X
 CONFIG_SYS_FSL_PEBUF_BASE
 CONFIG_SYS_FSL_PEBUF_SIZE
 CONFIG_SYS_FSL_PEX_LUT_BE
 CONFIG_SYS_FSL_PEX_LUT_LE
 CONFIG_SYS_FSL_PMIC_I2C_ADDR
 CONFIG_SYS_FSL_PMU_ADDR
 CONFIG_SYS_FSL_PMU_CLTBENR
 CONFIG_SYS_FSL_QBMAN_BASE
 CONFIG_SYS_FSL_QBMAN_SIZE
 CONFIG_SYS_FSL_QBMAN_SIZE_1
 CONFIG_SYS_FSL_QMAN_ADDR
 CONFIG_SYS_FSL_QMAN_OFFSET
 CONFIG_SYS_FSL_QMAN_V3
 CONFIG_SYS_FSL_QSPI_AHB
 CONFIG_SYS_FSL_QSPI_BASE
 CONFIG_SYS_FSL_QSPI_BASE1
 CONFIG_SYS_FSL_QSPI_BASE2
 CONFIG_SYS_FSL_QSPI_BE
 CONFIG_SYS_FSL_QSPI_LE
 CONFIG_SYS_FSL_QSPI_SIZE
 CONFIG_SYS_FSL_QSPI_SIZE1
 CONFIG_SYS_FSL_QSPI_SIZE2
 CONFIG_SYS_FSL_RAID_ENGINE
 CONFIG_SYS_FSL_RAID_ENGINE_ADDR
 CONFIG_SYS_FSL_RAID_ENGINE_OFFSET
 CONFIG_SYS_FSL_RCPM_ADDR
 CONFIG_SYS_FSL_RMU
 CONFIG_SYS_FSL_RST_ADDR
 CONFIG_SYS_FSL_SCFG_ADDR
 CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
 CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET
 CONFIG_SYS_FSL_SCFG_OFFSET
 CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
 CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
 CONFIG_SYS_FSL_SEC_ADDR
 CONFIG_SYS_FSL_SEC_IDX_OFFSET
 CONFIG_SYS_FSL_SEC_MON_BE
 CONFIG_SYS_FSL_SEC_MON_LE
 CONFIG_SYS_FSL_SEC_OFFSET
 CONFIG_SYS_FSL_SERDES
 CONFIG_SYS_FSL_SERDES_ADDR
 CONFIG_SYS_FSL_SFP_BE
 CONFIG_SYS_FSL_SFP_LE
 CONFIG_SYS_FSL_SFP_VER_3_0
 CONFIG_SYS_FSL_SFP_VER_3_2
 CONFIG_SYS_FSL_SFP_VER_3_4
 CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 CONFIG_SYS_FSL_SRDS_3
 CONFIG_SYS_FSL_SRDS_4
 CONFIG_SYS_FSL_SRDS_NUM_PLLS
 CONFIG_SYS_FSL_SRIO_ADDR
 CONFIG_SYS_FSL_SRIO_IB_WIN_NUM
 CONFIG_SYS_FSL_SRIO_LIODN
 CONFIG_SYS_FSL_SRIO_MAX_PORTS
 CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM
 CONFIG_SYS_FSL_SRIO_OB_WIN_NUM
 CONFIG_SYS_FSL_SRIO_OFFSET
 CONFIG_SYS_FSL_SRK_LE
 CONFIG_SYS_FSL_TBCLK_DIV
 CONFIG_SYS_FSL_TIMER_ADDR
 CONFIG_SYS_FSL_USB1_ADDR
 CONFIG_SYS_FSL_USB1_PHY_ENABLE
 CONFIG_SYS_FSL_USB2_ADDR
 CONFIG_SYS_FSL_USB2_PHY_ENABLE
 CONFIG_SYS_FSL_USB_CTRL_PHY_EN
 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN
 CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE
 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC
 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN
 CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV
 CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN
 CONFIG_SYS_FSL_USB_PLLPRG2_MFI
 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK
 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN
 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN
 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN
 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV
 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK
 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN
 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3
 CONFIG_SYS_FSL_USB_SYS_CLK_VALID
 CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN
 CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK
 CONFIG_SYS_FSL_USDHC_NUM
 CONFIG_SYS_FSL_WDOG_BE
 CONFIG_SYS_FSL_WRIOP1_ADDR
 CONFIG_SYS_FSL_WRIOP1_BASE
 CONFIG_SYS_FSL_WRIOP1_MDIO1
 CONFIG_SYS_FSL_WRIOP1_MDIO2
 CONFIG_SYS_FSL_WRIOP1_SIZE
 CONFIG_SYS_FSL_XHCI_USB1_ADDR
 CONFIG_SYS_FSL_XHCI_USB2_ADDR
 CONFIG_SYS_FSL_XHCI_USB3_ADDR
 CONFIG_SYS_FSMC_BASE
 CONFIG_SYS_FSMC_NAND_16BIT
 CONFIG_SYS_FSMC_NAND_8BIT
 CONFIG_SYS_FSMC_NAND_SP
 CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
 CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS
 CONFIG_SYS_FTPMU010_SDRAMHTC
 CONFIG_SYS_FTSDMC021_BANK0_BASE
 CONFIG_SYS_FTSDMC021_BANK0_BSR
 CONFIG_SYS_FTSDMC021_BANK1_BASE
 CONFIG_SYS_FTSDMC021_BANK1_BSR
 CONFIG_SYS_FTSDMC021_CR1
 CONFIG_SYS_FTSDMC021_CR2
 CONFIG_SYS_FTSDMC021_TP1
 CONFIG_SYS_FTSDMC021_TP2
 CONFIG_SYS_FTSMC020_CONFIGS
 CONFIG_SYS_FULL_VA
 CONFIG_SYS_GAFR0_L_VAL
 CONFIG_SYS_GAFR0_U_VAL
 CONFIG_SYS_GAFR1_L_VAL
 CONFIG_SYS_GAFR1_U_VAL
 CONFIG_SYS_GAFR2_L_VAL
 CONFIG_SYS_GAFR2_U_VAL
 CONFIG_SYS_GAFR3_L_VAL
 CONFIG_SYS_GAFR3_U_VAL
 CONFIG_SYS_GBIT_MII1_BUSNAME
 CONFIG_SYS_GBIT_MII_BUSNAME
 CONFIG_SYS_GBL_DATA_OFFSET
 CONFIG_SYS_GBL_DATA_SIZE
 CONFIG_SYS_GENERIC_BOARD
 CONFIG_SYS_GIC400_ADDR
 CONFIG_SYS_GP1DIR
 CONFIG_SYS_GP1ODR
 CONFIG_SYS_GP2DIR
 CONFIG_SYS_GP2ODR
 CONFIG_SYS_GPCR0_VAL
 CONFIG_SYS_GPCR1_VAL
 CONFIG_SYS_GPCR2_VAL
 CONFIG_SYS_GPCR3_VAL
 CONFIG_SYS_GPDR0_VAL
 CONFIG_SYS_GPDR1_VAL
 CONFIG_SYS_GPDR2_VAL
 CONFIG_SYS_GPDR3_VAL
 CONFIG_SYS_GPIO1_DAT
 CONFIG_SYS_GPIO1_DIR
 CONFIG_SYS_GPIO1_EN
 CONFIG_SYS_GPIO1_FUNC
 CONFIG_SYS_GPIO1_LED
 CONFIG_SYS_GPIO1_OUT
 CONFIG_SYS_GPIO1_PRELIM
 CONFIG_SYS_GPIO2_DAT
 CONFIG_SYS_GPIO2_DIR
 CONFIG_SYS_GPIO2_PRELIM
 CONFIG_SYS_GPIO_0_ADDR
 CONFIG_SYS_GPIO_EN
 CONFIG_SYS_GPIO_FUNC
 CONFIG_SYS_GPIO_I2C_SCL
 CONFIG_SYS_GPIO_I2C_SDA
 CONFIG_SYS_GPIO_OUT
 CONFIG_SYS_GPIO_PHY_RST
 CONFIG_SYS_GPR1
 CONFIG_SYS_GPSR0_VAL
 CONFIG_SYS_GPSR1_VAL
 CONFIG_SYS_GPSR2_VAL
 CONFIG_SYS_GPSR3_VAL
 CONFIG_SYS_HALT_BEFOR_RAM_JUMP
 CONFIG_SYS_HELP_CMD_WIDTH
 CONFIG_SYS_HID0_FINAL
 CONFIG_SYS_HID0_INIT
 CONFIG_SYS_HID2
 CONFIG_SYS_HIGH
 CONFIG_SYS_HMI_BASE
 CONFIG_SYS_HOSTNAME
 CONFIG_SYS_HRCW_HIGH
 CONFIG_SYS_HRCW_HIGH_BASE
 CONFIG_SYS_HRCW_LOW
 CONFIG_SYS_HZ_CLOCK
 CONFIG_SYS_I2C
 CONFIG_SYS_I2C2_FSL_OFFSET
 CONFIG_SYS_I2C2_OFFSET
 CONFIG_SYS_I2C2_PINMUX_CLR
 CONFIG_SYS_I2C2_PINMUX_REG
 CONFIG_SYS_I2C2_PINMUX_SET
 CONFIG_SYS_I2C_0
 CONFIG_SYS_I2C_2
 CONFIG_SYS_I2C_5
 CONFIG_SYS_I2C_8574A_ADDR1
 CONFIG_SYS_I2C_8574A_ADDR2
 CONFIG_SYS_I2C_8574_ADDR1
 CONFIG_SYS_I2C_8574_ADDR2
 CONFIG_SYS_I2C_BASE
 CONFIG_SYS_I2C_BASE0
 CONFIG_SYS_I2C_BASE1
 CONFIG_SYS_I2C_BASE2
 CONFIG_SYS_I2C_BASE3
 CONFIG_SYS_I2C_BASE4
 CONFIG_SYS_I2C_BASE5
 CONFIG_SYS_I2C_BUSES
 CONFIG_SYS_I2C_CLK_OFFSET
 CONFIG_SYS_I2C_DAVINCI
 CONFIG_SYS_I2C_DIRECT_BUS
 CONFIG_SYS_I2C_DVI_ADDR
 CONFIG_SYS_I2C_DVI_BUS_NUM
 CONFIG_SYS_I2C_EARLY_INIT
 CONFIG_SYS_I2C_EEPROM
 CONFIG_SYS_I2C_EEPROM_CCID
 CONFIG_SYS_I2C_EEPROM_NXID
 CONFIG_SYS_I2C_EEPROM_NXID_MAC
 CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS
 CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS
 CONFIG_SYS_I2C_EXPANDER_ADDR
 CONFIG_SYS_I2C_FPGA_ADDR
 CONFIG_SYS_I2C_FRAM
 CONFIG_SYS_I2C_G762_ADDR
 CONFIG_SYS_I2C_GENERIC_MAC
 CONFIG_SYS_I2C_IDT6V49205B
 CONFIG_SYS_I2C_IFDR_DIV
 CONFIG_SYS_I2C_IHS
 CONFIG_SYS_I2C_IHS_CH0
 CONFIG_SYS_I2C_IHS_CH0_1
 CONFIG_SYS_I2C_IHS_CH1
 CONFIG_SYS_I2C_IHS_CH1_1
 CONFIG_SYS_I2C_IHS_CH2
 CONFIG_SYS_I2C_IHS_CH2_1
 CONFIG_SYS_I2C_IHS_CH3
 CONFIG_SYS_I2C_IHS_CH3_1
 CONFIG_SYS_I2C_IHS_DUAL
 CONFIG_SYS_I2C_IHS_SLAVE_0
 CONFIG_SYS_I2C_IHS_SLAVE_0_1
 CONFIG_SYS_I2C_IHS_SLAVE_1
 CONFIG_SYS_I2C_IHS_SLAVE_1_1
 CONFIG_SYS_I2C_IHS_SLAVE_2
 CONFIG_SYS_I2C_IHS_SLAVE_2_1
 CONFIG_SYS_I2C_IHS_SLAVE_3
 CONFIG_SYS_I2C_IHS_SLAVE_3_1
 CONFIG_SYS_I2C_IHS_SPEED_0
 CONFIG_SYS_I2C_IHS_SPEED_0_1
 CONFIG_SYS_I2C_IHS_SPEED_1
 CONFIG_SYS_I2C_IHS_SPEED_1_1
 CONFIG_SYS_I2C_IHS_SPEED_2
 CONFIG_SYS_I2C_IHS_SPEED_2_1
 CONFIG_SYS_I2C_IHS_SPEED_3
 CONFIG_SYS_I2C_IHS_SPEED_3_1
 CONFIG_SYS_I2C_INIT_BOARD
 CONFIG_SYS_I2C_KONA
 CONFIG_SYS_I2C_LDI_ADDR
 CONFIG_SYS_I2C_LM75_ADDR
 CONFIG_SYS_I2C_LM90_ADDR
 CONFIG_SYS_I2C_LPC32XX
 CONFIG_SYS_I2C_LPC32XX_SLAVE
 CONFIG_SYS_I2C_LPC32XX_SPEED
 CONFIG_SYS_I2C_MAC1_BUS
 CONFIG_SYS_I2C_MAC1_CHIP_ADDR
 CONFIG_SYS_I2C_MAC1_DATA_ADDR
 CONFIG_SYS_I2C_MAC2_BUS
 CONFIG_SYS_I2C_MAC2_CHIP_ADDR
 CONFIG_SYS_I2C_MAC2_DATA_ADDR
 CONFIG_SYS_I2C_MAC_OFFSET
 CONFIG_SYS_I2C_MAX1237_ADDR
 CONFIG_SYS_I2C_MAX_HOPS
 CONFIG_SYS_I2C_MXC_I2C1
 CONFIG_SYS_I2C_MXC_I2C2
 CONFIG_SYS_I2C_MXC_I2C3
 CONFIG_SYS_I2C_MXC_I2C4
 CONFIG_SYS_I2C_NCT72_ADDR
 CONFIG_SYS_I2C_NOPROBES
 CONFIG_SYS_I2C_OFFSET
 CONFIG_SYS_I2C_PCA953X_ADDR
 CONFIG_SYS_I2C_PCA953X_ADDR0
 CONFIG_SYS_I2C_PCA953X_ADDR1
 CONFIG_SYS_I2C_PCA953X_ADDR2
 CONFIG_SYS_I2C_PCA953X_ADDR3
 CONFIG_SYS_I2C_PCA953X_WIDTH
 CONFIG_SYS_I2C_PCA9553_ADDR
 CONFIG_SYS_I2C_PCA9555_ADDR
 CONFIG_SYS_I2C_PCA9557_ADDR
 CONFIG_SYS_I2C_PCF8574A_ADDR
 CONFIG_SYS_I2C_PEX8518_ADDR
 CONFIG_SYS_I2C_PINMUX_CLR
 CONFIG_SYS_I2C_PINMUX_REG
 CONFIG_SYS_I2C_PINMUX_SET
 CONFIG_SYS_I2C_POWERIC_ADDR
 CONFIG_SYS_I2C_PXA
 CONFIG_SYS_I2C_QIXIS_ADDR
 CONFIG_SYS_I2C_RCAR
 CONFIG_SYS_I2C_RTC_ADDR
 CONFIG_SYS_I2C_S3C24X0_SLAVE
 CONFIG_SYS_I2C_S3C24X0_SPEED
 CONFIG_SYS_I2C_SH
 CONFIG_SYS_I2C_SH_BASE0
 CONFIG_SYS_I2C_SH_BASE1
 CONFIG_SYS_I2C_SH_BASE2
 CONFIG_SYS_I2C_SH_BASE3
 CONFIG_SYS_I2C_SH_BASE4
 CONFIG_SYS_I2C_SH_NUM_CONTROLLERS
 CONFIG_SYS_I2C_SH_SPEED0
 CONFIG_SYS_I2C_SH_SPEED1
 CONFIG_SYS_I2C_SH_SPEED2
 CONFIG_SYS_I2C_SH_SPEED3
 CONFIG_SYS_I2C_SH_SPEED4
 CONFIG_SYS_I2C_SLAVE
 CONFIG_SYS_I2C_SLAVE1
 CONFIG_SYS_I2C_SLAVE2
 CONFIG_SYS_I2C_SLAVE3
 CONFIG_SYS_I2C_SOFT
 CONFIG_SYS_I2C_SOFT_SLAVE
 CONFIG_SYS_I2C_SOFT_SLAVE_10
 CONFIG_SYS_I2C_SOFT_SLAVE_11
 CONFIG_SYS_I2C_SOFT_SLAVE_12
 CONFIG_SYS_I2C_SOFT_SLAVE_2
 CONFIG_SYS_I2C_SOFT_SLAVE_3
 CONFIG_SYS_I2C_SOFT_SLAVE_4
 CONFIG_SYS_I2C_SOFT_SLAVE_5
 CONFIG_SYS_I2C_SOFT_SLAVE_6
 CONFIG_SYS_I2C_SOFT_SLAVE_7
 CONFIG_SYS_I2C_SOFT_SLAVE_8
 CONFIG_SYS_I2C_SOFT_SLAVE_9
 CONFIG_SYS_I2C_SOFT_SPEED
 CONFIG_SYS_I2C_SOFT_SPEED_10
 CONFIG_SYS_I2C_SOFT_SPEED_11
 CONFIG_SYS_I2C_SOFT_SPEED_12
 CONFIG_SYS_I2C_SOFT_SPEED_2
 CONFIG_SYS_I2C_SOFT_SPEED_3
 CONFIG_SYS_I2C_SOFT_SPEED_4
 CONFIG_SYS_I2C_SOFT_SPEED_5
 CONFIG_SYS_I2C_SOFT_SPEED_6
 CONFIG_SYS_I2C_SOFT_SPEED_7
 CONFIG_SYS_I2C_SOFT_SPEED_8
 CONFIG_SYS_I2C_SOFT_SPEED_9
 CONFIG_SYS_I2C_SPEED
 CONFIG_SYS_I2C_SPEED1
 CONFIG_SYS_I2C_SPEED2
 CONFIG_SYS_I2C_SPEED3
 CONFIG_SYS_I2C_TCA642X_ADDR
 CONFIG_SYS_I2C_TCA642X_BUS_NUM
 CONFIG_SYS_I2C_TEGRA
 CONFIG_SYS_I2C_W83782G_ADDR
 CONFIG_SYS_I2C_ZYNQ
 CONFIG_SYS_I2C_ZYNQ_SLAVE
 CONFIG_SYS_I2C_ZYNQ_SPEED
 CONFIG_SYS_IBAT
 CONFIG_SYS_IBAT0L
 CONFIG_SYS_IBAT0U
 CONFIG_SYS_IBAT1L
 CONFIG_SYS_IBAT1U
 CONFIG_SYS_IBAT2L
 CONFIG_SYS_IBAT2U
 CONFIG_SYS_IBAT3L
 CONFIG_SYS_IBAT3U
 CONFIG_SYS_IBAT4L
 CONFIG_SYS_IBAT4U
 CONFIG_SYS_IBAT5L
 CONFIG_SYS_IBAT5U
 CONFIG_SYS_IBAT6L
 CONFIG_SYS_IBAT6L_EARLY
 CONFIG_SYS_IBAT6U
 CONFIG_SYS_IBAT6U_EARLY
 CONFIG_SYS_IBAT7L
 CONFIG_SYS_IBAT7U
 CONFIG_SYS_ICACHE_INV
 CONFIG_SYS_ICS8N3QV01_I2C
 CONFIG_SYS_IDE_MAXBUS
 CONFIG_SYS_IDE_MAXDEVICE
 CONFIG_SYS_ID_EEPROM
 CONFIG_SYS_IFC_ADDR
 CONFIG_SYS_IFC_CCR
 CONFIG_SYS_INIT_DBCR
 CONFIG_SYS_INIT_L2CSR0
 CONFIG_SYS_INIT_L2_ADDR
 CONFIG_SYS_INIT_L2_ADDR_PHYS
 CONFIG_SYS_INIT_L2_END
 CONFIG_SYS_INIT_L3_ADDR
 CONFIG_SYS_INIT_L3_ADDR_PHYS
 CONFIG_SYS_INIT_L3_END
 CONFIG_SYS_INIT_L3_VADDR
 CONFIG_SYS_INIT_RAM1_ADDR
 CONFIG_SYS_INIT_RAM1_CTRL
 CONFIG_SYS_INIT_RAM1_END
 CONFIG_SYS_INIT_RAM_ADDR
 CONFIG_SYS_INIT_RAM_ADDR_PHYS
 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW
 CONFIG_SYS_INIT_RAM_CTRL
 CONFIG_SYS_INIT_RAM_LOCK
 CONFIG_SYS_INIT_RAM_SIZE
 CONFIG_SYS_INIT_SP_ADDR
 CONFIG_SYS_INIT_SP_OFFSET
 CONFIG_SYS_INPUT_CLKSRC
 CONFIG_SYS_INTEL_BOOT
 CONFIG_SYS_INTERLAKEN
 CONFIG_SYS_INTR_BASE
 CONFIG_SYS_INTSRAM
 CONFIG_SYS_INTSRAMSZ
 CONFIG_SYS_INT_FLASH_BASE
 CONFIG_SYS_INT_FLASH_ENABLE
 CONFIG_SYS_IO_BASE
 CONFIG_SYS_ISA_BASE
 CONFIG_SYS_ISA_IO
 CONFIG_SYS_ISA_IO_BASE_ADDRESS
 CONFIG_SYS_ISA_IO_OFFSET
 CONFIG_SYS_ISA_IO_STRIDE
 CONFIG_SYS_ISA_MEM
 CONFIG_SYS_IVM_EEPROM_ADR
 CONFIG_SYS_IVM_EEPROM_MAX_LEN
 CONFIG_SYS_IVM_EEPROM_PAGE_LEN
 CONFIG_SYS_JFFS2_FIRST_BANK
 CONFIG_SYS_JFFS2_FIRST_SECTOR
 CONFIG_SYS_JFFS2_MEM_NAND
 CONFIG_SYS_JFFS2_NUM_BANKS
 CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 CONFIG_SYS_KMBEC_FPGA_BASE
 CONFIG_SYS_KMBEC_FPGA_SIZE
 CONFIG_SYS_KWD_CONFIG
 CONFIG_SYS_KW_SPI_MPP
 CONFIG_SYS_L2
 CONFIG_SYS_L2_PL310
 CONFIG_SYS_L2_SIZE
 CONFIG_SYS_L3_SIZE
 CONFIG_SYS_LATCH_ADDR
 CONFIG_SYS_LBAPP1_BASE
 CONFIG_SYS_LBAPP1_BASE_PHYS
 CONFIG_SYS_LBAPP1_BR_PRELIM
 CONFIG_SYS_LBAPP1_OR_PRELIM
 CONFIG_SYS_LBAPP2_BASE
 CONFIG_SYS_LBAPP2_BASE_PHYS
 CONFIG_SYS_LBAPP2_BR_PRELIM
 CONFIG_SYS_LBAPP2_OR_PRELIM
 CONFIG_SYS_LBC0_BASE
 CONFIG_SYS_LBC0_BASE_PHYS
 CONFIG_SYS_LBC1_BASE
 CONFIG_SYS_LBC1_BASE_PHYS
 CONFIG_SYS_LBCR_ADDR
 CONFIG_SYS_LBC_ADDR
 CONFIG_SYS_LBC_BASE
 CONFIG_SYS_LBC_BASE_PHYS_LOW
 CONFIG_SYS_LBC_CACHE_BASE
 CONFIG_SYS_LBC_FLASH_BASE
 CONFIG_SYS_LBC_LBCR
 CONFIG_SYS_LBC_LCRR
 CONFIG_SYS_LBC_LSDMR_1
 CONFIG_SYS_LBC_LSDMR_2
 CONFIG_SYS_LBC_LSDMR_3
 CONFIG_SYS_LBC_LSDMR_4
 CONFIG_SYS_LBC_LSDMR_5
 CONFIG_SYS_LBC_LSDMR_ARFRSH
 CONFIG_SYS_LBC_LSDMR_COMMON
 CONFIG_SYS_LBC_LSDMR_MRW
 CONFIG_SYS_LBC_LSDMR_PCHALL
 CONFIG_SYS_LBC_LSDMR_RFEN
 CONFIG_SYS_LBC_LSRT
 CONFIG_SYS_LBC_MRTPR
 CONFIG_SYS_LBC_NONCACHE_BASE
 CONFIG_SYS_LBC_SDRAM_BASE
 CONFIG_SYS_LBC_SDRAM_BASE_PHYS
 CONFIG_SYS_LBC_SDRAM_SIZE
 CONFIG_SYS_LBLAWAR0_PRELIM
 CONFIG_SYS_LBLAWAR1_PRELIM
 CONFIG_SYS_LBLAWAR2_PRELIM
 CONFIG_SYS_LBLAWAR3_PRELIM
 CONFIG_SYS_LBLAWAR4_PRELIM
 CONFIG_SYS_LBLAWAR5_PRELIM
 CONFIG_SYS_LBLAWAR6_PRELIM
 CONFIG_SYS_LBLAWAR7_PRELIM
 CONFIG_SYS_LBLAWBAR0_PRELIM
 CONFIG_SYS_LBLAWBAR1_PRELIM
 CONFIG_SYS_LBLAWBAR2_PRELIM
 CONFIG_SYS_LBLAWBAR3_PRELIM
 CONFIG_SYS_LBLAWBAR4_PRELIM
 CONFIG_SYS_LBLAWBAR5_PRELIM
 CONFIG_SYS_LBLAWBAR6_PRELIM
 CONFIG_SYS_LBLAWBAR7_PRELIM
 CONFIG_SYS_LB_SDRAM
 CONFIG_SYS_LCD_BASE
 CONFIG_SYS_LCRR_CLKDIV
 CONFIG_SYS_LCRR_DBYP
 CONFIG_SYS_LCRR_EADC
 CONFIG_SYS_LDB_CLOCK
 CONFIG_SYS_LDSCRIPT
 CONFIG_SYS_LED_BASE
 CONFIG_SYS_LED_DISP_BASE
 CONFIG_SYS_LIME_BASE
 CONFIG_SYS_LIME_SIZE
 CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
 CONFIG_SYS_LOADS_BAUD_CHANGE
 CONFIG_SYS_LOAD_ADDR
 CONFIG_SYS_LOAD_ADDR2
 CONFIG_SYS_LONGHELP
 CONFIG_SYS_LOW
 CONFIG_SYS_LOWBOOT
 CONFIG_SYS_LOWMEM_BASE
 CONFIG_SYS_LOW_RES_TIMER
 CONFIG_SYS_LPAE_SDRAM_BASE
 CONFIG_SYS_LPC32XX_UART
 CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
 CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
 CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
 CONFIG_SYS_LS_MC_DPC_ADDR
 CONFIG_SYS_LS_MC_DPC_IN_DDR
 CONFIG_SYS_LS_MC_DPC_IN_NOR
 CONFIG_SYS_LS_MC_DPC_MAX_LENGTH
 CONFIG_SYS_LS_MC_DPL_ADDR
 CONFIG_SYS_LS_MC_DPL_IN_DDR
 CONFIG_SYS_LS_MC_DPL_IN_NOR
 CONFIG_SYS_LS_MC_DPL_MAX_LENGTH
 CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
 CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
 CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
 CONFIG_SYS_LS_MC_FW_IN_DDR
 CONFIG_SYS_LS_PPA_FW_IN_xxx
 CONFIG_SYS_M41T11_BASE_YEAR
 CONFIG_SYS_M41T11_EXT_CENTURY_DATA
 CONFIG_SYS_MACB0_BASE
 CONFIG_SYS_MACB1_BASE
 CONFIG_SYS_MACB2_BASE
 CONFIG_SYS_MACB3_BASE
 CONFIG_SYS_MAIN_PWR_ON
 CONFIG_SYS_MALLOC_BASE
 CONFIG_SYS_MALLOC_LEN
 CONFIG_SYS_MALLOC_SIMPLE
 CONFIG_SYS_MAMR
 CONFIG_SYS_MAPLE
 CONFIG_SYS_MAPLE_MEM_PHYS
 CONFIG_SYS_MAPPED_RAM_BASE
 CONFIG_SYS_MARUBUN_IO
 CONFIG_SYS_MARUBUN_MRSHPC
 CONFIG_SYS_MARUBUN_MW1
 CONFIG_SYS_MARUBUN_MW2
 CONFIG_SYS_MASTER_CLOCK
 CONFIG_SYS_MATRIX_EBI0CSA_VAL
 CONFIG_SYS_MATRIX_EBICSA_VAL
 CONFIG_SYS_MATRIX_MCFG_REMAP
 CONFIG_SYS_MAXARGS
 CONFIG_SYS_MAX_DDR_BAT_SIZE
 CONFIG_SYS_MAX_FLASH_BANKS
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 CONFIG_SYS_MAX_FLASH_SECT
 CONFIG_SYS_MAX_I2C_BUS
 CONFIG_SYS_MAX_MTD_BANKS
 CONFIG_SYS_MAX_NAND_CHIPS
 CONFIG_SYS_MAX_NAND_DEVICE
 CONFIG_SYS_MAX_PCI_EPS
 CONFIG_SYS_MB862xx_CCF
 CONFIG_SYS_MB862xx_MMR
 CONFIG_SYS_MBAR
 CONFIG_SYS_MBAR2
 CONFIG_SYS_MBYTES_SDRAM
 CONFIG_SYS_MCATT0_VAL
 CONFIG_SYS_MCATT1_VAL
 CONFIG_SYS_MCFRRTC_BASE
 CONFIG_SYS_MCFRTC_BASE
 CONFIG_SYS_MCF_SYNCR
 CONFIG_SYS_MCIO0_VAL
 CONFIG_SYS_MCIO1_VAL
 CONFIG_SYS_MCKR
 CONFIG_SYS_MCKR1_VAL
 CONFIG_SYS_MCKR2_VAL
 CONFIG_SYS_MCKR_CSS
 CONFIG_SYS_MCKR_VAL
 CONFIG_SYS_MCLINK_MAX
 CONFIG_SYS_MCMEM0_VAL
 CONFIG_SYS_MCMEM1_VAL
 CONFIG_SYS_MDC1_PIN
 CONFIG_SYS_MDCNFG_VAL
 CONFIG_SYS_MDC_PIN
 CONFIG_SYS_MDIO1_OFFSET
 CONFIG_SYS_MDIO1_PIN
 CONFIG_SYS_MDIO_BASE_ADDR
 CONFIG_SYS_MDIO_PIN
 CONFIG_SYS_MDMRS_VAL
 CONFIG_SYS_MDREFR_VAL
 CONFIG_SYS_MECR_VAL
 CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 CONFIG_SYS_MEMORY_BASE
 CONFIG_SYS_MEMORY_SIZE
 CONFIG_SYS_MEMORY_TOP
 CONFIG_SYS_MEMTEST_END
 CONFIG_SYS_MEMTEST_SCRATCH
 CONFIG_SYS_MEMTEST_START
 CONFIG_SYS_MEM_MAP
 CONFIG_SYS_MEM_RESERVE_SECURE
 CONFIG_SYS_MEM_SIZE
 CONFIG_SYS_MEM_TOP_HIDE
 CONFIG_SYS_MFD
 CONFIG_SYS_MHZ
 CONFIG_SYS_MII_MODE
 CONFIG_SYS_MIPS_CACHE_MODE
 CONFIG_SYS_MIPS_TIMER_FREQ
 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
 CONFIG_SYS_MMC_BASE
 CONFIG_SYS_MMC_CD_PIN
 CONFIG_SYS_MMC_CLK_OD
 CONFIG_SYS_MMC_ENV_DEV
 CONFIG_SYS_MMC_ENV_PART
 CONFIG_SYS_MMC_MAX_BLK_COUNT
 CONFIG_SYS_MMC_MAX_DEVICE
 CONFIG_SYS_MMC_U_BOOT_DST
 CONFIG_SYS_MMC_U_BOOT_OFFS
 CONFIG_SYS_MMC_U_BOOT_SIZE
 CONFIG_SYS_MMC_U_BOOT_START
 CONFIG_SYS_MONITOR_
 CONFIG_SYS_MONITOR_BASE
 CONFIG_SYS_MONITOR_BASE_EARLY
 CONFIG_SYS_MONITOR_LEN
 CONFIG_SYS_MONITOR_SEC
 CONFIG_SYS_MOR_VAL
 CONFIG_SYS_MPC83xx_DMA_ADDR
 CONFIG_SYS_MPC83xx_DMA_OFFSET
 CONFIG_SYS_MPC83xx_ESDHC_ADDR
 CONFIG_SYS_MPC83xx_ESDHC_OFFSET
 CONFIG_SYS_MPC83xx_USB1_ADDR
 CONFIG_SYS_MPC83xx_USB1_OFFSET
 CONFIG_SYS_MPC83xx_USB2_ADDR
 CONFIG_SYS_MPC83xx_USB2_OFFSET
 CONFIG_SYS_MPC85XX_NO_RESETVEC
 CONFIG_SYS_MPC85xx_CPM_ADDR
 CONFIG_SYS_MPC85xx_CPM_OFFSET
 CONFIG_SYS_MPC85xx_DMA
 CONFIG_SYS_MPC85xx_DMA1_OFFSET
 CONFIG_SYS_MPC85xx_DMA2_OFFSET
 CONFIG_SYS_MPC85xx_DMA3_OFFSET
 CONFIG_SYS_MPC85xx_DMA_ADDR
 CONFIG_SYS_MPC85xx_DMA_OFFSET
 CONFIG_SYS_MPC85xx_ECM_ADDR
 CONFIG_SYS_MPC85xx_ECM_OFFSET
 CONFIG_SYS_MPC85xx_ESDHC_ADDR
 CONFIG_SYS_MPC85xx_ESDHC_OFFSET
 CONFIG_SYS_MPC85xx_ESPI_ADDR
 CONFIG_SYS_MPC85xx_ESPI_OFFSET
 CONFIG_SYS_MPC85xx_GPIO3_ADDR
 CONFIG_SYS_MPC85xx_GPIO_ADDR
 CONFIG_SYS_MPC85xx_GPIO_OFFSET
 CONFIG_SYS_MPC85xx_GUTS_ADDR
 CONFIG_SYS_MPC85xx_GUTS_OFFSET
 CONFIG_SYS_MPC85xx_IFC_OFFSET
 CONFIG_SYS_MPC85xx_L2_ADDR
 CONFIG_SYS_MPC85xx_L2_OFFSET
 CONFIG_SYS_MPC85xx_LBC_OFFSET
 CONFIG_SYS_MPC85xx_PCI1_OFFSET
 CONFIG_SYS_MPC85xx_PCI2_OFFSET
 CONFIG_SYS_MPC85xx_PCIE
 CONFIG_SYS_MPC85xx_PCIE1_OFFSET
 CONFIG_SYS_MPC85xx_PCIE2_OFFSET
 CONFIG_SYS_MPC85xx_PCIE3_OFFSET
 CONFIG_SYS_MPC85xx_PCIE4_OFFSET
 CONFIG_SYS_MPC85xx_PCIX2_ADDR
 CONFIG_SYS_MPC85xx_PCIX2_OFFSET
 CONFIG_SYS_MPC85xx_PCIX_ADDR
 CONFIG_SYS_MPC85xx_PCIX_OFFSET
 CONFIG_SYS_MPC85xx_PIC_OFFSET
 CONFIG_SYS_MPC85xx_QE_OFFSET
 CONFIG_SYS_MPC85xx_SATA
 CONFIG_SYS_MPC85xx_SATA1_ADDR
 CONFIG_SYS_MPC85xx_SATA1_OFFSET
 CONFIG_SYS_MPC85xx_SATA2_ADDR
 CONFIG_SYS_MPC85xx_SATA2_OFFSET
 CONFIG_SYS_MPC85xx_SCFG
 CONFIG_SYS_MPC85xx_SCFG_OFFSET
 CONFIG_SYS_MPC85xx_SERDES1_ADDR
 CONFIG_SYS_MPC85xx_SERDES1_OFFSET
 CONFIG_SYS_MPC85xx_SERDES2_ADDR
 CONFIG_SYS_MPC85xx_SERDES2_OFFSET
 CONFIG_SYS_MPC85xx_TDM_OFFSET
 CONFIG_SYS_MPC85xx_USB
 CONFIG_SYS_MPC85xx_USB1_ADDR
 CONFIG_SYS_MPC85xx_USB1_OFFSET
 CONFIG_SYS_MPC85xx_USB1_PHY_ADDR
 CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET
 CONFIG_SYS_MPC85xx_USB2_ADDR
 CONFIG_SYS_MPC85xx_USB2_OFFSET
 CONFIG_SYS_MPC85xx_USB2_PHY_ADDR
 CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET
 CONFIG_SYS_MPC86xx_DMA_ADDR
 CONFIG_SYS_MPC86xx_DMA_OFFSET
 CONFIG_SYS_MPC86xx_PCI1_OFFSET
 CONFIG_SYS_MPC86xx_PCI2_OFFSET
 CONFIG_SYS_MPC86xx_PCIE1_OFFSET
 CONFIG_SYS_MPC86xx_PCIE2_OFFSET
 CONFIG_SYS_MPC86xx_PIC_OFFSET
 CONFIG_SYS_MPC8xxx_DDR2_OFFSET
 CONFIG_SYS_MPC8xxx_DDR3_OFFSET
 CONFIG_SYS_MPC8xxx_DDR_OFFSET
 CONFIG_SYS_MPC8xxx_GUTS_ADDR
 CONFIG_SYS_MPC8xxx_PIC_ADDR
 CONFIG_SYS_MPC92469AC
 CONFIG_SYS_MRAM_BASE
 CONFIG_SYS_MRAM_SIZE
 CONFIG_SYS_MSC0_VAL
 CONFIG_SYS_MSC1_VAL
 CONFIG_SYS_MSC2_VAL
 CONFIG_SYS_MTDPARTS_RUNTIME
 CONFIG_SYS_MVFS
 CONFIG_SYS_MX5_CLK32
 CONFIG_SYS_MX5_HCLK
 CONFIG_SYS_MX6_CLK32
 CONFIG_SYS_MX6_HCLK
 CONFIG_SYS_MX7_CLK32
 CONFIG_SYS_MX7_HCLK
 CONFIG_SYS_MXC_I2C1_SLAVE
 CONFIG_SYS_MXC_I2C1_SPEED
 CONFIG_SYS_MXC_I2C2_SLAVE
 CONFIG_SYS_MXC_I2C2_SPEED
 CONFIG_SYS_MXC_I2C3_SLAVE
 CONFIG_SYS_MXC_I2C3_SPEED
 CONFIG_SYS_MXC_I2C4_SLAVE
 CONFIG_SYS_MXC_I2C4_SPEED
 CONFIG_SYS_MXS_VDD5V_ONLY
 CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 CONFIG_SYS_NAND_4_ADDR_CYCLE
 CONFIG_SYS_NAND_5_ADDR_CYCLE
 CONFIG_SYS_NAND_ACTL_ALE
 CONFIG_SYS_NAND_ACTL_CLE
 CONFIG_SYS_NAND_ACTL_DELAY
 CONFIG_SYS_NAND_ACTL_NCE
 CONFIG_SYS_NAND_ADDR
 CONFIG_SYS_NAND_ALE
 CONFIG_SYS_NAND_AMASK
 CONFIG_SYS_NAND_BAD_BLOCK_POS
 CONFIG_SYS_NAND_BASE
 CONFIG_SYS_NAND_BASE2
 CONFIG_SYS_NAND_BASE_LIST
 CONFIG_SYS_NAND_BASE_PHYS
 CONFIG_SYS_NAND_BCR
 CONFIG_SYS_NAND_BLOCK_SIZE
 CONFIG_SYS_NAND_BOOT
 CONFIG_SYS_NAND_BR_PRELIM
 CONFIG_SYS_NAND_BUSWIDTH_16
 CONFIG_SYS_NAND_CLE
 CONFIG_SYS_NAND_CS
 CONFIG_SYS_NAND_CSOR
 CONFIG_SYS_NAND_CSPR
 CONFIG_SYS_NAND_CSPR_EXT
 CONFIG_SYS_NAND_DATA_BASE
 CONFIG_SYS_NAND_DBW_16
 CONFIG_SYS_NAND_DBW_8
 CONFIG_SYS_NAND_DDR_LAW
 CONFIG_SYS_NAND_ECCBYTES
 CONFIG_SYS_NAND_ECCPOS
 CONFIG_SYS_NAND_ECCSIZE
 CONFIG_SYS_NAND_ECCSTEPS
 CONFIG_SYS_NAND_ECCTOTAL
 CONFIG_SYS_NAND_ECC_BASE
 CONFIG_SYS_NAND_ENABLE_PIN
 CONFIG_SYS_NAND_ENABLE_PIN_SPL
 CONFIG_SYS_NAND_FTIM0
 CONFIG_SYS_NAND_FTIM1
 CONFIG_SYS_NAND_FTIM2
 CONFIG_SYS_NAND_FTIM3
 CONFIG_SYS_NAND_HW_ECC
 CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 CONFIG_SYS_NAND_LARGEPAGE
 CONFIG_SYS_NAND_LBLAWAR_PRELIM
 CONFIG_SYS_NAND_LBLAWBAR_PRELIM
 CONFIG_SYS_NAND_MASK_ALE
 CONFIG_SYS_NAND_MASK_CLE
 CONFIG_SYS_NAND_MAX_CHIPS
 CONFIG_SYS_NAND_MAX_ECCPOS
 CONFIG_SYS_NAND_MAX_OOBFREE
 CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
 CONFIG_SYS_NAND_NO_SUBPAGE
 CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
 CONFIG_SYS_NAND_ONFI_DETECTION
 CONFIG_SYS_NAND_OOBSIZE
 CONFIG_SYS_NAND_OR_PRELIM
 CONFIG_SYS_NAND_PAGE_2K
 CONFIG_SYS_NAND_PAGE_4K
 CONFIG_SYS_NAND_PAGE_COUNT
 CONFIG_SYS_NAND_PAGE_SIZE
 CONFIG_SYS_NAND_QUIET
 CONFIG_SYS_NAND_READY_PIN
 CONFIG_SYS_NAND_REGS_BASE
 CONFIG_SYS_NAND_SELECT_DEVICE
 CONFIG_SYS_NAND_SIZE
 CONFIG_SYS_NAND_SPL_KERNEL_OFFS
 CONFIG_SYS_NAND_SPL_SIZE
 CONFIG_SYS_NAND_USE_FLASH_BBT
 CONFIG_SYS_NAND_U_BOOT_DST
 CONFIG_SYS_NAND_U_BOOT_RELOC
 CONFIG_SYS_NAND_U_BOOT_RELOC_SP
 CONFIG_SYS_NAND_U_BOOT_SIZE
 CONFIG_SYS_NAND_U_BOOT_START
 CONFIG_SYS_NAND_WINDOW_SIZE
 CONFIG_SYS_NDFC_EBC0_CFG
 CONFIG_SYS_NETA_INTERFACE_TYPE
 CONFIG_SYS_NONCACHED_MEMORY
 CONFIG_SYS_NOR0_CSPR
 CONFIG_SYS_NOR0_CSPR_EARLY
 CONFIG_SYS_NOR0_CSPR_EXT
 CONFIG_SYS_NOR1SZ
 CONFIG_SYS_NOR1_CSPR
 CONFIG_SYS_NOR1_CSPR_EARLY
 CONFIG_SYS_NOR1_CSPR_EXT
 CONFIG_SYS_NOR_AMASK
 CONFIG_SYS_NOR_AMASK_EARLY
 CONFIG_SYS_NOR_BR_PRELIM
 CONFIG_SYS_NOR_CSOR
 CONFIG_SYS_NOR_CSPR
 CONFIG_SYS_NOR_CSPR_EXT
 CONFIG_SYS_NOR_FTIM0
 CONFIG_SYS_NOR_FTIM1
 CONFIG_SYS_NOR_FTIM2
 CONFIG_SYS_NOR_FTIM3
 CONFIG_SYS_NOR_OR_PRELIM
 CONFIG_SYS_NO_DCACHE
 CONFIG_SYS_NS16550_CLK
 CONFIG_SYS_NS16550_CLK_DIV
 CONFIG_SYS_NS16550_COM1
 CONFIG_SYS_NS16550_COM2
 CONFIG_SYS_NS16550_COM3
 CONFIG_SYS_NS16550_COM4
 CONFIG_SYS_NS16550_COM5
 CONFIG_SYS_NS16550_COM6
 CONFIG_SYS_NS16550_IER
 CONFIG_SYS_NS16550_MEM32
 CONFIG_SYS_NS16550_PORT_MAPPED
 CONFIG_SYS_NS16550_REG_SIZE
 CONFIG_SYS_NS16550_SERIAL
 CONFIG_SYS_NS87308_CS0_BASE
 CONFIG_SYS_NS87308_CS0_CONF
 CONFIG_SYS_NS87308_CS1_BASE
 CONFIG_SYS_NS87308_CS1_CONF
 CONFIG_SYS_NS87308_CS2_BASE
 CONFIG_SYS_NS87308_CS2_CONF
 CONFIG_SYS_NS87308_FDC
 CONFIG_SYS_NS87308_FDC_BASE
 CONFIG_SYS_NS87308_GPIO
 CONFIG_SYS_NS87308_GPIO_BASE
 CONFIG_SYS_NS87308_KBC1
 CONFIG_SYS_NS87308_KBC1_BASE
 CONFIG_SYS_NS87308_KBC2
 CONFIG_SYS_NS87308_LPT_BASE
 CONFIG_SYS_NS87308_MOUSE
 CONFIG_SYS_NS87308_PARP
 CONFIG_SYS_NS87308_PMC1
 CONFIG_SYS_NS87308_PMC2
 CONFIG_SYS_NS87308_PMC3
 CONFIG_SYS_NS87308_POWRMAN
 CONFIG_SYS_NS87308_PS2MOD
 CONFIG_SYS_NS87308_PWMAN_BASE
 CONFIG_SYS_NS87308_RARP
 CONFIG_SYS_NS87308_RTC_APC
 CONFIG_SYS_NS87308_RTC_BASE
 CONFIG_SYS_NS87308_UART1
 CONFIG_SYS_NS87308_UART1_BASE
 CONFIG_SYS_NS87308_UART2
 CONFIG_SYS_NS87308_UART2_BASE
 CONFIG_SYS_NUM_ADDR_MAP
 CONFIG_SYS_NUM_CPC
 CONFIG_SYS_NUM_FM1_10GEC
 CONFIG_SYS_NUM_FM1_DTSEC
 CONFIG_SYS_NUM_FM2_10GEC
 CONFIG_SYS_NUM_FM2_DTSEC
 CONFIG_SYS_NUM_FMAN
 CONFIG_SYS_NUM_I2C_BUSES
 CONFIG_SYS_NUM_IRQS
 CONFIG_SYS_NVRAM_ACCESS_ROUTINE
 CONFIG_SYS_NVRAM_BASE_ADDR
 CONFIG_SYS_NVRAM_SIZE
 CONFIG_SYS_OBIR
 CONFIG_SYS_OHCI_BE_CONTROLLER
 CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 CONFIG_SYS_OMAP24_I2C_SLAVE
 CONFIG_SYS_OMAP24_I2C_SLAVE1
 CONFIG_SYS_OMAP24_I2C_SLAVE2
 CONFIG_SYS_OMAP24_I2C_SLAVE3
 CONFIG_SYS_OMAP24_I2C_SLAVE4
 CONFIG_SYS_OMAP24_I2C_SPEED
 CONFIG_SYS_OMAP24_I2C_SPEED1
 CONFIG_SYS_OMAP24_I2C_SPEED2
 CONFIG_SYS_OMAP24_I2C_SPEED3
 CONFIG_SYS_OMAP24_I2C_SPEED4
 CONFIG_SYS_OMAP24_I2C_SPEED_PSOC
 CONFIG_SYS_OMAP_ABE_SYSCK
 CONFIG_SYS_ONENAND_BASE
 CONFIG_SYS_ONENAND_BLOCK_SIZE
 CONFIG_SYS_ONENAND_PAGE_SIZE
 CONFIG_SYS_OR0_64M
 CONFIG_SYS_OR0_8M
 CONFIG_SYS_OR0_REMAP
 CONFIG_SYS_OR1_REMAP
 CONFIG_SYS_OR6_64M
 CONFIG_SYS_OR6_8M
 CONFIG_SYS_OR_TIMING_FLASH
 CONFIG_SYS_OR_TIMING_MRAM
 CONFIG_SYS_OSCIN_FREQ
 CONFIG_SYS_OSD_DH
 CONFIG_SYS_OSD_SCREENS
 CONFIG_SYS_OSPR_OFFSET
 CONFIG_SYS_PACNT
 CONFIG_SYS_PADAT
 CONFIG_SYS_PADDR
 CONFIG_SYS_PAGE_SIZE
 CONFIG_SYS_PAMU_ADDR
 CONFIG_SYS_PASPAR
 CONFIG_SYS_PAXE_BASE
 CONFIG_SYS_PAXE_SIZE
 CONFIG_SYS_PBCNT
 CONFIG_SYS_PBDAT
 CONFIG_SYS_PBDDR
 CONFIG_SYS_PBI_FLASH_BASE
 CONFIG_SYS_PBI_FLASH_WINDOW
 CONFIG_SYS_PBSIZE
 CONFIG_SYS_PCA953X_BRD_CFG0
 CONFIG_SYS_PCA953X_BRD_CFG1
 CONFIG_SYS_PCA953X_BRD_CFG2
 CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS
 CONFIG_SYS_PCA953X_C0_SER0_EN
 CONFIG_SYS_PCA953X_C0_SER0_MODE
 CONFIG_SYS_PCA953X_C0_SER1_EN
 CONFIG_SYS_PCA953X_C0_SER1_MODE
 CONFIG_SYS_PCA953X_C0_VCORE_VID2
 CONFIG_SYS_PCA953X_C0_VCORE_VID3
 CONFIG_SYS_PCA953X_EREADY
 CONFIG_SYS_PCA953X_FLASH_PASS_CS
 CONFIG_SYS_PCA953X_GPIO_VPX0
 CONFIG_SYS_PCA953X_GPIO_VPX1
 CONFIG_SYS_PCA953X_GPIO_VPX2
 CONFIG_SYS_PCA953X_GPIO_VPX3
 CONFIG_SYS_PCA953X_MC_GPIO0
 CONFIG_SYS_PCA953X_MC_GPIO1
 CONFIG_SYS_PCA953X_MC_GPIO2
 CONFIG_SYS_PCA953X_MC_GPIO3
 CONFIG_SYS_PCA953X_MC_GPIO4
 CONFIG_SYS_PCA953X_MC_GPIO5
 CONFIG_SYS_PCA953X_MC_GPIO6
 CONFIG_SYS_PCA953X_MC_GPIO7
 CONFIG_SYS_PCA953X_MONARCH
 CONFIG_SYS_PCA953X_NVM_WP
 CONFIG_SYS_PCA953X_P0_GA0
 CONFIG_SYS_PCA953X_P0_GA1
 CONFIG_SYS_PCA953X_P0_GA2
 CONFIG_SYS_PCA953X_P0_GA3
 CONFIG_SYS_PCA953X_P0_GA4
 CONFIG_SYS_PCA953X_P0_GAP
 CONFIG_SYS_PCA953X_P14_IO0
 CONFIG_SYS_PCA953X_P14_IO1
 CONFIG_SYS_PCA953X_P14_IO2
 CONFIG_SYS_PCA953X_P14_IO3
 CONFIG_SYS_PCA953X_P14_IO4
 CONFIG_SYS_PCA953X_P14_IO5
 CONFIG_SYS_PCA953X_P14_IO6
 CONFIG_SYS_PCA953X_P14_IO7
 CONFIG_SYS_PCA953X_P1_SYSEN
 CONFIG_SYS_PCA953X_PLUG_GPIO0
 CONFIG_SYS_PCA953X_PMC0_EREADY
 CONFIG_SYS_PCA953X_PMC0_MONARCH
 CONFIG_SYS_PCA953X_PMC_EREADY
 CONFIG_SYS_PCA953X_PMC_MONARCH
 CONFIG_SYS_PCA953X_PMC_PRESENT
 CONFIG_SYS_PCA953X_VPX_FRU_WRCTL
 CONFIG_SYS_PCA953X_VPX_GPIO0
 CONFIG_SYS_PCA953X_VPX_GPIO1
 CONFIG_SYS_PCA953X_VPX_GPIO2
 CONFIG_SYS_PCA953X_VPX_GPIO3
 CONFIG_SYS_PCA953X_XMC0_BIST
 CONFIG_SYS_PCA953X_XMC0_MVMR0
 CONFIG_SYS_PCA953X_XMC0_ROOT0
 CONFIG_SYS_PCA953X_XMC0_WAKE
 CONFIG_SYS_PCA953X_XMC_BIST
 CONFIG_SYS_PCA953X_XMC_GA0
 CONFIG_SYS_PCA953X_XMC_GA1
 CONFIG_SYS_PCA953X_XMC_GA2
 CONFIG_SYS_PCA953X_XMC_PRESENT
 CONFIG_SYS_PCA953X_XMC_ROOT0
 CONFIG_SYS_PCA953X_XMC_WAKE
 CONFIG_SYS_PCCNT
 CONFIG_SYS_PCDAT
 CONFIG_SYS_PCDDR
 CONFIG_SYS_PCI
 CONFIG_SYS_PCI1_ADDR
 CONFIG_SYS_PCI1_IO_BASE
 CONFIG_SYS_PCI1_IO_BUS
 CONFIG_SYS_PCI1_IO_PHYS
 CONFIG_SYS_PCI1_IO_SIZE
 CONFIG_SYS_PCI1_IO_VIRT
 CONFIG_SYS_PCI1_MEM_BASE
 CONFIG_SYS_PCI1_MEM_BUS
 CONFIG_SYS_PCI1_MEM_PHYS
 CONFIG_SYS_PCI1_MEM_SIZE
 CONFIG_SYS_PCI1_MEM_VIRT
 CONFIG_SYS_PCI1_MMIO_BASE
 CONFIG_SYS_PCI1_MMIO_PHYS
 CONFIG_SYS_PCI1_MMIO_SIZE
 CONFIG_SYS_PCI2_ADDR
 CONFIG_SYS_PCI2_IO_BASE
 CONFIG_SYS_PCI2_IO_BUS
 CONFIG_SYS_PCI2_IO_PHYS
 CONFIG_SYS_PCI2_IO_SIZE
 CONFIG_SYS_PCI2_IO_VIRT
 CONFIG_SYS_PCI2_MEM_BASE
 CONFIG_SYS_PCI2_MEM_BUS
 CONFIG_SYS_PCI2_MEM_PHYS
 CONFIG_SYS_PCI2_MEM_SIZE
 CONFIG_SYS_PCI2_MEM_VIRT
 CONFIG_SYS_PCI2_MMIO_BASE
 CONFIG_SYS_PCI2_MMIO_PHYS
 CONFIG_SYS_PCI2_MMIO_SIZE
 CONFIG_SYS_PCI64_MEMORY_BUS
 CONFIG_SYS_PCIE
 CONFIG_SYS_PCIE1_ADDR
 CONFIG_SYS_PCIE1_BASE
 CONFIG_SYS_PCIE1_CFG_BASE
 CONFIG_SYS_PCIE1_CFG_SIZE
 CONFIG_SYS_PCIE1_IO_BASE
 CONFIG_SYS_PCIE1_IO_BUS
 CONFIG_SYS_PCIE1_IO_PHYS
 CONFIG_SYS_PCIE1_IO_PHYS_LOW
 CONFIG_SYS_PCIE1_IO_SIZE
 CONFIG_SYS_PCIE1_IO_VIRT
 CONFIG_SYS_PCIE1_MEM_BASE
 CONFIG_SYS_PCIE1_MEM_BUS
 CONFIG_SYS_PCIE1_MEM_PHYS
 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 CONFIG_SYS_PCIE1_MEM_PHYS_LOW
 CONFIG_SYS_PCIE1_MEM_SIZE
 CONFIG_SYS_PCIE1_MEM_VIRT
 CONFIG_SYS_PCIE1_NAME
 CONFIG_SYS_PCIE1_PHYS_ADDR
 CONFIG_SYS_PCIE1_PHYS_BASE
 CONFIG_SYS_PCIE1_PHYS_SIZE
 CONFIG_SYS_PCIE1_VIRT_ADDR
 CONFIG_SYS_PCIE2_ADDR
 CONFIG_SYS_PCIE2_BASE
 CONFIG_SYS_PCIE2_CFG_BASE
 CONFIG_SYS_PCIE2_CFG_SIZE
 CONFIG_SYS_PCIE2_IO_BASE
 CONFIG_SYS_PCIE2_IO_BUS
 CONFIG_SYS_PCIE2_IO_PHYS
 CONFIG_SYS_PCIE2_IO_PHYS_LOW
 CONFIG_SYS_PCIE2_IO_SIZE
 CONFIG_SYS_PCIE2_IO_VIRT
 CONFIG_SYS_PCIE2_MEM_BASE
 CONFIG_SYS_PCIE2_MEM_BUS
 CONFIG_SYS_PCIE2_MEM_PHYS
 CONFIG_SYS_PCIE2_MEM_PHYS_HIGH
 CONFIG_SYS_PCIE2_MEM_PHYS_LOW
 CONFIG_SYS_PCIE2_MEM_SIZE
 CONFIG_SYS_PCIE2_MEM_VIRT
 CONFIG_SYS_PCIE2_NAME
 CONFIG_SYS_PCIE2_PHYS_ADDR
 CONFIG_SYS_PCIE2_PHYS_BASE
 CONFIG_SYS_PCIE2_PHYS_SIZE
 CONFIG_SYS_PCIE2_VIRT_ADDR
 CONFIG_SYS_PCIE3_ADDR
 CONFIG_SYS_PCIE3_IO_BUS
 CONFIG_SYS_PCIE3_IO_PHYS
 CONFIG_SYS_PCIE3_IO_SIZE
 CONFIG_SYS_PCIE3_IO_VIRT
 CONFIG_SYS_PCIE3_MEM_BUS
 CONFIG_SYS_PCIE3_MEM_BUS2
 CONFIG_SYS_PCIE3_MEM_PHYS
 CONFIG_SYS_PCIE3_MEM_PHYS2
 CONFIG_SYS_PCIE3_MEM_SIZE
 CONFIG_SYS_PCIE3_MEM_SIZE2
 CONFIG_SYS_PCIE3_MEM_VIRT
 CONFIG_SYS_PCIE3_MEM_VIRT2
 CONFIG_SYS_PCIE3_NAME
 CONFIG_SYS_PCIE3_PHYS_ADDR
 CONFIG_SYS_PCIE3_PHYS_SIZE
 CONFIG_SYS_PCIE4_ADDR
 CONFIG_SYS_PCIE4_IO_BUS
 CONFIG_SYS_PCIE4_IO_PHYS
 CONFIG_SYS_PCIE4_IO_SIZE
 CONFIG_SYS_PCIE4_IO_VIRT
 CONFIG_SYS_PCIE4_MEM_BUS
 CONFIG_SYS_PCIE4_MEM_PHYS
 CONFIG_SYS_PCIE4_MEM_SIZE
 CONFIG_SYS_PCIE4_MEM_VIRT
 CONFIG_SYS_PCIE4_NAME
 CONFIG_SYS_PCIE4_PHYS_ADDR
 CONFIG_SYS_PCIE4_PHYS_SIZE
 CONFIG_SYS_PCIE_MMAP_SIZE
 CONFIG_SYS_PCIE_PHYS
 CONFIG_SYS_PCIE_VIRT
 CONFIG_SYS_PCI_64BIT
 CONFIG_SYS_PCI_BAR0
 CONFIG_SYS_PCI_BAR1
 CONFIG_SYS_PCI_BAR2
 CONFIG_SYS_PCI_BAR3
 CONFIG_SYS_PCI_BAR4
 CONFIG_SYS_PCI_BAR5
 CONFIG_SYS_PCI_CACHE_LINE_SIZE
 CONFIG_SYS_PCI_CFG_BASE
 CONFIG_SYS_PCI_CFG_BUS
 CONFIG_SYS_PCI_CFG_PHYS
 CONFIG_SYS_PCI_CFG_SIZE
 CONFIG_SYS_PCI_EP_MEMORY_BASE
 CONFIG_SYS_PCI_IO_BASE
 CONFIG_SYS_PCI_IO_BUS
 CONFIG_SYS_PCI_IO_PHYS
 CONFIG_SYS_PCI_IO_SIZE
 CONFIG_SYS_PCI_MAP_END
 CONFIG_SYS_PCI_MAP_START
 CONFIG_SYS_PCI_MEMORY_BUS
 CONFIG_SYS_PCI_MEMORY_PHYS
 CONFIG_SYS_PCI_MEMORY_SIZE
 CONFIG_SYS_PCI_MEM_BASE
 CONFIG_SYS_PCI_MEM_BUS
 CONFIG_SYS_PCI_MEM_PHYS
 CONFIG_SYS_PCI_MEM_SIZE
 CONFIG_SYS_PCI_MMIO_BASE
 CONFIG_SYS_PCI_MMIO_PHYS
 CONFIG_SYS_PCI_MMIO_SIZE
 CONFIG_SYS_PCI_NR_INBOUND_WIN
 CONFIG_SYS_PCI_PHYS
 CONFIG_SYS_PCI_SLV_MEM_BUS
 CONFIG_SYS_PCI_SLV_MEM_LOCAL
 CONFIG_SYS_PCI_SLV_MEM_SIZE
 CONFIG_SYS_PCI_SUBSYS_VENDORID
 CONFIG_SYS_PCI_SYS_MEM_BUS
 CONFIG_SYS_PCI_SYS_MEM_PHYS
 CONFIG_SYS_PCI_SYS_MEM_SIZE
 CONFIG_SYS_PCI_TBATR0
 CONFIG_SYS_PCI_TBATR1
 CONFIG_SYS_PCI_TBATR2
 CONFIG_SYS_PCI_TBATR3
 CONFIG_SYS_PCI_TBATR4
 CONFIG_SYS_PCI_TBATR5
 CONFIG_SYS_PCI_VIRT
 CONFIG_SYS_PCMCIA_ATTR_BASE
 CONFIG_SYS_PCMCIA_IO_BASE
 CONFIG_SYS_PCMCIA_MEM_ADDR
 CONFIG_SYS_PCMCIA_MEM_SIZE
 CONFIG_SYS_PCMCIA_PBR0
 CONFIG_SYS_PCMCIA_PBR1
 CONFIG_SYS_PCMCIA_PBR2
 CONFIG_SYS_PCMCIA_PBR3
 CONFIG_SYS_PCMCIA_PBR4
 CONFIG_SYS_PCMCIA_PBR5
 CONFIG_SYS_PCMCIA_PBR6
 CONFIG_SYS_PCMCIA_PBR7
 CONFIG_SYS_PCMCIA_POR0
 CONFIG_SYS_PCMCIA_POR1
 CONFIG_SYS_PCMCIA_POR2
 CONFIG_SYS_PCMCIA_POR3
 CONFIG_SYS_PCMCIA_POR4
 CONFIG_SYS_PCMCIA_POR5
 CONFIG_SYS_PCMCIA_POR6
 CONFIG_SYS_PCMCIA_POR7
 CONFIG_SYS_PDCNT
 CONFIG_SYS_PEHLPAR
 CONFIG_SYS_PEPAR
 CONFIG_SYS_PFPAR
 CONFIG_SYS_PHYS_ADDR_HIGH
 CONFIG_SYS_PHY_UBOOT_BASE
 CONFIG_SYS_PIB_BASE
 CONFIG_SYS_PIB_WINDOW_SIZE
 CONFIG_SYS_PIOC_ASR_VAL
 CONFIG_SYS_PIOC_BSR_VAL
 CONFIG_SYS_PIOC_PDR_VAL
 CONFIG_SYS_PIOC_PDR_VAL1
 CONFIG_SYS_PIOC_PPUDR_VAL
 CONFIG_SYS_PIOD_PDR_VAL1
 CONFIG_SYS_PIOD_PPUDR_VAL
 CONFIG_SYS_PIO_MODE
 CONFIG_SYS_PIT_BASE
 CONFIG_SYS_PIT_PRESCALE
 CONFIG_SYS_PIXIS_VBOOT_ENABLE
 CONFIG_SYS_PIXIS_VBOOT_MASK
 CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
 CONFIG_SYS_PJPAR
 CONFIG_SYS_PL310_BASE
 CONFIG_SYS_PLATFORM_SRAM_BASE
 CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS
 CONFIG_SYS_PLATFORM_SRAM_SIZE
 CONFIG_SYS_PLLAR_VAL
 CONFIG_SYS_PLLBR_VAL
 CONFIG_SYS_PLLCR
 CONFIG_SYS_PLL_BYPASS
 CONFIG_SYS_PLL_FDR
 CONFIG_SYS_PLL_ODR
 CONFIG_SYS_PLL_SETTLING_TIME
 CONFIG_SYS_PLUG_BASE
 CONFIG_SYS_PMAN
 CONFIG_SYS_PMC_BASE
 CONFIG_SYS_PMC_BASE_PHYS
 CONFIG_SYS_PME_CLK
 CONFIG_SYS_PORTTC
 CONFIG_SYS_POST_BSPEC1
 CONFIG_SYS_POST_BSPEC2
 CONFIG_SYS_POST_BSPEC3
 CONFIG_SYS_POST_BSPEC4
 CONFIG_SYS_POST_BSPEC5
 CONFIG_SYS_POST_CACHE
 CONFIG_SYS_POST_CODEC
 CONFIG_SYS_POST_COPROC
 CONFIG_SYS_POST_CPU
 CONFIG_SYS_POST_DSP
 CONFIG_SYS_POST_ECC
 CONFIG_SYS_POST_ETHER
 CONFIG_SYS_POST_FLASH
 CONFIG_SYS_POST_FLASH_END
 CONFIG_SYS_POST_FLASH_NUM
 CONFIG_SYS_POST_FLASH_START
 CONFIG_SYS_POST_FPU
 CONFIG_SYS_POST_HOTKEYS_GPIO
 CONFIG_SYS_POST_I2C
 CONFIG_SYS_POST_I2C_ADDRS
 CONFIG_SYS_POST_I2C_IGNORES
 CONFIG_SYS_POST_MEMORY
 CONFIG_SYS_POST_MEM_REGIONS
 CONFIG_SYS_POST_OCM
 CONFIG_SYS_POST_PREREL
 CONFIG_SYS_POST_RTC
 CONFIG_SYS_POST_SPR
 CONFIG_SYS_POST_SYSMON
 CONFIG_SYS_POST_UART
 CONFIG_SYS_POST_USB
 CONFIG_SYS_POST_WATCHDOG
 CONFIG_SYS_POST_WORD_ADDR
 CONFIG_SYS_PPC_DDR_WIMGE
 CONFIG_SYS_PQSPAR
 CONFIG_SYS_PRELIM_OR_AM
 CONFIG_SYS_PROMPT_HUSH_PS2
 CONFIG_SYS_PSDPAR
 CONFIG_SYS_PSSR_VAL
 CONFIG_SYS_PTCPAR
 CONFIG_SYS_PTDPAR
 CONFIG_SYS_PTV
 CONFIG_SYS_PUAPAR
 CONFIG_SYS_QE_FMAN_FW_IN_MMC
 CONFIG_SYS_QE_FMAN_FW_IN_NAND
 CONFIG_SYS_QE_FMAN_FW_IN_NOR
 CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 CONFIG_SYS_QE_FMAN_FW_LENGTH
 CONFIG_SYS_QE_FW_ADDR
 CONFIG_SYS_QE_FW_IN_SPIFLASH
 CONFIG_SYS_QMAN_CENA_BASE
 CONFIG_SYS_QMAN_CENA_SIZE
 CONFIG_SYS_QMAN_CINH_BASE
 CONFIG_SYS_QMAN_CINH_SIZE
 CONFIG_SYS_QMAN_MEM_BASE
 CONFIG_SYS_QMAN_MEM_PHYS
 CONFIG_SYS_QMAN_MEM_SIZE
 CONFIG_SYS_QMAN_NUM_PORTALS
 CONFIG_SYS_QMAN_SP_CENA_SIZE
 CONFIG_SYS_QMAN_SP_CINH_SIZE
 CONFIG_SYS_QMAN_SWP_ISDR_REG
 CONFIG_SYS_QRIO_BASE
 CONFIG_SYS_QRIO_BASE_PHYS
 CONFIG_SYS_QRIO_BR_PRELIM
 CONFIG_SYS_QRIO_OR_PRELIM
 CONFIG_SYS_R7780MP_OLD_FLASH
 CONFIG_SYS_RAMBOOT
 CONFIG_SYS_RAM_BASE
 CONFIG_SYS_RAM_CS
 CONFIG_SYS_RAM_FREQ_DIV
 CONFIG_SYS_RAM_SIZE
 CONFIG_SYS_RCAR_I2C0_BASE
 CONFIG_SYS_RCAR_I2C0_SPEED
 CONFIG_SYS_RCAR_I2C1_BASE
 CONFIG_SYS_RCAR_I2C1_SPEED
 CONFIG_SYS_RCAR_I2C2_BASE
 CONFIG_SYS_RCAR_I2C2_SPEED
 CONFIG_SYS_RCAR_I2C3_BASE
 CONFIG_SYS_RCAR_I2C3_SPEED
 CONFIG_SYS_RCWH_PCIHOST
 CONFIG_SYS_READ_SPD
 CONFIG_SYS_REDUNDAND_ENVIRONMENT
 CONFIG_SYS_RESET_ADDR
 CONFIG_SYS_RESET_ADDRESS
 CONFIG_SYS_RESET_SCTRL
 CONFIG_SYS_RFD
 CONFIG_SYS_RGMII1_PHY_ADDR
 CONFIG_SYS_RGMII2_PHY_ADDR
 CONFIG_SYS_RIO_MEM_BASE
 CONFIG_SYS_RIO_MEM_BUS
 CONFIG_SYS_RIO_MEM_PHYS
 CONFIG_SYS_RIO_MEM_SIZE
 CONFIG_SYS_RIO_MEM_VIRT
 CONFIG_SYS_ROM_BASE
 CONFIG_SYS_RSTC_RMR_VAL
 CONFIG_SYS_RTC_BUS_NUM
 CONFIG_SYS_RTC_CNT
 CONFIG_SYS_RTC_OSCILLATOR
 CONFIG_SYS_RTC_PL031_BASE
 CONFIG_SYS_RTC_REG_BASE_ADDR
 CONFIG_SYS_RTC_SETUP
 CONFIG_SYS_RV3029_TCR
 CONFIG_SYS_RX_ETH_BUFFER
 CONFIG_SYS_SATA
 CONFIG_SYS_SATA1
 CONFIG_SYS_SATA1_FLAGS
 CONFIG_SYS_SATA1_OFFSET
 CONFIG_SYS_SATA2
 CONFIG_SYS_SATA2_FLAGS
 CONFIG_SYS_SATA2_OFFSET
 CONFIG_SYS_SATA_ENV_DEV
 CONFIG_SYS_SATA_FAT_BOOT_PARTITION
 CONFIG_SYS_SATA_MAX_DEVICE
 CONFIG_SYS_SBFHDR_DATA_OFFSET
 CONFIG_SYS_SBFHDR_SIZE
 CONFIG_SYS_SCCR_ENCCM
 CONFIG_SYS_SCCR_PCICM
 CONFIG_SYS_SCCR_PCIEXP1CM
 CONFIG_SYS_SCCR_PCIEXP2CM
 CONFIG_SYS_SCCR_SATACM
 CONFIG_SYS_SCCR_TSEC1CM
 CONFIG_SYS_SCCR_TSEC1ON
 CONFIG_SYS_SCCR_TSEC2CM
 CONFIG_SYS_SCCR_TSEC2ON
 CONFIG_SYS_SCCR_TSECCM
 CONFIG_SYS_SCCR_USBDRCM
 CONFIG_SYS_SCCR_USBMPHCM
 CONFIG_SYS_SCR
 CONFIG_SYS_SCRATCH_VA
 CONFIG_SYS_SCSI_MAXDEVICE
 CONFIG_SYS_SCSI_MAX_DEVICE
 CONFIG_SYS_SCSI_MAX_LUN
 CONFIG_SYS_SCSI_MAX_SCSI_ID
 CONFIG_SYS_SDHC_CLK
 CONFIG_SYS_SDHC_CLK_2_PLL
 CONFIG_SYS_SDIO0
 CONFIG_SYS_SDIO0_MAX_CLK
 CONFIG_SYS_SDIO1
 CONFIG_SYS_SDIO1_MAX_CLK
 CONFIG_SYS_SDIO2
 CONFIG_SYS_SDIO2_MAX_CLK
 CONFIG_SYS_SDIO3
 CONFIG_SYS_SDIO3_MAX_CLK
 CONFIG_SYS_SDIO_BASE0
 CONFIG_SYS_SDIO_BASE1
 CONFIG_SYS_SDIO_BASE2
 CONFIG_SYS_SDIO_BASE3
 CONFIG_SYS_SDRAM
 CONFIG_SYS_SDRAM1
 CONFIG_SYS_SDRAM_BASE
 CONFIG_SYS_SDRAM_BASE0
 CONFIG_SYS_SDRAM_BASE1
 CONFIG_SYS_SDRAM_BASE1xx
 CONFIG_SYS_SDRAM_BASE2
 CONFIG_SYS_SDRAM_CFG
 CONFIG_SYS_SDRAM_CFG1
 CONFIG_SYS_SDRAM_CFG2
 CONFIG_SYS_SDRAM_CTRL
 CONFIG_SYS_SDRAM_DRVSTRENGTH
 CONFIG_SYS_SDRAM_DRV_STRENGTH
 CONFIG_SYS_SDRAM_EMOD
 CONFIG_SYS_SDRAM_LOWER
 CONFIG_SYS_SDRAM_MODE
 CONFIG_SYS_SDRAM_SIZE
 CONFIG_SYS_SDRAM_SIZE0
 CONFIG_SYS_SDRAM_SIZE1
 CONFIG_SYS_SDRAM_SIZE_LAW
 CONFIG_SYS_SDRAM_UPPER
 CONFIG_SYS_SDRAM_VAL
 CONFIG_SYS_SDRAM_VAL1
 CONFIG_SYS_SDRAM_VAL10
 CONFIG_SYS_SDRAM_VAL11
 CONFIG_SYS_SDRAM_VAL12
 CONFIG_SYS_SDRAM_VAL2
 CONFIG_SYS_SDRAM_VAL3
 CONFIG_SYS_SDRAM_VAL4
 CONFIG_SYS_SDRAM_VAL5
 CONFIG_SYS_SDRAM_VAL6
 CONFIG_SYS_SDRAM_VAL7
 CONFIG_SYS_SDRAM_VAL8
 CONFIG_SYS_SDRAM_VAL9
 CONFIG_SYS_SDRC_CR_VAL
 CONFIG_SYS_SDRC_MDR_VAL
 CONFIG_SYS_SDRC_MR_VAL
 CONFIG_SYS_SDRC_MR_VAL1
 CONFIG_SYS_SDRC_MR_VAL2
 CONFIG_SYS_SDRC_MR_VAL3
 CONFIG_SYS_SDRC_MR_VAL4
 CONFIG_SYS_SDRC_MR_VAL5
 CONFIG_SYS_SDRC_TR_VAL
 CONFIG_SYS_SDRC_TR_VAL1
 CONFIG_SYS_SDRC_TR_VAL2
 CONFIG_SYS_SD_VOLTAGE
 CONFIG_SYS_SEC_MON_ADDR
 CONFIG_SYS_SEC_MON_OFFSET
 CONFIG_SYS_SERIAL0
 CONFIG_SYS_SERIAL1
 CONFIG_SYS_SERIAL2
 CONFIG_SYS_SERIAL3
 CONFIG_SYS_SERIAL4
 CONFIG_SYS_SERIAL5
 CONFIG_SYS_SERIAL_BOOT
 CONFIG_SYS_SFP_ADDR
 CONFIG_SYS_SFP_OFFSET
 CONFIG_SYS_SGMII1_PHY_ADDR
 CONFIG_SYS_SGMII2_PHY_ADDR
 CONFIG_SYS_SGMII3_PHY_ADDR
 CONFIG_SYS_SGMII_LINERATE_MHZ
 CONFIG_SYS_SGMII_RATESCALE
 CONFIG_SYS_SGMII_REFCLK_MHZ
 CONFIG_SYS_SH_SDHI0_BASE
 CONFIG_SYS_SH_SDHI1_BASE
 CONFIG_SYS_SH_SDHI2_BASE
 CONFIG_SYS_SH_SDHI3_BASE
 CONFIG_SYS_SH_SDHI_NR_CHANNEL
 CONFIG_SYS_SICRH
 CONFIG_SYS_SICRL
 CONFIG_SYS_SIL1178_I2C
 CONFIG_SYS_SJA1000_BASE
 CONFIG_SYS_SMC0_CYCLE0_VAL
 CONFIG_SYS_SMC0_MODE0_VAL
 CONFIG_SYS_SMC0_PULSE0_VAL
 CONFIG_SYS_SMC0_SETUP0_VAL
 CONFIG_SYS_SMC_CSR0_VAL
 CONFIG_SYS_SMI_BASE
 CONFIG_SYS_SPANSION_BASE
 CONFIG_SYS_SPANSION_BOOT
 CONFIG_SYS_SPCR_OPT
 CONFIG_SYS_SPCR_TSEC1EP
 CONFIG_SYS_SPCR_TSEC2EP
 CONFIG_SYS_SPCR_TSECEP
 CONFIG_SYS_SPD_BUS_NUM
 CONFIG_SYS_SPI0
 CONFIG_SYS_SPI0_NUM_CS
 CONFIG_SYS_SPI1
 CONFIG_SYS_SPI1_BASE
 CONFIG_SYS_SPI1_NUM_CS
 CONFIG_SYS_SPI2
 CONFIG_SYS_SPI2_BASE
 CONFIG_SYS_SPI2_NUM_CS
 CONFIG_SYS_SPI_ARGS_OFFS
 CONFIG_SYS_SPI_ARGS_SIZE
 CONFIG_SYS_SPI_BASE
 CONFIG_SYS_SPI_CLK
 CONFIG_SYS_SPI_FLASH_U_BOOT_DST
 CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS
 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE
 CONFIG_SYS_SPI_FLASH_U_BOOT_START
 CONFIG_SYS_SPI_KERNEL_OFFS
 CONFIG_SYS_SPI_MXC_WAIT
 CONFIG_SYS_SPI_RTC_DEVID
 CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
 CONFIG_SYS_SPI_U_BOOT_OFFS
 CONFIG_SYS_SPI_U_BOOT_SIZE
 CONFIG_SYS_SPI_WRITE_TOUT
 CONFIG_SYS_SPL_ARGS_ADDR
 CONFIG_SYS_SPL_LEN
 CONFIG_SYS_SPL_MALLOC_SIZE
 CONFIG_SYS_SPL_MALLOC_START
 CONFIG_SYS_SPR
 CONFIG_SYS_SRAM_BASE
 CONFIG_SYS_SRAM_SIZE
 CONFIG_SYS_SRAM_START
 CONFIG_SYS_SRIO
 CONFIG_SYS_SRIO1_MEM_BASE
 CONFIG_SYS_SRIO1_MEM_BUS
 CONFIG_SYS_SRIO1_MEM_PHYS
 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH
 CONFIG_SYS_SRIO1_MEM_PHYS_LOW
 CONFIG_SYS_SRIO1_MEM_SIZE
 CONFIG_SYS_SRIO1_MEM_VIRT
 CONFIG_SYS_SRIO2_MEM_PHYS
 CONFIG_SYS_SRIO2_MEM_SIZE
 CONFIG_SYS_SRIO2_MEM_VIRT
 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS
 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR
 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS
 CONFIG_SYS_SSD_BASE
 CONFIG_SYS_SSD_BASE_PHYS
 CONFIG_SYS_SST_SECT
 CONFIG_SYS_SST_SECTSZ
 CONFIG_SYS_STACK_SIZE
 CONFIG_SYS_STATUS_C
 CONFIG_SYS_STATUS_OK
 CONFIG_SYS_STMICRO_BOOT
 CONFIG_SYS_SUPPORT_64BIT_DATA
 CONFIG_SYS_SXCNFG_VAL
 CONFIG_SYS_SYSTEMACE_BASE
 CONFIG_SYS_SYSTEMACE_WIDTH
 CONFIG_SYS_TBIPA_VALUE
 CONFIG_SYS_TCLK
 CONFIG_SYS_TEXT_ADDR
 CONFIG_SYS_TEXT_BASE_NOR
 CONFIG_SYS_TEXT_BASE_SPL
 CONFIG_SYS_TIMERBASE
 CONFIG_SYS_TIMER_BASE
 CONFIG_SYS_TIMER_COUNTER
 CONFIG_SYS_TIMER_COUNTS_DOWN
 CONFIG_SYS_TIMER_PRESCALER
 CONFIG_SYS_TIMER_RATE
 CONFIG_SYS_TMPVIRT
 CONFIG_SYS_TMRINTR_MASK
 CONFIG_SYS_TMRINTR_NO
 CONFIG_SYS_TMRINTR_PEND
 CONFIG_SYS_TMRINTR_PRI
 CONFIG_SYS_TMRPND_REG
 CONFIG_SYS_TMR_BASE
 CONFIG_SYS_TMU_CLK_DIV
 CONFIG_SYS_TSEC1
 CONFIG_SYS_TSEC1_OFFSET
 CONFIG_SYS_TSEC2
 CONFIG_SYS_TSEC2_OFFSET
 CONFIG_SYS_TSEC3_OFFSET
 CONFIG_SYS_TX_ETH_BUFFER
 CONFIG_SYS_UART1_ALT1_GPIO
 CONFIG_SYS_UART1_PRI_GPIO
 CONFIG_SYS_UART2_ALT1_GPIO
 CONFIG_SYS_UART2_ALT3_GPIO
 CONFIG_SYS_UART2_PRI_GPIO
 CONFIG_SYS_UART_BASE
 CONFIG_SYS_UART_PORT
 CONFIG_SYS_UBOOT_BASE
 CONFIG_SYS_UBOOT_END
 CONFIG_SYS_UBOOT_START
 CONFIG_SYS_UCC_RGMII_MODE
 CONFIG_SYS_UCC_RMII_MODE
 CONFIG_SYS_UDELAY_BASE
 CONFIG_SYS_UEC
 CONFIG_SYS_UEC1_ETH_TYPE
 CONFIG_SYS_UEC1_INTERFACE_SPEED
 CONFIG_SYS_UEC1_INTERFACE_TYPE
 CONFIG_SYS_UEC1_PHY_ADDR
 CONFIG_SYS_UEC1_RX_CLK
 CONFIG_SYS_UEC1_TX_CLK
 CONFIG_SYS_UEC1_UCC_NUM
 CONFIG_SYS_UEC2_ETH_TYPE
 CONFIG_SYS_UEC2_INTERFACE_SPEED
 CONFIG_SYS_UEC2_INTERFACE_TYPE
 CONFIG_SYS_UEC2_PHY_ADDR
 CONFIG_SYS_UEC2_RX_CLK
 CONFIG_SYS_UEC2_TX_CLK
 CONFIG_SYS_UEC2_UCC_NUM
 CONFIG_SYS_UEC3_ETH_TYPE
 CONFIG_SYS_UEC3_INTERFACE_SPEED
 CONFIG_SYS_UEC3_INTERFACE_TYPE
 CONFIG_SYS_UEC3_PHY_ADDR
 CONFIG_SYS_UEC3_RX_CLK
 CONFIG_SYS_UEC3_TX_CLK
 CONFIG_SYS_UEC3_UCC_NUM
 CONFIG_SYS_UEC4_ETH_TYPE
 CONFIG_SYS_UEC4_INTERFACE_SPEED
 CONFIG_SYS_UEC4_INTERFACE_TYPE
 CONFIG_SYS_UEC4_PHY_ADDR
 CONFIG_SYS_UEC4_RX_CLK
 CONFIG_SYS_UEC4_TX_CLK
 CONFIG_SYS_UEC4_UCC_NUM
 CONFIG_SYS_UEC5_ETH_TYPE
 CONFIG_SYS_UEC5_INTERFACE_SPEED
 CONFIG_SYS_UEC5_INTERFACE_TYPE
 CONFIG_SYS_UEC5_PHY_ADDR
 CONFIG_SYS_UEC5_RX_CLK
 CONFIG_SYS_UEC5_TX_CLK
 CONFIG_SYS_UEC5_UCC_NUM
 CONFIG_SYS_UEC6_ETH_TYPE
 CONFIG_SYS_UEC6_INTERFACE_SPEED
 CONFIG_SYS_UEC6_INTERFACE_TYPE
 CONFIG_SYS_UEC6_PHY_ADDR
 CONFIG_SYS_UEC6_RX_CLK
 CONFIG_SYS_UEC6_TX_CLK
 CONFIG_SYS_UEC6_UCC_NUM
 CONFIG_SYS_UEC8_ETH_TYPE
 CONFIG_SYS_UEC8_INTERFACE_SPEED
 CONFIG_SYS_UEC8_INTERFACE_TYPE
 CONFIG_SYS_UEC8_PHY_ADDR
 CONFIG_SYS_UEC8_RX_CLK
 CONFIG_SYS_UEC8_TX_CLK
 CONFIG_SYS_UEC8_UCC_NUM
 CONFIG_SYS_UECx_PHY_ADDR
 CONFIG_SYS_UHC0_EHCI_BASE
 CONFIG_SYS_UHC1_EHCI_BASE
 CONFIG_SYS_ULB_CLK
 CONFIG_SYS_UNIFY_CACHE
 CONFIG_SYS_UNSPEC_PHYID
 CONFIG_SYS_UNSPEC_STRID
 CONFIG_SYS_USBCTRL
 CONFIG_SYS_USBD_BASE
 CONFIG_SYS_USB_EHCI_CPU_INIT
 CONFIG_SYS_USB_EHCI_REGS_BASE
 CONFIG_SYS_USB_FAT_BOOT_PARTITION
 CONFIG_SYS_USB_HOST
 CONFIG_SYS_USB_OHCI_BOARD_INIT
 CONFIG_SYS_USB_OHCI_CPU_INIT
 CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
 CONFIG_SYS_USB_OHCI_REGS_BASE
 CONFIG_SYS_USB_OHCI_SLOT_NAME
 CONFIG_SYS_USER_SWITCHES_BASE
 CONFIG_SYS_USE_BOOT_NORFLASH
 CONFIG_SYS_USE_DATAFLASH
 CONFIG_SYS_USE_DATAFLASH_CS0
 CONFIG_SYS_USE_DATAFLASH_CS1
 CONFIG_SYS_USE_DATAFLASH_CS3
 CONFIG_SYS_USE_DSPLINK
 CONFIG_SYS_USE_FLASH
 CONFIG_SYS_USE_MAIN_OSCILLATOR
 CONFIG_SYS_USE_MMC
 CONFIG_SYS_USE_MPC834XSYS_USB_PHY
 CONFIG_SYS_USE_NAND
 CONFIG_SYS_USE_NANDFLASH
 CONFIG_SYS_USE_NOR
 CONFIG_SYS_USE_NORFLASH
 CONFIG_SYS_USE_SERIALFLASH
 CONFIG_SYS_USR_EXCEP
 CONFIG_SYS_U_BOOT_OFFS
 CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
 CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
 CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
 CONFIG_SYS_VCXK_AUTODETECT
 CONFIG_SYS_VCXK_BASE
 CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
 CONFIG_SYS_VCXK_DOUBLEBUFFERED
 CONFIG_SYS_VCXK_ENABLE_DDR
 CONFIG_SYS_VCXK_ENABLE_PIN
 CONFIG_SYS_VCXK_ENABLE_PORT
 CONFIG_SYS_VCXK_INVERT_DDR
 CONFIG_SYS_VCXK_INVERT_PIN
 CONFIG_SYS_VCXK_INVERT_PORT
 CONFIG_SYS_VCXK_REQUEST_DDR
 CONFIG_SYS_VCXK_REQUEST_PIN
 CONFIG_SYS_VCXK_REQUEST_PORT
 CONFIG_SYS_VCXK_RESET_DDR
 CONFIG_SYS_VCXK_RESET_PIN
 CONFIG_SYS_VCXK_RESET_PORT
 CONFIG_SYS_VGA_RAM_EN
 CONFIG_SYS_VIDEO
 CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
 CONFIG_SYS_VSC7385_BASE
 CONFIG_SYS_VSC7385_BASE_PHYS
 CONFIG_SYS_VSC7385_BR_PRELIM
 CONFIG_SYS_VSC7385_OR_PRELIM
 CONFIG_SYS_VSC7385_SIZE
 CONFIG_SYS_VXWORKS_MAC_PTR
 CONFIG_SYS_WATCHDOG_FREQ
 CONFIG_SYS_WATCHDOG_VALUE
 CONFIG_SYS_WDTC_WDMR_VAL
 CONFIG_SYS_WDTTIMERBASE
 CONFIG_SYS_WDT_PERIOD_HIGH
 CONFIG_SYS_WDT_PERIOD_LOW
 CONFIG_SYS_WINDOW1_BASE
 CONFIG_SYS_WRITE_SWAPPED_DATA
 CONFIG_SYS_XHCI_USB1_ADDR
 CONFIG_SYS_XHCI_USB2_ADDR
 CONFIG_SYS_XHCI_USB3_ADDR
 CONFIG_SYS_XILINX_SPI_LIST
 CONFIG_SYS_XIMG_LEN
 CONFIG_SYS_XWAY_EBU_BOOTCFG
 CONFIG_SYS_ZYNQ_QSPI_WAIT
 CONFIG_SYS_ZYNQ_SPI_WAIT
 CONFIG_SYS_i2C_FSL
 CONFIG_TAM3517_SETTINGS
 CONFIG_TAM3517_SW3_SETTINGS
 CONFIG_TCA642X
 CONFIG_TEGRA_BOARD_STRING
 CONFIG_TEGRA_CLOCK_SCALING
 CONFIG_TEGRA_ENABLE_UARTA
 CONFIG_TEGRA_ENABLE_UARTB
 CONFIG_TEGRA_ENABLE_UARTC
 CONFIG_TEGRA_ENABLE_UARTD
 CONFIG_TEGRA_ENABLE_UARTE
 CONFIG_TEGRA_GPU
 CONFIG_TEGRA_KEYBOARD
 CONFIG_TEGRA_LP0
 CONFIG_TEGRA_NAND
 CONFIG_TEGRA_PMU
 CONFIG_TEGRA_SLINK_CTRLS
 CONFIG_TEGRA_SPI
 CONFIG_TEGRA_UARTA_GPU
 CONFIG_TEGRA_UARTA_SDIO1
 CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
 CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
 CONFIG_TESTPIN_MASK
 CONFIG_TESTPIN_REG
 CONFIG_TEST_LIST_SORT
 CONFIG_TFP410_I2C_ADDR
 CONFIG_TFTP_BLOCKSIZE
 CONFIG_TFTP_FILE_NAME_MAX_LEN
 CONFIG_TFTP_PORT
 CONFIG_TFTP_TSIZE
 CONFIG_THOR_RESET_OFF
 CONFIG_THUNDERX
 CONFIG_TIMESTAMP
 CONFIG_TIZEN
 CONFIG_TI_KEYSTONE_SERDES
 CONFIG_TI_KSNAV
 CONFIG_TI_SPI_MMAP
 CONFIG_TMU_TIMER
 CONFIG_TPL_PAD_TO
 CONFIG_TPM_TIS_BASE_ADDRESS
 CONFIG_TPS6586X_POWER
 CONFIG_TQM834X
 CONFIG_TRACE
 CONFIG_TRACE_BUFFER_SIZE
 CONFIG_TRACE_EARLY
 CONFIG_TRACE_EARLY_ADDR
 CONFIG_TRACE_EARLY_SIZE
 CONFIG_TRAILBLAZER
 CONFIG_TRATS
 CONFIG_TSEC
 CONFIG_TSEC1
 CONFIG_TSEC1_NAME
 CONFIG_TSEC2
 CONFIG_TSEC2_NAME
 CONFIG_TSEC3
 CONFIG_TSEC3_NAME
 CONFIG_TSEC4
 CONFIG_TSEC4_NAME
 CONFIG_TSECV2
 CONFIG_TSECV2_1
 CONFIG_TSEC_ENET
 CONFIG_TSEC_TBI
 CONFIG_TSEC_TBICR_SETTINGS
 CONFIG_TSI108_ETH_NUM_PORTS
 CONFIG_TUGE1
 CONFIG_TULIP
 CONFIG_TULIP_FIX_DAVICOM
 CONFIG_TULIP_SELECT_MEDIA
 CONFIG_TULIP_USE_IO
 CONFIG_TUXX1
 CONFIG_TWL4030_INPUT
 CONFIG_TWL4030_KEYPAD
 CONFIG_TWL4030_LED
 CONFIG_TWL4030_USB
 CONFIG_TWL6030_INPUT
 CONFIG_TWL6030_POWER
 CONFIG_TWR
 CONFIG_TWR_P1025
 CONFIG_TX_DESCR_NUM
 CONFIG_TZSW_RESERVED_DRAM_SIZE
 CONFIG_T_SH7706LSR
 CONFIG_UART_BR_PRELIM
 CONFIG_UART_OR_PRELIM
 CONFIG_UBIBLOCK
 CONFIG_UBIFS_SILENCE_MSG
 CONFIG_UBIFS_VOLUME
 CONFIG_UBI_PART
 CONFIG_UBI_SILENCE_MSG
 CONFIG_UBI_SIZE
 CONFIG_UBOOT1_ENV_ADDR
 CONFIG_UBOOT2_ENV_ADDR
 CONFIG_UBOOTPATH
 CONFIG_UBOOT_ENABLE_PADS_ALL
 CONFIG_UBOOT_SECTOR_COUNT
 CONFIG_UBOOT_SECTOR_START
 CONFIG_UCP1020
 CONFIG_UCP1020_REV_1_3
 CONFIG_UDP_CHECKSUM
 CONFIG_UEC_ETH
 CONFIG_UEC_ETH1
 CONFIG_UEC_ETH2
 CONFIG_UEC_ETH3
 CONFIG_UEC_ETH4
 CONFIG_UEC_ETH5
 CONFIG_UEC_ETH6
 CONFIG_UEC_ETH7
 CONFIG_UEC_ETH8
 CONFIG_UID16
 CONFIG_ULI526X
 CONFIG_ULPI_REF_CLK
 CONFIG_UMSDEVS
 CONFIG_UPDATEB
 CONFIG_UPDATE_LOAD_ADDR
 CONFIG_UPDATE_TFTP
 CONFIG_UPDATE_TFTP_CNT_MAX
 CONFIG_UPDATE_TFTP_MSEC_MAX
 CONFIG_USART1
 CONFIG_USART_BASE
 CONFIG_USART_ID
 CONFIG_USBBOOTCOMMAND
 CONFIG_USBDEBUG
 CONFIG_USBD_CONFIGURATION_STR
 CONFIG_USBD_CTRL_INTERFACE_STR
 CONFIG_USBD_DATA_INTERFACE_STR
 CONFIG_USBD_HS
 CONFIG_USBD_MANUFACTURER
 CONFIG_USBD_PRODUCTID
 CONFIG_USBD_PRODUCTID_CDCACM
 CONFIG_USBD_PRODUCTID_GSERIAL
 CONFIG_USBD_PRODUCT_NAME
 CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE
 CONFIG_USBD_SERIAL_BULK_PKTSIZE
 CONFIG_USBD_SERIAL_INT_ENDPOINT
 CONFIG_USBD_SERIAL_INT_PKTSIZE
 CONFIG_USBD_SERIAL_IN_ENDPOINT
 CONFIG_USBD_SERIAL_IN_PKTSIZE
 CONFIG_USBD_SERIAL_OUT_ENDPOINT
 CONFIG_USBD_SERIAL_OUT_PKTSIZE
 CONFIG_USBD_VENDORID
 CONFIG_USBID_ADDR
 CONFIG_USBNET_DEV_ADDR
 CONFIG_USBTTY
 CONFIG_USB_AM35X
 CONFIG_USB_ATMEL
 CONFIG_USB_ATMEL_CLK_SEL_PLLB
 CONFIG_USB_ATMEL_CLK_SEL_UPLL
 CONFIG_USB_BIN_FIXUP
 CONFIG_USB_BOOTING
 CONFIG_USB_CABLE_CHECK
 CONFIG_USB_DEVICE
 CONFIG_USB_DEV_BASE
 CONFIG_USB_DEV_PULLUP_GPIO
 CONFIG_USB_DWC2_REG_ADDR
 CONFIG_USB_EHCI_ARMADA100
 CONFIG_USB_EHCI_BASE
 CONFIG_USB_EHCI_BASE_LIST
 CONFIG_USB_EHCI_EXYNOS
 CONFIG_USB_EHCI_FARADAY
 CONFIG_USB_EHCI_FSL
 CONFIG_USB_EHCI_KIRKWOOD
 CONFIG_USB_EHCI_MX5
 CONFIG_USB_EHCI_MXC
 CONFIG_USB_EHCI_MXS
 CONFIG_USB_EHCI_RMOBILE
 CONFIG_USB_EHCI_SPEAR
 CONFIG_USB_EHCI_SUNXI
 CONFIG_USB_EHCI_TEGRA
 CONFIG_USB_EHCI_TXFIFO_THRESH
 CONFIG_USB_EHCI_VCT
 CONFIG_USB_EHCI_VF
 CONFIG_USB_ETH_QMULT
 CONFIG_USB_ETH_SUBSET
 CONFIG_USB_EXT2_BOOT
 CONFIG_USB_FAT_BOOT
 CONFIG_USB_FREQ
 CONFIG_USB_FUNCTION_MASS_STORAGE
 CONFIG_USB_FUNCTION_THOR
 CONFIG_USB_GADGET_AMD5536UDC
 CONFIG_USB_GADGET_AT91
 CONFIG_USB_GADGET_AU1X00
 CONFIG_USB_GADGET_DUMMY_HCD
 CONFIG_USB_GADGET_DWC2_OTG_PHY
 CONFIG_USB_GADGET_FOTG210
 CONFIG_USB_GADGET_FSL_USB2
 CONFIG_USB_GADGET_GOKU
 CONFIG_USB_GADGET_IMX
 CONFIG_USB_GADGET_M66592
 CONFIG_USB_GADGET_MASS_STORAGE
 CONFIG_USB_GADGET_MQ11XX
 CONFIG_USB_GADGET_MUSBHSFC
 CONFIG_USB_GADGET_N9604
 CONFIG_USB_GADGET_NET2280
 CONFIG_USB_GADGET_OMAP
 CONFIG_USB_GADGET_PXA27X
 CONFIG_USB_GADGET_PXA2XX
 CONFIG_USB_GADGET_SA1100
 CONFIG_USB_GADGET_SUPERH
 CONFIG_USB_GADGET_SX2
 CONFIG_USB_HOST_XHCI_BASE
 CONFIG_USB_INVENTRA_DMA
 CONFIG_USB_ISP1301_I2C_ADDR
 CONFIG_USB_MAX_CONTROLLER_COUNT
 CONFIG_USB_MUSB_AM35X
 CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 CONFIG_USB_MUSB_DSPS
 CONFIG_USB_MUSB_HCD
 CONFIG_USB_MUSB_OMAP2PLUS
 CONFIG_USB_MUSB_PIO_ONLY
 CONFIG_USB_MUSB_TIMEOUT
 CONFIG_USB_MUSB_TUSB6010
 CONFIG_USB_MUSB_UDC
 CONFIG_USB_OHCI
 CONFIG_USB_OHCI_EP93XX
 CONFIG_USB_OHCI_LPC32XX
 CONFIG_USB_OHCI_NEW
 CONFIG_USB_OHCI_SUNXI
 CONFIG_USB_OMAP3
 CONFIG_USB_OTG
 CONFIG_USB_OTG_BLACKLIST_HUB
 CONFIG_USB_PHY_CFG_BASE
 CONFIG_USB_PHY_TYPE
 CONFIG_USB_PXA25X_SMALL
 CONFIG_USB_R8A66597_HCD
 CONFIG_USB_SERIALNO
 CONFIG_USB_SS_BASE
 CONFIG_USB_TI_CPPI_DMA
 CONFIG_USB_TTY
 CONFIG_USB_TUSB_OMAP_DMA
 CONFIG_USB_ULPI_TIMEOUT
 CONFIG_USB_XHCI_EXYNOS
 CONFIG_USB_XHCI_KEYSTONE
 CONFIG_USB_XHCI_OMAP
 CONFIG_USER_LOWLEVEL_INIT
 CONFIG_USE_FDT
 CONFIG_USE_INTERRUPT
 CONFIG_USE_NAND
 CONFIG_USE_NOR
 CONFIG_USE_ONENAND_BOARD_INIT
 CONFIG_USE_SPIFLASH
 CONFIG_USE_STDINT
 CONFIG_UTBIPAR_INIT_TBIPA
 CONFIG_U_BOOT_HDR_ADDR
 CONFIG_U_BOOT_HDR_SIZE
 CONFIG_U_QE
 CONFIG_VAL
 CONFIG_VAR_SIZE_SPL
 CONFIG_VCT_NOR
 CONFIG_VE8313
 CONFIG_VERY_BIG_RAM
 CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
 CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
 CONFIG_VID
 CONFIG_VIDEO_BCM2835
 CONFIG_VIDEO_BMP_GZIP
 CONFIG_VIDEO_BMP_LOGO
 CONFIG_VIDEO_BMP_RLE8
 CONFIG_VIDEO_CORALP
 CONFIG_VIDEO_DA8XX
 CONFIG_VIDEO_FONT_4X6
 CONFIG_VIDEO_LCD_I2C_BUS
 CONFIG_VIDEO_LOGO
 CONFIG_VIDEO_MB862xx
 CONFIG_VIDEO_MB862xx_ACCEL
 CONFIG_VIDEO_MX3
 CONFIG_VIDEO_MXS
 CONFIG_VIDEO_MXS_MODE_SYSTEM
 CONFIG_VIDEO_OMAP3
 CONFIG_VIDEO_STD_TIMINGS
 CONFIG_VIDEO_VCXK
 CONFIG_VID_FLS_ENV
 CONFIG_VM86
 CONFIG_VME8349
 CONFIG_VOIPAC_LCD
 CONFIG_VOL_MONITOR_INA220
 CONFIG_VOL_MONITOR_IR36021_READ
 CONFIG_VOL_MONITOR_IR36021_SET
 CONFIG_VSC7385_ENET
 CONFIG_VSC7385_IMAGE
 CONFIG_VSC7385_IMAGE_SIZE
 CONFIG_VSC9953
 CONFIG_VSC_CROSSBAR
 CONFIG_WATCHDOG
 CONFIG_WATCHDOG_BASEADDR
 CONFIG_WATCHDOG_IRQ
 CONFIG_WATCHDOG_NOWAYOUT
 CONFIG_WATCHDOG_PRESC
 CONFIG_WATCHDOG_RC
 CONFIG_WATCHDOG_TIMEOUT
 CONFIG_WATCHDOG_TIMEOUT_MSECS
 CONFIG_WD_PERIOD
 CONFIG_X600
 CONFIG_X86EMU_DEBUG
 CONFIG_X86EMU_RAW_IO
 CONFIG_X86_MRC_ADDR
 CONFIG_X86_REFCODE_ADDR
 CONFIG_X86_REFCODE_RUN_ADDR
 CONFIG_XGI_XG22_BASE
 CONFIG_XILINX_GPIO
 CONFIG_XILINX_LL_TEMAC_CLK
 CONFIG_XILINX_SPI_IDLE_VAL
 CONFIG_XILINX_TB_WATCHDOG
 CONFIG_XPEDITE5140
 CONFIG_XPEDITE5200
 CONFIG_XPEDITE550X
 CONFIG_XR16L2751
 CONFIG_XSENGINE
 CONFIG_XTFPGA
 CONFIG_YAFFSFS_PROVIDE_VALUES
 CONFIG_YAFFS_AUTO_UNICODE
 CONFIG_YAFFS_CASE_INSENSITIVE
 CONFIG_YAFFS_DEFINES_TYPES
 CONFIG_YAFFS_DIRECT
 CONFIG_YAFFS_PROVIDE_DEFS
 CONFIG_YAFFS_UNICODE
 CONFIG_YAFFS_UTIL
 CONFIG_YAFFS_WINCE
 CONFIG_YELLOW_LED
 CONFIG_ZC770_XM010
 CONFIG_ZC770_XM011
 CONFIG_ZC770_XM012
 CONFIG_ZC770_XM013
 CONFIG_ZLIB
 CONFIG_ZLT
 CONFIG_ZM7300
 CONFIG_ZYNQMP_EEPROM
 CONFIG_ZYNQMP_XHCI_LIST
 CONFIG_ZYNQ_EEPROM
 CONFIG_ZYNQ_EEPROM_BUS
 CONFIG_ZYNQ_GEM_EEPROM_ADDR
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
 CONFIG_ZYNQ_HISPD_BROKEN
 CONFIG_ZYNQ_I2C0
 CONFIG_ZYNQ_I2C1
 CONFIG_ZYNQ_SDHCI0
 CONFIG_ZYNQ_SDHCI1
 CONFIG_ZYNQ_SDHCI_MAX_FREQ
 CONFIG_ZYNQ_SDHCI_MIN_FREQ
 CONFIG_eTSEC_MDIO_BUS