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Commit 99b0b68a1ddf248e9766b194821da97045f04a4f

Authored by Robin Gong
1 parent bf7ffcfd66
Exists in smarc-imx-l5.0.0_1.0.0-ga

MLK-9891-1: ARM: imx6: split WDOG_B setting from set_anatop_bypass() function 

We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now
on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to
reboot whole board, so split these code to independent function so that board file
can call it freely.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 93d457e4c601ee5266bc30b7dfa5fa1bbfa8500a)

Showing 2 changed files with 21 additions and 15 deletions Inline Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 99b0b68
1 /* 1 /*
2 * (C) Copyright 2007 2 * (C) Copyright 2007
3 * Sascha Hauer, Pengutronix 3 * Sascha Hauer, Pengutronix
4 * 4 *
5 * (C) Copyright 2009-2014 Freescale Semiconductor, Inc. 5 * (C) Copyright 2009-2014 Freescale Semiconductor, Inc.
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <asm/armv7.h> 11 #include <asm/armv7.h>
12 #include <asm/pl310.h> 12 #include <asm/pl310.h>
13 #include <asm/errno.h> 13 #include <asm/errno.h>
14 #include <asm/io.h> 14 #include <asm/io.h>
15 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h> 16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/boot_mode.h> 18 #include <asm/imx-common/boot_mode.h>
19 #include <asm/imx-common/dma.h> 19 #include <asm/imx-common/dma.h>
20 #include <libfdt.h> 20 #include <libfdt.h>
21 #include <stdbool.h> 21 #include <stdbool.h>
22 #include <asm/arch/mxc_hdmi.h> 22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h> 23 #include <asm/arch/crm_regs.h>
24 #ifdef CONFIG_FASTBOOT 24 #ifdef CONFIG_FASTBOOT
25 #ifdef CONFIG_ANDROID_RECOVERY 25 #ifdef CONFIG_ANDROID_RECOVERY
26 #include <recovery.h> 26 #include <recovery.h>
27 #endif 27 #endif
28 #endif 28 #endif
29 #ifdef CONFIG_IMX_UDC 29 #ifdef CONFIG_IMX_UDC
30 #include <asm/arch/mx6_usbphy.h> 30 #include <asm/arch/mx6_usbphy.h>
31 #include <usb/imx_udc.h> 31 #include <usb/imx_udc.h>
32 #endif 32 #endif
33 33
34 enum ldo_reg { 34 enum ldo_reg {
35 LDO_ARM, 35 LDO_ARM,
36 LDO_SOC, 36 LDO_SOC,
37 LDO_PU, 37 LDO_PU,
38 }; 38 };
39 39
40 struct scu_regs { 40 struct scu_regs {
41 u32 ctrl; 41 u32 ctrl;
42 u32 config; 42 u32 config;
43 u32 status; 43 u32 status;
44 u32 invalidate; 44 u32 invalidate;
45 u32 fpga_rev; 45 u32 fpga_rev;
46 }; 46 };
47 47
48 #define TEMPERATURE_MIN -40 48 #define TEMPERATURE_MIN -40
49 #define TEMPERATURE_HOT 80 49 #define TEMPERATURE_HOT 80
50 #define TEMPERATURE_MAX 125 50 #define TEMPERATURE_MAX 125
51 #define FACTOR1 15976 51 #define FACTOR1 15976
52 #define FACTOR2 4297157 52 #define FACTOR2 4297157
53 #define MEASURE_FREQ 327 53 #define MEASURE_FREQ 327
54 54
55 #define REG_VALUE_TO_CEL(ratio, raw) \ 55 #define REG_VALUE_TO_CEL(ratio, raw) \
56 ((raw_n40c - raw) * 100 / ratio - 40) 56 ((raw_n40c - raw) * 100 / ratio - 40)
57 57
58 static unsigned int fuse = ~0; 58 static unsigned int fuse = ~0;
59 59
60 u32 get_cpu_rev(void) 60 u32 get_cpu_rev(void)
61 { 61 {
62 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 62 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
63 u32 reg = readl(&ccm_regs->digprog_sololite); 63 u32 reg = readl(&ccm_regs->digprog_sololite);
64 u32 type = ((reg >> 16) & 0xff); 64 u32 type = ((reg >> 16) & 0xff);
65 65
66 if (type != MXC_CPU_MX6SL) { 66 if (type != MXC_CPU_MX6SL) {
67 reg = readl(&ccm_regs->digprog); 67 reg = readl(&ccm_regs->digprog);
68 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; 68 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
69 u32 cfg = readl(&scu->config) & 3; 69 u32 cfg = readl(&scu->config) & 3;
70 type = ((reg >> 16) & 0xff); 70 type = ((reg >> 16) & 0xff);
71 if (type == MXC_CPU_MX6DL) { 71 if (type == MXC_CPU_MX6DL) {
72 if (!cfg) 72 if (!cfg)
73 type = MXC_CPU_MX6SOLO; 73 type = MXC_CPU_MX6SOLO;
74 } 74 }
75 75
76 if (type == MXC_CPU_MX6Q) { 76 if (type == MXC_CPU_MX6Q) {
77 if (cfg == 1) 77 if (cfg == 1)
78 type = MXC_CPU_MX6D; 78 type = MXC_CPU_MX6D;
79 } 79 }
80 80
81 } 81 }
82 reg &= 0xff; /* mx6 silicon revision */ 82 reg &= 0xff; /* mx6 silicon revision */
83 return (type << 12) | (reg + 0x10); 83 return (type << 12) | (reg + 0x10);
84 } 84 }
85 85
86 #ifdef CONFIG_REVISION_TAG 86 #ifdef CONFIG_REVISION_TAG
87 u32 __weak get_board_rev(void) 87 u32 __weak get_board_rev(void)
88 { 88 {
89 u32 cpurev = get_cpu_rev(); 89 u32 cpurev = get_cpu_rev();
90 u32 type = ((cpurev >> 12) & 0xff); 90 u32 type = ((cpurev >> 12) & 0xff);
91 if (type == MXC_CPU_MX6SOLO) 91 if (type == MXC_CPU_MX6SOLO)
92 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); 92 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
93 93
94 if (type == MXC_CPU_MX6D) 94 if (type == MXC_CPU_MX6D)
95 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); 95 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
96 96
97 return cpurev; 97 return cpurev;
98 } 98 }
99 #endif 99 #endif
100 100
101 void init_aips(void) 101 void init_aips(void)
102 { 102 {
103 struct aipstz_regs *aips1, *aips2; 103 struct aipstz_regs *aips1, *aips2;
104 #ifdef CONFIG_MX6SX 104 #ifdef CONFIG_MX6SX
105 struct aipstz_regs *aips3; 105 struct aipstz_regs *aips3;
106 #endif 106 #endif
107 107
108 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; 108 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
109 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; 109 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
110 #ifdef CONFIG_MX6SX 110 #ifdef CONFIG_MX6SX
111 aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR; 111 aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
112 #endif 112 #endif
113 113
114 /* 114 /*
115 * Set all MPROTx to be non-bufferable, trusted for R/W, 115 * Set all MPROTx to be non-bufferable, trusted for R/W,
116 * not forced to user-mode. 116 * not forced to user-mode.
117 */ 117 */
118 writel(0x77777777, &aips1->mprot0); 118 writel(0x77777777, &aips1->mprot0);
119 writel(0x77777777, &aips1->mprot1); 119 writel(0x77777777, &aips1->mprot1);
120 writel(0x77777777, &aips2->mprot0); 120 writel(0x77777777, &aips2->mprot0);
121 writel(0x77777777, &aips2->mprot1); 121 writel(0x77777777, &aips2->mprot1);
122 122
123 /* 123 /*
124 * Set all OPACRx to be non-bufferable, not require 124 * Set all OPACRx to be non-bufferable, not require
125 * supervisor privilege level for access,allow for 125 * supervisor privilege level for access,allow for
126 * write access and untrusted master access. 126 * write access and untrusted master access.
127 */ 127 */
128 writel(0x00000000, &aips1->opacr0); 128 writel(0x00000000, &aips1->opacr0);
129 writel(0x00000000, &aips1->opacr1); 129 writel(0x00000000, &aips1->opacr1);
130 writel(0x00000000, &aips1->opacr2); 130 writel(0x00000000, &aips1->opacr2);
131 writel(0x00000000, &aips1->opacr3); 131 writel(0x00000000, &aips1->opacr3);
132 writel(0x00000000, &aips1->opacr4); 132 writel(0x00000000, &aips1->opacr4);
133 writel(0x00000000, &aips2->opacr0); 133 writel(0x00000000, &aips2->opacr0);
134 writel(0x00000000, &aips2->opacr1); 134 writel(0x00000000, &aips2->opacr1);
135 writel(0x00000000, &aips2->opacr2); 135 writel(0x00000000, &aips2->opacr2);
136 writel(0x00000000, &aips2->opacr3); 136 writel(0x00000000, &aips2->opacr3);
137 writel(0x00000000, &aips2->opacr4); 137 writel(0x00000000, &aips2->opacr4);
138 138
139 #ifdef CONFIG_MX6SX 139 #ifdef CONFIG_MX6SX
140 /* 140 /*
141 * Set all MPROTx to be non-bufferable, trusted for R/W, 141 * Set all MPROTx to be non-bufferable, trusted for R/W,
142 * not forced to user-mode. 142 * not forced to user-mode.
143 */ 143 */
144 writel(0x77777777, &aips3->mprot0); 144 writel(0x77777777, &aips3->mprot0);
145 writel(0x77777777, &aips3->mprot1); 145 writel(0x77777777, &aips3->mprot1);
146 146
147 /* 147 /*
148 * Set all OPACRx to be non-bufferable, not require 148 * Set all OPACRx to be non-bufferable, not require
149 * supervisor privilege level for access,allow for 149 * supervisor privilege level for access,allow for
150 * write access and untrusted master access. 150 * write access and untrusted master access.
151 */ 151 */
152 writel(0x00000000, &aips3->opacr0); 152 writel(0x00000000, &aips3->opacr0);
153 writel(0x00000000, &aips3->opacr1); 153 writel(0x00000000, &aips3->opacr1);
154 writel(0x00000000, &aips3->opacr2); 154 writel(0x00000000, &aips3->opacr2);
155 writel(0x00000000, &aips3->opacr3); 155 writel(0x00000000, &aips3->opacr3);
156 writel(0x00000000, &aips3->opacr4); 156 writel(0x00000000, &aips3->opacr4);
157 #endif 157 #endif
158 } 158 }
159 159
160 static void clear_ldo_ramp(void) 160 static void clear_ldo_ramp(void)
161 { 161 {
162 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 162 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
163 int reg; 163 int reg;
164 164
165 /* ROM may modify LDO ramp up time according to fuse setting, so in 165 /* ROM may modify LDO ramp up time according to fuse setting, so in
166 * order to be in the safe side we neeed to reset these settings to 166 * order to be in the safe side we neeed to reset these settings to
167 * match the reset value: 0'b00 167 * match the reset value: 0'b00
168 */ 168 */
169 reg = readl(&ccm_regs->ana_misc2); 169 reg = readl(&ccm_regs->ana_misc2);
170 reg &= ~(0x3f << 24); 170 reg &= ~(0x3f << 24);
171 writel(reg, &ccm_regs->ana_misc2); 171 writel(reg, &ccm_regs->ana_misc2);
172 } 172 }
173 173
174 /* 174 /*
175 * Set the PMU_REG_CORE register 175 * Set the PMU_REG_CORE register
176 * 176 *
177 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. 177 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
178 * Possible values are from 0.725V to 1.450V in steps of 178 * Possible values are from 0.725V to 1.450V in steps of
179 * 0.025V (25mV). 179 * 0.025V (25mV).
180 */ 180 */
181 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) 181 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
182 { 182 {
183 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 183 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
184 u32 val, step, old, reg = readl(&ccm_regs->reg_core); 184 u32 val, step, old, reg = readl(&ccm_regs->reg_core);
185 u8 shift; 185 u8 shift;
186 186
187 if (mv < 725) 187 if (mv < 725)
188 val = 0x00; /* Power gated off */ 188 val = 0x00; /* Power gated off */
189 else if (mv > 1450) 189 else if (mv > 1450)
190 val = 0x1F; /* Power FET switched full on. No regulation */ 190 val = 0x1F; /* Power FET switched full on. No regulation */
191 else 191 else
192 val = (mv - 700) / 25; 192 val = (mv - 700) / 25;
193 193
194 clear_ldo_ramp(); 194 clear_ldo_ramp();
195 195
196 switch (ldo) { 196 switch (ldo) {
197 case LDO_SOC: 197 case LDO_SOC:
198 shift = 18; 198 shift = 18;
199 break; 199 break;
200 case LDO_PU: 200 case LDO_PU:
201 shift = 9; 201 shift = 9;
202 break; 202 break;
203 case LDO_ARM: 203 case LDO_ARM:
204 shift = 0; 204 shift = 0;
205 break; 205 break;
206 default: 206 default:
207 return -EINVAL; 207 return -EINVAL;
208 } 208 }
209 209
210 old = (reg & (0x1F << shift)) >> shift; 210 old = (reg & (0x1F << shift)) >> shift;
211 step = abs(val - old); 211 step = abs(val - old);
212 if (step == 0) 212 if (step == 0)
213 return 0; 213 return 0;
214 214
215 reg = (reg & ~(0x1F << shift)) | (val << shift); 215 reg = (reg & ~(0x1F << shift)) | (val << shift);
216 writel(reg, &ccm_regs->reg_core); 216 writel(reg, &ccm_regs->reg_core);
217 217
218 /* 218 /*
219 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per 219 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
220 * step 220 * step
221 */ 221 */
222 udelay(3 * step); 222 udelay(3 * step);
223 223
224 return 0; 224 return 0;
225 } 225 }
226 226
227 static void imx_set_wdog_powerdown(bool enable) 227 static void imx_set_wdog_powerdown(bool enable)
228 { 228 {
229 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; 229 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
230 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; 230 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
231 #ifdef CONFIG_MX6SX 231 #ifdef CONFIG_MX6SX
232 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; 232 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
233 writew(enable, &wdog3->wmcr); 233 writew(enable, &wdog3->wmcr);
234 #endif 234 #endif
235 235
236 /* Write to the PDE (Power Down Enable) bit */ 236 /* Write to the PDE (Power Down Enable) bit */
237 writew(enable, &wdog1->wmcr); 237 writew(enable, &wdog1->wmcr);
238 writew(enable, &wdog2->wmcr); 238 writew(enable, &wdog2->wmcr);
239 } 239 }
240 240
241 static int read_cpu_temperature(void) 241 static int read_cpu_temperature(void)
242 { 242 {
243 int temperature; 243 int temperature;
244 unsigned int ccm_ccgr2; 244 unsigned int ccm_ccgr2;
245 unsigned int reg, tmp; 245 unsigned int reg, tmp;
246 unsigned int raw_25c, raw_n40c, ratio; 246 unsigned int raw_25c, raw_n40c, ratio;
247 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 247 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
248 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 248 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
249 struct fuse_bank *bank = &ocotp->bank[1]; 249 struct fuse_bank *bank = &ocotp->bank[1];
250 struct fuse_bank1_regs *fuse_bank1 = 250 struct fuse_bank1_regs *fuse_bank1 =
251 (struct fuse_bank1_regs *)bank->fuse_regs; 251 (struct fuse_bank1_regs *)bank->fuse_regs;
252 252
253 /* need to make sure pll3 is enabled for thermal sensor */ 253 /* need to make sure pll3 is enabled for thermal sensor */
254 if ((readl(&mxc_ccm->analog_usb1_pll_480_ctrl) & 254 if ((readl(&mxc_ccm->analog_usb1_pll_480_ctrl) &
255 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { 255 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
256 /* enable pll's power */ 256 /* enable pll's power */
257 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, 257 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
258 &mxc_ccm->analog_usb1_pll_480_ctrl_set); 258 &mxc_ccm->analog_usb1_pll_480_ctrl_set);
259 writel(0x80, &mxc_ccm->ana_misc2_clr); 259 writel(0x80, &mxc_ccm->ana_misc2_clr);
260 /* wait for pll lock */ 260 /* wait for pll lock */
261 while ((readl(&mxc_ccm->analog_usb1_pll_480_ctrl) & 261 while ((readl(&mxc_ccm->analog_usb1_pll_480_ctrl) &
262 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) 262 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
263 ; 263 ;
264 /* disable bypass */ 264 /* disable bypass */
265 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, 265 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
266 &mxc_ccm->analog_usb1_pll_480_ctrl_clr); 266 &mxc_ccm->analog_usb1_pll_480_ctrl_clr);
267 /* enable pll output */ 267 /* enable pll output */
268 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, 268 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
269 &mxc_ccm->analog_usb1_pll_480_ctrl_set); 269 &mxc_ccm->analog_usb1_pll_480_ctrl_set);
270 } 270 }
271 271
272 ccm_ccgr2 = readl(&mxc_ccm->CCGR2); 272 ccm_ccgr2 = readl(&mxc_ccm->CCGR2);
273 /* enable OCOTP_CTRL clock in CCGR2 */ 273 /* enable OCOTP_CTRL clock in CCGR2 */
274 writel(ccm_ccgr2 | MXC_CCM_CCGR2_OCOTP_CTRL_MASK, &mxc_ccm->CCGR2); 274 writel(ccm_ccgr2 | MXC_CCM_CCGR2_OCOTP_CTRL_MASK, &mxc_ccm->CCGR2);
275 fuse = readl(&fuse_bank1->ana1); 275 fuse = readl(&fuse_bank1->ana1);
276 276
277 /* restore CCGR2 */ 277 /* restore CCGR2 */
278 writel(ccm_ccgr2, &mxc_ccm->CCGR2); 278 writel(ccm_ccgr2, &mxc_ccm->CCGR2);
279 279
280 if (fuse == 0 || fuse == 0xffffffff || (fuse & 0xfff00000) == 0) 280 if (fuse == 0 || fuse == 0xffffffff || (fuse & 0xfff00000) == 0)
281 return TEMPERATURE_MIN; 281 return TEMPERATURE_MIN;
282 282
283 /* 283 /*
284 * fuse data layout: 284 * fuse data layout:
285 * [31:20] sensor value @ 25C 285 * [31:20] sensor value @ 25C
286 * [19:8] sensor value of hot 286 * [19:8] sensor value of hot
287 * [7:0] hot temperature value 287 * [7:0] hot temperature value
288 */ 288 */
289 raw_25c = fuse >> 20; 289 raw_25c = fuse >> 20;
290 290
291 /* 291 /*
292 * The universal equation for thermal sensor 292 * The universal equation for thermal sensor
293 * is slope = 0.4297157 - (0.0015976 * 25C fuse), 293 * is slope = 0.4297157 - (0.0015976 * 25C fuse),
294 * here we convert them to integer to make them 294 * here we convert them to integer to make them
295 * easy for counting, FACTOR1 is 15976, 295 * easy for counting, FACTOR1 is 15976,
296 * FACTOR2 is 4297157. Our ratio = -100 * slope 296 * FACTOR2 is 4297157. Our ratio = -100 * slope
297 */ 297 */
298 ratio = ((FACTOR1 * raw_25c - FACTOR2) + 50000) / 100000; 298 ratio = ((FACTOR1 * raw_25c - FACTOR2) + 50000) / 100000;
299 299
300 debug("Thermal sensor with ratio = %d\n", ratio); 300 debug("Thermal sensor with ratio = %d\n", ratio);
301 301
302 raw_n40c = raw_25c + (13 * ratio) / 20; 302 raw_n40c = raw_25c + (13 * ratio) / 20;
303 303
304 /* 304 /*
305 * now we only use single measure, every time we read 305 * now we only use single measure, every time we read
306 * the temperature, we will power on/down anadig thermal 306 * the temperature, we will power on/down anadig thermal
307 * module 307 * module
308 */ 308 */
309 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &mxc_ccm->tempsense0_clr); 309 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &mxc_ccm->tempsense0_clr);
310 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_set); 310 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_set);
311 311
312 /* write measure freq */ 312 /* write measure freq */
313 reg = readl(&mxc_ccm->tempsense1); 313 reg = readl(&mxc_ccm->tempsense1);
314 reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ; 314 reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ;
315 reg |= MEASURE_FREQ; 315 reg |= MEASURE_FREQ;
316 writel(reg, &mxc_ccm->tempsense1); 316 writel(reg, &mxc_ccm->tempsense1);
317 317
318 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &mxc_ccm->tempsense0_clr); 318 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &mxc_ccm->tempsense0_clr);
319 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &mxc_ccm->tempsense0_clr); 319 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &mxc_ccm->tempsense0_clr);
320 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &mxc_ccm->tempsense0_set); 320 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &mxc_ccm->tempsense0_set);
321 321
322 while ((readl(&mxc_ccm->tempsense0) & 322 while ((readl(&mxc_ccm->tempsense0) &
323 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) 323 BM_ANADIG_TEMPSENSE0_FINISHED) == 0)
324 udelay(10000); 324 udelay(10000);
325 325
326 reg = readl(&mxc_ccm->tempsense0); 326 reg = readl(&mxc_ccm->tempsense0);
327 tmp = (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) 327 tmp = (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
328 >> BP_ANADIG_TEMPSENSE0_TEMP_VALUE; 328 >> BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
329 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &mxc_ccm->tempsense0_clr); 329 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &mxc_ccm->tempsense0_clr);
330 330
331 if (tmp <= raw_n40c) 331 if (tmp <= raw_n40c)
332 temperature = REG_VALUE_TO_CEL(ratio, tmp); 332 temperature = REG_VALUE_TO_CEL(ratio, tmp);
333 else 333 else
334 temperature = TEMPERATURE_MIN; 334 temperature = TEMPERATURE_MIN;
335 /* power down anatop thermal sensor */ 335 /* power down anatop thermal sensor */
336 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &mxc_ccm->tempsense0_set); 336 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &mxc_ccm->tempsense0_set);
337 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_clr); 337 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_clr);
338 338
339 return temperature; 339 return temperature;
340 } 340 }
341 341
342 void check_cpu_temperature(void) 342 void check_cpu_temperature(void)
343 { 343 {
344 int cpu_tmp = 0; 344 int cpu_tmp = 0;
345 345
346 cpu_tmp = read_cpu_temperature(); 346 cpu_tmp = read_cpu_temperature();
347 while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) { 347 while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) {
348 if (cpu_tmp >= TEMPERATURE_HOT) { 348 if (cpu_tmp >= TEMPERATURE_HOT) {
349 printf("CPU is %d C, too hot to boot, waiting...\n", 349 printf("CPU is %d C, too hot to boot, waiting...\n",
350 cpu_tmp); 350 cpu_tmp);
351 udelay(5000000); 351 udelay(5000000);
352 cpu_tmp = read_cpu_temperature(); 352 cpu_tmp = read_cpu_temperature();
353 } else 353 } else
354 break; 354 break;
355 } 355 }
356 if (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) 356 if (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX)
357 printf("CPU: Temperature %d C, calibration data: 0x%x\n", 357 printf("CPU: Temperature %d C, calibration data: 0x%x\n",
358 cpu_tmp, fuse); 358 cpu_tmp, fuse);
359 else 359 else
360 printf("CPU: Temperature: can't get valid data!\n"); 360 printf("CPU: Temperature: can't get valid data!\n");
361 } 361 }
362 362
363 static void set_ahb_rate(u32 val) 363 static void set_ahb_rate(u32 val)
364 { 364 {
365 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 365 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
366 u32 reg, div; 366 u32 reg, div;
367 367
368 div = get_periph_clk() / val - 1; 368 div = get_periph_clk() / val - 1;
369 reg = readl(&mxc_ccm->cbcdr); 369 reg = readl(&mxc_ccm->cbcdr);
370 370
371 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | 371 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
372 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); 372 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
373 } 373 }
374 374
375 static void clear_mmdc_ch_mask(void) 375 static void clear_mmdc_ch_mask(void)
376 { 376 {
377 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 377 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
378 378
379 /* Clear MMDC channel mask */ 379 /* Clear MMDC channel mask */
380 writel(0, &mxc_ccm->ccdr); 380 writel(0, &mxc_ccm->ccdr);
381 } 381 }
382 382
383 static void init_bandgap(void) 383 static void init_bandgap(void)
384 { 384 {
385 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 385 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
386 386
387 /* 387 /*
388 * Ensure the bandgap has stabilized. 388 * Ensure the bandgap has stabilized.
389 */ 389 */
390 while (!(readl(&mxc_ccm->ana_misc0) & 0x80)) 390 while (!(readl(&mxc_ccm->ana_misc0) & 0x80))
391 ; 391 ;
392 /* 392 /*
393 * For best noise performance of the analog blocks using the 393 * For best noise performance of the analog blocks using the
394 * outputs of the bandgap, the reftop_selfbiasoff bit should 394 * outputs of the bandgap, the reftop_selfbiasoff bit should
395 * be set. 395 * be set.
396 */ 396 */
397 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_set); 397 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_set);
398 } 398 }
399 399
400 #ifdef CONFIG_MX6SL 400 #ifdef CONFIG_MX6SL
401 static void set_preclk_from_osc(void) 401 static void set_preclk_from_osc(void)
402 { 402 {
403 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 403 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
404 u32 reg; 404 u32 reg;
405 405
406 reg = readl(&mxc_ccm->cscmr1); 406 reg = readl(&mxc_ccm->cscmr1);
407 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; 407 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
408 writel(reg, &mxc_ccm->cscmr1); 408 writel(reg, &mxc_ccm->cscmr1);
409 } 409 }
410 #endif 410 #endif
411 411
412 #ifdef CONFIG_MX6SX 412 #ifdef CONFIG_MX6SX
413 void vadc_power_up(void) 413 void vadc_power_up(void)
414 { 414 {
415 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_GPR_BASE_ADDR; 415 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_GPR_BASE_ADDR;
416 u32 val; 416 u32 val;
417 417
418 /* csi0 */ 418 /* csi0 */
419 val = readl(&iomux->gpr[5]); 419 val = readl(&iomux->gpr[5]);
420 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, 420 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
421 val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD; 421 val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD;
422 writel(val, &iomux->gpr[5]); 422 writel(val, &iomux->gpr[5]);
423 423
424 /* Power on vadc analog 424 /* Power on vadc analog
425 * Power down vadc ext power */ 425 * Power down vadc ext power */
426 val = readl(GPC_BASE_ADDR + 0); 426 val = readl(GPC_BASE_ADDR + 0);
427 val &= ~0x60000; 427 val &= ~0x60000;
428 writel(val, GPC_BASE_ADDR + 0); 428 writel(val, GPC_BASE_ADDR + 0);
429 429
430 /* software reset afe */ 430 /* software reset afe */
431 val = readl(&iomux->gpr[1]); 431 val = readl(&iomux->gpr[1]);
432 writel(val | 0x80000, &iomux->gpr[1]); 432 writel(val | 0x80000, &iomux->gpr[1]);
433 433
434 udelay(10*1000); 434 udelay(10*1000);
435 435
436 /* Release reset bit */ 436 /* Release reset bit */
437 writel(val & ~0x80000, &iomux->gpr[1]); 437 writel(val & ~0x80000, &iomux->gpr[1]);
438 438
439 /* Power on vadc ext power */ 439 /* Power on vadc ext power */
440 val = readl(GPC_BASE_ADDR + 0); 440 val = readl(GPC_BASE_ADDR + 0);
441 val |= 0x40000; 441 val |= 0x40000;
442 writel(val, GPC_BASE_ADDR + 0); 442 writel(val, GPC_BASE_ADDR + 0);
443 } 443 }
444 444
445 void vadc_power_down(void) 445 void vadc_power_down(void)
446 { 446 {
447 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_GPR_BASE_ADDR; 447 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_GPR_BASE_ADDR;
448 u32 val; 448 u32 val;
449 449
450 /* Power down vadc ext power 450 /* Power down vadc ext power
451 * Power off vadc analog */ 451 * Power off vadc analog */
452 val = readl(GPC_BASE_ADDR + 0); 452 val = readl(GPC_BASE_ADDR + 0);
453 val &= ~0x40000; 453 val &= ~0x40000;
454 val |= 0x20000; 454 val |= 0x20000;
455 writel(val, GPC_BASE_ADDR + 0); 455 writel(val, GPC_BASE_ADDR + 0);
456 456
457 /* clean csi0 connect to vadc */ 457 /* clean csi0 connect to vadc */
458 val = readl(&iomux->gpr[5]); 458 val = readl(&iomux->gpr[5]);
459 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, 459 val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
460 writel(val, &iomux->gpr[5]); 460 writel(val, &iomux->gpr[5]);
461 } 461 }
462 462
463 void pcie_power_up(void) 463 void pcie_power_up(void)
464 { 464 {
465 set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */ 465 set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */
466 } 466 }
467 467
468 void pcie_power_off(void) 468 void pcie_power_off(void)
469 { 469 {
470 set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */ 470 set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */
471 } 471 }
472 #endif 472 #endif
473 473
474 static void imx_set_vddpu_power_down(void) 474 static void imx_set_vddpu_power_down(void)
475 { 475 {
476 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 476 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
477 u32 val; 477 u32 val;
478 478
479 /* need to power down xPU in GPC before turn off PU LDO */ 479 /* need to power down xPU in GPC before turn off PU LDO */
480 val = readl(GPC_BASE_ADDR + 0x260); 480 val = readl(GPC_BASE_ADDR + 0x260);
481 writel(val | 0x1, GPC_BASE_ADDR + 0x260); 481 writel(val | 0x1, GPC_BASE_ADDR + 0x260);
482 482
483 val = readl(GPC_BASE_ADDR + 0x0); 483 val = readl(GPC_BASE_ADDR + 0x0);
484 writel(val | 0x1, GPC_BASE_ADDR + 0x0); 484 writel(val | 0x1, GPC_BASE_ADDR + 0x0);
485 while (readl(GPC_BASE_ADDR + 0x0) & 0x1) 485 while (readl(GPC_BASE_ADDR + 0x0) & 0x1)
486 ; 486 ;
487 487
488 /* disable VDDPU */ 488 /* disable VDDPU */
489 val = 0x3e00; 489 val = 0x3e00;
490 writel(val, &ccm_regs->reg_core_clr); 490 writel(val, &ccm_regs->reg_core_clr);
491 } 491 }
492 492
493 #ifndef CONFIG_MX6SL 493 #ifndef CONFIG_MX6SL
494 static void imx_set_pcie_phy_power_down(void) 494 static void imx_set_pcie_phy_power_down(void)
495 { 495 {
496 u32 val; 496 u32 val;
497 497
498 #ifndef CONFIG_MX6SX 498 #ifndef CONFIG_MX6SX
499 val = readl(IOMUXC_BASE_ADDR + 0x4); 499 val = readl(IOMUXC_BASE_ADDR + 0x4);
500 val |= 0x1 << 18; 500 val |= 0x1 << 18;
501 writel(val, IOMUXC_BASE_ADDR + 0x4); 501 writel(val, IOMUXC_BASE_ADDR + 0x4);
502 #else 502 #else
503 val = readl(IOMUXC_GPR_BASE_ADDR + 0x30); 503 val = readl(IOMUXC_GPR_BASE_ADDR + 0x30);
504 val |= 0x1 << 30; 504 val |= 0x1 << 30;
505 writel(val, IOMUXC_GPR_BASE_ADDR + 0x30); 505 writel(val, IOMUXC_GPR_BASE_ADDR + 0x30);
506 #endif 506 #endif
507 } 507 }
508 #endif 508 #endif
509 509
510 int arch_cpu_init(void) 510 int arch_cpu_init(void)
511 { 511 {
512 /* Clear the Align bit in SCTLR */ 512 /* Clear the Align bit in SCTLR */
513 set_cr(get_cr() & ~CR_A); 513 set_cr(get_cr() & ~CR_A);
514 514
515 #if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6SL) 515 #if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6SL)
516 /* 516 /*
517 * imx6sl doesn't have pcie at all. 517 * imx6sl doesn't have pcie at all.
518 * this bit is not used by imx6sx anymore 518 * this bit is not used by imx6sx anymore
519 */ 519 */
520 u32 val; 520 u32 val;
521 521
522 /* 522 /*
523 * There are about 0.02% percentage, random pcie link down 523 * There are about 0.02% percentage, random pcie link down
524 * when warm-reset is used. 524 * when warm-reset is used.
525 * clear the ref_ssp_en bit16 of gpr1 to workaround it. 525 * clear the ref_ssp_en bit16 of gpr1 to workaround it.
526 * then warm-reset imx6q/dl/solo again. 526 * then warm-reset imx6q/dl/solo again.
527 */ 527 */
528 val = readl(IOMUXC_BASE_ADDR + 0x4); 528 val = readl(IOMUXC_BASE_ADDR + 0x4);
529 if (val & (0x1 << 16)) { 529 if (val & (0x1 << 16)) {
530 val &= ~(0x1 << 16); 530 val &= ~(0x1 << 16);
531 writel(val, IOMUXC_BASE_ADDR + 0x4); 531 writel(val, IOMUXC_BASE_ADDR + 0x4);
532 reset_cpu(0); 532 reset_cpu(0);
533 } 533 }
534 #endif 534 #endif
535 535
536 init_aips(); 536 init_aips();
537 537
538 /* Need to clear MMDC_CHx_MASK to make warm reset work. */ 538 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
539 clear_mmdc_ch_mask(); 539 clear_mmdc_ch_mask();
540 540
541 /* 541 /*
542 * Disable self-bias circuit in the analog bandap. 542 * Disable self-bias circuit in the analog bandap.
543 * The self-bias circuit is used by the bandgap during startup. 543 * The self-bias circuit is used by the bandgap during startup.
544 * This bit should be set after the bandgap has initialized. 544 * This bit should be set after the bandgap has initialized.
545 */ 545 */
546 init_bandgap(); 546 init_bandgap();
547 /* 547 /*
548 * When low freq boot is enabled, ROM will not set AHB 548 * When low freq boot is enabled, ROM will not set AHB
549 * freq, so we need to ensure AHB freq is 132MHz in such 549 * freq, so we need to ensure AHB freq is 132MHz in such
550 * scenario. 550 * scenario.
551 */ 551 */
552 if (mxc_get_clock(MXC_ARM_CLK) == 396000000) 552 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
553 set_ahb_rate(132000000); 553 set_ahb_rate(132000000);
554 554
555 /* Set perclk to source from OSC 24MHz */ 555 /* Set perclk to source from OSC 24MHz */
556 #if defined(CONFIG_MX6SL) 556 #if defined(CONFIG_MX6SL)
557 set_preclk_from_osc(); 557 set_preclk_from_osc();
558 #endif 558 #endif
559 559
560 #ifdef CONFIG_MX6SX 560 #ifdef CONFIG_MX6SX
561 u32 reg; 561 u32 reg;
562 562
563 /* set uart clk to OSC */ 563 /* set uart clk to OSC */
564 reg = readl(CCM_BASE_ADDR + 0x24); 564 reg = readl(CCM_BASE_ADDR + 0x24);
565 reg |= 0x40; 565 reg |= 0x40;
566 writel(reg, CCM_BASE_ADDR + 0x24); 566 writel(reg, CCM_BASE_ADDR + 0x24);
567 #endif 567 #endif
568 568
569 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ 569 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
570 570
571 #ifndef CONFIG_MX6SL 571 #ifndef CONFIG_MX6SL
572 imx_set_pcie_phy_power_down(); 572 imx_set_pcie_phy_power_down();
573 #endif 573 #endif
574 imx_set_vddpu_power_down(); 574 imx_set_vddpu_power_down();
575 575
576 #ifdef CONFIG_APBH_DMA 576 #ifdef CONFIG_APBH_DMA
577 /* Start APBH DMA */ 577 /* Start APBH DMA */
578 mxs_dma_init(); 578 mxs_dma_init();
579 #endif 579 #endif
580 580
581 return 0; 581 return 0;
582 } 582 }
583 583
584 int board_postclk_init(void) 584 int board_postclk_init(void)
585 { 585 {
586 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ 586 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
587 587
588 return 0; 588 return 0;
589 } 589 }
590 590
591 #ifdef CONFIG_SERIAL_TAG 591 #ifdef CONFIG_SERIAL_TAG
592 void get_board_serial(struct tag_serialnr *serialnr) 592 void get_board_serial(struct tag_serialnr *serialnr)
593 { 593 {
594 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 594 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
595 struct fuse_bank *bank = &ocotp->bank[0]; 595 struct fuse_bank *bank = &ocotp->bank[0];
596 struct fuse_bank0_regs *fuse = 596 struct fuse_bank0_regs *fuse =
597 (struct fuse_bank0_regs *)bank->fuse_regs; 597 (struct fuse_bank0_regs *)bank->fuse_regs;
598 598
599 serialnr->low = fuse->uid_low; 599 serialnr->low = fuse->uid_low;
600 serialnr->high = fuse->uid_high; 600 serialnr->high = fuse->uid_high;
601 } 601 }
602 #endif 602 #endif
603 603
604 #ifndef CONFIG_SYS_DCACHE_OFF 604 #ifndef CONFIG_SYS_DCACHE_OFF
605 void enable_caches(void) 605 void enable_caches(void)
606 { 606 {
607 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 607 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
608 enum dcache_option option = DCACHE_WRITETHROUGH; 608 enum dcache_option option = DCACHE_WRITETHROUGH;
609 #else 609 #else
610 enum dcache_option option = DCACHE_WRITEBACK; 610 enum dcache_option option = DCACHE_WRITEBACK;
611 #endif 611 #endif
612 612
613 /* Avoid random hang when download by usb */ 613 /* Avoid random hang when download by usb */
614 invalidate_dcache_all(); 614 invalidate_dcache_all();
615 615
616 /* Enable D-cache. I-cache is already enabled in start.S */ 616 /* Enable D-cache. I-cache is already enabled in start.S */
617 dcache_enable(); 617 dcache_enable();
618 618
619 /* Enable caching on OCRAM and ROM */ 619 /* Enable caching on OCRAM and ROM */
620 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, 620 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
621 ROMCP_ARB_END_ADDR, 621 ROMCP_ARB_END_ADDR,
622 option); 622 option);
623 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, 623 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
624 IRAM_SIZE, 624 IRAM_SIZE,
625 option); 625 option);
626 } 626 }
627 #endif 627 #endif
628 628
629 #if defined(CONFIG_FEC_MXC) 629 #if defined(CONFIG_FEC_MXC)
630 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 630 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
631 { 631 {
632 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 632 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
633 struct fuse_bank *bank = &ocotp->bank[4]; 633 struct fuse_bank *bank = &ocotp->bank[4];
634 struct fuse_bank4_regs *fuse = 634 struct fuse_bank4_regs *fuse =
635 (struct fuse_bank4_regs *)bank->fuse_regs; 635 (struct fuse_bank4_regs *)bank->fuse_regs;
636 636
637 #ifdef CONFIG_MX6SX 637 #ifdef CONFIG_MX6SX
638 if (0 == dev_id) { 638 if (0 == dev_id) {
639 u32 value = readl(&fuse->mac_addr1); 639 u32 value = readl(&fuse->mac_addr1);
640 mac[0] = (value >> 8); 640 mac[0] = (value >> 8);
641 mac[1] = value ; 641 mac[1] = value ;
642 642
643 value = readl(&fuse->mac_addr0); 643 value = readl(&fuse->mac_addr0);
644 mac[2] = value >> 24 ; 644 mac[2] = value >> 24 ;
645 mac[3] = value >> 16 ; 645 mac[3] = value >> 16 ;
646 mac[4] = value >> 8 ; 646 mac[4] = value >> 8 ;
647 mac[5] = value ; 647 mac[5] = value ;
648 } else { 648 } else {
649 u32 value = readl(&fuse->mac_addr2); 649 u32 value = readl(&fuse->mac_addr2);
650 mac[0] = value >> 24 ; 650 mac[0] = value >> 24 ;
651 mac[1] = value >> 16 ; 651 mac[1] = value >> 16 ;
652 mac[2] = value >> 8 ; 652 mac[2] = value >> 8 ;
653 mac[3] = value ; 653 mac[3] = value ;
654 654
655 value = readl(&fuse->mac_addr1); 655 value = readl(&fuse->mac_addr1);
656 mac[4] = value >> 24 ; 656 mac[4] = value >> 24 ;
657 mac[5] = value >> 16 ; 657 mac[5] = value >> 16 ;
658 } 658 }
659 #else 659 #else
660 u32 value = readl(&fuse->mac_addr_high); 660 u32 value = readl(&fuse->mac_addr_high);
661 mac[0] = (value >> 8); 661 mac[0] = (value >> 8);
662 mac[1] = value ; 662 mac[1] = value ;
663 663
664 value = readl(&fuse->mac_addr_low); 664 value = readl(&fuse->mac_addr_low);
665 mac[2] = value >> 24 ; 665 mac[2] = value >> 24 ;
666 mac[3] = value >> 16 ; 666 mac[3] = value >> 16 ;
667 mac[4] = value >> 8 ; 667 mac[4] = value >> 8 ;
668 mac[5] = value ; 668 mac[5] = value ;
669 #endif 669 #endif
670 } 670 }
671 #endif 671 #endif
672 672
673 #ifdef CONFIG_MX6SX 673 #ifdef CONFIG_MX6SX
674 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) 674 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
675 { 675 {
676 struct src *src_reg; 676 struct src *src_reg;
677 u32 stack, pc; 677 u32 stack, pc;
678 678
679 if (!boot_private_data) 679 if (!boot_private_data)
680 return 1; 680 return 1;
681 681
682 stack = *(u32 *)boot_private_data; 682 stack = *(u32 *)boot_private_data;
683 pc = *(u32 *)(boot_private_data + 4); 683 pc = *(u32 *)(boot_private_data + 4);
684 684
685 /* Set the stack and pc to M4 bootROM */ 685 /* Set the stack and pc to M4 bootROM */
686 writel(stack, M4_BOOTROM_BASE_ADDR); 686 writel(stack, M4_BOOTROM_BASE_ADDR);
687 writel(pc, M4_BOOTROM_BASE_ADDR + 4); 687 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
688 688
689 /* Enable M4 */ 689 /* Enable M4 */
690 src_reg = (struct src *)SRC_BASE_ADDR; 690 src_reg = (struct src *)SRC_BASE_ADDR;
691 setbits_le32(&src_reg->scr, 0x00400000); 691 setbits_le32(&src_reg->scr, 0x00400000);
692 clrbits_le32(&src_reg->scr, 0x00000010); 692 clrbits_le32(&src_reg->scr, 0x00000010);
693 693
694 return 0; 694 return 0;
695 } 695 }
696 696
697 int arch_auxiliary_core_check_up(u32 core_id) 697 int arch_auxiliary_core_check_up(u32 core_id)
698 { 698 {
699 struct src *src_reg = (struct src *)SRC_BASE_ADDR; 699 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
700 unsigned val; 700 unsigned val;
701 701
702 val = readl(&src_reg->scr); 702 val = readl(&src_reg->scr);
703 703
704 if (val & 0x00000010) 704 if (val & 0x00000010)
705 return 0; /* assert in reset */ 705 return 0; /* assert in reset */
706 706
707 return 1; 707 return 1;
708 } 708 }
709 #endif 709 #endif
710 710
711 void boot_mode_apply(unsigned cfg_val) 711 void boot_mode_apply(unsigned cfg_val)
712 { 712 {
713 unsigned reg; 713 unsigned reg;
714 struct src *psrc = (struct src *)SRC_BASE_ADDR; 714 struct src *psrc = (struct src *)SRC_BASE_ADDR;
715 writel(cfg_val, &psrc->gpr9); 715 writel(cfg_val, &psrc->gpr9);
716 reg = readl(&psrc->gpr10); 716 reg = readl(&psrc->gpr10);
717 if (cfg_val) 717 if (cfg_val)
718 reg |= 1 << 28; 718 reg |= 1 << 28;
719 else 719 else
720 reg &= ~(1 << 28); 720 reg &= ~(1 << 28);
721 writel(reg, &psrc->gpr10); 721 writel(reg, &psrc->gpr10);
722 } 722 }
723 /* 723 /*
724 * cfg_val will be used for 724 * cfg_val will be used for
725 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] 725 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
726 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] 726 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
727 * to SBMR1, which will determine the boot device. 727 * to SBMR1, which will determine the boot device.
728 */ 728 */
729 const struct boot_mode soc_boot_modes[] = { 729 const struct boot_mode soc_boot_modes[] = {
730 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, 730 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
731 /* reserved value should start rom usb */ 731 /* reserved value should start rom usb */
732 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, 732 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
733 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, 733 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
734 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, 734 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
735 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, 735 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
736 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, 736 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
737 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, 737 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
738 /* 4 bit bus width */ 738 /* 4 bit bus width */
739 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 739 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
740 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 740 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
741 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 741 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
742 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 742 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
743 {NULL, 0}, 743 {NULL, 0},
744 }; 744 };
745 745
746 enum boot_device get_boot_device(void) 746 enum boot_device get_boot_device(void)
747 { 747 {
748 enum boot_device boot_dev = UNKNOWN_BOOT; 748 enum boot_device boot_dev = UNKNOWN_BOOT;
749 uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); 749 uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
750 uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; 750 uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
751 uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; 751 uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
752 uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11; 752 uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11;
753 753
754 switch (bt_mem_ctl) { 754 switch (bt_mem_ctl) {
755 case 0x0: 755 case 0x0:
756 if (bt_mem_type) 756 if (bt_mem_type)
757 boot_dev = ONE_NAND_BOOT; 757 boot_dev = ONE_NAND_BOOT;
758 else 758 else
759 boot_dev = WEIM_NOR_BOOT; 759 boot_dev = WEIM_NOR_BOOT;
760 break; 760 break;
761 case 0x2: 761 case 0x2:
762 boot_dev = SATA_BOOT; 762 boot_dev = SATA_BOOT;
763 break; 763 break;
764 case 0x3: 764 case 0x3:
765 if (bt_mem_type) 765 if (bt_mem_type)
766 boot_dev = I2C_BOOT; 766 boot_dev = I2C_BOOT;
767 else 767 else
768 boot_dev = SPI_NOR_BOOT; 768 boot_dev = SPI_NOR_BOOT;
769 break; 769 break;
770 case 0x4: 770 case 0x4:
771 case 0x5: 771 case 0x5:
772 boot_dev = bt_dev_port + SD1_BOOT; 772 boot_dev = bt_dev_port + SD1_BOOT;
773 break; 773 break;
774 case 0x6: 774 case 0x6:
775 case 0x7: 775 case 0x7:
776 boot_dev = bt_dev_port + MMC1_BOOT; 776 boot_dev = bt_dev_port + MMC1_BOOT;
777 break; 777 break;
778 case 0x8 ... 0xf: 778 case 0x8 ... 0xf:
779 boot_dev = NAND_BOOT; 779 boot_dev = NAND_BOOT;
780 break; 780 break;
781 default: 781 default:
782 boot_dev = UNKNOWN_BOOT; 782 boot_dev = UNKNOWN_BOOT;
783 break; 783 break;
784 } 784 }
785 785
786 return boot_dev; 786 return boot_dev;
787 } 787 }
788 788
789 void s_init(void) 789 void s_init(void)
790 { 790 {
791 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 791 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
792 int is_6sx = is_cpu_type(MXC_CPU_MX6SX); 792 int is_6sx = is_cpu_type(MXC_CPU_MX6SX);
793 u32 mask480; 793 u32 mask480;
794 u32 mask528; 794 u32 mask528;
795 u32 reg, periph1, periph2; 795 u32 reg, periph1, periph2;
796 796
797 /* Don't reset PFD for MX6SX */ 797 /* Don't reset PFD for MX6SX */
798 if (is_6sx) 798 if (is_6sx)
799 return; 799 return;
800 800
801 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs 801 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
802 * to make sure PFD is working right, otherwise, PFDs may 802 * to make sure PFD is working right, otherwise, PFDs may
803 * not output clock after reset, MX6DL and MX6SL have added 396M pfd 803 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
804 * workaround in ROM code, as bus clock need it 804 * workaround in ROM code, as bus clock need it
805 */ 805 */
806 806
807 mask480 = ANATOP_PFD_CLKGATE_MASK(0) | 807 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
808 ANATOP_PFD_CLKGATE_MASK(1) | 808 ANATOP_PFD_CLKGATE_MASK(1) |
809 ANATOP_PFD_CLKGATE_MASK(2) | 809 ANATOP_PFD_CLKGATE_MASK(2) |
810 ANATOP_PFD_CLKGATE_MASK(3); 810 ANATOP_PFD_CLKGATE_MASK(3);
811 mask528 = ANATOP_PFD_CLKGATE_MASK(1) | 811 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
812 ANATOP_PFD_CLKGATE_MASK(3); 812 ANATOP_PFD_CLKGATE_MASK(3);
813 813
814 reg = readl(&ccm->cbcmr); 814 reg = readl(&ccm->cbcmr);
815 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) 815 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
816 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); 816 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
817 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) 817 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
818 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); 818 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
819 819
820 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ 820 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
821 if ((periph2 != 0x2) && (periph1 != 0x2)) 821 if ((periph2 != 0x2) && (periph1 != 0x2))
822 mask528 |= ANATOP_PFD_CLKGATE_MASK(0); 822 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
823 823
824 if ((periph2 != 0x1) && (periph1 != 0x1) && 824 if ((periph2 != 0x1) && (periph1 != 0x1) &&
825 (periph2 != 0x3) && (periph1 != 0x3)) 825 (periph2 != 0x3) && (periph1 != 0x3))
826 mask528 |= ANATOP_PFD_CLKGATE_MASK(2); 826 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
827 827
828 writel(mask480, &ccm->analog_pfd_480_set); 828 writel(mask480, &ccm->analog_pfd_480_set);
829 writel(mask528, &ccm->analog_pfd_528_set); 829 writel(mask528, &ccm->analog_pfd_528_set);
830 writel(mask480, &ccm->analog_pfd_480_clr); 830 writel(mask480, &ccm->analog_pfd_480_clr);
831 writel(mask528, &ccm->analog_pfd_528_clr); 831 writel(mask528, &ccm->analog_pfd_528_clr);
832 } 832 }
833 833
834 #ifdef CONFIG_LDO_BYPASS_CHECK 834 #ifdef CONFIG_LDO_BYPASS_CHECK
835 DECLARE_GLOBAL_DATA_PTR; 835 DECLARE_GLOBAL_DATA_PTR;
836 static int ldo_bypass; 836 static int ldo_bypass;
837 837
838 int check_ldo_bypass(void) 838 int check_ldo_bypass(void)
839 { 839 {
840 const int *ldo_mode; 840 const int *ldo_mode;
841 int node; 841 int node;
842 842
843 /* get the right fdt_blob from the global working_fdt */ 843 /* get the right fdt_blob from the global working_fdt */
844 gd->fdt_blob = working_fdt; 844 gd->fdt_blob = working_fdt;
845 /* Get the node from FDT for anatop ldo-bypass */ 845 /* Get the node from FDT for anatop ldo-bypass */
846 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 846 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
847 "fsl,imx6q-gpc"); 847 "fsl,imx6q-gpc");
848 if (node < 0) { 848 if (node < 0) {
849 printf("No gpc device node %d, force to ldo-enable.\n", node); 849 printf("No gpc device node %d, force to ldo-enable.\n", node);
850 return 0; 850 return 0;
851 } 851 }
852 ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL); 852 ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL);
853 /* 853 /*
854 * return 1 if "fsl,ldo-bypass = <1>", else return 0 if 854 * return 1 if "fsl,ldo-bypass = <1>", else return 0 if
855 * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property 855 * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property
856 */ 856 */
857 ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0; 857 ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0;
858 858
859 return ldo_bypass; 859 return ldo_bypass;
860 } 860 }
861 861
862 int check_1_2G(void) 862 int check_1_2G(void)
863 { 863 {
864 u32 reg; 864 u32 reg;
865 int result = 0; 865 int result = 0;
866 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 866 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
867 struct fuse_bank *bank = &ocotp->bank[0]; 867 struct fuse_bank *bank = &ocotp->bank[0];
868 struct fuse_bank0_regs *fuse_bank0 = 868 struct fuse_bank0_regs *fuse_bank0 =
869 (struct fuse_bank0_regs *)bank->fuse_regs; 869 (struct fuse_bank0_regs *)bank->fuse_regs;
870 870
871 reg = readl(&fuse_bank0->cfg3); 871 reg = readl(&fuse_bank0->cfg3);
872 if (((reg >> 16) & 0x3) == 0x3) { 872 if (((reg >> 16) & 0x3) == 0x3) {
873 if (ldo_bypass) { 873 if (ldo_bypass) {
874 printf("Wrong dtb file used! i.MX6Q@1.2Ghz only " 874 printf("Wrong dtb file used! i.MX6Q@1.2Ghz only "
875 "works with ldo-enable mode!\n"); 875 "works with ldo-enable mode!\n");
876 /* 876 /*
877 * Currently, only imx6q-sabresd board might be here, 877 * Currently, only imx6q-sabresd board might be here,
878 * since only i.MX6Q support 1.2G and only Sabresd board 878 * since only i.MX6Q support 1.2G and only Sabresd board
879 * support ldo-bypass mode. So hardcode here. 879 * support ldo-bypass mode. So hardcode here.
880 * You can also modify your board(i.MX6Q) dtb name if it 880 * You can also modify your board(i.MX6Q) dtb name if it
881 * supports both ldo-bypass and ldo-enable mode. 881 * supports both ldo-bypass and ldo-enable mode.
882 */ 882 */
883 printf("Please use imx6q-sabresd-ldo.dtb!\n"); 883 printf("Please use imx6q-sabresd-ldo.dtb!\n");
884 hang(); 884 hang();
885 } 885 }
886 result = 1; 886 result = 1;
887 } 887 }
888 888
889 return result; 889 return result;
890 } 890 }
891 891
892 static int arm_orig_podf; 892 static int arm_orig_podf;
893 void set_arm_freq_400M(bool is_400M) 893 void set_arm_freq_400M(bool is_400M)
894 { 894 {
895 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 895 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
896 896
897 if (is_400M) 897 if (is_400M)
898 writel(0x1, &mxc_ccm->cacrr); 898 writel(0x1, &mxc_ccm->cacrr);
899 else 899 else
900 writel(arm_orig_podf, &mxc_ccm->cacrr); 900 writel(arm_orig_podf, &mxc_ccm->cacrr);
901 } 901 }
902 902
903 void prep_anatop_bypass(void) 903 void prep_anatop_bypass(void)
904 { 904 {
905 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 905 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
906 906
907 arm_orig_podf = readl(&mxc_ccm->cacrr); 907 arm_orig_podf = readl(&mxc_ccm->cacrr);
908 /* 908 /*
909 * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo 909 * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo
910 * bypassed, also downgrade internal vddarm ldo to 0.975V. 910 * bypassed, also downgrade internal vddarm ldo to 0.975V.
911 * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V) 911 * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V)
912 * otherwise at 800Mhz(i.mx6dl): 912 * otherwise at 800Mhz(i.mx6dl):
913 * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V) 913 * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V)
914 * We need provide enough gap in this case. 914 * We need provide enough gap in this case.
915 * skip if boot from 400M. 915 * skip if boot from 400M.
916 */ 916 */
917 if (!arm_orig_podf) 917 if (!arm_orig_podf)
918 set_arm_freq_400M(true); 918 set_arm_freq_400M(true);
919 #if !defined(CONFIG_MX6DL) && !defined(CONFIG_MX6SX) 919 #if !defined(CONFIG_MX6DL) && !defined(CONFIG_MX6SX)
920 set_ldo_voltage(LDO_ARM, 975); 920 set_ldo_voltage(LDO_ARM, 975);
921 #else 921 #else
922 set_ldo_voltage(LDO_ARM, 1150); 922 set_ldo_voltage(LDO_ARM, 1150);
923 #endif 923 #endif
924 } 924 }
925 925
926 int set_anatop_bypass(int wdog_reset_pin) 926 void set_wdog_reset(struct wdog_regs *wdog)
927 { 927 {
928 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 928 u32 reg = readw(&wdog->wcr);
929 struct wdog_regs *wdog;
930 u32 reg = readl(&ccm_regs->reg_core);
931
932 /* bypass VDDARM/VDDSOC */
933 reg = reg | (0x1F << 18) | 0x1F;
934 writel(reg, &ccm_regs->reg_core);
935
936 if (wdog_reset_pin == 2)
937 wdog = (struct wdog_regs *) WDOG2_BASE_ADDR;
938 else if (wdog_reset_pin == 1)
939 wdog = (struct wdog_regs *) WDOG1_BASE_ADDR;
940 else
941 return arm_orig_podf;
942 /* 929 /*
943 * use WDOG_B mode to reset external pmic because it's risky for the 930 * use WDOG_B mode to reset external pmic because it's risky for the
944 * following watchdog reboot in case of cpu freq at lowest 400Mhz with 931 * following watchdog reboot in case of cpu freq at lowest 400Mhz with
945 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So 932 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So
946 * in ldo-bypass mode watchdog reset will only triger POR reset, not 933 * in ldo-bypass mode watchdog reset will only triger POR reset, not
947 * WDOG reset. But below code depends on hardware design, if HW didn't 934 * WDOG reset. But below code depends on hardware design, if HW didn't
948 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip 935 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip
949 * these code since it assumed boot from 400Mhz always. 936 * these code since it assumed boot from 400Mhz always.
950 */ 937 */
951 reg = readw(&wdog->wcr); 938 reg = readw(&wdog->wcr);
952 reg |= 1 << 3; 939 reg |= 1 << 3;
953 /* 940 /*
954 * WDZST bit is write-once only bit. Align this bit in kernel, 941 * WDZST bit is write-once only bit. Align this bit in kernel,
955 * otherwise kernel code will have no chance to set this bit. 942 * otherwise kernel code will have no chance to set this bit.
956 */ 943 */
957 reg |= 1 << 0; 944 reg |= 1 << 0;
958 writew(reg, &wdog->wcr); 945 writew(reg, &wdog->wcr);
946 }
959 947
948 int set_anatop_bypass(int wdog_reset_pin)
949 {
950 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
951 struct wdog_regs *wdog;
952 u32 reg = readl(&ccm_regs->reg_core);
953
954 /* bypass VDDARM/VDDSOC */
955 reg = reg | (0x1F << 18) | 0x1F;
956 writel(reg, &ccm_regs->reg_core);
957
958 if (wdog_reset_pin == 2)
959 wdog = (struct wdog_regs *) WDOG2_BASE_ADDR;
960 else if (wdog_reset_pin == 1)
961 wdog = (struct wdog_regs *) WDOG1_BASE_ADDR;
962 else
963 return arm_orig_podf;
964 set_wdog_reset(wdog);
960 return arm_orig_podf; 965 return arm_orig_podf;
961 } 966 }
962 967
963 void finish_anatop_bypass(void) 968 void finish_anatop_bypass(void)
964 { 969 {
965 if (!arm_orig_podf) 970 if (!arm_orig_podf)
966 set_arm_freq_400M(false); 971 set_arm_freq_400M(false);
967 } 972 }
968 973
969 #endif 974 #endif
970 975
971 #ifdef CONFIG_IMX_HDMI 976 #ifdef CONFIG_IMX_HDMI
972 void imx_enable_hdmi_phy(void) 977 void imx_enable_hdmi_phy(void)
973 { 978 {
974 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 979 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
975 u8 reg; 980 u8 reg;
976 reg = readb(&hdmi->phy_conf0); 981 reg = readb(&hdmi->phy_conf0);
977 reg |= HDMI_PHY_CONF0_PDZ_MASK; 982 reg |= HDMI_PHY_CONF0_PDZ_MASK;
978 writeb(reg, &hdmi->phy_conf0); 983 writeb(reg, &hdmi->phy_conf0);
979 udelay(3000); 984 udelay(3000);
980 reg |= HDMI_PHY_CONF0_ENTMDS_MASK; 985 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
981 writeb(reg, &hdmi->phy_conf0); 986 writeb(reg, &hdmi->phy_conf0);
982 udelay(3000); 987 udelay(3000);
983 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; 988 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
984 writeb(reg, &hdmi->phy_conf0); 989 writeb(reg, &hdmi->phy_conf0);
985 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); 990 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
986 } 991 }
987 992
988 void imx_setup_hdmi(void) 993 void imx_setup_hdmi(void)
989 { 994 {
990 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 995 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
991 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 996 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
992 int reg, count; 997 int reg, count;
993 u8 val; 998 u8 val;
994 999
995 /* Turn on HDMI PHY clock */ 1000 /* Turn on HDMI PHY clock */
996 reg = readl(&mxc_ccm->CCGR2); 1001 reg = readl(&mxc_ccm->CCGR2);
997 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| 1002 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
998 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; 1003 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
999 writel(reg, &mxc_ccm->CCGR2); 1004 writel(reg, &mxc_ccm->CCGR2);
1000 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); 1005 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
1001 reg = readl(&mxc_ccm->chsccdr); 1006 reg = readl(&mxc_ccm->chsccdr);
1002 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| 1007 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
1003 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| 1008 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
1004 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); 1009 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
1005 reg |= (CHSCCDR_PODF_DIVIDE_BY_3 1010 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
1006 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) 1011 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
1007 |(CHSCCDR_IPU_PRE_CLK_540M_PFD 1012 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
1008 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); 1013 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
1009 writel(reg, &mxc_ccm->chsccdr); 1014 writel(reg, &mxc_ccm->chsccdr);
1010 1015
1011 /* Workaround to clear the overflow condition */ 1016 /* Workaround to clear the overflow condition */
1012 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { 1017 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
1013 /* TMDS software reset */ 1018 /* TMDS software reset */
1014 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); 1019 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
1015 val = readb(&hdmi->fc_invidconf); 1020 val = readb(&hdmi->fc_invidconf);
1016 for (count = 0 ; count < 5 ; count++) 1021 for (count = 0 ; count < 5 ; count++)
1017 writeb(val, &hdmi->fc_invidconf); 1022 writeb(val, &hdmi->fc_invidconf);
1018 } 1023 }
1019 } 1024 }
1020 #endif 1025 #endif
1021 1026
1022 #ifndef CONFIG_SYS_L2CACHE_OFF 1027 #ifndef CONFIG_SYS_L2CACHE_OFF
1023 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 1028 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
1024 void v7_outer_cache_enable(void) 1029 void v7_outer_cache_enable(void)
1025 { 1030 {
1026 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; 1031 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
1027 unsigned int val; 1032 unsigned int val;
1028 1033
1029 #if defined CONFIG_MX6SL 1034 #if defined CONFIG_MX6SL
1030 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 1035 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
1031 val = readl(&iomux->gpr[11]); 1036 val = readl(&iomux->gpr[11]);
1032 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { 1037 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
1033 /* L2 cache configured as OCRAM, reset it */ 1038 /* L2 cache configured as OCRAM, reset it */
1034 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; 1039 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
1035 writel(val, &iomux->gpr[11]); 1040 writel(val, &iomux->gpr[11]);
1036 } 1041 }
1037 #endif 1042 #endif
1038 1043
1039 /* Must disable the L2 before changing the latency parameters */ 1044 /* Must disable the L2 before changing the latency parameters */
1040 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 1045 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
1041 1046
1042 writel(0x132, &pl310->pl310_tag_latency_ctrl); 1047 writel(0x132, &pl310->pl310_tag_latency_ctrl);
1043 writel(0x132, &pl310->pl310_data_latency_ctrl); 1048 writel(0x132, &pl310->pl310_data_latency_ctrl);
1044 1049
1045 val = readl(&pl310->pl310_prefetch_ctrl); 1050 val = readl(&pl310->pl310_prefetch_ctrl);
1046 1051
1047 /* Turn on the L2 I/D prefetch */ 1052 /* Turn on the L2 I/D prefetch */
1048 val |= 0x30000000; 1053 val |= 0x30000000;
1049 1054
1050 /* 1055 /*
1051 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 1056 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
1052 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 1057 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
1053 * But according to ARM PL310 errata: 752271 1058 * But according to ARM PL310 errata: 752271
1054 * ID: 752271: Double linefill feature can cause data corruption 1059 * ID: 752271: Double linefill feature can cause data corruption
1055 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 1060 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
1056 * Workaround: The only workaround to this erratum is to disable the 1061 * Workaround: The only workaround to this erratum is to disable the
1057 * double linefill feature. This is the default behavior. 1062 * double linefill feature. This is the default behavior.
1058 */ 1063 */
1059 1064
1060 #ifndef CONFIG_MX6Q 1065 #ifndef CONFIG_MX6Q
1061 val |= 0x40800000; 1066 val |= 0x40800000;
1062 #endif 1067 #endif
1063 writel(val, &pl310->pl310_prefetch_ctrl); 1068 writel(val, &pl310->pl310_prefetch_ctrl);
1064 1069
1065 val = readl(&pl310->pl310_power_ctrl); 1070 val = readl(&pl310->pl310_power_ctrl);
1066 val |= L2X0_DYNAMIC_CLK_GATING_EN; 1071 val |= L2X0_DYNAMIC_CLK_GATING_EN;
1067 val |= L2X0_STNDBY_MODE_EN; 1072 val |= L2X0_STNDBY_MODE_EN;
1068 writel(val, &pl310->pl310_power_ctrl); 1073 writel(val, &pl310->pl310_power_ctrl);
1069 1074
1070 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 1075 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
1071 } 1076 }
1072 1077
1073 void v7_outer_cache_disable(void) 1078 void v7_outer_cache_disable(void)
1074 { 1079 {
1075 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; 1080 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
1076 1081
1077 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 1082 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
1078 } 1083 }
1079 #endif /* !CONFIG_SYS_L2CACHE_OFF */ 1084 #endif /* !CONFIG_SYS_L2CACHE_OFF */
1080 1085
1081 #ifdef CONFIG_FASTBOOT 1086 #ifdef CONFIG_FASTBOOT
1082 1087
1083 #ifdef CONFIG_ANDROID_RECOVERY 1088 #ifdef CONFIG_ANDROID_RECOVERY
1084 #define ANDROID_RECOVERY_BOOT (1 << 7) 1089 #define ANDROID_RECOVERY_BOOT (1 << 7)
1085 /* check if the recovery bit is set by kernel, it can be set by kernel 1090 /* check if the recovery bit is set by kernel, it can be set by kernel
1086 * issue a command '# reboot recovery' */ 1091 * issue a command '# reboot recovery' */
1087 int recovery_check_and_clean_flag(void) 1092 int recovery_check_and_clean_flag(void)
1088 { 1093 {
1089 int flag_set = 0; 1094 int flag_set = 0;
1090 u32 reg; 1095 u32 reg;
1091 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR); 1096 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR);
1092 1097
1093 flag_set = !!(reg & ANDROID_RECOVERY_BOOT); 1098 flag_set = !!(reg & ANDROID_RECOVERY_BOOT);
1094 printf("check_and_clean: reg %x, flag_set %d\n", reg, flag_set); 1099 printf("check_and_clean: reg %x, flag_set %d\n", reg, flag_set);
1095 /* clean it in case looping infinite here.... */ 1100 /* clean it in case looping infinite here.... */
1096 if (flag_set) { 1101 if (flag_set) {
1097 reg &= ~ANDROID_RECOVERY_BOOT; 1102 reg &= ~ANDROID_RECOVERY_BOOT;
1098 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR); 1103 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR);
1099 } 1104 }
1100 1105
1101 return flag_set; 1106 return flag_set;
1102 } 1107 }
1103 #endif /*CONFIG_ANDROID_RECOVERY*/ 1108 #endif /*CONFIG_ANDROID_RECOVERY*/
1104 1109
1105 #define ANDROID_FASTBOOT_BOOT (1 << 8) 1110 #define ANDROID_FASTBOOT_BOOT (1 << 8)
1106 /* check if the recovery bit is set by kernel, it can be set by kernel 1111 /* check if the recovery bit is set by kernel, it can be set by kernel
1107 * issue a command '# reboot fastboot' */ 1112 * issue a command '# reboot fastboot' */
1108 int fastboot_check_and_clean_flag(void) 1113 int fastboot_check_and_clean_flag(void)
1109 { 1114 {
1110 int flag_set = 0; 1115 int flag_set = 0;
1111 u32 reg; 1116 u32 reg;
1112 1117
1113 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR); 1118 reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR);
1114 1119
1115 flag_set = !!(reg & ANDROID_FASTBOOT_BOOT); 1120 flag_set = !!(reg & ANDROID_FASTBOOT_BOOT);
1116 1121
1117 /* clean it in case looping infinite here.... */ 1122 /* clean it in case looping infinite here.... */
1118 if (flag_set) { 1123 if (flag_set) {
1119 reg &= ~ANDROID_FASTBOOT_BOOT; 1124 reg &= ~ANDROID_FASTBOOT_BOOT;
1120 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR); 1125 writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR);
1121 } 1126 }
1122 1127
1123 return flag_set; 1128 return flag_set;
1124 } 1129 }
1125 #endif /*CONFIG_FASTBOOT*/ 1130 #endif /*CONFIG_FASTBOOT*/
1126 1131
1127 #ifdef CONFIG_IMX_UDC 1132 #ifdef CONFIG_IMX_UDC
1128 void set_usboh3_clk(void) 1133 void set_usboh3_clk(void)
1129 { 1134 {
1130 udc_pins_setting(); 1135 udc_pins_setting();
1131 } 1136 }
1132 1137
1133 void set_usb_phy1_clk(void) 1138 void set_usb_phy1_clk(void)
1134 { 1139 {
1135 /* make sure pll3 is enable here */ 1140 /* make sure pll3 is enable here */
1136 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1141 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1137 1142
1138 writel((BM_ANADIG_USB1_CHRG_DETECT_EN_B | 1143 writel((BM_ANADIG_USB1_CHRG_DETECT_EN_B |
1139 BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B), 1144 BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B),
1140 &ccm_regs->usb1_chrg_detect_set); 1145 &ccm_regs->usb1_chrg_detect_set);
1141 1146
1142 writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS, 1147 writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
1143 &ccm_regs->analog_usb1_pll_480_ctrl_set); 1148 &ccm_regs->analog_usb1_pll_480_ctrl_set);
1144 } 1149 }
1145 void enable_usb_phy1_clk(unsigned char enable) 1150 void enable_usb_phy1_clk(unsigned char enable)
1146 { 1151 {
1147 if (enable) 1152 if (enable)
1148 writel(BM_USBPHY_CTRL_CLKGATE, 1153 writel(BM_USBPHY_CTRL_CLKGATE,
1149 USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_CLR); 1154 USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_CLR);
1150 else 1155 else
1151 writel(BM_USBPHY_CTRL_CLKGATE, 1156 writel(BM_USBPHY_CTRL_CLKGATE,
1152 USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_SET); 1157 USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_SET);
1153 } 1158 }
1154 1159
1155 void reset_usb_phy1(void) 1160 void reset_usb_phy1(void)
1156 { 1161 {
1157 /* Reset USBPHY module */ 1162 /* Reset USBPHY module */
1158 u32 temp; 1163 u32 temp;
1159 temp = readl(USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); 1164 temp = readl(USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL);
1160 temp |= BM_USBPHY_CTRL_SFTRST; 1165 temp |= BM_USBPHY_CTRL_SFTRST;
1161 writel(temp, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); 1166 writel(temp, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL);
arch/arm/include/asm/arch-mx6/sys_proto.h
Diff comments   View file @ 99b0b68
1 /* 1 /*
2 * (C) Copyright 2009 2 * (C) Copyright 2009
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef _SYS_PROTO_H_ 8 #ifndef _SYS_PROTO_H_
9 #define _SYS_PROTO_H_ 9 #define _SYS_PROTO_H_
10 10
11 #include <asm/imx-common/regs-common.h> 11 #include <asm/imx-common/regs-common.h>
12 #include "../arch-imx/cpu.h" 12 #include "../arch-imx/cpu.h"
13 13
14 #define is_soc_rev(rev) ((int)((get_cpu_rev() & 0xFF) - rev)) 14 #define is_soc_rev(rev) ((int)((get_cpu_rev() & 0xFF) - rev))
15 u32 get_cpu_rev(void); 15 u32 get_cpu_rev(void);
16 16
17 /* returns MXC_CPU_ value */ 17 /* returns MXC_CPU_ value */
18 #define cpu_type(rev) (((rev) >> 12)&0xff) 18 #define cpu_type(rev) (((rev) >> 12)&0xff)
19 19
20 /* use with MXC_CPU_ constants */ 20 /* use with MXC_CPU_ constants */
21 #define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu) 21 #define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
22 22
23 const char *get_imx_type(u32 imxtype); 23 const char *get_imx_type(u32 imxtype);
24 unsigned imx_ddr_size(void); 24 unsigned imx_ddr_size(void);
25 void set_wdog_reset(struct wdog_regs *wdog);
25 26
26 #ifdef CONFIG_LDO_BYPASS_CHECK 27 #ifdef CONFIG_LDO_BYPASS_CHECK
27 int check_ldo_bypass(void); 28 int check_ldo_bypass(void);
28 int check_1_2G(void); 29 int check_1_2G(void);
29 int set_anatop_bypass(int wdog_reset_pin); 30 int set_anatop_bypass(int wdog_reset_pin);
30 void ldo_mode_set(int ldo_bypass); 31 void ldo_mode_set(int ldo_bypass);
31 void prep_anatop_bypass(void); 32 void prep_anatop_bypass(void);
32 void finish_anatop_bypass(void); 33 void finish_anatop_bypass(void);
33 #endif 34 #endif
34 35
35 #ifdef CONFIG_MX6SX 36 #ifdef CONFIG_MX6SX
36 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data); 37 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data);
37 int arch_auxiliary_core_check_up(u32 core_id); 38 int arch_auxiliary_core_check_up(u32 core_id);
38 #endif 39 #endif
39 40
40 /* 41 /*
41 * Initializes on-chip ethernet controllers. 42 * Initializes on-chip ethernet controllers.
42 * to override, implement board_eth_init() 43 * to override, implement board_eth_init()
43 */ 44 */
44 45
45 int fecmxc_initialize(bd_t *bis); 46 int fecmxc_initialize(bd_t *bis);
46 u32 get_ahb_clk(void); 47 u32 get_ahb_clk(void);
47 u32 get_periph_clk(void); 48 u32 get_periph_clk(void);
48 49
49 int mxs_reset_block(struct mxs_register_32 *reg); 50 int mxs_reset_block(struct mxs_register_32 *reg);
50 int mxs_wait_mask_set(struct mxs_register_32 *reg, 51 int mxs_wait_mask_set(struct mxs_register_32 *reg,
51 uint32_t mask, 52 uint32_t mask,
52 unsigned int timeout); 53 unsigned int timeout);
53 int mxs_wait_mask_clr(struct mxs_register_32 *reg, 54 int mxs_wait_mask_clr(struct mxs_register_32 *reg,
54 uint32_t mask, 55 uint32_t mask,
55 unsigned int timeout); 56 unsigned int timeout);
56 #endif 57 #endif
57 58