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Commit 9a63b7f4f8f3c99cf017e0d3d4a152dfcd913b5a

Authored by Wolfgang Denk
1 parent e3ba7f137c
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Enable ext2 support for TQM8xxL/M based boards 

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 13 changed files with 13 additions and 0 deletions Inline Diff

include/configs/TQM823L.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37 #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ 37 #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
38 38
39 #ifdef CONFIG_LCD /* with LCD controller ? */ 39 #ifdef CONFIG_LCD /* with LCD controller ? */
40 #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ 40 #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
41 #define CONFIG_LCD_INFO 1 /* ... and some board info */ 41 #define CONFIG_LCD_INFO 1 /* ... and some board info */
42 #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ 42 #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
43 #endif 43 #endif
44 44
45 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 45 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
46 #undef CONFIG_8xx_CONS_SMC2 46 #undef CONFIG_8xx_CONS_SMC2
47 #undef CONFIG_8xx_CONS_NONE 47 #undef CONFIG_8xx_CONS_NONE
48 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 48 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
49 49
50 #define CONFIG_BOOTCOUNT_LIMIT 50 #define CONFIG_BOOTCOUNT_LIMIT
51 51
52 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 52 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
53 53
54 #define CONFIG_BOARD_TYPES 1 /* support board types */ 54 #define CONFIG_BOARD_TYPES 1 /* support board types */
55 55
56 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 56 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
57 57
58 #undef CONFIG_BOOTARGS 58 #undef CONFIG_BOOTARGS
59 59
60 #define CONFIG_EXTRA_ENV_SETTINGS \ 60 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "netdev=eth0\0" \ 61 "netdev=eth0\0" \
62 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 62 "nfsargs=setenv bootargs root=/dev/nfs rw " \
63 "nfsroot=${serverip}:${rootpath}\0" \ 63 "nfsroot=${serverip}:${rootpath}\0" \
64 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 64 "ramargs=setenv bootargs root=/dev/ram rw\0" \
65 "addip=setenv bootargs ${bootargs} " \ 65 "addip=setenv bootargs ${bootargs} " \
66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
67 ":${hostname}:${netdev}:off panic=1\0" \ 67 ":${hostname}:${netdev}:off panic=1\0" \
68 "flash_nfs=run nfsargs addip;" \ 68 "flash_nfs=run nfsargs addip;" \
69 "bootm ${kernel_addr}\0" \ 69 "bootm ${kernel_addr}\0" \
70 "flash_self=run ramargs addip;" \ 70 "flash_self=run ramargs addip;" \
71 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 71 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
73 "rootpath=/opt/eldk/ppc_8xx\0" \ 73 "rootpath=/opt/eldk/ppc_8xx\0" \
74 "hostname=TQM823L\0" \ 74 "hostname=TQM823L\0" \
75 "bootfile=TQM823L/uImage\0" \ 75 "bootfile=TQM823L/uImage\0" \
76 "fdt_addr=40040000\0" \ 76 "fdt_addr=40040000\0" \
77 "kernel_addr=40060000\0" \ 77 "kernel_addr=40060000\0" \
78 "ramdisk_addr=40200000\0" \ 78 "ramdisk_addr=40200000\0" \
79 "u-boot=TQM823L/u-image.bin\0" \ 79 "u-boot=TQM823L/u-image.bin\0" \
80 "load=tftp 200000 ${u-boot}\0" \ 80 "load=tftp 200000 ${u-boot}\0" \
81 "update=prot off 40000000 +${filesize};" \ 81 "update=prot off 40000000 +${filesize};" \
82 "era 40000000 +${filesize};" \ 82 "era 40000000 +${filesize};" \
83 "cp.b 200000 40000000 ${filesize};" \ 83 "cp.b 200000 40000000 ${filesize};" \
84 "sete filesize;save\0" \ 84 "sete filesize;save\0" \
85 "" 85 ""
86 #define CONFIG_BOOTCOMMAND "run flash_self" 86 #define CONFIG_BOOTCOMMAND "run flash_self"
87 87
88 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 88 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
89 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 89 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
90 90
91 #undef CONFIG_WATCHDOG /* watchdog disabled */ 91 #undef CONFIG_WATCHDOG /* watchdog disabled */
92 92
93 #if defined(CONFIG_LCD) 93 #if defined(CONFIG_LCD)
94 # undef CONFIG_STATUS_LED /* disturbs display */ 94 # undef CONFIG_STATUS_LED /* disturbs display */
95 #else 95 #else
96 # define CONFIG_STATUS_LED 1 /* Status LED enabled */ 96 # define CONFIG_STATUS_LED 1 /* Status LED enabled */
97 #endif /* CONFIG_LCD */ 97 #endif /* CONFIG_LCD */
98 98
99 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 99 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
100 100
101 /* 101 /*
102 * BOOTP options 102 * BOOTP options
103 */ 103 */
104 #define CONFIG_BOOTP_SUBNETMASK 104 #define CONFIG_BOOTP_SUBNETMASK
105 #define CONFIG_BOOTP_GATEWAY 105 #define CONFIG_BOOTP_GATEWAY
106 #define CONFIG_BOOTP_HOSTNAME 106 #define CONFIG_BOOTP_HOSTNAME
107 #define CONFIG_BOOTP_BOOTPATH 107 #define CONFIG_BOOTP_BOOTPATH
108 #define CONFIG_BOOTP_BOOTFILESIZE 108 #define CONFIG_BOOTP_BOOTFILESIZE
109 109
110 110
111 #define CONFIG_MAC_PARTITION 111 #define CONFIG_MAC_PARTITION
112 #define CONFIG_DOS_PARTITION 112 #define CONFIG_DOS_PARTITION
113 113
114 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 114 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
115 115
116 116
117 /* 117 /*
118 * Command line configuration. 118 * Command line configuration.
119 */ 119 */
120 #include <config_cmd_default.h> 120 #include <config_cmd_default.h>
121 121
122 #define CONFIG_CMD_ASKENV 122 #define CONFIG_CMD_ASKENV
123 #define CONFIG_CMD_DATE 123 #define CONFIG_CMD_DATE
124 #define CONFIG_CMD_DHCP 124 #define CONFIG_CMD_DHCP
125 #define CONFIG_CMD_ELF 125 #define CONFIG_CMD_ELF
126 #define CONFIG_CMD_EXT2
126 #define CONFIG_CMD_IDE 127 #define CONFIG_CMD_IDE
127 #define CONFIG_CMD_JFFS2 128 #define CONFIG_CMD_JFFS2
128 #define CONFIG_CMD_NFS 129 #define CONFIG_CMD_NFS
129 #define CONFIG_CMD_SNTP 130 #define CONFIG_CMD_SNTP
130 131
131 #ifdef CONFIG_SPLASH_SCREEN 132 #ifdef CONFIG_SPLASH_SCREEN
132 #define CONFIG_CMD_BMP 133 #define CONFIG_CMD_BMP
133 #endif 134 #endif
134 135
135 136
136 #define CONFIG_NETCONSOLE 137 #define CONFIG_NETCONSOLE
137 138
138 /* 139 /*
139 * Miscellaneous configurable options 140 * Miscellaneous configurable options
140 */ 141 */
141 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 142 #define CONFIG_SYS_LONGHELP /* undef to save memory */
142 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 143 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
143 144
144 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 145 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
145 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 146 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
146 #ifdef CONFIG_SYS_HUSH_PARSER 147 #ifdef CONFIG_SYS_HUSH_PARSER
147 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 148 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
148 #endif 149 #endif
149 150
150 #if defined(CONFIG_CMD_KGDB) 151 #if defined(CONFIG_CMD_KGDB)
151 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 152 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
152 #else 153 #else
153 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 154 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
154 #endif 155 #endif
155 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 156 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
156 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 157 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
157 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 158 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
158 159
159 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 160 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
160 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 161 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
161 162
162 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 163 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
163 164
164 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 165 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
165 166
166 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 167 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
167 168
168 /* 169 /*
169 * Low Level Configuration Settings 170 * Low Level Configuration Settings
170 * (address mappings, register initial values, etc.) 171 * (address mappings, register initial values, etc.)
171 * You should know what you are doing if you make changes here. 172 * You should know what you are doing if you make changes here.
172 */ 173 */
173 /*----------------------------------------------------------------------- 174 /*-----------------------------------------------------------------------
174 * Internal Memory Mapped Register 175 * Internal Memory Mapped Register
175 */ 176 */
176 #define CONFIG_SYS_IMMR 0xFFF00000 177 #define CONFIG_SYS_IMMR 0xFFF00000
177 178
178 /*----------------------------------------------------------------------- 179 /*-----------------------------------------------------------------------
179 * Definitions for initial stack pointer and data area (in DPRAM) 180 * Definitions for initial stack pointer and data area (in DPRAM)
180 */ 181 */
181 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 182 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
182 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 183 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
183 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 184 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
184 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 185 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
185 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 186 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
186 187
187 /*----------------------------------------------------------------------- 188 /*-----------------------------------------------------------------------
188 * Start addresses for the final memory configuration 189 * Start addresses for the final memory configuration
189 * (Set up by the startup code) 190 * (Set up by the startup code)
190 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 191 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
191 */ 192 */
192 #define CONFIG_SYS_SDRAM_BASE 0x00000000 193 #define CONFIG_SYS_SDRAM_BASE 0x00000000
193 #define CONFIG_SYS_FLASH_BASE 0x40000000 194 #define CONFIG_SYS_FLASH_BASE 0x40000000
194 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 195 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 196 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
196 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 197 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
197 198
198 /* 199 /*
199 * For booting Linux, the board info and command line data 200 * For booting Linux, the board info and command line data
200 * have to be in the first 8 MB of memory, since this is 201 * have to be in the first 8 MB of memory, since this is
201 * the maximum mapped by the Linux kernel during initialization. 202 * the maximum mapped by the Linux kernel during initialization.
202 */ 203 */
203 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 204 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
204 205
205 /*----------------------------------------------------------------------- 206 /*-----------------------------------------------------------------------
206 * FLASH organization 207 * FLASH organization
207 */ 208 */
208 209
209 /* use CFI flash driver */ 210 /* use CFI flash driver */
210 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 211 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
211 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 212 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
212 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 213 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
213 #define CONFIG_SYS_FLASH_EMPTY_INFO 214 #define CONFIG_SYS_FLASH_EMPTY_INFO
214 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 215 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
216 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 217 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
217 218
218 #define CONFIG_ENV_IS_IN_FLASH 1 219 #define CONFIG_ENV_IS_IN_FLASH 1
219 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 220 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
220 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 221 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
221 222
222 /* Address and size of Redundant Environment Sector */ 223 /* Address and size of Redundant Environment Sector */
223 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 224 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
224 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 225 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
225 226
226 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 227 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
227 228
228 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 229 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
229 230
230 /*----------------------------------------------------------------------- 231 /*-----------------------------------------------------------------------
231 * Dynamic MTD partition support 232 * Dynamic MTD partition support
232 */ 233 */
233 #define CONFIG_JFFS2_CMDLINE 234 #define CONFIG_JFFS2_CMDLINE
234 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 235 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
235 236
236 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 237 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
237 "128k(dtb)," \ 238 "128k(dtb)," \
238 "1664k(kernel)," \ 239 "1664k(kernel)," \
239 "2m(rootfs)," \ 240 "2m(rootfs)," \
240 "4m(data)" 241 "4m(data)"
241 242
242 /*----------------------------------------------------------------------- 243 /*-----------------------------------------------------------------------
243 * Hardware Information Block 244 * Hardware Information Block
244 */ 245 */
245 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 246 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
246 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 247 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
247 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 248 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
248 249
249 /*----------------------------------------------------------------------- 250 /*-----------------------------------------------------------------------
250 * Cache Configuration 251 * Cache Configuration
251 */ 252 */
252 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 253 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
253 #if defined(CONFIG_CMD_KGDB) 254 #if defined(CONFIG_CMD_KGDB)
254 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 255 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
255 #endif 256 #endif
256 257
257 /*----------------------------------------------------------------------- 258 /*-----------------------------------------------------------------------
258 * SYPCR - System Protection Control 11-9 259 * SYPCR - System Protection Control 11-9
259 * SYPCR can only be written once after reset! 260 * SYPCR can only be written once after reset!
260 *----------------------------------------------------------------------- 261 *-----------------------------------------------------------------------
261 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 262 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
262 */ 263 */
263 #if defined(CONFIG_WATCHDOG) 264 #if defined(CONFIG_WATCHDOG)
264 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 265 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
265 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 266 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
266 #else 267 #else
267 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 268 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
268 #endif 269 #endif
269 270
270 /*----------------------------------------------------------------------- 271 /*-----------------------------------------------------------------------
271 * SIUMCR - SIU Module Configuration 11-6 272 * SIUMCR - SIU Module Configuration 11-6
272 *----------------------------------------------------------------------- 273 *-----------------------------------------------------------------------
273 * PCMCIA config., multi-function pin tri-state 274 * PCMCIA config., multi-function pin tri-state
274 */ 275 */
275 #ifndef CONFIG_CAN_DRIVER 276 #ifndef CONFIG_CAN_DRIVER
276 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 277 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
277 #else /* we must activate GPL5 in the SIUMCR for CAN */ 278 #else /* we must activate GPL5 in the SIUMCR for CAN */
278 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 279 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
279 #endif /* CONFIG_CAN_DRIVER */ 280 #endif /* CONFIG_CAN_DRIVER */
280 281
281 /*----------------------------------------------------------------------- 282 /*-----------------------------------------------------------------------
282 * TBSCR - Time Base Status and Control 11-26 283 * TBSCR - Time Base Status and Control 11-26
283 *----------------------------------------------------------------------- 284 *-----------------------------------------------------------------------
284 * Clear Reference Interrupt Status, Timebase freezing enabled 285 * Clear Reference Interrupt Status, Timebase freezing enabled
285 */ 286 */
286 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 287 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
287 288
288 /*----------------------------------------------------------------------- 289 /*-----------------------------------------------------------------------
289 * RTCSC - Real-Time Clock Status and Control Register 11-27 290 * RTCSC - Real-Time Clock Status and Control Register 11-27
290 *----------------------------------------------------------------------- 291 *-----------------------------------------------------------------------
291 */ 292 */
292 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 293 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
293 294
294 /*----------------------------------------------------------------------- 295 /*-----------------------------------------------------------------------
295 * PISCR - Periodic Interrupt Status and Control 11-31 296 * PISCR - Periodic Interrupt Status and Control 11-31
296 *----------------------------------------------------------------------- 297 *-----------------------------------------------------------------------
297 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 298 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
298 */ 299 */
299 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 300 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
300 301
301 /*----------------------------------------------------------------------- 302 /*-----------------------------------------------------------------------
302 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 303 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
303 *----------------------------------------------------------------------- 304 *-----------------------------------------------------------------------
304 * Reset PLL lock status sticky bit, timer expired status bit and timer 305 * Reset PLL lock status sticky bit, timer expired status bit and timer
305 * interrupt status bit 306 * interrupt status bit
306 */ 307 */
307 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 308 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
308 309
309 /*----------------------------------------------------------------------- 310 /*-----------------------------------------------------------------------
310 * SCCR - System Clock and reset Control Register 15-27 311 * SCCR - System Clock and reset Control Register 15-27
311 *----------------------------------------------------------------------- 312 *-----------------------------------------------------------------------
312 * Set clock output, timebase and RTC source and divider, 313 * Set clock output, timebase and RTC source and divider,
313 * power management and some other internal clocks 314 * power management and some other internal clocks
314 */ 315 */
315 #define SCCR_MASK SCCR_EBDF11 316 #define SCCR_MASK SCCR_EBDF11
316 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 317 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
317 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 318 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
318 SCCR_DFALCD00) 319 SCCR_DFALCD00)
319 320
320 /*----------------------------------------------------------------------- 321 /*-----------------------------------------------------------------------
321 * PCMCIA stuff 322 * PCMCIA stuff
322 *----------------------------------------------------------------------- 323 *-----------------------------------------------------------------------
323 * 324 *
324 */ 325 */
325 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 326 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
326 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 327 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
327 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 328 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
328 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 329 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
329 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 330 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
330 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 331 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
331 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 332 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
332 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 333 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
333 334
334 /*----------------------------------------------------------------------- 335 /*-----------------------------------------------------------------------
335 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 336 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
336 *----------------------------------------------------------------------- 337 *-----------------------------------------------------------------------
337 */ 338 */
338 339
339 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 340 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
340 341
341 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 342 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
342 #undef CONFIG_IDE_LED /* LED for ide not supported */ 343 #undef CONFIG_IDE_LED /* LED for ide not supported */
343 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 344 #undef CONFIG_IDE_RESET /* reset for ide not supported */
344 345
345 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 346 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
346 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 347 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
347 348
348 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 349 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
349 350
350 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 351 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
351 352
352 /* Offset for data I/O */ 353 /* Offset for data I/O */
353 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 354 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
354 355
355 /* Offset for normal register accesses */ 356 /* Offset for normal register accesses */
356 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 357 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
357 358
358 /* Offset for alternate registers */ 359 /* Offset for alternate registers */
359 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 360 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
360 361
361 /*----------------------------------------------------------------------- 362 /*-----------------------------------------------------------------------
362 * 363 *
363 *----------------------------------------------------------------------- 364 *-----------------------------------------------------------------------
364 * 365 *
365 */ 366 */
366 #define CONFIG_SYS_DER 0 367 #define CONFIG_SYS_DER 0
367 368
368 /* 369 /*
369 * Init Memory Controller: 370 * Init Memory Controller:
370 * 371 *
371 * BR0/1 and OR0/1 (FLASH) 372 * BR0/1 and OR0/1 (FLASH)
372 */ 373 */
373 374
374 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 375 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
375 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 376 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
376 377
377 /* used to re-map FLASH both when starting from SRAM or FLASH: 378 /* used to re-map FLASH both when starting from SRAM or FLASH:
378 * restrict access enough to keep SRAM working (if any) 379 * restrict access enough to keep SRAM working (if any)
379 * but not too much to meddle with FLASH accesses 380 * but not too much to meddle with FLASH accesses
380 */ 381 */
381 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 382 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
382 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 383 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
383 384
384 /* 385 /*
385 * FLASH timing: 386 * FLASH timing:
386 */ 387 */
387 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 388 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
388 OR_SCY_3_CLK | OR_EHTR | OR_BI) 389 OR_SCY_3_CLK | OR_EHTR | OR_BI)
389 390
390 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 391 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
391 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 392 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
392 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 393 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
393 394
394 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 395 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
395 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 396 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
396 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 397 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
397 398
398 /* 399 /*
399 * BR2/3 and OR2/3 (SDRAM) 400 * BR2/3 and OR2/3 (SDRAM)
400 * 401 *
401 */ 402 */
402 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 403 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
403 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 404 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
404 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 405 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
405 406
406 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 407 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
407 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 408 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
408 409
409 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 410 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
410 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 411 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
411 412
412 #ifndef CONFIG_CAN_DRIVER 413 #ifndef CONFIG_CAN_DRIVER
413 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 414 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
414 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 415 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
415 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 416 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
416 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 417 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
417 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 418 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
418 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 419 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
419 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 420 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
420 BR_PS_8 | BR_MS_UPMB | BR_V ) 421 BR_PS_8 | BR_MS_UPMB | BR_V )
421 #endif /* CONFIG_CAN_DRIVER */ 422 #endif /* CONFIG_CAN_DRIVER */
422 423
423 /* 424 /*
424 * Memory Periodic Timer Prescaler 425 * Memory Periodic Timer Prescaler
425 * 426 *
426 * The Divider for PTA (refresh timer) configuration is based on an 427 * The Divider for PTA (refresh timer) configuration is based on an
427 * example SDRAM configuration (64 MBit, one bank). The adjustment to 428 * example SDRAM configuration (64 MBit, one bank). The adjustment to
428 * the number of chip selects (NCS) and the actually needed refresh 429 * the number of chip selects (NCS) and the actually needed refresh
429 * rate is done by setting MPTPR. 430 * rate is done by setting MPTPR.
430 * 431 *
431 * PTA is calculated from 432 * PTA is calculated from
432 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 433 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
433 * 434 *
434 * gclk CPU clock (not bus clock!) 435 * gclk CPU clock (not bus clock!)
435 * Trefresh Refresh cycle * 4 (four word bursts used) 436 * Trefresh Refresh cycle * 4 (four word bursts used)
436 * 437 *
437 * 4096 Rows from SDRAM example configuration 438 * 4096 Rows from SDRAM example configuration
438 * 1000 factor s -> ms 439 * 1000 factor s -> ms
439 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 440 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
440 * 4 Number of refresh cycles per period 441 * 4 Number of refresh cycles per period
441 * 64 Refresh cycle in ms per number of rows 442 * 64 Refresh cycle in ms per number of rows
442 * -------------------------------------------- 443 * --------------------------------------------
443 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 444 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
444 * 445 *
445 * 50 MHz => 50.000.000 / Divider = 98 446 * 50 MHz => 50.000.000 / Divider = 98
446 * 66 Mhz => 66.000.000 / Divider = 129 447 * 66 Mhz => 66.000.000 / Divider = 129
447 * 80 Mhz => 80.000.000 / Divider = 156 448 * 80 Mhz => 80.000.000 / Divider = 156
448 */ 449 */
449 450
450 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 451 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
451 #define CONFIG_SYS_MAMR_PTA 98 452 #define CONFIG_SYS_MAMR_PTA 98
452 453
453 /* 454 /*
454 * For 16 MBit, refresh rates could be 31.3 us 455 * For 16 MBit, refresh rates could be 31.3 us
455 * (= 64 ms / 2K = 125 / quad bursts). 456 * (= 64 ms / 2K = 125 / quad bursts).
456 * For a simpler initialization, 15.6 us is used instead. 457 * For a simpler initialization, 15.6 us is used instead.
457 * 458 *
458 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 459 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
459 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 460 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
460 */ 461 */
461 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 462 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
462 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 463 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
463 464
464 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 465 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
465 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 466 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
466 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 467 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
467 468
468 /* 469 /*
469 * MAMR settings for SDRAM 470 * MAMR settings for SDRAM
470 */ 471 */
471 472
472 /* 8 column SDRAM */ 473 /* 8 column SDRAM */
473 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 474 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
474 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 475 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 476 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
476 /* 9 column SDRAM */ 477 /* 9 column SDRAM */
477 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 478 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
478 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 479 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
479 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 480 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
480 481
481 482
482 /* 483 /*
483 * Internal Definitions 484 * Internal Definitions
484 * 485 *
485 * Boot Flags 486 * Boot Flags
486 */ 487 */
487 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 488 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
488 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 489 #define BOOTFLAG_WARM 0x02 /* Software reboot */
489 490
490 #endif /* __CONFIG_H */ 491 #endif /* __CONFIG_H */
491 492
include/configs/TQM823M.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37 #define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ 37 #define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
38 38
39 #ifdef CONFIG_LCD /* with LCD controller ? */ 39 #ifdef CONFIG_LCD /* with LCD controller ? */
40 /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ 40 /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
41 #endif 41 #endif
42 42
43 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 43 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44 #undef CONFIG_8xx_CONS_SMC2 44 #undef CONFIG_8xx_CONS_SMC2
45 #undef CONFIG_8xx_CONS_NONE 45 #undef CONFIG_8xx_CONS_NONE
46 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 46 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
47 47
48 #define CONFIG_BOOTCOUNT_LIMIT 48 #define CONFIG_BOOTCOUNT_LIMIT
49 49
50 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 50 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
51 51
52 #define CONFIG_BOARD_TYPES 1 /* support board types */ 52 #define CONFIG_BOARD_TYPES 1 /* support board types */
53 53
54 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 54 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
55 55
56 #undef CONFIG_BOOTARGS 56 #undef CONFIG_BOOTARGS
57 57
58 #define CONFIG_EXTRA_ENV_SETTINGS \ 58 #define CONFIG_EXTRA_ENV_SETTINGS \
59 "netdev=eth0\0" \ 59 "netdev=eth0\0" \
60 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 60 "nfsargs=setenv bootargs root=/dev/nfs rw " \
61 "nfsroot=${serverip}:${rootpath}\0" \ 61 "nfsroot=${serverip}:${rootpath}\0" \
62 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 62 "ramargs=setenv bootargs root=/dev/ram rw\0" \
63 "addip=setenv bootargs ${bootargs} " \ 63 "addip=setenv bootargs ${bootargs} " \
64 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 64 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
65 ":${hostname}:${netdev}:off panic=1\0" \ 65 ":${hostname}:${netdev}:off panic=1\0" \
66 "flash_nfs=run nfsargs addip;" \ 66 "flash_nfs=run nfsargs addip;" \
67 "bootm ${kernel_addr}\0" \ 67 "bootm ${kernel_addr}\0" \
68 "flash_self=run ramargs addip;" \ 68 "flash_self=run ramargs addip;" \
69 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 69 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
70 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 70 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
71 "rootpath=/opt/eldk/ppc_8xx\0" \ 71 "rootpath=/opt/eldk/ppc_8xx\0" \
72 "hostname=TQM823M\0" \ 72 "hostname=TQM823M\0" \
73 "bootfile=TQM823M/uImage\0" \ 73 "bootfile=TQM823M/uImage\0" \
74 "fdt_addr=40080000\0" \ 74 "fdt_addr=40080000\0" \
75 "kernel_addr=400A0000\0" \ 75 "kernel_addr=400A0000\0" \
76 "ramdisk_addr=40280000\0" \ 76 "ramdisk_addr=40280000\0" \
77 "u-boot=TQM823M/u-image.bin\0" \ 77 "u-boot=TQM823M/u-image.bin\0" \
78 "load=tftp 200000 ${u-boot}\0" \ 78 "load=tftp 200000 ${u-boot}\0" \
79 "update=prot off 40000000 +${filesize};" \ 79 "update=prot off 40000000 +${filesize};" \
80 "era 40000000 +${filesize};" \ 80 "era 40000000 +${filesize};" \
81 "cp.b 200000 40000000 ${filesize};" \ 81 "cp.b 200000 40000000 ${filesize};" \
82 "sete filesize;save\0" \ 82 "sete filesize;save\0" \
83 "" 83 ""
84 #define CONFIG_BOOTCOMMAND "run flash_self" 84 #define CONFIG_BOOTCOMMAND "run flash_self"
85 85
86 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 86 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
87 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 87 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
88 88
89 #undef CONFIG_WATCHDOG /* watchdog disabled */ 89 #undef CONFIG_WATCHDOG /* watchdog disabled */
90 90
91 #ifdef CONFIG_LCD 91 #ifdef CONFIG_LCD
92 # undef CONFIG_STATUS_LED /* disturbs display */ 92 # undef CONFIG_STATUS_LED /* disturbs display */
93 #else 93 #else
94 # define CONFIG_STATUS_LED 1 /* Status LED enabled */ 94 # define CONFIG_STATUS_LED 1 /* Status LED enabled */
95 #endif /* CONFIG_LCD */ 95 #endif /* CONFIG_LCD */
96 96
97 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 97 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
98 98
99 /* 99 /*
100 * BOOTP options 100 * BOOTP options
101 */ 101 */
102 #define CONFIG_BOOTP_SUBNETMASK 102 #define CONFIG_BOOTP_SUBNETMASK
103 #define CONFIG_BOOTP_GATEWAY 103 #define CONFIG_BOOTP_GATEWAY
104 #define CONFIG_BOOTP_HOSTNAME 104 #define CONFIG_BOOTP_HOSTNAME
105 #define CONFIG_BOOTP_BOOTPATH 105 #define CONFIG_BOOTP_BOOTPATH
106 #define CONFIG_BOOTP_BOOTFILESIZE 106 #define CONFIG_BOOTP_BOOTFILESIZE
107 107
108 108
109 #define CONFIG_MAC_PARTITION 109 #define CONFIG_MAC_PARTITION
110 #define CONFIG_DOS_PARTITION 110 #define CONFIG_DOS_PARTITION
111 111
112 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 112 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
113 113
114 114
115 /* 115 /*
116 * Command line configuration. 116 * Command line configuration.
117 */ 117 */
118 #include <config_cmd_default.h> 118 #include <config_cmd_default.h>
119 119
120 #define CONFIG_CMD_ASKENV 120 #define CONFIG_CMD_ASKENV
121 #define CONFIG_CMD_DATE 121 #define CONFIG_CMD_DATE
122 #define CONFIG_CMD_DHCP 122 #define CONFIG_CMD_DHCP
123 #define CONFIG_CMD_ELF 123 #define CONFIG_CMD_ELF
124 #define CONFIG_CMD_EXT2
124 #define CONFIG_CMD_IDE 125 #define CONFIG_CMD_IDE
125 #define CONFIG_CMD_JFFS2 126 #define CONFIG_CMD_JFFS2
126 #define CONFIG_CMD_NFS 127 #define CONFIG_CMD_NFS
127 #define CONFIG_CMD_SNTP 128 #define CONFIG_CMD_SNTP
128 129
129 130
130 #define CONFIG_NETCONSOLE 131 #define CONFIG_NETCONSOLE
131 132
132 133
133 /* 134 /*
134 * Miscellaneous configurable options 135 * Miscellaneous configurable options
135 */ 136 */
136 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 137 #define CONFIG_SYS_LONGHELP /* undef to save memory */
137 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 138 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
138 139
139 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 140 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
140 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 141 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
141 #ifdef CONFIG_SYS_HUSH_PARSER 142 #ifdef CONFIG_SYS_HUSH_PARSER
142 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 143 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
143 #endif 144 #endif
144 145
145 #if defined(CONFIG_CMD_KGDB) 146 #if defined(CONFIG_CMD_KGDB)
146 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 147 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
147 #else 148 #else
148 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 149 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
149 #endif 150 #endif
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 151 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
151 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 152 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
152 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 153 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
153 154
154 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 155 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
155 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 156 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
156 157
157 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 158 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
158 159
159 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 160 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
160 161
161 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 162 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
162 163
163 /* 164 /*
164 * Low Level Configuration Settings 165 * Low Level Configuration Settings
165 * (address mappings, register initial values, etc.) 166 * (address mappings, register initial values, etc.)
166 * You should know what you are doing if you make changes here. 167 * You should know what you are doing if you make changes here.
167 */ 168 */
168 /*----------------------------------------------------------------------- 169 /*-----------------------------------------------------------------------
169 * Internal Memory Mapped Register 170 * Internal Memory Mapped Register
170 */ 171 */
171 #define CONFIG_SYS_IMMR 0xFFF00000 172 #define CONFIG_SYS_IMMR 0xFFF00000
172 173
173 /*----------------------------------------------------------------------- 174 /*-----------------------------------------------------------------------
174 * Definitions for initial stack pointer and data area (in DPRAM) 175 * Definitions for initial stack pointer and data area (in DPRAM)
175 */ 176 */
176 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 177 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
177 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 178 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
178 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 179 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
179 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 180 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 181 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
181 182
182 /*----------------------------------------------------------------------- 183 /*-----------------------------------------------------------------------
183 * Start addresses for the final memory configuration 184 * Start addresses for the final memory configuration
184 * (Set up by the startup code) 185 * (Set up by the startup code)
185 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 186 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
186 */ 187 */
187 #define CONFIG_SYS_SDRAM_BASE 0x00000000 188 #define CONFIG_SYS_SDRAM_BASE 0x00000000
188 #define CONFIG_SYS_FLASH_BASE 0x40000000 189 #define CONFIG_SYS_FLASH_BASE 0x40000000
189 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 190 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
191 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 192 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
192 193
193 /* 194 /*
194 * For booting Linux, the board info and command line data 195 * For booting Linux, the board info and command line data
195 * have to be in the first 8 MB of memory, since this is 196 * have to be in the first 8 MB of memory, since this is
196 * the maximum mapped by the Linux kernel during initialization. 197 * the maximum mapped by the Linux kernel during initialization.
197 */ 198 */
198 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 199 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
199 200
200 /*----------------------------------------------------------------------- 201 /*-----------------------------------------------------------------------
201 * FLASH organization 202 * FLASH organization
202 */ 203 */
203 204
204 /* use CFI flash driver */ 205 /* use CFI flash driver */
205 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 206 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
206 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 207 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
207 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 208 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
208 #define CONFIG_SYS_FLASH_EMPTY_INFO 209 #define CONFIG_SYS_FLASH_EMPTY_INFO
209 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 210 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
210 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
211 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 212 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
212 213
213 #define CONFIG_ENV_IS_IN_FLASH 1 214 #define CONFIG_ENV_IS_IN_FLASH 1
214 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 215 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
215 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 216 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
216 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 217 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
217 218
218 /* Address and size of Redundant Environment Sector */ 219 /* Address and size of Redundant Environment Sector */
219 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 220 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
220 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 221 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
221 222
222 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 223 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
223 224
224 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 225 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
225 226
226 /*----------------------------------------------------------------------- 227 /*-----------------------------------------------------------------------
227 * Dynamic MTD partition support 228 * Dynamic MTD partition support
228 */ 229 */
229 #define CONFIG_JFFS2_CMDLINE 230 #define CONFIG_JFFS2_CMDLINE
230 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 231 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
231 232
232 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 233 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
233 "128k(dtb)," \ 234 "128k(dtb)," \
234 "1920k(kernel)," \ 235 "1920k(kernel)," \
235 "5632(rootfs)," \ 236 "5632(rootfs)," \
236 "4m(data)" 237 "4m(data)"
237 238
238 /*----------------------------------------------------------------------- 239 /*-----------------------------------------------------------------------
239 * Hardware Information Block 240 * Hardware Information Block
240 */ 241 */
241 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 242 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
242 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 243 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
243 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 244 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
244 245
245 /*----------------------------------------------------------------------- 246 /*-----------------------------------------------------------------------
246 * Cache Configuration 247 * Cache Configuration
247 */ 248 */
248 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 249 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
249 #if defined(CONFIG_CMD_KGDB) 250 #if defined(CONFIG_CMD_KGDB)
250 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 251 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
251 #endif 252 #endif
252 253
253 /*----------------------------------------------------------------------- 254 /*-----------------------------------------------------------------------
254 * SYPCR - System Protection Control 11-9 255 * SYPCR - System Protection Control 11-9
255 * SYPCR can only be written once after reset! 256 * SYPCR can only be written once after reset!
256 *----------------------------------------------------------------------- 257 *-----------------------------------------------------------------------
257 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 258 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
258 */ 259 */
259 #if defined(CONFIG_WATCHDOG) 260 #if defined(CONFIG_WATCHDOG)
260 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 261 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
261 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 262 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
262 #else 263 #else
263 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 264 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
264 #endif 265 #endif
265 266
266 /*----------------------------------------------------------------------- 267 /*-----------------------------------------------------------------------
267 * SIUMCR - SIU Module Configuration 11-6 268 * SIUMCR - SIU Module Configuration 11-6
268 *----------------------------------------------------------------------- 269 *-----------------------------------------------------------------------
269 * PCMCIA config., multi-function pin tri-state 270 * PCMCIA config., multi-function pin tri-state
270 */ 271 */
271 #ifndef CONFIG_CAN_DRIVER 272 #ifndef CONFIG_CAN_DRIVER
272 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 273 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
273 #else /* we must activate GPL5 in the SIUMCR for CAN */ 274 #else /* we must activate GPL5 in the SIUMCR for CAN */
274 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 275 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
275 #endif /* CONFIG_CAN_DRIVER */ 276 #endif /* CONFIG_CAN_DRIVER */
276 277
277 /*----------------------------------------------------------------------- 278 /*-----------------------------------------------------------------------
278 * TBSCR - Time Base Status and Control 11-26 279 * TBSCR - Time Base Status and Control 11-26
279 *----------------------------------------------------------------------- 280 *-----------------------------------------------------------------------
280 * Clear Reference Interrupt Status, Timebase freezing enabled 281 * Clear Reference Interrupt Status, Timebase freezing enabled
281 */ 282 */
282 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 283 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
283 284
284 /*----------------------------------------------------------------------- 285 /*-----------------------------------------------------------------------
285 * RTCSC - Real-Time Clock Status and Control Register 11-27 286 * RTCSC - Real-Time Clock Status and Control Register 11-27
286 *----------------------------------------------------------------------- 287 *-----------------------------------------------------------------------
287 */ 288 */
288 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 289 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
289 290
290 /*----------------------------------------------------------------------- 291 /*-----------------------------------------------------------------------
291 * PISCR - Periodic Interrupt Status and Control 11-31 292 * PISCR - Periodic Interrupt Status and Control 11-31
292 *----------------------------------------------------------------------- 293 *-----------------------------------------------------------------------
293 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 294 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
294 */ 295 */
295 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 296 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
296 297
297 /*----------------------------------------------------------------------- 298 /*-----------------------------------------------------------------------
298 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 299 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
299 *----------------------------------------------------------------------- 300 *-----------------------------------------------------------------------
300 * Reset PLL lock status sticky bit, timer expired status bit and timer 301 * Reset PLL lock status sticky bit, timer expired status bit and timer
301 * interrupt status bit 302 * interrupt status bit
302 */ 303 */
303 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 304 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
304 305
305 /*----------------------------------------------------------------------- 306 /*-----------------------------------------------------------------------
306 * SCCR - System Clock and reset Control Register 15-27 307 * SCCR - System Clock and reset Control Register 15-27
307 *----------------------------------------------------------------------- 308 *-----------------------------------------------------------------------
308 * Set clock output, timebase and RTC source and divider, 309 * Set clock output, timebase and RTC source and divider,
309 * power management and some other internal clocks 310 * power management and some other internal clocks
310 */ 311 */
311 #define SCCR_MASK SCCR_EBDF11 312 #define SCCR_MASK SCCR_EBDF11
312 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 313 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
313 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 314 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
314 SCCR_DFALCD00) 315 SCCR_DFALCD00)
315 316
316 /*----------------------------------------------------------------------- 317 /*-----------------------------------------------------------------------
317 * PCMCIA stuff 318 * PCMCIA stuff
318 *----------------------------------------------------------------------- 319 *-----------------------------------------------------------------------
319 * 320 *
320 */ 321 */
321 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 322 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
322 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 323 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
323 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 324 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
324 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 325 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
325 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 326 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
326 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 327 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
327 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 328 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
328 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 329 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
329 330
330 /*----------------------------------------------------------------------- 331 /*-----------------------------------------------------------------------
331 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 332 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
332 *----------------------------------------------------------------------- 333 *-----------------------------------------------------------------------
333 */ 334 */
334 335
335 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 336 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
336 337
337 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 338 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
338 #undef CONFIG_IDE_LED /* LED for ide not supported */ 339 #undef CONFIG_IDE_LED /* LED for ide not supported */
339 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 340 #undef CONFIG_IDE_RESET /* reset for ide not supported */
340 341
341 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 342 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
342 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 343 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
343 344
344 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 345 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
345 346
346 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 347 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
347 348
348 /* Offset for data I/O */ 349 /* Offset for data I/O */
349 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 350 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
350 351
351 /* Offset for normal register accesses */ 352 /* Offset for normal register accesses */
352 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 353 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
353 354
354 /* Offset for alternate registers */ 355 /* Offset for alternate registers */
355 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 356 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
356 357
357 /*----------------------------------------------------------------------- 358 /*-----------------------------------------------------------------------
358 * 359 *
359 *----------------------------------------------------------------------- 360 *-----------------------------------------------------------------------
360 * 361 *
361 */ 362 */
362 #define CONFIG_SYS_DER 0 363 #define CONFIG_SYS_DER 0
363 364
364 /* 365 /*
365 * Init Memory Controller: 366 * Init Memory Controller:
366 * 367 *
367 * BR0/1 and OR0/1 (FLASH) 368 * BR0/1 and OR0/1 (FLASH)
368 */ 369 */
369 370
370 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 371 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
371 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 372 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
372 373
373 /* used to re-map FLASH both when starting from SRAM or FLASH: 374 /* used to re-map FLASH both when starting from SRAM or FLASH:
374 * restrict access enough to keep SRAM working (if any) 375 * restrict access enough to keep SRAM working (if any)
375 * but not too much to meddle with FLASH accesses 376 * but not too much to meddle with FLASH accesses
376 */ 377 */
377 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 378 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
378 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 379 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
379 380
380 /* 381 /*
381 * FLASH timing: 382 * FLASH timing:
382 */ 383 */
383 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 384 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
384 OR_SCY_3_CLK | OR_EHTR | OR_BI) 385 OR_SCY_3_CLK | OR_EHTR | OR_BI)
385 386
386 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 387 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
387 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 388 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
388 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 389 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
389 390
390 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 391 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
391 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 392 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
392 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 393 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
393 394
394 /* 395 /*
395 * BR2/3 and OR2/3 (SDRAM) 396 * BR2/3 and OR2/3 (SDRAM)
396 * 397 *
397 */ 398 */
398 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 399 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
399 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 400 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
400 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 401 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
401 402
402 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 403 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
403 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 404 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
404 405
405 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 406 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
406 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 407 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
407 408
408 #ifndef CONFIG_CAN_DRIVER 409 #ifndef CONFIG_CAN_DRIVER
409 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 410 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
410 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 411 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
411 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 412 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
412 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 413 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
413 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 414 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
414 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 415 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
415 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 416 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
416 BR_PS_8 | BR_MS_UPMB | BR_V ) 417 BR_PS_8 | BR_MS_UPMB | BR_V )
417 #endif /* CONFIG_CAN_DRIVER */ 418 #endif /* CONFIG_CAN_DRIVER */
418 419
419 /* 420 /*
420 * Memory Periodic Timer Prescaler 421 * Memory Periodic Timer Prescaler
421 * 422 *
422 * The Divider for PTA (refresh timer) configuration is based on an 423 * The Divider for PTA (refresh timer) configuration is based on an
423 * example SDRAM configuration (64 MBit, one bank). The adjustment to 424 * example SDRAM configuration (64 MBit, one bank). The adjustment to
424 * the number of chip selects (NCS) and the actually needed refresh 425 * the number of chip selects (NCS) and the actually needed refresh
425 * rate is done by setting MPTPR. 426 * rate is done by setting MPTPR.
426 * 427 *
427 * PTA is calculated from 428 * PTA is calculated from
428 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 429 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
429 * 430 *
430 * gclk CPU clock (not bus clock!) 431 * gclk CPU clock (not bus clock!)
431 * Trefresh Refresh cycle * 4 (four word bursts used) 432 * Trefresh Refresh cycle * 4 (four word bursts used)
432 * 433 *
433 * 4096 Rows from SDRAM example configuration 434 * 4096 Rows from SDRAM example configuration
434 * 1000 factor s -> ms 435 * 1000 factor s -> ms
435 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 436 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
436 * 4 Number of refresh cycles per period 437 * 4 Number of refresh cycles per period
437 * 64 Refresh cycle in ms per number of rows 438 * 64 Refresh cycle in ms per number of rows
438 * -------------------------------------------- 439 * --------------------------------------------
439 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 440 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
440 * 441 *
441 * 50 MHz => 50.000.000 / Divider = 98 442 * 50 MHz => 50.000.000 / Divider = 98
442 * 66 Mhz => 66.000.000 / Divider = 129 443 * 66 Mhz => 66.000.000 / Divider = 129
443 * 80 Mhz => 80.000.000 / Divider = 156 444 * 80 Mhz => 80.000.000 / Divider = 156
444 */ 445 */
445 446
446 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 447 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
447 #define CONFIG_SYS_MAMR_PTA 98 448 #define CONFIG_SYS_MAMR_PTA 98
448 449
449 /* 450 /*
450 * For 16 MBit, refresh rates could be 31.3 us 451 * For 16 MBit, refresh rates could be 31.3 us
451 * (= 64 ms / 2K = 125 / quad bursts). 452 * (= 64 ms / 2K = 125 / quad bursts).
452 * For a simpler initialization, 15.6 us is used instead. 453 * For a simpler initialization, 15.6 us is used instead.
453 * 454 *
454 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 455 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
455 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 456 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
456 */ 457 */
457 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 458 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
458 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 459 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
459 460
460 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 461 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
461 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 462 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
462 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 463 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
463 464
464 /* 465 /*
465 * MAMR settings for SDRAM 466 * MAMR settings for SDRAM
466 */ 467 */
467 468
468 /* 8 column SDRAM */ 469 /* 8 column SDRAM */
469 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 470 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
470 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 471 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 472 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
472 /* 9 column SDRAM */ 473 /* 9 column SDRAM */
473 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 474 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
474 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 475 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 476 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
476 477
477 478
478 /* 479 /*
479 * Internal Definitions 480 * Internal Definitions
480 * 481 *
481 * Boot Flags 482 * Boot Flags
482 */ 483 */
483 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 484 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
484 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 485 #define BOOTFLAG_WARM 0x02 /* Software reboot */
485 486
486 #endif /* __CONFIG_H */ 487 #endif /* __CONFIG_H */
487 488
include/configs/TQM850L.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 36 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37 #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ 37 #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
38 38
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2 40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE 41 #undef CONFIG_8xx_CONS_NONE
42 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 42 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
43 43
44 #define CONFIG_BOOTCOUNT_LIMIT 44 #define CONFIG_BOOTCOUNT_LIMIT
45 45
46 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 46 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47 47
48 #define CONFIG_BOARD_TYPES 1 /* support board types */ 48 #define CONFIG_BOARD_TYPES 1 /* support board types */
49 49
50 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 50 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
51 51
52 #undef CONFIG_BOOTARGS 52 #undef CONFIG_BOOTARGS
53 53
54 #define CONFIG_EXTRA_ENV_SETTINGS \ 54 #define CONFIG_EXTRA_ENV_SETTINGS \
55 "netdev=eth0\0" \ 55 "netdev=eth0\0" \
56 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 56 "nfsargs=setenv bootargs root=/dev/nfs rw " \
57 "nfsroot=${serverip}:${rootpath}\0" \ 57 "nfsroot=${serverip}:${rootpath}\0" \
58 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 58 "ramargs=setenv bootargs root=/dev/ram rw\0" \
59 "addip=setenv bootargs ${bootargs} " \ 59 "addip=setenv bootargs ${bootargs} " \
60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
61 ":${hostname}:${netdev}:off panic=1\0" \ 61 ":${hostname}:${netdev}:off panic=1\0" \
62 "flash_nfs=run nfsargs addip;" \ 62 "flash_nfs=run nfsargs addip;" \
63 "bootm ${kernel_addr}\0" \ 63 "bootm ${kernel_addr}\0" \
64 "flash_self=run ramargs addip;" \ 64 "flash_self=run ramargs addip;" \
65 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 65 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
66 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 66 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
67 "rootpath=/opt/eldk/ppc_8xx\0" \ 67 "rootpath=/opt/eldk/ppc_8xx\0" \
68 "hostname=TQM850L\0" \ 68 "hostname=TQM850L\0" \
69 "bootfile=TQM850L/uImage\0" \ 69 "bootfile=TQM850L/uImage\0" \
70 "fdt_addr=40040000\0" \ 70 "fdt_addr=40040000\0" \
71 "kernel_addr=40060000\0" \ 71 "kernel_addr=40060000\0" \
72 "ramdisk_addr=40200000\0" \ 72 "ramdisk_addr=40200000\0" \
73 "u-boot=TQM850L/u-image.bin\0" \ 73 "u-boot=TQM850L/u-image.bin\0" \
74 "load=tftp 200000 ${u-boot}\0" \ 74 "load=tftp 200000 ${u-boot}\0" \
75 "update=prot off 40000000 +${filesize};" \ 75 "update=prot off 40000000 +${filesize};" \
76 "era 40000000 +${filesize};" \ 76 "era 40000000 +${filesize};" \
77 "cp.b 200000 40000000 ${filesize};" \ 77 "cp.b 200000 40000000 ${filesize};" \
78 "sete filesize;save\0" \ 78 "sete filesize;save\0" \
79 "" 79 ""
80 #define CONFIG_BOOTCOMMAND "run flash_self" 80 #define CONFIG_BOOTCOMMAND "run flash_self"
81 81
82 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 82 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
83 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 83 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
84 84
85 #undef CONFIG_WATCHDOG /* watchdog disabled */ 85 #undef CONFIG_WATCHDOG /* watchdog disabled */
86 86
87 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 87 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
88 88
89 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 89 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
90 90
91 /* 91 /*
92 * BOOTP options 92 * BOOTP options
93 */ 93 */
94 #define CONFIG_BOOTP_SUBNETMASK 94 #define CONFIG_BOOTP_SUBNETMASK
95 #define CONFIG_BOOTP_GATEWAY 95 #define CONFIG_BOOTP_GATEWAY
96 #define CONFIG_BOOTP_HOSTNAME 96 #define CONFIG_BOOTP_HOSTNAME
97 #define CONFIG_BOOTP_BOOTPATH 97 #define CONFIG_BOOTP_BOOTPATH
98 #define CONFIG_BOOTP_BOOTFILESIZE 98 #define CONFIG_BOOTP_BOOTFILESIZE
99 99
100 100
101 #define CONFIG_MAC_PARTITION 101 #define CONFIG_MAC_PARTITION
102 #define CONFIG_DOS_PARTITION 102 #define CONFIG_DOS_PARTITION
103 103
104 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 104 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
105 105
106 /* 106 /*
107 * Command line configuration. 107 * Command line configuration.
108 */ 108 */
109 #include <config_cmd_default.h> 109 #include <config_cmd_default.h>
110 110
111 #define CONFIG_CMD_ASKENV 111 #define CONFIG_CMD_ASKENV
112 #define CONFIG_CMD_DATE 112 #define CONFIG_CMD_DATE
113 #define CONFIG_CMD_DHCP 113 #define CONFIG_CMD_DHCP
114 #define CONFIG_CMD_ELF 114 #define CONFIG_CMD_ELF
115 #define CONFIG_CMD_EXT2
115 #define CONFIG_CMD_IDE 116 #define CONFIG_CMD_IDE
116 #define CONFIG_CMD_JFFS2 117 #define CONFIG_CMD_JFFS2
117 #define CONFIG_CMD_NFS 118 #define CONFIG_CMD_NFS
118 #define CONFIG_CMD_SNTP 119 #define CONFIG_CMD_SNTP
119 120
120 121
121 #define CONFIG_NETCONSOLE 122 #define CONFIG_NETCONSOLE
122 123
123 /* 124 /*
124 * Miscellaneous configurable options 125 * Miscellaneous configurable options
125 */ 126 */
126 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 127 #define CONFIG_SYS_LONGHELP /* undef to save memory */
127 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 128 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
128 129
129 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 130 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
130 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 131 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
131 #ifdef CONFIG_SYS_HUSH_PARSER 132 #ifdef CONFIG_SYS_HUSH_PARSER
132 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 133 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
133 #endif 134 #endif
134 135
135 #if defined(CONFIG_CMD_KGDB) 136 #if defined(CONFIG_CMD_KGDB)
136 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 137 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
137 #else 138 #else
138 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 139 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
139 #endif 140 #endif
140 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 141 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
141 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 142 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
142 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 143 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
143 144
144 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 145 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
145 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 146 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
146 147
147 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 148 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
148 149
149 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 150 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
150 151
151 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 152 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
152 153
153 /* 154 /*
154 * Low Level Configuration Settings 155 * Low Level Configuration Settings
155 * (address mappings, register initial values, etc.) 156 * (address mappings, register initial values, etc.)
156 * You should know what you are doing if you make changes here. 157 * You should know what you are doing if you make changes here.
157 */ 158 */
158 /*----------------------------------------------------------------------- 159 /*-----------------------------------------------------------------------
159 * Internal Memory Mapped Register 160 * Internal Memory Mapped Register
160 */ 161 */
161 #define CONFIG_SYS_IMMR 0xFFF00000 162 #define CONFIG_SYS_IMMR 0xFFF00000
162 163
163 /*----------------------------------------------------------------------- 164 /*-----------------------------------------------------------------------
164 * Definitions for initial stack pointer and data area (in DPRAM) 165 * Definitions for initial stack pointer and data area (in DPRAM)
165 */ 166 */
166 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 167 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
167 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 168 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
168 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 169 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
169 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
170 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
171 172
172 /*----------------------------------------------------------------------- 173 /*-----------------------------------------------------------------------
173 * Start addresses for the final memory configuration 174 * Start addresses for the final memory configuration
174 * (Set up by the startup code) 175 * (Set up by the startup code)
175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 176 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
176 */ 177 */
177 #define CONFIG_SYS_SDRAM_BASE 0x00000000 178 #define CONFIG_SYS_SDRAM_BASE 0x00000000
178 #define CONFIG_SYS_FLASH_BASE 0x40000000 179 #define CONFIG_SYS_FLASH_BASE 0x40000000
179 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 180 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
181 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 182 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
182 183
183 /* 184 /*
184 * For booting Linux, the board info and command line data 185 * For booting Linux, the board info and command line data
185 * have to be in the first 8 MB of memory, since this is 186 * have to be in the first 8 MB of memory, since this is
186 * the maximum mapped by the Linux kernel during initialization. 187 * the maximum mapped by the Linux kernel during initialization.
187 */ 188 */
188 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 189 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
189 190
190 /*----------------------------------------------------------------------- 191 /*-----------------------------------------------------------------------
191 * FLASH organization 192 * FLASH organization
192 */ 193 */
193 194
194 /* use CFI flash driver */ 195 /* use CFI flash driver */
195 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 196 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
196 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 197 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
197 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 198 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
198 #define CONFIG_SYS_FLASH_EMPTY_INFO 199 #define CONFIG_SYS_FLASH_EMPTY_INFO
199 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 200 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
200 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 201 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
201 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 202 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
202 203
203 #define CONFIG_ENV_IS_IN_FLASH 1 204 #define CONFIG_ENV_IS_IN_FLASH 1
204 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 205 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
205 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 206 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
206 207
207 /* Address and size of Redundant Environment Sector */ 208 /* Address and size of Redundant Environment Sector */
208 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 209 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
209 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 210 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
210 211
211 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 212 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
212 213
213 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 214 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
214 215
215 /*----------------------------------------------------------------------- 216 /*-----------------------------------------------------------------------
216 * Dynamic MTD partition support 217 * Dynamic MTD partition support
217 */ 218 */
218 #define CONFIG_JFFS2_CMDLINE 219 #define CONFIG_JFFS2_CMDLINE
219 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 220 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
220 221
221 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 222 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
222 "128k(dtb)," \ 223 "128k(dtb)," \
223 "1664k(kernel)," \ 224 "1664k(kernel)," \
224 "2m(rootfs)," \ 225 "2m(rootfs)," \
225 "4m(data)" 226 "4m(data)"
226 227
227 /*----------------------------------------------------------------------- 228 /*-----------------------------------------------------------------------
228 * Hardware Information Block 229 * Hardware Information Block
229 */ 230 */
230 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 231 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
231 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 232 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
232 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 233 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
233 234
234 /*----------------------------------------------------------------------- 235 /*-----------------------------------------------------------------------
235 * Cache Configuration 236 * Cache Configuration
236 */ 237 */
237 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 238 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
238 #if defined(CONFIG_CMD_KGDB) 239 #if defined(CONFIG_CMD_KGDB)
239 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 240 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
240 #endif 241 #endif
241 242
242 /*----------------------------------------------------------------------- 243 /*-----------------------------------------------------------------------
243 * SYPCR - System Protection Control 11-9 244 * SYPCR - System Protection Control 11-9
244 * SYPCR can only be written once after reset! 245 * SYPCR can only be written once after reset!
245 *----------------------------------------------------------------------- 246 *-----------------------------------------------------------------------
246 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 247 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
247 */ 248 */
248 #if defined(CONFIG_WATCHDOG) 249 #if defined(CONFIG_WATCHDOG)
249 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 250 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
250 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 251 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
251 #else 252 #else
252 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 253 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
253 #endif 254 #endif
254 255
255 /*----------------------------------------------------------------------- 256 /*-----------------------------------------------------------------------
256 * SIUMCR - SIU Module Configuration 11-6 257 * SIUMCR - SIU Module Configuration 11-6
257 *----------------------------------------------------------------------- 258 *-----------------------------------------------------------------------
258 * PCMCIA config., multi-function pin tri-state 259 * PCMCIA config., multi-function pin tri-state
259 */ 260 */
260 #ifndef CONFIG_CAN_DRIVER 261 #ifndef CONFIG_CAN_DRIVER
261 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 262 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
262 #else /* we must activate GPL5 in the SIUMCR for CAN */ 263 #else /* we must activate GPL5 in the SIUMCR for CAN */
263 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 264 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
264 #endif /* CONFIG_CAN_DRIVER */ 265 #endif /* CONFIG_CAN_DRIVER */
265 266
266 /*----------------------------------------------------------------------- 267 /*-----------------------------------------------------------------------
267 * TBSCR - Time Base Status and Control 11-26 268 * TBSCR - Time Base Status and Control 11-26
268 *----------------------------------------------------------------------- 269 *-----------------------------------------------------------------------
269 * Clear Reference Interrupt Status, Timebase freezing enabled 270 * Clear Reference Interrupt Status, Timebase freezing enabled
270 */ 271 */
271 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 272 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
272 273
273 /*----------------------------------------------------------------------- 274 /*-----------------------------------------------------------------------
274 * RTCSC - Real-Time Clock Status and Control Register 11-27 275 * RTCSC - Real-Time Clock Status and Control Register 11-27
275 *----------------------------------------------------------------------- 276 *-----------------------------------------------------------------------
276 */ 277 */
277 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 278 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
278 279
279 /*----------------------------------------------------------------------- 280 /*-----------------------------------------------------------------------
280 * PISCR - Periodic Interrupt Status and Control 11-31 281 * PISCR - Periodic Interrupt Status and Control 11-31
281 *----------------------------------------------------------------------- 282 *-----------------------------------------------------------------------
282 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 283 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
283 */ 284 */
284 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 285 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
285 286
286 /*----------------------------------------------------------------------- 287 /*-----------------------------------------------------------------------
287 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 288 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
288 *----------------------------------------------------------------------- 289 *-----------------------------------------------------------------------
289 * Reset PLL lock status sticky bit, timer expired status bit and timer 290 * Reset PLL lock status sticky bit, timer expired status bit and timer
290 * interrupt status bit 291 * interrupt status bit
291 */ 292 */
292 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 293 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
293 294
294 /*----------------------------------------------------------------------- 295 /*-----------------------------------------------------------------------
295 * SCCR - System Clock and reset Control Register 15-27 296 * SCCR - System Clock and reset Control Register 15-27
296 *----------------------------------------------------------------------- 297 *-----------------------------------------------------------------------
297 * Set clock output, timebase and RTC source and divider, 298 * Set clock output, timebase and RTC source and divider,
298 * power management and some other internal clocks 299 * power management and some other internal clocks
299 */ 300 */
300 #define SCCR_MASK SCCR_EBDF11 301 #define SCCR_MASK SCCR_EBDF11
301 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 302 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
302 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 303 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
303 SCCR_DFALCD00) 304 SCCR_DFALCD00)
304 305
305 /*----------------------------------------------------------------------- 306 /*-----------------------------------------------------------------------
306 * PCMCIA stuff 307 * PCMCIA stuff
307 *----------------------------------------------------------------------- 308 *-----------------------------------------------------------------------
308 * 309 *
309 */ 310 */
310 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 311 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
311 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 312 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
312 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 313 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
313 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 314 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
314 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 315 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
315 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 316 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
316 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 317 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
317 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 318 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
318 319
319 /*----------------------------------------------------------------------- 320 /*-----------------------------------------------------------------------
320 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 321 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
321 *----------------------------------------------------------------------- 322 *-----------------------------------------------------------------------
322 */ 323 */
323 324
324 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 325 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
325 326
326 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 327 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
327 #undef CONFIG_IDE_LED /* LED for ide not supported */ 328 #undef CONFIG_IDE_LED /* LED for ide not supported */
328 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 329 #undef CONFIG_IDE_RESET /* reset for ide not supported */
329 330
330 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 331 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
331 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 332 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
332 333
333 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 334 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
334 335
335 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 336 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
336 337
337 /* Offset for data I/O */ 338 /* Offset for data I/O */
338 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 339 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
339 340
340 /* Offset for normal register accesses */ 341 /* Offset for normal register accesses */
341 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 342 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
342 343
343 /* Offset for alternate registers */ 344 /* Offset for alternate registers */
344 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 345 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
345 346
346 /*----------------------------------------------------------------------- 347 /*-----------------------------------------------------------------------
347 * 348 *
348 *----------------------------------------------------------------------- 349 *-----------------------------------------------------------------------
349 * 350 *
350 */ 351 */
351 #define CONFIG_SYS_DER 0 352 #define CONFIG_SYS_DER 0
352 353
353 /* 354 /*
354 * Init Memory Controller: 355 * Init Memory Controller:
355 * 356 *
356 * BR0/1 and OR0/1 (FLASH) 357 * BR0/1 and OR0/1 (FLASH)
357 */ 358 */
358 359
359 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 360 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
360 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 361 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
361 362
362 /* used to re-map FLASH both when starting from SRAM or FLASH: 363 /* used to re-map FLASH both when starting from SRAM or FLASH:
363 * restrict access enough to keep SRAM working (if any) 364 * restrict access enough to keep SRAM working (if any)
364 * but not too much to meddle with FLASH accesses 365 * but not too much to meddle with FLASH accesses
365 */ 366 */
366 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 367 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
367 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 368 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
368 369
369 /* 370 /*
370 * FLASH timing: 371 * FLASH timing:
371 */ 372 */
372 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 373 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
373 OR_SCY_3_CLK | OR_EHTR | OR_BI) 374 OR_SCY_3_CLK | OR_EHTR | OR_BI)
374 375
375 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 376 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
376 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 377 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
377 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 378 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
378 379
379 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 380 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
380 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 381 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
381 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 382 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
382 383
383 /* 384 /*
384 * BR2/3 and OR2/3 (SDRAM) 385 * BR2/3 and OR2/3 (SDRAM)
385 * 386 *
386 */ 387 */
387 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 388 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
388 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 389 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
389 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 390 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
390 391
391 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 392 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
392 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 393 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
393 394
394 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 395 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
395 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 396 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
396 397
397 #ifndef CONFIG_CAN_DRIVER 398 #ifndef CONFIG_CAN_DRIVER
398 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 399 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
399 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 400 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
400 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 401 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
401 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 402 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
402 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 403 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
403 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 404 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
404 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 405 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
405 BR_PS_8 | BR_MS_UPMB | BR_V ) 406 BR_PS_8 | BR_MS_UPMB | BR_V )
406 #endif /* CONFIG_CAN_DRIVER */ 407 #endif /* CONFIG_CAN_DRIVER */
407 408
408 /* 409 /*
409 * Memory Periodic Timer Prescaler 410 * Memory Periodic Timer Prescaler
410 * 411 *
411 * The Divider for PTA (refresh timer) configuration is based on an 412 * The Divider for PTA (refresh timer) configuration is based on an
412 * example SDRAM configuration (64 MBit, one bank). The adjustment to 413 * example SDRAM configuration (64 MBit, one bank). The adjustment to
413 * the number of chip selects (NCS) and the actually needed refresh 414 * the number of chip selects (NCS) and the actually needed refresh
414 * rate is done by setting MPTPR. 415 * rate is done by setting MPTPR.
415 * 416 *
416 * PTA is calculated from 417 * PTA is calculated from
417 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 418 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
418 * 419 *
419 * gclk CPU clock (not bus clock!) 420 * gclk CPU clock (not bus clock!)
420 * Trefresh Refresh cycle * 4 (four word bursts used) 421 * Trefresh Refresh cycle * 4 (four word bursts used)
421 * 422 *
422 * 4096 Rows from SDRAM example configuration 423 * 4096 Rows from SDRAM example configuration
423 * 1000 factor s -> ms 424 * 1000 factor s -> ms
424 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 425 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
425 * 4 Number of refresh cycles per period 426 * 4 Number of refresh cycles per period
426 * 64 Refresh cycle in ms per number of rows 427 * 64 Refresh cycle in ms per number of rows
427 * -------------------------------------------- 428 * --------------------------------------------
428 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 429 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
429 * 430 *
430 * 50 MHz => 50.000.000 / Divider = 98 431 * 50 MHz => 50.000.000 / Divider = 98
431 * 66 Mhz => 66.000.000 / Divider = 129 432 * 66 Mhz => 66.000.000 / Divider = 129
432 * 80 Mhz => 80.000.000 / Divider = 156 433 * 80 Mhz => 80.000.000 / Divider = 156
433 */ 434 */
434 435
435 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 436 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
436 #define CONFIG_SYS_MAMR_PTA 98 437 #define CONFIG_SYS_MAMR_PTA 98
437 438
438 /* 439 /*
439 * For 16 MBit, refresh rates could be 31.3 us 440 * For 16 MBit, refresh rates could be 31.3 us
440 * (= 64 ms / 2K = 125 / quad bursts). 441 * (= 64 ms / 2K = 125 / quad bursts).
441 * For a simpler initialization, 15.6 us is used instead. 442 * For a simpler initialization, 15.6 us is used instead.
442 * 443 *
443 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 444 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
444 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 445 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
445 */ 446 */
446 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 447 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
447 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 448 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
448 449
449 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 450 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
450 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 451 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
451 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 452 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
452 453
453 /* 454 /*
454 * MAMR settings for SDRAM 455 * MAMR settings for SDRAM
455 */ 456 */
456 457
457 /* 8 column SDRAM */ 458 /* 8 column SDRAM */
458 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 459 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
459 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 460 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
460 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 461 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
461 /* 9 column SDRAM */ 462 /* 9 column SDRAM */
462 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 463 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
463 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 464 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
464 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 465 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
465 466
466 467
467 /* 468 /*
468 * Internal Definitions 469 * Internal Definitions
469 * 470 *
470 * Boot Flags 471 * Boot Flags
471 */ 472 */
472 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 473 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
473 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 474 #define BOOTFLAG_WARM 0x02 /* Software reboot */
474 475
475 #endif /* __CONFIG_H */ 476 #endif /* __CONFIG_H */
476 477
include/configs/TQM850M.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 36 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37 #define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ 37 #define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
38 38
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2 40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE 41 #undef CONFIG_8xx_CONS_NONE
42 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 42 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
43 43
44 #define CONFIG_BOOTCOUNT_LIMIT 44 #define CONFIG_BOOTCOUNT_LIMIT
45 45
46 #define CONFIG_BOARD_TYPES 1 /* support board types */ 46 #define CONFIG_BOARD_TYPES 1 /* support board types */
47 47
48 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 48 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
49 49
50 #undef CONFIG_BOOTARGS 50 #undef CONFIG_BOOTARGS
51 51
52 #define CONFIG_EXTRA_ENV_SETTINGS \ 52 #define CONFIG_EXTRA_ENV_SETTINGS \
53 "netdev=eth0\0" \ 53 "netdev=eth0\0" \
54 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 54 "nfsargs=setenv bootargs root=/dev/nfs rw " \
55 "nfsroot=${serverip}:${rootpath}\0" \ 55 "nfsroot=${serverip}:${rootpath}\0" \
56 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 56 "ramargs=setenv bootargs root=/dev/ram rw\0" \
57 "addip=setenv bootargs ${bootargs} " \ 57 "addip=setenv bootargs ${bootargs} " \
58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
59 ":${hostname}:${netdev}:off panic=1\0" \ 59 ":${hostname}:${netdev}:off panic=1\0" \
60 "flash_nfs=run nfsargs addip;" \ 60 "flash_nfs=run nfsargs addip;" \
61 "bootm ${kernel_addr}\0" \ 61 "bootm ${kernel_addr}\0" \
62 "flash_self=run ramargs addip;" \ 62 "flash_self=run ramargs addip;" \
63 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 63 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
64 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 64 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
65 "rootpath=/opt/eldk/ppc_8xx\0" \ 65 "rootpath=/opt/eldk/ppc_8xx\0" \
66 "hostname=TQM850M\0" \ 66 "hostname=TQM850M\0" \
67 "bootfile=TQM850M/uImage\0" \ 67 "bootfile=TQM850M/uImage\0" \
68 "fdt_addr=40080000\0" \ 68 "fdt_addr=40080000\0" \
69 "kernel_addr=400A0000\0" \ 69 "kernel_addr=400A0000\0" \
70 "ramdisk_addr=40280000\0" \ 70 "ramdisk_addr=40280000\0" \
71 "u-boot=TQM850M/u-image.bin\0" \ 71 "u-boot=TQM850M/u-image.bin\0" \
72 "load=tftp 200000 ${u-boot}\0" \ 72 "load=tftp 200000 ${u-boot}\0" \
73 "update=prot off 40000000 +${filesize};" \ 73 "update=prot off 40000000 +${filesize};" \
74 "era 40000000 +${filesize};" \ 74 "era 40000000 +${filesize};" \
75 "cp.b 200000 40000000 ${filesize};" \ 75 "cp.b 200000 40000000 ${filesize};" \
76 "sete filesize;save\0" \ 76 "sete filesize;save\0" \
77 "" 77 ""
78 #define CONFIG_BOOTCOMMAND "run flash_self" 78 #define CONFIG_BOOTCOMMAND "run flash_self"
79 79
80 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 80 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
81 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 81 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
82 82
83 #undef CONFIG_WATCHDOG /* watchdog disabled */ 83 #undef CONFIG_WATCHDOG /* watchdog disabled */
84 84
85 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 85 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
86 86
87 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 87 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
88 88
89 /* 89 /*
90 * BOOTP options 90 * BOOTP options
91 */ 91 */
92 #define CONFIG_BOOTP_SUBNETMASK 92 #define CONFIG_BOOTP_SUBNETMASK
93 #define CONFIG_BOOTP_GATEWAY 93 #define CONFIG_BOOTP_GATEWAY
94 #define CONFIG_BOOTP_HOSTNAME 94 #define CONFIG_BOOTP_HOSTNAME
95 #define CONFIG_BOOTP_BOOTPATH 95 #define CONFIG_BOOTP_BOOTPATH
96 #define CONFIG_BOOTP_BOOTFILESIZE 96 #define CONFIG_BOOTP_BOOTFILESIZE
97 97
98 98
99 #define CONFIG_MAC_PARTITION 99 #define CONFIG_MAC_PARTITION
100 #define CONFIG_DOS_PARTITION 100 #define CONFIG_DOS_PARTITION
101 101
102 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 102 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
103 103
104 /* 104 /*
105 * Command line configuration. 105 * Command line configuration.
106 */ 106 */
107 #include <config_cmd_default.h> 107 #include <config_cmd_default.h>
108 108
109 #define CONFIG_CMD_ASKENV 109 #define CONFIG_CMD_ASKENV
110 #define CONFIG_CMD_DATE 110 #define CONFIG_CMD_DATE
111 #define CONFIG_CMD_DHCP 111 #define CONFIG_CMD_DHCP
112 #define CONFIG_CMD_ELF 112 #define CONFIG_CMD_ELF
113 #define CONFIG_CMD_EXT2
113 #define CONFIG_CMD_IDE 114 #define CONFIG_CMD_IDE
114 #define CONFIG_CMD_JFFS2 115 #define CONFIG_CMD_JFFS2
115 #define CONFIG_CMD_NFS 116 #define CONFIG_CMD_NFS
116 #define CONFIG_CMD_SNTP 117 #define CONFIG_CMD_SNTP
117 118
118 119
119 #define CONFIG_NETCONSOLE 120 #define CONFIG_NETCONSOLE
120 121
121 122
122 /* 123 /*
123 * Miscellaneous configurable options 124 * Miscellaneous configurable options
124 */ 125 */
125 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 126 #define CONFIG_SYS_LONGHELP /* undef to save memory */
126 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 127 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
127 128
128 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 129 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
129 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 130 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
130 #ifdef CONFIG_SYS_HUSH_PARSER 131 #ifdef CONFIG_SYS_HUSH_PARSER
131 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 132 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
132 #endif 133 #endif
133 134
134 #if defined(CONFIG_CMD_KGDB) 135 #if defined(CONFIG_CMD_KGDB)
135 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 136 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
136 #else 137 #else
137 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 138 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
138 #endif 139 #endif
139 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 140 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
140 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 141 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
141 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 142 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
142 143
143 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 144 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
144 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 145 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
145 146
146 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 147 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
147 148
148 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 149 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
149 150
150 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 151 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
151 152
152 /* 153 /*
153 * Low Level Configuration Settings 154 * Low Level Configuration Settings
154 * (address mappings, register initial values, etc.) 155 * (address mappings, register initial values, etc.)
155 * You should know what you are doing if you make changes here. 156 * You should know what you are doing if you make changes here.
156 */ 157 */
157 /*----------------------------------------------------------------------- 158 /*-----------------------------------------------------------------------
158 * Internal Memory Mapped Register 159 * Internal Memory Mapped Register
159 */ 160 */
160 #define CONFIG_SYS_IMMR 0xFFF00000 161 #define CONFIG_SYS_IMMR 0xFFF00000
161 162
162 /*----------------------------------------------------------------------- 163 /*-----------------------------------------------------------------------
163 * Definitions for initial stack pointer and data area (in DPRAM) 164 * Definitions for initial stack pointer and data area (in DPRAM)
164 */ 165 */
165 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 166 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
166 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 167 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
167 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 168 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
168 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 169 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
169 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 170 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
170 171
171 /*----------------------------------------------------------------------- 172 /*-----------------------------------------------------------------------
172 * Start addresses for the final memory configuration 173 * Start addresses for the final memory configuration
173 * (Set up by the startup code) 174 * (Set up by the startup code)
174 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
175 */ 176 */
176 #define CONFIG_SYS_SDRAM_BASE 0x00000000 177 #define CONFIG_SYS_SDRAM_BASE 0x00000000
177 #define CONFIG_SYS_FLASH_BASE 0x40000000 178 #define CONFIG_SYS_FLASH_BASE 0x40000000
178 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 179 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
179 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
180 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 181 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
181 182
182 /* 183 /*
183 * For booting Linux, the board info and command line data 184 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is 185 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization. 186 * the maximum mapped by the Linux kernel during initialization.
186 */ 187 */
187 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 188 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
188 189
189 /*----------------------------------------------------------------------- 190 /*-----------------------------------------------------------------------
190 * FLASH organization 191 * FLASH organization
191 */ 192 */
192 193
193 /* use CFI flash driver */ 194 /* use CFI flash driver */
194 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 195 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
195 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 196 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
196 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 197 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
197 #define CONFIG_SYS_FLASH_EMPTY_INFO 198 #define CONFIG_SYS_FLASH_EMPTY_INFO
198 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 199 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
199 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 200 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
200 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 201 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
201 202
202 #define CONFIG_ENV_IS_IN_FLASH 1 203 #define CONFIG_ENV_IS_IN_FLASH 1
203 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 204 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
204 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 205 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
205 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 206 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
206 207
207 /* Address and size of Redundant Environment Sector */ 208 /* Address and size of Redundant Environment Sector */
208 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 209 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
209 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 210 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
210 211
211 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 212 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
212 213
213 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 214 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
214 215
215 /*----------------------------------------------------------------------- 216 /*-----------------------------------------------------------------------
216 * Dynamic MTD partition support 217 * Dynamic MTD partition support
217 */ 218 */
218 #define CONFIG_JFFS2_CMDLINE 219 #define CONFIG_JFFS2_CMDLINE
219 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 220 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
220 221
221 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 222 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
222 "128k(dtb)," \ 223 "128k(dtb)," \
223 "1920k(kernel)," \ 224 "1920k(kernel)," \
224 "5632(rootfs)," \ 225 "5632(rootfs)," \
225 "4m(data)" 226 "4m(data)"
226 227
227 /*----------------------------------------------------------------------- 228 /*-----------------------------------------------------------------------
228 * Hardware Information Block 229 * Hardware Information Block
229 */ 230 */
230 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 231 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
231 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 232 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
232 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 233 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
233 234
234 /*----------------------------------------------------------------------- 235 /*-----------------------------------------------------------------------
235 * Cache Configuration 236 * Cache Configuration
236 */ 237 */
237 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 238 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
238 #if defined(CONFIG_CMD_KGDB) 239 #if defined(CONFIG_CMD_KGDB)
239 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 240 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
240 #endif 241 #endif
241 242
242 /*----------------------------------------------------------------------- 243 /*-----------------------------------------------------------------------
243 * SYPCR - System Protection Control 11-9 244 * SYPCR - System Protection Control 11-9
244 * SYPCR can only be written once after reset! 245 * SYPCR can only be written once after reset!
245 *----------------------------------------------------------------------- 246 *-----------------------------------------------------------------------
246 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 247 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
247 */ 248 */
248 #if defined(CONFIG_WATCHDOG) 249 #if defined(CONFIG_WATCHDOG)
249 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 250 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
250 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 251 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
251 #else 252 #else
252 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 253 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
253 #endif 254 #endif
254 255
255 /*----------------------------------------------------------------------- 256 /*-----------------------------------------------------------------------
256 * SIUMCR - SIU Module Configuration 11-6 257 * SIUMCR - SIU Module Configuration 11-6
257 *----------------------------------------------------------------------- 258 *-----------------------------------------------------------------------
258 * PCMCIA config., multi-function pin tri-state 259 * PCMCIA config., multi-function pin tri-state
259 */ 260 */
260 #ifndef CONFIG_CAN_DRIVER 261 #ifndef CONFIG_CAN_DRIVER
261 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 262 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
262 #else /* we must activate GPL5 in the SIUMCR for CAN */ 263 #else /* we must activate GPL5 in the SIUMCR for CAN */
263 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 264 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
264 #endif /* CONFIG_CAN_DRIVER */ 265 #endif /* CONFIG_CAN_DRIVER */
265 266
266 /*----------------------------------------------------------------------- 267 /*-----------------------------------------------------------------------
267 * TBSCR - Time Base Status and Control 11-26 268 * TBSCR - Time Base Status and Control 11-26
268 *----------------------------------------------------------------------- 269 *-----------------------------------------------------------------------
269 * Clear Reference Interrupt Status, Timebase freezing enabled 270 * Clear Reference Interrupt Status, Timebase freezing enabled
270 */ 271 */
271 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 272 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
272 273
273 /*----------------------------------------------------------------------- 274 /*-----------------------------------------------------------------------
274 * RTCSC - Real-Time Clock Status and Control Register 11-27 275 * RTCSC - Real-Time Clock Status and Control Register 11-27
275 *----------------------------------------------------------------------- 276 *-----------------------------------------------------------------------
276 */ 277 */
277 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 278 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
278 279
279 /*----------------------------------------------------------------------- 280 /*-----------------------------------------------------------------------
280 * PISCR - Periodic Interrupt Status and Control 11-31 281 * PISCR - Periodic Interrupt Status and Control 11-31
281 *----------------------------------------------------------------------- 282 *-----------------------------------------------------------------------
282 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 283 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
283 */ 284 */
284 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 285 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
285 286
286 /*----------------------------------------------------------------------- 287 /*-----------------------------------------------------------------------
287 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 288 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
288 *----------------------------------------------------------------------- 289 *-----------------------------------------------------------------------
289 * Reset PLL lock status sticky bit, timer expired status bit and timer 290 * Reset PLL lock status sticky bit, timer expired status bit and timer
290 * interrupt status bit 291 * interrupt status bit
291 */ 292 */
292 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 293 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
293 294
294 /*----------------------------------------------------------------------- 295 /*-----------------------------------------------------------------------
295 * SCCR - System Clock and reset Control Register 15-27 296 * SCCR - System Clock and reset Control Register 15-27
296 *----------------------------------------------------------------------- 297 *-----------------------------------------------------------------------
297 * Set clock output, timebase and RTC source and divider, 298 * Set clock output, timebase and RTC source and divider,
298 * power management and some other internal clocks 299 * power management and some other internal clocks
299 */ 300 */
300 #define SCCR_MASK SCCR_EBDF11 301 #define SCCR_MASK SCCR_EBDF11
301 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 302 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
302 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 303 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
303 SCCR_DFALCD00) 304 SCCR_DFALCD00)
304 305
305 /*----------------------------------------------------------------------- 306 /*-----------------------------------------------------------------------
306 * PCMCIA stuff 307 * PCMCIA stuff
307 *----------------------------------------------------------------------- 308 *-----------------------------------------------------------------------
308 * 309 *
309 */ 310 */
310 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 311 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
311 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 312 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
312 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 313 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
313 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 314 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
314 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 315 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
315 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 316 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
316 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 317 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
317 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 318 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
318 319
319 /*----------------------------------------------------------------------- 320 /*-----------------------------------------------------------------------
320 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 321 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
321 *----------------------------------------------------------------------- 322 *-----------------------------------------------------------------------
322 */ 323 */
323 324
324 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 325 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
325 326
326 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 327 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
327 #undef CONFIG_IDE_LED /* LED for ide not supported */ 328 #undef CONFIG_IDE_LED /* LED for ide not supported */
328 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 329 #undef CONFIG_IDE_RESET /* reset for ide not supported */
329 330
330 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 331 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
331 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 332 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
332 333
333 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 334 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
334 335
335 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 336 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
336 337
337 /* Offset for data I/O */ 338 /* Offset for data I/O */
338 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 339 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
339 340
340 /* Offset for normal register accesses */ 341 /* Offset for normal register accesses */
341 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 342 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
342 343
343 /* Offset for alternate registers */ 344 /* Offset for alternate registers */
344 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 345 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
345 346
346 /*----------------------------------------------------------------------- 347 /*-----------------------------------------------------------------------
347 * 348 *
348 *----------------------------------------------------------------------- 349 *-----------------------------------------------------------------------
349 * 350 *
350 */ 351 */
351 #define CONFIG_SYS_DER 0 352 #define CONFIG_SYS_DER 0
352 353
353 /* 354 /*
354 * Init Memory Controller: 355 * Init Memory Controller:
355 * 356 *
356 * BR0/1 and OR0/1 (FLASH) 357 * BR0/1 and OR0/1 (FLASH)
357 */ 358 */
358 359
359 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 360 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
360 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 361 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
361 362
362 /* used to re-map FLASH both when starting from SRAM or FLASH: 363 /* used to re-map FLASH both when starting from SRAM or FLASH:
363 * restrict access enough to keep SRAM working (if any) 364 * restrict access enough to keep SRAM working (if any)
364 * but not too much to meddle with FLASH accesses 365 * but not too much to meddle with FLASH accesses
365 */ 366 */
366 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 367 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
367 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 368 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
368 369
369 /* 370 /*
370 * FLASH timing: 371 * FLASH timing:
371 */ 372 */
372 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 373 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
373 OR_SCY_3_CLK | OR_EHTR | OR_BI) 374 OR_SCY_3_CLK | OR_EHTR | OR_BI)
374 375
375 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 376 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
376 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 377 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
377 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 378 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
378 379
379 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 380 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
380 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 381 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
381 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 382 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
382 383
383 /* 384 /*
384 * BR2/3 and OR2/3 (SDRAM) 385 * BR2/3 and OR2/3 (SDRAM)
385 * 386 *
386 */ 387 */
387 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 388 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
388 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 389 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
389 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 390 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
390 391
391 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 392 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
392 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 393 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
393 394
394 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 395 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
395 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 396 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
396 397
397 #ifndef CONFIG_CAN_DRIVER 398 #ifndef CONFIG_CAN_DRIVER
398 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 399 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
399 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 400 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
400 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 401 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
401 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 402 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
402 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 403 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
403 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 404 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
404 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 405 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
405 BR_PS_8 | BR_MS_UPMB | BR_V ) 406 BR_PS_8 | BR_MS_UPMB | BR_V )
406 #endif /* CONFIG_CAN_DRIVER */ 407 #endif /* CONFIG_CAN_DRIVER */
407 408
408 /* 409 /*
409 * Memory Periodic Timer Prescaler 410 * Memory Periodic Timer Prescaler
410 * 411 *
411 * The Divider for PTA (refresh timer) configuration is based on an 412 * The Divider for PTA (refresh timer) configuration is based on an
412 * example SDRAM configuration (64 MBit, one bank). The adjustment to 413 * example SDRAM configuration (64 MBit, one bank). The adjustment to
413 * the number of chip selects (NCS) and the actually needed refresh 414 * the number of chip selects (NCS) and the actually needed refresh
414 * rate is done by setting MPTPR. 415 * rate is done by setting MPTPR.
415 * 416 *
416 * PTA is calculated from 417 * PTA is calculated from
417 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 418 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
418 * 419 *
419 * gclk CPU clock (not bus clock!) 420 * gclk CPU clock (not bus clock!)
420 * Trefresh Refresh cycle * 4 (four word bursts used) 421 * Trefresh Refresh cycle * 4 (four word bursts used)
421 * 422 *
422 * 4096 Rows from SDRAM example configuration 423 * 4096 Rows from SDRAM example configuration
423 * 1000 factor s -> ms 424 * 1000 factor s -> ms
424 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 425 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
425 * 4 Number of refresh cycles per period 426 * 4 Number of refresh cycles per period
426 * 64 Refresh cycle in ms per number of rows 427 * 64 Refresh cycle in ms per number of rows
427 * -------------------------------------------- 428 * --------------------------------------------
428 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 429 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
429 * 430 *
430 * 50 MHz => 50.000.000 / Divider = 98 431 * 50 MHz => 50.000.000 / Divider = 98
431 * 66 Mhz => 66.000.000 / Divider = 129 432 * 66 Mhz => 66.000.000 / Divider = 129
432 * 80 Mhz => 80.000.000 / Divider = 156 433 * 80 Mhz => 80.000.000 / Divider = 156
433 */ 434 */
434 435
435 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 436 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
436 #define CONFIG_SYS_MAMR_PTA 98 437 #define CONFIG_SYS_MAMR_PTA 98
437 438
438 /* 439 /*
439 * For 16 MBit, refresh rates could be 31.3 us 440 * For 16 MBit, refresh rates could be 31.3 us
440 * (= 64 ms / 2K = 125 / quad bursts). 441 * (= 64 ms / 2K = 125 / quad bursts).
441 * For a simpler initialization, 15.6 us is used instead. 442 * For a simpler initialization, 15.6 us is used instead.
442 * 443 *
443 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 444 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
444 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 445 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
445 */ 446 */
446 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 447 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
447 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 448 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
448 449
449 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 450 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
450 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 451 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
451 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 452 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
452 453
453 /* 454 /*
454 * MAMR settings for SDRAM 455 * MAMR settings for SDRAM
455 */ 456 */
456 457
457 /* 8 column SDRAM */ 458 /* 8 column SDRAM */
458 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 459 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
459 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 460 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
460 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 461 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
461 /* 9 column SDRAM */ 462 /* 9 column SDRAM */
462 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 463 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
463 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 464 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
464 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 465 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
465 466
466 467
467 /* 468 /*
468 * Internal Definitions 469 * Internal Definitions
469 * 470 *
470 * Boot Flags 471 * Boot Flags
471 */ 472 */
472 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 473 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
473 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 474 #define BOOTFLAG_WARM 0x02 /* Software reboot */
474 475
475 #endif /* __CONFIG_H */ 476 #endif /* __CONFIG_H */
476 477
include/configs/TQM855L.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ 36 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37 #define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ 37 #define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
38 38
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2 40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE 41 #undef CONFIG_8xx_CONS_NONE
42 42
43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44 44
45 #define CONFIG_BOOTCOUNT_LIMIT 45 #define CONFIG_BOOTCOUNT_LIMIT
46 46
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48 48
49 #define CONFIG_BOARD_TYPES 1 /* support board types */ 49 #define CONFIG_BOARD_TYPES 1 /* support board types */
50 50
51 #define CONFIG_PREBOOT "echo;" \ 51 #define CONFIG_PREBOOT "echo;" \
52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
53 "echo" 53 "echo"
54 54
55 #undef CONFIG_BOOTARGS 55 #undef CONFIG_BOOTARGS
56 56
57 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "netdev=eth0\0" \ 58 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
60 "nfsroot=${serverip}:${rootpath}\0" \ 60 "nfsroot=${serverip}:${rootpath}\0" \
61 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 61 "ramargs=setenv bootargs root=/dev/ram rw\0" \
62 "addip=setenv bootargs ${bootargs} " \ 62 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \ 64 ":${hostname}:${netdev}:off panic=1\0" \
65 "flash_nfs=run nfsargs addip;" \ 65 "flash_nfs=run nfsargs addip;" \
66 "bootm ${kernel_addr}\0" \ 66 "bootm ${kernel_addr}\0" \
67 "flash_self=run ramargs addip;" \ 67 "flash_self=run ramargs addip;" \
68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
70 "rootpath=/opt/eldk/ppc_8xx\0" \ 70 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "hostname=TQM855L\0" \ 71 "hostname=TQM855L\0" \
72 "bootfile=TQM855L/uImage\0" \ 72 "bootfile=TQM855L/uImage\0" \
73 "fdt_addr=40040000\0" \ 73 "fdt_addr=40040000\0" \
74 "kernel_addr=40060000\0" \ 74 "kernel_addr=40060000\0" \
75 "ramdisk_addr=40200000\0" \ 75 "ramdisk_addr=40200000\0" \
76 "u-boot=TQM855L/u-image.bin\0" \ 76 "u-boot=TQM855L/u-image.bin\0" \
77 "load=tftp 200000 ${u-boot}\0" \ 77 "load=tftp 200000 ${u-boot}\0" \
78 "update=prot off 40000000 +${filesize};" \ 78 "update=prot off 40000000 +${filesize};" \
79 "era 40000000 +${filesize};" \ 79 "era 40000000 +${filesize};" \
80 "cp.b 200000 40000000 ${filesize};" \ 80 "cp.b 200000 40000000 ${filesize};" \
81 "sete filesize;save\0" \ 81 "sete filesize;save\0" \
82 "" 82 ""
83 #define CONFIG_BOOTCOMMAND "run flash_self" 83 #define CONFIG_BOOTCOMMAND "run flash_self"
84 84
85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
86 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 86 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
87 87
88 #undef CONFIG_WATCHDOG /* watchdog disabled */ 88 #undef CONFIG_WATCHDOG /* watchdog disabled */
89 89
90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
91 91
92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93 93
94 /* 94 /*
95 * BOOTP options 95 * BOOTP options
96 */ 96 */
97 #define CONFIG_BOOTP_SUBNETMASK 97 #define CONFIG_BOOTP_SUBNETMASK
98 #define CONFIG_BOOTP_GATEWAY 98 #define CONFIG_BOOTP_GATEWAY
99 #define CONFIG_BOOTP_HOSTNAME 99 #define CONFIG_BOOTP_HOSTNAME
100 #define CONFIG_BOOTP_BOOTPATH 100 #define CONFIG_BOOTP_BOOTPATH
101 #define CONFIG_BOOTP_BOOTFILESIZE 101 #define CONFIG_BOOTP_BOOTFILESIZE
102 102
103 103
104 #define CONFIG_MAC_PARTITION 104 #define CONFIG_MAC_PARTITION
105 #define CONFIG_DOS_PARTITION 105 #define CONFIG_DOS_PARTITION
106 106
107 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 107 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
108 108
109 109
110 /* 110 /*
111 * Command line configuration. 111 * Command line configuration.
112 */ 112 */
113 #include <config_cmd_default.h> 113 #include <config_cmd_default.h>
114 114
115 #define CONFIG_CMD_ASKENV 115 #define CONFIG_CMD_ASKENV
116 #define CONFIG_CMD_DATE 116 #define CONFIG_CMD_DATE
117 #define CONFIG_CMD_DHCP 117 #define CONFIG_CMD_DHCP
118 #define CONFIG_CMD_ELF 118 #define CONFIG_CMD_ELF
119 #define CONFIG_CMD_EXT2
119 #define CONFIG_CMD_IDE 120 #define CONFIG_CMD_IDE
120 #define CONFIG_CMD_JFFS2 121 #define CONFIG_CMD_JFFS2
121 #define CONFIG_CMD_NFS 122 #define CONFIG_CMD_NFS
122 #define CONFIG_CMD_SNTP 123 #define CONFIG_CMD_SNTP
123 124
124 125
125 #define CONFIG_NETCONSOLE 126 #define CONFIG_NETCONSOLE
126 127
127 128
128 /* 129 /*
129 * Miscellaneous configurable options 130 * Miscellaneous configurable options
130 */ 131 */
131 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 132 #define CONFIG_SYS_LONGHELP /* undef to save memory */
132 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 133 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
133 134
134 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 135 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
135 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 136 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
136 #ifdef CONFIG_SYS_HUSH_PARSER 137 #ifdef CONFIG_SYS_HUSH_PARSER
137 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 138 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
138 #endif 139 #endif
139 140
140 #if defined(CONFIG_CMD_KGDB) 141 #if defined(CONFIG_CMD_KGDB)
141 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 142 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
142 #else 143 #else
143 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 144 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
144 #endif 145 #endif
145 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 146 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
146 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 147 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 148 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
148 149
149 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 150 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
150 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 151 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
151 152
152 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 153 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
153 154
154 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 155 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
155 156
156 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 157 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
157 158
158 /* 159 /*
159 * Low Level Configuration Settings 160 * Low Level Configuration Settings
160 * (address mappings, register initial values, etc.) 161 * (address mappings, register initial values, etc.)
161 * You should know what you are doing if you make changes here. 162 * You should know what you are doing if you make changes here.
162 */ 163 */
163 /*----------------------------------------------------------------------- 164 /*-----------------------------------------------------------------------
164 * Internal Memory Mapped Register 165 * Internal Memory Mapped Register
165 */ 166 */
166 #define CONFIG_SYS_IMMR 0xFFF00000 167 #define CONFIG_SYS_IMMR 0xFFF00000
167 168
168 /*----------------------------------------------------------------------- 169 /*-----------------------------------------------------------------------
169 * Definitions for initial stack pointer and data area (in DPRAM) 170 * Definitions for initial stack pointer and data area (in DPRAM)
170 */ 171 */
171 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 172 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
172 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 173 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
173 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 174 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
174 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 175 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
175 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 176 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
176 177
177 /*----------------------------------------------------------------------- 178 /*-----------------------------------------------------------------------
178 * Start addresses for the final memory configuration 179 * Start addresses for the final memory configuration
179 * (Set up by the startup code) 180 * (Set up by the startup code)
180 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 181 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
181 */ 182 */
182 #define CONFIG_SYS_SDRAM_BASE 0x00000000 183 #define CONFIG_SYS_SDRAM_BASE 0x00000000
183 #define CONFIG_SYS_FLASH_BASE 0x40000000 184 #define CONFIG_SYS_FLASH_BASE 0x40000000
184 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 185 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 186 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
186 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 187 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
187 188
188 /* 189 /*
189 * For booting Linux, the board info and command line data 190 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is 191 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization. 192 * the maximum mapped by the Linux kernel during initialization.
192 */ 193 */
193 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 194 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
194 195
195 /*----------------------------------------------------------------------- 196 /*-----------------------------------------------------------------------
196 * FLASH organization 197 * FLASH organization
197 */ 198 */
198 199
199 /* use CFI flash driver */ 200 /* use CFI flash driver */
200 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 201 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
201 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 202 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
202 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 203 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
203 #define CONFIG_SYS_FLASH_EMPTY_INFO 204 #define CONFIG_SYS_FLASH_EMPTY_INFO
204 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 205 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 206 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
206 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 207 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
207 208
208 #define CONFIG_ENV_IS_IN_FLASH 1 209 #define CONFIG_ENV_IS_IN_FLASH 1
209 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 210 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
210 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 211 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
211 212
212 /* Address and size of Redundant Environment Sector */ 213 /* Address and size of Redundant Environment Sector */
213 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 214 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
214 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 215 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
215 216
216 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 217 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
217 218
218 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 219 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
219 220
220 /*----------------------------------------------------------------------- 221 /*-----------------------------------------------------------------------
221 * Dynamic MTD partition support 222 * Dynamic MTD partition support
222 */ 223 */
223 #define CONFIG_JFFS2_CMDLINE 224 #define CONFIG_JFFS2_CMDLINE
224 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 225 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
225 226
226 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 227 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
227 "128k(dtb)," \ 228 "128k(dtb)," \
228 "1664k(kernel)," \ 229 "1664k(kernel)," \
229 "2m(rootfs)," \ 230 "2m(rootfs)," \
230 "4m(data)" 231 "4m(data)"
231 232
232 /*----------------------------------------------------------------------- 233 /*-----------------------------------------------------------------------
233 * Hardware Information Block 234 * Hardware Information Block
234 */ 235 */
235 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 236 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
236 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 237 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
237 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 238 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
238 239
239 /*----------------------------------------------------------------------- 240 /*-----------------------------------------------------------------------
240 * Cache Configuration 241 * Cache Configuration
241 */ 242 */
242 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 243 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
243 #if defined(CONFIG_CMD_KGDB) 244 #if defined(CONFIG_CMD_KGDB)
244 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 245 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
245 #endif 246 #endif
246 247
247 /*----------------------------------------------------------------------- 248 /*-----------------------------------------------------------------------
248 * SYPCR - System Protection Control 11-9 249 * SYPCR - System Protection Control 11-9
249 * SYPCR can only be written once after reset! 250 * SYPCR can only be written once after reset!
250 *----------------------------------------------------------------------- 251 *-----------------------------------------------------------------------
251 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 252 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
252 */ 253 */
253 #if defined(CONFIG_WATCHDOG) 254 #if defined(CONFIG_WATCHDOG)
254 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 255 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
255 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 256 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
256 #else 257 #else
257 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 258 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
258 #endif 259 #endif
259 260
260 /*----------------------------------------------------------------------- 261 /*-----------------------------------------------------------------------
261 * SIUMCR - SIU Module Configuration 11-6 262 * SIUMCR - SIU Module Configuration 11-6
262 *----------------------------------------------------------------------- 263 *-----------------------------------------------------------------------
263 * PCMCIA config., multi-function pin tri-state 264 * PCMCIA config., multi-function pin tri-state
264 */ 265 */
265 #ifndef CONFIG_CAN_DRIVER 266 #ifndef CONFIG_CAN_DRIVER
266 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 267 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
267 #else /* we must activate GPL5 in the SIUMCR for CAN */ 268 #else /* we must activate GPL5 in the SIUMCR for CAN */
268 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 269 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
269 #endif /* CONFIG_CAN_DRIVER */ 270 #endif /* CONFIG_CAN_DRIVER */
270 271
271 /*----------------------------------------------------------------------- 272 /*-----------------------------------------------------------------------
272 * TBSCR - Time Base Status and Control 11-26 273 * TBSCR - Time Base Status and Control 11-26
273 *----------------------------------------------------------------------- 274 *-----------------------------------------------------------------------
274 * Clear Reference Interrupt Status, Timebase freezing enabled 275 * Clear Reference Interrupt Status, Timebase freezing enabled
275 */ 276 */
276 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 277 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
277 278
278 /*----------------------------------------------------------------------- 279 /*-----------------------------------------------------------------------
279 * RTCSC - Real-Time Clock Status and Control Register 11-27 280 * RTCSC - Real-Time Clock Status and Control Register 11-27
280 *----------------------------------------------------------------------- 281 *-----------------------------------------------------------------------
281 */ 282 */
282 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 283 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
283 284
284 /*----------------------------------------------------------------------- 285 /*-----------------------------------------------------------------------
285 * PISCR - Periodic Interrupt Status and Control 11-31 286 * PISCR - Periodic Interrupt Status and Control 11-31
286 *----------------------------------------------------------------------- 287 *-----------------------------------------------------------------------
287 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 288 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
288 */ 289 */
289 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 290 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
290 291
291 /*----------------------------------------------------------------------- 292 /*-----------------------------------------------------------------------
292 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 293 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
293 *----------------------------------------------------------------------- 294 *-----------------------------------------------------------------------
294 * Reset PLL lock status sticky bit, timer expired status bit and timer 295 * Reset PLL lock status sticky bit, timer expired status bit and timer
295 * interrupt status bit 296 * interrupt status bit
296 */ 297 */
297 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 298 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
298 299
299 /*----------------------------------------------------------------------- 300 /*-----------------------------------------------------------------------
300 * SCCR - System Clock and reset Control Register 15-27 301 * SCCR - System Clock and reset Control Register 15-27
301 *----------------------------------------------------------------------- 302 *-----------------------------------------------------------------------
302 * Set clock output, timebase and RTC source and divider, 303 * Set clock output, timebase and RTC source and divider,
303 * power management and some other internal clocks 304 * power management and some other internal clocks
304 */ 305 */
305 #define SCCR_MASK SCCR_EBDF11 306 #define SCCR_MASK SCCR_EBDF11
306 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 307 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
307 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 308 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
308 SCCR_DFALCD00) 309 SCCR_DFALCD00)
309 310
310 /*----------------------------------------------------------------------- 311 /*-----------------------------------------------------------------------
311 * PCMCIA stuff 312 * PCMCIA stuff
312 *----------------------------------------------------------------------- 313 *-----------------------------------------------------------------------
313 * 314 *
314 */ 315 */
315 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 316 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
316 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 317 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
317 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 318 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
318 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 319 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
319 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 320 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
320 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 321 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
321 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 322 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
322 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 323 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
323 324
324 /*----------------------------------------------------------------------- 325 /*-----------------------------------------------------------------------
325 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 326 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
326 *----------------------------------------------------------------------- 327 *-----------------------------------------------------------------------
327 */ 328 */
328 329
329 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 330 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
330 331
331 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 332 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
332 #undef CONFIG_IDE_LED /* LED for ide not supported */ 333 #undef CONFIG_IDE_LED /* LED for ide not supported */
333 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 334 #undef CONFIG_IDE_RESET /* reset for ide not supported */
334 335
335 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 336 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
336 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 337 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
337 338
338 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 339 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
339 340
340 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 341 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
341 342
342 /* Offset for data I/O */ 343 /* Offset for data I/O */
343 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 344 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
344 345
345 /* Offset for normal register accesses */ 346 /* Offset for normal register accesses */
346 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 347 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
347 348
348 /* Offset for alternate registers */ 349 /* Offset for alternate registers */
349 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 350 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
350 351
351 /*----------------------------------------------------------------------- 352 /*-----------------------------------------------------------------------
352 * 353 *
353 *----------------------------------------------------------------------- 354 *-----------------------------------------------------------------------
354 * 355 *
355 */ 356 */
356 #define CONFIG_SYS_DER 0 357 #define CONFIG_SYS_DER 0
357 358
358 /* 359 /*
359 * Init Memory Controller: 360 * Init Memory Controller:
360 * 361 *
361 * BR0/1 and OR0/1 (FLASH) 362 * BR0/1 and OR0/1 (FLASH)
362 */ 363 */
363 364
364 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 365 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
365 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 366 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
366 367
367 /* used to re-map FLASH both when starting from SRAM or FLASH: 368 /* used to re-map FLASH both when starting from SRAM or FLASH:
368 * restrict access enough to keep SRAM working (if any) 369 * restrict access enough to keep SRAM working (if any)
369 * but not too much to meddle with FLASH accesses 370 * but not too much to meddle with FLASH accesses
370 */ 371 */
371 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 372 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
372 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 373 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
373 374
374 /* 375 /*
375 * FLASH timing: 376 * FLASH timing:
376 */ 377 */
377 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 378 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
378 OR_SCY_3_CLK | OR_EHTR | OR_BI) 379 OR_SCY_3_CLK | OR_EHTR | OR_BI)
379 380
380 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 381 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
381 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 382 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
382 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 383 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
383 384
384 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 385 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
385 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 386 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
386 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 387 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
387 388
388 /* 389 /*
389 * BR2/3 and OR2/3 (SDRAM) 390 * BR2/3 and OR2/3 (SDRAM)
390 * 391 *
391 */ 392 */
392 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 393 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
393 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 394 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
394 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 395 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
395 396
396 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 397 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
397 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 398 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
398 399
399 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 400 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
400 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 401 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
401 402
402 #ifndef CONFIG_CAN_DRIVER 403 #ifndef CONFIG_CAN_DRIVER
403 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 404 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
404 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 405 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
405 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 406 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
406 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 407 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
407 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 408 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
408 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 409 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
409 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 410 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
410 BR_PS_8 | BR_MS_UPMB | BR_V ) 411 BR_PS_8 | BR_MS_UPMB | BR_V )
411 #endif /* CONFIG_CAN_DRIVER */ 412 #endif /* CONFIG_CAN_DRIVER */
412 413
413 /* 414 /*
414 * Memory Periodic Timer Prescaler 415 * Memory Periodic Timer Prescaler
415 * 416 *
416 * The Divider for PTA (refresh timer) configuration is based on an 417 * The Divider for PTA (refresh timer) configuration is based on an
417 * example SDRAM configuration (64 MBit, one bank). The adjustment to 418 * example SDRAM configuration (64 MBit, one bank). The adjustment to
418 * the number of chip selects (NCS) and the actually needed refresh 419 * the number of chip selects (NCS) and the actually needed refresh
419 * rate is done by setting MPTPR. 420 * rate is done by setting MPTPR.
420 * 421 *
421 * PTA is calculated from 422 * PTA is calculated from
422 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 423 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
423 * 424 *
424 * gclk CPU clock (not bus clock!) 425 * gclk CPU clock (not bus clock!)
425 * Trefresh Refresh cycle * 4 (four word bursts used) 426 * Trefresh Refresh cycle * 4 (four word bursts used)
426 * 427 *
427 * 4096 Rows from SDRAM example configuration 428 * 4096 Rows from SDRAM example configuration
428 * 1000 factor s -> ms 429 * 1000 factor s -> ms
429 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 430 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
430 * 4 Number of refresh cycles per period 431 * 4 Number of refresh cycles per period
431 * 64 Refresh cycle in ms per number of rows 432 * 64 Refresh cycle in ms per number of rows
432 * -------------------------------------------- 433 * --------------------------------------------
433 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 434 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
434 * 435 *
435 * 50 MHz => 50.000.000 / Divider = 98 436 * 50 MHz => 50.000.000 / Divider = 98
436 * 66 Mhz => 66.000.000 / Divider = 129 437 * 66 Mhz => 66.000.000 / Divider = 129
437 * 80 Mhz => 80.000.000 / Divider = 156 438 * 80 Mhz => 80.000.000 / Divider = 156
438 */ 439 */
439 440
440 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 441 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
441 #define CONFIG_SYS_MAMR_PTA 98 442 #define CONFIG_SYS_MAMR_PTA 98
442 443
443 /* 444 /*
444 * For 16 MBit, refresh rates could be 31.3 us 445 * For 16 MBit, refresh rates could be 31.3 us
445 * (= 64 ms / 2K = 125 / quad bursts). 446 * (= 64 ms / 2K = 125 / quad bursts).
446 * For a simpler initialization, 15.6 us is used instead. 447 * For a simpler initialization, 15.6 us is used instead.
447 * 448 *
448 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 449 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
449 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 450 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
450 */ 451 */
451 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 452 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
452 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 453 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
453 454
454 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 455 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
455 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 456 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
456 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 457 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
457 458
458 /* 459 /*
459 * MAMR settings for SDRAM 460 * MAMR settings for SDRAM
460 */ 461 */
461 462
462 /* 8 column SDRAM */ 463 /* 8 column SDRAM */
463 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 464 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
464 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 465 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
465 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
466 /* 9 column SDRAM */ 467 /* 9 column SDRAM */
467 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 468 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
468 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 469 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
469 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
470 471
471 472
472 /* 473 /*
473 * Internal Definitions 474 * Internal Definitions
474 * 475 *
475 * Boot Flags 476 * Boot Flags
476 */ 477 */
477 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 478 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
478 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 479 #define BOOTFLAG_WARM 0x02 /* Software reboot */
479 480
480 #define CONFIG_SCC1_ENET 481 #define CONFIG_SCC1_ENET
481 #define CONFIG_FEC_ENET 482 #define CONFIG_FEC_ENET
482 #define CONFIG_ETHPRIME "SCC ETHERNET" 483 #define CONFIG_ETHPRIME "SCC ETHERNET"
483 484
484 #endif /* __CONFIG_H */ 485 #endif /* __CONFIG_H */
485 486
include/configs/TQM855M.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ 36 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37 #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ 37 #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
38 38
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2 40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE 41 #undef CONFIG_8xx_CONS_NONE
42 42
43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44 44
45 #define CONFIG_BOOTCOUNT_LIMIT 45 #define CONFIG_BOOTCOUNT_LIMIT
46 46
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48 48
49 #define CONFIG_BOARD_TYPES 1 /* support board types */ 49 #define CONFIG_BOARD_TYPES 1 /* support board types */
50 50
51 #define CONFIG_PREBOOT "echo;" \ 51 #define CONFIG_PREBOOT "echo;" \
52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
53 "echo" 53 "echo"
54 54
55 #undef CONFIG_BOOTARGS 55 #undef CONFIG_BOOTARGS
56 56
57 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "netdev=eth0\0" \ 58 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
60 "nfsroot=${serverip}:${rootpath}\0" \ 60 "nfsroot=${serverip}:${rootpath}\0" \
61 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 61 "ramargs=setenv bootargs root=/dev/ram rw\0" \
62 "addip=setenv bootargs ${bootargs} " \ 62 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \ 64 ":${hostname}:${netdev}:off panic=1\0" \
65 "flash_nfs=run nfsargs addip;" \ 65 "flash_nfs=run nfsargs addip;" \
66 "bootm ${kernel_addr}\0" \ 66 "bootm ${kernel_addr}\0" \
67 "flash_self=run ramargs addip;" \ 67 "flash_self=run ramargs addip;" \
68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
70 "rootpath=/opt/eldk/ppc_8xx\0" \ 70 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "hostname=TQM855M\0" \ 71 "hostname=TQM855M\0" \
72 "bootfile=TQM855M/uImage\0" \ 72 "bootfile=TQM855M/uImage\0" \
73 "fdt_addr=40080000\0" \ 73 "fdt_addr=40080000\0" \
74 "kernel_addr=400A0000\0" \ 74 "kernel_addr=400A0000\0" \
75 "ramdisk_addr=40280000\0" \ 75 "ramdisk_addr=40280000\0" \
76 "u-boot=TQM855M/u-image.bin\0" \ 76 "u-boot=TQM855M/u-image.bin\0" \
77 "load=tftp 200000 ${u-boot}\0" \ 77 "load=tftp 200000 ${u-boot}\0" \
78 "update=prot off 40000000 +${filesize};" \ 78 "update=prot off 40000000 +${filesize};" \
79 "era 40000000 +${filesize};" \ 79 "era 40000000 +${filesize};" \
80 "cp.b 200000 40000000 ${filesize};" \ 80 "cp.b 200000 40000000 ${filesize};" \
81 "sete filesize;save\0" \ 81 "sete filesize;save\0" \
82 "" 82 ""
83 #define CONFIG_BOOTCOMMAND "run flash_self" 83 #define CONFIG_BOOTCOMMAND "run flash_self"
84 84
85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
86 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 86 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
87 87
88 #undef CONFIG_WATCHDOG /* watchdog disabled */ 88 #undef CONFIG_WATCHDOG /* watchdog disabled */
89 89
90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
91 91
92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93 93
94 /* enable I2C and select the hardware/software driver */ 94 /* enable I2C and select the hardware/software driver */
95 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 95 #undef CONFIG_HARD_I2C /* I2C with hardware support */
96 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 96 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
97 97
98 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ 98 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
99 #define CONFIG_SYS_I2C_SLAVE 0xFE 99 #define CONFIG_SYS_I2C_SLAVE 0xFE
100 100
101 #ifdef CONFIG_SOFT_I2C 101 #ifdef CONFIG_SOFT_I2C
102 /* 102 /*
103 * Software (bit-bang) I2C driver configuration 103 * Software (bit-bang) I2C driver configuration
104 */ 104 */
105 #define PB_SCL 0x00000020 /* PB 26 */ 105 #define PB_SCL 0x00000020 /* PB 26 */
106 #define PB_SDA 0x00000010 /* PB 27 */ 106 #define PB_SDA 0x00000010 /* PB 27 */
107 107
108 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 108 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
109 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 109 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
110 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 110 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
111 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 111 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
112 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 112 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
113 else immr->im_cpm.cp_pbdat &= ~PB_SDA 113 else immr->im_cpm.cp_pbdat &= ~PB_SDA
114 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 114 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
115 else immr->im_cpm.cp_pbdat &= ~PB_SCL 115 else immr->im_cpm.cp_pbdat &= ~PB_SCL
116 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 116 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
117 #endif /* CONFIG_SOFT_I2C */ 117 #endif /* CONFIG_SOFT_I2C */
118 118
119 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ 119 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
120 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 120 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
121 #if 0 121 #if 0
122 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ 122 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
123 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 123 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
125 #endif 125 #endif
126 126
127 /* 127 /*
128 * BOOTP options 128 * BOOTP options
129 */ 129 */
130 #define CONFIG_BOOTP_SUBNETMASK 130 #define CONFIG_BOOTP_SUBNETMASK
131 #define CONFIG_BOOTP_GATEWAY 131 #define CONFIG_BOOTP_GATEWAY
132 #define CONFIG_BOOTP_HOSTNAME 132 #define CONFIG_BOOTP_HOSTNAME
133 #define CONFIG_BOOTP_BOOTPATH 133 #define CONFIG_BOOTP_BOOTPATH
134 #define CONFIG_BOOTP_BOOTFILESIZE 134 #define CONFIG_BOOTP_BOOTFILESIZE
135 135
136 136
137 #define CONFIG_MAC_PARTITION 137 #define CONFIG_MAC_PARTITION
138 #define CONFIG_DOS_PARTITION 138 #define CONFIG_DOS_PARTITION
139 139
140 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 140 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
141 141
142 142
143 /* 143 /*
144 * Command line configuration. 144 * Command line configuration.
145 */ 145 */
146 #include <config_cmd_default.h> 146 #include <config_cmd_default.h>
147 147
148 #define CONFIG_CMD_ASKENV 148 #define CONFIG_CMD_ASKENV
149 #define CONFIG_CMD_DATE 149 #define CONFIG_CMD_DATE
150 #define CONFIG_CMD_DHCP 150 #define CONFIG_CMD_DHCP
151 #define CONFIG_CMD_ELF 151 #define CONFIG_CMD_ELF
152 #define CONFIG_CMD_EXT2
152 #define CONFIG_CMD_EEPROM 153 #define CONFIG_CMD_EEPROM
153 #define CONFIG_CMD_IDE 154 #define CONFIG_CMD_IDE
154 #define CONFIG_CMD_JFFS2 155 #define CONFIG_CMD_JFFS2
155 #define CONFIG_CMD_NFS 156 #define CONFIG_CMD_NFS
156 #define CONFIG_CMD_SNTP 157 #define CONFIG_CMD_SNTP
157 158
158 159
159 #define CONFIG_NETCONSOLE 160 #define CONFIG_NETCONSOLE
160 161
161 162
162 /* 163 /*
163 * Miscellaneous configurable options 164 * Miscellaneous configurable options
164 */ 165 */
165 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 166 #define CONFIG_SYS_LONGHELP /* undef to save memory */
166 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 167 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
167 168
168 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 169 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
169 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 170 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
170 #ifdef CONFIG_SYS_HUSH_PARSER 171 #ifdef CONFIG_SYS_HUSH_PARSER
171 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 172 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
172 #endif 173 #endif
173 174
174 #if defined(CONFIG_CMD_KGDB) 175 #if defined(CONFIG_CMD_KGDB)
175 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 176 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
176 #else 177 #else
177 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 178 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
178 #endif 179 #endif
179 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 180 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
180 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 181 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
181 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 182 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
182 183
183 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 184 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
184 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 185 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
185 186
186 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 187 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
187 188
188 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 189 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
189 190
190 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 191 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
191 192
192 /* 193 /*
193 * Low Level Configuration Settings 194 * Low Level Configuration Settings
194 * (address mappings, register initial values, etc.) 195 * (address mappings, register initial values, etc.)
195 * You should know what you are doing if you make changes here. 196 * You should know what you are doing if you make changes here.
196 */ 197 */
197 /*----------------------------------------------------------------------- 198 /*-----------------------------------------------------------------------
198 * Internal Memory Mapped Register 199 * Internal Memory Mapped Register
199 */ 200 */
200 #define CONFIG_SYS_IMMR 0xFFF00000 201 #define CONFIG_SYS_IMMR 0xFFF00000
201 202
202 /*----------------------------------------------------------------------- 203 /*-----------------------------------------------------------------------
203 * Definitions for initial stack pointer and data area (in DPRAM) 204 * Definitions for initial stack pointer and data area (in DPRAM)
204 */ 205 */
205 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 206 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
206 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 207 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
207 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 208 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
208 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 209 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
209 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 210 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
210 211
211 /*----------------------------------------------------------------------- 212 /*-----------------------------------------------------------------------
212 * Start addresses for the final memory configuration 213 * Start addresses for the final memory configuration
213 * (Set up by the startup code) 214 * (Set up by the startup code)
214 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 215 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
215 */ 216 */
216 #define CONFIG_SYS_SDRAM_BASE 0x00000000 217 #define CONFIG_SYS_SDRAM_BASE 0x00000000
217 #define CONFIG_SYS_FLASH_BASE 0x40000000 218 #define CONFIG_SYS_FLASH_BASE 0x40000000
218 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 219 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
219 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
220 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 221 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
221 222
222 /* 223 /*
223 * For booting Linux, the board info and command line data 224 * For booting Linux, the board info and command line data
224 * have to be in the first 8 MB of memory, since this is 225 * have to be in the first 8 MB of memory, since this is
225 * the maximum mapped by the Linux kernel during initialization. 226 * the maximum mapped by the Linux kernel during initialization.
226 */ 227 */
227 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 228 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
228 229
229 /*----------------------------------------------------------------------- 230 /*-----------------------------------------------------------------------
230 * FLASH organization 231 * FLASH organization
231 */ 232 */
232 233
233 /* use CFI flash driver */ 234 /* use CFI flash driver */
234 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 235 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
235 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 236 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
236 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 237 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
237 #define CONFIG_SYS_FLASH_EMPTY_INFO 238 #define CONFIG_SYS_FLASH_EMPTY_INFO
238 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 239 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
239 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 240 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
240 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 241 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
241 242
242 #define CONFIG_ENV_IS_IN_FLASH 1 243 #define CONFIG_ENV_IS_IN_FLASH 1
243 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 244 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
244 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 245 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
245 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 246 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
246 247
247 /* Address and size of Redundant Environment Sector */ 248 /* Address and size of Redundant Environment Sector */
248 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 249 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
249 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 250 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
250 251
251 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 252 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
252 253
253 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 254 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
254 255
255 /*----------------------------------------------------------------------- 256 /*-----------------------------------------------------------------------
256 * Dynamic MTD partition support 257 * Dynamic MTD partition support
257 */ 258 */
258 #define CONFIG_JFFS2_CMDLINE 259 #define CONFIG_JFFS2_CMDLINE
259 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 260 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
260 261
261 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 262 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
262 "128k(dtb)," \ 263 "128k(dtb)," \
263 "1920k(kernel)," \ 264 "1920k(kernel)," \
264 "5632(rootfs)," \ 265 "5632(rootfs)," \
265 "4m(data)" 266 "4m(data)"
266 267
267 /*----------------------------------------------------------------------- 268 /*-----------------------------------------------------------------------
268 * Hardware Information Block 269 * Hardware Information Block
269 */ 270 */
270 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 271 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
271 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 272 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
272 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 273 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
273 274
274 /*----------------------------------------------------------------------- 275 /*-----------------------------------------------------------------------
275 * Cache Configuration 276 * Cache Configuration
276 */ 277 */
277 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 278 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
278 #if defined(CONFIG_CMD_KGDB) 279 #if defined(CONFIG_CMD_KGDB)
279 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 280 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
280 #endif 281 #endif
281 282
282 /*----------------------------------------------------------------------- 283 /*-----------------------------------------------------------------------
283 * SYPCR - System Protection Control 11-9 284 * SYPCR - System Protection Control 11-9
284 * SYPCR can only be written once after reset! 285 * SYPCR can only be written once after reset!
285 *----------------------------------------------------------------------- 286 *-----------------------------------------------------------------------
286 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 287 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
287 */ 288 */
288 #if defined(CONFIG_WATCHDOG) 289 #if defined(CONFIG_WATCHDOG)
289 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 290 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
290 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 291 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
291 #else 292 #else
292 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 293 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
293 #endif 294 #endif
294 295
295 /*----------------------------------------------------------------------- 296 /*-----------------------------------------------------------------------
296 * SIUMCR - SIU Module Configuration 11-6 297 * SIUMCR - SIU Module Configuration 11-6
297 *----------------------------------------------------------------------- 298 *-----------------------------------------------------------------------
298 * PCMCIA config., multi-function pin tri-state 299 * PCMCIA config., multi-function pin tri-state
299 */ 300 */
300 #ifndef CONFIG_CAN_DRIVER 301 #ifndef CONFIG_CAN_DRIVER
301 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 302 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
302 #else /* we must activate GPL5 in the SIUMCR for CAN */ 303 #else /* we must activate GPL5 in the SIUMCR for CAN */
303 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 304 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
304 #endif /* CONFIG_CAN_DRIVER */ 305 #endif /* CONFIG_CAN_DRIVER */
305 306
306 /*----------------------------------------------------------------------- 307 /*-----------------------------------------------------------------------
307 * TBSCR - Time Base Status and Control 11-26 308 * TBSCR - Time Base Status and Control 11-26
308 *----------------------------------------------------------------------- 309 *-----------------------------------------------------------------------
309 * Clear Reference Interrupt Status, Timebase freezing enabled 310 * Clear Reference Interrupt Status, Timebase freezing enabled
310 */ 311 */
311 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 312 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
312 313
313 /*----------------------------------------------------------------------- 314 /*-----------------------------------------------------------------------
314 * RTCSC - Real-Time Clock Status and Control Register 11-27 315 * RTCSC - Real-Time Clock Status and Control Register 11-27
315 *----------------------------------------------------------------------- 316 *-----------------------------------------------------------------------
316 */ 317 */
317 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 318 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
318 319
319 /*----------------------------------------------------------------------- 320 /*-----------------------------------------------------------------------
320 * PISCR - Periodic Interrupt Status and Control 11-31 321 * PISCR - Periodic Interrupt Status and Control 11-31
321 *----------------------------------------------------------------------- 322 *-----------------------------------------------------------------------
322 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 323 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
323 */ 324 */
324 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 325 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
325 326
326 /*----------------------------------------------------------------------- 327 /*-----------------------------------------------------------------------
327 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 328 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
328 *----------------------------------------------------------------------- 329 *-----------------------------------------------------------------------
329 * Reset PLL lock status sticky bit, timer expired status bit and timer 330 * Reset PLL lock status sticky bit, timer expired status bit and timer
330 * interrupt status bit 331 * interrupt status bit
331 */ 332 */
332 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 333 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
333 334
334 /*----------------------------------------------------------------------- 335 /*-----------------------------------------------------------------------
335 * SCCR - System Clock and reset Control Register 15-27 336 * SCCR - System Clock and reset Control Register 15-27
336 *----------------------------------------------------------------------- 337 *-----------------------------------------------------------------------
337 * Set clock output, timebase and RTC source and divider, 338 * Set clock output, timebase and RTC source and divider,
338 * power management and some other internal clocks 339 * power management and some other internal clocks
339 */ 340 */
340 #define SCCR_MASK SCCR_EBDF11 341 #define SCCR_MASK SCCR_EBDF11
341 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 342 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
342 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 343 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
343 SCCR_DFALCD00) 344 SCCR_DFALCD00)
344 345
345 /*----------------------------------------------------------------------- 346 /*-----------------------------------------------------------------------
346 * PCMCIA stuff 347 * PCMCIA stuff
347 *----------------------------------------------------------------------- 348 *-----------------------------------------------------------------------
348 * 349 *
349 */ 350 */
350 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 351 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
351 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 352 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
352 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 353 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
353 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 354 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
354 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 355 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
355 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 356 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
356 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 357 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
357 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 358 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
358 359
359 /*----------------------------------------------------------------------- 360 /*-----------------------------------------------------------------------
360 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 361 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
361 *----------------------------------------------------------------------- 362 *-----------------------------------------------------------------------
362 */ 363 */
363 364
364 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 365 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
365 366
366 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 367 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
367 #undef CONFIG_IDE_LED /* LED for ide not supported */ 368 #undef CONFIG_IDE_LED /* LED for ide not supported */
368 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 369 #undef CONFIG_IDE_RESET /* reset for ide not supported */
369 370
370 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 371 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
371 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 372 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
372 373
373 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 374 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
374 375
375 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 376 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
376 377
377 /* Offset for data I/O */ 378 /* Offset for data I/O */
378 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 379 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
379 380
380 /* Offset for normal register accesses */ 381 /* Offset for normal register accesses */
381 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 382 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
382 383
383 /* Offset for alternate registers */ 384 /* Offset for alternate registers */
384 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 385 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
385 386
386 /*----------------------------------------------------------------------- 387 /*-----------------------------------------------------------------------
387 * 388 *
388 *----------------------------------------------------------------------- 389 *-----------------------------------------------------------------------
389 * 390 *
390 */ 391 */
391 #define CONFIG_SYS_DER 0 392 #define CONFIG_SYS_DER 0
392 393
393 /* 394 /*
394 * Init Memory Controller: 395 * Init Memory Controller:
395 * 396 *
396 * BR0/1 and OR0/1 (FLASH) 397 * BR0/1 and OR0/1 (FLASH)
397 */ 398 */
398 399
399 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 400 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
400 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 401 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
401 402
402 /* used to re-map FLASH both when starting from SRAM or FLASH: 403 /* used to re-map FLASH both when starting from SRAM or FLASH:
403 * restrict access enough to keep SRAM working (if any) 404 * restrict access enough to keep SRAM working (if any)
404 * but not too much to meddle with FLASH accesses 405 * but not too much to meddle with FLASH accesses
405 */ 406 */
406 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 407 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
407 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 408 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
408 409
409 /* 410 /*
410 * FLASH timing: 411 * FLASH timing:
411 */ 412 */
412 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 413 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
413 OR_SCY_3_CLK | OR_EHTR | OR_BI) 414 OR_SCY_3_CLK | OR_EHTR | OR_BI)
414 415
415 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 416 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
416 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 417 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
417 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 418 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
418 419
419 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 420 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
420 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 421 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
421 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 422 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
422 423
423 /* 424 /*
424 * BR2/3 and OR2/3 (SDRAM) 425 * BR2/3 and OR2/3 (SDRAM)
425 * 426 *
426 */ 427 */
427 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 428 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
428 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 429 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
429 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 430 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
430 431
431 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 432 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
432 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 433 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
433 434
434 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 435 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
435 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 436 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
436 437
437 #ifndef CONFIG_CAN_DRIVER 438 #ifndef CONFIG_CAN_DRIVER
438 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 439 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
439 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 440 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
440 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 441 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
441 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 442 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
442 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 443 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
443 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 444 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
444 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 445 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
445 BR_PS_8 | BR_MS_UPMB | BR_V ) 446 BR_PS_8 | BR_MS_UPMB | BR_V )
446 #endif /* CONFIG_CAN_DRIVER */ 447 #endif /* CONFIG_CAN_DRIVER */
447 448
448 /* 449 /*
449 * Memory Periodic Timer Prescaler 450 * Memory Periodic Timer Prescaler
450 * 451 *
451 * The Divider for PTA (refresh timer) configuration is based on an 452 * The Divider for PTA (refresh timer) configuration is based on an
452 * example SDRAM configuration (64 MBit, one bank). The adjustment to 453 * example SDRAM configuration (64 MBit, one bank). The adjustment to
453 * the number of chip selects (NCS) and the actually needed refresh 454 * the number of chip selects (NCS) and the actually needed refresh
454 * rate is done by setting MPTPR. 455 * rate is done by setting MPTPR.
455 * 456 *
456 * PTA is calculated from 457 * PTA is calculated from
457 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 458 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
458 * 459 *
459 * gclk CPU clock (not bus clock!) 460 * gclk CPU clock (not bus clock!)
460 * Trefresh Refresh cycle * 4 (four word bursts used) 461 * Trefresh Refresh cycle * 4 (four word bursts used)
461 * 462 *
462 * 4096 Rows from SDRAM example configuration 463 * 4096 Rows from SDRAM example configuration
463 * 1000 factor s -> ms 464 * 1000 factor s -> ms
464 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 465 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
465 * 4 Number of refresh cycles per period 466 * 4 Number of refresh cycles per period
466 * 64 Refresh cycle in ms per number of rows 467 * 64 Refresh cycle in ms per number of rows
467 * -------------------------------------------- 468 * --------------------------------------------
468 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 469 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
469 * 470 *
470 * 50 MHz => 50.000.000 / Divider = 98 471 * 50 MHz => 50.000.000 / Divider = 98
471 * 66 Mhz => 66.000.000 / Divider = 129 472 * 66 Mhz => 66.000.000 / Divider = 129
472 * 80 Mhz => 80.000.000 / Divider = 156 473 * 80 Mhz => 80.000.000 / Divider = 156
473 */ 474 */
474 475
475 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 476 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
476 #define CONFIG_SYS_MAMR_PTA 98 477 #define CONFIG_SYS_MAMR_PTA 98
477 478
478 /* 479 /*
479 * For 16 MBit, refresh rates could be 31.3 us 480 * For 16 MBit, refresh rates could be 31.3 us
480 * (= 64 ms / 2K = 125 / quad bursts). 481 * (= 64 ms / 2K = 125 / quad bursts).
481 * For a simpler initialization, 15.6 us is used instead. 482 * For a simpler initialization, 15.6 us is used instead.
482 * 483 *
483 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 484 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
484 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 485 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
485 */ 486 */
486 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 487 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
487 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 488 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
488 489
489 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 490 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
490 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 491 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
491 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 492 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
492 493
493 /* 494 /*
494 * MAMR settings for SDRAM 495 * MAMR settings for SDRAM
495 */ 496 */
496 497
497 /* 8 column SDRAM */ 498 /* 8 column SDRAM */
498 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 499 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
499 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 500 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
500 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 501 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
501 /* 9 column SDRAM */ 502 /* 9 column SDRAM */
502 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 503 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
503 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 504 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
504 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 505 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
505 506
506 507
507 /* 508 /*
508 * Internal Definitions 509 * Internal Definitions
509 * 510 *
510 * Boot Flags 511 * Boot Flags
511 */ 512 */
512 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 513 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
513 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 514 #define BOOTFLAG_WARM 0x02 /* Software reboot */
514 515
515 #define CONFIG_SCC1_ENET 516 #define CONFIG_SCC1_ENET
516 #define CONFIG_FEC_ENET 517 #define CONFIG_FEC_ENET
517 #define CONFIG_ETHPRIME "SCC ETHERNET" 518 #define CONFIG_ETHPRIME "SCC ETHERNET"
518 519
519 #endif /* __CONFIG_H */ 520 #endif /* __CONFIG_H */
520 521
include/configs/TQM860L.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37 #define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ 37 #define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
38 38
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2 40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE 41 #undef CONFIG_8xx_CONS_NONE
42 42
43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44 44
45 #define CONFIG_BOOTCOUNT_LIMIT 45 #define CONFIG_BOOTCOUNT_LIMIT
46 46
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48 48
49 #define CONFIG_BOARD_TYPES 1 /* support board types */ 49 #define CONFIG_BOARD_TYPES 1 /* support board types */
50 50
51 #define CONFIG_PREBOOT "echo;" \ 51 #define CONFIG_PREBOOT "echo;" \
52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
53 "echo" 53 "echo"
54 54
55 #undef CONFIG_BOOTARGS 55 #undef CONFIG_BOOTARGS
56 56
57 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "netdev=eth0\0" \ 58 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
60 "nfsroot=${serverip}:${rootpath}\0" \ 60 "nfsroot=${serverip}:${rootpath}\0" \
61 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 61 "ramargs=setenv bootargs root=/dev/ram rw\0" \
62 "addip=setenv bootargs ${bootargs} " \ 62 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \ 64 ":${hostname}:${netdev}:off panic=1\0" \
65 "flash_nfs=run nfsargs addip;" \ 65 "flash_nfs=run nfsargs addip;" \
66 "bootm ${kernel_addr}\0" \ 66 "bootm ${kernel_addr}\0" \
67 "flash_self=run ramargs addip;" \ 67 "flash_self=run ramargs addip;" \
68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
70 "rootpath=/opt/eldk/ppc_8xx\0" \ 70 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "hostname=TQM860L\0" \ 71 "hostname=TQM860L\0" \
72 "bootfile=TQM860L/uImage\0" \ 72 "bootfile=TQM860L/uImage\0" \
73 "fdt_addr=40040000\0" \ 73 "fdt_addr=40040000\0" \
74 "kernel_addr=40060000\0" \ 74 "kernel_addr=40060000\0" \
75 "ramdisk_addr=40200000\0" \ 75 "ramdisk_addr=40200000\0" \
76 "u-boot=TQM860L/u-image.bin\0" \ 76 "u-boot=TQM860L/u-image.bin\0" \
77 "load=tftp 200000 ${u-boot}\0" \ 77 "load=tftp 200000 ${u-boot}\0" \
78 "update=prot off 40000000 +${filesize};" \ 78 "update=prot off 40000000 +${filesize};" \
79 "era 40000000 +${filesize};" \ 79 "era 40000000 +${filesize};" \
80 "cp.b 200000 40000000 ${filesize};" \ 80 "cp.b 200000 40000000 ${filesize};" \
81 "sete filesize;save\0" \ 81 "sete filesize;save\0" \
82 "" 82 ""
83 #define CONFIG_BOOTCOMMAND "run flash_self" 83 #define CONFIG_BOOTCOMMAND "run flash_self"
84 84
85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
86 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 86 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
87 87
88 #undef CONFIG_WATCHDOG /* watchdog disabled */ 88 #undef CONFIG_WATCHDOG /* watchdog disabled */
89 89
90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
91 91
92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93 93
94 /* 94 /*
95 * BOOTP options 95 * BOOTP options
96 */ 96 */
97 #define CONFIG_BOOTP_SUBNETMASK 97 #define CONFIG_BOOTP_SUBNETMASK
98 #define CONFIG_BOOTP_GATEWAY 98 #define CONFIG_BOOTP_GATEWAY
99 #define CONFIG_BOOTP_HOSTNAME 99 #define CONFIG_BOOTP_HOSTNAME
100 #define CONFIG_BOOTP_BOOTPATH 100 #define CONFIG_BOOTP_BOOTPATH
101 #define CONFIG_BOOTP_BOOTFILESIZE 101 #define CONFIG_BOOTP_BOOTFILESIZE
102 102
103 103
104 #define CONFIG_MAC_PARTITION 104 #define CONFIG_MAC_PARTITION
105 #define CONFIG_DOS_PARTITION 105 #define CONFIG_DOS_PARTITION
106 106
107 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 107 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
108 108
109 109
110 /* 110 /*
111 * Command line configuration. 111 * Command line configuration.
112 */ 112 */
113 #include <config_cmd_default.h> 113 #include <config_cmd_default.h>
114 114
115 #define CONFIG_CMD_ASKENV 115 #define CONFIG_CMD_ASKENV
116 #define CONFIG_CMD_DATE 116 #define CONFIG_CMD_DATE
117 #define CONFIG_CMD_DHCP 117 #define CONFIG_CMD_DHCP
118 #define CONFIG_CMD_ELF 118 #define CONFIG_CMD_ELF
119 #define CONFIG_CMD_EXT2
119 #define CONFIG_CMD_IDE 120 #define CONFIG_CMD_IDE
120 #define CONFIG_CMD_JFFS2 121 #define CONFIG_CMD_JFFS2
121 #define CONFIG_CMD_NFS 122 #define CONFIG_CMD_NFS
122 #define CONFIG_CMD_SNTP 123 #define CONFIG_CMD_SNTP
123 124
124 125
125 #define CONFIG_NETCONSOLE 126 #define CONFIG_NETCONSOLE
126 127
127 /* 128 /*
128 * Miscellaneous configurable options 129 * Miscellaneous configurable options
129 */ 130 */
130 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 131 #define CONFIG_SYS_LONGHELP /* undef to save memory */
131 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 132 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
132 133
133 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 134 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
134 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 135 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
135 #ifdef CONFIG_SYS_HUSH_PARSER 136 #ifdef CONFIG_SYS_HUSH_PARSER
136 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 137 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
137 #endif 138 #endif
138 139
139 #if defined(CONFIG_CMD_KGDB) 140 #if defined(CONFIG_CMD_KGDB)
140 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 141 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
141 #else 142 #else
142 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 143 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
143 #endif 144 #endif
144 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 145 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
145 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 146 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
147 148
148 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 149 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
149 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 150 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
150 151
151 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 152 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
152 153
153 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 154 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
154 155
155 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 156 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
156 157
157 /* 158 /*
158 * Low Level Configuration Settings 159 * Low Level Configuration Settings
159 * (address mappings, register initial values, etc.) 160 * (address mappings, register initial values, etc.)
160 * You should know what you are doing if you make changes here. 161 * You should know what you are doing if you make changes here.
161 */ 162 */
162 /*----------------------------------------------------------------------- 163 /*-----------------------------------------------------------------------
163 * Internal Memory Mapped Register 164 * Internal Memory Mapped Register
164 */ 165 */
165 #define CONFIG_SYS_IMMR 0xFFF00000 166 #define CONFIG_SYS_IMMR 0xFFF00000
166 167
167 /*----------------------------------------------------------------------- 168 /*-----------------------------------------------------------------------
168 * Definitions for initial stack pointer and data area (in DPRAM) 169 * Definitions for initial stack pointer and data area (in DPRAM)
169 */ 170 */
170 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 171 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
171 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 172 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
172 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 173 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
173 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 174 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
174 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 175 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
175 176
176 /*----------------------------------------------------------------------- 177 /*-----------------------------------------------------------------------
177 * Start addresses for the final memory configuration 178 * Start addresses for the final memory configuration
178 * (Set up by the startup code) 179 * (Set up by the startup code)
179 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 180 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
180 */ 181 */
181 #define CONFIG_SYS_SDRAM_BASE 0x00000000 182 #define CONFIG_SYS_SDRAM_BASE 0x00000000
182 #define CONFIG_SYS_FLASH_BASE 0x40000000 183 #define CONFIG_SYS_FLASH_BASE 0x40000000
183 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 184 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
185 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 186 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
186 187
187 /* 188 /*
188 * For booting Linux, the board info and command line data 189 * For booting Linux, the board info and command line data
189 * have to be in the first 8 MB of memory, since this is 190 * have to be in the first 8 MB of memory, since this is
190 * the maximum mapped by the Linux kernel during initialization. 191 * the maximum mapped by the Linux kernel during initialization.
191 */ 192 */
192 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 193 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
193 194
194 /*----------------------------------------------------------------------- 195 /*-----------------------------------------------------------------------
195 * FLASH organization 196 * FLASH organization
196 */ 197 */
197 198
198 /* use CFI flash driver */ 199 /* use CFI flash driver */
199 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 200 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
200 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 201 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
201 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 202 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
202 #define CONFIG_SYS_FLASH_EMPTY_INFO 203 #define CONFIG_SYS_FLASH_EMPTY_INFO
203 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 204 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
204 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
205 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
206 207
207 #define CONFIG_ENV_IS_IN_FLASH 1 208 #define CONFIG_ENV_IS_IN_FLASH 1
208 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 209 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
209 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 210 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
210 211
211 /* Address and size of Redundant Environment Sector */ 212 /* Address and size of Redundant Environment Sector */
212 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 213 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
213 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 214 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
214 215
215 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 216 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
216 217
217 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 218 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
218 219
219 /*----------------------------------------------------------------------- 220 /*-----------------------------------------------------------------------
220 * Dynamic MTD partition support 221 * Dynamic MTD partition support
221 */ 222 */
222 #define CONFIG_JFFS2_CMDLINE 223 #define CONFIG_JFFS2_CMDLINE
223 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 224 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
224 225
225 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 226 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
226 "128k(dtb)," \ 227 "128k(dtb)," \
227 "1664k(kernel)," \ 228 "1664k(kernel)," \
228 "2m(rootfs)," \ 229 "2m(rootfs)," \
229 "4m(data)" 230 "4m(data)"
230 231
231 /*----------------------------------------------------------------------- 232 /*-----------------------------------------------------------------------
232 * Hardware Information Block 233 * Hardware Information Block
233 */ 234 */
234 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 235 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
235 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 236 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
236 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 237 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
237 238
238 /*----------------------------------------------------------------------- 239 /*-----------------------------------------------------------------------
239 * Cache Configuration 240 * Cache Configuration
240 */ 241 */
241 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 242 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
242 #if defined(CONFIG_CMD_KGDB) 243 #if defined(CONFIG_CMD_KGDB)
243 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 244 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
244 #endif 245 #endif
245 246
246 /*----------------------------------------------------------------------- 247 /*-----------------------------------------------------------------------
247 * SYPCR - System Protection Control 11-9 248 * SYPCR - System Protection Control 11-9
248 * SYPCR can only be written once after reset! 249 * SYPCR can only be written once after reset!
249 *----------------------------------------------------------------------- 250 *-----------------------------------------------------------------------
250 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 251 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
251 */ 252 */
252 #if defined(CONFIG_WATCHDOG) 253 #if defined(CONFIG_WATCHDOG)
253 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 254 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
254 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 255 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
255 #else 256 #else
256 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 257 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
257 #endif 258 #endif
258 259
259 /*----------------------------------------------------------------------- 260 /*-----------------------------------------------------------------------
260 * SIUMCR - SIU Module Configuration 11-6 261 * SIUMCR - SIU Module Configuration 11-6
261 *----------------------------------------------------------------------- 262 *-----------------------------------------------------------------------
262 * PCMCIA config., multi-function pin tri-state 263 * PCMCIA config., multi-function pin tri-state
263 */ 264 */
264 #ifndef CONFIG_CAN_DRIVER 265 #ifndef CONFIG_CAN_DRIVER
265 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 266 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
266 #else /* we must activate GPL5 in the SIUMCR for CAN */ 267 #else /* we must activate GPL5 in the SIUMCR for CAN */
267 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 268 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
268 #endif /* CONFIG_CAN_DRIVER */ 269 #endif /* CONFIG_CAN_DRIVER */
269 270
270 /*----------------------------------------------------------------------- 271 /*-----------------------------------------------------------------------
271 * TBSCR - Time Base Status and Control 11-26 272 * TBSCR - Time Base Status and Control 11-26
272 *----------------------------------------------------------------------- 273 *-----------------------------------------------------------------------
273 * Clear Reference Interrupt Status, Timebase freezing enabled 274 * Clear Reference Interrupt Status, Timebase freezing enabled
274 */ 275 */
275 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 276 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
276 277
277 /*----------------------------------------------------------------------- 278 /*-----------------------------------------------------------------------
278 * RTCSC - Real-Time Clock Status and Control Register 11-27 279 * RTCSC - Real-Time Clock Status and Control Register 11-27
279 *----------------------------------------------------------------------- 280 *-----------------------------------------------------------------------
280 */ 281 */
281 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 282 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
282 283
283 /*----------------------------------------------------------------------- 284 /*-----------------------------------------------------------------------
284 * PISCR - Periodic Interrupt Status and Control 11-31 285 * PISCR - Periodic Interrupt Status and Control 11-31
285 *----------------------------------------------------------------------- 286 *-----------------------------------------------------------------------
286 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 287 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
287 */ 288 */
288 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 289 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
289 290
290 /*----------------------------------------------------------------------- 291 /*-----------------------------------------------------------------------
291 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 292 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
292 *----------------------------------------------------------------------- 293 *-----------------------------------------------------------------------
293 * Reset PLL lock status sticky bit, timer expired status bit and timer 294 * Reset PLL lock status sticky bit, timer expired status bit and timer
294 * interrupt status bit 295 * interrupt status bit
295 */ 296 */
296 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 297 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
297 298
298 /*----------------------------------------------------------------------- 299 /*-----------------------------------------------------------------------
299 * SCCR - System Clock and reset Control Register 15-27 300 * SCCR - System Clock and reset Control Register 15-27
300 *----------------------------------------------------------------------- 301 *-----------------------------------------------------------------------
301 * Set clock output, timebase and RTC source and divider, 302 * Set clock output, timebase and RTC source and divider,
302 * power management and some other internal clocks 303 * power management and some other internal clocks
303 */ 304 */
304 #define SCCR_MASK SCCR_EBDF11 305 #define SCCR_MASK SCCR_EBDF11
305 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 306 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
306 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 307 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
307 SCCR_DFALCD00) 308 SCCR_DFALCD00)
308 309
309 /*----------------------------------------------------------------------- 310 /*-----------------------------------------------------------------------
310 * PCMCIA stuff 311 * PCMCIA stuff
311 *----------------------------------------------------------------------- 312 *-----------------------------------------------------------------------
312 * 313 *
313 */ 314 */
314 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 315 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
315 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 316 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
316 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 317 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
317 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 318 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
318 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 319 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
319 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 320 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
320 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 321 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
321 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 322 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
322 323
323 /*----------------------------------------------------------------------- 324 /*-----------------------------------------------------------------------
324 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 325 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
325 *----------------------------------------------------------------------- 326 *-----------------------------------------------------------------------
326 */ 327 */
327 328
328 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 329 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
329 330
330 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 331 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
331 #undef CONFIG_IDE_LED /* LED for ide not supported */ 332 #undef CONFIG_IDE_LED /* LED for ide not supported */
332 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 333 #undef CONFIG_IDE_RESET /* reset for ide not supported */
333 334
334 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 335 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
335 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 336 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
336 337
337 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 338 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
338 339
339 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 340 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
340 341
341 /* Offset for data I/O */ 342 /* Offset for data I/O */
342 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 343 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
343 344
344 /* Offset for normal register accesses */ 345 /* Offset for normal register accesses */
345 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 346 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
346 347
347 /* Offset for alternate registers */ 348 /* Offset for alternate registers */
348 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 349 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
349 350
350 /*----------------------------------------------------------------------- 351 /*-----------------------------------------------------------------------
351 * 352 *
352 *----------------------------------------------------------------------- 353 *-----------------------------------------------------------------------
353 * 354 *
354 */ 355 */
355 #define CONFIG_SYS_DER 0 356 #define CONFIG_SYS_DER 0
356 357
357 /* 358 /*
358 * Init Memory Controller: 359 * Init Memory Controller:
359 * 360 *
360 * BR0/1 and OR0/1 (FLASH) 361 * BR0/1 and OR0/1 (FLASH)
361 */ 362 */
362 363
363 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 364 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
364 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 365 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
365 366
366 /* used to re-map FLASH both when starting from SRAM or FLASH: 367 /* used to re-map FLASH both when starting from SRAM or FLASH:
367 * restrict access enough to keep SRAM working (if any) 368 * restrict access enough to keep SRAM working (if any)
368 * but not too much to meddle with FLASH accesses 369 * but not too much to meddle with FLASH accesses
369 */ 370 */
370 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 371 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
371 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 372 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
372 373
373 /* 374 /*
374 * FLASH timing: 375 * FLASH timing:
375 */ 376 */
376 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 377 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
377 OR_SCY_3_CLK | OR_EHTR | OR_BI) 378 OR_SCY_3_CLK | OR_EHTR | OR_BI)
378 379
379 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 380 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
380 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 381 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
381 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 382 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
382 383
383 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 384 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
384 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 385 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
385 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 386 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
386 387
387 /* 388 /*
388 * BR2/3 and OR2/3 (SDRAM) 389 * BR2/3 and OR2/3 (SDRAM)
389 * 390 *
390 */ 391 */
391 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 392 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
392 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 393 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
393 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 394 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
394 395
395 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 396 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
396 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 397 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
397 398
398 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 399 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
399 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 400 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
400 401
401 #ifndef CONFIG_CAN_DRIVER 402 #ifndef CONFIG_CAN_DRIVER
402 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 403 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
403 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 404 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
404 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 405 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
405 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 406 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
406 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 407 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
407 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 408 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
408 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 409 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
409 BR_PS_8 | BR_MS_UPMB | BR_V ) 410 BR_PS_8 | BR_MS_UPMB | BR_V )
410 #endif /* CONFIG_CAN_DRIVER */ 411 #endif /* CONFIG_CAN_DRIVER */
411 412
412 /* 413 /*
413 * Memory Periodic Timer Prescaler 414 * Memory Periodic Timer Prescaler
414 * 415 *
415 * The Divider for PTA (refresh timer) configuration is based on an 416 * The Divider for PTA (refresh timer) configuration is based on an
416 * example SDRAM configuration (64 MBit, one bank). The adjustment to 417 * example SDRAM configuration (64 MBit, one bank). The adjustment to
417 * the number of chip selects (NCS) and the actually needed refresh 418 * the number of chip selects (NCS) and the actually needed refresh
418 * rate is done by setting MPTPR. 419 * rate is done by setting MPTPR.
419 * 420 *
420 * PTA is calculated from 421 * PTA is calculated from
421 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 422 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
422 * 423 *
423 * gclk CPU clock (not bus clock!) 424 * gclk CPU clock (not bus clock!)
424 * Trefresh Refresh cycle * 4 (four word bursts used) 425 * Trefresh Refresh cycle * 4 (four word bursts used)
425 * 426 *
426 * 4096 Rows from SDRAM example configuration 427 * 4096 Rows from SDRAM example configuration
427 * 1000 factor s -> ms 428 * 1000 factor s -> ms
428 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 429 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
429 * 4 Number of refresh cycles per period 430 * 4 Number of refresh cycles per period
430 * 64 Refresh cycle in ms per number of rows 431 * 64 Refresh cycle in ms per number of rows
431 * -------------------------------------------- 432 * --------------------------------------------
432 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 433 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
433 * 434 *
434 * 50 MHz => 50.000.000 / Divider = 98 435 * 50 MHz => 50.000.000 / Divider = 98
435 * 66 Mhz => 66.000.000 / Divider = 129 436 * 66 Mhz => 66.000.000 / Divider = 129
436 * 80 Mhz => 80.000.000 / Divider = 156 437 * 80 Mhz => 80.000.000 / Divider = 156
437 */ 438 */
438 439
439 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 440 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
440 #define CONFIG_SYS_MAMR_PTA 98 441 #define CONFIG_SYS_MAMR_PTA 98
441 442
442 /* 443 /*
443 * For 16 MBit, refresh rates could be 31.3 us 444 * For 16 MBit, refresh rates could be 31.3 us
444 * (= 64 ms / 2K = 125 / quad bursts). 445 * (= 64 ms / 2K = 125 / quad bursts).
445 * For a simpler initialization, 15.6 us is used instead. 446 * For a simpler initialization, 15.6 us is used instead.
446 * 447 *
447 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 448 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
448 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 449 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
449 */ 450 */
450 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 451 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
451 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 452 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
452 453
453 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 454 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
454 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 455 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
455 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 456 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
456 457
457 /* 458 /*
458 * MAMR settings for SDRAM 459 * MAMR settings for SDRAM
459 */ 460 */
460 461
461 /* 8 column SDRAM */ 462 /* 8 column SDRAM */
462 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 463 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
463 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 464 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
464 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 465 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
465 /* 9 column SDRAM */ 466 /* 9 column SDRAM */
466 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 467 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
467 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 468 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
468 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 469 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
469 470
470 471
471 /* 472 /*
472 * Internal Definitions 473 * Internal Definitions
473 * 474 *
474 * Boot Flags 475 * Boot Flags
475 */ 476 */
476 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 477 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
477 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 478 #define BOOTFLAG_WARM 0x02 /* Software reboot */
478 479
479 #define CONFIG_SCC1_ENET 480 #define CONFIG_SCC1_ENET
480 #define CONFIG_FEC_ENET 481 #define CONFIG_FEC_ENET
481 #define CONFIG_ETHPRIME "SCC ETHERNET" 482 #define CONFIG_ETHPRIME "SCC ETHERNET"
482 483
483 #endif /* __CONFIG_H */ 484 #endif /* __CONFIG_H */
484 485
include/configs/TQM860M.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37 #define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ 37 #define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
38 38
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2 40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE 41 #undef CONFIG_8xx_CONS_NONE
42 42
43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44 44
45 #define CONFIG_BOOTCOUNT_LIMIT 45 #define CONFIG_BOOTCOUNT_LIMIT
46 46
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48 48
49 #define CONFIG_BOARD_TYPES 1 /* support board types */ 49 #define CONFIG_BOARD_TYPES 1 /* support board types */
50 50
51 #define CONFIG_PREBOOT "echo;" \ 51 #define CONFIG_PREBOOT "echo;" \
52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
53 "echo" 53 "echo"
54 54
55 #undef CONFIG_BOOTARGS 55 #undef CONFIG_BOOTARGS
56 56
57 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "netdev=eth0\0" \ 58 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
60 "nfsroot=${serverip}:${rootpath}\0" \ 60 "nfsroot=${serverip}:${rootpath}\0" \
61 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 61 "ramargs=setenv bootargs root=/dev/ram rw\0" \
62 "addip=setenv bootargs ${bootargs} " \ 62 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \ 64 ":${hostname}:${netdev}:off panic=1\0" \
65 "flash_nfs=run nfsargs addip;" \ 65 "flash_nfs=run nfsargs addip;" \
66 "bootm ${kernel_addr}\0" \ 66 "bootm ${kernel_addr}\0" \
67 "flash_self=run ramargs addip;" \ 67 "flash_self=run ramargs addip;" \
68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
70 "rootpath=/opt/eldk/ppc_8xx\0" \ 70 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "hostname=TQM860M\0" \ 71 "hostname=TQM860M\0" \
72 "bootfile=TQM860M/uImage\0" \ 72 "bootfile=TQM860M/uImage\0" \
73 "fdt_addr=400C0000\0" \ 73 "fdt_addr=400C0000\0" \
74 "kernel_addr=40100000\0" \ 74 "kernel_addr=40100000\0" \
75 "ramdisk_addr=40280000\0" \ 75 "ramdisk_addr=40280000\0" \
76 "u-boot=TQM860M/u-image.bin\0" \ 76 "u-boot=TQM860M/u-image.bin\0" \
77 "load=tftp 200000 ${u-boot}\0" \ 77 "load=tftp 200000 ${u-boot}\0" \
78 "update=prot off 40000000 +${filesize};" \ 78 "update=prot off 40000000 +${filesize};" \
79 "era 40000000 +${filesize};" \ 79 "era 40000000 +${filesize};" \
80 "cp.b 200000 40000000 ${filesize};" \ 80 "cp.b 200000 40000000 ${filesize};" \
81 "sete filesize;save\0" \ 81 "sete filesize;save\0" \
82 "" 82 ""
83 #define CONFIG_BOOTCOMMAND "run flash_self" 83 #define CONFIG_BOOTCOMMAND "run flash_self"
84 84
85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
86 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 86 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
87 87
88 #undef CONFIG_WATCHDOG /* watchdog disabled */ 88 #undef CONFIG_WATCHDOG /* watchdog disabled */
89 89
90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
91 91
92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93 93
94 /* 94 /*
95 * BOOTP options 95 * BOOTP options
96 */ 96 */
97 #define CONFIG_BOOTP_SUBNETMASK 97 #define CONFIG_BOOTP_SUBNETMASK
98 #define CONFIG_BOOTP_GATEWAY 98 #define CONFIG_BOOTP_GATEWAY
99 #define CONFIG_BOOTP_HOSTNAME 99 #define CONFIG_BOOTP_HOSTNAME
100 #define CONFIG_BOOTP_BOOTPATH 100 #define CONFIG_BOOTP_BOOTPATH
101 #define CONFIG_BOOTP_BOOTFILESIZE 101 #define CONFIG_BOOTP_BOOTFILESIZE
102 102
103 103
104 #define CONFIG_MAC_PARTITION 104 #define CONFIG_MAC_PARTITION
105 #define CONFIG_DOS_PARTITION 105 #define CONFIG_DOS_PARTITION
106 106
107 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 107 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
108 108
109 109
110 /* 110 /*
111 * Command line configuration. 111 * Command line configuration.
112 */ 112 */
113 #include <config_cmd_default.h> 113 #include <config_cmd_default.h>
114 114
115 #define CONFIG_CMD_ASKENV 115 #define CONFIG_CMD_ASKENV
116 #define CONFIG_CMD_DATE 116 #define CONFIG_CMD_DATE
117 #define CONFIG_CMD_DHCP 117 #define CONFIG_CMD_DHCP
118 #define CONFIG_CMD_ELF 118 #define CONFIG_CMD_ELF
119 #define CONFIG_CMD_EXT2
119 #define CONFIG_CMD_IDE 120 #define CONFIG_CMD_IDE
120 #define CONFIG_CMD_JFFS2 121 #define CONFIG_CMD_JFFS2
121 #define CONFIG_CMD_NFS 122 #define CONFIG_CMD_NFS
122 #define CONFIG_CMD_SNTP 123 #define CONFIG_CMD_SNTP
123 124
124 125
125 #define CONFIG_NETCONSOLE 126 #define CONFIG_NETCONSOLE
126 127
127 128
128 /* 129 /*
129 * Miscellaneous configurable options 130 * Miscellaneous configurable options
130 */ 131 */
131 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 132 #define CONFIG_SYS_LONGHELP /* undef to save memory */
132 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 133 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
133 134
134 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 135 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
135 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 136 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
136 #ifdef CONFIG_SYS_HUSH_PARSER 137 #ifdef CONFIG_SYS_HUSH_PARSER
137 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 138 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
138 #endif 139 #endif
139 140
140 #if defined(CONFIG_CMD_KGDB) 141 #if defined(CONFIG_CMD_KGDB)
141 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 142 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
142 #else 143 #else
143 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 144 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
144 #endif 145 #endif
145 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 146 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
146 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 147 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 148 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
148 149
149 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 150 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
150 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 151 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
151 152
152 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 153 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
153 154
154 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 155 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
155 156
156 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 157 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
157 158
158 /* 159 /*
159 * Low Level Configuration Settings 160 * Low Level Configuration Settings
160 * (address mappings, register initial values, etc.) 161 * (address mappings, register initial values, etc.)
161 * You should know what you are doing if you make changes here. 162 * You should know what you are doing if you make changes here.
162 */ 163 */
163 /*----------------------------------------------------------------------- 164 /*-----------------------------------------------------------------------
164 * Internal Memory Mapped Register 165 * Internal Memory Mapped Register
165 */ 166 */
166 #define CONFIG_SYS_IMMR 0xFFF00000 167 #define CONFIG_SYS_IMMR 0xFFF00000
167 168
168 /*----------------------------------------------------------------------- 169 /*-----------------------------------------------------------------------
169 * Definitions for initial stack pointer and data area (in DPRAM) 170 * Definitions for initial stack pointer and data area (in DPRAM)
170 */ 171 */
171 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 172 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
172 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 173 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
173 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 174 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
174 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 175 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
175 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 176 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
176 177
177 /*----------------------------------------------------------------------- 178 /*-----------------------------------------------------------------------
178 * Start addresses for the final memory configuration 179 * Start addresses for the final memory configuration
179 * (Set up by the startup code) 180 * (Set up by the startup code)
180 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 181 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
181 */ 182 */
182 #define CONFIG_SYS_SDRAM_BASE 0x00000000 183 #define CONFIG_SYS_SDRAM_BASE 0x00000000
183 #define CONFIG_SYS_FLASH_BASE 0x40000000 184 #define CONFIG_SYS_FLASH_BASE 0x40000000
184 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 185 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 186 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
186 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ 187 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
187 188
188 /* 189 /*
189 * For booting Linux, the board info and command line data 190 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is 191 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization. 192 * the maximum mapped by the Linux kernel during initialization.
192 */ 193 */
193 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 194 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
194 195
195 /*----------------------------------------------------------------------- 196 /*-----------------------------------------------------------------------
196 * FLASH organization 197 * FLASH organization
197 */ 198 */
198 /* use CFI flash driver */ 199 /* use CFI flash driver */
199 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 200 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
200 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 201 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
201 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 202 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
202 #define CONFIG_SYS_FLASH_EMPTY_INFO 203 #define CONFIG_SYS_FLASH_EMPTY_INFO
203 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 204 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
204 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 205 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
205 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
206 207
207 #define CONFIG_ENV_IS_IN_FLASH 1 208 #define CONFIG_ENV_IS_IN_FLASH 1
208 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 209 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
209 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ 210 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
210 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 211 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
211 212
212 /* Address and size of Redundant Environment Sector */ 213 /* Address and size of Redundant Environment Sector */
213 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 214 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
214 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 215 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
215 216
216 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 217 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
217 218
218 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 219 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
219 220
220 /*----------------------------------------------------------------------- 221 /*-----------------------------------------------------------------------
221 * Dynamic MTD partition support 222 * Dynamic MTD partition support
222 */ 223 */
223 #define CONFIG_JFFS2_CMDLINE 224 #define CONFIG_JFFS2_CMDLINE
224 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 225 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
225 226
226 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 227 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
227 "128k(dtb)," \ 228 "128k(dtb)," \
228 "1920k(kernel)," \ 229 "1920k(kernel)," \
229 "5632(rootfs)," \ 230 "5632(rootfs)," \
230 "4m(data)" 231 "4m(data)"
231 232
232 /*----------------------------------------------------------------------- 233 /*-----------------------------------------------------------------------
233 * Hardware Information Block 234 * Hardware Information Block
234 */ 235 */
235 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 236 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
236 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 237 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
237 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 238 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
238 239
239 /*----------------------------------------------------------------------- 240 /*-----------------------------------------------------------------------
240 * Cache Configuration 241 * Cache Configuration
241 */ 242 */
242 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 243 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
243 #if defined(CONFIG_CMD_KGDB) 244 #if defined(CONFIG_CMD_KGDB)
244 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 245 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
245 #endif 246 #endif
246 247
247 /*----------------------------------------------------------------------- 248 /*-----------------------------------------------------------------------
248 * SYPCR - System Protection Control 11-9 249 * SYPCR - System Protection Control 11-9
249 * SYPCR can only be written once after reset! 250 * SYPCR can only be written once after reset!
250 *----------------------------------------------------------------------- 251 *-----------------------------------------------------------------------
251 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 252 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
252 */ 253 */
253 #if defined(CONFIG_WATCHDOG) 254 #if defined(CONFIG_WATCHDOG)
254 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 255 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
255 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 256 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
256 #else 257 #else
257 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 258 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
258 #endif 259 #endif
259 260
260 /*----------------------------------------------------------------------- 261 /*-----------------------------------------------------------------------
261 * SIUMCR - SIU Module Configuration 11-6 262 * SIUMCR - SIU Module Configuration 11-6
262 *----------------------------------------------------------------------- 263 *-----------------------------------------------------------------------
263 * PCMCIA config., multi-function pin tri-state 264 * PCMCIA config., multi-function pin tri-state
264 */ 265 */
265 #ifndef CONFIG_CAN_DRIVER 266 #ifndef CONFIG_CAN_DRIVER
266 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 267 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
267 #else /* we must activate GPL5 in the SIUMCR for CAN */ 268 #else /* we must activate GPL5 in the SIUMCR for CAN */
268 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 269 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
269 #endif /* CONFIG_CAN_DRIVER */ 270 #endif /* CONFIG_CAN_DRIVER */
270 271
271 /*----------------------------------------------------------------------- 272 /*-----------------------------------------------------------------------
272 * TBSCR - Time Base Status and Control 11-26 273 * TBSCR - Time Base Status and Control 11-26
273 *----------------------------------------------------------------------- 274 *-----------------------------------------------------------------------
274 * Clear Reference Interrupt Status, Timebase freezing enabled 275 * Clear Reference Interrupt Status, Timebase freezing enabled
275 */ 276 */
276 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 277 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
277 278
278 /*----------------------------------------------------------------------- 279 /*-----------------------------------------------------------------------
279 * RTCSC - Real-Time Clock Status and Control Register 11-27 280 * RTCSC - Real-Time Clock Status and Control Register 11-27
280 *----------------------------------------------------------------------- 281 *-----------------------------------------------------------------------
281 */ 282 */
282 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 283 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
283 284
284 /*----------------------------------------------------------------------- 285 /*-----------------------------------------------------------------------
285 * PISCR - Periodic Interrupt Status and Control 11-31 286 * PISCR - Periodic Interrupt Status and Control 11-31
286 *----------------------------------------------------------------------- 287 *-----------------------------------------------------------------------
287 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 288 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
288 */ 289 */
289 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 290 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
290 291
291 /*----------------------------------------------------------------------- 292 /*-----------------------------------------------------------------------
292 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 293 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
293 *----------------------------------------------------------------------- 294 *-----------------------------------------------------------------------
294 * Reset PLL lock status sticky bit, timer expired status bit and timer 295 * Reset PLL lock status sticky bit, timer expired status bit and timer
295 * interrupt status bit 296 * interrupt status bit
296 */ 297 */
297 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 298 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
298 299
299 /*----------------------------------------------------------------------- 300 /*-----------------------------------------------------------------------
300 * SCCR - System Clock and reset Control Register 15-27 301 * SCCR - System Clock and reset Control Register 15-27
301 *----------------------------------------------------------------------- 302 *-----------------------------------------------------------------------
302 * Set clock output, timebase and RTC source and divider, 303 * Set clock output, timebase and RTC source and divider,
303 * power management and some other internal clocks 304 * power management and some other internal clocks
304 */ 305 */
305 #define SCCR_MASK SCCR_EBDF11 306 #define SCCR_MASK SCCR_EBDF11
306 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 307 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
307 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 308 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
308 SCCR_DFALCD00) 309 SCCR_DFALCD00)
309 310
310 /*----------------------------------------------------------------------- 311 /*-----------------------------------------------------------------------
311 * PCMCIA stuff 312 * PCMCIA stuff
312 *----------------------------------------------------------------------- 313 *-----------------------------------------------------------------------
313 * 314 *
314 */ 315 */
315 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 316 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
316 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 317 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
317 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 318 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
318 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 319 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
319 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 320 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
320 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 321 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
321 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 322 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
322 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 323 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
323 324
324 /*----------------------------------------------------------------------- 325 /*-----------------------------------------------------------------------
325 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 326 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
326 *----------------------------------------------------------------------- 327 *-----------------------------------------------------------------------
327 */ 328 */
328 329
329 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 330 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
330 331
331 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 332 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
332 #undef CONFIG_IDE_LED /* LED for ide not supported */ 333 #undef CONFIG_IDE_LED /* LED for ide not supported */
333 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 334 #undef CONFIG_IDE_RESET /* reset for ide not supported */
334 335
335 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 336 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
336 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 337 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
337 338
338 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 339 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
339 340
340 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 341 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
341 342
342 /* Offset for data I/O */ 343 /* Offset for data I/O */
343 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 344 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
344 345
345 /* Offset for normal register accesses */ 346 /* Offset for normal register accesses */
346 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 347 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
347 348
348 /* Offset for alternate registers */ 349 /* Offset for alternate registers */
349 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 350 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
350 351
351 /*----------------------------------------------------------------------- 352 /*-----------------------------------------------------------------------
352 * 353 *
353 *----------------------------------------------------------------------- 354 *-----------------------------------------------------------------------
354 * 355 *
355 */ 356 */
356 #define CONFIG_SYS_DER 0 357 #define CONFIG_SYS_DER 0
357 358
358 /* 359 /*
359 * Init Memory Controller: 360 * Init Memory Controller:
360 * 361 *
361 * BR0/1 and OR0/1 (FLASH) 362 * BR0/1 and OR0/1 (FLASH)
362 */ 363 */
363 364
364 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 365 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
365 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 366 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
366 367
367 /* used to re-map FLASH both when starting from SRAM or FLASH: 368 /* used to re-map FLASH both when starting from SRAM or FLASH:
368 * restrict access enough to keep SRAM working (if any) 369 * restrict access enough to keep SRAM working (if any)
369 * but not too much to meddle with FLASH accesses 370 * but not too much to meddle with FLASH accesses
370 */ 371 */
371 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 372 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
372 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 373 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
373 374
374 /* 375 /*
375 * FLASH timing: 376 * FLASH timing:
376 */ 377 */
377 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 378 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
378 OR_SCY_3_CLK | OR_EHTR | OR_BI) 379 OR_SCY_3_CLK | OR_EHTR | OR_BI)
379 380
380 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 381 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
381 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 382 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
382 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 383 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
383 384
384 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 385 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
385 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 386 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
386 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 387 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
387 388
388 /* 389 /*
389 * BR2/3 and OR2/3 (SDRAM) 390 * BR2/3 and OR2/3 (SDRAM)
390 * 391 *
391 */ 392 */
392 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 393 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
393 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 394 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
394 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ 395 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */
395 396
396 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 397 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
397 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 398 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
398 399
399 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 400 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
400 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 401 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
401 402
402 #ifndef CONFIG_CAN_DRIVER 403 #ifndef CONFIG_CAN_DRIVER
403 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 404 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
404 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 405 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
405 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 406 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
406 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 407 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
407 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 408 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
408 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 409 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
409 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 410 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
410 BR_PS_8 | BR_MS_UPMB | BR_V ) 411 BR_PS_8 | BR_MS_UPMB | BR_V )
411 #endif /* CONFIG_CAN_DRIVER */ 412 #endif /* CONFIG_CAN_DRIVER */
412 413
413 /* 414 /*
414 * Memory Periodic Timer Prescaler 415 * Memory Periodic Timer Prescaler
415 * 416 *
416 * The Divider for PTA (refresh timer) configuration is based on an 417 * The Divider for PTA (refresh timer) configuration is based on an
417 * example SDRAM configuration (64 MBit, one bank). The adjustment to 418 * example SDRAM configuration (64 MBit, one bank). The adjustment to
418 * the number of chip selects (NCS) and the actually needed refresh 419 * the number of chip selects (NCS) and the actually needed refresh
419 * rate is done by setting MPTPR. 420 * rate is done by setting MPTPR.
420 * 421 *
421 * PTA is calculated from 422 * PTA is calculated from
422 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 423 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
423 * 424 *
424 * gclk CPU clock (not bus clock!) 425 * gclk CPU clock (not bus clock!)
425 * Trefresh Refresh cycle * 4 (four word bursts used) 426 * Trefresh Refresh cycle * 4 (four word bursts used)
426 * 427 *
427 * 4096 Rows from SDRAM example configuration 428 * 4096 Rows from SDRAM example configuration
428 * 1000 factor s -> ms 429 * 1000 factor s -> ms
429 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 430 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
430 * 4 Number of refresh cycles per period 431 * 4 Number of refresh cycles per period
431 * 64 Refresh cycle in ms per number of rows 432 * 64 Refresh cycle in ms per number of rows
432 * -------------------------------------------- 433 * --------------------------------------------
433 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 434 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
434 * 435 *
435 * 50 MHz => 50.000.000 / Divider = 98 436 * 50 MHz => 50.000.000 / Divider = 98
436 * 66 Mhz => 66.000.000 / Divider = 129 437 * 66 Mhz => 66.000.000 / Divider = 129
437 * 80 Mhz => 80.000.000 / Divider = 156 438 * 80 Mhz => 80.000.000 / Divider = 156
438 */ 439 */
439 440
440 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 441 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
441 #define CONFIG_SYS_MAMR_PTA 98 442 #define CONFIG_SYS_MAMR_PTA 98
442 443
443 /* 444 /*
444 * For 16 MBit, refresh rates could be 31.3 us 445 * For 16 MBit, refresh rates could be 31.3 us
445 * (= 64 ms / 2K = 125 / quad bursts). 446 * (= 64 ms / 2K = 125 / quad bursts).
446 * For a simpler initialization, 15.6 us is used instead. 447 * For a simpler initialization, 15.6 us is used instead.
447 * 448 *
448 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 449 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
449 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 450 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
450 */ 451 */
451 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 452 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
452 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 453 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
453 454
454 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 455 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
455 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 456 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
456 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 457 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
457 458
458 /* 459 /*
459 * MAMR settings for SDRAM 460 * MAMR settings for SDRAM
460 */ 461 */
461 462
462 /* 8 column SDRAM */ 463 /* 8 column SDRAM */
463 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 464 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
464 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 465 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
465 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
466 /* 9 column SDRAM */ 467 /* 9 column SDRAM */
467 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 468 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
468 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 469 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
469 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
470 /* 10 column SDRAM */ 471 /* 10 column SDRAM */
471 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 472 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
472 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 473 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 474 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
474 475
475 /* 476 /*
476 * Internal Definitions 477 * Internal Definitions
477 * 478 *
478 * Boot Flags 479 * Boot Flags
479 */ 480 */
480 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 481 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
481 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 482 #define BOOTFLAG_WARM 0x02 /* Software reboot */
482 483
483 #define CONFIG_SCC1_ENET 484 #define CONFIG_SCC1_ENET
484 #define CONFIG_FEC_ENET 485 #define CONFIG_FEC_ENET
485 #define CONFIG_ETHPRIME "SCC ETHERNET" 486 #define CONFIG_ETHPRIME "SCC ETHERNET"
486 487
487 #endif /* __CONFIG_H */ 488 #endif /* __CONFIG_H */
488 489
include/configs/TQM862L.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC860 1 36 #define CONFIG_MPC860 1
37 #define CONFIG_MPC860T 1 37 #define CONFIG_MPC860T 1
38 #define CONFIG_MPC862 1 38 #define CONFIG_MPC862 1
39 39
40 #define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ 40 #define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
41 41
42 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 42 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43 #undef CONFIG_8xx_CONS_SMC2 43 #undef CONFIG_8xx_CONS_SMC2
44 #undef CONFIG_8xx_CONS_NONE 44 #undef CONFIG_8xx_CONS_NONE
45 45
46 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 46 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
47 47
48 #define CONFIG_BOOTCOUNT_LIMIT 48 #define CONFIG_BOOTCOUNT_LIMIT
49 49
50 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 50 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
51 51
52 #define CONFIG_BOARD_TYPES 1 /* support board types */ 52 #define CONFIG_BOARD_TYPES 1 /* support board types */
53 53
54 #define CONFIG_PREBOOT "echo;" \ 54 #define CONFIG_PREBOOT "echo;" \
55 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 55 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
56 "echo" 56 "echo"
57 57
58 #undef CONFIG_BOOTARGS 58 #undef CONFIG_BOOTARGS
59 59
60 #define CONFIG_EXTRA_ENV_SETTINGS \ 60 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "netdev=eth0\0" \ 61 "netdev=eth0\0" \
62 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 62 "nfsargs=setenv bootargs root=/dev/nfs rw " \
63 "nfsroot=${serverip}:${rootpath}\0" \ 63 "nfsroot=${serverip}:${rootpath}\0" \
64 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 64 "ramargs=setenv bootargs root=/dev/ram rw\0" \
65 "addip=setenv bootargs ${bootargs} " \ 65 "addip=setenv bootargs ${bootargs} " \
66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
67 ":${hostname}:${netdev}:off panic=1\0" \ 67 ":${hostname}:${netdev}:off panic=1\0" \
68 "flash_nfs=run nfsargs addip;" \ 68 "flash_nfs=run nfsargs addip;" \
69 "bootm ${kernel_addr}\0" \ 69 "bootm ${kernel_addr}\0" \
70 "flash_self=run ramargs addip;" \ 70 "flash_self=run ramargs addip;" \
71 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 71 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
73 "rootpath=/opt/eldk/ppc_8xx\0" \ 73 "rootpath=/opt/eldk/ppc_8xx\0" \
74 "hostname=TQM862L\0" \ 74 "hostname=TQM862L\0" \
75 "bootfile=TQM862L/uImage\0" \ 75 "bootfile=TQM862L/uImage\0" \
76 "fdt_addr=40040000\0" \ 76 "fdt_addr=40040000\0" \
77 "kernel_addr=40060000\0" \ 77 "kernel_addr=40060000\0" \
78 "ramdisk_addr=40200000\0" \ 78 "ramdisk_addr=40200000\0" \
79 "u-boot=TQM862L/u-image.bin\0" \ 79 "u-boot=TQM862L/u-image.bin\0" \
80 "load=tftp 200000 ${u-boot}\0" \ 80 "load=tftp 200000 ${u-boot}\0" \
81 "update=prot off 40000000 +${filesize};" \ 81 "update=prot off 40000000 +${filesize};" \
82 "era 40000000 +${filesize};" \ 82 "era 40000000 +${filesize};" \
83 "cp.b 200000 40000000 ${filesize};" \ 83 "cp.b 200000 40000000 ${filesize};" \
84 "sete filesize;save\0" \ 84 "sete filesize;save\0" \
85 "" 85 ""
86 #define CONFIG_BOOTCOMMAND "run flash_self" 86 #define CONFIG_BOOTCOMMAND "run flash_self"
87 87
88 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 88 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
89 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 89 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
90 90
91 #undef CONFIG_WATCHDOG /* watchdog disabled */ 91 #undef CONFIG_WATCHDOG /* watchdog disabled */
92 92
93 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 93 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
94 94
95 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 95 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
96 96
97 /* 97 /*
98 * BOOTP options 98 * BOOTP options
99 */ 99 */
100 #define CONFIG_BOOTP_SUBNETMASK 100 #define CONFIG_BOOTP_SUBNETMASK
101 #define CONFIG_BOOTP_GATEWAY 101 #define CONFIG_BOOTP_GATEWAY
102 #define CONFIG_BOOTP_HOSTNAME 102 #define CONFIG_BOOTP_HOSTNAME
103 #define CONFIG_BOOTP_BOOTPATH 103 #define CONFIG_BOOTP_BOOTPATH
104 #define CONFIG_BOOTP_BOOTFILESIZE 104 #define CONFIG_BOOTP_BOOTFILESIZE
105 105
106 106
107 #define CONFIG_MAC_PARTITION 107 #define CONFIG_MAC_PARTITION
108 #define CONFIG_DOS_PARTITION 108 #define CONFIG_DOS_PARTITION
109 109
110 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 110 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
111 111
112 112
113 /* 113 /*
114 * Command line configuration. 114 * Command line configuration.
115 */ 115 */
116 #include <config_cmd_default.h> 116 #include <config_cmd_default.h>
117 117
118 #define CONFIG_CMD_ASKENV 118 #define CONFIG_CMD_ASKENV
119 #define CONFIG_CMD_DATE 119 #define CONFIG_CMD_DATE
120 #define CONFIG_CMD_DHCP 120 #define CONFIG_CMD_DHCP
121 #define CONFIG_CMD_ELF 121 #define CONFIG_CMD_ELF
122 #define CONFIG_CMD_EXT2
122 #define CONFIG_CMD_IDE 123 #define CONFIG_CMD_IDE
123 #define CONFIG_CMD_JFFS2 124 #define CONFIG_CMD_JFFS2
124 #define CONFIG_CMD_NFS 125 #define CONFIG_CMD_NFS
125 #define CONFIG_CMD_SNTP 126 #define CONFIG_CMD_SNTP
126 127
127 128
128 #define CONFIG_NETCONSOLE 129 #define CONFIG_NETCONSOLE
129 130
130 131
131 /* 132 /*
132 * Miscellaneous configurable options 133 * Miscellaneous configurable options
133 */ 134 */
134 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 135 #define CONFIG_SYS_LONGHELP /* undef to save memory */
135 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 136 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
136 137
137 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 138 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
138 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 139 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
139 #ifdef CONFIG_SYS_HUSH_PARSER 140 #ifdef CONFIG_SYS_HUSH_PARSER
140 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 141 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
141 #endif 142 #endif
142 143
143 #if defined(CONFIG_CMD_KGDB) 144 #if defined(CONFIG_CMD_KGDB)
144 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 145 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
145 #else 146 #else
146 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 147 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
147 #endif 148 #endif
148 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 149 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 150 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 151 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
151 152
152 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 153 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
153 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 154 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
154 155
155 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 156 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
156 157
157 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 158 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
158 159
159 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 160 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
160 161
161 /* 162 /*
162 * Low Level Configuration Settings 163 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.) 164 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here. 165 * You should know what you are doing if you make changes here.
165 */ 166 */
166 /*----------------------------------------------------------------------- 167 /*-----------------------------------------------------------------------
167 * Internal Memory Mapped Register 168 * Internal Memory Mapped Register
168 */ 169 */
169 #define CONFIG_SYS_IMMR 0xFFF00000 170 #define CONFIG_SYS_IMMR 0xFFF00000
170 171
171 /*----------------------------------------------------------------------- 172 /*-----------------------------------------------------------------------
172 * Definitions for initial stack pointer and data area (in DPRAM) 173 * Definitions for initial stack pointer and data area (in DPRAM)
173 */ 174 */
174 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 175 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
175 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 176 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
176 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 177 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
177 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 178 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
178 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
179 180
180 /*----------------------------------------------------------------------- 181 /*-----------------------------------------------------------------------
181 * Start addresses for the final memory configuration 182 * Start addresses for the final memory configuration
182 * (Set up by the startup code) 183 * (Set up by the startup code)
183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 184 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
184 */ 185 */
185 #define CONFIG_SYS_SDRAM_BASE 0x00000000 186 #define CONFIG_SYS_SDRAM_BASE 0x00000000
186 #define CONFIG_SYS_FLASH_BASE 0x40000000 187 #define CONFIG_SYS_FLASH_BASE 0x40000000
187 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 188 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
188 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
189 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 190 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
190 191
191 /* 192 /*
192 * For booting Linux, the board info and command line data 193 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is 194 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization. 195 * the maximum mapped by the Linux kernel during initialization.
195 */ 196 */
196 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 197 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
197 198
198 /*----------------------------------------------------------------------- 199 /*-----------------------------------------------------------------------
199 * FLASH organization 200 * FLASH organization
200 */ 201 */
201 202
202 /* use CFI flash driver */ 203 /* use CFI flash driver */
203 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 204 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
204 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 205 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
205 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 206 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
206 #define CONFIG_SYS_FLASH_EMPTY_INFO 207 #define CONFIG_SYS_FLASH_EMPTY_INFO
207 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 208 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
208 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 209 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
209 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 210 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
210 211
211 #define CONFIG_ENV_IS_IN_FLASH 1 212 #define CONFIG_ENV_IS_IN_FLASH 1
212 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 213 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
213 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 214 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
214 215
215 /* Address and size of Redundant Environment Sector */ 216 /* Address and size of Redundant Environment Sector */
216 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 217 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
217 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 218 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
218 219
219 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 220 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
220 221
221 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 222 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
222 223
223 /*----------------------------------------------------------------------- 224 /*-----------------------------------------------------------------------
224 * Dynamic MTD partition support 225 * Dynamic MTD partition support
225 */ 226 */
226 #define CONFIG_JFFS2_CMDLINE 227 #define CONFIG_JFFS2_CMDLINE
227 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 228 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
228 229
229 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 230 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
230 "128k(dtb)," \ 231 "128k(dtb)," \
231 "1664k(kernel)," \ 232 "1664k(kernel)," \
232 "2m(rootfs)," \ 233 "2m(rootfs)," \
233 "4m(data)" 234 "4m(data)"
234 235
235 /*----------------------------------------------------------------------- 236 /*-----------------------------------------------------------------------
236 * Hardware Information Block 237 * Hardware Information Block
237 */ 238 */
238 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 239 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
239 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 240 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
240 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 241 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
241 242
242 /*----------------------------------------------------------------------- 243 /*-----------------------------------------------------------------------
243 * Cache Configuration 244 * Cache Configuration
244 */ 245 */
245 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 246 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
246 #if defined(CONFIG_CMD_KGDB) 247 #if defined(CONFIG_CMD_KGDB)
247 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 248 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
248 #endif 249 #endif
249 250
250 /*----------------------------------------------------------------------- 251 /*-----------------------------------------------------------------------
251 * SYPCR - System Protection Control 11-9 252 * SYPCR - System Protection Control 11-9
252 * SYPCR can only be written once after reset! 253 * SYPCR can only be written once after reset!
253 *----------------------------------------------------------------------- 254 *-----------------------------------------------------------------------
254 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 255 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
255 */ 256 */
256 #if defined(CONFIG_WATCHDOG) 257 #if defined(CONFIG_WATCHDOG)
257 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 258 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
258 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 259 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
259 #else 260 #else
260 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 261 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
261 #endif 262 #endif
262 263
263 /*----------------------------------------------------------------------- 264 /*-----------------------------------------------------------------------
264 * SIUMCR - SIU Module Configuration 11-6 265 * SIUMCR - SIU Module Configuration 11-6
265 *----------------------------------------------------------------------- 266 *-----------------------------------------------------------------------
266 * PCMCIA config., multi-function pin tri-state 267 * PCMCIA config., multi-function pin tri-state
267 */ 268 */
268 #ifndef CONFIG_CAN_DRIVER 269 #ifndef CONFIG_CAN_DRIVER
269 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 270 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
270 #else /* we must activate GPL5 in the SIUMCR for CAN */ 271 #else /* we must activate GPL5 in the SIUMCR for CAN */
271 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 272 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
272 #endif /* CONFIG_CAN_DRIVER */ 273 #endif /* CONFIG_CAN_DRIVER */
273 274
274 /*----------------------------------------------------------------------- 275 /*-----------------------------------------------------------------------
275 * TBSCR - Time Base Status and Control 11-26 276 * TBSCR - Time Base Status and Control 11-26
276 *----------------------------------------------------------------------- 277 *-----------------------------------------------------------------------
277 * Clear Reference Interrupt Status, Timebase freezing enabled 278 * Clear Reference Interrupt Status, Timebase freezing enabled
278 */ 279 */
279 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 280 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
280 281
281 /*----------------------------------------------------------------------- 282 /*-----------------------------------------------------------------------
282 * RTCSC - Real-Time Clock Status and Control Register 11-27 283 * RTCSC - Real-Time Clock Status and Control Register 11-27
283 *----------------------------------------------------------------------- 284 *-----------------------------------------------------------------------
284 */ 285 */
285 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 286 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
286 287
287 /*----------------------------------------------------------------------- 288 /*-----------------------------------------------------------------------
288 * PISCR - Periodic Interrupt Status and Control 11-31 289 * PISCR - Periodic Interrupt Status and Control 11-31
289 *----------------------------------------------------------------------- 290 *-----------------------------------------------------------------------
290 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 291 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
291 */ 292 */
292 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 293 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
293 294
294 /*----------------------------------------------------------------------- 295 /*-----------------------------------------------------------------------
295 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 296 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
296 *----------------------------------------------------------------------- 297 *-----------------------------------------------------------------------
297 * Reset PLL lock status sticky bit, timer expired status bit and timer 298 * Reset PLL lock status sticky bit, timer expired status bit and timer
298 * interrupt status bit 299 * interrupt status bit
299 */ 300 */
300 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 301 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
301 302
302 /*----------------------------------------------------------------------- 303 /*-----------------------------------------------------------------------
303 * SCCR - System Clock and reset Control Register 15-27 304 * SCCR - System Clock and reset Control Register 15-27
304 *----------------------------------------------------------------------- 305 *-----------------------------------------------------------------------
305 * Set clock output, timebase and RTC source and divider, 306 * Set clock output, timebase and RTC source and divider,
306 * power management and some other internal clocks 307 * power management and some other internal clocks
307 */ 308 */
308 #define SCCR_MASK SCCR_EBDF11 309 #define SCCR_MASK SCCR_EBDF11
309 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 310 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
310 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 311 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
311 SCCR_DFALCD00) 312 SCCR_DFALCD00)
312 313
313 /*----------------------------------------------------------------------- 314 /*-----------------------------------------------------------------------
314 * PCMCIA stuff 315 * PCMCIA stuff
315 *----------------------------------------------------------------------- 316 *-----------------------------------------------------------------------
316 * 317 *
317 */ 318 */
318 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 319 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
319 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 320 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
320 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 321 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
321 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 322 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
322 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 323 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
323 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 324 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
324 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 325 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
325 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 326 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
326 327
327 /*----------------------------------------------------------------------- 328 /*-----------------------------------------------------------------------
328 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 329 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
329 *----------------------------------------------------------------------- 330 *-----------------------------------------------------------------------
330 */ 331 */
331 332
332 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 333 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
333 334
334 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 335 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
335 #undef CONFIG_IDE_LED /* LED for ide not supported */ 336 #undef CONFIG_IDE_LED /* LED for ide not supported */
336 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 337 #undef CONFIG_IDE_RESET /* reset for ide not supported */
337 338
338 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 339 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
339 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 340 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
340 341
341 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 342 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
342 343
343 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 344 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
344 345
345 /* Offset for data I/O */ 346 /* Offset for data I/O */
346 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 347 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
347 348
348 /* Offset for normal register accesses */ 349 /* Offset for normal register accesses */
349 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 350 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
350 351
351 /* Offset for alternate registers */ 352 /* Offset for alternate registers */
352 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 353 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
353 354
354 /*----------------------------------------------------------------------- 355 /*-----------------------------------------------------------------------
355 * 356 *
356 *----------------------------------------------------------------------- 357 *-----------------------------------------------------------------------
357 * 358 *
358 */ 359 */
359 #define CONFIG_SYS_DER 0 360 #define CONFIG_SYS_DER 0
360 361
361 /* 362 /*
362 * Init Memory Controller: 363 * Init Memory Controller:
363 * 364 *
364 * BR0/1 and OR0/1 (FLASH) 365 * BR0/1 and OR0/1 (FLASH)
365 */ 366 */
366 367
367 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 368 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
368 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ 369 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
369 370
370 /* used to re-map FLASH both when starting from SRAM or FLASH: 371 /* used to re-map FLASH both when starting from SRAM or FLASH:
371 * restrict access enough to keep SRAM working (if any) 372 * restrict access enough to keep SRAM working (if any)
372 * but not too much to meddle with FLASH accesses 373 * but not too much to meddle with FLASH accesses
373 */ 374 */
374 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 375 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
375 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 376 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
376 377
377 /* 378 /*
378 * FLASH timing: 379 * FLASH timing:
379 */ 380 */
380 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
381 OR_SCY_3_CLK | OR_EHTR | OR_BI) 382 OR_SCY_3_CLK | OR_EHTR | OR_BI)
382 383
383 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 384 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
384 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 385 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
385 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 386 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
386 387
387 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 388 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
388 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 389 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
389 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 390 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
390 391
391 /* 392 /*
392 * BR2/3 and OR2/3 (SDRAM) 393 * BR2/3 and OR2/3 (SDRAM)
393 * 394 *
394 */ 395 */
395 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 396 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
396 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 397 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
397 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 398 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
398 399
399 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 400 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
400 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 401 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
401 402
402 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 403 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
403 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 404 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
404 405
405 #ifndef CONFIG_CAN_DRIVER 406 #ifndef CONFIG_CAN_DRIVER
406 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 407 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
407 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 408 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
408 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 409 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
409 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 410 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
410 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 411 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
411 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 412 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
412 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 413 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
413 BR_PS_8 | BR_MS_UPMB | BR_V ) 414 BR_PS_8 | BR_MS_UPMB | BR_V )
414 #endif /* CONFIG_CAN_DRIVER */ 415 #endif /* CONFIG_CAN_DRIVER */
415 416
416 /* 417 /*
417 * Memory Periodic Timer Prescaler 418 * Memory Periodic Timer Prescaler
418 * 419 *
419 * The Divider for PTA (refresh timer) configuration is based on an 420 * The Divider for PTA (refresh timer) configuration is based on an
420 * example SDRAM configuration (64 MBit, one bank). The adjustment to 421 * example SDRAM configuration (64 MBit, one bank). The adjustment to
421 * the number of chip selects (NCS) and the actually needed refresh 422 * the number of chip selects (NCS) and the actually needed refresh
422 * rate is done by setting MPTPR. 423 * rate is done by setting MPTPR.
423 * 424 *
424 * PTA is calculated from 425 * PTA is calculated from
425 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 426 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
426 * 427 *
427 * gclk CPU clock (not bus clock!) 428 * gclk CPU clock (not bus clock!)
428 * Trefresh Refresh cycle * 4 (four word bursts used) 429 * Trefresh Refresh cycle * 4 (four word bursts used)
429 * 430 *
430 * 4096 Rows from SDRAM example configuration 431 * 4096 Rows from SDRAM example configuration
431 * 1000 factor s -> ms 432 * 1000 factor s -> ms
432 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 433 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
433 * 4 Number of refresh cycles per period 434 * 4 Number of refresh cycles per period
434 * 64 Refresh cycle in ms per number of rows 435 * 64 Refresh cycle in ms per number of rows
435 * -------------------------------------------- 436 * --------------------------------------------
436 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 437 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
437 * 438 *
438 * 50 MHz => 50.000.000 / Divider = 98 439 * 50 MHz => 50.000.000 / Divider = 98
439 * 66 Mhz => 66.000.000 / Divider = 129 440 * 66 Mhz => 66.000.000 / Divider = 129
440 * 80 Mhz => 80.000.000 / Divider = 156 441 * 80 Mhz => 80.000.000 / Divider = 156
441 * 100 Mhz => 100.000.000 / Divider = 195 442 * 100 Mhz => 100.000.000 / Divider = 195
442 */ 443 */
443 444
444 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 445 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
445 #define CONFIG_SYS_MAMR_PTA 98 446 #define CONFIG_SYS_MAMR_PTA 98
446 447
447 /* 448 /*
448 * For 16 MBit, refresh rates could be 31.3 us 449 * For 16 MBit, refresh rates could be 31.3 us
449 * (= 64 ms / 2K = 125 / quad bursts). 450 * (= 64 ms / 2K = 125 / quad bursts).
450 * For a simpler initialization, 15.6 us is used instead. 451 * For a simpler initialization, 15.6 us is used instead.
451 * 452 *
452 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 453 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
453 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 454 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
454 */ 455 */
455 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 456 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
456 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 457 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
457 458
458 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 459 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
459 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 460 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
460 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 461 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
461 462
462 /* 463 /*
463 * MAMR settings for SDRAM 464 * MAMR settings for SDRAM
464 */ 465 */
465 466
466 /* 8 column SDRAM */ 467 /* 8 column SDRAM */
467 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 468 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
468 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 469 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
469 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
470 /* 9 column SDRAM */ 471 /* 9 column SDRAM */
471 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 472 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
472 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 473 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 474 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
474 475
475 476
476 /* 477 /*
477 * Internal Definitions 478 * Internal Definitions
478 * 479 *
479 * Boot Flags 480 * Boot Flags
480 */ 481 */
481 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 482 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
482 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 483 #define BOOTFLAG_WARM 0x02 /* Software reboot */
483 484
484 #define CONFIG_NET_MULTI 485 #define CONFIG_NET_MULTI
485 #define CONFIG_SCC1_ENET 486 #define CONFIG_SCC1_ENET
486 #define CONFIG_FEC_ENET 487 #define CONFIG_FEC_ENET
487 #define CONFIG_ETHPRIME "SCC ETHERNET" 488 #define CONFIG_ETHPRIME "SCC ETHERNET"
488 489
489 #endif /* __CONFIG_H */ 490 #endif /* __CONFIG_H */
490 491
include/configs/TQM862M.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC860 1 36 #define CONFIG_MPC860 1
37 #define CONFIG_MPC860T 1 37 #define CONFIG_MPC860T 1
38 #define CONFIG_MPC862 1 38 #define CONFIG_MPC862 1
39 39
40 #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ 40 #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
41 41
42 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 42 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43 #undef CONFIG_8xx_CONS_SMC2 43 #undef CONFIG_8xx_CONS_SMC2
44 #undef CONFIG_8xx_CONS_NONE 44 #undef CONFIG_8xx_CONS_NONE
45 45
46 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 46 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
47 47
48 #define CONFIG_BOOTCOUNT_LIMIT 48 #define CONFIG_BOOTCOUNT_LIMIT
49 49
50 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 50 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
51 51
52 #define CONFIG_BOARD_TYPES 1 /* support board types */ 52 #define CONFIG_BOARD_TYPES 1 /* support board types */
53 53
54 #define CONFIG_PREBOOT "echo;" \ 54 #define CONFIG_PREBOOT "echo;" \
55 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 55 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
56 "echo" 56 "echo"
57 57
58 #undef CONFIG_BOOTARGS 58 #undef CONFIG_BOOTARGS
59 59
60 #define CONFIG_EXTRA_ENV_SETTINGS \ 60 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "netdev=eth0\0" \ 61 "netdev=eth0\0" \
62 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 62 "nfsargs=setenv bootargs root=/dev/nfs rw " \
63 "nfsroot=${serverip}:${rootpath}\0" \ 63 "nfsroot=${serverip}:${rootpath}\0" \
64 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 64 "ramargs=setenv bootargs root=/dev/ram rw\0" \
65 "addip=setenv bootargs ${bootargs} " \ 65 "addip=setenv bootargs ${bootargs} " \
66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
67 ":${hostname}:${netdev}:off panic=1\0" \ 67 ":${hostname}:${netdev}:off panic=1\0" \
68 "flash_nfs=run nfsargs addip;" \ 68 "flash_nfs=run nfsargs addip;" \
69 "bootm ${kernel_addr}\0" \ 69 "bootm ${kernel_addr}\0" \
70 "flash_self=run ramargs addip;" \ 70 "flash_self=run ramargs addip;" \
71 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 71 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
73 "rootpath=/opt/eldk/ppc_8xx\0" \ 73 "rootpath=/opt/eldk/ppc_8xx\0" \
74 "hostname=TQM862M\0" \ 74 "hostname=TQM862M\0" \
75 "bootfile=TQM862M/uImage\0" \ 75 "bootfile=TQM862M/uImage\0" \
76 "fdt_addr=40080000\0" \ 76 "fdt_addr=40080000\0" \
77 "kernel_addr=400A0000\0" \ 77 "kernel_addr=400A0000\0" \
78 "ramdisk_addr=40280000\0" \ 78 "ramdisk_addr=40280000\0" \
79 "u-boot=TQM862M/u-image.bin\0" \ 79 "u-boot=TQM862M/u-image.bin\0" \
80 "load=tftp 200000 ${u-boot}\0" \ 80 "load=tftp 200000 ${u-boot}\0" \
81 "update=prot off 40000000 +${filesize};" \ 81 "update=prot off 40000000 +${filesize};" \
82 "era 40000000 +${filesize};" \ 82 "era 40000000 +${filesize};" \
83 "cp.b 200000 40000000 ${filesize};" \ 83 "cp.b 200000 40000000 ${filesize};" \
84 "sete filesize;save\0" \ 84 "sete filesize;save\0" \
85 "" 85 ""
86 #define CONFIG_BOOTCOMMAND "run flash_self" 86 #define CONFIG_BOOTCOMMAND "run flash_self"
87 87
88 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 88 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
89 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 89 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
90 90
91 #undef CONFIG_WATCHDOG /* watchdog disabled */ 91 #undef CONFIG_WATCHDOG /* watchdog disabled */
92 92
93 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 93 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
94 94
95 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 95 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
96 96
97 /* 97 /*
98 * BOOTP options 98 * BOOTP options
99 */ 99 */
100 #define CONFIG_BOOTP_SUBNETMASK 100 #define CONFIG_BOOTP_SUBNETMASK
101 #define CONFIG_BOOTP_GATEWAY 101 #define CONFIG_BOOTP_GATEWAY
102 #define CONFIG_BOOTP_HOSTNAME 102 #define CONFIG_BOOTP_HOSTNAME
103 #define CONFIG_BOOTP_BOOTPATH 103 #define CONFIG_BOOTP_BOOTPATH
104 #define CONFIG_BOOTP_BOOTFILESIZE 104 #define CONFIG_BOOTP_BOOTFILESIZE
105 105
106 106
107 #define CONFIG_MAC_PARTITION 107 #define CONFIG_MAC_PARTITION
108 #define CONFIG_DOS_PARTITION 108 #define CONFIG_DOS_PARTITION
109 109
110 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 110 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
111 111
112 112
113 /* 113 /*
114 * Command line configuration. 114 * Command line configuration.
115 */ 115 */
116 #include <config_cmd_default.h> 116 #include <config_cmd_default.h>
117 117
118 #define CONFIG_CMD_ASKENV 118 #define CONFIG_CMD_ASKENV
119 #define CONFIG_CMD_DATE 119 #define CONFIG_CMD_DATE
120 #define CONFIG_CMD_DHCP 120 #define CONFIG_CMD_DHCP
121 #define CONFIG_CMD_ELF 121 #define CONFIG_CMD_ELF
122 #define CONFIG_CMD_EXT2
122 #define CONFIG_CMD_IDE 123 #define CONFIG_CMD_IDE
123 #define CONFIG_CMD_JFFS2 124 #define CONFIG_CMD_JFFS2
124 #define CONFIG_CMD_NFS 125 #define CONFIG_CMD_NFS
125 #define CONFIG_CMD_SNTP 126 #define CONFIG_CMD_SNTP
126 127
127 128
128 #define CONFIG_NETCONSOLE 129 #define CONFIG_NETCONSOLE
129 130
130 131
131 /* 132 /*
132 * Miscellaneous configurable options 133 * Miscellaneous configurable options
133 */ 134 */
134 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 135 #define CONFIG_SYS_LONGHELP /* undef to save memory */
135 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 136 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
136 137
137 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 138 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
138 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 139 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
139 #ifdef CONFIG_SYS_HUSH_PARSER 140 #ifdef CONFIG_SYS_HUSH_PARSER
140 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 141 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
141 #endif 142 #endif
142 143
143 #if defined(CONFIG_CMD_KGDB) 144 #if defined(CONFIG_CMD_KGDB)
144 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 145 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
145 #else 146 #else
146 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 147 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
147 #endif 148 #endif
148 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 149 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 150 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 151 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
151 152
152 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 153 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
153 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 154 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
154 155
155 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 156 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
156 157
157 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 158 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
158 159
159 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 160 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
160 161
161 /* 162 /*
162 * Low Level Configuration Settings 163 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.) 164 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here. 165 * You should know what you are doing if you make changes here.
165 */ 166 */
166 /*----------------------------------------------------------------------- 167 /*-----------------------------------------------------------------------
167 * Internal Memory Mapped Register 168 * Internal Memory Mapped Register
168 */ 169 */
169 #define CONFIG_SYS_IMMR 0xFFF00000 170 #define CONFIG_SYS_IMMR 0xFFF00000
170 171
171 /*----------------------------------------------------------------------- 172 /*-----------------------------------------------------------------------
172 * Definitions for initial stack pointer and data area (in DPRAM) 173 * Definitions for initial stack pointer and data area (in DPRAM)
173 */ 174 */
174 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 175 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
175 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 176 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
176 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 177 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
177 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 178 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
178 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
179 180
180 /*----------------------------------------------------------------------- 181 /*-----------------------------------------------------------------------
181 * Start addresses for the final memory configuration 182 * Start addresses for the final memory configuration
182 * (Set up by the startup code) 183 * (Set up by the startup code)
183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 184 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
184 */ 185 */
185 #define CONFIG_SYS_SDRAM_BASE 0x00000000 186 #define CONFIG_SYS_SDRAM_BASE 0x00000000
186 #define CONFIG_SYS_FLASH_BASE 0x40000000 187 #define CONFIG_SYS_FLASH_BASE 0x40000000
187 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 188 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
188 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
189 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 190 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
190 191
191 /* 192 /*
192 * For booting Linux, the board info and command line data 193 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is 194 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization. 195 * the maximum mapped by the Linux kernel during initialization.
195 */ 196 */
196 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 197 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
197 198
198 /*----------------------------------------------------------------------- 199 /*-----------------------------------------------------------------------
199 * FLASH organization 200 * FLASH organization
200 */ 201 */
201 202
202 /* use CFI flash driver */ 203 /* use CFI flash driver */
203 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 204 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
204 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 205 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
205 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 206 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
206 #define CONFIG_SYS_FLASH_EMPTY_INFO 207 #define CONFIG_SYS_FLASH_EMPTY_INFO
207 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 208 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 209 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
209 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 210 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
210 211
211 #define CONFIG_ENV_IS_IN_FLASH 1 212 #define CONFIG_ENV_IS_IN_FLASH 1
212 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 213 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
213 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 214 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
214 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 215 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
215 216
216 /* Address and size of Redundant Environment Sector */ 217 /* Address and size of Redundant Environment Sector */
217 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 218 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
218 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 219 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
219 220
220 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 221 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
221 222
222 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 223 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
223 224
224 /*----------------------------------------------------------------------- 225 /*-----------------------------------------------------------------------
225 * Dynamic MTD partition support 226 * Dynamic MTD partition support
226 */ 227 */
227 #define CONFIG_JFFS2_CMDLINE 228 #define CONFIG_JFFS2_CMDLINE
228 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 229 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
229 230
230 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 231 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
231 "128k(dtb)," \ 232 "128k(dtb)," \
232 "1920k(kernel)," \ 233 "1920k(kernel)," \
233 "5632(rootfs)," \ 234 "5632(rootfs)," \
234 "4m(data)" 235 "4m(data)"
235 236
236 /*----------------------------------------------------------------------- 237 /*-----------------------------------------------------------------------
237 * Hardware Information Block 238 * Hardware Information Block
238 */ 239 */
239 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 240 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
240 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 241 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
241 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 242 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
242 243
243 /*----------------------------------------------------------------------- 244 /*-----------------------------------------------------------------------
244 * Cache Configuration 245 * Cache Configuration
245 */ 246 */
246 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 247 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
247 #if defined(CONFIG_CMD_KGDB) 248 #if defined(CONFIG_CMD_KGDB)
248 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 249 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
249 #endif 250 #endif
250 251
251 /*----------------------------------------------------------------------- 252 /*-----------------------------------------------------------------------
252 * SYPCR - System Protection Control 11-9 253 * SYPCR - System Protection Control 11-9
253 * SYPCR can only be written once after reset! 254 * SYPCR can only be written once after reset!
254 *----------------------------------------------------------------------- 255 *-----------------------------------------------------------------------
255 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 256 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
256 */ 257 */
257 #if defined(CONFIG_WATCHDOG) 258 #if defined(CONFIG_WATCHDOG)
258 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 259 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
259 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 260 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
260 #else 261 #else
261 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 262 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
262 #endif 263 #endif
263 264
264 /*----------------------------------------------------------------------- 265 /*-----------------------------------------------------------------------
265 * SIUMCR - SIU Module Configuration 11-6 266 * SIUMCR - SIU Module Configuration 11-6
266 *----------------------------------------------------------------------- 267 *-----------------------------------------------------------------------
267 * PCMCIA config., multi-function pin tri-state 268 * PCMCIA config., multi-function pin tri-state
268 */ 269 */
269 #ifndef CONFIG_CAN_DRIVER 270 #ifndef CONFIG_CAN_DRIVER
270 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 271 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
271 #else /* we must activate GPL5 in the SIUMCR for CAN */ 272 #else /* we must activate GPL5 in the SIUMCR for CAN */
272 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 273 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
273 #endif /* CONFIG_CAN_DRIVER */ 274 #endif /* CONFIG_CAN_DRIVER */
274 275
275 /*----------------------------------------------------------------------- 276 /*-----------------------------------------------------------------------
276 * TBSCR - Time Base Status and Control 11-26 277 * TBSCR - Time Base Status and Control 11-26
277 *----------------------------------------------------------------------- 278 *-----------------------------------------------------------------------
278 * Clear Reference Interrupt Status, Timebase freezing enabled 279 * Clear Reference Interrupt Status, Timebase freezing enabled
279 */ 280 */
280 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 281 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
281 282
282 /*----------------------------------------------------------------------- 283 /*-----------------------------------------------------------------------
283 * RTCSC - Real-Time Clock Status and Control Register 11-27 284 * RTCSC - Real-Time Clock Status and Control Register 11-27
284 *----------------------------------------------------------------------- 285 *-----------------------------------------------------------------------
285 */ 286 */
286 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 287 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
287 288
288 /*----------------------------------------------------------------------- 289 /*-----------------------------------------------------------------------
289 * PISCR - Periodic Interrupt Status and Control 11-31 290 * PISCR - Periodic Interrupt Status and Control 11-31
290 *----------------------------------------------------------------------- 291 *-----------------------------------------------------------------------
291 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 292 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
292 */ 293 */
293 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 294 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
294 295
295 /*----------------------------------------------------------------------- 296 /*-----------------------------------------------------------------------
296 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 297 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
297 *----------------------------------------------------------------------- 298 *-----------------------------------------------------------------------
298 * Reset PLL lock status sticky bit, timer expired status bit and timer 299 * Reset PLL lock status sticky bit, timer expired status bit and timer
299 * interrupt status bit 300 * interrupt status bit
300 */ 301 */
301 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 302 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
302 303
303 /*----------------------------------------------------------------------- 304 /*-----------------------------------------------------------------------
304 * SCCR - System Clock and reset Control Register 15-27 305 * SCCR - System Clock and reset Control Register 15-27
305 *----------------------------------------------------------------------- 306 *-----------------------------------------------------------------------
306 * Set clock output, timebase and RTC source and divider, 307 * Set clock output, timebase and RTC source and divider,
307 * power management and some other internal clocks 308 * power management and some other internal clocks
308 */ 309 */
309 #define SCCR_MASK SCCR_EBDF11 310 #define SCCR_MASK SCCR_EBDF11
310 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 311 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
311 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 312 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
312 SCCR_DFALCD00) 313 SCCR_DFALCD00)
313 314
314 /*----------------------------------------------------------------------- 315 /*-----------------------------------------------------------------------
315 * PCMCIA stuff 316 * PCMCIA stuff
316 *----------------------------------------------------------------------- 317 *-----------------------------------------------------------------------
317 * 318 *
318 */ 319 */
319 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 320 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
320 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 321 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
321 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 322 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
322 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 323 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
323 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 324 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
324 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 325 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
325 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 326 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
326 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 327 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
327 328
328 /*----------------------------------------------------------------------- 329 /*-----------------------------------------------------------------------
329 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 330 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
330 *----------------------------------------------------------------------- 331 *-----------------------------------------------------------------------
331 */ 332 */
332 333
333 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 334 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
334 335
335 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 336 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
336 #undef CONFIG_IDE_LED /* LED for ide not supported */ 337 #undef CONFIG_IDE_LED /* LED for ide not supported */
337 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 338 #undef CONFIG_IDE_RESET /* reset for ide not supported */
338 339
339 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 340 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
340 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 341 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
341 342
342 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 343 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
343 344
344 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 345 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
345 346
346 /* Offset for data I/O */ 347 /* Offset for data I/O */
347 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 348 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
348 349
349 /* Offset for normal register accesses */ 350 /* Offset for normal register accesses */
350 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 351 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
351 352
352 /* Offset for alternate registers */ 353 /* Offset for alternate registers */
353 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 354 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
354 355
355 /*----------------------------------------------------------------------- 356 /*-----------------------------------------------------------------------
356 * 357 *
357 *----------------------------------------------------------------------- 358 *-----------------------------------------------------------------------
358 * 359 *
359 */ 360 */
360 #define CONFIG_SYS_DER 0 361 #define CONFIG_SYS_DER 0
361 362
362 /* 363 /*
363 * Init Memory Controller: 364 * Init Memory Controller:
364 * 365 *
365 * BR0/1 and OR0/1 (FLASH) 366 * BR0/1 and OR0/1 (FLASH)
366 */ 367 */
367 368
368 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 369 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
369 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ 370 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
370 371
371 /* used to re-map FLASH both when starting from SRAM or FLASH: 372 /* used to re-map FLASH both when starting from SRAM or FLASH:
372 * restrict access enough to keep SRAM working (if any) 373 * restrict access enough to keep SRAM working (if any)
373 * but not too much to meddle with FLASH accesses 374 * but not too much to meddle with FLASH accesses
374 */ 375 */
375 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 376 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
376 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 377 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
377 378
378 /* 379 /*
379 * FLASH timing: 380 * FLASH timing:
380 */ 381 */
381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 382 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
382 OR_SCY_3_CLK | OR_EHTR | OR_BI) 383 OR_SCY_3_CLK | OR_EHTR | OR_BI)
383 384
384 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 385 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
385 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 386 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
386 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 387 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
387 388
388 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 389 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
389 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 390 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
390 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 391 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
391 392
392 /* 393 /*
393 * BR2/3 and OR2/3 (SDRAM) 394 * BR2/3 and OR2/3 (SDRAM)
394 * 395 *
395 */ 396 */
396 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 397 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
397 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 398 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
398 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 399 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
399 400
400 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 401 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
401 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 402 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
402 403
403 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 404 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
404 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 405 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
405 406
406 #ifndef CONFIG_CAN_DRIVER 407 #ifndef CONFIG_CAN_DRIVER
407 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 408 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
408 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 409 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
409 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 410 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
410 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 411 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
411 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 412 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
412 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 413 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
413 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 414 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
414 BR_PS_8 | BR_MS_UPMB | BR_V ) 415 BR_PS_8 | BR_MS_UPMB | BR_V )
415 #endif /* CONFIG_CAN_DRIVER */ 416 #endif /* CONFIG_CAN_DRIVER */
416 417
417 /* 418 /*
418 * Memory Periodic Timer Prescaler 419 * Memory Periodic Timer Prescaler
419 * 420 *
420 * The Divider for PTA (refresh timer) configuration is based on an 421 * The Divider for PTA (refresh timer) configuration is based on an
421 * example SDRAM configuration (64 MBit, one bank). The adjustment to 422 * example SDRAM configuration (64 MBit, one bank). The adjustment to
422 * the number of chip selects (NCS) and the actually needed refresh 423 * the number of chip selects (NCS) and the actually needed refresh
423 * rate is done by setting MPTPR. 424 * rate is done by setting MPTPR.
424 * 425 *
425 * PTA is calculated from 426 * PTA is calculated from
426 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 427 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
427 * 428 *
428 * gclk CPU clock (not bus clock!) 429 * gclk CPU clock (not bus clock!)
429 * Trefresh Refresh cycle * 4 (four word bursts used) 430 * Trefresh Refresh cycle * 4 (four word bursts used)
430 * 431 *
431 * 4096 Rows from SDRAM example configuration 432 * 4096 Rows from SDRAM example configuration
432 * 1000 factor s -> ms 433 * 1000 factor s -> ms
433 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 434 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
434 * 4 Number of refresh cycles per period 435 * 4 Number of refresh cycles per period
435 * 64 Refresh cycle in ms per number of rows 436 * 64 Refresh cycle in ms per number of rows
436 * -------------------------------------------- 437 * --------------------------------------------
437 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 438 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
438 * 439 *
439 * 50 MHz => 50.000.000 / Divider = 98 440 * 50 MHz => 50.000.000 / Divider = 98
440 * 66 Mhz => 66.000.000 / Divider = 129 441 * 66 Mhz => 66.000.000 / Divider = 129
441 * 80 Mhz => 80.000.000 / Divider = 156 442 * 80 Mhz => 80.000.000 / Divider = 156
442 * 100 Mhz => 100.000.000 / Divider = 195 443 * 100 Mhz => 100.000.000 / Divider = 195
443 */ 444 */
444 445
445 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 446 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
446 #define CONFIG_SYS_MAMR_PTA 98 447 #define CONFIG_SYS_MAMR_PTA 98
447 448
448 /* 449 /*
449 * For 16 MBit, refresh rates could be 31.3 us 450 * For 16 MBit, refresh rates could be 31.3 us
450 * (= 64 ms / 2K = 125 / quad bursts). 451 * (= 64 ms / 2K = 125 / quad bursts).
451 * For a simpler initialization, 15.6 us is used instead. 452 * For a simpler initialization, 15.6 us is used instead.
452 * 453 *
453 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 454 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
454 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 455 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
455 */ 456 */
456 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 457 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
457 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 458 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
458 459
459 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 460 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
460 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 461 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
461 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 462 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
462 463
463 /* 464 /*
464 * MAMR settings for SDRAM 465 * MAMR settings for SDRAM
465 */ 466 */
466 467
467 /* 8 column SDRAM */ 468 /* 8 column SDRAM */
468 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 469 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
469 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 470 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
471 /* 9 column SDRAM */ 472 /* 9 column SDRAM */
472 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 473 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
473 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 474 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
474 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
475 476
476 477
477 /* 478 /*
478 * Internal Definitions 479 * Internal Definitions
479 * 480 *
480 * Boot Flags 481 * Boot Flags
481 */ 482 */
482 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 483 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
483 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 484 #define BOOTFLAG_WARM 0x02 /* Software reboot */
484 485
485 #define CONFIG_NET_MULTI 486 #define CONFIG_NET_MULTI
486 #define CONFIG_SCC1_ENET 487 #define CONFIG_SCC1_ENET
487 #define CONFIG_FEC_ENET 488 #define CONFIG_FEC_ENET
488 #define CONFIG_ETHPRIME "SCC ETHERNET" 489 #define CONFIG_ETHPRIME "SCC ETHERNET"
489 490
490 #endif /* __CONFIG_H */ 491 #endif /* __CONFIG_H */
491 492
include/configs/TQM866M.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2008 2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ 36 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37 #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ 37 #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
38 38
39 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ 39 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
40 #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ 40 #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
41 #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ 41 #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
42 #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ 42 #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
43 /* (it will be used if there is no */ 43 /* (it will be used if there is no */
44 /* 'cpuclk' variable with valid value) */ 44 /* 'cpuclk' variable with valid value) */
45 45
46 #undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ 46 #undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */
47 /* (function measure_gclk() */ 47 /* (function measure_gclk() */
48 /* will be called) */ 48 /* will be called) */
49 #ifdef CONFIG_SYS_MEASURE_CPUCLK 49 #ifdef CONFIG_SYS_MEASURE_CPUCLK
50 #define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ 50 #define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */
51 #endif 51 #endif
52 52
53 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 53 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
54 54
55 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 55 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
56 56
57 #define CONFIG_BOOTCOUNT_LIMIT 57 #define CONFIG_BOOTCOUNT_LIMIT
58 58
59 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 59 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60 60
61 #define CONFIG_BOARD_TYPES 1 /* support board types */ 61 #define CONFIG_BOARD_TYPES 1 /* support board types */
62 62
63 #define CONFIG_PREBOOT "echo;" \ 63 #define CONFIG_PREBOOT "echo;" \
64 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 64 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
65 "echo" 65 "echo"
66 66
67 #undef CONFIG_BOOTARGS 67 #undef CONFIG_BOOTARGS
68 68
69 #define CONFIG_EXTRA_ENV_SETTINGS \ 69 #define CONFIG_EXTRA_ENV_SETTINGS \
70 "netdev=eth0\0" \ 70 "netdev=eth0\0" \
71 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 71 "nfsargs=setenv bootargs root=/dev/nfs rw " \
72 "nfsroot=${serverip}:${rootpath}\0" \ 72 "nfsroot=${serverip}:${rootpath}\0" \
73 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 73 "ramargs=setenv bootargs root=/dev/ram rw\0" \
74 "addip=setenv bootargs ${bootargs} " \ 74 "addip=setenv bootargs ${bootargs} " \
75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
76 ":${hostname}:${netdev}:off panic=1\0" \ 76 ":${hostname}:${netdev}:off panic=1\0" \
77 "flash_nfs=run nfsargs addip;" \ 77 "flash_nfs=run nfsargs addip;" \
78 "bootm ${kernel_addr}\0" \ 78 "bootm ${kernel_addr}\0" \
79 "flash_self=run ramargs addip;" \ 79 "flash_self=run ramargs addip;" \
80 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 80 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
82 "rootpath=/opt/eldk/ppc_8xx\0" \ 82 "rootpath=/opt/eldk/ppc_8xx\0" \
83 "hostname=TQM866M\0" \ 83 "hostname=TQM866M\0" \
84 "bootfile=TQM866M/uImage\0" \ 84 "bootfile=TQM866M/uImage\0" \
85 "fdt_addr=400C0000\0" \ 85 "fdt_addr=400C0000\0" \
86 "kernel_addr=40100000\0" \ 86 "kernel_addr=40100000\0" \
87 "ramdisk_addr=40280000\0" \ 87 "ramdisk_addr=40280000\0" \
88 "u-boot=TQM866M/u-image.bin\0" \ 88 "u-boot=TQM866M/u-image.bin\0" \
89 "load=tftp 200000 ${u-boot}\0" \ 89 "load=tftp 200000 ${u-boot}\0" \
90 "update=prot off 40000000 +${filesize};" \ 90 "update=prot off 40000000 +${filesize};" \
91 "era 40000000 +${filesize};" \ 91 "era 40000000 +${filesize};" \
92 "cp.b 200000 40000000 ${filesize};" \ 92 "cp.b 200000 40000000 ${filesize};" \
93 "sete filesize;save\0" \ 93 "sete filesize;save\0" \
94 "" 94 ""
95 #define CONFIG_BOOTCOMMAND "run flash_self" 95 #define CONFIG_BOOTCOMMAND "run flash_self"
96 96
97 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 97 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
98 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 98 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
99 99
100 #undef CONFIG_WATCHDOG /* watchdog disabled */ 100 #undef CONFIG_WATCHDOG /* watchdog disabled */
101 101
102 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 102 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
103 103
104 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 104 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
105 105
106 /* enable I2C and select the hardware/software driver */ 106 /* enable I2C and select the hardware/software driver */
107 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 107 #undef CONFIG_HARD_I2C /* I2C with hardware support */
108 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 108 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
109 109
110 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ 110 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
111 #define CONFIG_SYS_I2C_SLAVE 0xFE 111 #define CONFIG_SYS_I2C_SLAVE 0xFE
112 112
113 #ifdef CONFIG_SOFT_I2C 113 #ifdef CONFIG_SOFT_I2C
114 /* 114 /*
115 * Software (bit-bang) I2C driver configuration 115 * Software (bit-bang) I2C driver configuration
116 */ 116 */
117 #define PB_SCL 0x00000020 /* PB 26 */ 117 #define PB_SCL 0x00000020 /* PB 26 */
118 #define PB_SDA 0x00000010 /* PB 27 */ 118 #define PB_SDA 0x00000010 /* PB 27 */
119 119
120 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 120 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
121 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 121 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
122 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 122 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
123 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 123 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
124 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 124 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
125 else immr->im_cpm.cp_pbdat &= ~PB_SDA 125 else immr->im_cpm.cp_pbdat &= ~PB_SDA
126 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 126 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
127 else immr->im_cpm.cp_pbdat &= ~PB_SCL 127 else immr->im_cpm.cp_pbdat &= ~PB_SCL
128 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 128 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
129 #endif /* CONFIG_SOFT_I2C */ 129 #endif /* CONFIG_SOFT_I2C */
130 130
131 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ 131 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
135 135
136 /* 136 /*
137 * BOOTP options 137 * BOOTP options
138 */ 138 */
139 #define CONFIG_BOOTP_SUBNETMASK 139 #define CONFIG_BOOTP_SUBNETMASK
140 #define CONFIG_BOOTP_GATEWAY 140 #define CONFIG_BOOTP_GATEWAY
141 #define CONFIG_BOOTP_HOSTNAME 141 #define CONFIG_BOOTP_HOSTNAME
142 #define CONFIG_BOOTP_BOOTPATH 142 #define CONFIG_BOOTP_BOOTPATH
143 #define CONFIG_BOOTP_BOOTFILESIZE 143 #define CONFIG_BOOTP_BOOTFILESIZE
144 144
145 145
146 #define CONFIG_MAC_PARTITION 146 #define CONFIG_MAC_PARTITION
147 #define CONFIG_DOS_PARTITION 147 #define CONFIG_DOS_PARTITION
148 148
149 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ 149 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
150 150
151 #define CONFIG_TIMESTAMP /* but print image timestmps */ 151 #define CONFIG_TIMESTAMP /* but print image timestmps */
152 152
153 153
154 /* 154 /*
155 * Command line configuration. 155 * Command line configuration.
156 */ 156 */
157 #include <config_cmd_default.h> 157 #include <config_cmd_default.h>
158 158
159 #define CONFIG_CMD_ASKENV 159 #define CONFIG_CMD_ASKENV
160 #define CONFIG_CMD_DHCP 160 #define CONFIG_CMD_DHCP
161 #define CONFIG_CMD_EEPROM 161 #define CONFIG_CMD_EEPROM
162 #define CONFIG_CMD_ELF 162 #define CONFIG_CMD_ELF
163 #define CONFIG_CMD_EXT2
163 #define CONFIG_CMD_IDE 164 #define CONFIG_CMD_IDE
164 #define CONFIG_CMD_JFFS2 165 #define CONFIG_CMD_JFFS2
165 #define CONFIG_CMD_NFS 166 #define CONFIG_CMD_NFS
166 #define CONFIG_CMD_SNTP 167 #define CONFIG_CMD_SNTP
167 168
168 169
169 #define CONFIG_NETCONSOLE 170 #define CONFIG_NETCONSOLE
170 171
171 172
172 /* 173 /*
173 * Miscellaneous configurable options 174 * Miscellaneous configurable options
174 */ 175 */
175 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 176 #define CONFIG_SYS_LONGHELP /* undef to save memory */
176 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 177 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
177 178
178 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 179 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
179 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 180 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
180 #ifdef CONFIG_SYS_HUSH_PARSER 181 #ifdef CONFIG_SYS_HUSH_PARSER
181 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 182 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
182 #endif 183 #endif
183 184
184 #if defined(CONFIG_CMD_KGDB) 185 #if defined(CONFIG_CMD_KGDB)
185 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 186 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
186 #else 187 #else
187 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 188 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
188 #endif 189 #endif
189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 190 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
190 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 191 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
191 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 192 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
192 193
193 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 194 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
194 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 195 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
195 196
196 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 197 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
197 198
198 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 199 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
199 200
200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 201 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
201 202
202 /* 203 /*
203 * Low Level Configuration Settings 204 * Low Level Configuration Settings
204 * (address mappings, register initial values, etc.) 205 * (address mappings, register initial values, etc.)
205 * You should know what you are doing if you make changes here. 206 * You should know what you are doing if you make changes here.
206 */ 207 */
207 /*----------------------------------------------------------------------- 208 /*-----------------------------------------------------------------------
208 * Internal Memory Mapped Register 209 * Internal Memory Mapped Register
209 */ 210 */
210 #define CONFIG_SYS_IMMR 0xFFF00000 211 #define CONFIG_SYS_IMMR 0xFFF00000
211 212
212 /*----------------------------------------------------------------------- 213 /*-----------------------------------------------------------------------
213 * Definitions for initial stack pointer and data area (in DPRAM) 214 * Definitions for initial stack pointer and data area (in DPRAM)
214 */ 215 */
215 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 216 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
216 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 217 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
217 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 218 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
218 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 219 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
219 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 220 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
220 221
221 /*----------------------------------------------------------------------- 222 /*-----------------------------------------------------------------------
222 * Start addresses for the final memory configuration 223 * Start addresses for the final memory configuration
223 * (Set up by the startup code) 224 * (Set up by the startup code)
224 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 225 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
225 */ 226 */
226 #define CONFIG_SYS_SDRAM_BASE 0x00000000 227 #define CONFIG_SYS_SDRAM_BASE 0x00000000
227 #define CONFIG_SYS_FLASH_BASE 0x40000000 228 #define CONFIG_SYS_FLASH_BASE 0x40000000
228 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 229 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 230 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
230 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ 231 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
231 232
232 /* 233 /*
233 * For booting Linux, the board info and command line data 234 * For booting Linux, the board info and command line data
234 * have to be in the first 8 MB of memory, since this is 235 * have to be in the first 8 MB of memory, since this is
235 * the maximum mapped by the Linux kernel during initialization. 236 * the maximum mapped by the Linux kernel during initialization.
236 */ 237 */
237 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 238 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
238 239
239 /*----------------------------------------------------------------------- 240 /*-----------------------------------------------------------------------
240 * FLASH organization 241 * FLASH organization
241 */ 242 */
242 /* use CFI flash driver */ 243 /* use CFI flash driver */
243 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 244 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
244 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 245 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
245 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 246 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
246 #define CONFIG_SYS_FLASH_EMPTY_INFO 247 #define CONFIG_SYS_FLASH_EMPTY_INFO
247 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 248 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
248 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 249 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
249 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 250 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
250 251
251 #define CONFIG_ENV_IS_IN_FLASH 1 252 #define CONFIG_ENV_IS_IN_FLASH 1
252 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 253 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
253 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ 254 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
254 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 255 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
255 256
256 /* Address and size of Redundant Environment Sector */ 257 /* Address and size of Redundant Environment Sector */
257 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 258 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
258 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 259 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
259 260
260 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 261 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
261 262
262 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 263 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
263 264
264 /*----------------------------------------------------------------------- 265 /*-----------------------------------------------------------------------
265 * Dynamic MTD partition support 266 * Dynamic MTD partition support
266 */ 267 */
267 #define CONFIG_JFFS2_CMDLINE 268 #define CONFIG_JFFS2_CMDLINE
268 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 269 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
269 270
270 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 271 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
271 "128k(dtb)," \ 272 "128k(dtb)," \
272 "1920k(kernel)," \ 273 "1920k(kernel)," \
273 "5632(rootfs)," \ 274 "5632(rootfs)," \
274 "4m(data)" 275 "4m(data)"
275 276
276 /*----------------------------------------------------------------------- 277 /*-----------------------------------------------------------------------
277 * Hardware Information Block 278 * Hardware Information Block
278 */ 279 */
279 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 280 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
280 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 281 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
281 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 282 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
282 283
283 /*----------------------------------------------------------------------- 284 /*-----------------------------------------------------------------------
284 * Cache Configuration 285 * Cache Configuration
285 */ 286 */
286 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 287 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
287 #if defined(CONFIG_CMD_KGDB) 288 #if defined(CONFIG_CMD_KGDB)
288 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 289 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
289 #endif 290 #endif
290 291
291 /*----------------------------------------------------------------------- 292 /*-----------------------------------------------------------------------
292 * SYPCR - System Protection Control 11-9 293 * SYPCR - System Protection Control 11-9
293 * SYPCR can only be written once after reset! 294 * SYPCR can only be written once after reset!
294 *----------------------------------------------------------------------- 295 *-----------------------------------------------------------------------
295 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 296 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
296 */ 297 */
297 #if defined(CONFIG_WATCHDOG) 298 #if defined(CONFIG_WATCHDOG)
298 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 299 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
299 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 300 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
300 #else 301 #else
301 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 302 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
302 #endif 303 #endif
303 304
304 /*----------------------------------------------------------------------- 305 /*-----------------------------------------------------------------------
305 * SIUMCR - SIU Module Configuration 11-6 306 * SIUMCR - SIU Module Configuration 11-6
306 *----------------------------------------------------------------------- 307 *-----------------------------------------------------------------------
307 * PCMCIA config., multi-function pin tri-state 308 * PCMCIA config., multi-function pin tri-state
308 */ 309 */
309 #ifndef CONFIG_CAN_DRIVER 310 #ifndef CONFIG_CAN_DRIVER
310 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 311 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
311 #else /* we must activate GPL5 in the SIUMCR for CAN */ 312 #else /* we must activate GPL5 in the SIUMCR for CAN */
312 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 313 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
313 #endif /* CONFIG_CAN_DRIVER */ 314 #endif /* CONFIG_CAN_DRIVER */
314 315
315 /*----------------------------------------------------------------------- 316 /*-----------------------------------------------------------------------
316 * TBSCR - Time Base Status and Control 11-26 317 * TBSCR - Time Base Status and Control 11-26
317 *----------------------------------------------------------------------- 318 *-----------------------------------------------------------------------
318 * Clear Reference Interrupt Status, Timebase freezing enabled 319 * Clear Reference Interrupt Status, Timebase freezing enabled
319 */ 320 */
320 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 321 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
321 322
322 /*----------------------------------------------------------------------- 323 /*-----------------------------------------------------------------------
323 * PISCR - Periodic Interrupt Status and Control 11-31 324 * PISCR - Periodic Interrupt Status and Control 11-31
324 *----------------------------------------------------------------------- 325 *-----------------------------------------------------------------------
325 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 326 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
326 */ 327 */
327 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 328 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
328 329
329 /*----------------------------------------------------------------------- 330 /*-----------------------------------------------------------------------
330 * SCCR - System Clock and reset Control Register 15-27 331 * SCCR - System Clock and reset Control Register 15-27
331 *----------------------------------------------------------------------- 332 *-----------------------------------------------------------------------
332 * Set clock output, timebase and RTC source and divider, 333 * Set clock output, timebase and RTC source and divider,
333 * power management and some other internal clocks 334 * power management and some other internal clocks
334 */ 335 */
335 #define SCCR_MASK SCCR_EBDF11 336 #define SCCR_MASK SCCR_EBDF11
336 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 337 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
337 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 338 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
338 SCCR_DFALCD00) 339 SCCR_DFALCD00)
339 340
340 /*----------------------------------------------------------------------- 341 /*-----------------------------------------------------------------------
341 * PCMCIA stuff 342 * PCMCIA stuff
342 *----------------------------------------------------------------------- 343 *-----------------------------------------------------------------------
343 * 344 *
344 */ 345 */
345 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 346 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
346 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 347 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
347 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 348 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
348 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 349 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
349 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 350 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
350 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 351 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
351 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 352 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
352 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 353 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
353 354
354 /*----------------------------------------------------------------------- 355 /*-----------------------------------------------------------------------
355 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 356 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
356 *----------------------------------------------------------------------- 357 *-----------------------------------------------------------------------
357 */ 358 */
358 359
359 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 360 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
360 361
361 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 362 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
362 #undef CONFIG_IDE_LED /* LED for ide not supported */ 363 #undef CONFIG_IDE_LED /* LED for ide not supported */
363 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 364 #undef CONFIG_IDE_RESET /* reset for ide not supported */
364 365
365 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 366 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
366 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 367 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
367 368
368 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 369 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
369 370
370 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 371 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
371 372
372 /* Offset for data I/O */ 373 /* Offset for data I/O */
373 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 374 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
374 375
375 /* Offset for normal register accesses */ 376 /* Offset for normal register accesses */
376 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 377 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
377 378
378 /* Offset for alternate registers */ 379 /* Offset for alternate registers */
379 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 380 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
380 381
381 /*----------------------------------------------------------------------- 382 /*-----------------------------------------------------------------------
382 * 383 *
383 *----------------------------------------------------------------------- 384 *-----------------------------------------------------------------------
384 * 385 *
385 */ 386 */
386 #define CONFIG_SYS_DER 0 387 #define CONFIG_SYS_DER 0
387 388
388 /* 389 /*
389 * Init Memory Controller: 390 * Init Memory Controller:
390 * 391 *
391 * BR0/1 and OR0/1 (FLASH) 392 * BR0/1 and OR0/1 (FLASH)
392 */ 393 */
393 394
394 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 395 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
395 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 396 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
396 397
397 /* used to re-map FLASH both when starting from SRAM or FLASH: 398 /* used to re-map FLASH both when starting from SRAM or FLASH:
398 * restrict access enough to keep SRAM working (if any) 399 * restrict access enough to keep SRAM working (if any)
399 * but not too much to meddle with FLASH accesses 400 * but not too much to meddle with FLASH accesses
400 */ 401 */
401 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 402 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
402 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 403 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
403 404
404 /* 405 /*
405 * FLASH timing: Default value of OR0 after reset 406 * FLASH timing: Default value of OR0 after reset
406 */ 407 */
407 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ 408 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
408 OR_SCY_15_CLK | OR_TRLX) 409 OR_SCY_15_CLK | OR_TRLX)
409 410
410 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 411 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
411 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 412 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
412 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 413 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
413 414
414 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 415 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
415 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 416 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
416 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 417 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
417 418
418 /* 419 /*
419 * BR2/3 and OR2/3 (SDRAM) 420 * BR2/3 and OR2/3 (SDRAM)
420 * 421 *
421 */ 422 */
422 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 423 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
423 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 424 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
424 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ 425 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
425 426
426 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 427 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
427 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 428 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
428 429
429 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 430 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
430 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 431 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
431 432
432 #ifndef CONFIG_CAN_DRIVER 433 #ifndef CONFIG_CAN_DRIVER
433 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 434 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
434 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 435 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
435 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 436 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
436 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 437 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
437 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 438 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
438 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 439 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
439 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 440 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
440 BR_PS_8 | BR_MS_UPMB | BR_V ) 441 BR_PS_8 | BR_MS_UPMB | BR_V )
441 #endif /* CONFIG_CAN_DRIVER */ 442 #endif /* CONFIG_CAN_DRIVER */
442 443
443 /* 444 /*
444 * 4096 Rows from SDRAM example configuration 445 * 4096 Rows from SDRAM example configuration
445 * 1000 factor s -> ms 446 * 1000 factor s -> ms
446 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration 447 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
447 * 4 Number of refresh cycles per period 448 * 4 Number of refresh cycles per period
448 * 64 Refresh cycle in ms per number of rows 449 * 64 Refresh cycle in ms per number of rows
449 */ 450 */
450 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) 451 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
451 452
452 /* 453 /*
453 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) 454 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
454 * 455 *
455 * CPUclock(MHz) * 31.2 456 * CPUclock(MHz) * 31.2
456 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 457 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
457 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 458 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
458 * 459 *
459 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us 460 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
460 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us 461 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
461 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us 462 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
462 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us 463 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
463 * 464 *
464 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will 465 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
465 * be met also in the default configuration, i.e. if environment variable 466 * be met also in the default configuration, i.e. if environment variable
466 * 'cpuclk' is not set. 467 * 'cpuclk' is not set.
467 */ 468 */
468 #define CONFIG_SYS_MAMR_PTA 97 469 #define CONFIG_SYS_MAMR_PTA 97
469 470
470 /* 471 /*
471 * Memory Periodic Timer Prescaler Register (MPTPR) values. 472 * Memory Periodic Timer Prescaler Register (MPTPR) values.
472 */ 473 */
473 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ 474 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
474 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 475 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
475 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ 476 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
476 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 477 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
477 478
478 /* 479 /*
479 * MAMR settings for SDRAM 480 * MAMR settings for SDRAM
480 */ 481 */
481 482
482 /* 8 column SDRAM */ 483 /* 8 column SDRAM */
483 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 484 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
484 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 485 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
485 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 486 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
486 /* 9 column SDRAM */ 487 /* 9 column SDRAM */
487 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 488 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
488 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 489 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
489 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 490 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
490 /* 10 column SDRAM */ 491 /* 10 column SDRAM */
491 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 492 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
492 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 493 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
493 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 494 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
494 495
495 /* 496 /*
496 * Internal Definitions 497 * Internal Definitions
497 * 498 *
498 * Boot Flags 499 * Boot Flags
499 */ 500 */
500 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 501 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
501 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 502 #define BOOTFLAG_WARM 0x02 /* Software reboot */
502 503
503 #define CONFIG_SCC1_ENET 504 #define CONFIG_SCC1_ENET
504 #define CONFIG_FEC_ENET 505 #define CONFIG_FEC_ENET
505 #define CONFIG_ETHPRIME "SCC ETHERNET" 506 #define CONFIG_ETHPRIME "SCC ETHERNET"
506 507
507 #endif /* __CONFIG_H */ 508 #endif /* __CONFIG_H */
508 509
include/configs/TQM885D.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2000-2005 2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * (C) Copyright 2006 5 * (C) Copyright 2006
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de 6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
7 * 7 *
8 * See file CREDITS for list of people who contributed to this 8 * See file CREDITS for list of people who contributed to this
9 * project. 9 * project.
10 * 10 *
11 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of 13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version. 14 * the License, or (at your option) any later version.
15 * 15 *
16 * This program is distributed in the hope that it will be useful, 16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public License 21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software 22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA 24 * MA 02111-1307 USA
25 */ 25 */
26 26
27 /* 27 /*
28 * board/config.h - configuration options, board specific 28 * board/config.h - configuration options, board specific
29 */ 29 */
30 30
31 #ifndef __CONFIG_H 31 #ifndef __CONFIG_H
32 #define __CONFIG_H 32 #define __CONFIG_H
33 33
34 /* 34 /*
35 * High Level Configuration Options 35 * High Level Configuration Options
36 * (easy to change) 36 * (easy to change)
37 */ 37 */
38 38
39 #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ 39 #define CONFIG_MPC885 1 /* This is a MPC885 CPU */
40 #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ 40 #define CONFIG_TQM885D 1 /* ...on a TQM88D module */
41 41
42 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ 42 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
43 #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ 43 #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
44 #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ 44 #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
45 #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ 45 #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
46 /* (it will be used if there is no */ 46 /* (it will be used if there is no */
47 /* 'cpuclk' variable with valid value) */ 47 /* 'cpuclk' variable with valid value) */
48 48
49 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 49 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
50 50
51 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 51 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
52 52
53 #define CONFIG_BOOTCOUNT_LIMIT 53 #define CONFIG_BOOTCOUNT_LIMIT
54 54
55 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 55 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56 56
57 #define CONFIG_BOARD_TYPES 1 /* support board types */ 57 #define CONFIG_BOARD_TYPES 1 /* support board types */
58 58
59 #define CONFIG_PREBOOT "echo;" \ 59 #define CONFIG_PREBOOT "echo;" \
60 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 60 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
61 "echo" 61 "echo"
62 62
63 #undef CONFIG_BOOTARGS 63 #undef CONFIG_BOOTARGS
64 64
65 #define CONFIG_EXTRA_ENV_SETTINGS \ 65 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "netdev=eth0\0" \ 66 "netdev=eth0\0" \
67 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 67 "nfsargs=setenv bootargs root=/dev/nfs rw " \
68 "nfsroot=${serverip}:${rootpath}\0" \ 68 "nfsroot=${serverip}:${rootpath}\0" \
69 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 69 "ramargs=setenv bootargs root=/dev/ram rw\0" \
70 "addip=setenv bootargs ${bootargs} " \ 70 "addip=setenv bootargs ${bootargs} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
72 ":${hostname}:${netdev}:off panic=1\0" \ 72 ":${hostname}:${netdev}:off panic=1\0" \
73 "flash_nfs=run nfsargs addip;" \ 73 "flash_nfs=run nfsargs addip;" \
74 "bootm ${kernel_addr}\0" \ 74 "bootm ${kernel_addr}\0" \
75 "flash_self=run ramargs addip;" \ 75 "flash_self=run ramargs addip;" \
76 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 76 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
77 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 77 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
78 "rootpath=/opt/eldk/ppc_8xx\0" \ 78 "rootpath=/opt/eldk/ppc_8xx\0" \
79 "bootfile=/tftpboot/TQM885D/uImage\0" \ 79 "bootfile=/tftpboot/TQM885D/uImage\0" \
80 "fdt_addr=400C0000\0" \ 80 "fdt_addr=400C0000\0" \
81 "kernel_addr=40100000\0" \ 81 "kernel_addr=40100000\0" \
82 "ramdisk_addr=40280000\0" \ 82 "ramdisk_addr=40280000\0" \
83 "load=tftp 200000 ${u-boot}\0" \ 83 "load=tftp 200000 ${u-boot}\0" \
84 "update=protect off 40000000 +${filesize};" \ 84 "update=protect off 40000000 +${filesize};" \
85 "erase 40000000 +${filesize};" \ 85 "erase 40000000 +${filesize};" \
86 "cp.b 200000 40000000 ${filesize};" \ 86 "cp.b 200000 40000000 ${filesize};" \
87 "protect on 40000000 +${filesize}\0" \ 87 "protect on 40000000 +${filesize}\0" \
88 "" 88 ""
89 #define CONFIG_BOOTCOMMAND "run flash_self" 89 #define CONFIG_BOOTCOMMAND "run flash_self"
90 90
91 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 91 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
92 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 92 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
93 93
94 #undef CONFIG_WATCHDOG /* watchdog disabled */ 94 #undef CONFIG_WATCHDOG /* watchdog disabled */
95 95
96 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 96 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
97 97
98 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 98 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
99 99
100 /* enable I2C and select the hardware/software driver */ 100 /* enable I2C and select the hardware/software driver */
101 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 101 #undef CONFIG_HARD_I2C /* I2C with hardware support */
102 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 102 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
103 103
104 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ 104 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
105 #define CONFIG_SYS_I2C_SLAVE 0xFE 105 #define CONFIG_SYS_I2C_SLAVE 0xFE
106 106
107 #ifdef CONFIG_SOFT_I2C 107 #ifdef CONFIG_SOFT_I2C
108 /* 108 /*
109 * Software (bit-bang) I2C driver configuration 109 * Software (bit-bang) I2C driver configuration
110 */ 110 */
111 #define PB_SCL 0x00000020 /* PB 26 */ 111 #define PB_SCL 0x00000020 /* PB 26 */
112 #define PB_SDA 0x00000010 /* PB 27 */ 112 #define PB_SDA 0x00000010 /* PB 27 */
113 113
114 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 114 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
115 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 115 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
116 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 116 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
117 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 117 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
118 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 118 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
119 else immr->im_cpm.cp_pbdat &= ~PB_SDA 119 else immr->im_cpm.cp_pbdat &= ~PB_SDA
120 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 120 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
121 else immr->im_cpm.cp_pbdat &= ~PB_SCL 121 else immr->im_cpm.cp_pbdat &= ~PB_SCL
122 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 122 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
123 #endif /* CONFIG_SOFT_I2C */ 123 #endif /* CONFIG_SOFT_I2C */
124 124
125 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ 125 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
127 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 127 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
128 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 128 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
129 129
130 # define CONFIG_RTC_DS1337 1 130 # define CONFIG_RTC_DS1337 1
131 # define CONFIG_SYS_I2C_RTC_ADDR 0x68 131 # define CONFIG_SYS_I2C_RTC_ADDR 0x68
132 132
133 /* 133 /*
134 * BOOTP options 134 * BOOTP options
135 */ 135 */
136 #define CONFIG_BOOTP_SUBNETMASK 136 #define CONFIG_BOOTP_SUBNETMASK
137 #define CONFIG_BOOTP_GATEWAY 137 #define CONFIG_BOOTP_GATEWAY
138 #define CONFIG_BOOTP_HOSTNAME 138 #define CONFIG_BOOTP_HOSTNAME
139 #define CONFIG_BOOTP_BOOTPATH 139 #define CONFIG_BOOTP_BOOTPATH
140 #define CONFIG_BOOTP_BOOTFILESIZE 140 #define CONFIG_BOOTP_BOOTFILESIZE
141 141
142 142
143 #define CONFIG_MAC_PARTITION 143 #define CONFIG_MAC_PARTITION
144 #define CONFIG_DOS_PARTITION 144 #define CONFIG_DOS_PARTITION
145 145
146 #undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ 146 #undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
147 147
148 #define CONFIG_TIMESTAMP /* but print image timestmps */ 148 #define CONFIG_TIMESTAMP /* but print image timestmps */
149 149
150 150
151 /* 151 /*
152 * Command line configuration. 152 * Command line configuration.
153 */ 153 */
154 #include <config_cmd_default.h> 154 #include <config_cmd_default.h>
155 155
156 #define CONFIG_CMD_ASKENV 156 #define CONFIG_CMD_ASKENV
157 #define CONFIG_CMD_DATE 157 #define CONFIG_CMD_DATE
158 #define CONFIG_CMD_DHCP 158 #define CONFIG_CMD_DHCP
159 #define CONFIG_CMD_EEPROM 159 #define CONFIG_CMD_EEPROM
160 #define CONFIG_CMD_EXT2
160 #define CONFIG_CMD_I2C 161 #define CONFIG_CMD_I2C
161 #define CONFIG_CMD_IDE 162 #define CONFIG_CMD_IDE
162 #define CONFIG_CMD_MII 163 #define CONFIG_CMD_MII
163 #define CONFIG_CMD_NFS 164 #define CONFIG_CMD_NFS
164 #define CONFIG_CMD_PING 165 #define CONFIG_CMD_PING
165 166
166 167
167 /* 168 /*
168 * Miscellaneous configurable options 169 * Miscellaneous configurable options
169 */ 170 */
170 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 171 #define CONFIG_SYS_LONGHELP /* undef to save memory */
171 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 172 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
172 173
173 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 174 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
174 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 175 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
175 #ifdef CONFIG_SYS_HUSH_PARSER 176 #ifdef CONFIG_SYS_HUSH_PARSER
176 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 177 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
177 #endif 178 #endif
178 179
179 #if defined(CONFIG_CMD_KGDB) 180 #if defined(CONFIG_CMD_KGDB)
180 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 181 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
181 #else 182 #else
182 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 183 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
183 #endif 184 #endif
184 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 185 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
185 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 186 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
186 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 187 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
187 188
188 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 189 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
189 #define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ 190 #define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
190 #define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive 191 #define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
191 memory test.*/ 192 memory test.*/
192 193
193 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 194 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
194 195
195 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 196 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
196 197
197 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 198 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
198 199
199 /* 200 /*
200 * Enable loopw command. 201 * Enable loopw command.
201 */ 202 */
202 #define CONFIG_LOOPW 203 #define CONFIG_LOOPW
203 204
204 /* 205 /*
205 * Low Level Configuration Settings 206 * Low Level Configuration Settings
206 * (address mappings, register initial values, etc.) 207 * (address mappings, register initial values, etc.)
207 * You should know what you are doing if you make changes here. 208 * You should know what you are doing if you make changes here.
208 */ 209 */
209 /*----------------------------------------------------------------------- 210 /*-----------------------------------------------------------------------
210 * Internal Memory Mapped Register 211 * Internal Memory Mapped Register
211 */ 212 */
212 #define CONFIG_SYS_IMMR 0xFFF00000 213 #define CONFIG_SYS_IMMR 0xFFF00000
213 214
214 /*----------------------------------------------------------------------- 215 /*-----------------------------------------------------------------------
215 * Definitions for initial stack pointer and data area (in DPRAM) 216 * Definitions for initial stack pointer and data area (in DPRAM)
216 */ 217 */
217 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 218 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
218 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 219 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
219 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 220 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
220 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 221 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
221 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 222 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
222 223
223 /*----------------------------------------------------------------------- 224 /*-----------------------------------------------------------------------
224 * Start addresses for the final memory configuration 225 * Start addresses for the final memory configuration
225 * (Set up by the startup code) 226 * (Set up by the startup code)
226 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 227 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
227 */ 228 */
228 #define CONFIG_SYS_SDRAM_BASE 0x00000000 229 #define CONFIG_SYS_SDRAM_BASE 0x00000000
229 #define CONFIG_SYS_FLASH_BASE 0x40000000 230 #define CONFIG_SYS_FLASH_BASE 0x40000000
230 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 231 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
232 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ 233 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
233 234
234 /* 235 /*
235 * For booting Linux, the board info and command line data 236 * For booting Linux, the board info and command line data
236 * have to be in the first 8 MB of memory, since this is 237 * have to be in the first 8 MB of memory, since this is
237 * the maximum mapped by the Linux kernel during initialization. 238 * the maximum mapped by the Linux kernel during initialization.
238 */ 239 */
239 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 240 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
240 241
241 /*----------------------------------------------------------------------- 242 /*-----------------------------------------------------------------------
242 * FLASH organization 243 * FLASH organization
243 */ 244 */
244 245
245 /* use CFI flash driver */ 246 /* use CFI flash driver */
246 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 247 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
247 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 248 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
248 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 249 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
249 #define CONFIG_SYS_FLASH_EMPTY_INFO 250 #define CONFIG_SYS_FLASH_EMPTY_INFO
250 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 251 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 252 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
252 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 253 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
253 254
254 #define CONFIG_ENV_IS_IN_FLASH 1 255 #define CONFIG_ENV_IS_IN_FLASH 1
255 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 256 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
256 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 257 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
257 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 258 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
258 259
259 /* Address and size of Redundant Environment Sector */ 260 /* Address and size of Redundant Environment Sector */
260 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 261 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
261 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 262 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
262 263
263 /*----------------------------------------------------------------------- 264 /*-----------------------------------------------------------------------
264 * Hardware Information Block 265 * Hardware Information Block
265 */ 266 */
266 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 267 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
267 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 268 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
268 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 269 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
269 270
270 /*----------------------------------------------------------------------- 271 /*-----------------------------------------------------------------------
271 * Cache Configuration 272 * Cache Configuration
272 */ 273 */
273 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 274 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
274 #if defined(CONFIG_CMD_KGDB) 275 #if defined(CONFIG_CMD_KGDB)
275 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 276 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
276 #endif 277 #endif
277 278
278 /*----------------------------------------------------------------------- 279 /*-----------------------------------------------------------------------
279 * SYPCR - System Protection Control 11-9 280 * SYPCR - System Protection Control 11-9
280 * SYPCR can only be written once after reset! 281 * SYPCR can only be written once after reset!
281 *----------------------------------------------------------------------- 282 *-----------------------------------------------------------------------
282 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 283 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
283 */ 284 */
284 #if defined(CONFIG_WATCHDOG) 285 #if defined(CONFIG_WATCHDOG)
285 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 286 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
286 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 287 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
287 #else 288 #else
288 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 289 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
289 #endif 290 #endif
290 291
291 /*----------------------------------------------------------------------- 292 /*-----------------------------------------------------------------------
292 * SIUMCR - SIU Module Configuration 11-6 293 * SIUMCR - SIU Module Configuration 11-6
293 *----------------------------------------------------------------------- 294 *-----------------------------------------------------------------------
294 * PCMCIA config., multi-function pin tri-state 295 * PCMCIA config., multi-function pin tri-state
295 */ 296 */
296 #ifndef CONFIG_CAN_DRIVER 297 #ifndef CONFIG_CAN_DRIVER
297 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 298 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
298 #else /* we must activate GPL5 in the SIUMCR for CAN */ 299 #else /* we must activate GPL5 in the SIUMCR for CAN */
299 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 300 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
300 #endif /* CONFIG_CAN_DRIVER */ 301 #endif /* CONFIG_CAN_DRIVER */
301 302
302 /*----------------------------------------------------------------------- 303 /*-----------------------------------------------------------------------
303 * TBSCR - Time Base Status and Control 11-26 304 * TBSCR - Time Base Status and Control 11-26
304 *----------------------------------------------------------------------- 305 *-----------------------------------------------------------------------
305 * Clear Reference Interrupt Status, Timebase freezing enabled 306 * Clear Reference Interrupt Status, Timebase freezing enabled
306 */ 307 */
307 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 308 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
308 309
309 /*----------------------------------------------------------------------- 310 /*-----------------------------------------------------------------------
310 * PISCR - Periodic Interrupt Status and Control 11-31 311 * PISCR - Periodic Interrupt Status and Control 11-31
311 *----------------------------------------------------------------------- 312 *-----------------------------------------------------------------------
312 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 313 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
313 */ 314 */
314 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 315 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
315 316
316 /*----------------------------------------------------------------------- 317 /*-----------------------------------------------------------------------
317 * SCCR - System Clock and reset Control Register 15-27 318 * SCCR - System Clock and reset Control Register 15-27
318 *----------------------------------------------------------------------- 319 *-----------------------------------------------------------------------
319 * Set clock output, timebase and RTC source and divider, 320 * Set clock output, timebase and RTC source and divider,
320 * power management and some other internal clocks 321 * power management and some other internal clocks
321 */ 322 */
322 #define SCCR_MASK SCCR_EBDF11 323 #define SCCR_MASK SCCR_EBDF11
323 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 324 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
324 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 325 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
325 SCCR_DFALCD00) 326 SCCR_DFALCD00)
326 327
327 /*----------------------------------------------------------------------- 328 /*-----------------------------------------------------------------------
328 * PCMCIA stuff 329 * PCMCIA stuff
329 *----------------------------------------------------------------------- 330 *-----------------------------------------------------------------------
330 * 331 *
331 */ 332 */
332 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 333 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
333 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 334 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
334 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 335 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
335 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 336 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
336 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 337 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
337 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 338 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
338 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 339 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
339 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 340 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
340 341
341 /*----------------------------------------------------------------------- 342 /*-----------------------------------------------------------------------
342 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 343 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
343 *----------------------------------------------------------------------- 344 *-----------------------------------------------------------------------
344 */ 345 */
345 346
346 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 347 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
347 348
348 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 349 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
349 #undef CONFIG_IDE_LED /* LED for ide not supported */ 350 #undef CONFIG_IDE_LED /* LED for ide not supported */
350 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 351 #undef CONFIG_IDE_RESET /* reset for ide not supported */
351 352
352 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 353 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
353 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 354 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
354 355
355 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 356 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
356 357
357 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 358 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
358 359
359 /* Offset for data I/O */ 360 /* Offset for data I/O */
360 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 361 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
361 362
362 /* Offset for normal register accesses */ 363 /* Offset for normal register accesses */
363 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 364 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
364 365
365 /* Offset for alternate registers */ 366 /* Offset for alternate registers */
366 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 367 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
367 368
368 /*----------------------------------------------------------------------- 369 /*-----------------------------------------------------------------------
369 * 370 *
370 *----------------------------------------------------------------------- 371 *-----------------------------------------------------------------------
371 * 372 *
372 */ 373 */
373 #define CONFIG_SYS_DER 0 374 #define CONFIG_SYS_DER 0
374 375
375 /* 376 /*
376 * Init Memory Controller: 377 * Init Memory Controller:
377 * 378 *
378 * BR0/1 and OR0/1 (FLASH) 379 * BR0/1 and OR0/1 (FLASH)
379 */ 380 */
380 381
381 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 382 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
382 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 383 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
383 384
384 /* used to re-map FLASH both when starting from SRAM or FLASH: 385 /* used to re-map FLASH both when starting from SRAM or FLASH:
385 * restrict access enough to keep SRAM working (if any) 386 * restrict access enough to keep SRAM working (if any)
386 * but not too much to meddle with FLASH accesses 387 * but not too much to meddle with FLASH accesses
387 */ 388 */
388 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 389 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
389 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 390 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
390 391
391 /* 392 /*
392 * FLASH timing: Default value of OR0 after reset 393 * FLASH timing: Default value of OR0 after reset
393 */ 394 */
394 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ 395 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
395 OR_SCY_6_CLK | OR_TRLX) 396 OR_SCY_6_CLK | OR_TRLX)
396 397
397 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 398 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
398 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 399 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
399 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 400 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
400 401
401 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 402 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
402 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 403 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
403 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 404 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
404 405
405 /* 406 /*
406 * BR2/3 and OR2/3 (SDRAM) 407 * BR2/3 and OR2/3 (SDRAM)
407 * 408 *
408 */ 409 */
409 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 410 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
410 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 411 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
411 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ 412 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
412 413
413 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 414 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
414 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 415 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
415 416
416 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 417 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
417 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 418 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
418 419
419 #ifndef CONFIG_CAN_DRIVER 420 #ifndef CONFIG_CAN_DRIVER
420 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 421 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
421 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 422 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
422 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 423 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
423 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 424 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
424 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 425 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
425 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 426 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
426 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 427 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
427 BR_PS_8 | BR_MS_UPMB | BR_V ) 428 BR_PS_8 | BR_MS_UPMB | BR_V )
428 #endif /* CONFIG_CAN_DRIVER */ 429 #endif /* CONFIG_CAN_DRIVER */
429 430
430 /* 431 /*
431 * 4096 Rows from SDRAM example configuration 432 * 4096 Rows from SDRAM example configuration
432 * 1000 factor s -> ms 433 * 1000 factor s -> ms
433 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration 434 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
434 * 4 Number of refresh cycles per period 435 * 4 Number of refresh cycles per period
435 * 64 Refresh cycle in ms per number of rows 436 * 64 Refresh cycle in ms per number of rows
436 */ 437 */
437 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) 438 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
438 439
439 /* 440 /*
440 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) 441 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
441 * 442 *
442 * CPUclock(MHz) * 31.2 443 * CPUclock(MHz) * 31.2
443 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 444 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
444 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 445 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
445 * 446 *
446 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us 447 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
447 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us 448 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
448 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us 449 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
449 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us 450 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
450 * 451 *
451 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will 452 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
452 * be met also in the default configuration, i.e. if environment variable 453 * be met also in the default configuration, i.e. if environment variable
453 * 'cpuclk' is not set. 454 * 'cpuclk' is not set.
454 */ 455 */
455 #define CONFIG_SYS_MAMR_PTA 128 456 #define CONFIG_SYS_MAMR_PTA 128
456 457
457 /* 458 /*
458 * Memory Periodic Timer Prescaler Register (MPTPR) values. 459 * Memory Periodic Timer Prescaler Register (MPTPR) values.
459 */ 460 */
460 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ 461 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
461 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 462 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
462 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ 463 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
463 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 464 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
464 465
465 /* 466 /*
466 * MAMR settings for SDRAM 467 * MAMR settings for SDRAM
467 */ 468 */
468 469
469 /* 8 column SDRAM */ 470 /* 8 column SDRAM */
470 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 471 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
471 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 472 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
472 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
473 /* 9 column SDRAM */ 474 /* 9 column SDRAM */
474 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 475 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
475 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 476 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
476 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 477 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
477 /* 10 column SDRAM */ 478 /* 10 column SDRAM */
478 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 479 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
479 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 480 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
480 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 481 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
481 482
482 /* 483 /*
483 * Internal Definitions 484 * Internal Definitions
484 * 485 *
485 * Boot Flags 486 * Boot Flags
486 */ 487 */
487 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 488 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
488 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 489 #define BOOTFLAG_WARM 0x02 /* Software reboot */
489 490
490 /* 491 /*
491 * Network configuration 492 * Network configuration
492 */ 493 */
493 #define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ 494 #define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
494 #define CONFIG_FEC_ENET /* enable ethernet on FEC */ 495 #define CONFIG_FEC_ENET /* enable ethernet on FEC */
495 #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ 496 #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
496 #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ 497 #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
497 498
498 #if defined(CONFIG_CMD_MII) 499 #if defined(CONFIG_CMD_MII)
499 #define CONFIG_SYS_DISCOVER_PHY 500 #define CONFIG_SYS_DISCOVER_PHY
500 #define CONFIG_MII_INIT 1 501 #define CONFIG_MII_INIT 1
501 #endif 502 #endif
502 503
503 #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before 504 #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
504 switching to another netwok (if the 505 switching to another netwok (if the
505 tried network is unreachable) */ 506 tried network is unreachable) */
506 507
507 #define CONFIG_ETHPRIME "SCC ETHERNET" 508 #define CONFIG_ETHPRIME "SCC ETHERNET"
508 509
509 #endif /* __CONFIG_H */ 510 #endif /* __CONFIG_H */
510 511
include/configs/virtlab2.h
Diff comments   View file @ 9a63b7f
1 /* 1 /*
2 * (C) Copyright 2006-2008 2 * (C) Copyright 2006-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37 #define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */ 37 #define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
38 #define CONFIG_TQM8xxL 1 38 #define CONFIG_TQM8xxL 1
39 39
40 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 40 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
41 #undef CONFIG_8xx_CONS_SMC2 41 #undef CONFIG_8xx_CONS_SMC2
42 #undef CONFIG_8xx_CONS_NONE 42 #undef CONFIG_8xx_CONS_NONE
43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44 44
45 #define CONFIG_BOOTCOUNT_LIMIT 45 #define CONFIG_BOOTCOUNT_LIMIT
46 46
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48 48
49 #define CONFIG_BOARD_TYPES 1 /* support board types */ 49 #define CONFIG_BOARD_TYPES 1 /* support board types */
50 50
51 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 51 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
52 52
53 #undef CONFIG_BOOTARGS 53 #undef CONFIG_BOOTARGS
54 54
55 #define CONFIG_EXTRA_ENV_SETTINGS \ 55 #define CONFIG_EXTRA_ENV_SETTINGS \
56 "netdev=eth0\0" \ 56 "netdev=eth0\0" \
57 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 57 "nfsargs=setenv bootargs root=/dev/nfs rw " \
58 "nfsroot=${serverip}:${rootpath}\0" \ 58 "nfsroot=${serverip}:${rootpath}\0" \
59 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 59 "ramargs=setenv bootargs root=/dev/ram rw\0" \
60 "addip=setenv bootargs ${bootargs} " \ 60 "addip=setenv bootargs ${bootargs} " \
61 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 61 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
62 ":${hostname}:${netdev}:off panic=1\0" \ 62 ":${hostname}:${netdev}:off panic=1\0" \
63 "flash_nfs=run nfsargs addip;" \ 63 "flash_nfs=run nfsargs addip;" \
64 "bootm ${kernel_addr}\0" \ 64 "bootm ${kernel_addr}\0" \
65 "flash_self=run ramargs addip;" \ 65 "flash_self=run ramargs addip;" \
66 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 66 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
67 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 67 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
68 "rootpath=/opt/eldk/ppc_8xx\0" \ 68 "rootpath=/opt/eldk/ppc_8xx\0" \
69 "hostname=virtlab2\0" \ 69 "hostname=virtlab2\0" \
70 "bootfile=virtlab2/uImage\0" \ 70 "bootfile=virtlab2/uImage\0" \
71 "fdt_addr=40040000\0" \ 71 "fdt_addr=40040000\0" \
72 "kernel_addr=40060000\0" \ 72 "kernel_addr=40060000\0" \
73 "ramdisk_addr=40200000\0" \ 73 "ramdisk_addr=40200000\0" \
74 "u-boot=virtlab2/u-image.bin\0" \ 74 "u-boot=virtlab2/u-image.bin\0" \
75 "load=tftp 200000 ${u-boot}\0" \ 75 "load=tftp 200000 ${u-boot}\0" \
76 "update=prot off 40000000 +${filesize};" \ 76 "update=prot off 40000000 +${filesize};" \
77 "era 40000000 +${filesize};" \ 77 "era 40000000 +${filesize};" \
78 "cp.b 200000 40000000 ${filesize};" \ 78 "cp.b 200000 40000000 ${filesize};" \
79 "sete filesize;save\0" \ 79 "sete filesize;save\0" \
80 "" 80 ""
81 #define CONFIG_BOOTCOMMAND "run flash_self" 81 #define CONFIG_BOOTCOMMAND "run flash_self"
82 82
83 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 83 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
84 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 84 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
85 85
86 #undef CONFIG_WATCHDOG /* watchdog disabled */ 86 #undef CONFIG_WATCHDOG /* watchdog disabled */
87 87
88 #if defined(CONFIG_LCD) 88 #if defined(CONFIG_LCD)
89 # undef CONFIG_STATUS_LED /* disturbs display */ 89 # undef CONFIG_STATUS_LED /* disturbs display */
90 #else 90 #else
91 # define CONFIG_STATUS_LED 1 /* Status LED enabled */ 91 # define CONFIG_STATUS_LED 1 /* Status LED enabled */
92 #endif /* CONFIG_LCD */ 92 #endif /* CONFIG_LCD */
93 93
94 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 94 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
95 95
96 /* 96 /*
97 * BOOTP options 97 * BOOTP options
98 */ 98 */
99 #define CONFIG_BOOTP_SUBNETMASK 99 #define CONFIG_BOOTP_SUBNETMASK
100 #define CONFIG_BOOTP_GATEWAY 100 #define CONFIG_BOOTP_GATEWAY
101 #define CONFIG_BOOTP_HOSTNAME 101 #define CONFIG_BOOTP_HOSTNAME
102 #define CONFIG_BOOTP_BOOTPATH 102 #define CONFIG_BOOTP_BOOTPATH
103 #define CONFIG_BOOTP_BOOTFILESIZE 103 #define CONFIG_BOOTP_BOOTFILESIZE
104 104
105 105
106 #define CONFIG_MAC_PARTITION 106 #define CONFIG_MAC_PARTITION
107 #define CONFIG_DOS_PARTITION 107 #define CONFIG_DOS_PARTITION
108 108
109 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 109 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
110 110
111 111
112 /* 112 /*
113 * Command line configuration. 113 * Command line configuration.
114 */ 114 */
115 #include <config_cmd_default.h> 115 #include <config_cmd_default.h>
116 116
117 #define CONFIG_CMD_ASKENV 117 #define CONFIG_CMD_ASKENV
118 #define CONFIG_CMD_DATE 118 #define CONFIG_CMD_DATE
119 #define CONFIG_CMD_DHCP 119 #define CONFIG_CMD_DHCP
120 #define CONFIG_CMD_EXT2
120 #define CONFIG_CMD_IDE 121 #define CONFIG_CMD_IDE
121 #define CONFIG_CMD_JFFS2 122 #define CONFIG_CMD_JFFS2
122 #define CONFIG_CMD_NFS 123 #define CONFIG_CMD_NFS
123 #define CONFIG_CMD_SNTP 124 #define CONFIG_CMD_SNTP
124 125
125 #if defined(CONFIG_SPLASH_SCREEN) 126 #if defined(CONFIG_SPLASH_SCREEN)
126 #define CONFIG_CMD_BMP 127 #define CONFIG_CMD_BMP
127 #endif 128 #endif
128 129
129 130
130 #define CONFIG_NETCONSOLE 131 #define CONFIG_NETCONSOLE
131 132
132 /* 133 /*
133 * Miscellaneous configurable options 134 * Miscellaneous configurable options
134 */ 135 */
135 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 136 #define CONFIG_SYS_LONGHELP /* undef to save memory */
136 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 137 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
137 138
138 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 139 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
139 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 140 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
140 #ifdef CONFIG_SYS_HUSH_PARSER 141 #ifdef CONFIG_SYS_HUSH_PARSER
141 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 142 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
142 #endif 143 #endif
143 144
144 #if defined(CONFIG_CMD_KGDB) 145 #if defined(CONFIG_CMD_KGDB)
145 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 146 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
146 #else 147 #else
147 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 148 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
148 #endif 149 #endif
149 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
150 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 151 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
151 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 152 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
152 153
153 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 154 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
154 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 155 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
155 156
156 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 157 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
157 158
158 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 159 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
159 160
160 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 161 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
161 162
162 /* 163 /*
163 * Low Level Configuration Settings 164 * Low Level Configuration Settings
164 * (address mappings, register initial values, etc.) 165 * (address mappings, register initial values, etc.)
165 * You should know what you are doing if you make changes here. 166 * You should know what you are doing if you make changes here.
166 */ 167 */
167 /*----------------------------------------------------------------------- 168 /*-----------------------------------------------------------------------
168 * Internal Memory Mapped Register 169 * Internal Memory Mapped Register
169 */ 170 */
170 #define CONFIG_SYS_IMMR 0xFFF00000 171 #define CONFIG_SYS_IMMR 0xFFF00000
171 172
172 /*----------------------------------------------------------------------- 173 /*-----------------------------------------------------------------------
173 * Definitions for initial stack pointer and data area (in DPRAM) 174 * Definitions for initial stack pointer and data area (in DPRAM)
174 */ 175 */
175 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 176 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
176 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 177 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
177 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 178 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
178 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 179 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
180 181
181 /*----------------------------------------------------------------------- 182 /*-----------------------------------------------------------------------
182 * Start addresses for the final memory configuration 183 * Start addresses for the final memory configuration
183 * (Set up by the startup code) 184 * (Set up by the startup code)
184 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 185 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
185 */ 186 */
186 #define CONFIG_SYS_SDRAM_BASE 0x00000000 187 #define CONFIG_SYS_SDRAM_BASE 0x00000000
187 #define CONFIG_SYS_FLASH_BASE 0x40000000 188 #define CONFIG_SYS_FLASH_BASE 0x40000000
188 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 189 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
190 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 191 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
191 192
192 /* 193 /*
193 * For booting Linux, the board info and command line data 194 * For booting Linux, the board info and command line data
194 * have to be in the first 8 MB of memory, since this is 195 * have to be in the first 8 MB of memory, since this is
195 * the maximum mapped by the Linux kernel during initialization. 196 * the maximum mapped by the Linux kernel during initialization.
196 */ 197 */
197 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 198 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
198 199
199 /*----------------------------------------------------------------------- 200 /*-----------------------------------------------------------------------
200 * FLASH organization 201 * FLASH organization
201 */ 202 */
202 203
203 /* use CFI flash driver */ 204 /* use CFI flash driver */
204 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 205 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
205 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 206 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
206 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 207 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
207 #define CONFIG_SYS_FLASH_EMPTY_INFO 208 #define CONFIG_SYS_FLASH_EMPTY_INFO
208 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 209 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
209 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 210 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
210 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 211 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
211 212
212 #define CONFIG_ENV_IS_IN_FLASH 1 213 #define CONFIG_ENV_IS_IN_FLASH 1
213 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 214 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
214 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 215 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
215 216
216 /* Address and size of Redundant Environment Sector */ 217 /* Address and size of Redundant Environment Sector */
217 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 218 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
218 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 219 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
219 220
220 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 221 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
221 222
222 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 223 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
223 224
224 /*----------------------------------------------------------------------- 225 /*-----------------------------------------------------------------------
225 * Dynamic MTD partition support 226 * Dynamic MTD partition support
226 */ 227 */
227 #define CONFIG_JFFS2_CMDLINE 228 #define CONFIG_JFFS2_CMDLINE
228 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 229 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
229 230
230 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 231 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
231 "128k(dtb)," \ 232 "128k(dtb)," \
232 "1664k(kernel)," \ 233 "1664k(kernel)," \
233 "2m(rootfs)," \ 234 "2m(rootfs)," \
234 "4m(data)" 235 "4m(data)"
235 236
236 /*----------------------------------------------------------------------- 237 /*-----------------------------------------------------------------------
237 * Hardware Information Block 238 * Hardware Information Block
238 */ 239 */
239 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 240 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
240 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 241 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
241 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 242 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
242 243
243 /*----------------------------------------------------------------------- 244 /*-----------------------------------------------------------------------
244 * Cache Configuration 245 * Cache Configuration
245 */ 246 */
246 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 247 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
247 #if defined(CONFIG_CMD_KGDB) 248 #if defined(CONFIG_CMD_KGDB)
248 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 249 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
249 #endif 250 #endif
250 251
251 /*----------------------------------------------------------------------- 252 /*-----------------------------------------------------------------------
252 * SYPCR - System Protection Control 11-9 253 * SYPCR - System Protection Control 11-9
253 * SYPCR can only be written once after reset! 254 * SYPCR can only be written once after reset!
254 *----------------------------------------------------------------------- 255 *-----------------------------------------------------------------------
255 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 256 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
256 */ 257 */
257 #if defined(CONFIG_WATCHDOG) 258 #if defined(CONFIG_WATCHDOG)
258 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 259 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
259 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 260 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
260 #else 261 #else
261 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 262 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
262 #endif 263 #endif
263 264
264 /*----------------------------------------------------------------------- 265 /*-----------------------------------------------------------------------
265 * SIUMCR - SIU Module Configuration 11-6 266 * SIUMCR - SIU Module Configuration 11-6
266 *----------------------------------------------------------------------- 267 *-----------------------------------------------------------------------
267 * PCMCIA config., multi-function pin tri-state 268 * PCMCIA config., multi-function pin tri-state
268 */ 269 */
269 #ifndef CONFIG_CAN_DRIVER 270 #ifndef CONFIG_CAN_DRIVER
270 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 271 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
271 #else /* we must activate GPL5 in the SIUMCR for CAN */ 272 #else /* we must activate GPL5 in the SIUMCR for CAN */
272 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 273 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
273 #endif /* CONFIG_CAN_DRIVER */ 274 #endif /* CONFIG_CAN_DRIVER */
274 275
275 /*----------------------------------------------------------------------- 276 /*-----------------------------------------------------------------------
276 * TBSCR - Time Base Status and Control 11-26 277 * TBSCR - Time Base Status and Control 11-26
277 *----------------------------------------------------------------------- 278 *-----------------------------------------------------------------------
278 * Clear Reference Interrupt Status, Timebase freezing enabled 279 * Clear Reference Interrupt Status, Timebase freezing enabled
279 */ 280 */
280 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 281 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
281 282
282 /*----------------------------------------------------------------------- 283 /*-----------------------------------------------------------------------
283 * RTCSC - Real-Time Clock Status and Control Register 11-27 284 * RTCSC - Real-Time Clock Status and Control Register 11-27
284 *----------------------------------------------------------------------- 285 *-----------------------------------------------------------------------
285 */ 286 */
286 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 287 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
287 288
288 /*----------------------------------------------------------------------- 289 /*-----------------------------------------------------------------------
289 * PISCR - Periodic Interrupt Status and Control 11-31 290 * PISCR - Periodic Interrupt Status and Control 11-31
290 *----------------------------------------------------------------------- 291 *-----------------------------------------------------------------------
291 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 292 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
292 */ 293 */
293 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 294 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
294 295
295 /*----------------------------------------------------------------------- 296 /*-----------------------------------------------------------------------
296 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 297 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
297 *----------------------------------------------------------------------- 298 *-----------------------------------------------------------------------
298 * Reset PLL lock status sticky bit, timer expired status bit and timer 299 * Reset PLL lock status sticky bit, timer expired status bit and timer
299 * interrupt status bit 300 * interrupt status bit
300 */ 301 */
301 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 302 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
302 303
303 /*----------------------------------------------------------------------- 304 /*-----------------------------------------------------------------------
304 * SCCR - System Clock and reset Control Register 15-27 305 * SCCR - System Clock and reset Control Register 15-27
305 *----------------------------------------------------------------------- 306 *-----------------------------------------------------------------------
306 * Set clock output, timebase and RTC source and divider, 307 * Set clock output, timebase and RTC source and divider,
307 * power management and some other internal clocks 308 * power management and some other internal clocks
308 */ 309 */
309 #define SCCR_MASK SCCR_EBDF11 310 #define SCCR_MASK SCCR_EBDF11
310 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 311 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
311 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 312 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
312 SCCR_DFALCD00) 313 SCCR_DFALCD00)
313 314
314 /*----------------------------------------------------------------------- 315 /*-----------------------------------------------------------------------
315 * PCMCIA stuff 316 * PCMCIA stuff
316 *----------------------------------------------------------------------- 317 *-----------------------------------------------------------------------
317 * 318 *
318 */ 319 */
319 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 320 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
320 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 321 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
321 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 322 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
322 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 323 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
323 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 324 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
324 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 325 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
325 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 326 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
326 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 327 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
327 328
328 /*----------------------------------------------------------------------- 329 /*-----------------------------------------------------------------------
329 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 330 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
330 *----------------------------------------------------------------------- 331 *-----------------------------------------------------------------------
331 */ 332 */
332 333
333 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 334 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
334 335
335 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 336 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
336 #undef CONFIG_IDE_LED /* LED for ide not supported */ 337 #undef CONFIG_IDE_LED /* LED for ide not supported */
337 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 338 #undef CONFIG_IDE_RESET /* reset for ide not supported */
338 339
339 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 340 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
340 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 341 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
341 342
342 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 343 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
343 344
344 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 345 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
345 346
346 /* Offset for data I/O */ 347 /* Offset for data I/O */
347 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 348 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
348 349
349 /* Offset for normal register accesses */ 350 /* Offset for normal register accesses */
350 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 351 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
351 352
352 /* Offset for alternate registers */ 353 /* Offset for alternate registers */
353 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 354 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
354 355
355 /*----------------------------------------------------------------------- 356 /*-----------------------------------------------------------------------
356 * 357 *
357 *----------------------------------------------------------------------- 358 *-----------------------------------------------------------------------
358 * 359 *
359 */ 360 */
360 #define CONFIG_SYS_DER 0 361 #define CONFIG_SYS_DER 0
361 362
362 /* 363 /*
363 * Init Memory Controller: 364 * Init Memory Controller:
364 * 365 *
365 * BR0/1 and OR0/1 (FLASH) 366 * BR0/1 and OR0/1 (FLASH)
366 */ 367 */
367 368
368 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 369 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
369 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 370 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
370 371
371 /* used to re-map FLASH both when starting from SRAM or FLASH: 372 /* used to re-map FLASH both when starting from SRAM or FLASH:
372 * restrict access enough to keep SRAM working (if any) 373 * restrict access enough to keep SRAM working (if any)
373 * but not too much to meddle with FLASH accesses 374 * but not too much to meddle with FLASH accesses
374 */ 375 */
375 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 376 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
376 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 377 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
377 378
378 /* 379 /*
379 * FLASH timing: 380 * FLASH timing:
380 */ 381 */
381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 382 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
382 OR_SCY_3_CLK | OR_EHTR | OR_BI) 383 OR_SCY_3_CLK | OR_EHTR | OR_BI)
383 384
384 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 385 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
385 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 386 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
386 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 387 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
387 388
388 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 389 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
389 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 390 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
390 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 391 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
391 392
392 /* 393 /*
393 * BR2/3 and OR2/3 (SDRAM) 394 * BR2/3 and OR2/3 (SDRAM)
394 * 395 *
395 */ 396 */
396 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 397 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
397 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 398 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
398 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 399 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
399 400
400 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 401 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
401 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 402 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
402 403
403 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 404 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
404 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 405 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
405 406
406 #ifndef CONFIG_CAN_DRIVER 407 #ifndef CONFIG_CAN_DRIVER
407 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 408 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
408 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 409 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
409 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 410 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
410 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 411 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
411 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 412 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
412 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 413 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
413 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 414 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
414 BR_PS_8 | BR_MS_UPMB | BR_V ) 415 BR_PS_8 | BR_MS_UPMB | BR_V )
415 #endif /* CONFIG_CAN_DRIVER */ 416 #endif /* CONFIG_CAN_DRIVER */
416 417
417 /* 418 /*
418 * Memory Periodic Timer Prescaler 419 * Memory Periodic Timer Prescaler
419 * 420 *
420 * The Divider for PTA (refresh timer) configuration is based on an 421 * The Divider for PTA (refresh timer) configuration is based on an
421 * example SDRAM configuration (64 MBit, one bank). The adjustment to 422 * example SDRAM configuration (64 MBit, one bank). The adjustment to
422 * the number of chip selects (NCS) and the actually needed refresh 423 * the number of chip selects (NCS) and the actually needed refresh
423 * rate is done by setting MPTPR. 424 * rate is done by setting MPTPR.
424 * 425 *
425 * PTA is calculated from 426 * PTA is calculated from
426 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 427 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
427 * 428 *
428 * gclk CPU clock (not bus clock!) 429 * gclk CPU clock (not bus clock!)
429 * Trefresh Refresh cycle * 4 (four word bursts used) 430 * Trefresh Refresh cycle * 4 (four word bursts used)
430 * 431 *
431 * 4096 Rows from SDRAM example configuration 432 * 4096 Rows from SDRAM example configuration
432 * 1000 factor s -> ms 433 * 1000 factor s -> ms
433 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 434 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
434 * 4 Number of refresh cycles per period 435 * 4 Number of refresh cycles per period
435 * 64 Refresh cycle in ms per number of rows 436 * 64 Refresh cycle in ms per number of rows
436 * -------------------------------------------- 437 * --------------------------------------------
437 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 438 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
438 * 439 *
439 * 50 MHz => 50.000.000 / Divider = 98 440 * 50 MHz => 50.000.000 / Divider = 98
440 * 66 Mhz => 66.000.000 / Divider = 129 441 * 66 Mhz => 66.000.000 / Divider = 129
441 * 80 Mhz => 80.000.000 / Divider = 156 442 * 80 Mhz => 80.000.000 / Divider = 156
442 */ 443 */
443 444
444 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 445 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
445 #define CONFIG_SYS_MAMR_PTA 98 446 #define CONFIG_SYS_MAMR_PTA 98
446 447
447 /* 448 /*
448 * For 16 MBit, refresh rates could be 31.3 us 449 * For 16 MBit, refresh rates could be 31.3 us
449 * (= 64 ms / 2K = 125 / quad bursts). 450 * (= 64 ms / 2K = 125 / quad bursts).
450 * For a simpler initialization, 15.6 us is used instead. 451 * For a simpler initialization, 15.6 us is used instead.
451 * 452 *
452 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 453 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
453 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 454 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
454 */ 455 */
455 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 456 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
456 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 457 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
457 458
458 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 459 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
459 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 460 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
460 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 461 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
461 462
462 /* 463 /*
463 * MAMR settings for SDRAM 464 * MAMR settings for SDRAM
464 */ 465 */
465 466
466 /* 8 column SDRAM */ 467 /* 8 column SDRAM */
467 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 468 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
468 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 469 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
469 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
470 /* 9 column SDRAM */ 471 /* 9 column SDRAM */
471 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 472 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
472 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 473 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 474 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
474 475
475 476
476 /* 477 /*
477 * Internal Definitions 478 * Internal Definitions
478 * 479 *
479 * Boot Flags 480 * Boot Flags
480 */ 481 */
481 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 482 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
482 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 483 #define BOOTFLAG_WARM 0x02 /* Software reboot */
483 484
484 /* Map peripheral control registers on CS4 */ 485 /* Map peripheral control registers on CS4 */
485 #define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000 486 #define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000
486 #define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */ 487 #define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
487 #define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \ 488 #define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
488 OR_SCY_2_CLK) 489 OR_SCY_2_CLK)
489 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) 490 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
490 #define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00) 491 #define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
491 #endif /* __CONFIG_H */ 492 #endif /* __CONFIG_H */
492 493