Eric Lee / smarc-uboot

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/*

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/*

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*

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*

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* SPDX-License-Identifier: GPL-2.0+

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* SPDX-License-Identifier: GPL-2.0+

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*/

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*/

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#include <asm/arch/clock.h>

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#include <asm/arch/clock.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/arch/mx7-pins.h>

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#include <asm/arch/mx7-pins.h>

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#include <asm/arch/sys_proto.h>

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#include <asm/arch/sys_proto.h>

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#include <asm/gpio.h>

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#include <asm/gpio.h>

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#include <asm/imx-common/iomux-v3.h>

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#include <asm/imx-common/iomux-v3.h>

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#include <asm/imx-common/boot_mode.h>

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#include <asm/imx-common/boot_mode.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <linux/sizes.h>

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#include <linux/sizes.h>

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#include <common.h>

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#include <common.h>

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#include <fsl_esdhc.h>

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#include <fsl_esdhc.h>

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#include <mmc.h>

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#include <mmc.h>

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#include <miiphy.h>

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#include <miiphy.h>

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#include <netdev.h>

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#include <netdev.h>

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#include <power/pmic.h>

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#include <power/pmic.h>

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#include <power/pfuze3000_pmic.h>

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#include <power/pfuze3000_pmic.h>

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#include "pfuze.h"

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#include "pfuze.h"

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#include <pwm.h>

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#include <pwm.h>

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#include <i2c.h>

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#include <i2c.h>

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#include <asm/imx-common/mxc_i2c.h>

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#include <asm/imx-common/mxc_i2c.h>

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#include <asm/arch/crm_regs.h>

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#include <asm/arch/crm_regs.h>

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#include <usb.h>

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#include <usb.h>

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#include <usb/ehci-fsl.h>

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#include <usb/ehci-fsl.h>

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#if defined(CONFIG_MXC_EPDC)

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#if defined(CONFIG_MXC_EPDC)

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#include <lcd.h>

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#include <lcd.h>

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#include <mxc_epdc_fb.h>

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#include <mxc_epdc_fb.h>

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#endif

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#endif

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#include <asm/imx-common/video.h>

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#include <asm/imx-common/video.h>

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#include "smarcfimx7.h"

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#include "smarcfimx7.h"

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#ifdef CONFIG_FSL_FASTBOOT

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#ifdef CONFIG_FSL_FASTBOOT

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#include <fsl_fastboot.h>

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#include <fsl_fastboot.h>

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#ifdef CONFIG_ANDROID_RECOVERY

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#ifdef CONFIG_ANDROID_RECOVERY

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#include <recovery.h>

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#include <recovery.h>

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#endif

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#endif

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#endif /*CONFIG_FSL_FASTBOOT*/

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#endif /*CONFIG_FSL_FASTBOOT*/

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DECLARE_GLOBAL_DATA_PTR;

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DECLARE_GLOBAL_DATA_PTR;

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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \

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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \

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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)

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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)

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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \

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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \

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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)

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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)

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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)

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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)

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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \

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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \

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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)

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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)

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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \

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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \

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PAD_CTL_DSE_3P3V_49OHM)

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PAD_CTL_DSE_3P3V_49OHM)

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#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM)

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#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM)

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#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)

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#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)

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#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)

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#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)

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#define EPDC_PAD_CTRL 0x0

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#define EPDC_PAD_CTRL 0x0

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#define WEAK_PULLUP (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM | \

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#define WEAK_PULLUP (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM | \

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PAD_CTL_HYS | PAD_CTL_SRE_SLOW)

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PAD_CTL_HYS | PAD_CTL_SRE_SLOW)

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#ifdef CONFIG_SYS_I2C_MXC

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#ifdef CONFIG_SYS_I2C_MXC

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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

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/*

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/*

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* Read header information from EEPROM into global structure.

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* Read header information from EEPROM into global structure.

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*/

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*/

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static int read_eeprom(struct smarcfimx7_id *header)

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static int read_eeprom(struct smarcfimx7_id *header)

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{

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{

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i2c_set_bus_num(1);

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i2c_set_bus_num(1);

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/* Check if baseboard eeprom is available */

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/* Check if baseboard eeprom is available */

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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {

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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {

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puts("Could not probe the EEPROM; something fundamentally "

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puts("Could not probe the EEPROM; something fundamentally "

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"wrong on the I2C bus.\n");

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"wrong on the I2C bus.\n");

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return -ENODEV;

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return -ENODEV;

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}

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}

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/* read the eeprom using i2c */

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/* read the eeprom using i2c */

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,

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sizeof(struct smarcfimx7_id))) {

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sizeof(struct smarcfimx7_id))) {

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puts("Could not read the EEPROM; something fundamentally"

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puts("Could not read the EEPROM; something fundamentally"

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" wrong on the I2C bus.\n");

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" wrong on the I2C bus.\n");

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return -EIO;

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return -EIO;

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}

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}

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if (header->magic != 0xEE3355AA) {

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if (header->magic != 0xEE3355AA) {

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/*

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/*

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* read the eeprom using i2c again,

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* read the eeprom using i2c again,

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* but use only a 1 byte address

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* but use only a 1 byte address

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*/

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*/

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,

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sizeof(struct smarcfimx7_id))) {

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sizeof(struct smarcfimx7_id))) {

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puts("Could not read the EEPROM; something "

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puts("Could not read the EEPROM; something "

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"fundamentally wrong on the I2C bus.\n");

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"fundamentally wrong on the I2C bus.\n");

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return -EIO;

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return -EIO;

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}

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}

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if (header->magic != 0xEE3355AA) {

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if (header->magic != 0xEE3355AA) {

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printf("Incorrect magic number (0x%x) in EEPROM\n",

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printf("Incorrect magic number (0x%x) in EEPROM\n",

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header->magic);

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header->magic);

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return -EINVAL;

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return -EINVAL;

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}

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}

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}

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}

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return 0;

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return 0;

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}

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}

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/* I2C1 for PMIC (I2C_PM)*/

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/* I2C1 for PMIC (I2C_PM)*/

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static struct i2c_pads_info i2c_pad_info1 = {

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static struct i2c_pads_info i2c_pad_info1 = {

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.scl = {

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.scl = {

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.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,

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.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,

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.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,

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.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,

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.gp = IMX_GPIO_NR(4, 8),

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.gp = IMX_GPIO_NR(4, 8),

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,

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.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,

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.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,

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.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,

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.gp = IMX_GPIO_NR(4, 9),

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.gp = IMX_GPIO_NR(4, 9),

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},

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},

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};

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};

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/* I2C2 for I2C_GP */

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/* I2C2 for I2C_GP */

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static struct i2c_pads_info i2c_pad_info2 = {

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static struct i2c_pads_info i2c_pad_info2 = {

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.scl = {

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.scl = {

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.i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,

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.i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,

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.gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,

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.gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,

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.gp = IMX_GPIO_NR(4, 10),

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.gp = IMX_GPIO_NR(4, 10),

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,

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.i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,

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.gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,

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.gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,

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.gp = IMX_GPIO_NR(4, 11),

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.gp = IMX_GPIO_NR(4, 11),

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},

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},

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};

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};

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/* I2C3 for I2C_LCD */

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/* I2C3 for I2C_LCD */

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static struct i2c_pads_info i2c_pad_info3 = {

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static struct i2c_pads_info i2c_pad_info3 = {

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.scl = {

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.scl = {

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.i2c_mode = MX7D_PAD_I2C3_SCL__I2C3_SCL | PC,

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.i2c_mode = MX7D_PAD_I2C3_SCL__I2C3_SCL | PC,

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.gpio_mode = MX7D_PAD_I2C3_SCL__GPIO4_IO12 | PC,

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.gpio_mode = MX7D_PAD_I2C3_SCL__GPIO4_IO12 | PC,

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.gp = IMX_GPIO_NR(4, 12),

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.gp = IMX_GPIO_NR(4, 12),

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX7D_PAD_I2C3_SDA__I2C3_SDA | PC,

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.i2c_mode = MX7D_PAD_I2C3_SDA__I2C3_SDA | PC,

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.gpio_mode = MX7D_PAD_I2C3_SDA__GPIO4_IO13 | PC,

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.gpio_mode = MX7D_PAD_I2C3_SDA__GPIO4_IO13 | PC,

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.gp = IMX_GPIO_NR(4, 13),

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.gp = IMX_GPIO_NR(4, 13),

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},

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},

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};

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};

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/* I2C4 for I2C_CAM1 */

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/* I2C4 for I2C_CAM1 */

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static struct i2c_pads_info i2c_pad_info4 = {

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static struct i2c_pads_info i2c_pad_info4 = {

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.scl = {

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.scl = {

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.i2c_mode = MX7D_PAD_I2C4_SCL__I2C4_SCL | PC,

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.i2c_mode = MX7D_PAD_I2C4_SCL__I2C4_SCL | PC,

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.gpio_mode = MX7D_PAD_I2C4_SCL__GPIO4_IO14 | PC,

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.gpio_mode = MX7D_PAD_I2C4_SCL__GPIO4_IO14 | PC,

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.gp = IMX_GPIO_NR(4, 14),

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.gp = IMX_GPIO_NR(4, 14),

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX7D_PAD_I2C4_SDA__I2C4_SDA | PC,

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.i2c_mode = MX7D_PAD_I2C4_SDA__I2C4_SDA | PC,

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.gpio_mode = MX7D_PAD_I2C4_SDA__GPIO4_IO15 | PC,

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.gpio_mode = MX7D_PAD_I2C4_SDA__GPIO4_IO15 | PC,

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.gp = IMX_GPIO_NR(4, 15),

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.gp = IMX_GPIO_NR(4, 15),

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},

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},

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};

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};

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#endif

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#endif

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int dram_init(void)

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int dram_init(void)

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{

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{

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gd->ram_size = PHYS_SDRAM_SIZE;

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gd->ram_size = PHYS_SDRAM_SIZE;

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return 0;

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return 0;

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}

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}

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static iomux_v3_cfg_t const wdog_pads[] = {

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static iomux_v3_cfg_t const wdog_pads[] = {

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MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),

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};

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};

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/* SER0/UART6 */

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/* SER0/UART6 */

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static iomux_v3_cfg_t const uart6_pads[] = {

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static iomux_v3_cfg_t const uart6_pads[] = {

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MX7D_PAD_EPDC_DATA09__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA09__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA08__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA08__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* SER1/UART2 */

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/* SER1/UART2 */

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static iomux_v3_cfg_t const uart2_pads[] = {

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static iomux_v3_cfg_t const uart2_pads[] = {

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MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* SER2/UART7 */

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/* SER2/UART7 */

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static iomux_v3_cfg_t const uart7_pads[] = {

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static iomux_v3_cfg_t const uart7_pads[] = {

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MX7D_PAD_EPDC_DATA13__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA13__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA12__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA12__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* SER3/UART3 Debug Port */

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/* SER3/UART3 Debug Port */

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static iomux_v3_cfg_t const uart3_pads[] = {

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static iomux_v3_cfg_t const uart3_pads[] = {

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MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* RESET_OUT# */

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/* RESET_OUT# */

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static iomux_v3_cfg_t const reset_out_pads[] = {

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static iomux_v3_cfg_t const reset_out_pads[] = {

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MX7D_PAD_EPDC_BDR1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX7D_PAD_EPDC_BDR1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

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};

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};

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/* SD Card */

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/* SD Card */

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static iomux_v3_cfg_t const usdhc1_pads[] = {

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static iomux_v3_cfg_t const usdhc1_pads[] = {

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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /*CD */

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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /*CD */

232

MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */

232

MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */

233

MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* SDIO_PWR_EN */

233

MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* SDIO_PWR_EN */

234

};

234

};

235

236

/* eMMC */

236

/* eMMC */

237

static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {

237

static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {

238

MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

238

MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

239

MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

239

MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

240

MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

240

MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

241

MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

241

MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

242

MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

242

MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

243

MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

243

MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

244

MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

244

MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

245

MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

245

MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

246

MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

246

MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

247

MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

247

MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

248

MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),

248

MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),

249

MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

249

MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

250

};

250

};

251

252

/* SPI0 */

252

/* SPI0 */

253

static iomux_v3_cfg_t const ecspi1_pads[] = {

253

static iomux_v3_cfg_t const ecspi1_pads[] = {

254

MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

254

MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

255

MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

255

MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

256

MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

256

MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

257

MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

257

MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

258

MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/

258

MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/

259

};

259

};

260

261

/* ESPI */

261

/* ESPI */

262

static iomux_v3_cfg_t const ecspi3_pads[] = {

262

static iomux_v3_cfg_t const ecspi3_pads[] = {

263

MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

263

MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

264

MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

264

MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

265

MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

265

MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

266

MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

266

MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

267

MX7D_PAD_SD2_CD_B__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/

267

MX7D_PAD_SD2_CD_B__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/

268

};

268

};

269

270

/* CAN0/FLEXCAN1 */

270

/* CAN0/FLEXCAN1 */

271

static iomux_v3_cfg_t const flexcan1_pads[] = {

271

static iomux_v3_cfg_t const flexcan1_pads[] = {

272

MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),

272

MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),

273

MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),

273

MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),

274

};

274

};

275

276

/* CAN1/FLEXCAN2 */

276

/* CAN1/FLEXCAN2 */

277

static iomux_v3_cfg_t const flexcan2_pads[] = {

277

static iomux_v3_cfg_t const flexcan2_pads[] = {

278

MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),

278

MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),

279

MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),

279

MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),

280

};

280

};

281

282

/* GPIOs */

282

/* GPIOs */

283

static iomux_v3_cfg_t const gpios_pads[] = {

283

static iomux_v3_cfg_t const gpios_pads[] = {

284

MX7D_PAD_EPDC_DATA00__GPIO2_IO0 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */

284

MX7D_PAD_EPDC_DATA00__GPIO2_IO0 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */

285

MX7D_PAD_EPDC_DATA01__GPIO2_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */

285

MX7D_PAD_EPDC_DATA01__GPIO2_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */

286

MX7D_PAD_EPDC_DATA02__GPIO2_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */

286

MX7D_PAD_EPDC_DATA02__GPIO2_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */

287

MX7D_PAD_EPDC_DATA03__GPIO2_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */

287

MX7D_PAD_EPDC_DATA03__GPIO2_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */

288

MX7D_PAD_EPDC_DATA04__GPIO2_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */

288

MX7D_PAD_EPDC_DATA04__GPIO2_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */

289

MX7D_PAD_EPDC_DATA05__GPIO2_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */

289

MX7D_PAD_EPDC_DATA05__GPIO2_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */

290

MX7D_PAD_EPDC_DATA07__GPIO2_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */

290

MX7D_PAD_EPDC_DATA07__GPIO2_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */

291

MX7D_PAD_EPDC_DATA06__GPIO2_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */

291

MX7D_PAD_EPDC_DATA06__GPIO2_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */

292

MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */

292

MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */

293

MX7D_PAD_UART3_RTS_B__GPIO4_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */

293

MX7D_PAD_UART3_RTS_B__GPIO4_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */

294

MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */

294

MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */

295

};

295

};

296

297

/* LVDS channel selection, set low as single channel LVDS and high as dual channel LVDS */

297

/* LVDS channel selection, set low as single channel LVDS and high as dual channel LVDS */

298

static iomux_v3_cfg_t const lvds_ch_sel_pads[] = {

298

static iomux_v3_cfg_t const lvds_ch_sel_pads[] = {

299

MX7D_PAD_SD2_CMD__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), /* LVDS_CH_SEL */

299

MX7D_PAD_SD2_CMD__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), /* LVDS_CH_SEL */

300

};

300

};

301

302

/* Misc. pins */

302

/* Misc. pins */

303

static iomux_v3_cfg_t const misc_pads[] = {

303

static iomux_v3_cfg_t const misc_pads[] = {

304

MX7D_PAD_SD2_DATA0__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* SLEEP# */

304

MX7D_PAD_SD2_DATA0__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* SLEEP# */

305

MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGER_PRSNT# */

305

MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGER_PRSNT# */

306

MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGING# */

306

MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGING# */

307

MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /* CARRIER_STBY# */

307

MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /* CARRIER_STBY# */

308

MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), /* CARRIER_PWR_ON# */

308

MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), /* CARRIER_PWR_ON# */

309

MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* BATLOW# */

309

MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* BATLOW# */

310

MX7D_PAD_EPDC_BDR0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe_RST# */

310

MX7D_PAD_EPDC_BDR0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe_RST# */

311

MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe_WAKE# */

311

};

312

};

312

313

#ifdef CONFIG_VIDEO_MXS

314

#ifdef CONFIG_VIDEO_MXS

314

static iomux_v3_cfg_t const lcd_pads[] = {

315

static iomux_v3_cfg_t const lcd_pads[] = {

315

MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),

316

MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),

316

MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),

317

MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),

317

MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),

318

MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),

318

MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),

319

MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),

319

MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),

320

MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),

320

MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),

321

MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),

321

MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),

322

MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),

322

MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),

323

MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),

323

MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),

324

MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),

324

MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),

325

MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),

325

MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),

326

MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),

326

MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),

327

MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),

327

MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),

328

MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),

328

MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),

329

MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),

329

MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),

330

MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),

330

MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),

331

MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),

331

MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),

332

MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),

332

MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),

333

MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),

333

MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),

334

MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),

334

MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),

335

MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),

335

MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),

336

MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),

336

MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),

337

MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),

337

MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),

338

MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),

338

MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),

339

MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),

339

MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),

340

MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),

340

MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),

341

MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),

341

MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),

342

MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),

342

MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),

343

MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),

343

344

MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),

345

MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),

345

};

346

};

346

347

static iomux_v3_cfg_t const backlight_pads[] = {

348

static iomux_v3_cfg_t const backlight_pads[] = {

348

/* Backlight Enable for RGB: S127 */

349

/* Backlight Enable for RGB: S127 */

349

MX7D_PAD_GPIO1_IO02__GPIO1_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),

350

MX7D_PAD_GPIO1_IO02__GPIO1_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),

350

351

/* PWM Backlight Control: S141. Use GPIO for Brightness adjustment, duty cycle = period */

352

/* PWM Backlight Control: S141. Use GPIO for Brightness adjustment, duty cycle = period */

352

MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),

353

MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),

353

};

354

};

354

355

void do_enable_parallel_lcd(struct display_info_t const *dev)

356

void do_enable_parallel_lcd(struct display_info_t const *dev)

356

{

357

{

357

imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));

358

imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));

358

359

imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));

360

imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));

360

361

/* Reset LCD */

362

/* Reset LCD */

362

/*gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);

363

udelay(500);*/

364

gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);

363

gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);

365

364

366

/* Turn on Backlight */

365

/* Turn on Backlight */

367

gpio_direction_output(IMX_GPIO_NR(1, 2), 1);

366

gpio_direction_output(IMX_GPIO_NR(1, 2), 1);

368

367

369

/* Set Brightness to high */

368

/* Set Brightness to high */

370

gpio_direction_output(IMX_GPIO_NR(1, 0) , 1);

369

gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);

371

}

370

}

372

371

373

372

374

/* LVDS Panel for AUO G070VW01 V0 7-inch Color TFT 800x480 Panel Settings */

373

/* LVDS Panel for AUO G070VW01 V0 7-inch Color TFT 800x480 Panel Settings */

375

struct display_info_t const displays[] = {{

374

struct display_info_t const displays[] = {{

376

.bus = ELCDIF1_IPS_BASE_ADDR,

375

.bus = ELCDIF1_IPS_BASE_ADDR,

377

.addr = 0,

376

.addr = 0,

378

.pixfmt = 24,

377

.pixfmt = 24,

379

.detect = NULL,

378

.detect = NULL,

380

.enable = do_enable_parallel_lcd,

379

.enable = do_enable_parallel_lcd,

381

.mode = {

380

.mode = {

382

.name = "G070VW01",

381

.name = "G070VW01",

383

.xres = 800,

382

.xres = 800,

384

.yres = 480,

383

.yres = 480,

385

.pixclock = 31069,

384

.pixclock = 31069,

386

.left_margin = 64,

385

.left_margin = 64,

387

.right_margin = 64,

386

.right_margin = 64,

388

.upper_margin = 12,

387

.upper_margin = 12,

389

.lower_margin = 4,

388

.lower_margin = 4,

390

.hsync_len = 128,

389

.hsync_len = 128,

391

.vsync_len = 12,

390

.vsync_len = 12,

392

.sync = 0,

391

.sync = 0,

393

.vmode = FB_VMODE_NONINTERLACED

392

.vmode = FB_VMODE_NONINTERLACED

394

} } };

393

} } };

395

size_t display_count = ARRAY_SIZE(displays);

394

size_t display_count = ARRAY_SIZE(displays);

396

#endif

395

#endif

397

396

398

static void setup_iomux_uart6(void)

397

static void setup_iomux_uart6(void)

399

{

398

{

400

imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));

399

imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));

401

}

400

}

402

401

403

static void setup_iomux_uart2(void)

402

static void setup_iomux_uart2(void)

404

{

403

{

405

imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));

404

imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));

406

}

405

}

407

406

408

static void setup_iomux_uart7(void)

407

static void setup_iomux_uart7(void)

409

{

408

{

410

imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));

409

imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));

411

}

410

}

412

411

413

static void setup_iomux_uart3(void)

412

static void setup_iomux_uart3(void)

414

{

413

{

415

imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));

414

imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));

416

}

415

}

417

416

418

static void setup_iomux_reset_out(void)

417

static void setup_iomux_reset_out(void)

419

{

418

{

420

imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));

419

imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));

421

420

422

/* Set CPU RESET_OUT as Output */

421

/* Set CPU RESET_OUT as Output */

423

gpio_direction_output(IMX_GPIO_NR(2, 29) , 0);

422

gpio_direction_output(IMX_GPIO_NR(2, 29) , 0);

424

}

423

}

425

424

426

static void setup_iomux_spi1(void)

425

static void setup_iomux_spi1(void)

427

{

426

{

428

imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));

427

imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));

429

gpio_direction_output(IMX_GPIO_NR(4, 19), 0);

428

gpio_direction_output(IMX_GPIO_NR(4, 19), 0);

430

gpio_direction_output(IMX_GPIO_NR(4, 0), 0);

429

gpio_direction_output(IMX_GPIO_NR(4, 0), 0);

431

}

430

}

432

431

433

static void setup_iomux_spi3(void)

432

static void setup_iomux_spi3(void)

434

{

433

{

435

imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));

434

imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));

436

gpio_direction_output(IMX_GPIO_NR(6, 22), 0);

435

gpio_direction_output(IMX_GPIO_NR(6, 22), 0);

437

gpio_direction_output(IMX_GPIO_NR(5, 9), 0);

436

gpio_direction_output(IMX_GPIO_NR(5, 9), 0);

438

}

437

}

439

438

440

static void setup_iomux_gpios(void)

439

static void setup_iomux_gpios(void)

441

{

440

{

442

imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));

441

imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));

443

gpio_direction_output(IMX_GPIO_NR(2, 0), 0);

442

gpio_direction_output(IMX_GPIO_NR(2, 0), 0);

444

gpio_direction_output(IMX_GPIO_NR(2, 1), 0);

443

gpio_direction_output(IMX_GPIO_NR(2, 1), 0);

445

gpio_direction_output(IMX_GPIO_NR(2, 2), 0);

444

gpio_direction_output(IMX_GPIO_NR(2, 2), 0);

446

gpio_direction_output(IMX_GPIO_NR(2, 3), 0);

445

gpio_direction_output(IMX_GPIO_NR(2, 3), 0);

447

gpio_direction_output(IMX_GPIO_NR(2, 4), 0);

446

gpio_direction_output(IMX_GPIO_NR(2, 4), 0);

448

gpio_direction_input(IMX_GPIO_NR(2, 5));

447

gpio_direction_input(IMX_GPIO_NR(2, 5));

449

gpio_direction_input(IMX_GPIO_NR(2, 7));

448

gpio_direction_input(IMX_GPIO_NR(2, 7));

450

gpio_direction_input(IMX_GPIO_NR(2, 6));

449

gpio_direction_input(IMX_GPIO_NR(2, 6));

451

gpio_direction_input(IMX_GPIO_NR(4, 1));

450

gpio_direction_input(IMX_GPIO_NR(4, 1));

452

gpio_direction_input(IMX_GPIO_NR(4, 6));

451

gpio_direction_input(IMX_GPIO_NR(4, 6));

453

gpio_direction_input(IMX_GPIO_NR(4, 7));

452

gpio_direction_input(IMX_GPIO_NR(4, 7));

454

}

453

}

455

454

456

static void setup_iomux_lvds_ch_sel(void)

455

static void setup_iomux_lvds_ch_sel(void)

457

{

456

{

458

imx_iomux_v3_setup_multiple_pads(lvds_ch_sel_pads, ARRAY_SIZE(lvds_ch_sel_pads));

457

imx_iomux_v3_setup_multiple_pads(lvds_ch_sel_pads, ARRAY_SIZE(lvds_ch_sel_pads));

459

gpio_direction_output(IMX_GPIO_NR(5, 13), 0);

458

gpio_direction_output(IMX_GPIO_NR(5, 13), 0);

460

}

459

}

461

460

462

static void setup_iomux_misc(void)

461

static void setup_iomux_misc(void)

463

{

462

{

464

imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));

463

imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));

465

gpio_direction_input(IMX_GPIO_NR(5, 14));

464

gpio_direction_input(IMX_GPIO_NR(5, 14));

466

gpio_direction_input(IMX_GPIO_NR(1, 8));

465

gpio_direction_input(IMX_GPIO_NR(1, 8));

467

gpio_direction_input(IMX_GPIO_NR(1, 9));

466

gpio_direction_input(IMX_GPIO_NR(1, 9));

468

gpio_direction_input(IMX_GPIO_NR(5, 11));

467

gpio_direction_input(IMX_GPIO_NR(5, 11));

469

gpio_direction_output(IMX_GPIO_NR(6, 16), 0);

468

gpio_direction_output(IMX_GPIO_NR(6, 16), 0);

470

gpio_direction_output(IMX_GPIO_NR(6, 17), 0);

469

gpio_direction_output(IMX_GPIO_NR(6, 17), 0);

471

gpio_direction_output(IMX_GPIO_NR(2, 28), 0);

470

gpio_direction_output(IMX_GPIO_NR(2, 28), 0);

471

udelay(500);

472

gpio_direction_output(IMX_GPIO_NR(2, 28), 1);

473

gpio_direction_input(IMX_GPIO_NR(2, 31));

472

}

474

}

473

475

474

static void setup_iomux_flexcan1(void)

476

static void setup_iomux_flexcan1(void)

475

{

477

{

476

imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));

478

imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));

477

}

479

}

478

480

479

static void setup_iomux_flexcan2(void)

481

static void setup_iomux_flexcan2(void)

480

{

482

{

481

imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));

483

imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));

482

}

484

}

483

485

484

#ifdef CONFIG_FSL_ESDHC

486

#ifdef CONFIG_FSL_ESDHC

485

487

486

#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)

488

#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)

487

#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)

489

#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)

488

#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)

490

#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)

489

491

490

static struct fsl_esdhc_cfg usdhc_cfg[3] = {

492

static struct fsl_esdhc_cfg usdhc_cfg[3] = {

491

{USDHC1_BASE_ADDR, 0, 4},

493

{USDHC1_BASE_ADDR, 0, 4},

492

{USDHC3_BASE_ADDR},

494

{USDHC3_BASE_ADDR},

493

};

495

};

494

496

495

int board_mmc_get_env_dev(int devno)

497

int board_mmc_get_env_dev(int devno)

496

{

498

{

497

if (devno == 2)

499

if (devno == 2)

498

devno--;

500

devno--;

499

501

500

return devno;

502

return devno;

501

}

503

}

502

504

503

int mmc_map_to_kernel_blk(int dev_no)

505

int mmc_map_to_kernel_blk(int dev_no)

504

{

506

{

505

if (dev_no == 1)

507

if (dev_no == 1)

506

dev_no++;

508

dev_no++;

507

509

508

return dev_no;

510

return dev_no;

509

}

511

}

510

512

511

int board_mmc_getcd(struct mmc *mmc)

513

int board_mmc_getcd(struct mmc *mmc)

512

{

514

{

513

struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;

515

struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;

514

int ret = 0;

516

int ret = 0;

515

517

516

switch (cfg->esdhc_base) {

518

switch (cfg->esdhc_base) {

517

case USDHC1_BASE_ADDR:

519

case USDHC1_BASE_ADDR:

518

ret = !gpio_get_value(USDHC1_CD_GPIO);

520

ret = !gpio_get_value(USDHC1_CD_GPIO);

519

break;

521

break;

520

case USDHC3_BASE_ADDR:

522

case USDHC3_BASE_ADDR:

521

ret = 1; /* Assume uSDHC3 emmc is always present */

523

ret = 1; /* Assume uSDHC3 emmc is always present */

522

break;

524

break;

523

}

525

}

524

526

525

return ret;

527

return ret;

526

}

528

}

527

529

528

int board_mmc_init(bd_t *bis)

530

int board_mmc_init(bd_t *bis)

529

{

531

{

530

int i, ret;

532

int i, ret;

531

/*

533

/*

532

* According to the board_mmc_init() the following map is done:

534

* According to the board_mmc_init() the following map is done:

533

* (U-Boot device node) (Physical Port)

535

* (U-Boot device node) (Physical Port)

534

* mmc0 USDHC1

536

* mmc0 USDHC1

535

* mmc2 USDHC3 (eMMC)

537

* mmc2 USDHC3 (eMMC)

536

*/

538

*/

537

for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

539

for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

538

switch (i) {

540

switch (i) {

539

case 0:

541

case 0:

540

imx_iomux_v3_setup_multiple_pads(

542

imx_iomux_v3_setup_multiple_pads(

541

usdhc1_pads, ARRAY_SIZE(usdhc1_pads));

543

usdhc1_pads, ARRAY_SIZE(usdhc1_pads));

542

gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");

544

gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");

543

gpio_direction_input(USDHC1_CD_GPIO);

545

gpio_direction_input(USDHC1_CD_GPIO);

544

gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");

546

gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");

545

gpio_direction_output(USDHC1_PWR_GPIO, 0);

547

gpio_direction_output(USDHC1_PWR_GPIO, 0);

546

udelay(500);

548

udelay(500);

547

gpio_direction_output(USDHC1_PWR_GPIO, 1);

549

gpio_direction_output(USDHC1_PWR_GPIO, 1);

548

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

550

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

549

break;

551

break;

550

case 1:

552

case 1:

551

imx_iomux_v3_setup_multiple_pads(

553

imx_iomux_v3_setup_multiple_pads(

552

usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));

554

usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));

553

gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");

555

gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");

554

gpio_direction_output(USDHC3_PWR_GPIO, 0);

556

gpio_direction_output(USDHC3_PWR_GPIO, 0);

555

udelay(500);

557

udelay(500);

556

gpio_direction_output(USDHC3_PWR_GPIO, 1);

558

gpio_direction_output(USDHC3_PWR_GPIO, 1);

557

usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

559

usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

558

break;

560

break;

559

default:

561

default:

560

printf("Warning: you configured more USDHC controllers"

562

printf("Warning: you configured more USDHC controllers"

561

"(%d) than supported by the board\n", i + 1);

563

"(%d) than supported by the board\n", i + 1);

562

return -EINVAL;

564

return -EINVAL;

563

}

565

}

564

566

565

ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);

567

ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);

566

if (ret)

568

if (ret)

567

return ret;

569

return ret;

568

}

570

}

569

571

570

return 0;

572

return 0;

571

}

573

}

572

#endif

574

#endif

573

575

574

#ifdef CONFIG_FEC_MXC

576

#ifdef CONFIG_FEC_MXC

575

static iomux_v3_cfg_t const fec1_pads[] = {

577

static iomux_v3_cfg_t const fec1_pads[] = {

576

MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

578

MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

577

MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

579

MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

578

MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

580

MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

579

MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

581

MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

580

MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

582

MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

581

MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

583

MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

582

MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

584

MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

583

MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

585

MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

584

MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

586

MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

585

MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

587

MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

586

MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

588

MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

587

MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

589

MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

588

MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

590

MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

589

MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

591

MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

590

};

592

};

591

593

592

static iomux_v3_cfg_t const fec2_pads[] = {

594

static iomux_v3_cfg_t const fec2_pads[] = {

593

MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

595

MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

594

MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

596

MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

595

MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

597

MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

596

MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

598

MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

597

MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

599

MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

598

MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

600

MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

599

MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

601

MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

600

MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

602

MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

601

MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

603

MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

602

MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

604

MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

603

MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

605

MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

604

MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

606

MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

605

MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

607

MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

606

MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

608

MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

607

};

609

};

608

610

609

static void setup_iomux_fec(void)

611

static void setup_iomux_fec(void)

610

{

612

{

611

if (0 == CONFIG_FEC_ENET_DEV) {

613

if (0 == CONFIG_FEC_ENET_DEV) {

612

imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));

614

imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));

613

gpio_direction_input(IMX_GPIO_NR(7, 15));

615

gpio_direction_input(IMX_GPIO_NR(7, 15));

614

} else {

616

} else {

615

imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));

617

imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));

616

gpio_direction_input(IMX_GPIO_NR(7, 14));

618

gpio_direction_input(IMX_GPIO_NR(7, 14));

617

}

619

}

618

}

620

}

619

621

620

int board_eth_init(bd_t *bis)

622

int board_eth_init(bd_t *bis)

621

{

623

{

622

#if defined(CONFIG_MAC_ADDR_IN_EEPROM)

624

#if defined(CONFIG_MAC_ADDR_IN_EEPROM)

623

625

624

uchar env_enetaddr[6];

626

uchar env_enetaddr[6];

625

int enetaddr_found;

627

int enetaddr_found;

626

628

627

enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);

629

enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);

628

630

629

uint8_t enetaddr[8];

631

uint8_t enetaddr[8];

630

int eeprom_mac_read;

632

int eeprom_mac_read;

631

633

632

/* Read Ethernet MAC address from EEPROM */

634

/* Read Ethernet MAC address from EEPROM */

633

eeprom_mac_read = smarcfimx7_read_mac_address(enetaddr);

635

eeprom_mac_read = smarcfimx7_read_mac_address(enetaddr);

634

636

635

/*

637

/*

636

* MAC address not present in the environment

638

* MAC address not present in the environment

637

* try and read the MAC address from EEPROM flash

639

* try and read the MAC address from EEPROM flash

638

* and set it.

640

* and set it.

639

*/

641

*/

640

if (!enetaddr_found) {

642

if (!enetaddr_found) {

641

if (eeprom_mac_read)

643

if (eeprom_mac_read)

642

/* Set Ethernet MAC address from EEPROM */

644

/* Set Ethernet MAC address from EEPROM */

643

smarcfimx7_sync_env_enetaddr(enetaddr);

645

smarcfimx7_sync_env_enetaddr(enetaddr);

644

} else {

646

} else {

645

/*

647

/*

646

* MAC address present in environment compare it with

648

* MAC address present in environment compare it with

647

* the MAC address in EEPROM and warn on mismatch

649

* the MAC address in EEPROM and warn on mismatch

648

*/

650

*/

649

if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))

651

if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))

650

printf("Warning: MAC address in EEPROM don't match "

652

printf("Warning: MAC address in EEPROM don't match "

651

"with the MAC address in the environment\n");

653

"with the MAC address in the environment\n");

652

printf("Default using MAC address from environment\n");

654

printf("Default using MAC address from environment\n");

653

}

655

}

654

656

655

uchar env_enet1addr[6];

657

uchar env_enet1addr[6];

656

int enet1addr_found;

658

int enet1addr_found;

657

659

658

enet1addr_found = eth_getenv_enetaddr("eth1addr", env_enet1addr);

660

enet1addr_found = eth_getenv_enetaddr("eth1addr", env_enet1addr);

659

661

660

uint8_t enet1addr[8];

662

uint8_t enet1addr[8];

661

int eeprom_mac1_read;

663

int eeprom_mac1_read;

662

664

663

/* Read Ethernet MAC address from EEPROM */

665

/* Read Ethernet MAC address from EEPROM */

664

eeprom_mac1_read = smarcfimx7_read_mac_address(enet1addr);

666

eeprom_mac1_read = smarcfimx7_read_mac1_address(enet1addr);

665

667

666

/*

668

/*

667

* MAC address not present in the environment

669

* MAC address not present in the environment

668

* try and read the MAC address from EEPROM flash

670

* try and read the MAC address from EEPROM flash

669

* and set it.

671

* and set it.

670

*/

672

*/

671

if (!enet1addr_found) {

673

if (!enet1addr_found) {

672

if (eeprom_mac1_read)

674

if (eeprom_mac1_read)

673

/* Set Ethernet MAC address from EEPROM */

675

/* Set Ethernet MAC address from EEPROM */

674

smarcfimx7_sync_env_enet1addr(enet1addr);

676

smarcfimx7_sync_env_enet1addr(enet1addr);

675

} else {

677

} else {

676

/*

678

/*

677

* MAC address present in environment compare it with

679

* MAC address present in environment compare it with

678

* the MAC address in EEPROM and warn on mismatch

680

* the MAC address in EEPROM and warn on mismatch

679

*/

681

*/

680

if (eeprom_mac_read && memcmp(enet1addr, env_enet1addr, 6))

682

if (eeprom_mac_read && memcmp(enet1addr, env_enet1addr, 6))

681

printf("Warning: 2nd GBE MAC address in EEPROM don't match "

683

printf("Warning: 2nd GBE MAC address in EEPROM don't match "

682

"with the MAC address in the environment\n");

684

"with the MAC address in the environment\n");

683

printf("Default using 2nd GBE MAC address from environment\n");

685

printf("Default using 2nd GBE MAC address from environment\n");

684

}

686

}

685

687

686

#endif

688

#endif

687

689

688

int ret;

690

int ret;

689

691

690

setup_iomux_fec();

692

setup_iomux_fec();

691

693

692

ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,

694

ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,

693

CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);

695

CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);

694

if (ret)

696

if (ret)

695

printf("FEC1 MXC: %s:failed\n", __func__);

697

printf("FEC1 MXC: %s:failed\n", __func__);

696

698

697

return ret;

699

return ret;

698

}

700

}

699

701

700

static int setup_fec(int fec_id)

702

static int setup_fec(int fec_id)

701

{

703

{

702

struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs

704

struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs

703

= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

705

= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

704

706

705

if (0 == fec_id) {

707

if (0 == fec_id) {

706

/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/

708

/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/

707

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

709

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

708

(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |

710

(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |

709

IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);

711

IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);

710

} else {

712

} else {

711

/* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/

713

/* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/

712

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

714

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

713

(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |

715

(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |

714

IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);

716

IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);

715

}

717

}

716

718

717

return set_clk_enet(ENET_125MHz);

719

return set_clk_enet(ENET_125MHz);

718

720

719

}

721

}

720

722

721

int board_phy_config(struct phy_device *phydev)

723

int board_phy_config(struct phy_device *phydev)

722

{

724

{

723

/* enable rgmii rxc skew and phy mode select to RGMII copper */

725

/* enable rgmii rxc skew and phy mode select to RGMII copper */

724

/*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);

726

/*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);

725

phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);

727

phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);

726

phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);

728

phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);

727

phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/

729

phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/

728

730

729

if (phydev->drv->config)

731

if (phydev->drv->config)

730

phydev->drv->config(phydev);

732

phydev->drv->config(phydev);

731

return 0;

733

return 0;

732

}

734

}

733

#endif

735

#endif

734

736

735

#ifdef CONFIG_MXC_SPI

737

#ifdef CONFIG_MXC_SPI

736

/* SPI2 (SPINOR) */

738

/* SPI2 (SPINOR) */

737

static iomux_v3_cfg_t const ecspi2_pads[] = {

739

static iomux_v3_cfg_t const ecspi2_pads[] = {

738

MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

740

MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

739

MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

741

MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

740

MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

742

MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

741

MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

743

MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

742

};

744

};

743

745

744

static void setup_spinor(void)

746

static void setup_spinor(void)

745

{

747

{

746

imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));

748

imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));

747

gpio_direction_output(IMX_GPIO_NR(4, 23), 0);

749

gpio_direction_output(IMX_GPIO_NR(4, 23), 0);

748

}

750

}

749

751

750

int board_spi_cs_gpio(unsigned bus, unsigned cs)

752

int board_spi_cs_gpio(unsigned bus, unsigned cs)

751

{

753

{

752

return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 23)) : -1;

754

return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 23)) : -1;

753

}

755

}

754

#endif

756

#endif

755

757

756

#ifdef CONFIG_MXC_EPDC

758

#ifdef CONFIG_MXC_EPDC

757

static iomux_v3_cfg_t const epdc_enable_pads[] = {

759

static iomux_v3_cfg_t const epdc_enable_pads[] = {

758

MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

760

MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

759

MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

761

MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

760

MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

762

MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

761

MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

763

MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

762

MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

764

MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

763

MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

765

MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

764

MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

766

MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

765

MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

767

MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

766

MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

768

MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

767

MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

769

MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

768

MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

770

MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

769

MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),

771

MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),

770

MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

772

MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

771

MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

773

MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

772

MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

774

MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

773

MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

775

MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

774

MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),

776

MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),

775

MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),

777

MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),

776

MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

778

MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

777

MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

779

MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

778

};

780

};

779

781

780

static iomux_v3_cfg_t const epdc_disable_pads[] = {

782

static iomux_v3_cfg_t const epdc_disable_pads[] = {

781

MX7D_PAD_EPDC_DATA00__GPIO2_IO0,

783

MX7D_PAD_EPDC_DATA00__GPIO2_IO0,

782

MX7D_PAD_EPDC_DATA01__GPIO2_IO1,

784

MX7D_PAD_EPDC_DATA01__GPIO2_IO1,

783

MX7D_PAD_EPDC_DATA02__GPIO2_IO2,

785

MX7D_PAD_EPDC_DATA02__GPIO2_IO2,

784

MX7D_PAD_EPDC_DATA03__GPIO2_IO3,

786

MX7D_PAD_EPDC_DATA03__GPIO2_IO3,

785

MX7D_PAD_EPDC_DATA04__GPIO2_IO4,

787

MX7D_PAD_EPDC_DATA04__GPIO2_IO4,

786

MX7D_PAD_EPDC_DATA05__GPIO2_IO5,

788

MX7D_PAD_EPDC_DATA05__GPIO2_IO5,

787

MX7D_PAD_EPDC_DATA06__GPIO2_IO6,

789

MX7D_PAD_EPDC_DATA06__GPIO2_IO6,

788

MX7D_PAD_EPDC_DATA07__GPIO2_IO7,

790

MX7D_PAD_EPDC_DATA07__GPIO2_IO7,

789

MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,

791

MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,

790

MX7D_PAD_EPDC_SDLE__GPIO2_IO17,

792

MX7D_PAD_EPDC_SDLE__GPIO2_IO17,

791

MX7D_PAD_EPDC_SDOE__GPIO2_IO18,

793

MX7D_PAD_EPDC_SDOE__GPIO2_IO18,

792

MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,

794

MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,

793

MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,

795

MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,

794

MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,

796

MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,

795

MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,

797

MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,

796

MX7D_PAD_EPDC_GDOE__GPIO2_IO25,

798

MX7D_PAD_EPDC_GDOE__GPIO2_IO25,

797

MX7D_PAD_EPDC_GDRL__GPIO2_IO26,

799

MX7D_PAD_EPDC_GDRL__GPIO2_IO26,

798

MX7D_PAD_EPDC_GDSP__GPIO2_IO27,

800

MX7D_PAD_EPDC_GDSP__GPIO2_IO27,

799

MX7D_PAD_EPDC_BDR0__GPIO2_IO28,

801

MX7D_PAD_EPDC_BDR0__GPIO2_IO28,

800

MX7D_PAD_EPDC_BDR1__GPIO2_IO29,

802

MX7D_PAD_EPDC_BDR1__GPIO2_IO29,

801

};

803

};

802

804

803

vidinfo_t panel_info = {

805

vidinfo_t panel_info = {

804

.vl_refresh = 85,

806

.vl_refresh = 85,

805

.vl_col = 1024,

807

.vl_col = 1024,

806

.vl_row = 758,

808

.vl_row = 758,

807

.vl_pixclock = 40000000,

809

.vl_pixclock = 40000000,

808

.vl_left_margin = 12,

810

.vl_left_margin = 12,

809

.vl_right_margin = 76,

811

.vl_right_margin = 76,

810

.vl_upper_margin = 4,

812

.vl_upper_margin = 4,

811

.vl_lower_margin = 5,

813

.vl_lower_margin = 5,

812

.vl_hsync = 12,

814

.vl_hsync = 12,

813

.vl_vsync = 2,

815

.vl_vsync = 2,

814

.vl_sync = 0,

816

.vl_sync = 0,

815

.vl_mode = 0,

817

.vl_mode = 0,

816

.vl_flag = 0,

818

.vl_flag = 0,

817

.vl_bpix = 3,

819

.vl_bpix = 3,

818

.cmap = 0,

820

.cmap = 0,

819

};

821

};

820

822

821

struct epdc_timing_params panel_timings = {

823

struct epdc_timing_params panel_timings = {

822

.vscan_holdoff = 4,

824

.vscan_holdoff = 4,

823

.sdoed_width = 10,

825

.sdoed_width = 10,

824

.sdoed_delay = 20,

826

.sdoed_delay = 20,

825

.sdoez_width = 10,

827

.sdoez_width = 10,

826

.sdoez_delay = 20,

828

.sdoez_delay = 20,

827

.gdclk_hp_offs = 524,

829

.gdclk_hp_offs = 524,

828

.gdsp_offs = 327,

830

.gdsp_offs = 327,

829

.gdoe_offs = 0,

831

.gdoe_offs = 0,

830

.gdclk_offs = 19,

832

.gdclk_offs = 19,

831

.num_ce = 1,

833

.num_ce = 1,

832

};

834

};

833

835

834

static void setup_epdc_power(void)

836

static void setup_epdc_power(void)

835

{

837

{

836

/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */

838

/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */

837

struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs

839

struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs

838

= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

840

= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

839

841

840

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

842

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

841

IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);

843

IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);

842

844

843

/* Setup epdc voltage */

845

/* Setup epdc voltage */

844

846

845

/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */

847

/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */

846

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |

848

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |

847

MUX_PAD_CTRL(EPDC_PAD_CTRL));

849

MUX_PAD_CTRL(EPDC_PAD_CTRL));

848

gpio_direction_input(IMX_GPIO_NR(2, 31));

850

gpio_direction_input(IMX_GPIO_NR(2, 31));

849

851

850

/* EPDC_VCOM0 - GPIO4[14] for VCOM control */

852

/* EPDC_VCOM0 - GPIO4[14] for VCOM control */

851

imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |

853

imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |

852

MUX_PAD_CTRL(EPDC_PAD_CTRL));

854

MUX_PAD_CTRL(EPDC_PAD_CTRL));

853

855

854

/* Set as output */

856

/* Set as output */

855

gpio_direction_output(IMX_GPIO_NR(4, 14), 1);

857

gpio_direction_output(IMX_GPIO_NR(4, 14), 1);

856

858

857

/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */

859

/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */

858

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |

860

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |

859

MUX_PAD_CTRL(EPDC_PAD_CTRL));

861

MUX_PAD_CTRL(EPDC_PAD_CTRL));

860

/* Set as output */

862

/* Set as output */

861

gpio_direction_output(IMX_GPIO_NR(2, 23), 1);

863

gpio_direction_output(IMX_GPIO_NR(2, 23), 1);

862

864

863

/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */

865

/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */

864

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |

866

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |

865

MUX_PAD_CTRL(EPDC_PAD_CTRL));

867

MUX_PAD_CTRL(EPDC_PAD_CTRL));

866

/* Set as output */

868

/* Set as output */

867

gpio_direction_output(IMX_GPIO_NR(2, 30), 1);

869

gpio_direction_output(IMX_GPIO_NR(2, 30), 1);

868

}

870

}

869

871

870

static void epdc_enable_pins(void)

872

static void epdc_enable_pins(void)

871

{

873

{

872

/* epdc iomux settings */

874

/* epdc iomux settings */

873

imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,

875

imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,

874

ARRAY_SIZE(epdc_enable_pads));

876

ARRAY_SIZE(epdc_enable_pads));

875

}

877

}

876

878

877

static void epdc_disable_pins(void)

879

static void epdc_disable_pins(void)

878

{

880

{

879

/* Configure MUX settings for EPDC pins to GPIO and drive to 0 */

881

/* Configure MUX settings for EPDC pins to GPIO and drive to 0 */

880

imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,

882

imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,

881

ARRAY_SIZE(epdc_disable_pads));

883

ARRAY_SIZE(epdc_disable_pads));

882

}

884

}

883

885

884

static void setup_epdc(void)

886

static void setup_epdc(void)

885

{

887

{

886

/*** epdc Maxim PMIC settings ***/

888

/*** epdc Maxim PMIC settings ***/

887

889

888

/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */

890

/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */

889

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |

891

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |

890

MUX_PAD_CTRL(EPDC_PAD_CTRL));

892

MUX_PAD_CTRL(EPDC_PAD_CTRL));

891

893

892

/* EPDC_VCOM0 - GPIO4[14] for VCOM control */

894

/* EPDC_VCOM0 - GPIO4[14] for VCOM control */

893

imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |

895

imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |

894

MUX_PAD_CTRL(EPDC_PAD_CTRL));

896

MUX_PAD_CTRL(EPDC_PAD_CTRL));

895

897

896

/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */

898

/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */

897

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |

899

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |

898

MUX_PAD_CTRL(EPDC_PAD_CTRL));

900

MUX_PAD_CTRL(EPDC_PAD_CTRL));

899

901

900

/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */

902

/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */

901

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |

903

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |

902

MUX_PAD_CTRL(EPDC_PAD_CTRL));

904

MUX_PAD_CTRL(EPDC_PAD_CTRL));

903

905

904

/* Set pixel clock rates for EPDC in clock.c */

906

/* Set pixel clock rates for EPDC in clock.c */

905

907

906

panel_info.epdc_data.wv_modes.mode_init = 0;

908

panel_info.epdc_data.wv_modes.mode_init = 0;

907

panel_info.epdc_data.wv_modes.mode_du = 1;

909

panel_info.epdc_data.wv_modes.mode_du = 1;

908

panel_info.epdc_data.wv_modes.mode_gc4 = 3;

910

panel_info.epdc_data.wv_modes.mode_gc4 = 3;

909

panel_info.epdc_data.wv_modes.mode_gc8 = 2;

911

panel_info.epdc_data.wv_modes.mode_gc8 = 2;

910

panel_info.epdc_data.wv_modes.mode_gc16 = 2;

912

panel_info.epdc_data.wv_modes.mode_gc16 = 2;

911

panel_info.epdc_data.wv_modes.mode_gc32 = 2;

913

panel_info.epdc_data.wv_modes.mode_gc32 = 2;

912

914

913

panel_info.epdc_data.epdc_timings = panel_timings;

915

panel_info.epdc_data.epdc_timings = panel_timings;

914

916

915

setup_epdc_power();

917

setup_epdc_power();

916

}

918

}

917

919

918

void epdc_power_on(void)

920

void epdc_power_on(void)

919

{

921

{

920

unsigned int reg;

922

unsigned int reg;

921

struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;

923

struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;

922

924

923

/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */

925

/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */

924

gpio_set_value(IMX_GPIO_NR(2, 30), 1);

926

gpio_set_value(IMX_GPIO_NR(2, 30), 1);

925

udelay(1000);

927

udelay(1000);

926

928

927

/* Enable epdc signal pin */

929

/* Enable epdc signal pin */

928

epdc_enable_pins();

930

epdc_enable_pins();

929

931

930

/* Set PMIC Wakeup to high - enable Display power */

932

/* Set PMIC Wakeup to high - enable Display power */

931

gpio_set_value(IMX_GPIO_NR(2, 23), 1);

933

gpio_set_value(IMX_GPIO_NR(2, 23), 1);

932

934

933

/* Wait for PWRGOOD == 1 */

935

/* Wait for PWRGOOD == 1 */

934

while (1) {

936

while (1) {

935

reg = readl(&gpio_regs->gpio_psr);

937

reg = readl(&gpio_regs->gpio_psr);

936

if (!(reg & (1 << 31)))

938

if (!(reg & (1 << 31)))

937

break;

939

break;

938

940

939

udelay(100);

941

udelay(100);

940

}

942

}

941

943

942

/* Enable VCOM */

944

/* Enable VCOM */

943

gpio_set_value(IMX_GPIO_NR(4, 14), 1);

945

gpio_set_value(IMX_GPIO_NR(4, 14), 1);

944

946

945

udelay(500);

947

udelay(500);

946

}

948

}

947

949

948

void epdc_power_off(void)

950

void epdc_power_off(void)

949

{

951

{

950

/* Set PMIC Wakeup to low - disable Display power */

952

/* Set PMIC Wakeup to low - disable Display power */

951

gpio_set_value(IMX_GPIO_NR(2, 23), 0);

953

gpio_set_value(IMX_GPIO_NR(2, 23), 0);

952

954

953

/* Disable VCOM */

955

/* Disable VCOM */

954

gpio_set_value(IMX_GPIO_NR(4, 14), 0);

956

gpio_set_value(IMX_GPIO_NR(4, 14), 0);

955

957

956

epdc_disable_pins();

958

epdc_disable_pins();

957

959

958

/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */

960

/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */

959

gpio_set_value(IMX_GPIO_NR(2, 30), 0);

961

gpio_set_value(IMX_GPIO_NR(2, 30), 0);

960

}

962

}

961

#endif

963

#endif

962

964

963

#ifdef CONFIG_USB_EHCI_MX7

965

#ifdef CONFIG_USB_EHCI_MX7

964

static iomux_v3_cfg_t const usb_otg1_pads[] = {

966

static iomux_v3_cfg_t const usb_otg1_pads[] = {

965

MX7D_PAD_GPIO1_IO12__USB_OTG1_ID | MUX_PAD_CTRL(WEAK_PULLUP),

967

MX7D_PAD_GPIO1_IO12__USB_OTG1_ID | MUX_PAD_CTRL(WEAK_PULLUP),

966

/* OTG1 Power Enable */

968

/* OTG1 Power Enable */

967

MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

969

MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

968

/* OTG1 Over Current */

970

/* OTG1 Over Current */

969

MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),

971

MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),

970

972

971

};

973

};

972

974

973

static iomux_v3_cfg_t const usb_otg2_pads[] = {

975

static iomux_v3_cfg_t const usb_otg2_pads[] = {

974

/* OTG2 Power Enable */

976

/* OTG2 Power Enable */

975

MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

977

MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

976

/* OTG2 Over Current */

978

/* OTG2 Over Current */

977

MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),

979

MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),

978

};

980

};

979

981

980

static void setup_usb(void)

982

static void setup_usb(void)

981

{

983

{

982

imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,

984

imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,

983

ARRAY_SIZE(usb_otg1_pads));

985

ARRAY_SIZE(usb_otg1_pads));

984

gpio_direction_input(IMX_GPIO_NR(1, 4));

986

gpio_direction_input(IMX_GPIO_NR(1, 4));

985

987

986

imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,

988

imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,

987

ARRAY_SIZE(usb_otg2_pads));

989

ARRAY_SIZE(usb_otg2_pads));

988

gpio_direction_input(IMX_GPIO_NR(1, 6));

990

gpio_direction_input(IMX_GPIO_NR(1, 6));

989

}

991

}

990

992

991

int board_usb_phy_mode(int port)

993

int board_usb_phy_mode(int port)

992

{

994

{

993

if (port == 0)

995

if (port == 0)

994

return usb_phy_mode(port);

996

return usb_phy_mode(port);

995

else

997

else

996

return USB_INIT_HOST;

998

return USB_INIT_HOST;

997

}

999

}

998

#endif

1000

#endif

999

1001

1000

int board_early_init_f(void)

1002

int board_early_init_f(void)

1001

{

1003

{

1002

setup_iomux_reset_out();

1004

setup_iomux_reset_out();

1003

setup_iomux_uart6();

1005

setup_iomux_uart6();

1004

setup_iomux_uart2();

1006

setup_iomux_uart2();

1005

setup_iomux_uart7();

1007

setup_iomux_uart7();

1006

setup_iomux_uart3();

1008

setup_iomux_uart3();

1007

1009

1008

#ifdef CONFIG_SYS_I2C_MXC

1010

#ifdef CONFIG_SYS_I2C_MXC

1009

setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

1011

setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

1010

setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);

1012

setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);

1011

setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);

1013

setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);

1012

setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);

1014

setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);

1013

#endif

1015

#endif

1014

1016

1015

#ifdef CONFIG_MXC_SPI

1017

#ifdef CONFIG_MXC_SPI

1016

setup_spinor();

1018

setup_spinor();

1017

#endif

1019

#endif

1018

1020

1019

#ifdef CONFIG_USB_EHCI_MX7

1021

#ifdef CONFIG_USB_EHCI_MX7

1020

setup_usb();

1022

setup_usb();

1021

#endif

1023

#endif

1022

setup_iomux_spi1();

1024

setup_iomux_spi1();

1023

setup_iomux_spi3();

1025

setup_iomux_spi3();

1024

setup_iomux_flexcan1();

1026

setup_iomux_flexcan1();

1025

setup_iomux_flexcan2();

1027

setup_iomux_flexcan2();

1026

setup_iomux_gpios();

1028

setup_iomux_gpios();

1027

setup_iomux_lvds_ch_sel();

1029

setup_iomux_lvds_ch_sel();

1028

setup_iomux_misc();

1030

setup_iomux_misc();

1029

1031

1030

return 0;

1032

return 0;

1031

}

1033

}

1032

1034

1033

int board_init(void)

1035

int board_init(void)

1034

{

1036

{

1035

/* address of boot parameters */

1037

/* address of boot parameters */

1036

gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

1038

gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

1037

1039

1038

#ifdef CONFIG_FEC_MXC

1040

#ifdef CONFIG_FEC_MXC

1039

setup_fec(CONFIG_FEC_ENET_DEV);

1041

setup_fec(CONFIG_FEC_ENET_DEV);

1040

#endif

1042

#endif

1041

1043

1042

#ifdef CONFIG_NAND_MXS

1044

#ifdef CONFIG_NAND_MXS

1043

setup_gpmi_nand();

1045

setup_gpmi_nand();

1044

#endif

1046

#endif

1045

1047

1046

#ifdef CONFIG_FSL_QSPI

1048

#ifdef CONFIG_FSL_QSPI

1047

board_qspi_init();

1049

board_qspi_init();

1048

#endif

1050

#endif

1049

1051

1050

return 0;

1052

return 0;

1051

}

1053

}

1052

1054

1053

#ifdef CONFIG_CMD_BMODE

1055

#ifdef CONFIG_CMD_BMODE

1054

static const struct boot_mode board_boot_modes[] = {

1056

static const struct boot_mode board_boot_modes[] = {

1055

/* 4 bit bus width */

1057

/* 4 bit bus width */

1056

{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},

1058

{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},

1057

{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},

1059

{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},

1058

/* TODO: Nand */

1060

/* TODO: Nand */

1059

{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},

1061

{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},

1060

{NULL, 0},

1062

{NULL, 0},

1061

};

1063

};

1062

#endif

1064

#endif

1063

1065

1064

#ifdef CONFIG_POWER

1066

#ifdef CONFIG_POWER

1065

#define I2C_PMIC 0

1067

#define I2C_PMIC 0

1066

int power_init_board(void)

1068

int power_init_board(void)

1067

{

1069

{

1068

struct pmic *p;

1070

struct pmic *p;

1069

int ret;

1071

int ret;

1070

unsigned int reg, rev_id;

1072

unsigned int reg, rev_id;

1071

1073

1072

ret = power_pfuze3000_init(I2C_PMIC);

1074

ret = power_pfuze3000_init(I2C_PMIC);

1073

if (ret)

1075

if (ret)

1074

return ret;

1076

return ret;

1075

1077

1076

p = pmic_get("PFUZE3000");

1078

p = pmic_get("PFUZE3000");

1077

ret = pmic_probe(p);

1079

ret = pmic_probe(p);

1078

if (ret)

1080

if (ret)

1079

return ret;

1081

return ret;

1080

1082

1081

pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);

1083

pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);

1082

pmic_reg_read(p, PFUZE3000_REVID, &rev_id);

1084

pmic_reg_read(p, PFUZE3000_REVID, &rev_id);

1083

printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);

1085

printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);

1084

1086

1085

/* disable Low Power Mode during standby mode */

1087

/* disable Low Power Mode during standby mode */

1086

pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);

1088

pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);

1087

reg |= 0x1;

1089

reg |= 0x1;

1088

pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);

1090

pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);

1089

1091

1090

/* SW1A/1B mode set to APS/APS */

1092

/* SW1A/1B mode set to APS/APS */

1091

reg = 0x8;

1093

reg = 0x8;

1092

pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);

1094

pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);

1093

pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);

1095

pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);

1094

1096

1095

/* SW1A/1B standby voltage set to 0.975V */

1097

/* SW1A/1B standby voltage set to 0.975V */

1096

reg = 0xb;

1098

reg = 0xb;

1097

pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);

1099

pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);

1098

pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);

1100

pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);

1099

1101

1100

/* decrease SW1B normal voltage to 0.975V */

1102

/* decrease SW1B normal voltage to 0.975V */

1101

pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);

1103

pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);

1102

reg &= ~0x1f;

1104

reg &= ~0x1f;

1103

reg |= PFUZE3000_SW1AB_SETP(975);

1105

reg |= PFUZE3000_SW1AB_SETP(975);

1104

pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);

1106

pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);

1105

1107

1106

return 0;

1108

return 0;

1107

}

1109

}

1108

#endif

1110

#endif

1109

1111

1110

int board_late_init(void)

1112

int board_late_init(void)

1111

{

1113

{

1112

struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

1114

struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

1113

#ifdef CONFIG_CMD_BMODE

1115

#ifdef CONFIG_CMD_BMODE

1114

add_board_boot_modes(board_boot_modes);

1116

add_board_boot_modes(board_boot_modes);

1115

#endif

1117

#endif

1116

1118

1117

#ifdef CONFIG_ENV_IS_IN_MMC

1119

#ifdef CONFIG_ENV_IS_IN_MMC

1118

board_late_mmc_env_init();

1120

board_late_mmc_env_init();

1119

#endif

1121

#endif

1120

1122

1121

imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));

1123

imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));

1122

1124

1123

set_wdog_reset(wdog);

1125

set_wdog_reset(wdog);

1124

1126

1125

/* Check Board Information */

1127

/* Check Board Information */

1126

setup_i2c(1, CONFIG_SYS_I2C_SPEED,

1128

setup_i2c(1, CONFIG_SYS_I2C_SPEED,

1127

0x50, &i2c_pad_info2);

1129

0x50, &i2c_pad_info2);

1128

1130

1129

struct smarcfimx7_id header;

1131

struct smarcfimx7_id header;

1130

1132

1131

if (read_eeprom(&header) < 0)

1133

if (read_eeprom(&header) < 0)

1132

puts("Could not get board ID.\n");

1134

puts("Could not get board ID.\n");

1133

1135

1134

puts("---------Embedian SMARC-FiMX7------------\n");

1136

puts("---------Embedian SMARC-FiMX7------------\n");

1135

printf("Board ID: %.*s\n",

1137

printf("Board ID: %.*s\n",

1136

sizeof(header.name), header.name);

1138

sizeof(header.name), header.name);

1137

printf("Board Revision: %.*s\n",

1139

printf("Board Revision: %.*s\n",

1138

sizeof(header.version), header.version);

1140

sizeof(header.version), header.version);

1139

printf("Board Serial#: %.*s\n",

1141

printf("Board Serial#: %.*s\n",

1140

sizeof(header.serial), header.serial);

1142

sizeof(header.serial), header.serial);

1141

puts("-----------------------------------------\n");

1143

puts("-----------------------------------------\n");

1142

1144

1143

/* SMARC BOOT_SEL*/

1145

/* SMARC BOOT_SEL*/

1144

if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1146

if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1145

puts("BOOT_SEL Detected: OFF OFF OFF, unsupported boot up device: SATA...\n");

1147

puts("BOOT_SEL Detected: OFF OFF OFF, unsupported boot up device: SATA...\n");

1146

hang();

1148

hang();

1147

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1149

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1148

puts("BOOT_SEL Detected: OFF OFF ON, unsupported boot up device: NAND...\n");

1150

puts("BOOT_SEL Detected: OFF OFF ON, unsupported boot up device: NAND...\n");

1149

hang();

1151

hang();

1150

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1152

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1151

puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier eSPI...\n");

1153

puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier eSPI...\n");

1152

hang();

1154

hang();

1153

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1155

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1154

puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n");

1156

puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n");

1155

setenv_ulong("mmcdev", 0);

1157

setenv_ulong("mmcdev", 0);

1156

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1158

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1157

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1159

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1158

puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n");

1160

puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n");

1159

setenv_ulong("mmcdev", 1);

1161

setenv_ulong("mmcdev", 1);

1160

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1162

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1161

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1163

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1162

puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");

1164

puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");

1163

setenv("bootcmd", "run netboot;");

1165

setenv("bootcmd", "run netboot;");

1164

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1166

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1165

puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier SPI...\n");

1167

puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier SPI...\n");

1166

hang();

1168

hang();

1167

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1169

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1168

puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n");

1170

puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n");

1169

setenv_ulong("mmcdev", 1);

1171

setenv_ulong("mmcdev", 1);

1170

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1172

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1171

} else {

1173

} else {

1172

puts("unsupported boot devices\n");

1174

puts("unsupported boot devices\n");

1173

hang();

1175

hang();

1174

}

1176

}

1175

1177

1176

return 0;

1178

return 0;

1177

}

1179

}

1178

1180

1179

#ifdef CONFIG_FSL_FASTBOOT

1181

#ifdef CONFIG_FSL_FASTBOOT

1180

void board_fastboot_setup(void)

1182

void board_fastboot_setup(void)

1181

{

1183

{

1182

switch (get_boot_device()) {

1184

switch (get_boot_device()) {

1183

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1185

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1184

case SD1_BOOT:

1186

case SD1_BOOT:

1185

case MMC1_BOOT:

1187

case MMC1_BOOT:

1186

if (!getenv("fastboot_dev"))

1188

if (!getenv("fastboot_dev"))

1187

setenv("fastboot_dev", "mmc0");

1189

setenv("fastboot_dev", "mmc0");

1188

if (!getenv("bootcmd"))

1190

if (!getenv("bootcmd"))

1189

setenv("bootcmd", "boota mmc0");

1191

setenv("bootcmd", "boota mmc0");

1190

break;

1192

break;

1191

case SD3_BOOT:

1193

case SD3_BOOT:

1192

case MMC3_BOOT:

1194

case MMC3_BOOT:

1193

if (!getenv("fastboot_dev"))

1195

if (!getenv("fastboot_dev"))

1194

setenv("fastboot_dev", "mmc1");

1196

setenv("fastboot_dev", "mmc1");

1195

if (!getenv("bootcmd"))

1197

if (!getenv("bootcmd"))

1196

setenv("bootcmd", "boota mmc1");

1198

setenv("bootcmd", "boota mmc1");

1197

break;

1199

break;

1198

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1200

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1199

default:

1201

default:

1200

printf("unsupported boot devices\n");

1202

printf("unsupported boot devices\n");

1201

break;

1203

break;

1202

}

1204

}

1203

}

1205

}

1204

1206

1205

#ifdef CONFIG_ANDROID_RECOVERY

1207

#ifdef CONFIG_ANDROID_RECOVERY

1206

1208

1207

/* Use LID# for recovery key */

1209

/* Use LID# for recovery key */

1208

#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10)

1210

#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10)

1209

iomux_v3_cfg_t const recovery_key_pads[] = {

1211

iomux_v3_cfg_t const recovery_key_pads[] = {

1210

(MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)),

1212

(MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)),

1211

};

1213

};

1212

1214

1213

int check_recovery_cmd_file(void)

1215

int check_recovery_cmd_file(void)

1214

{

1216

{

1215

int button_pressed = 0;

1217

int button_pressed = 0;

1216

int recovery_mode = 0;

1218

int recovery_mode = 0;

1217

1219

1218

recovery_mode = recovery_check_and_clean_flag();

1220

recovery_mode = recovery_check_and_clean_flag();

1219

1221

1220

/* Check Recovery Combo Button press or not. */

1222

/* Check Recovery Combo Button press or not. */

1221

imx_iomux_v3_setup_multiple_pads(recovery_key_pads,

1223

imx_iomux_v3_setup_multiple_pads(recovery_key_pads,

1222

ARRAY_SIZE(recovery_key_pads));

1224

ARRAY_SIZE(recovery_key_pads));

1223

1225

1224

gpio_direction_input(GPIO_VOL_DN_KEY);

1226

gpio_direction_input(GPIO_VOL_DN_KEY);

1225

1227

1226

if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */

1228

if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */

1227

button_pressed = 1;

1229

button_pressed = 1;

1228

printf("Recovery key pressed\n");

1230

printf("Recovery key pressed\n");

1229

}

1231

}

1230

1232

1231

return recovery_mode || button_pressed;

1233

return recovery_mode || button_pressed;

1232

}

1234

}

1233

1235

1234

void board_recovery_setup(void)

1236

void board_recovery_setup(void)

1235

{

1237

{

1236

int bootdev = get_boot_device();

1238

int bootdev = get_boot_device();

1237

1239

1238

switch (bootdev) {

1240

switch (bootdev) {

1239

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1241

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1240

case SD1_BOOT:

1242

case SD1_BOOT:

1241

case MMC1_BOOT:

1243

case MMC1_BOOT:

1242

if (!getenv("bootcmd_android_recovery"))

1244

if (!getenv("bootcmd_android_recovery"))

1243

setenv("bootcmd_android_recovery", "boota mmc0 recovery");

1245

setenv("bootcmd_android_recovery", "boota mmc0 recovery");

1244

break;

1246

break;

1245

case SD3_BOOT:

1247

case SD3_BOOT:

1246

case MMC3_BOOT:

1248

case MMC3_BOOT:

1247

if (!getenv("bootcmd_android_recovery"))

1249

if (!getenv("bootcmd_android_recovery"))

1248

setenv("bootcmd_android_recovery", "boota mmc1 recovery");

1250

setenv("bootcmd_android_recovery", "boota mmc1 recovery");

1249

break;

1251

break;

1250

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1252

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1251

default:

1253

default:

1252

printf("Unsupported bootup device for recovery: dev: %d\n",

1254

printf("Unsupported bootup device for recovery: dev: %d\n",

1253

bootdev);

1255

bootdev);

1254

return;

1256

return;

1255

}

1257

}

1256

1258

1257

printf("setup env for recovery..\n");

1259

printf("setup env for recovery..\n");

1258

setenv("bootcmd", "run bootcmd_android_recovery");

1260

setenv("bootcmd", "run bootcmd_android_recovery");

1259

}

1261

}

1260

#endif /*CONFIG_ANDROID_RECOVERY*/

1262

#endif /*CONFIG_ANDROID_RECOVERY*/

1261

1263

1262

#endif /*CONFIG_FSL_FASTBOOT*/

1264

#endif /*CONFIG_FSL_FASTBOOT*/

GITLAB

Pinmux fixed for rev. 00B0 i.MX7 SMARC module

 /*
  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx7-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <power/pmic.h>
 #include <power/pfuze3000_pmic.h>
 #include "pfuze.h"
 #include <pwm.h>
 #include <i2c.h>
 #include <asm/imx-common/mxc_i2c.h>
 #include <asm/arch/crm_regs.h>
 #include <usb.h>
 #include <usb/ehci-fsl.h>
 #if defined(CONFIG_MXC_EPDC)
 #include <lcd.h>
 #include <mxc_epdc_fb.h>
 #endif
 #include <asm/imx-common/video.h>
 #include "smarcfimx7.h"
 #ifdef CONFIG_FSL_FASTBOOT
 #include <fsl_fastboot.h>
 #ifdef CONFIG_ANDROID_RECOVERY
 #include <recovery.h>
 #endif
 #endif /*CONFIG_FSL_FASTBOOT*/
 DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
 	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
 	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
 	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
         PAD_CTL_DSE_3P3V_49OHM)
 #define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 #define BUTTON_PAD_CTRL    (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM)
 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
 #define EPDC_PAD_CTRL	0x0
 #define WEAK_PULLUP (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM | \
 	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /*
  * Read header information from EEPROM into global structure.
  */
 static int read_eeprom(struct smarcfimx7_id *header)
 {
         i2c_set_bus_num(1);
         /* Check if baseboard eeprom is available */
         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
                 puts("Could not probe the EEPROM; something fundamentally "
                         "wrong on the I2C bus.\n");
                 return -ENODEV;
         }
         /* read the eeprom using i2c */
         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
                      sizeof(struct smarcfimx7_id))) {
                 puts("Could not read the EEPROM; something fundamentally"
                         " wrong on the I2C bus.\n");
                 return -EIO;
         }
         if (header->magic != 0xEE3355AA) {
                 /*
                  * read the eeprom using i2c again,
                  * but use only a 1 byte address
                  */
                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
                              sizeof(struct smarcfimx7_id))) {
                         puts("Could not read the EEPROM; something "
                                 "fundamentally wrong on the I2C bus.\n");
                         return -EIO;
                 }
                 if (header->magic != 0xEE3355AA) {
                         printf("Incorrect magic number (0x%x) in EEPROM\n",
                                         header->magic);
                         return -EINVAL;
                 }
         }
         return 0;
 }
 /* I2C1 for PMIC (I2C_PM)*/
 static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
 		.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
 		.gp = IMX_GPIO_NR(4, 8),
 	},
 	.sda = {
 		.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
 		.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
 		.gp = IMX_GPIO_NR(4, 9),
 	},
 };
 /* I2C2 for I2C_GP */
 static struct i2c_pads_info i2c_pad_info2 = {
         .scl = {
                 .i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,
                 .gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,
                 .gp = IMX_GPIO_NR(4, 10),
         },
         .sda = {
                 .i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,
                 .gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,
                 .gp = IMX_GPIO_NR(4, 11),
         },
 };
 /* I2C3 for I2C_LCD */
 static struct i2c_pads_info i2c_pad_info3 = {
 	.scl = {
 		.i2c_mode = MX7D_PAD_I2C3_SCL__I2C3_SCL | PC,
 		.gpio_mode = MX7D_PAD_I2C3_SCL__GPIO4_IO12 | PC,
 		.gp = IMX_GPIO_NR(4, 12),
 	},
 	.sda = {
 		.i2c_mode = MX7D_PAD_I2C3_SDA__I2C3_SDA | PC,
 		.gpio_mode = MX7D_PAD_I2C3_SDA__GPIO4_IO13 | PC,
 		.gp = IMX_GPIO_NR(4, 13),
 	},
 };
 /* I2C4 for I2C_CAM1 */
 static struct i2c_pads_info i2c_pad_info4 = {
         .scl = {
                 .i2c_mode = MX7D_PAD_I2C4_SCL__I2C4_SCL | PC,
                 .gpio_mode = MX7D_PAD_I2C4_SCL__GPIO4_IO14 | PC,
                 .gp = IMX_GPIO_NR(4, 14),
         },
         .sda = {
                 .i2c_mode = MX7D_PAD_I2C4_SDA__I2C4_SDA | PC,
                 .gpio_mode = MX7D_PAD_I2C4_SDA__GPIO4_IO15 | PC,
                 .gp = IMX_GPIO_NR(4, 15),
         },
 };
 #endif
 int dram_init(void)
 {
 	gd->ram_size = PHYS_SDRAM_SIZE;
 	return 0;
 }
 static iomux_v3_cfg_t const wdog_pads[] = {
-	MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 /* SER0/UART6 */
 static iomux_v3_cfg_t const uart6_pads[] = {
         MX7D_PAD_EPDC_DATA09__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA08__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* SER1/UART2 */
 static iomux_v3_cfg_t const uart2_pads[] = {
         MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* SER2/UART7 */
 static iomux_v3_cfg_t const uart7_pads[] = {
         MX7D_PAD_EPDC_DATA13__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA12__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* SER3/UART3 Debug Port */
 static iomux_v3_cfg_t const uart3_pads[] = {
         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* RESET_OUT# */
 static iomux_v3_cfg_t const reset_out_pads[] = {
         MX7D_PAD_EPDC_BDR1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 /* SD Card */
 static iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 	/*CD */
         MX7D_PAD_SD1_WP__GPIO5_IO1  | MUX_PAD_CTRL(NO_PAD_CTRL), 	/* WP */
 	MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* SDIO_PWR_EN */
 };
 /* eMMC */
 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
 	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_STROBE__SD3_STROBE	 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 /* SPI0 */
 static iomux_v3_cfg_t const ecspi1_pads[] = {
         MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL),    /*SS0#*/
         MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/
 };
 /* ESPI */
 static iomux_v3_cfg_t const ecspi3_pads[] = {
         MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL),  /*SS0#*/
         MX7D_PAD_SD2_CD_B__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL),      /*SS2#*/
 };
 /* CAN0/FLEXCAN1 */
 static iomux_v3_cfg_t const flexcan1_pads[] = {
         MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),
         MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 /* CAN1/FLEXCAN2 */
 static iomux_v3_cfg_t const flexcan2_pads[] = {
         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),
         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 /* GPIOs */
 static iomux_v3_cfg_t const gpios_pads[] = {
         MX7D_PAD_EPDC_DATA00__GPIO2_IO0 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO0 */
         MX7D_PAD_EPDC_DATA01__GPIO2_IO1 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO1 */
         MX7D_PAD_EPDC_DATA02__GPIO2_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO2 */
         MX7D_PAD_EPDC_DATA03__GPIO2_IO3 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO3 */
         MX7D_PAD_EPDC_DATA04__GPIO2_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO4 */
         MX7D_PAD_EPDC_DATA05__GPIO2_IO5 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO6 */
         MX7D_PAD_EPDC_DATA07__GPIO2_IO7 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO7 */
         MX7D_PAD_EPDC_DATA06__GPIO2_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO8 */
         MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | MUX_PAD_CTRL(WEAK_PULLUP),  /* GPIO9 */
         MX7D_PAD_UART3_RTS_B__GPIO4_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO10 */
         MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO11 */
 };
 /* LVDS channel selection, set low as single channel LVDS and high as dual channel LVDS */
 static iomux_v3_cfg_t const lvds_ch_sel_pads[] = {
         MX7D_PAD_SD2_CMD__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),       /* LVDS_CH_SEL */
 };
 /* Misc. pins */
 static iomux_v3_cfg_t const misc_pads[] = {
         MX7D_PAD_SD2_DATA0__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),     /* SLEEP# */
-        MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP),     /* CHARGER_PRSNT# */
+        MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), 	/* CHARGER_PRSNT# */
         MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP),     /* CHARGING# */
         MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),  /* CARRIER_STBY# */
         MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),  /* CARRIER_PWR_ON# */
         MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),   /* BATLOW# */
 	MX7D_PAD_EPDC_BDR0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),   	/* PCIe_RST# */
+        MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* PCIe_WAKE# */
 };
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lcd_pads[] = {
 	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_RESET__GPIO3_IO4	| MUX_PAD_CTRL(LCD_PAD_CTRL),
 };
 static iomux_v3_cfg_t const backlight_pads[] = {
         /* Backlight Enable for RGB: S127 */
 	MX7D_PAD_GPIO1_IO02__GPIO1_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),
         /* PWM Backlight Control: S141. Use GPIO for Brightness adjustment, duty cycle = period */
-       	MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       	MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 void do_enable_parallel_lcd(struct display_info_t const *dev)
 {
 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 	imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 	/* Reset LCD */
-	/*gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
-	udelay(500);*/
 	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
 	/* Turn on Backlight */
         gpio_direction_output(IMX_GPIO_NR(1, 2), 1);
         /* Set Brightness to high */
-        gpio_direction_output(IMX_GPIO_NR(1, 0) , 1);
+       	gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
 }
 /* LVDS Panel for AUO G070VW01 V0 7-inch Color TFT 800x480 Panel Settings */
 struct display_info_t const displays[] = {{
         .bus = ELCDIF1_IPS_BASE_ADDR,
         .addr = 0,
         .pixfmt = 24,
         .detect = NULL,
         .enable = do_enable_parallel_lcd,
         .mode   = {
                 .name          	= "G070VW01",
                 .xres           = 800,
                 .yres           = 480,
                 .pixclock       = 31069,
                 .left_margin    = 64,
                 .right_margin   = 64,
                 .upper_margin   = 12,
                 .lower_margin   = 4,
                 .hsync_len      = 128,
                 .vsync_len      = 12,
                 .sync           = 0,
                 .vmode          = FB_VMODE_NONINTERLACED
 } } };
 size_t display_count = ARRAY_SIZE(displays);
 #endif
 static void setup_iomux_uart6(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
 }
 static void setup_iomux_uart2(void)
 {
         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 }
 static void setup_iomux_uart7(void)
 {
         imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));
 }
 static void setup_iomux_uart3(void)
 {
         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 }
 static void setup_iomux_reset_out(void)
 {
         imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));
         /* Set CPU RESET_OUT as Output */
         gpio_direction_output(IMX_GPIO_NR(2, 29) , 0);
 }
 static void setup_iomux_spi1(void)
 {
         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
         gpio_direction_output(IMX_GPIO_NR(4, 19), 0);
         gpio_direction_output(IMX_GPIO_NR(4, 0), 0);
 }
 static void setup_iomux_spi3(void)
 {
         imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
         gpio_direction_output(IMX_GPIO_NR(6, 22), 0);
         gpio_direction_output(IMX_GPIO_NR(5, 9), 0);
 }
 static void setup_iomux_gpios(void)
 {
         imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));
         gpio_direction_output(IMX_GPIO_NR(2, 0), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 1), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 2), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 3), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 4), 0);
         gpio_direction_input(IMX_GPIO_NR(2, 5));
         gpio_direction_input(IMX_GPIO_NR(2, 7));
         gpio_direction_input(IMX_GPIO_NR(2, 6));
         gpio_direction_input(IMX_GPIO_NR(4, 1));
         gpio_direction_input(IMX_GPIO_NR(4, 6));
         gpio_direction_input(IMX_GPIO_NR(4, 7));
 }
 static void setup_iomux_lvds_ch_sel(void)
 {
         imx_iomux_v3_setup_multiple_pads(lvds_ch_sel_pads, ARRAY_SIZE(lvds_ch_sel_pads));
         gpio_direction_output(IMX_GPIO_NR(5, 13), 0);
 }
 static void setup_iomux_misc(void)
 {
         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
         gpio_direction_input(IMX_GPIO_NR(5, 14));
         gpio_direction_input(IMX_GPIO_NR(1, 8));
         gpio_direction_input(IMX_GPIO_NR(1, 9));
         gpio_direction_input(IMX_GPIO_NR(5, 11));
         gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
         gpio_direction_output(IMX_GPIO_NR(6, 17), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
+       	udelay(500);
+        gpio_direction_output(IMX_GPIO_NR(2, 28), 1);
+        gpio_direction_input(IMX_GPIO_NR(2, 31));
 }
 static void setup_iomux_flexcan1(void)
 {
         imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));
 }
 static void setup_iomux_flexcan2(void)
 {
         imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));
 }
 #ifdef CONFIG_FSL_ESDHC
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 0)
 #define USDHC1_PWR_GPIO	IMX_GPIO_NR(5, 2)
 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC1_BASE_ADDR, 0, 4},
 	{USDHC3_BASE_ADDR},
 };
 int board_mmc_get_env_dev(int devno)
 {
 	if (devno == 2)
 		devno--;
 	return devno;
 }
 int mmc_map_to_kernel_blk(int dev_no)
 {
 	if (dev_no == 1)
 		dev_no++;
 	return dev_no;
 }
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret = 0;
 	switch (cfg->esdhc_base) {
 	case USDHC1_BASE_ADDR:
 		ret = !gpio_get_value(USDHC1_CD_GPIO);
 		break;
 	case USDHC3_BASE_ADDR:
 		ret = 1; /* Assume uSDHC3 emmc is always present */
 		break;
 	}
 	return ret;
 }
 int board_mmc_init(bd_t *bis)
 {
 	int i, ret;
 	/*
 	 * According to the board_mmc_init() the following map is done:
 	 * (U-Boot device node)    (Physical Port)
 	 * mmc0                    USDHC1
 	 * mmc2                    USDHC3 (eMMC)
 	 */
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
 		case 0:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 			gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
 			gpio_direction_input(USDHC1_CD_GPIO);
 			gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
 			gpio_direction_output(USDHC1_PWR_GPIO, 0);
 			udelay(500);
 			gpio_direction_output(USDHC1_PWR_GPIO, 1);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 			break;
 		case 1:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
 			gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
 			gpio_direction_output(USDHC3_PWR_GPIO, 0);
 			udelay(500);
 			gpio_direction_output(USDHC3_PWR_GPIO, 1);
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 			break;
 		default:
 			printf("Warning: you configured more USDHC controllers"
 				"(%d) than supported by the board\n", i + 1);
 			return -EINVAL;
 			}
 			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 			if (ret)
 				return ret;
 	}
 	return 0;
 }
 #endif
 #ifdef CONFIG_FEC_MXC
 static iomux_v3_cfg_t const fec1_pads[] = {
 	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 	MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 };
 static iomux_v3_cfg_t const fec2_pads[] = {
 	MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 	MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 };
 static void setup_iomux_fec(void)
 {
 	if (0 == CONFIG_FEC_ENET_DEV) {
 		imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
         	gpio_direction_input(IMX_GPIO_NR(7, 15));
 	} else {
 		imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
                 gpio_direction_input(IMX_GPIO_NR(7, 14));
 	}
 }
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_MAC_ADDR_IN_EEPROM)
         uchar env_enetaddr[6];
         int enetaddr_found;
         enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);
         uint8_t enetaddr[8];
         int eeprom_mac_read;
         /* Read Ethernet MAC address from EEPROM */
         eeprom_mac_read = smarcfimx7_read_mac_address(enetaddr);
         /*
          * MAC address not present in the environment
          * try and read the MAC address from EEPROM flash
          * and set it.
          */
         if (!enetaddr_found) {
                 if (eeprom_mac_read)
                         /* Set Ethernet MAC address from EEPROM */
                         smarcfimx7_sync_env_enetaddr(enetaddr);
         } else {
                 /*
                  * MAC address present in environment compare it with
                  * the MAC address in EEPROM and warn on mismatch
                  */
                 if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
                         printf("Warning: MAC address in EEPROM don't match "
                                         "with the MAC address in the environment\n");
                         printf("Default using MAC address from environment\n");
         }
         uchar env_enet1addr[6];
         int enet1addr_found;
         enet1addr_found = eth_getenv_enetaddr("eth1addr", env_enet1addr);
         uint8_t enet1addr[8];
         int eeprom_mac1_read;
         /* Read Ethernet MAC address from EEPROM */
-        eeprom_mac1_read = smarcfimx7_read_mac_address(enet1addr);
+        eeprom_mac1_read = smarcfimx7_read_mac1_address(enet1addr);
         /*
          * MAC address not present in the environment
          * try and read the MAC address from EEPROM flash
          * and set it.
          */
         if (!enet1addr_found) {
                 if (eeprom_mac1_read)
                         /* Set Ethernet MAC address from EEPROM */
                         smarcfimx7_sync_env_enet1addr(enet1addr);
         } else {
                 /*
                  * MAC address present in environment compare it with
                  * the MAC address in EEPROM and warn on mismatch
                  */
                 if (eeprom_mac_read && memcmp(enet1addr, env_enet1addr, 6))
                         printf("Warning: 2nd GBE MAC address in EEPROM don't match "
                                         "with the MAC address in the environment\n");
                         printf("Default using 2nd GBE MAC address from environment\n");
         }
 #endif
 	int ret;
 	setup_iomux_fec();
 	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
 		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 	if (ret)
 		printf("FEC1 MXC: %s:failed\n", __func__);
 	return ret;
 }
 static int setup_fec(int fec_id)
 {
         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
                 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
         if (0 == fec_id) {
                 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
                 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
                         (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
                          IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
         } else {
                 /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/
                 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
                         (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
                          IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
         }
         return set_clk_enet(ENET_125MHz);
 }
 int board_phy_config(struct phy_device *phydev)
 {
         /* enable rgmii rxc skew and phy mode select to RGMII copper */
         /*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/
         if (phydev->drv->config)
                 phydev->drv->config(phydev);
         return 0;
 }
 #endif
 #ifdef CONFIG_MXC_SPI
 /* SPI2 (SPINOR) */
 static iomux_v3_cfg_t const ecspi2_pads[] = {
         MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),	/*SS0#*/
 };
 static void setup_spinor(void)
 {
         imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
         gpio_direction_output(IMX_GPIO_NR(4, 23), 0);
 }
 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 {
         return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 23)) : -1;
 }
 #endif
 #ifdef CONFIG_MXC_EPDC
 static iomux_v3_cfg_t const epdc_enable_pads[] = {
 	MX7D_PAD_EPDC_DATA00__EPDC_DATA0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA01__EPDC_DATA1	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA02__EPDC_DATA2	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA03__EPDC_DATA3	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA04__EPDC_DATA4	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA05__EPDC_DATA5	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA06__EPDC_DATA6	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA07__EPDC_DATA7	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDLE__EPDC_SDLE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDOE__EPDC_SDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_GDOE__EPDC_GDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_GDRL__EPDC_GDRL		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_GDSP__EPDC_GDSP		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_BDR0__EPDC_BDR0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_BDR1__EPDC_BDR1		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 };
 static iomux_v3_cfg_t const epdc_disable_pads[] = {
 	MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
 	MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
 	MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
 	MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
 	MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
 	MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
 	MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
 	MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
 	MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
 	MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
 	MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
 	MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
 	MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
 	MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
 	MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
 	MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
 	MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
 	MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
 	MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
 	MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
 };
 vidinfo_t panel_info = {
 	.vl_refresh = 85,
 	.vl_col = 1024,
 	.vl_row = 758,
 	.vl_pixclock = 40000000,
 	.vl_left_margin = 12,
 	.vl_right_margin = 76,
 	.vl_upper_margin = 4,
 	.vl_lower_margin = 5,
 	.vl_hsync = 12,
 	.vl_vsync = 2,
 	.vl_sync = 0,
 	.vl_mode = 0,
 	.vl_flag = 0,
 	.vl_bpix = 3,
 	.cmap = 0,
 };
 struct epdc_timing_params panel_timings = {
 	.vscan_holdoff = 4,
 	.sdoed_width = 10,
 	.sdoed_delay = 20,
 	.sdoez_width = 10,
 	.sdoez_delay = 20,
 	.gdclk_hp_offs = 524,
 	.gdsp_offs = 327,
 	.gdoe_offs = 0,
 	.gdclk_offs = 19,
 	.num_ce = 1,
 };
 static void setup_epdc_power(void)
 {
 	/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
 	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
 	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 		IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
 	/* Setup epdc voltage */
 	/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	gpio_direction_input(IMX_GPIO_NR(2, 31));
 	/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
 	imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
 	/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
 	/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_direction_output(IMX_GPIO_NR(2, 30), 1);
 }
 static void epdc_enable_pins(void)
 {
 	/* epdc iomux settings */
 	imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
 				ARRAY_SIZE(epdc_enable_pads));
 }
 static void epdc_disable_pins(void)
 {
 	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
 	imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
 				ARRAY_SIZE(epdc_disable_pads));
 }
 static void setup_epdc(void)
 {
 	/*** epdc Maxim PMIC settings ***/
 	/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
 	imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set pixel clock rates for EPDC in clock.c */
 	panel_info.epdc_data.wv_modes.mode_init = 0;
 	panel_info.epdc_data.wv_modes.mode_du = 1;
 	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
 	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
 	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
 	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
 	panel_info.epdc_data.epdc_timings = panel_timings;
 	setup_epdc_power();
 }
 void epdc_power_on(void)
 {
 	unsigned int reg;
 	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
 	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
 	gpio_set_value(IMX_GPIO_NR(2, 30), 1);
 	udelay(1000);
 	/* Enable epdc signal pin */
 	epdc_enable_pins();
 	/* Set PMIC Wakeup to high - enable Display power */
 	gpio_set_value(IMX_GPIO_NR(2, 23), 1);
 	/* Wait for PWRGOOD == 1 */
 	while (1) {
 		reg = readl(&gpio_regs->gpio_psr);
 		if (!(reg & (1 << 31)))
 			break;
 		udelay(100);
 	}
 	/* Enable VCOM */
 	gpio_set_value(IMX_GPIO_NR(4, 14), 1);
 	udelay(500);
 }
 void epdc_power_off(void)
 {
 	/* Set PMIC Wakeup to low - disable Display power */
 	gpio_set_value(IMX_GPIO_NR(2, 23), 0);
 	/* Disable VCOM */
 	gpio_set_value(IMX_GPIO_NR(4, 14), 0);
 	epdc_disable_pins();
 	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
 	gpio_set_value(IMX_GPIO_NR(2, 30), 0);
 }
 #endif
 #ifdef CONFIG_USB_EHCI_MX7
 static iomux_v3_cfg_t const usb_otg1_pads[] = {
         MX7D_PAD_GPIO1_IO12__USB_OTG1_ID | MUX_PAD_CTRL(WEAK_PULLUP),
 	/* OTG1 Power Enable */
         MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* OTG1 Over Current */
         MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 static iomux_v3_cfg_t const usb_otg2_pads[] = {
         /* OTG2 Power Enable */
         MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
         /* OTG2 Over Current */
         MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 static void setup_usb(void)
 {
 	imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
 						 ARRAY_SIZE(usb_otg1_pads));
         gpio_direction_input(IMX_GPIO_NR(1, 4));
 	imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 						 ARRAY_SIZE(usb_otg2_pads));
         gpio_direction_input(IMX_GPIO_NR(1, 6));
 }
 int board_usb_phy_mode(int port)
 {
 	if (port == 0)
 		return usb_phy_mode(port);
 	else
 		return USB_INIT_HOST;
 }
 #endif
 int board_early_init_f(void)
 {
         setup_iomux_reset_out();
 	setup_iomux_uart6();
         setup_iomux_uart2();
         setup_iomux_uart7();
         setup_iomux_uart3();
 #ifdef CONFIG_SYS_I2C_MXC
 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
 #endif
 #ifdef CONFIG_MXC_SPI
         setup_spinor();
 #endif
 #ifdef CONFIG_USB_EHCI_MX7
 	setup_usb();
 #endif
         setup_iomux_spi1();
         setup_iomux_spi3();
         setup_iomux_flexcan1();
         setup_iomux_flexcan2();
         setup_iomux_gpios();
 	setup_iomux_lvds_ch_sel();
         setup_iomux_misc();
 	return 0;
 }
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 #ifdef CONFIG_FEC_MXC
         setup_fec(CONFIG_FEC_ENET_DEV);
 #endif
 #ifdef CONFIG_NAND_MXS
 	setup_gpmi_nand();
 #endif
 #ifdef CONFIG_FSL_QSPI
 	board_qspi_init();
 #endif
 	return 0;
 }
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
 	{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
 	{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
 	/* TODO: Nand */
 	{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
 	{NULL,   0},
 };
 #endif
 #ifdef CONFIG_POWER
 #define I2C_PMIC	0
 int power_init_board(void)
 {
 	struct pmic *p;
 	int ret;
 	unsigned int reg, rev_id;
 	ret = power_pfuze3000_init(I2C_PMIC);
 	if (ret)
 		return ret;
 	p = pmic_get("PFUZE3000");
 	ret = pmic_probe(p);
 	if (ret)
 		return ret;
 	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
 	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
 	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 	/* disable Low Power Mode during standby mode */
 	pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
 	reg |= 0x1;
 	pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
 	/* SW1A/1B mode set to APS/APS */
 	reg = 0x8;
 	pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
 	pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
 	/* SW1A/1B standby voltage set to 0.975V */
 	reg = 0xb;
 	pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 	pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 	/* decrease SW1B normal voltage to 0.975V */
 	pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 	reg &= ~0x1f;
 	reg |= PFUZE3000_SW1AB_SETP(975);
 	pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 	return 0;
 }
 #endif
 int board_late_init(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
 #ifdef CONFIG_ENV_IS_IN_MMC
 	board_late_mmc_env_init();
 #endif
 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 	set_wdog_reset(wdog);
 /* Check Board Information */
         setup_i2c(1, CONFIG_SYS_I2C_SPEED,
                         0x50, &i2c_pad_info2);
         struct smarcfimx7_id header;
         if (read_eeprom(&header) < 0)
         puts("Could not get board ID.\n");
         puts("---------Embedian SMARC-FiMX7------------\n");
         printf("Board ID:               %.*s\n",
                sizeof(header.name), header.name);
         printf("Board Revision:         %.*s\n",
                sizeof(header.version), header.version);
         printf("Board Serial#:          %.*s\n",
                sizeof(header.serial), header.serial);
         puts("-----------------------------------------\n");
 /* SMARC BOOT_SEL*/
         if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {
                 puts("BOOT_SEL Detected: OFF OFF OFF, unsupported boot up device: SATA...\n");
                 hang();
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {
                 puts("BOOT_SEL Detected: OFF OFF ON, unsupported boot up device: NAND...\n");
                 hang();
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {
                 puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier eSPI...\n");
                 hang();
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {
                 puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n");
                 setenv_ulong("mmcdev", 0);
                 setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {
                 puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n");
                 setenv_ulong("mmcdev", 1);
                 setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {
                 puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");
                 setenv("bootcmd", "run netboot;");
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {
                 puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier SPI...\n");
                 hang();
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {
                 puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n");
                 setenv_ulong("mmcdev", 1);
                 setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
         } else {
                 puts("unsupported boot devices\n");
                 hang();
         }
         return 0;
 }
 #ifdef CONFIG_FSL_FASTBOOT
 void board_fastboot_setup(void)
 {
 	switch (get_boot_device()) {
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD1_BOOT:
 	case MMC1_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc0");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "boota mmc0");
 		break;
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc1");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "boota mmc1");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 	default:
 		printf("unsupported boot devices\n");
 		break;
 	}
 }
 #ifdef CONFIG_ANDROID_RECOVERY
 /* Use LID# for recovery key */
 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10)
 iomux_v3_cfg_t const recovery_key_pads[] = {
 	(MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)),
 };
 int check_recovery_cmd_file(void)
 {
 	int button_pressed = 0;
 	int recovery_mode = 0;
 	recovery_mode = recovery_check_and_clean_flag();
 	/* Check Recovery Combo Button press or not. */
 	imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
 		ARRAY_SIZE(recovery_key_pads));
 	gpio_direction_input(GPIO_VOL_DN_KEY);
 	if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
 		button_pressed = 1;
 		printf("Recovery key pressed\n");
 	}
 	return recovery_mode || button_pressed;
 }
 void board_recovery_setup(void)
 {
 	int bootdev = get_boot_device();
 	switch (bootdev) {
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD1_BOOT:
 	case MMC1_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery", "boota mmc0 recovery");
 		break;
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery", "boota mmc1 recovery");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 	default:
 		printf("Unsupported bootup device for recovery: dev: %d\n",
 			bootdev);
 		return;
 	}
 	printf("setup env for recovery..\n");
 	setenv("bootcmd", "run bootcmd_android_recovery");
 }
 #endif /*CONFIG_ANDROID_RECOVERY*/
 #endif /*CONFIG_FSL_FASTBOOT*/

1	/*	1	/*
2	* smarcfimx7.h	2	* smarcfimx7.h
3	*	3	*
4	* Embedian SMARC-FiMX7 boards information header	4	* Embedian SMARC-FiMX7 boards information header
5	*	5	*
6	* Copyright (C) 2017, Embedian, Inc. - http://www.embedian.com/	6	* Copyright (C) 2017, Embedian, Inc. - http://www.embedian.com/
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#ifndef _SMARCFIMX7_H_	11	#ifndef _SMARCFIMX7_H_
12	#define _SMARCFIMX7_H_	12	#define _SMARCFIMX7_H_
13	/*	13	/*
14	* SMARC-FiMX7 Config held in module eeprom device.	14	* SMARC-FiMX7 Config held in module eeprom device.
15	*	15	*
16	* Header Format	16	* Header Format
17	*	17	*
18	* Name Size Contents	18	* Name Size Contents
19	* (Bytes)	19	* (Bytes)
20	*-------------------------------------------------------------	20	*-------------------------------------------------------------
21	* Header 4 0xAA, 0x55, 0x33, 0xEE	21	* Header 4 0xAA, 0x55, 0x33, 0xEE
22	*	22	*
23	* Board Name 8 Name for board in ASCII.	23	* Board Name 8 Name for board in ASCII.
24	* example "SMCMX7D1" = "SMARC-FiMX7	24	* example "SMCMX7D1" = "SMARC-FiMX7
25	* Dual Core and 1GB DDR3 memory". "SMCMX7S0" =	25	* Dual Core and 1GB DDR3 memory". "SMCMX7S0" =
26	* SMARC-FiMX7 Computer on Module with solo Core	26	* SMARC-FiMX7 Computer on Module with solo Core
27	* and 512MB DDR3L Configuration	27	* and 512MB DDR3L Configuration
28	*	28	*
29	* Version 4 Hardware version code for board in	29	* Version 4 Hardware version code for board in
30	* in ASCII. "00A0" = rev.0A	30	* in ASCII. "00A0" = rev.0A
31	* Serial Number 12 Serial number of the board. This is a 12	31	* Serial Number 12 Serial number of the board. This is a 12
32	* character string which is: WWYYMSkknnnn, where	32	* character string which is: WWYYMSkknnnn, where
33	* WW = 2 digit week of the year of production	33	* WW = 2 digit week of the year of production
34	* YY = 2 digit year of production	34	* YY = 2 digit year of production
35	* kk = 2 digit module variants	35	* kk = 2 digit module variants
36	* nnnn = incrementing board number	36	* nnnn = incrementing board number
37	* Configuration Option 32 Codes to show the configuration	37	* Configuration Option 32 Codes to show the configuration
38	* setup on this board.	38	* setup on this board.
39	* MAC Address (LAN1) MAC Address for FEC controller	39	* MAC Address (LAN1) MAC Address for FEC controller
40	* MAC Address (LAN2, if any) MAC Address for 2nd LAN (if any)	40	* MAC Address (LAN2, if any) MAC Address for 2nd LAN (if any)
41	* Available 32700 Available space for other non-volatile	41	* Available 32700 Available space for other non-volatile
42	* codes/data	42	* codes/data
43	*/	43	*/
44		44
45	#define HDR_NO_OF_MAC_ADDR 3	45	#define HDR_NO_OF_MAC_ADDR 3
46	#define HDR_ETH_ALEN 6	46	#define HDR_ETH_ALEN 6
47	#define HDR_NAME_LEN 8	47	#define HDR_NAME_LEN 8
48		48
49	struct smarcfimx7_id {	49	struct smarcfimx7_id {
50	unsigned int magic;	50	unsigned int magic;
51	char name[HDR_NAME_LEN];	51	char name[HDR_NAME_LEN];
52	char version[4];	52	char version[4];
53	char serial[12];	53	char serial[12];
54	char config[32];	54	char config[32];
55	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];	55	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
56	};	56	};
57		57
58	static inline int board_is_smcmx7s0(struct smarcfimx7_id *header)	58	static inline int board_is_smcmx7s0(struct smarcfimx7_id *header)
59	{	59	{
60	return !strncmp(header->name, "SMCMX7S0", HDR_NAME_LEN);	60	return !strncmp(header->name, "SMCMX7S0", HDR_NAME_LEN);
61	}	61	}
62		62
63	static inline int board_is_smcmx7d1(struct smarcfimx7_id *header)	63	static inline int board_is_smcmx7d1(struct smarcfimx7_id *header)
64	{	64	{
65	return !strncmp(header->name, "SMCMX7D1", HDR_NAME_LEN);	65	return !strncmp(header->name, "SMCMX7D1", HDR_NAME_LEN);
66	}	66	}
67		67
68	/*	68	/*
69	* Read ethernet MAC address from EEPROM for SMARC-FiMX7 compatible boards.	69	* Read ethernet MAC address from EEPROM for SMARC-FiMX7 compatible boards.
70	* Returns 1 if found, 0 otherwise.	70	* Returns 1 if found, 0 otherwise.
71	*/	71	*/
72	int smarcfimx7_read_mac_address(uint8_t *buf)	72	int smarcfimx7_read_mac_address(uint8_t *buf)
73	{	73	{
74	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR	74	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
75	/* Read MAC address. */	75	/* Read MAC address. */
76	i2c_set_bus_num(1);	76	i2c_set_bus_num(1);
77	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x3C,	77	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x3C,
78	CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))	78	CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
79	goto i2cerr;	79	goto i2cerr;
80		80
81	/* Check that MAC address is valid. */	81	/* Check that MAC address is valid. */
82	if (!is_valid_ethaddr(buf))	82	if (!is_valid_ethaddr(buf))
83	goto err;	83	goto err;
84		84
85	return 1; /* Found */	85	return 1; /* Found */
86		86
87	i2cerr:	87	i2cerr:
88	printf("Read from EEPROM @ 0x%02x failed\n",	88	printf("Read from EEPROM @ 0x%02x failed\n",
89	CONFIG_SYS_I2C_EEPROM_ADDR);	89	CONFIG_SYS_I2C_EEPROM_ADDR);
90	err:	90	err:
91	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */	91	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
92		92
93	return 0;	93	return 0;
94	}	94	}
95		95
96	/*	96	/*
97	* If there is no MAC address in the environment, then it will be initialized	97	* If there is no MAC address in the environment, then it will be initialized
98	* (silently) from the value in the EEPROM.	98	* (silently) from the value in the EEPROM.
99	*/	99	*/
100	void smarcfimx7_sync_env_enetaddr(uint8_t *rom_enetaddr)	100	void smarcfimx7_sync_env_enetaddr(uint8_t *rom_enetaddr)
101	{	101	{
102	i2c_set_bus_num(1);	102	i2c_set_bus_num(1);
103	uint8_t env_enetaddr[6];	103	uint8_t env_enetaddr[6];
104	int ret;	104	int ret;
105		105
106	ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);	106	ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
107	if (!ret) {	107	if (!ret) {
108	/*	108	/*
109	* There is no MAC address in the environment, so we	109	* There is no MAC address in the environment, so we
110	* initialize it from the value in the EEPROM.	110	* initialize it from the value in the EEPROM.
111	*/	111	*/
112	debug("### Setting environment from EEPROM MAC address = "	112	debug("### Setting environment from EEPROM MAC address = "
113	"\"%pM\"\n",	113	"\"%pM\"\n",
114	env_enetaddr);	114	env_enetaddr);
115	ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);	115	ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
116	}	116	}
117	if (!ret)	117	if (!ret)
118	printf("Failed to set mac address from EEPROM: %d\n", ret);	118	printf("Failed to set mac address from EEPROM: %d\n", ret);
119	}	119	}
120		120
121	int smarcfimx7_read_mac_address1(uint8_t *buf)	121	int smarcfimx7_read_mac1_address(uint8_t *buf)
122	{	122	{
123	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR	123	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
124	/* Read MAC address. */	124	/* Read MAC address. */
125	i2c_set_bus_num(1);	125	i2c_set_bus_num(1);
126	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x42,	126	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x42,
127	CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))	127	CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
128	goto i2cerr;	128	goto i2cerr;
129		129
130	/* Check that MAC address is valid. */	130	/* Check that MAC address is valid. */
131	if (!is_valid_ethaddr(buf))	131	if (!is_valid_ethaddr(buf))
132	goto err;	132	goto err;
133		133
134	return 1; /* Found */	134	return 1; /* Found */
135		135
136	i2cerr:	136	i2cerr:
137	printf("Read 2nd GBE MAC address from EEPROM @ 0x%02x failed\n",	137	printf("Read 2nd GBE MAC address from EEPROM @ 0x%02x failed\n",
138	CONFIG_SYS_I2C_EEPROM_ADDR);	138	CONFIG_SYS_I2C_EEPROM_ADDR);
139	err:	139	err:
140	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */	140	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
141		141
142	return 0;	142	return 0;
143	}	143	}
144		144
145	/*	145	/*
146	* If there is no MAC address in the environment, then it will be initialized	146	* If there is no MAC address in the environment, then it will be initialized
147	* (silently) from the value in the EEPROM.	147	* (silently) from the value in the EEPROM.
148	*/	148	*/
149	void smarcfimx7_sync_env_enet1addr(uint8_t *rom_enet1addr)	149	void smarcfimx7_sync_env_enet1addr(uint8_t *rom_enet1addr)
150	{	150	{
151	i2c_set_bus_num(1);	151	i2c_set_bus_num(1);
152	uint8_t env_enet1addr[6];	152	uint8_t env_enet1addr[6];
153	int ret;	153	int ret;
154		154
155	ret = eth_getenv_enetaddr_by_index("eth1", 0, env_enet1addr);	155	ret = eth_getenv_enetaddr_by_index("eth", 1, env_enet1addr);
156	if (!ret) {	156	if (!ret) {
157	/*	157	/*
158	* There is no MAC address in the environment, so we	158	* There is no MAC address in the environment, so we
159	* initialize it from the value in the EEPROM.	159	* initialize it from the value in the EEPROM.
160	*/	160	*/
161	debug("### Setting environment from EEPROM MAC address = "	161	debug("### Setting environment from EEPROM MAC address = "
162	"\"%pM\"\n",	162	"\"%pM\"\n",
163	env_enet1addr);	163	env_enet1addr);
164	ret = !eth_setenv_enetaddr("eth1addr", rom_enet1addr);	164	ret = !eth_setenv_enetaddr("eth1addr", rom_enet1addr);
165	}	165	}
166	if (!ret)	166	if (!ret)
167	printf("Failed to set 2nd GBE mac address from EEPROM: %d\n", ret);	167	printf("Failed to set 2nd GBE mac address from EEPROM: %d\n", ret);
168	}	168	}
169		169
170	#endif	170	#endif
171		171

 /*
  * Freescale i.MX23/i.MX28 LCDIF driver
  *
  * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
  *
  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <malloc.h>
 #include <video_fb.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/imx-common/dma.h>
 #include "videomodes.h"
 #include <linux/string.h>
 #include <linux/list.h>
 #include <linux/fb.h>
 #include <mxsfb.h>
 #ifdef CONFIG_VIDEO_GIS
 #include <gis.h>
 #endif
 #define	PS2KHZ(ps)	(1000000000UL / (ps))
 static GraphicDevice panel;
 struct mxs_dma_desc desc;
 /**
  * mxsfb_system_setup() - Fine-tune LCDIF configuration
  *
  * This function is used to adjust the LCDIF configuration. This is usually
  * needed when driving the controller in System-Mode to operate an 8080 or
  * 6800 connected SmartLCD.
  */
 __weak void mxsfb_system_setup(void)
 {
 }
 static int setup;
 static struct fb_videomode fbmode;
 static int depth;
 int mxs_lcd_panel_setup(struct fb_videomode mode, int bpp,
 	uint32_t base_addr)
 {
 	fbmode = mode;
 	depth  = bpp;
 	panel.isaBase  = base_addr;
 	setup = 1;
 	return 0;
 }
 void mxs_lcd_get_panel(struct display_panel *dispanel)
 {
 	dispanel->width = fbmode.xres;
 	dispanel->height = fbmode.yres;
 	dispanel->reg_base = panel.isaBase;
 	dispanel->gdfindex = panel.gdfIndex;
 	dispanel->gdfbytespp = panel.gdfBytesPP;
 }
 /*
  * DENX M28EVK:
  * setenv videomode
  * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  *
  * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  * setenv videomode
  * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  * 	 le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  */
 static void mxs_lcd_init(GraphicDevice *panel,
 			struct ctfb_res_modes *mode, int bpp)
 {
 	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)(panel->isaBase);
 	uint32_t word_len = 0, bus_width = 0;
 	uint8_t valid_data = 0;
 	/* Kick in the LCDIF clock */
 	mxs_set_lcdclk(panel->isaBase, PS2KHZ(mode->pixclock));
 	/* Restart the LCDIF block */
 	mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
 	switch (bpp) {
 	case 24:
 		word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
 		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
 		valid_data = 0x7;
 		break;
 	case 18:
 		word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
 		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
 		valid_data = 0x7;
 		break;
 	case 16:
 		word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
 		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
 		valid_data = 0xf;
 		break;
 	case 8:
 		word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
 		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
 		valid_data = 0xf;
 		break;
 	}
 	writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
 		LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
 		&regs->hw_lcdif_ctrl);
 	writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
 		&regs->hw_lcdif_ctrl1);
 	mxsfb_system_setup();
 	writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
 		&regs->hw_lcdif_transfer_count);
 	writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
 		LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 		LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 		mode->vsync_len, &regs->hw_lcdif_vdctrl0);
 	writel(mode->upper_margin + mode->lower_margin +
 		mode->vsync_len + mode->yres,
 		&regs->hw_lcdif_vdctrl1);
 	writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
 		(mode->left_margin + mode->right_margin +
 		mode->hsync_len + mode->xres),
 		&regs->hw_lcdif_vdctrl2);
 	writel(((mode->left_margin + mode->hsync_len) <<
 		LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
 		(mode->upper_margin + mode->vsync_len),
 		&regs->hw_lcdif_vdctrl3);
 	writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
 		&regs->hw_lcdif_vdctrl4);
 	writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
 	writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
 	/* Flush FIFO first */
 	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
 	/* Sync signals ON */
 	setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
 #endif
 	/* FIFO cleared */
 	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
 	/* RUN! */
 	writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 }
 void lcdif_power_down(void)
 {
 	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)(panel.isaBase);
 	int timeout = 1000000;
+       	char *penv;
+       	penv = getenv("videomode");
+       	if (!penv)
+               	return;
 #ifdef CONFIG_MX6
 	if (check_module_fused(MX6_MODULE_LCDIF))
 		return;
 #endif
 	writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
 	writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
 	writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
 	while (--timeout) {
 		if (readl(&regs->hw_lcdif_ctrl1_reg) &
 		    LCDIF_CTRL1_VSYNC_EDGE_IRQ)
 			break;
 		udelay(1);
 	}
 	mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
 }
 void *video_hw_init(void)
 {
 	int bpp = -1;
 	char *penv;
 	void *fb;
 	struct ctfb_res_modes mode;
 	puts("Video: ");
 	if (!setup) {
 		/* Suck display configuration from "videomode" variable */
 		penv = getenv("videomode");
 		if (!penv) {
 			printf("MXSFB: 'videomode' variable not set!\n");
 			return NULL;
 		}
 		bpp = video_get_params(&mode, penv);
 		panel.isaBase  = MXS_LCDIF_BASE;
 	} else {
 		mode.xres = fbmode.xres;
 		mode.yres = fbmode.yres;
 		mode.pixclock = fbmode.pixclock;
 		mode.left_margin = fbmode.left_margin;
 		mode.right_margin = fbmode.right_margin;
 		mode.upper_margin = fbmode.upper_margin;
 		mode.lower_margin = fbmode.lower_margin;
 		mode.hsync_len = fbmode.hsync_len;
 		mode.vsync_len = fbmode.vsync_len;
 		mode.sync = fbmode.sync;
 		mode.vmode = fbmode.vmode;
 		bpp = depth;
 	}
 #ifdef CONFIG_MX6
 	if (check_module_fused(MX6_MODULE_LCDIF)) {
 		printf("LCDIF@0x%x is fused, disable it\n", MXS_LCDIF_BASE);
 		return NULL;
 	}
 #endif
 	/* fill in Graphic device struct */
 	sprintf(panel.modeIdent, "%dx%dx%d",
 			mode.xres, mode.yres, bpp);
 	panel.winSizeX = mode.xres;
 	panel.winSizeY = mode.yres;
 	panel.plnSizeX = mode.xres;
 	panel.plnSizeY = mode.yres;
 	switch (bpp) {
 	case 24:
 	case 18:
 		panel.gdfBytesPP = 4;
 		panel.gdfIndex = GDF_32BIT_X888RGB;
 		break;
 	case 16:
 		panel.gdfBytesPP = 2;
 		panel.gdfIndex = GDF_16BIT_565RGB;
 		break;
 	case 8:
 		panel.gdfBytesPP = 1;
 		panel.gdfIndex = GDF__8BIT_INDEX;
 		break;
 	default:
 		printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
 		return NULL;
 	}
 	panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
 	/* Allocate framebuffer */
 	fb = memalign(ARCH_DMA_MINALIGN,
 		      roundup(panel.memSize, ARCH_DMA_MINALIGN));
 	if (!fb) {
 		printf("MXSFB: Error allocating framebuffer!\n");
 		return NULL;
 	}
 	/* Wipe framebuffer */
 	memset(fb, 0, panel.memSize);
 	panel.frameAdrs = (u32)fb;
 	printf("%s\n", panel.modeIdent);
 	/* Start framebuffer */
 	mxs_lcd_init(&panel, &mode, bpp);
 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
 	/*
 	 * If the LCD runs in system mode, the LCD refresh has to be triggered
 	 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
 	 * having to set this bit manually after every single change in the
 	 * framebuffer memory, we set up specially crafted circular DMA, which
 	 * sets the RUN bit, then waits until it gets cleared and repeats this
 	 * infinitelly. This way, we get smooth continuous updates of the LCD.
 	 */
 	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 	memset(&desc, 0, sizeof(struct mxs_dma_desc));
 	desc.address = (dma_addr_t)&desc;
 	desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
 			MXS_DMA_DESC_WAIT4END |
 			(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
 	desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
 	desc.cmd.next = (uint32_t)&desc.cmd;
 	/* Execute the DMA chain. */
 	mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
 #endif
 #ifdef CONFIG_VIDEO_GIS
 	/* Entry for GIS */
 	mxc_enable_gis();
 #endif
 	return (void *)&panel;
 }

 /*
  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  *
  * Configuration settings for the Freescale i.MX7D SABRESD board.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __SMARCFIMX7_CONFIG_H
 #define __SMARCFIMX7_CONFIG_H
 #include "mx7smarc_common.h"
 #define CONFIG_DBG_MONITOR
 #if defined(CONFIG_MX7D)
 #define PHYS_SDRAM_SIZE			SZ_1G
 #else
 #define PHYS_SDRAM_SIZE                 SZ_512M
 #endif
 /* uncomment for PLUGIN mode support */
 /* #define CONFIG_USE_PLUGIN */
 /* Uncomment to enable secure boot support */
 /* #define CONFIG_SECURE_BOOT */
 #ifdef CONFIG_SECURE_BOOT
 #ifndef CONFIG_CSF_SIZE
 #define CONFIG_CSF_SIZE 0x4000
 #endif
 #endif
 /* Network */
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_ETHPRIME                 "FEC"
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 #define CONFIG_FEC_ENET_DEV 0
 #if (CONFIG_FEC_ENET_DEV == 0)
 #define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR          0x6
 #elif (CONFIG_FEC_ENET_DEV == 1)
 #define IMX_FEC_BASE			ENET2_IPS_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR          0x7
 #endif
 #define CONFIG_FEC_MXC_MDIO_BASE	ENET_IPS_BASE_ADDR
 /* PMIC */
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_PFUZE3000
 #define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
 #undef CONFIG_BOOTM_NETBSD
 #undef CONFIG_BOOTM_PLAN9
 #undef CONFIG_BOOTM_RTEMS
 #undef CONFIG_CMD_EXPORTENV
 /* I2C configs */
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_SPEED		100000
 /*
 * I2C EEPROM definitions EEPROM chip
 */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 #define CONFIG_MAC_ADDR_IN_EEPROM
 #ifdef CONFIG_SYS_BOOT_SPINOR
 #define CONFIG_SYS_USE_SPINOR
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #elif defined CONFIG_SYS_BOOT_NAND
 #define CONFIG_SYS_USE_NAND
 #define CONFIG_ENV_IS_IN_NAND
 #else
 #define CONFIG_ENV_IS_IN_MMC
 #endif
 #ifdef CONFIG_SYS_USE_SPINOR
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_MACRONIX
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS  	1
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
 #ifdef CONFIG_IMX_BOOTAUX
 /* Set to SPI2 flash at default */
 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x7F8000 /* Set to TCML address */
 #ifdef CONFIG_SYS_USE_QSPI
 #define UPDATE_M4_ENV \
 	"m4image=m4_qspi.bin\0" \
 	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
 	"update_m4_from_sd=" \
 		"if sf probe 0:0; then " \
 			"if run loadm4image; then " \
 				"setexpr fw_sz ${filesize} + 0xffff; " \
 				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
 				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
 				"sf erase 0x100000 ${fw_sz}; " \
 				"sf write ${loadaddr} 0x100000 ${filesize}; " \
 			"fi; " \
 		"fi\0" \
 	"m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
 #else
 #define UPDATE_M4_ENV \
 	"m4image=m4_qspi.bin\0" \
 	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)" ${m4image}\0" \
 	"m4boot=run loadm4image; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
 #endif
 #else
 #define UPDATE_M4_ENV ""
 #endif
 #ifdef CONFIG_SYS_BOOT_NAND
 #define CONFIG_MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs) "
 #else
 #define CONFIG_MFG_NAND_PARTITION ""
 #endif
 #define CONFIG_MFG_ENV_SETTINGS \
 	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
 		"rdinit=/linuxrc " \
 		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
 		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
 		"g_mass_storage.iSerialNumber=\"\" "\
 		CONFIG_MFG_NAND_PARTITION \
 		"clk_ignore_unused "\
 		"\0" \
 	"initrd_addr=0x83800000\0" \
 	"initrd_high=0xffffffff\0" \
 	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
 #define CONFIG_DFU_ENV_SETTINGS \
 	"dfu_alt_info=image raw 0 0x800000;"\
 		"u-boot raw 0 0x4000;"\
 		"bootimg part 0 1;"\
 		"rootfs part 0 2\0" \
 #if defined(CONFIG_SYS_BOOT_NAND)
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONFIG_MFG_ENV_SETTINGS \
 	"panel=TFT43AB\0" \
 	"fdt_addr=0x83000000\0" \
 	"fdt_high=0xffffffff\0"	  \
 	"console=ttymxc0\0" \
 	"bootargs=console=ttymxc0,115200 ubi.mtd=3 "  \
 		"root=ubi0:rootfs rootfstype=ubifs "		     \
 		"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
 	"bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
 		"nand read ${fdt_addr} 0x5000000 0x100000;"\
 		"bootz ${loadaddr} - ${fdt_addr}\0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	UPDATE_M4_ENV \
 	CONFIG_MFG_ENV_SETTINGS \
 	CONFIG_DFU_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
         "console=" CONFIG_CONSOLE_DEV "\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
         "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"fdt_addr=0x83000000\0" \
         "ethprime=FEC0\0" \
-        "fec.macaddr=${ethaddr}\0" \
-        "fec1.macaddr=${eth1addr}\0" \
         "ipaddr=192.168.1.60\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"panel=G070VW01\0" \
-        "optargs= fec.macaddr=${ethaddr} fec1.macaddr=${eth1addr}\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
         "mmcrootfstype=ext4 rootwait\0" \
 	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
                 "${optargs} " \
                 "rootfstype=${mmcrootfstype} " \
 		"root=${mmcroot}\0" \
         "loadbootenv=load mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \
         "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \
                 "env import -t $loadaddr $filesize\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
         "loadzimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
 				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
 					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
 			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
 	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 		"netboot=echo Booting from net ...; " \
 		"run netargs; " \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
 				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
 					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
 			"bootz; " \
 		"fi;\0"
 #define CONFIG_BOOTCOMMAND \
         "mmc dev ${mmcdev};" \
         "if mmc rescan; then " \
                 "echo SD/MMC found on device ${mmcdev};" \
                 "if run loadbootenv; then " \
                         "run importbootenv;" \
                 "fi;" \
                 "echo Checking if uenvcmd is set ...;" \
                 "if test -n $uenvcmd; then " \
                         "echo Running uenvcmd ...;" \
                         "run uenvcmd;" \
                 "fi;" \
                 "echo Running default loadzimage ...;" \
                 "if run loadzimage; then " \
                         "run loadfdt;" \
                         "run mmcboot;" \
                 "fi;" \
         "else run netboot; fi"
 #endif
 #define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_STACKSIZE		SZ_128K
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_SIZE			SZ_8K
 /*
  * If want to use nand, define CONFIG_NAND_MXS and rework board
  * to support nand, since emmc has pin conflicts with nand
  */
 #ifdef CONFIG_SYS_USE_NAND
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
 /* NAND stuff */
 #define CONFIG_NAND_MXS
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		0x40000000
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* DMA stuff, needed for GPMI/MXS NAND support */
 #define CONFIG_APBH_DMA
 #define CONFIG_APBH_DMA_BURST
 #define CONFIG_APBH_DMA_BURST8
 #endif
 #ifdef CONFIG_SYS_USE_QSPI
 #define CONFIG_FSL_QSPI
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_MACRONIX
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_BUS		0
 #define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		40000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_QSPI_BASE		QSPI1_IPS_BASE_ADDR
 #define CONFIG_QSPI_MEMMAP_BASE		QSPI0_ARB_BASE_ADDR
 #endif
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_ENV_OFFSET		(12 * SZ_64K)
 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 #define CONFIG_ENV_OFFSET		(768 * 1024)
 #define CONFIG_ENV_SECT_SIZE		(64 * 1024)
 #define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
 #define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
 #elif defined(CONFIG_ENV_IS_IN_NAND)
 #undef CONFIG_ENV_SIZE
 #define CONFIG_ENV_OFFSET		(60 << 20)
 #define CONFIG_ENV_SECT_SIZE		(128 << 10)
 #define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
 #endif
 #ifdef CONFIG_SYS_USE_NAND
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 #else
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #endif
 /* MMC Config*/
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 #define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC3 */
 #define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC3 */
 /*#if defined(CONFIG_MX7D)
 #define CONFIG_DEFAULT_FDT_FILE 	"imx7d-smarcfimx7.dtb"
 #endif*/
 /* USB Configs */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX7
 #define CONFIG_USB_STORAGE
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS   0
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_IMX_THERMAL
 #define CONFIG_CMD_BMODE
 #define CONFIG_VIDEO
 #ifdef CONFIG_VIDEO
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_MXS
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
 /* #define CONFIG_SPLASH_SCREEN*/
 /* #define CONFIG_MXC_EPDC*/
 /*
  * SPLASH SCREEN Configs
  */
 #if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
 /*
  * Framebuffer and LCD
  */
 #define	CONFIG_CFB_CONSOLE
 #define CONFIG_CMD_BMP
 #define CONFIG_LCD
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #undef LCD_TEST_PATTERN
 /* #define CONFIG_SPLASH_IS_IN_MMC			1 */
 #define LCD_BPP					LCD_MONOCHROME
 /* #define CONFIG_SPLASH_SCREEN_ALIGN		1 */
 #define CONFIG_WAVEFORM_BUF_SIZE		0x400000
 #endif
 #if defined(CONFIG_MXC_EPDC) && defined(CONFIG_SYS_USE_QSPI)
 #error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!"
 #endif
 #if defined(CONFIG_ANDROID_SUPPORT)
 #include "mx7dsabresdandroid.h"
 #else
 #define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
 #define CONFIG_G_DNL_MANUFACTURER	"FSL"
 /* USB Device Firmware Update support */
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define CONFIG_DFU_RAM
 #endif
 #endif	/* __CONFIG_H */