Eric Lee / smarc-uboot

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Commit 9cb3e8816ae4d854e7dc22128c3eea3d70bb982c

Authored by Haiying Wang
Committed by Jon Loeliger
1 parent 239db37c94
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Change the space size of PEX IO in README

Showing 1 changed file with 2 additions and 2 deletions Inline Diff

doc/README.mpc8641hpcn
Diff comments   View file @ 9cb3e88
1 Freescale MPC8641HPCN board 1 Freescale MPC8641HPCN board
2 =========================== 2 ===========================
3 3
4 Created 05/24/2006 Haiying Wang 4 Created 05/24/2006 Haiying Wang
5 ------------------------------- 5 -------------------------------
6 6
7 1. Building U-Boot 7 1. Building U-Boot
8 ------------------ 8 ------------------
9 The 86xx HPCN code base is known to compile using: 9 The 86xx HPCN code base is known to compile using:
10 Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 10 Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
11 11
12 $ make MPC8641HPCN_config 12 $ make MPC8641HPCN_config
13 Configuring for MPC8641HPCN board... 13 Configuring for MPC8641HPCN board...
14 14
15 $ make 15 $ make
16 16
17 17
18 2. Switch and Jumper Setting 18 2. Switch and Jumper Setting
19 ---------------------------- 19 ----------------------------
20 Jumpers: 20 Jumpers:
21 J14 Pins 1-2 (near plcc32 socket) 21 J14 Pins 1-2 (near plcc32 socket)
22 22
23 Switches: 23 Switches:
24 SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1 24 SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1
25 01100 :: CORE = 2.5:1 25 01100 :: CORE = 2.5:1
26 10000 :: CORE = 3:1 26 10000 :: CORE = 3:1
27 11100 :: CORE = 3.5:1 27 11100 :: CORE = 3.5:1
28 10100 :: CORE = 4:1 28 10100 :: CORE = 4:1
29 01110 :: CORE = 4.5:1 29 01110 :: CORE = 4.5:1
30 SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz 30 SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz
31 001 :: SYSCLK = 40MHz 31 001 :: SYSCLK = 40MHz
32 32
33 SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X 33 SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X
34 0100 :: 4X 34 0100 :: 4X
35 0110 :: 6X 35 0110 :: 6X
36 1000 :: 8X 36 1000 :: 8X
37 1010 :: 10X 37 1010 :: 10X
38 1100 :: 12X 38 1100 :: 12X
39 1110 :: 14X 39 1110 :: 14X
40 0000 :: 16X 40 0000 :: 16X
41 SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus 41 SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus
42 42
43 SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V 43 SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V
44 0100000 :: VCORE = 1.11V 44 0100000 :: VCORE = 1.11V
45 SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V 45 SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
46 1 :: VCC_PLAT = 1.0V 46 1 :: VCC_PLAT = 1.0V
47 47
48 SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root 48 SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root
49 SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq 49 SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq
50 SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX 50 SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX
51 51
52 SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash 52 SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash
53 0 :: boot from PromJet 53 0 :: boot from PromJet
54 SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower 54 SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower
55 halves (virtual banks) 55 halves (virtual banks)
56 0 :: normal 56 0 :: normal
57 SW5(3) = 0 CFG_FLASHWP = 0 :: not protected 57 SW5(3) = 0 CFG_FLASHWP = 0 :: not protected
58 SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4 58 SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4
59 1:1 for PD6 59 1:1 for PD6
60 SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined 60 SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined
61 SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined 61 SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined
62 62
63 SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff 63 SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff
64 SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation 64 SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation
65 SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ 65 SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ
66 SW6(6) = 1 CFG_SERROM_ADDR= 1 :: 66 SW6(6) = 1 CFG_SERROM_ADDR= 1 ::
67 SW6(7) = 1 CFG_MEMDEBUG = 1 :: 67 SW6(7) = 1 CFG_MEMDEBUG = 1 ::
68 SW6(8) = 1 CFG_DDRDEBUG = 1 :: 68 SW6(8) = 1 CFG_DDRDEBUG = 1 ::
69 69
70 SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49 70 SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
71 SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled 71 SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
72 SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode 72 SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
73 SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz 73 SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
74 SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode 74 SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
75 SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled 75 SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
76 SW8(7) = 1 ACPWR = 1 :: non-battery 76 SW8(7) = 1 ACPWR = 1 :: non-battery
77 SW8(8) = 0 CFG_IDWP = 0 :: write enable 77 SW8(8) = 0 CFG_IDWP = 0 :: write enable
78 78
79 79
80 3. Flash U-Boot 80 3. Flash U-Boot
81 --------------- 81 ---------------
82 The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves. 82 The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
83 It is possible to use either half to boot using u-boot. Switch 5 bit 2 83 It is possible to use either half to boot using u-boot. Switch 5 bit 2
84 is used for this purpose. 84 is used for this purpose.
85 85
86 0xFF800000 to 0xFFBFFFFF - 4MB 86 0xFF800000 to 0xFFBFFFFF - 4MB
87 0xFFC00000 to 0xFFFFFFFF - 4MB 87 0xFFC00000 to 0xFFFFFFFF - 4MB
88 When this bit is 0, U-Boot is at 0xFFF00000. 88 When this bit is 0, U-Boot is at 0xFFF00000.
89 When this bit is 1, U-Boot is at 0xFFB00000. 89 When this bit is 1, U-Boot is at 0xFFB00000.
90 90
91 Use the above mentioned flash commands to program the other half, and 91 Use the above mentioned flash commands to program the other half, and
92 use switch 5, bit 2 to alternate between the halves. Note: The booting 92 use switch 5, bit 2 to alternate between the halves. Note: The booting
93 version of U-Boot will always be at 0xFFF00000. 93 version of U-Boot will always be at 0xFFF00000.
94 94
95 To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF): 95 To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
96 96
97 tftp 1000000 u-boot.bin 97 tftp 1000000 u-boot.bin
98 protect off all 98 protect off all
99 erase fff00000 ffffffff 99 erase fff00000 ffffffff
100 cp.b 1000000 fff00100 80000 100 cp.b 1000000 fff00100 80000
101 101
102 To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): 102 To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
103 103
104 tftp 1000000 u-boot.bin 104 tftp 1000000 u-boot.bin
105 erase ffb00000 ffbfffff 105 erase ffb00000 ffbfffff
106 cp.b 1000000 ffb00100 80000 106 cp.b 1000000 ffb00100 80000
107 107
108 108
109 4. Memory Map 109 4. Memory Map
110 ------------- 110 -------------
111 111
112 Memory Range Device Size 112 Memory Range Device Size
113 ------------ ------ ---- 113 ------------ ------ ----
114 0x0000_0000 0x7fff_ffff DDR 2G 114 0x0000_0000 0x7fff_ffff DDR 2G
115 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M 115 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
116 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M 116 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M
117 0xf800_0000 0xf80f_ffff CCSR 1M 117 0xf800_0000 0xf80f_ffff CCSR 1M
118 0xf810_0000 0xf81f_ffff PIXIS 1M 118 0xf810_0000 0xf81f_ffff PIXIS 1M
119 0xf840_0000 0xf840_3fff Stack space 32K 119 0xf840_0000 0xf840_3fff Stack space 32K
120 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 512M 120 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M
121 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 512M 121 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
122 0xfe00_0000 0xfeff_ffff Flash(alternate)16M 122 0xfe00_0000 0xfeff_ffff Flash(alternate)16M
123 0xff00_0000 0xffff_ffff Flash(boot bank)16M 123 0xff00_0000 0xffff_ffff Flash(boot bank)16M
124 124