Eric Lee / smarc-uboot | Embedian Git Server

Commit 9fafe7dab9bc8a9e33e1ba5e28a3ec870d689b82

Authored by Troy Kisky 2012-02-07 22:08:49 +0800

Committed by Albert ARIBAUD 2012-02-28 04:19:25 +0800

Exists in master and in 55 other branches

net: phy: make board_phy_config responsible for calling drv->config

Boards may have things they want done before or after normal phy config.
Letting the boards call drv->config allows them more flexibilty.
Boards affected by this change are corenet_ds and mpc8544ds.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>

Showing 3 changed files with 6 additions and 3 deletions Inline Diff

board/freescale/corenet_ds/eth_p4080.c
board/freescale/mpc8544ds/mpc8544ds.c
drivers/net/phy/phy.c

board/freescale/corenet_ds/eth_p4080.c

Diff comments View file @ 9fafe7d

 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <command.h>
 #include <netdev.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 #include <malloc.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
 #include <asm/fsl_dtsec.h>
 #define EMI_NONE	0xffffffff
 #define EMI_MASK	0xf0000000
 #define EMI1_RGMII	0x0
 #define EMI1_SLOT3	0x80000000	/* bank1 EFGH */
 #define EMI1_SLOT4	0x40000000	/* bank2 ABCD */
 #define EMI1_SLOT5	0xc0000000	/* bank3 ABCD */
 #define EMI2_SLOT4	0x10000000	/* bank2 ABCD */
 #define EMI2_SLOT5	0x30000000	/* bank3 ABCD */
 #define EMI1_MASK	0xc0000000
 #define EMI2_MASK	0x30000000
 static int mdio_mux[NUM_FM_PORTS];
 static char *mdio_names[16] = {
 	"P4080DS_MDIO0",
 	"P4080DS_MDIO1",
 	NULL,
 	"P4080DS_MDIO3",
 	"P4080DS_MDIO4",
 	NULL, NULL, NULL,
 	"P4080DS_MDIO8",
 	NULL, NULL, NULL,
 	"P4080DS_MDIO12",
 	NULL, NULL, NULL,
 };
 static char *p4080ds_mdio_name_for_muxval(u32 muxval)
 {
 	return mdio_names[(muxval & EMI_MASK) >> 28];
 }
 struct mii_dev *mii_dev_for_muxval(u32 muxval)
 {
 	struct mii_dev *bus;
 	char *name = p4080ds_mdio_name_for_muxval(muxval);
 	if (!name) {
 		printf("No bus for muxval %x\n", muxval);
 		return NULL;
 	}
 	bus = miiphy_get_dev_by_name(name);
 	if (!bus) {
 		printf("No bus by name %s\n", name);
 		return NULL;
 	}
 	return bus;
 }
 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
 int board_phy_config(struct phy_device *phydev)
 {
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
 	if (phydev->drv->uid == PHY_UID_TN2020) {
 		unsigned long timeout = 1 * 1000; /* 1 seconds */
 		enum srds_prtcl device;
 		/*
 		 * Wait for the XAUI to come out of reset.  This is when it
 		 * starts transmitting alignment signals.
 		 */
 		while (--timeout) {
 			int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
 			if (reg < 0) {
 				printf("TN2020: Error reading from PHY at "
 				       "address %u\n", phydev->addr);
 				break;
 			}
 			/*
 			 * Note that we've never actually seen
 			 * MDIO_CTRL1_RESET set to 1.
 			 */
 			if ((reg & MDIO_CTRL1_RESET) == 0)
 				break;
 			udelay(1000);
 		}
 		if (!timeout) {
 			printf("TN2020: Timeout waiting for PHY at address %u "
 			       " to reset.\n", phydev->addr);
 		}
 		switch (phydev->addr) {
 		case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
 			device = XAUI_FM1;
 			break;
 		case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
 			device = XAUI_FM2;
 			break;
 		default:
 			device = NONE;
 		}
 		serdes_reset_rx(device);
 	}
 	return 0;
 }
 #endif
 struct p4080ds_mdio {
 	u32 muxval;
 	struct mii_dev *realbus;
 };
 static void p4080ds_mux_mdio(u32 muxval)
 {
 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 	uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
 	gpioval |= muxval;
 	out_be32(&pgpio->gpdat, gpioval);
 }
 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
 				int regnum)
 {
 	struct p4080ds_mdio *priv = bus->priv;
 	p4080ds_mux_mdio(priv->muxval);
 	return priv->realbus->read(priv->realbus, addr, devad, regnum);
 }
 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
 				int regnum, u16 value)
 {
 	struct p4080ds_mdio *priv = bus->priv;
 	p4080ds_mux_mdio(priv->muxval);
 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 }
 static int p4080ds_mdio_reset(struct mii_dev *bus)
 {
 	struct p4080ds_mdio *priv = bus->priv;
 	return priv->realbus->reset(priv->realbus);
 }
 static int p4080ds_mdio_init(char *realbusname, u32 muxval)
 {
 	struct p4080ds_mdio *pmdio;
 	struct mii_dev *bus = mdio_alloc();
 	if (!bus) {
 		printf("Failed to allocate P4080DS MDIO bus\n");
 		return -1;
 	}
 	pmdio = malloc(sizeof(*pmdio));
 	if (!pmdio) {
 		printf("Failed to allocate P4080DS private data\n");
 		free(bus);
 		return -1;
 	}
 	bus->read = p4080ds_mdio_read;
 	bus->write = p4080ds_mdio_write;
 	bus->reset = p4080ds_mdio_reset;
 	sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 	if (!pmdio->realbus) {
 		printf("No bus with name %s\n", realbusname);
 		free(bus);
 		free(pmdio);
 		return -1;
 	}
 	pmdio->muxval = muxval;
 	bus->priv = pmdio;
 	return mdio_register(bus);
 }
 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 				enum fm_port port, int offset)
 {
 	if (mdio_mux[port] == EMI1_RGMII)
 		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
 	if (mdio_mux[port] == EMI1_SLOT3) {
 		int idx = port - FM2_DTSEC1 + 5;
 		char phy[16];
 		sprintf(phy, "phy%d_slot3", idx);
 		fdt_set_phy_handle(blob, prop, pa, phy);
 	}
 }
 void fdt_fixup_board_enet(void *fdt)
 {
 	int i;
 	/*
 	 * P4080DS can be configured in many different ways, supporting a number
 	 * of combinations of ethernet devices and phy types.  In order to
 	 * have just one device tree for all of those configurations, we fix up
 	 * the tree here.  By default, the device tree configures FM1 and FM2
 	 * for SGMII, and configures XAUI on both 10G interfaces.  So we have
 	 * a number of different variables to track:
 	 *
 	 * 1) Whether the device is configured at all.  Whichever devices are
 	 *    not enabled should be disabled by setting the "status" property
 	 *    to "disabled".
 	 * 2) What the PHY interface is.  If this is an RGMII connection,
 	 *    we should change the "phy-connection-type" property to
 	 *    "rgmii"
 	 * 3) Which PHY is being used.  Because the MDIO buses are muxed,
 	 *    we need to redirect the "phy-handle" property to point at the
 	 *    PHY on the right slot/bus.
 	 */
 	/* We've got six MDIO nodes that may or may not need to exist */
 	fdt_status_disabled_by_alias(fdt, "emi1_slot3");
 	fdt_status_disabled_by_alias(fdt, "emi1_slot4");
 	fdt_status_disabled_by_alias(fdt, "emi1_slot5");
 	fdt_status_disabled_by_alias(fdt, "emi2_slot4");
 	fdt_status_disabled_by_alias(fdt, "emi2_slot5");
 	for (i = 0; i < NUM_FM_PORTS; i++) {
 		switch (mdio_mux[i]) {
 		case EMI1_SLOT3:
 			fdt_status_okay_by_alias(fdt, "emi1_slot3");
 			break;
 		case EMI1_SLOT4:
 			fdt_status_okay_by_alias(fdt, "emi1_slot4");
 			break;
 		case EMI1_SLOT5:
 			fdt_status_okay_by_alias(fdt, "emi1_slot5");
 			break;
 		case EMI2_SLOT4:
 			fdt_status_okay_by_alias(fdt, "emi2_slot4");
 			break;
 		case EMI2_SLOT5:
 			fdt_status_okay_by_alias(fdt, "emi2_slot5");
 			break;
 		}
 	}
 }
 enum board_slots {
 	SLOT1 = 1,
 	SLOT2,
 	SLOT3,
 	SLOT4,
 	SLOT5,
 	SLOT6,
 };
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 	int i;
 	struct fsl_pq_mdio_info dtsec_mdio_info;
 	struct tgec_mdio_info tgec_mdio_info;
 	u8 lane_to_slot[] = {
 		SLOT1, /* 0 - Bank 1:A */
 		SLOT1, /* 1 - Bank 1:B */
 		SLOT2, /* 2 - Bank 1:C */
 		SLOT2, /* 3 - Bank 1:D */
 		SLOT3, /* 4 - Bank 1:E */
 		SLOT3, /* 5 - Bank 1:F */
 		SLOT3, /* 6 - Bank 1:G */
 		SLOT3, /* 7 - Bank 1:H */
 		SLOT6, /* 8 - Bank 1:I */
 		SLOT6, /* 9 - Bank 1:J */
 		SLOT4, /* 10 - Bank 2:A */
 		SLOT4, /* 11 - Bank 2:B */
 		SLOT4, /* 12 - Bank 2:C */
 		SLOT4, /* 13 - Bank 2:D */
 		SLOT5, /* 14 - Bank 3:A */
 		SLOT5, /* 15 - Bank 3:B */
 		SLOT5, /* 16 - Bank 3:C */
 		SLOT5, /* 17 - Bank 3:D */
 	};
 	/* Initialize the mdio_mux array so we can recognize empty elements */
 	for (i = 0; i < NUM_FM_PORTS; i++)
 		mdio_mux[i] = EMI_NONE;
 	/* The first 4 GPIOs are outputs to control MDIO bus muxing */
 	out_be32(&pgpio->gpdir, EMI_MASK);
 	dtsec_mdio_info.regs =
 		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 	/* Register the 1G MDIO bus */
 	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
 	tgec_mdio_info.regs =
 		(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 	/* Register the 10G MDIO bus */
 	fm_tgec_mdio_init(bis, &tgec_mdio_info);
 	/* Register the 6 muxing front-ends to the MDIO buses */
 	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
 	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 	p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
 	p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
 	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
 	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
 	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
 	fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
 	fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
 #if (CONFIG_SYS_NUM_FMAN == 2)
 	fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
 	fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
 	fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
 	fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
 	fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
 #endif
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		int idx = i - FM1_DTSEC1, lane, slot;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_SGMII:
 			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
 			if (lane < 0)
 				break;
 			slot = lane_to_slot[lane];
 			switch (slot) {
 			case SLOT3:
 				mdio_mux[i] = EMI1_SLOT3;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			case SLOT4:
 				mdio_mux[i] = EMI1_SLOT4;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			case SLOT5:
 				mdio_mux[i] = EMI1_SLOT5;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			};
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
 			fm_info_set_phy_address(i, 0);
 			mdio_mux[i] = EMI1_RGMII;
 			fm_info_set_mdio(i,
 				mii_dev_for_muxval(mdio_mux[i]));
 			break;
 		default:
 			break;
 		}
 	}
 	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 		int idx = i - FM1_10GEC1, lane, slot;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
 			lane = serdes_get_first_lane(XAUI_FM1 + idx);
 			if (lane < 0)
 				break;
 			slot = lane_to_slot[lane];
 			switch (slot) {
 			case SLOT4:
 				mdio_mux[i] = EMI2_SLOT4;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			case SLOT5:
 				mdio_mux[i] = EMI2_SLOT5;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			};
 			break;
 		default:
 			break;
 		}
 	}
 #if (CONFIG_SYS_NUM_FMAN == 2)
 	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 		int idx = i - FM2_DTSEC1, lane, slot;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_SGMII:
 			lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
 			if (lane < 0)
 				break;
 			slot = lane_to_slot[lane];
 			switch (slot) {
 			case SLOT3:
 				mdio_mux[i] = EMI1_SLOT3;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			case SLOT4:
 				mdio_mux[i] = EMI1_SLOT4;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			case SLOT5:
 				mdio_mux[i] = EMI1_SLOT5;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			};
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
 			fm_info_set_phy_address(i, 0);
 			mdio_mux[i] = EMI1_RGMII;
 			fm_info_set_mdio(i,
 				mii_dev_for_muxval(mdio_mux[i]));
 			break;
 		default:
 			break;
 		}
 	}
 	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 		int idx = i - FM2_10GEC1, lane, slot;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
 			lane = serdes_get_first_lane(XAUI_FM2 + idx);
 			if (lane < 0)
 				break;
 			slot = lane_to_slot[lane];
 			switch (slot) {
 			case SLOT4:
 				mdio_mux[i] = EMI2_SLOT4;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			case SLOT5:
 				mdio_mux[i] = EMI2_SLOT5;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
 			};
 			break;
 		default:
 			break;
 		}
 	}
 #endif
 	cpu_eth_init(bis);
 #endif /* CONFIG_FMAN_ENET */
 	return pci_eth_init(bis);
 }

board/freescale/mpc8544ds/mpc8544ds.c

Diff comments View file @ 9fafe7d

 /*
  * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <command.h>
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/io.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <fsl_mdio.h>
 #include <tsec.h>
 #include <netdev.h>
 #include "../common/sgmii_riser.h"
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	u8 vboot;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	if ((uint)&gur->porpllsr != 0xe00e0000) {
 		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
 	}
 	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
 		in_8(pixis_base + PIXIS_PVER));
 	vboot = in_8(pixis_base + PIXIS_VBOOT);
 	if (vboot & PIXIS_VBOOT_FMAP)
 		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
 	else
 		puts ("Promjet\n");
 	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
 	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
 	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
 	ecm->eeer = 0xffffffff;		/* Enable ecm errors */
 	return 0;
 }
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif
 #ifdef CONFIG_PCIE3
 static struct pci_controller pcie3_hose;
 #endif
 void pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	struct fsl_pci_info pci_info;
 	u32 devdisr, pordevsr, io_sel;
 	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
 	int first_free_busno = 0;
 	int pcie_ep, pcie_configured;
 	devdisr = in_be32(&gur->devdisr);
 	pordevsr = in_be32(&gur->pordevsr);
 	porpllsr = in_be32(&gur->porpllsr);
 	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 	puts("\n");
 #ifdef CONFIG_PCIE3
 	pcie_configured = is_serdes_configured(PCIE3);
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 		/* contains both PCIE3 MEM & IO space */
 		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
 				LAW_TRGT_IF_PCIE_3);
 		SET_STD_PCIE_INFO(pci_info, 3);
 		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
 		/* outbound memory */
 		pci_set_region(&pcie3_hose.regions[0],
 			       CONFIG_SYS_PCIE3_MEM_BUS2,
 			       CONFIG_SYS_PCIE3_MEM_PHYS2,
 			       CONFIG_SYS_PCIE3_MEM_SIZE2,
 			       PCI_REGION_MEM);
 		pcie3_hose.region_count = 1;
 		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
 			pcie_ep ? "Endpoint" : "Root Complex",
 			pci_info.regs);
 		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pcie3_hose, first_free_busno);
 		/*
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
 		 */
 		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
 	} else {
 		printf("PCIE3: disabled\n");
 	}
 	puts("\n");
 #else
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
 #endif
 #ifdef CONFIG_PCIE1
 	SET_STD_PCIE_INFO(pci_info, 1);
 	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
 #else
 	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
 #endif
 #ifdef CONFIG_PCIE2
 	SET_STD_PCIE_INFO(pci_info, 2);
 	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
 #else
 	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
 #endif
 #ifdef CONFIG_PCI1
 	pci_speed = 66666000;
 	pci_32 = 1;
 	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 		SET_STD_PCI_INFO(pci_info, 1);
 		set_next_law(pci_info.mem_phys,
 			law_size_bits(pci_info.mem_size), pci_info.law);
 		set_next_law(pci_info.io_phys,
 			law_size_bits(pci_info.io_size), pci_info.law);
 		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333000) ? "33" :
 			(pci_speed == 66666000) ? "66" : "unknown",
 			pci_clk_sel ? "sync" : "async",
 			pci_agent ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter",
 			pci_info.regs);
 		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI: disabled\n");
 	}
 	puts("\n");
 #else
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 #endif
 }
 int last_stage_init(void)
 {
 	return 0;
 }
 unsigned long
 get_board_sys_clk(ulong dummy)
 {
 	u8 i, go_bit, rd_clks;
 	ulong val = 0;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	go_bit = in_8(pixis_base + PIXIS_VCTL);
 	go_bit &= 0x01;
 	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
 	rd_clks &= 0x1C;
 	/*
 	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
 	 * should we be using the AUX register. Remember, we also set the
 	 * GO bit to boot from the alternate bank on the on-board flash
 	 */
 	if (go_bit) {
 		if (rd_clks == 0x1c)
 			i = in_8(pixis_base + PIXIS_AUX);
 		else
 			i = in_8(pixis_base + PIXIS_SPD);
 	} else {
 		i = in_8(pixis_base + PIXIS_SPD);
 	}
 	i &= 0x07;
 	switch (i) {
 	case 0:
 		val = 33333333;
 		break;
 	case 1:
 		val = 40000000;
 		break;
 	case 2:
 		val = 50000000;
 		break;
 	case 3:
 		val = 66666666;
 		break;
 	case 4:
 		val = 83000000;
 		break;
 	case 5:
 		val = 100000000;
 		break;
 	case 6:
 		val = 133333333;
 		break;
 	case 7:
 		val = 166666666;
 		break;
 	}
 	return val;
 }
 #define MIIM_CIS8204_SLED_CON		0x1b
 #define MIIM_CIS8204_SLEDCON_INIT	0x1115
 /*
  * Hack to write all 4 PHYs with the LED values
  */
 int board_phy_config(struct phy_device *phydev)
 {
 	static int do_once;
 	uint phyid;
 	struct mii_dev *bus = phydev->bus;
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
 	if (do_once)
 		return 0;
 	for (phyid = 0; phyid < 4; phyid++)
 		bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
 				MIIM_CIS8204_SLEDCON_INIT);
 	do_once = 1;
 	return 0;
 }
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_TSEC_ENET
 	struct fsl_pq_mdio_info mdio_info;
 	struct tsec_info_struct tsec_info[2];
 	int num = 0;
 #ifdef CONFIG_TSEC1
 	SET_STD_TSEC_INFO(tsec_info[num], 1);
 	if (is_serdes_configured(SGMII_TSEC1)) {
 		puts("eTSEC1 is in sgmii mode.\n");
 		tsec_info[num].flags |= TSEC_SGMII;
 	}
 	num++;
 #endif
 #ifdef CONFIG_TSEC3
 	SET_STD_TSEC_INFO(tsec_info[num], 3);
 	if (is_serdes_configured(SGMII_TSEC3)) {
 		puts("eTSEC3 is in sgmii mode.\n");
 		tsec_info[num].flags |= TSEC_SGMII;
 	}
 	num++;
 #endif
 	if (!num) {
 		printf("No TSECs initialized\n");
 		return 0;
 	}
 	if (is_serdes_configured(SGMII_TSEC1) ||
 	    is_serdes_configured(SGMII_TSEC3)) {
 		fsl_sgmii_riser_init(tsec_info, num);
 	}
 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 	mdio_info.name = DEFAULT_MII_NAME;
 	fsl_pq_mdio_init(bis, &mdio_info);
 	tsec_eth_init(bis, tsec_info, num);
 #endif
 	return pci_eth_init(bis);
 }
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 	FT_FSL_PCI_SETUP;
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
 #endif
 }
 #endif

drivers/net/phy/phy.c

Diff comments View file @ 9fafe7d

 /*
  * Generic PHY Management code
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
  *
  * Copyright 2011 Freescale Semiconductor, Inc.
  * author Andy Fleming
  *
  * Based loosely off of Linux's PHY Lib
  */
 #include <config.h>
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
 #include <command.h>
 #include <miiphy.h>
 #include <phy.h>
 #include <errno.h>
 /* Generic PHY support and helper functions */
 /**
  * genphy_config_advert - sanitize and advertise auto-negotation parameters
  * @phydev: target phy_device struct
  *
  * Description: Writes MII_ADVERTISE with the appropriate values,
  *   after sanitizing the values to make sure we only advertise
  *   what is supported.  Returns < 0 on error, 0 if the PHY's advertisement
  *   hasn't changed, and > 0 if it has changed.
  */
 int genphy_config_advert(struct phy_device *phydev)
 {
 	u32 advertise;
 	int oldadv, adv;
 	int err, changed = 0;
 	/* Only allow advertising what
 	 * this PHY supports */
 	phydev->advertising &= phydev->supported;
 	advertise = phydev->advertising;
 	/* Setup standard advertisement */
 	oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
 	if (adv < 0)
 		return adv;
 	adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
 		 ADVERTISE_PAUSE_ASYM);
 	if (advertise & ADVERTISED_10baseT_Half)
 		adv |= ADVERTISE_10HALF;
 	if (advertise & ADVERTISED_10baseT_Full)
 		adv |= ADVERTISE_10FULL;
 	if (advertise & ADVERTISED_100baseT_Half)
 		adv |= ADVERTISE_100HALF;
 	if (advertise & ADVERTISED_100baseT_Full)
 		adv |= ADVERTISE_100FULL;
 	if (advertise & ADVERTISED_Pause)
 		adv |= ADVERTISE_PAUSE_CAP;
 	if (advertise & ADVERTISED_Asym_Pause)
 		adv |= ADVERTISE_PAUSE_ASYM;
 	if (adv != oldadv) {
 		err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv);
 		if (err < 0)
 			return err;
 		changed = 1;
 	}
 	/* Configure gigabit if it's supported */
 	if (phydev->supported & (SUPPORTED_1000baseT_Half |
 				SUPPORTED_1000baseT_Full)) {
 		oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
 		if (adv < 0)
 			return adv;
 		adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 		if (advertise & SUPPORTED_1000baseT_Half)
 			adv |= ADVERTISE_1000HALF;
 		if (advertise & SUPPORTED_1000baseT_Full)
 			adv |= ADVERTISE_1000FULL;
 		if (adv != oldadv) {
 			err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000,
 					adv);
 			if (err < 0)
 				return err;
 			changed = 1;
 		}
 	}
 	return changed;
 }
 /**
  * genphy_setup_forced - configures/forces speed/duplex from @phydev
  * @phydev: target phy_device struct
  *
  * Description: Configures MII_BMCR to force speed/duplex
  *   to the values in phydev. Assumes that the values are valid.
  */
 int genphy_setup_forced(struct phy_device *phydev)
 {
 	int err;
 	int ctl = 0;
 	phydev->pause = phydev->asym_pause = 0;
 	if (SPEED_1000 == phydev->speed)
 		ctl |= BMCR_SPEED1000;
 	else if (SPEED_100 == phydev->speed)
 		ctl |= BMCR_SPEED100;
 	if (DUPLEX_FULL == phydev->duplex)
 		ctl |= BMCR_FULLDPLX;
 	err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
 	return err;
 }
 /**
  * genphy_restart_aneg - Enable and Restart Autonegotiation
  * @phydev: target phy_device struct
  */
 int genphy_restart_aneg(struct phy_device *phydev)
 {
 	int ctl;
 	ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
 	if (ctl < 0)
 		return ctl;
 	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
 	/* Don't isolate the PHY if we're negotiating */
 	ctl &= ~(BMCR_ISOLATE);
 	ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
 	return ctl;
 }
 /**
  * genphy_config_aneg - restart auto-negotiation or write BMCR
  * @phydev: target phy_device struct
  *
  * Description: If auto-negotiation is enabled, we configure the
  *   advertising, and then restart auto-negotiation.  If it is not
  *   enabled, then we write the BMCR.
  */
 int genphy_config_aneg(struct phy_device *phydev)
 {
 	int result;
 	if (AUTONEG_ENABLE != phydev->autoneg)
 		return genphy_setup_forced(phydev);
 	result = genphy_config_advert(phydev);
 	if (result < 0) /* error */
 		return result;
 	if (result == 0) {
 		/* Advertisment hasn't changed, but maybe aneg was never on to
 		 * begin with?  Or maybe phy was isolated? */
 		int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
 		if (ctl < 0)
 			return ctl;
 		if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
 			result = 1; /* do restart aneg */
 	}
 	/* Only restart aneg if we are advertising something different
 	 * than we were before.	 */
 	if (result > 0)
 		result = genphy_restart_aneg(phydev);
 	return result;
 }
 /**
  * genphy_update_link - update link status in @phydev
  * @phydev: target phy_device struct
  *
  * Description: Update the value in phydev->link to reflect the
  *   current link value.  In order to do this, we need to read
  *   the status register twice, keeping the second value.
  */
 int genphy_update_link(struct phy_device *phydev)
 {
 	unsigned int mii_reg;
 	/*
 	 * Wait if the link is up, and autonegotiation is in progress
 	 * (ie - we're capable and it's not done)
 	 */
 	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
 	/*
 	 * If we already saw the link up, and it hasn't gone down, then
 	 * we don't need to wait for autoneg again
 	 */
 	if (phydev->link && mii_reg & BMSR_LSTATUS)
 		return 0;
 	if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) {
 		int i = 0;
 		printf("%s Waiting for PHY auto negotiation to complete",
 			phydev->dev->name);
 		while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
 			/*
 			 * Timeout reached ?
 			 */
 			if (i > PHY_ANEG_TIMEOUT) {
 				printf(" TIMEOUT !\n");
 				phydev->link = 0;
 				return 0;
 			}
 			if (ctrlc()) {
 				puts("user interrupt!\n");
 				phydev->link = 0;
 				return -EINTR;
 			}
 			if ((i++ % 500) == 0)
 				printf(".");
 			udelay(1000);	/* 1 ms */
 			mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
 		}
 		printf(" done\n");
 		phydev->link = 1;
 	} else {
 		/* Read the link a second time to clear the latched state */
 		mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
 		if (mii_reg & BMSR_LSTATUS)
 			phydev->link = 1;
 		else
 			phydev->link = 0;
 	}
 	return 0;
 }
 /*
  * Generic function which updates the speed and duplex.  If
  * autonegotiation is enabled, it uses the AND of the link
  * partner's advertised capabilities and our advertised
  * capabilities.  If autonegotiation is disabled, we use the
  * appropriate bits in the control register.
  *
  * Stolen from Linux's mii.c and phy_device.c
  */
 static int genphy_parse_link(struct phy_device *phydev)
 {
 	int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
 	/* We're using autonegotiation */
 	if (mii_reg & BMSR_ANEGCAPABLE) {
 		u32 lpa = 0;
 		u32 gblpa = 0;
 		/* Check for gigabit capability */
 		if (mii_reg & BMSR_ERCAP) {
 			/* We want a list of states supported by
 			 * both PHYs in the link
 			 */
 			gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
 			gblpa &= phy_read(phydev,
 					MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
 		}
 		/* Set the baseline so we only have to set them
 		 * if they're different
 		 */
 		phydev->speed = SPEED_10;
 		phydev->duplex = DUPLEX_HALF;
 		/* Check the gigabit fields */
 		if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
 			phydev->speed = SPEED_1000;
 			if (gblpa & PHY_1000BTSR_1000FD)
 				phydev->duplex = DUPLEX_FULL;
 			/* We're done! */
 			return 0;
 		}
 		lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
 		lpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
 		if (lpa & (LPA_100FULL | LPA_100HALF)) {
 			phydev->speed = SPEED_100;
 			if (lpa & LPA_100FULL)
 				phydev->duplex = DUPLEX_FULL;
 		} else if (lpa & LPA_10FULL)
 			phydev->duplex = DUPLEX_FULL;
 	} else {
 		u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
 		phydev->speed = SPEED_10;
 		phydev->duplex = DUPLEX_HALF;
 		if (bmcr & BMCR_FULLDPLX)
 			phydev->duplex = DUPLEX_FULL;
 		if (bmcr & BMCR_SPEED1000)
 			phydev->speed = SPEED_1000;
 		else if (bmcr & BMCR_SPEED100)
 			phydev->speed = SPEED_100;
 	}
 	return 0;
 }
 int genphy_config(struct phy_device *phydev)
 {
 	int val;
 	u32 features;
 	/* For now, I'll claim that the generic driver supports
 	 * all possible port types */
 	features = (SUPPORTED_TP | SUPPORTED_MII
 			| SUPPORTED_AUI | SUPPORTED_FIBRE |
 			SUPPORTED_BNC);
 	/* Do we support autonegotiation? */
 	val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
 	if (val < 0)
 		return val;
 	if (val & BMSR_ANEGCAPABLE)
 		features |= SUPPORTED_Autoneg;
 	if (val & BMSR_100FULL)
 		features |= SUPPORTED_100baseT_Full;
 	if (val & BMSR_100HALF)
 		features |= SUPPORTED_100baseT_Half;
 	if (val & BMSR_10FULL)
 		features |= SUPPORTED_10baseT_Full;
 	if (val & BMSR_10HALF)
 		features |= SUPPORTED_10baseT_Half;
 	if (val & BMSR_ESTATEN) {
 		val = phy_read(phydev, MDIO_DEVAD_NONE, MII_ESTATUS);
 		if (val < 0)
 			return val;
 		if (val & ESTATUS_1000_TFULL)
 			features |= SUPPORTED_1000baseT_Full;
 		if (val & ESTATUS_1000_THALF)
 			features |= SUPPORTED_1000baseT_Half;
 	}
 	phydev->supported = features;
 	phydev->advertising = features;
 	genphy_config_aneg(phydev);
 	return 0;
 }
 int genphy_startup(struct phy_device *phydev)
 {
 	genphy_update_link(phydev);
 	genphy_parse_link(phydev);
 	return 0;
 }
 int genphy_shutdown(struct phy_device *phydev)
 {
 	return 0;
 }
 static struct phy_driver genphy_driver = {
 	.uid		= 0xffffffff,
 	.mask		= 0xffffffff,
 	.name		= "Generic PHY",
 	.features	= 0,
 	.config		= genphy_config,
 	.startup	= genphy_startup,
 	.shutdown	= genphy_shutdown,
 };
 static LIST_HEAD(phy_drivers);
 int phy_init(void)
 {
 #ifdef CONFIG_PHY_ATHEROS
 	phy_atheros_init();
 #endif
 #ifdef CONFIG_PHY_BROADCOM
 	phy_broadcom_init();
 #endif
 #ifdef CONFIG_PHY_DAVICOM
 	phy_davicom_init();
 #endif
 #ifdef CONFIG_PHY_LXT
 	phy_lxt_init();
 #endif
 #ifdef CONFIG_PHY_MARVELL
 	phy_marvell_init();
 #endif
 #ifdef CONFIG_PHY_MICREL
 	phy_micrel_init();
 #endif
 #ifdef CONFIG_PHY_NATSEMI
 	phy_natsemi_init();
 #endif
 #ifdef CONFIG_PHY_REALTEK
 	phy_realtek_init();
 #endif
 #ifdef CONFIG_PHY_SMSC
 	phy_smsc_init();
 #endif
 #ifdef CONFIG_PHY_TERANETICS
 	phy_teranetics_init();
 #endif
 #ifdef CONFIG_PHY_VITESSE
 	phy_vitesse_init();
 #endif
 	return 0;
 }
 int phy_register(struct phy_driver *drv)
 {
 	INIT_LIST_HEAD(&drv->list);
 	list_add_tail(&drv->list, &phy_drivers);
 	return 0;
 }
 int phy_probe(struct phy_device *phydev)
 {
 	int err = 0;
 	phydev->advertising = phydev->supported = phydev->drv->features;
 	phydev->mmds = phydev->drv->mmds;
 	if (phydev->drv->probe)
 		err = phydev->drv->probe(phydev);
 	return err;
 }
 static struct phy_driver *generic_for_interface(phy_interface_t interface)
 {
 #ifdef CONFIG_PHYLIB_10G
 	if (is_10g_interface(interface))
 		return &gen10g_driver;
 #endif
 	return &genphy_driver;
 }
 struct phy_driver *get_phy_driver(struct phy_device *phydev,
 				phy_interface_t interface)
 {
 	struct list_head *entry;
 	int phy_id = phydev->phy_id;
 	struct phy_driver *drv = NULL;
 	list_for_each(entry, &phy_drivers) {
 		drv = list_entry(entry, struct phy_driver, list);
 		if ((drv->uid & drv->mask) == (phy_id & drv->mask))
 			return drv;
 	}
 	/* If we made it here, there's no driver for this PHY */
 	return generic_for_interface(interface);
 }
 struct phy_device *phy_device_create(struct mii_dev *bus, int addr, int phy_id,
 					phy_interface_t interface)
 {
 	struct phy_device *dev;
 	/* We allocate the device, and initialize the
 	 * default values */
 	dev = malloc(sizeof(*dev));
 	if (!dev) {
 		printf("Failed to allocate PHY device for %s:%d\n",
 			bus->name, addr);
 		return NULL;
 	}
 	memset(dev, 0, sizeof(*dev));
 	dev->duplex = -1;
 	dev->link = 1;
 	dev->interface = interface;
 	dev->autoneg = AUTONEG_ENABLE;
 	dev->addr = addr;
 	dev->phy_id = phy_id;
 	dev->bus = bus;
 	dev->drv = get_phy_driver(dev, interface);
 	phy_probe(dev);
 	bus->phymap[addr] = dev;
 	return dev;
 }
 /**
  * get_phy_id - reads the specified addr for its ID.
  * @bus: the target MII bus
  * @addr: PHY address on the MII bus
  * @phy_id: where to store the ID retrieved.
  *
  * Description: Reads the ID registers of the PHY at @addr on the
  *   @bus, stores it in @phy_id and returns zero on success.
  */
 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 {
 	int phy_reg;
 	/* Grab the bits from PHYIR1, and put them
 	 * in the upper half */
 	phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
 	if (phy_reg < 0)
 		return -EIO;
 	*phy_id = (phy_reg & 0xffff) << 16;
 	/* Grab the bits from PHYIR2, and put them in the lower half */
 	phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
 	if (phy_reg < 0)
 		return -EIO;
 	*phy_id |= (phy_reg & 0xffff);
 	return 0;
 }
 /**
  * get_phy_device - reads the specified PHY device and returns its @phy_device struct
  * @bus: the target MII bus
  * @addr: PHY address on the MII bus
  *
  * Description: Reads the ID registers of the PHY at @addr on the
  *   @bus, then allocates and returns the phy_device to represent it.
  */
 struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
 				phy_interface_t interface)
 {
 	u32 phy_id = 0x1fffffff;
 	int i;
 	int r;
 	/* If we have one, return the existing device, with new interface */
 	if (bus->phymap[addr]) {
 		bus->phymap[addr]->interface = interface;
 		return bus->phymap[addr];
 	}
 	/* Try Standard (ie Clause 22) access */
 	r = get_phy_id(bus, addr, MDIO_DEVAD_NONE, &phy_id);
 	if (r)
 		return NULL;
 	/* If the PHY ID is mostly f's, we didn't find anything */
 	if ((phy_id & 0x1fffffff) != 0x1fffffff)
 		return phy_device_create(bus, addr, phy_id, interface);
 	/* Otherwise we have to try Clause 45 */
 	for (i = 1; i < 5; i++) {
 		r = get_phy_id(bus, addr, i, &phy_id);
 		if (r)
 			return NULL;
 		/* If the phy_id is mostly Fs, there is no device there */
 		if ((phy_id & 0x1fffffff) != 0x1fffffff)
 			break;
 	}
 	return phy_device_create(bus, addr, phy_id, interface);
 }
 int phy_reset(struct phy_device *phydev)
 {
 	int reg;
 	int timeout = 500;
 	int devad = MDIO_DEVAD_NONE;
 #ifdef CONFIG_PHYLIB_10G
 	/* If it's 10G, we need to issue reset through one of the MMDs */
 	if (is_10g_interface(phydev->interface)) {
 		if (!phydev->mmds)
 			gen10g_discover_mmds(phydev);
 		devad = ffs(phydev->mmds) - 1;
 	}
 #endif
 	reg = phy_read(phydev, devad, MII_BMCR);
 	if (reg < 0) {
 		debug("PHY status read failed\n");
 		return -1;
 	}
 	reg |= BMCR_RESET;
 	if (phy_write(phydev, devad, MII_BMCR, reg) < 0) {
 		debug("PHY reset failed\n");
 		return -1;
 	}
 #ifdef CONFIG_PHY_RESET_DELAY
 	udelay(CONFIG_PHY_RESET_DELAY);	/* Intel LXT971A needs this */
 #endif
 	/*
 	 * Poll the control register for the reset bit to go to 0 (it is
 	 * auto-clearing).  This should happen within 0.5 seconds per the
 	 * IEEE spec.
 	 */
 	while ((reg & BMCR_RESET) && timeout--) {
 		reg = phy_read(phydev, devad, MII_BMCR);
 		if (reg < 0) {
 			debug("PHY status read failed\n");
 			return -1;
 		}
 		udelay(1000);
 	}
 	if (reg & BMCR_RESET) {
 		puts("PHY reset timed out\n");
 		return -1;
 	}
 	return 0;
 }
 int miiphy_reset(const char *devname, unsigned char addr)
 {
 	struct mii_dev *bus = miiphy_get_dev_by_name(devname);
 	struct phy_device *phydev;
 	/*
 	 * miiphy_reset was only used on standard PHYs, so we'll fake it here.
 	 * If later code tries to connect with the right interface, this will
 	 * be corrected by get_phy_device in phy_connect()
 	 */
 	phydev = get_phy_device(bus, addr, PHY_INTERFACE_MODE_MII);
 	return phy_reset(phydev);
 }
 struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 				struct eth_device *dev,
 				phy_interface_t interface)
 {
 	struct phy_device *phydev;
 	/* Reset the bus */
 	if (bus->reset)
 		bus->reset(bus);
 	/* Wait 15ms to make sure the PHY has come out of hard reset */
 	udelay(15000);
 	phydev = get_phy_device(bus, addr, interface);
 	if (!phydev) {
 		printf("Could not get PHY for %s:%d\n", bus->name, addr);
 		return NULL;
 	}
 	/* Soft Reset the PHY */
 	phy_reset(phydev);
 	if (phydev->dev)
 		printf("%s:%d is connected to %s.  Reconnecting to %s\n",
 			bus->name, addr, phydev->dev->name, dev->name);
 	phydev->dev = dev;
 	debug("%s connected to %s\n", dev->name, phydev->drv->name);
 	return phydev;
 }
 int phy_startup(struct phy_device *phydev)
 {
 	if (phydev->drv->startup)
 		phydev->drv->startup(phydev);
 	return 0;
 }
 static int __board_phy_config(struct phy_device *phydev)
 {
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
 	return 0;
 }
 int board_phy_config(struct phy_device *phydev)
 	__attribute__((weak, alias("__board_phy_config")));
 int phy_config(struct phy_device *phydev)
 {
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
 	/* Invoke an optional board-specific helper */
 	board_phy_config(phydev);
 	return 0;
 }
 int phy_shutdown(struct phy_device *phydev)
 {
 	if (phydev->drv->shutdown)
 		phydev->drv->shutdown(phydev);
 	return 0;