Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit a68256074f4239008c6d5c936bc0f8857f3d1b8a

Authored by Christophe Leroy
Committed by Tom Rini
1 parent 12fdbbe860
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

watchdog: mpc8xx: Revert the 8xx watchdog back to CONFIG_HW_WATCHDOG 

Commit f3729ba6e7b2 ("watchdog: mpc8xx_wdt: Watchdog driver and macros
cleanup") switched the watchdog to CONFIG_WATCHDOG. But this is not
compatible with the 8xx because it starts the watchdog HW timer at
reset and must be serviced from the very beginning including while
U-boot is executed in the firmware before relocation in RAM.

Select CONFIG_HW_WATCHDOG and make hw_watchdog_reset() visible.

Meanwhile, finalise the cleanup of arch/powerpc/cpu/mpc8xx/Kconfig by
removing the lines put in comment in that commit, and also remove
again the selection of CONFIG_MPC8xx_WATCHDOG which was removed by
that commit and brought back by mistake by commit b3134ffbd944
("watchdog: Kconfig: Sort entry alphabetically")

Note that there was an 'imply WATCHDOG' in the original commit but
it disappeared in the Kconfig alphabetical sorting, so no need to
remove it here.

Fixes: f3729ba6e7b2 ("watchdog: mpc8xx_wdt: Watchdog driver and macros cleanup")
Fixes: b3134ffbd944 ("watchdog: Kconfig: Sort entry alphabetically")
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Stefan Roese <sr@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Stefan Roese <sr@denx.de>

Showing 3 changed files with 2 additions and 6 deletions Inline Diff

arch/powerpc/cpu/mpc8xx/Kconfig
Diff comments   View file @ a682560
1 menu "mpc8xx CPU" 1 menu "mpc8xx CPU"
2 depends on MPC8xx 2 depends on MPC8xx
3 3
4 config SYS_CPU 4 config SYS_CPU
5 default "mpc8xx" 5 default "mpc8xx"
6 6
7 choice 7 choice
8 prompt "Target select" 8 prompt "Target select"
9 optional 9 optional
10 10
11 config TARGET_MCR3000 11 config TARGET_MCR3000
12 bool "Support MCR3000 board from CSSI" 12 bool "Support MCR3000 board from CSSI"
13 13
14 endchoice 14 endchoice
15 15
16 choice 16 choice
17 prompt "CPU select" 17 prompt "CPU select"
18 default MPC866 18 default MPC866
19 19
20 config MPC866 20 config MPC866
21 bool "MPC866" 21 bool "MPC866"
22 22
23 config MPC885 23 config MPC885
24 bool "MPC885" 24 bool "MPC885"
25 25
26 endchoice 26 endchoice
27 27
28 #config MPC8xx_WATCHDOG
29 # bool "Watchdog"
30 # select HW_WATCHDOG
31
32 config 8xx_GCLK_FREQ 28 config 8xx_GCLK_FREQ
33 int "CPU GCLK Frequency" 29 int "CPU GCLK Frequency"
34 30
35 comment "Specific commands" 31 comment "Specific commands"
36 32
37 config CMD_IMMAP 33 config CMD_IMMAP
38 bool "Enable various commands to dump IMMR information" 34 bool "Enable various commands to dump IMMR information"
39 help 35 help
40 This enables various commands such as: 36 This enables various commands such as:
41 37
42 siuinfo - print System Interface Unit (SIU) registers 38 siuinfo - print System Interface Unit (SIU) registers
43 memcinfo - print Memory Controller registers 39 memcinfo - print Memory Controller registers
44 40
45 comment "Configuration Registers" 41 comment "Configuration Registers"
46 42
47 config SYS_SIUMCR 43 config SYS_SIUMCR
48 hex "SIUMCR register" 44 hex "SIUMCR register"
49 help 45 help
50 SIU Module Configuration (11-6) 46 SIU Module Configuration (11-6)
51 47
52 config SYS_SYPCR 48 config SYS_SYPCR
53 hex "SYPCR register" 49 hex "SYPCR register"
54 help 50 help
55 System Protection Control (11-9) 51 System Protection Control (11-9)
56 52
57 config SYS_TBSCR 53 config SYS_TBSCR
58 hex "TBSCR register" 54 hex "TBSCR register"
59 help 55 help
60 Time Base Status and Control (11-26) 56 Time Base Status and Control (11-26)
61 57
62 config SYS_PISCR 58 config SYS_PISCR
63 hex "PISCR register" 59 hex "PISCR register"
64 help 60 help
65 Periodic Interrupt Status and Control (11-31) 61 Periodic Interrupt Status and Control (11-31)
66 62
67 config SYS_PLPRCR_BOOL 63 config SYS_PLPRCR_BOOL
68 bool "Customise PLPRCR" 64 bool "Customise PLPRCR"
69 65
70 config SYS_PLPRCR 66 config SYS_PLPRCR
71 hex "PLPRCR register" 67 hex "PLPRCR register"
72 depends on SYS_PLPRCR_BOOL 68 depends on SYS_PLPRCR_BOOL
73 help 69 help
74 PLL, Low-Power, and Reset Control Register (15-30) 70 PLL, Low-Power, and Reset Control Register (15-30)
75 71
76 config SYS_SCCR 72 config SYS_SCCR
77 hex "SCCR register" 73 hex "SCCR register"
78 help 74 help
79 System Clock and reset Control Register (15-27) 75 System Clock and reset Control Register (15-27)
80 76
81 config SYS_SCCR_MASK 77 config SYS_SCCR_MASK
82 hex "MASK for setting SCCR register" 78 hex "MASK for setting SCCR register"
83 79
84 config SYS_DER 80 config SYS_DER
85 hex "DER register" 81 hex "DER register"
86 help 82 help
87 Debug Event Register (37-47) 83 Debug Event Register (37-47)
88 84
89 comment "Memory mapping" 85 comment "Memory mapping"
90 86
91 config SYS_BR0_PRELIM 87 config SYS_BR0_PRELIM
92 hex "Preliminary value for BR0" 88 hex "Preliminary value for BR0"
93 89
94 config SYS_OR0_PRELIM 90 config SYS_OR0_PRELIM
95 hex "Preliminary value for OR0" 91 hex "Preliminary value for OR0"
96 92
97 config SYS_BR1_PRELIM_BOOL 93 config SYS_BR1_PRELIM_BOOL
98 bool "Define Bank 1" 94 bool "Define Bank 1"
99 95
100 config SYS_BR1_PRELIM 96 config SYS_BR1_PRELIM
101 hex "Preliminary value for BR1" 97 hex "Preliminary value for BR1"
102 depends on SYS_BR1_PRELIM_BOOL 98 depends on SYS_BR1_PRELIM_BOOL
103 99
104 config SYS_OR1_PRELIM 100 config SYS_OR1_PRELIM
105 hex "Preliminary value for OR1" 101 hex "Preliminary value for OR1"
106 depends on SYS_BR1_PRELIM_BOOL 102 depends on SYS_BR1_PRELIM_BOOL
107 103
108 config SYS_BR2_PRELIM_BOOL 104 config SYS_BR2_PRELIM_BOOL
109 bool "Define Bank 2" 105 bool "Define Bank 2"
110 106
111 config SYS_BR2_PRELIM 107 config SYS_BR2_PRELIM
112 hex "Preliminary value for BR2" 108 hex "Preliminary value for BR2"
113 depends on SYS_BR2_PRELIM_BOOL 109 depends on SYS_BR2_PRELIM_BOOL
114 110
115 config SYS_OR2_PRELIM 111 config SYS_OR2_PRELIM
116 hex "Preliminary value for OR2" 112 hex "Preliminary value for OR2"
117 depends on SYS_BR2_PRELIM_BOOL 113 depends on SYS_BR2_PRELIM_BOOL
118 114
119 config SYS_BR3_PRELIM_BOOL 115 config SYS_BR3_PRELIM_BOOL
120 bool "Define Bank 3" 116 bool "Define Bank 3"
121 117
122 config SYS_BR3_PRELIM 118 config SYS_BR3_PRELIM
123 hex "Preliminary value for BR3" 119 hex "Preliminary value for BR3"
124 depends on SYS_BR3_PRELIM_BOOL 120 depends on SYS_BR3_PRELIM_BOOL
125 121
126 config SYS_OR3_PRELIM 122 config SYS_OR3_PRELIM
127 hex "Preliminary value for OR3" 123 hex "Preliminary value for OR3"
128 depends on SYS_BR3_PRELIM_BOOL 124 depends on SYS_BR3_PRELIM_BOOL
129 125
130 config SYS_BR4_PRELIM_BOOL 126 config SYS_BR4_PRELIM_BOOL
131 bool "Define Bank 4" 127 bool "Define Bank 4"
132 128
133 config SYS_BR4_PRELIM 129 config SYS_BR4_PRELIM
134 hex "Preliminary value for BR4" 130 hex "Preliminary value for BR4"
135 depends on SYS_BR4_PRELIM_BOOL 131 depends on SYS_BR4_PRELIM_BOOL
136 132
137 config SYS_OR4_PRELIM 133 config SYS_OR4_PRELIM
138 hex "Preliminary value for OR4" 134 hex "Preliminary value for OR4"
139 depends on SYS_BR4_PRELIM_BOOL 135 depends on SYS_BR4_PRELIM_BOOL
140 136
141 config SYS_BR5_PRELIM_BOOL 137 config SYS_BR5_PRELIM_BOOL
142 bool "Define Bank 5" 138 bool "Define Bank 5"
143 139
144 config SYS_BR5_PRELIM 140 config SYS_BR5_PRELIM
145 hex "Preliminary value for BR5" 141 hex "Preliminary value for BR5"
146 depends on SYS_BR5_PRELIM_BOOL 142 depends on SYS_BR5_PRELIM_BOOL
147 143
148 config SYS_OR5_PRELIM 144 config SYS_OR5_PRELIM
149 hex "Preliminary value for OR5" 145 hex "Preliminary value for OR5"
150 depends on SYS_BR5_PRELIM_BOOL 146 depends on SYS_BR5_PRELIM_BOOL
151 147
152 config SYS_BR6_PRELIM_BOOL 148 config SYS_BR6_PRELIM_BOOL
153 bool "Define Bank 6" 149 bool "Define Bank 6"
154 150
155 config SYS_BR6_PRELIM 151 config SYS_BR6_PRELIM
156 hex "Preliminary value for BR6" 152 hex "Preliminary value for BR6"
157 depends on SYS_BR6_PRELIM_BOOL 153 depends on SYS_BR6_PRELIM_BOOL
158 154
159 config SYS_OR6_PRELIM 155 config SYS_OR6_PRELIM
160 hex "Preliminary value for OR6" 156 hex "Preliminary value for OR6"
161 depends on SYS_BR6_PRELIM_BOOL 157 depends on SYS_BR6_PRELIM_BOOL
162 158
163 config SYS_BR7_PRELIM_BOOL 159 config SYS_BR7_PRELIM_BOOL
164 bool "Define Bank 7" 160 bool "Define Bank 7"
165 161
166 config SYS_BR7_PRELIM 162 config SYS_BR7_PRELIM
167 hex "Preliminary value for BR7" 163 hex "Preliminary value for BR7"
168 depends on SYS_BR7_PRELIM_BOOL 164 depends on SYS_BR7_PRELIM_BOOL
169 165
170 config SYS_OR7_PRELIM 166 config SYS_OR7_PRELIM
171 hex "Preliminary value for OR7" 167 hex "Preliminary value for OR7"
172 depends on SYS_BR7_PRELIM_BOOL 168 depends on SYS_BR7_PRELIM_BOOL
173 169
174 config SYS_IMMR 170 config SYS_IMMR
175 hex "Value for IMMR" 171 hex "Value for IMMR"
176 172
177 source "board/cssi/MCR3000/Kconfig" 173 source "board/cssi/MCR3000/Kconfig"
178 174
179 endmenu 175 endmenu
180 176
drivers/watchdog/Kconfig
Diff comments   View file @ a682560
1 menu "Watchdog Timer Support" 1 menu "Watchdog Timer Support"
2 2
3 config WATCHDOG 3 config WATCHDOG
4 bool "Enable U-Boot watchdog reset" 4 bool "Enable U-Boot watchdog reset"
5 help 5 help
6 This option enables U-Boot watchdog support where U-Boot is using 6 This option enables U-Boot watchdog support where U-Boot is using
7 watchdog_reset function to service watchdog device in U-Boot. Enable 7 watchdog_reset function to service watchdog device in U-Boot. Enable
8 this option if you want to service enabled watchdog by U-Boot. Disable 8 this option if you want to service enabled watchdog by U-Boot. Disable
9 this option if you want U-Boot to start watchdog but never service it. 9 this option if you want U-Boot to start watchdog but never service it.
10 10
11 config WATCHDOG_TIMEOUT_MSECS 11 config WATCHDOG_TIMEOUT_MSECS
12 int "Watchdog timeout in msec" 12 int "Watchdog timeout in msec"
13 default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6 13 default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6
14 default 128000 if ARCH_MX7 || ARCH_VF610 14 default 128000 if ARCH_MX7 || ARCH_VF610
15 default 30000 if ARCH_SOCFPGA 15 default 30000 if ARCH_SOCFPGA
16 default 60000 16 default 60000
17 help 17 help
18 Watchdog timeout in msec 18 Watchdog timeout in msec
19 19
20 config HW_WATCHDOG 20 config HW_WATCHDOG
21 bool 21 bool
22 22
23 config WATCHDOG_RESET_DISABLE 23 config WATCHDOG_RESET_DISABLE
24 bool "Disable reset watchdog" 24 bool "Disable reset watchdog"
25 help 25 help
26 Disable reset watchdog, which can let WATCHDOG_RESET invalid, so 26 Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
27 that the watchdog will not be fed in u-boot. 27 that the watchdog will not be fed in u-boot.
28 28
29 config IMX_WATCHDOG 29 config IMX_WATCHDOG
30 bool "Enable Watchdog Timer support for IMX and LSCH2 of NXP" 30 bool "Enable Watchdog Timer support for IMX and LSCH2 of NXP"
31 select HW_WATCHDOG if !WDT 31 select HW_WATCHDOG if !WDT
32 help 32 help
33 Select this to enable the IMX and LSCH2 of Layerscape watchdog 33 Select this to enable the IMX and LSCH2 of Layerscape watchdog
34 driver. 34 driver.
35 35
36 config OMAP_WATCHDOG 36 config OMAP_WATCHDOG
37 bool "TI OMAP watchdog driver" 37 bool "TI OMAP watchdog driver"
38 depends on ARCH_OMAP2PLUS 38 depends on ARCH_OMAP2PLUS
39 select HW_WATCHDOG 39 select HW_WATCHDOG
40 help 40 help
41 Say Y here to enable the OMAP3+ watchdog driver. 41 Say Y here to enable the OMAP3+ watchdog driver.
42 42
43 config ULP_WATCHDOG 43 config ULP_WATCHDOG
44 bool "i.MX7ULP watchdog" 44 bool "i.MX7ULP watchdog"
45 help 45 help
46 Say Y here to enable i.MX7ULP watchdog driver. 46 Say Y here to enable i.MX7ULP watchdog driver.
47 47
48 config DESIGNWARE_WATCHDOG 48 config DESIGNWARE_WATCHDOG
49 bool "Designware watchdog timer support" 49 bool "Designware watchdog timer support"
50 select HW_WATCHDOG if !WDT 50 select HW_WATCHDOG if !WDT
51 help 51 help
52 Enable this to support Designware Watchdog Timer IP, present e.g. 52 Enable this to support Designware Watchdog Timer IP, present e.g.
53 on Altera SoCFPGA SoCs. 53 on Altera SoCFPGA SoCs.
54 54
55 config WDT 55 config WDT
56 bool "Enable driver model for watchdog timer drivers" 56 bool "Enable driver model for watchdog timer drivers"
57 depends on DM 57 depends on DM
58 imply WATCHDOG 58 imply WATCHDOG
59 help 59 help
60 Enable driver model for watchdog timer. At the moment the API 60 Enable driver model for watchdog timer. At the moment the API
61 is very simple and only supports four operations: 61 is very simple and only supports four operations:
62 start, stop, reset and expire_now (expire immediately). 62 start, stop, reset and expire_now (expire immediately).
63 What exactly happens when the timer expires is up to a particular 63 What exactly happens when the timer expires is up to a particular
64 device/driver. 64 device/driver.
65 65
66 config WDT_ARMADA_37XX 66 config WDT_ARMADA_37XX
67 bool "Marvell Armada 37xx watchdog timer support" 67 bool "Marvell Armada 37xx watchdog timer support"
68 depends on WDT && ARMADA_3700 68 depends on WDT && ARMADA_3700
69 help 69 help
70 Enable this to support Watchdog Timer on Marvell Armada 37xx SoC. 70 Enable this to support Watchdog Timer on Marvell Armada 37xx SoC.
71 There are 4 possible clocks which can be used on these SoCs. This 71 There are 4 possible clocks which can be used on these SoCs. This
72 driver uses the second clock (ID 1), assuming that so will also 72 driver uses the second clock (ID 1), assuming that so will also
73 Linux's driver. 73 Linux's driver.
74 74
75 config WDT_ASPEED 75 config WDT_ASPEED
76 bool "Aspeed ast2400/ast2500 watchdog timer support" 76 bool "Aspeed ast2400/ast2500 watchdog timer support"
77 depends on WDT 77 depends on WDT
78 default y if ARCH_ASPEED 78 default y if ARCH_ASPEED
79 help 79 help
80 Select this to enable watchdog timer for Aspeed ast2500/ast2400 devices. 80 Select this to enable watchdog timer for Aspeed ast2500/ast2400 devices.
81 The watchdog timer is stopped when initialized. It performs reset, either 81 The watchdog timer is stopped when initialized. It performs reset, either
82 full SoC reset or CPU or just some peripherals, based on the flags. 82 full SoC reset or CPU or just some peripherals, based on the flags.
83 It currently does not support Boot Flash Addressing Mode Detection or 83 It currently does not support Boot Flash Addressing Mode Detection or
84 Second Boot. 84 Second Boot.
85 85
86 config WDT_AT91 86 config WDT_AT91
87 bool "AT91 watchdog timer support" 87 bool "AT91 watchdog timer support"
88 depends on WDT 88 depends on WDT
89 help 89 help
90 Select this to enable Microchip watchdog timer, which can be found on 90 Select this to enable Microchip watchdog timer, which can be found on
91 some AT91 devices. 91 some AT91 devices.
92 92
93 config WDT_BCM6345 93 config WDT_BCM6345
94 bool "BCM6345 watchdog timer support" 94 bool "BCM6345 watchdog timer support"
95 depends on WDT && (ARCH_BMIPS || ARCH_BCM68360 || \ 95 depends on WDT && (ARCH_BMIPS || ARCH_BCM68360 || \
96 ARCH_BCM6858 || ARCH_BCM63158) 96 ARCH_BCM6858 || ARCH_BCM63158)
97 help 97 help
98 Select this to enable watchdog timer for BCM6345 SoCs. 98 Select this to enable watchdog timer for BCM6345 SoCs.
99 The watchdog timer is stopped when initialized. 99 The watchdog timer is stopped when initialized.
100 It performs full SoC reset. 100 It performs full SoC reset.
101 101
102 config WDT_CDNS 102 config WDT_CDNS
103 bool "Cadence watchdog timer support" 103 bool "Cadence watchdog timer support"
104 depends on WDT 104 depends on WDT
105 imply WATCHDOG 105 imply WATCHDOG
106 help 106 help
107 Select this to enable Cadence watchdog timer, which can be found on some 107 Select this to enable Cadence watchdog timer, which can be found on some
108 Xilinx Microzed Platform. 108 Xilinx Microzed Platform.
109 109
110 config WDT_CORTINA 110 config WDT_CORTINA
111 bool "Cortina Access CAxxxx watchdog timer support" 111 bool "Cortina Access CAxxxx watchdog timer support"
112 depends on WDT 112 depends on WDT
113 help 113 help
114 Cortina Access CAxxxx watchdog timer support. 114 Cortina Access CAxxxx watchdog timer support.
115 This driver support all CPU ISAs supported by Cortina 115 This driver support all CPU ISAs supported by Cortina
116 Access CAxxxx SoCs. 116 Access CAxxxx SoCs.
117 117
118 config WDT_MPC8xx 118 config WDT_MPC8xx
119 bool "MPC8xx watchdog timer support" 119 bool "MPC8xx watchdog timer support"
120 depends on WDT && MPC8xx 120 depends on WDT && MPC8xx
121 select CONFIG_MPC8xx_WATCHDOG 121 select HW_WATCHDOG
122 help 122 help
123 Select this to enable mpc8xx watchdog timer 123 Select this to enable mpc8xx watchdog timer
124 124
125 config WDT_MT7621 125 config WDT_MT7621
126 bool "MediaTek MT7621 watchdog timer support" 126 bool "MediaTek MT7621 watchdog timer support"
127 depends on WDT && SOC_MT7628 127 depends on WDT && SOC_MT7628
128 help 128 help
129 Select this to enable Ralink / Mediatek watchdog timer, 129 Select this to enable Ralink / Mediatek watchdog timer,
130 which can be found on some MediaTek chips. 130 which can be found on some MediaTek chips.
131 131
132 config WDT_MTK 132 config WDT_MTK
133 bool "MediaTek watchdog timer support" 133 bool "MediaTek watchdog timer support"
134 depends on WDT && ARCH_MEDIATEK 134 depends on WDT && ARCH_MEDIATEK
135 help 135 help
136 Select this to enable watchdog timer for MediaTek SoCs. 136 Select this to enable watchdog timer for MediaTek SoCs.
137 The watchdog timer is stopped when initialized. 137 The watchdog timer is stopped when initialized.
138 It performs full SoC reset. 138 It performs full SoC reset.
139 139
140 config WDT_OMAP3 140 config WDT_OMAP3
141 bool "TI OMAP watchdog timer support" 141 bool "TI OMAP watchdog timer support"
142 depends on WDT && ARCH_OMAP2PLUS 142 depends on WDT && ARCH_OMAP2PLUS
143 default y if AM33XX 143 default y if AM33XX
144 help 144 help
145 This enables OMAP3+ watchdog timer driver, which can be 145 This enables OMAP3+ watchdog timer driver, which can be
146 found on some TI chipsets and inline with driver model. 146 found on some TI chipsets and inline with driver model.
147 147
148 config WDT_ORION 148 config WDT_ORION
149 bool "Orion watchdog timer support" 149 bool "Orion watchdog timer support"
150 depends on WDT 150 depends on WDT
151 select CLK 151 select CLK
152 help 152 help
153 Select this to enable Orion watchdog timer, which can be found on some 153 Select this to enable Orion watchdog timer, which can be found on some
154 Marvell Armada chips. 154 Marvell Armada chips.
155 155
156 config WDT_SANDBOX 156 config WDT_SANDBOX
157 bool "Enable Watchdog Timer support for Sandbox" 157 bool "Enable Watchdog Timer support for Sandbox"
158 depends on SANDBOX && WDT 158 depends on SANDBOX && WDT
159 help 159 help
160 Enable Watchdog Timer support in Sandbox. This is a dummy device that 160 Enable Watchdog Timer support in Sandbox. This is a dummy device that
161 can be probed and supports all of the methods of WDT, but does not 161 can be probed and supports all of the methods of WDT, but does not
162 really do anything. 162 really do anything.
163 163
164 config WDT_SP805 164 config WDT_SP805
165 bool "SP805 watchdog timer support" 165 bool "SP805 watchdog timer support"
166 depends on WDT 166 depends on WDT
167 help 167 help
168 Select this to enable SP805 watchdog timer, which can be found on some 168 Select this to enable SP805 watchdog timer, which can be found on some
169 nxp layerscape chips. 169 nxp layerscape chips.
170 170
171 config WDT_STM32MP 171 config WDT_STM32MP
172 bool "IWDG watchdog driver for STM32 MP's family" 172 bool "IWDG watchdog driver for STM32 MP's family"
173 depends on WDT 173 depends on WDT
174 imply WATCHDOG 174 imply WATCHDOG
175 help 175 help
176 Enable the STM32 watchdog (IWDG) driver. Enable support to 176 Enable the STM32 watchdog (IWDG) driver. Enable support to
177 configure STM32's on-SoC watchdog. 177 configure STM32's on-SoC watchdog.
178 178
179 config XILINX_TB_WATCHDOG 179 config XILINX_TB_WATCHDOG
180 bool "Xilinx Axi watchdog timer support" 180 bool "Xilinx Axi watchdog timer support"
181 depends on WDT 181 depends on WDT
182 imply WATCHDOG 182 imply WATCHDOG
183 help 183 help
184 Select this to enable Xilinx Axi watchdog timer, which can be found on some 184 Select this to enable Xilinx Axi watchdog timer, which can be found on some
185 Xilinx Microblaze Platforms. 185 Xilinx Microblaze Platforms.
186 186
187 config WDT_TANGIER 187 config WDT_TANGIER
188 bool "Intel Tangier watchdog timer support" 188 bool "Intel Tangier watchdog timer support"
189 depends on WDT && INTEL_MID 189 depends on WDT && INTEL_MID
190 help 190 help
191 This enables support for watchdog controller available on 191 This enables support for watchdog controller available on
192 Intel Tangier SoC. If you're using a board with Intel Tangier 192 Intel Tangier SoC. If you're using a board with Intel Tangier
193 SoC, say Y here. 193 SoC, say Y here.
194 194
195 config SPL_WDT 195 config SPL_WDT
196 bool "Enable driver model for watchdog timer drivers in SPL" 196 bool "Enable driver model for watchdog timer drivers in SPL"
197 depends on SPL_DM 197 depends on SPL_DM
198 help 198 help
199 Enable driver model for watchdog timer in SPL. 199 Enable driver model for watchdog timer in SPL.
200 This is similar to CONFIG_WDT in U-Boot. 200 This is similar to CONFIG_WDT in U-Boot.
201 201
202 endmenu 202 endmenu
203 203
drivers/watchdog/mpc8xx_wdt.c
Diff comments   View file @ a682560
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017 CS Systemes d'Information 3 * Copyright 2017 CS Systemes d'Information
4 */ 4 */
5 5
6 #include <common.h> 6 #include <common.h>
7 #include <dm.h> 7 #include <dm.h>
8 #include <wdt.h> 8 #include <wdt.h>
9 #include <mpc8xx.h> 9 #include <mpc8xx.h>
10 #include <asm/cpm_8xx.h> 10 #include <asm/cpm_8xx.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 12
13 static void hw_watchdog_reset(void) 13 void hw_watchdog_reset(void)
14 { 14 {
15 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 15 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
16 16
17 out_be16(&immap->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */ 17 out_be16(&immap->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */
18 out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */ 18 out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
19 } 19 }
20 20
21 static int mpc8xx_wdt_start(struct udevice *dev, u64 timeout, ulong flags) 21 static int mpc8xx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
22 { 22 {
23 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 23 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
24 24
25 out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR); 25 out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
26 26
27 if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)) 27 if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE))
28 return -EBUSY; 28 return -EBUSY;
29 return 0; 29 return 0;
30 30
31 } 31 }
32 32
33 static int mpc8xx_wdt_stop(struct udevice *dev) 33 static int mpc8xx_wdt_stop(struct udevice *dev)
34 { 34 {
35 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 35 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
36 36
37 out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); 37 out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
38 38
39 if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE) 39 if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)
40 return -EBUSY; 40 return -EBUSY;
41 return 0; 41 return 0;
42 } 42 }
43 43
44 static int mpc8xx_wdt_reset(struct udevice *dev) 44 static int mpc8xx_wdt_reset(struct udevice *dev)
45 { 45 {
46 hw_watchdog_reset(); 46 hw_watchdog_reset();
47 47
48 return 0; 48 return 0;
49 } 49 }
50 50
51 static const struct wdt_ops mpc8xx_wdt_ops = { 51 static const struct wdt_ops mpc8xx_wdt_ops = {
52 .start = mpc8xx_wdt_start, 52 .start = mpc8xx_wdt_start,
53 .reset = mpc8xx_wdt_reset, 53 .reset = mpc8xx_wdt_reset,
54 .stop = mpc8xx_wdt_stop, 54 .stop = mpc8xx_wdt_stop,
55 }; 55 };
56 56
57 static const struct udevice_id mpc8xx_wdt_ids[] = { 57 static const struct udevice_id mpc8xx_wdt_ids[] = {
58 { .compatible = "fsl,pq1-wdt" }, 58 { .compatible = "fsl,pq1-wdt" },
59 {} 59 {}
60 }; 60 };
61 61
62 U_BOOT_DRIVER(wdt_mpc8xx) = { 62 U_BOOT_DRIVER(wdt_mpc8xx) = {
63 .name = "wdt_mpc8xx", 63 .name = "wdt_mpc8xx",
64 .id = UCLASS_WDT, 64 .id = UCLASS_WDT,
65 .of_match = mpc8xx_wdt_ids, 65 .of_match = mpc8xx_wdt_ids,
66 .ops = &mpc8xx_wdt_ops, 66 .ops = &mpc8xx_wdt_ops,
67 }; 67 };
68 68