Eric Lee / smarc-uboot

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Commit a950edcdb7a52362287783386dc5f6404d1a9dd8

Authored by Clark Wang
Committed by Ye Li
1 parent f927599650
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-24941 arm: dts: set sensor regulator always on for imx6q/qp/dl 

This is a workaround.
Always open the regulator of the sensor to ensure that the
pull-up of i2c3 is 3.3v. Otherwise, there will be a 1.8v high level
pull-up before enable sensor regulator in kernel boot stage.

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
(cherry picked from commit 6db6c8bf1a60baad7032f92822a0030b077d3602)

Showing 1 changed file with 1 additions and 0 deletions Inline Diff

arch/arm/dts/imx6qdl-sabresd.dtsi
Diff comments   View file @ a950edc
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 // 2 //
3 // Copyright 2012 Freescale Semiconductor, Inc. 3 // Copyright 2012 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd. 4 // Copyright 2011 Linaro Ltd.
5 // Copyright 2017 NXP. 5 // Copyright 2017 NXP.
6 6
7 #include <dt-bindings/clock/imx6qdl-clock.h> 7 #include <dt-bindings/clock/imx6qdl-clock.h>
8 8
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
11 11
12 / { 12 / {
13 aliases { 13 aliases {
14 mxcfb0 = &mxcfb1; 14 mxcfb0 = &mxcfb1;
15 mxcfb1 = &mxcfb2; 15 mxcfb1 = &mxcfb2;
16 mxcfb2 = &mxcfb3; 16 mxcfb2 = &mxcfb3;
17 mxcfb3 = &mxcfb4; 17 mxcfb3 = &mxcfb4;
18 }; 18 };
19 19
20 battery: max8903@0 { 20 battery: max8903@0 {
21 compatible = "fsl,max8903-charger"; 21 compatible = "fsl,max8903-charger";
22 pinctrl-names = "default"; 22 pinctrl-names = "default";
23 dok_input = <&gpio2 24 1>; 23 dok_input = <&gpio2 24 1>;
24 uok_input = <&gpio1 27 1>; 24 uok_input = <&gpio1 27 1>;
25 chg_input = <&gpio3 23 1>; 25 chg_input = <&gpio3 23 1>;
26 flt_input = <&gpio5 2 1>; 26 flt_input = <&gpio5 2 1>;
27 fsl,dcm_always_high; 27 fsl,dcm_always_high;
28 fsl,dc_valid; 28 fsl,dc_valid;
29 fsl,usb_valid; 29 fsl,usb_valid;
30 status = "okay"; 30 status = "okay";
31 }; 31 };
32 32
33 hannstar_cabc { 33 hannstar_cabc {
34 compatible = "hannstar,cabc"; 34 compatible = "hannstar,cabc";
35 lvds0 { 35 lvds0 {
36 gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; 36 gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
37 }; 37 };
38 lvds1 { 38 lvds1 {
39 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; 39 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
40 }; 40 };
41 }; 41 };
42 42
43 chosen { 43 chosen {
44 stdout-path = &uart1; 44 stdout-path = &uart1;
45 }; 45 };
46 46
47 memory: memory { 47 memory: memory {
48 reg = <0x10000000 0x40000000>; 48 reg = <0x10000000 0x40000000>;
49 }; 49 };
50 50
51 regulators { 51 regulators {
52 compatible = "simple-bus"; 52 compatible = "simple-bus";
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <0>; 54 #size-cells = <0>;
55 55
56 reg_usb_otg_vbus: regulator@0 { 56 reg_usb_otg_vbus: regulator@0 {
57 compatible = "regulator-fixed"; 57 compatible = "regulator-fixed";
58 reg = <0>; 58 reg = <0>;
59 regulator-name = "usb_otg_vbus"; 59 regulator-name = "usb_otg_vbus";
60 regulator-min-microvolt = <5000000>; 60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>; 61 regulator-max-microvolt = <5000000>;
62 gpio = <&gpio3 22 0>; 62 gpio = <&gpio3 22 0>;
63 enable-active-high; 63 enable-active-high;
64 vin-supply = <&swbst_reg>; 64 vin-supply = <&swbst_reg>;
65 }; 65 };
66 66
67 reg_usb_h1_vbus: regulator@1 { 67 reg_usb_h1_vbus: regulator@1 {
68 compatible = "regulator-fixed"; 68 compatible = "regulator-fixed";
69 reg = <1>; 69 reg = <1>;
70 regulator-name = "usb_h1_vbus"; 70 regulator-name = "usb_h1_vbus";
71 regulator-min-microvolt = <5000000>; 71 regulator-min-microvolt = <5000000>;
72 regulator-max-microvolt = <5000000>; 72 regulator-max-microvolt = <5000000>;
73 gpio = <&gpio1 29 0>; 73 gpio = <&gpio1 29 0>;
74 enable-active-high; 74 enable-active-high;
75 vin-supply = <&swbst_reg>; 75 vin-supply = <&swbst_reg>;
76 }; 76 };
77 77
78 reg_audio: regulator@2 { 78 reg_audio: regulator@2 {
79 compatible = "regulator-fixed"; 79 compatible = "regulator-fixed";
80 reg = <2>; 80 reg = <2>;
81 regulator-name = "wm8962-supply"; 81 regulator-name = "wm8962-supply";
82 gpio = <&gpio4 10 0>; 82 gpio = <&gpio4 10 0>;
83 enable-active-high; 83 enable-active-high;
84 }; 84 };
85 85
86 reg_pcie: regulator@3 { 86 reg_pcie: regulator@3 {
87 compatible = "regulator-fixed"; 87 compatible = "regulator-fixed";
88 reg = <3>; 88 reg = <3>;
89 pinctrl-names = "default"; 89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_pcie_reg>; 90 pinctrl-0 = <&pinctrl_pcie_reg>;
91 regulator-name = "MPCIE_3V3"; 91 regulator-name = "MPCIE_3V3";
92 regulator-min-microvolt = <3300000>; 92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>; 93 regulator-max-microvolt = <3300000>;
94 gpio = <&gpio3 19 0>; 94 gpio = <&gpio3 19 0>;
95 regulator-always-on; 95 regulator-always-on;
96 enable-active-high; 96 enable-active-high;
97 }; 97 };
98 98
99 reg_sensor: regulator@4 { 99 reg_sensor: regulator@4 {
100 compatible = "regulator-fixed"; 100 compatible = "regulator-fixed";
101 reg = <4>; 101 reg = <4>;
102 regulator-name = "sensor-supply"; 102 regulator-name = "sensor-supply";
103 regulator-min-microvolt = <3300000>; 103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>; 104 regulator-max-microvolt = <3300000>;
105 gpio = <&gpio2 31 0>; 105 gpio = <&gpio2 31 0>;
106 startup-delay-us = <500>; 106 startup-delay-us = <500>;
107 regulator-always-on;
107 enable-active-high; 108 enable-active-high;
108 }; 109 };
109 110
110 reg_hdmi: regulator@5 { 111 reg_hdmi: regulator@5 {
111 compatible = "regulator-fixed"; 112 compatible = "regulator-fixed";
112 reg = <5>; 113 reg = <5>;
113 regulator-name = "hdmi-5v-supply"; 114 regulator-name = "hdmi-5v-supply";
114 regulator-min-microvolt = <5000000>; 115 regulator-min-microvolt = <5000000>;
115 regulator-max-microvolt = <5000000>; 116 regulator-max-microvolt = <5000000>;
116 enable-active-high; 117 enable-active-high;
117 hdmi-5v-supply = <&swbst_reg>; 118 hdmi-5v-supply = <&swbst_reg>;
118 }; 119 };
119 120
120 reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { 121 reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
121 compatible = "regulator-fixed"; 122 compatible = "regulator-fixed";
122 regulator-name = "mipi_dsi_pwr_on"; 123 regulator-name = "mipi_dsi_pwr_on";
123 gpio = <&gpio6 14 0>; 124 gpio = <&gpio6 14 0>;
124 enable-active-high; 125 enable-active-high;
125 }; 126 };
126 }; 127 };
127 128
128 gpio-keys { 129 gpio-keys {
129 compatible = "gpio-keys"; 130 compatible = "gpio-keys";
130 pinctrl-names = "default"; 131 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_gpio_keys>; 132 pinctrl-0 = <&pinctrl_gpio_keys>;
132 133
133 power { 134 power {
134 label = "Power Button"; 135 label = "Power Button";
135 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; 136 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
136 wakeup-source; 137 wakeup-source;
137 linux,code = <KEY_POWER>; 138 linux,code = <KEY_POWER>;
138 }; 139 };
139 140
140 volume-up { 141 volume-up {
141 label = "Volume Up"; 142 label = "Volume Up";
142 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 143 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
143 wakeup-source; 144 wakeup-source;
144 linux,code = <KEY_VOLUMEUP>; 145 linux,code = <KEY_VOLUMEUP>;
145 }; 146 };
146 147
147 volume-down { 148 volume-down {
148 label = "Volume Down"; 149 label = "Volume Down";
149 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 150 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
150 wakeup-source; 151 wakeup-source;
151 linux,code = <KEY_VOLUMEDOWN>; 152 linux,code = <KEY_VOLUMEDOWN>;
152 }; 153 };
153 }; 154 };
154 155
155 sound { 156 sound {
156 compatible = "fsl,imx6q-sabresd-wm8962", 157 compatible = "fsl,imx6q-sabresd-wm8962",
157 "fsl,imx-audio-wm8962"; 158 "fsl,imx-audio-wm8962";
158 model = "wm8962-audio"; 159 model = "wm8962-audio";
159 cpu-dai = <&ssi2>; 160 cpu-dai = <&ssi2>;
160 audio-codec = <&codec>; 161 audio-codec = <&codec>;
161 asrc-controller = <&asrc>; 162 asrc-controller = <&asrc>;
162 audio-routing = 163 audio-routing =
163 "Headphone Jack", "HPOUTL", 164 "Headphone Jack", "HPOUTL",
164 "Headphone Jack", "HPOUTR", 165 "Headphone Jack", "HPOUTR",
165 "Ext Spk", "SPKOUTL", 166 "Ext Spk", "SPKOUTL",
166 "Ext Spk", "SPKOUTR", 167 "Ext Spk", "SPKOUTR",
167 "AMIC", "MICBIAS", 168 "AMIC", "MICBIAS",
168 "IN3R", "AMIC", 169 "IN3R", "AMIC",
169 "DMIC", "MICBIAS", 170 "DMIC", "MICBIAS",
170 "DMICDAT", "DMIC", 171 "DMICDAT", "DMIC",
171 "CPU-Playback", "ASRC-Playback", 172 "CPU-Playback", "ASRC-Playback",
172 "Playback", "CPU-Playback", 173 "Playback", "CPU-Playback",
173 "ASRC-Capture", "CPU-Capture", 174 "ASRC-Capture", "CPU-Capture",
174 "CPU-Capture", "Capture"; 175 "CPU-Capture", "Capture";
175 mux-int-port = <2>; 176 mux-int-port = <2>;
176 mux-ext-port = <3>; 177 mux-ext-port = <3>;
177 codec-master; 178 codec-master;
178 hp-det-gpios = <&gpio7 8 1>; 179 hp-det-gpios = <&gpio7 8 1>;
179 mic-det-gpios = <&gpio1 9 1>; 180 mic-det-gpios = <&gpio1 9 1>;
180 }; 181 };
181 182
182 sound-hdmi { 183 sound-hdmi {
183 compatible = "fsl,imx6q-audio-hdmi", 184 compatible = "fsl,imx6q-audio-hdmi",
184 "fsl,imx-audio-hdmi"; 185 "fsl,imx-audio-hdmi";
185 model = "imx-audio-hdmi"; 186 model = "imx-audio-hdmi";
186 hdmi-controller = <&hdmi_audio>; 187 hdmi-controller = <&hdmi_audio>;
187 }; 188 };
188 189
189 mxcfb1: fb@0 { 190 mxcfb1: fb@0 {
190 compatible = "fsl,mxc_sdc_fb"; 191 compatible = "fsl,mxc_sdc_fb";
191 disp_dev = "ldb"; 192 disp_dev = "ldb";
192 interface_pix_fmt = "RGB666"; 193 interface_pix_fmt = "RGB666";
193 default_bpp = <16>; 194 default_bpp = <16>;
194 int_clk = <0>; 195 int_clk = <0>;
195 late_init = <0>; 196 late_init = <0>;
196 status = "disabled"; 197 status = "disabled";
197 }; 198 };
198 199
199 mxcfb2: fb@1 { 200 mxcfb2: fb@1 {
200 compatible = "fsl,mxc_sdc_fb"; 201 compatible = "fsl,mxc_sdc_fb";
201 disp_dev = "hdmi"; 202 disp_dev = "hdmi";
202 interface_pix_fmt = "RGB24"; 203 interface_pix_fmt = "RGB24";
203 mode_str ="1920x1080M@60"; 204 mode_str ="1920x1080M@60";
204 default_bpp = <24>; 205 default_bpp = <24>;
205 int_clk = <0>; 206 int_clk = <0>;
206 late_init = <0>; 207 late_init = <0>;
207 status = "disabled"; 208 status = "disabled";
208 }; 209 };
209 210
210 mxcfb3: fb@2 { 211 mxcfb3: fb@2 {
211 compatible = "fsl,mxc_sdc_fb"; 212 compatible = "fsl,mxc_sdc_fb";
212 disp_dev = "lcd"; 213 disp_dev = "lcd";
213 interface_pix_fmt = "RGB565"; 214 interface_pix_fmt = "RGB565";
214 mode_str ="CLAA-WVGA"; 215 mode_str ="CLAA-WVGA";
215 default_bpp = <16>; 216 default_bpp = <16>;
216 int_clk = <0>; 217 int_clk = <0>;
217 late_init = <0>; 218 late_init = <0>;
218 status = "disabled"; 219 status = "disabled";
219 }; 220 };
220 221
221 mxcfb4: fb@3 { 222 mxcfb4: fb@3 {
222 compatible = "fsl,mxc_sdc_fb"; 223 compatible = "fsl,mxc_sdc_fb";
223 disp_dev = "ldb"; 224 disp_dev = "ldb";
224 interface_pix_fmt = "RGB666"; 225 interface_pix_fmt = "RGB666";
225 default_bpp = <16>; 226 default_bpp = <16>;
226 int_clk = <0>; 227 int_clk = <0>;
227 late_init = <0>; 228 late_init = <0>;
228 status = "disabled"; 229 status = "disabled";
229 }; 230 };
230 231
231 lcd@0 { 232 lcd@0 {
232 compatible = "fsl,lcd"; 233 compatible = "fsl,lcd";
233 ipu_id = <0>; 234 ipu_id = <0>;
234 disp_id = <0>; 235 disp_id = <0>;
235 default_ifmt = "RGB565"; 236 default_ifmt = "RGB565";
236 pinctrl-names = "default"; 237 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_ipu1>; 238 pinctrl-0 = <&pinctrl_ipu1>;
238 status = "okay"; 239 status = "okay";
239 }; 240 };
240 241
241 backlight { 242 backlight {
242 compatible = "pwm-backlight"; 243 compatible = "pwm-backlight";
243 pwms = <&pwm1 0 5000000>; 244 pwms = <&pwm1 0 5000000>;
244 brightness-levels = <0 4 8 16 32 64 128 255>; 245 brightness-levels = <0 4 8 16 32 64 128 255>;
245 default-brightness-level = <7>; 246 default-brightness-level = <7>;
246 status = "okay"; 247 status = "okay";
247 }; 248 };
248 249
249 leds { 250 leds {
250 compatible = "gpio-leds"; 251 compatible = "gpio-leds";
251 pinctrl-names = "default"; 252 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_gpio_leds>; 253 pinctrl-0 = <&pinctrl_gpio_leds>;
253 254
254 charger-led { 255 charger-led {
255 gpios = <&gpio1 2 0>; 256 gpios = <&gpio1 2 0>;
256 linux,default-trigger = "max8903-charger-charging"; 257 linux,default-trigger = "max8903-charger-charging";
257 retain-state-suspended; 258 retain-state-suspended;
258 }; 259 };
259 }; 260 };
260 261
261 v4l2_cap_0 { 262 v4l2_cap_0 {
262 compatible = "fsl,imx6q-v4l2-capture"; 263 compatible = "fsl,imx6q-v4l2-capture";
263 ipu_id = <0>; 264 ipu_id = <0>;
264 csi_id = <0>; 265 csi_id = <0>;
265 mclk_source = <0>; 266 mclk_source = <0>;
266 status = "okay"; 267 status = "okay";
267 }; 268 };
268 269
269 v4l2_cap_1 { 270 v4l2_cap_1 {
270 compatible = "fsl,imx6q-v4l2-capture"; 271 compatible = "fsl,imx6q-v4l2-capture";
271 ipu_id = <0>; 272 ipu_id = <0>;
272 csi_id = <1>; 273 csi_id = <1>;
273 mclk_source = <0>; 274 mclk_source = <0>;
274 status = "okay"; 275 status = "okay";
275 }; 276 };
276 277
277 v4l2_out { 278 v4l2_out {
278 compatible = "fsl,mxc_v4l2_output"; 279 compatible = "fsl,mxc_v4l2_output";
279 status = "okay"; 280 status = "okay";
280 }; 281 };
281 }; 282 };
282 283
283 &ipu1_csi0_from_ipu1_csi0_mux { 284 &ipu1_csi0_from_ipu1_csi0_mux {
284 bus-width = <8>; 285 bus-width = <8>;
285 data-shift = <12>; /* Lines 19:12 used */ 286 data-shift = <12>; /* Lines 19:12 used */
286 hsync-active = <1>; 287 hsync-active = <1>;
287 vsync-active = <1>; 288 vsync-active = <1>;
288 }; 289 };
289 290
290 &ipu1_csi0_mux_from_parallel_sensor { 291 &ipu1_csi0_mux_from_parallel_sensor {
291 /* Downstream driver doesn't use endpoints */ 292 /* Downstream driver doesn't use endpoints */
292 /* 293 /*
293 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; 294 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
294 */ 295 */
295 }; 296 };
296 297
297 &ipu1_csi0 { 298 &ipu1_csi0 {
298 pinctrl-names = "default"; 299 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_ipu1_csi0>; 300 pinctrl-0 = <&pinctrl_ipu1_csi0>;
300 }; 301 };
301 302
302 &mipi_csi { 303 &mipi_csi {
303 status = "okay"; 304 status = "okay";
304 }; 305 };
305 306
306 &audmux { 307 &audmux {
307 pinctrl-names = "default"; 308 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_audmux>; 309 pinctrl-0 = <&pinctrl_audmux>;
309 status = "okay"; 310 status = "okay";
310 }; 311 };
311 312
312 &clks { 313 &clks {
313 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 314 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
314 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 315 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
315 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, 316 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
316 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; 317 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
317 }; 318 };
318 319
319 &ecspi1 { 320 &ecspi1 {
320 fsl,spi-num-chipselects = <1>; 321 fsl,spi-num-chipselects = <1>;
321 cs-gpios = <&gpio4 9 0>; 322 cs-gpios = <&gpio4 9 0>;
322 pinctrl-names = "default"; 323 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_ecspi1>; 324 pinctrl-0 = <&pinctrl_ecspi1>;
324 status = "okay"; 325 status = "okay";
325 326
326 flash: m25p80@0 { 327 flash: m25p80@0 {
327 #address-cells = <1>; 328 #address-cells = <1>;
328 #size-cells = <1>; 329 #size-cells = <1>;
329 compatible = "st,m25p32", "jedec,spi-nor"; 330 compatible = "st,m25p32", "jedec,spi-nor";
330 spi-max-frequency = <20000000>; 331 spi-max-frequency = <20000000>;
331 reg = <0>; 332 reg = <0>;
332 }; 333 };
333 }; 334 };
334 335
335 &fec { 336 &fec {
336 pinctrl-names = "default"; 337 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_enet>; 338 pinctrl-0 = <&pinctrl_enet>;
338 phy-mode = "rgmii"; 339 phy-mode = "rgmii";
339 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 340 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
340 fsl,magic-packet; 341 fsl,magic-packet;
341 status = "okay"; 342 status = "okay";
342 }; 343 };
343 344
344 &gpc { 345 &gpc {
345 fsl,ldo-bypass = <1>; 346 fsl,ldo-bypass = <1>;
346 }; 347 };
347 348
348 &dcic1 { 349 &dcic1 {
349 dcic_id = <0>; 350 dcic_id = <0>;
350 dcic_mux = "dcic-hdmi"; 351 dcic_mux = "dcic-hdmi";
351 status = "okay"; 352 status = "okay";
352 }; 353 };
353 354
354 &dcic2 { 355 &dcic2 {
355 dcic_id = <1>; 356 dcic_id = <1>;
356 dcic_mux = "dcic-lvds1"; 357 dcic_mux = "dcic-lvds1";
357 status = "okay"; 358 status = "okay";
358 }; 359 };
359 360
360 &hdmi_audio { 361 &hdmi_audio {
361 status = "okay"; 362 status = "okay";
362 }; 363 };
363 364
364 &hdmi_cec { 365 &hdmi_cec {
365 pinctrl-names = "default"; 366 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_hdmi_cec>; 367 pinctrl-0 = <&pinctrl_hdmi_cec>;
367 status = "okay"; 368 status = "okay";
368 }; 369 };
369 370
370 &hdmi_core { 371 &hdmi_core {
371 ipu_id = <0>; 372 ipu_id = <0>;
372 disp_id = <0>; 373 disp_id = <0>;
373 status = "okay"; 374 status = "okay";
374 }; 375 };
375 376
376 &hdmi_video { 377 &hdmi_video {
377 fsl,phy_reg_vlev = <0x0294>; 378 fsl,phy_reg_vlev = <0x0294>;
378 fsl,phy_reg_cksymtx = <0x800d>; 379 fsl,phy_reg_cksymtx = <0x800d>;
379 HDMI-supply = <&reg_hdmi>; 380 HDMI-supply = <&reg_hdmi>;
380 status = "okay"; 381 status = "okay";
381 }; 382 };
382 383
383 &i2c1 { 384 &i2c1 {
384 clock-frequency = <100000>; 385 clock-frequency = <100000>;
385 pinctrl-names = "default", "gpio"; 386 pinctrl-names = "default", "gpio";
386 pinctrl-0 = <&pinctrl_i2c1>; 387 pinctrl-0 = <&pinctrl_i2c1>;
387 pinctrl-1 = <&pinctrl_i2c1_gpio>; 388 pinctrl-1 = <&pinctrl_i2c1_gpio>;
388 scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; 389 scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
389 sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; 390 sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
390 status = "okay"; 391 status = "okay";
391 392
392 codec: wm8962@1a { 393 codec: wm8962@1a {
393 compatible = "wlf,wm8962"; 394 compatible = "wlf,wm8962";
394 reg = <0x1a>; 395 reg = <0x1a>;
395 clocks = <&clks IMX6QDL_CLK_CKO>; 396 clocks = <&clks IMX6QDL_CLK_CKO>;
396 DCVDD-supply = <&reg_audio>; 397 DCVDD-supply = <&reg_audio>;
397 DBVDD-supply = <&reg_audio>; 398 DBVDD-supply = <&reg_audio>;
398 AVDD-supply = <&reg_audio>; 399 AVDD-supply = <&reg_audio>;
399 CPVDD-supply = <&reg_audio>; 400 CPVDD-supply = <&reg_audio>;
400 MICVDD-supply = <&reg_audio>; 401 MICVDD-supply = <&reg_audio>;
401 PLLVDD-supply = <&reg_audio>; 402 PLLVDD-supply = <&reg_audio>;
402 SPKVDD1-supply = <&reg_audio>; 403 SPKVDD1-supply = <&reg_audio>;
403 SPKVDD2-supply = <&reg_audio>; 404 SPKVDD2-supply = <&reg_audio>;
404 gpio-cfg = < 405 gpio-cfg = <
405 0x0000 /* 0:Default */ 406 0x0000 /* 0:Default */
406 0x0000 /* 1:Default */ 407 0x0000 /* 1:Default */
407 0x0013 /* 2:FN_DMICCLK */ 408 0x0013 /* 2:FN_DMICCLK */
408 0x0000 /* 3:Default */ 409 0x0000 /* 3:Default */
409 0x8014 /* 4:FN_DMICCDAT */ 410 0x8014 /* 4:FN_DMICCDAT */
410 0x0000 /* 5:Default */ 411 0x0000 /* 5:Default */
411 >; 412 >;
412 amic-mono; 413 amic-mono;
413 }; 414 };
414 415
415 mma8451@1c { 416 mma8451@1c {
416 compatible = "fsl,mma8451"; 417 compatible = "fsl,mma8451";
417 reg = <0x1c>; 418 reg = <0x1c>;
418 position = <0>; 419 position = <0>;
419 vdd-supply = <&reg_sensor>; 420 vdd-supply = <&reg_sensor>;
420 vddio-supply = <&reg_sensor>; 421 vddio-supply = <&reg_sensor>;
421 interrupt-parent = <&gpio1>; 422 interrupt-parent = <&gpio1>;
422 interrupts = <18 8>; 423 interrupts = <18 8>;
423 interrupt-route = <1>; 424 interrupt-route = <1>;
424 }; 425 };
425 426
426 ov564x: ov564x@3c { 427 ov564x: ov564x@3c {
427 compatible = "ovti,ov564x"; 428 compatible = "ovti,ov564x";
428 reg = <0x3c>; 429 reg = <0x3c>;
429 pinctrl-names = "default"; 430 pinctrl-names = "default";
430 pinctrl-0 = <&pinctrl_ipu1_2>; 431 pinctrl-0 = <&pinctrl_ipu1_2>;
431 clocks = <&clks IMX6QDL_CLK_CKO>; 432 clocks = <&clks IMX6QDL_CLK_CKO>;
432 clock-names = "csi_mclk"; 433 clock-names = "csi_mclk";
433 DOVDD-supply = <&vgen4_reg>; /* 1.8v */ 434 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
434 AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, 435 AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3,
435 on rev B board is VGEN5 */ 436 on rev B board is VGEN5 */
436 DVDD-supply = <&vgen2_reg>; /* 1.5v*/ 437 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
437 pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */ 438 pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */
438 rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */ 439 rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */
439 csi_id = <0>; 440 csi_id = <0>;
440 mclk = <24000000>; 441 mclk = <24000000>;
441 mclk_source = <0>; 442 mclk_source = <0>;
442 }; 443 };
443 }; 444 };
444 445
445 &i2c2 { 446 &i2c2 {
446 clock-frequency = <100000>; 447 clock-frequency = <100000>;
447 pinctrl-names = "default", "gpio"; 448 pinctrl-names = "default", "gpio";
448 pinctrl-0 = <&pinctrl_i2c2>; 449 pinctrl-0 = <&pinctrl_i2c2>;
449 pinctrl-1 = <&pinctrl_i2c2_gpio>; 450 pinctrl-1 = <&pinctrl_i2c2_gpio>;
450 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; 451 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
451 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; 452 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
452 status = "okay"; 453 status = "okay";
453 454
454 egalax_ts@04 { 455 egalax_ts@04 {
455 compatible = "eeti,egalax_ts"; 456 compatible = "eeti,egalax_ts";
456 reg = <0x04>; 457 reg = <0x04>;
457 pinctrl-names = "default"; 458 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_i2c2_egalax_int>; 459 pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
459 interrupt-parent = <&gpio6>; 460 interrupt-parent = <&gpio6>;
460 interrupts = <8 2>; 461 interrupts = <8 2>;
461 wakeup-gpios = <&gpio6 8 0>; 462 wakeup-gpios = <&gpio6 8 0>;
462 }; 463 };
463 464
464 max11801@48 { 465 max11801@48 {
465 compatible = "maxim,max11801"; 466 compatible = "maxim,max11801";
466 reg = <0x48>; 467 reg = <0x48>;
467 interrupt-parent = <&gpio3>; 468 interrupt-parent = <&gpio3>;
468 interrupts = <26 2>; 469 interrupts = <26 2>;
469 work-mode = <1>;/*DCM mode*/ 470 work-mode = <1>;/*DCM mode*/
470 }; 471 };
471 472
472 pmic: pfuze100@8 { 473 pmic: pfuze100@8 {
473 compatible = "fsl,pfuze100"; 474 compatible = "fsl,pfuze100";
474 reg = <0x08>; 475 reg = <0x08>;
475 476
476 regulators { 477 regulators {
477 sw1a_reg: sw1ab { 478 sw1a_reg: sw1ab {
478 regulator-min-microvolt = <300000>; 479 regulator-min-microvolt = <300000>;
479 regulator-max-microvolt = <1875000>; 480 regulator-max-microvolt = <1875000>;
480 regulator-boot-on; 481 regulator-boot-on;
481 regulator-always-on; 482 regulator-always-on;
482 regulator-ramp-delay = <6250>; 483 regulator-ramp-delay = <6250>;
483 }; 484 };
484 485
485 sw1c_reg: sw1c { 486 sw1c_reg: sw1c {
486 regulator-min-microvolt = <300000>; 487 regulator-min-microvolt = <300000>;
487 regulator-max-microvolt = <1875000>; 488 regulator-max-microvolt = <1875000>;
488 regulator-boot-on; 489 regulator-boot-on;
489 regulator-always-on; 490 regulator-always-on;
490 regulator-ramp-delay = <6250>; 491 regulator-ramp-delay = <6250>;
491 }; 492 };
492 493
493 sw2_reg: sw2 { 494 sw2_reg: sw2 {
494 regulator-min-microvolt = <800000>; 495 regulator-min-microvolt = <800000>;
495 regulator-max-microvolt = <3300000>; 496 regulator-max-microvolt = <3300000>;
496 regulator-boot-on; 497 regulator-boot-on;
497 regulator-always-on; 498 regulator-always-on;
498 regulator-ramp-delay = <6250>; 499 regulator-ramp-delay = <6250>;
499 }; 500 };
500 501
501 sw3a_reg: sw3a { 502 sw3a_reg: sw3a {
502 regulator-min-microvolt = <400000>; 503 regulator-min-microvolt = <400000>;
503 regulator-max-microvolt = <1975000>; 504 regulator-max-microvolt = <1975000>;
504 regulator-boot-on; 505 regulator-boot-on;
505 regulator-always-on; 506 regulator-always-on;
506 }; 507 };
507 508
508 sw3b_reg: sw3b { 509 sw3b_reg: sw3b {
509 regulator-min-microvolt = <400000>; 510 regulator-min-microvolt = <400000>;
510 regulator-max-microvolt = <1975000>; 511 regulator-max-microvolt = <1975000>;
511 regulator-boot-on; 512 regulator-boot-on;
512 regulator-always-on; 513 regulator-always-on;
513 }; 514 };
514 515
515 sw4_reg: sw4 { 516 sw4_reg: sw4 {
516 regulator-min-microvolt = <800000>; 517 regulator-min-microvolt = <800000>;
517 regulator-max-microvolt = <3300000>; 518 regulator-max-microvolt = <3300000>;
518 regulator-always-on; 519 regulator-always-on;
519 }; 520 };
520 521
521 swbst_reg: swbst { 522 swbst_reg: swbst {
522 regulator-min-microvolt = <5000000>; 523 regulator-min-microvolt = <5000000>;
523 regulator-max-microvolt = <5150000>; 524 regulator-max-microvolt = <5150000>;
524 }; 525 };
525 526
526 snvs_reg: vsnvs { 527 snvs_reg: vsnvs {
527 regulator-min-microvolt = <1000000>; 528 regulator-min-microvolt = <1000000>;
528 regulator-max-microvolt = <3000000>; 529 regulator-max-microvolt = <3000000>;
529 regulator-boot-on; 530 regulator-boot-on;
530 regulator-always-on; 531 regulator-always-on;
531 }; 532 };
532 533
533 vref_reg: vrefddr { 534 vref_reg: vrefddr {
534 regulator-boot-on; 535 regulator-boot-on;
535 regulator-always-on; 536 regulator-always-on;
536 }; 537 };
537 538
538 vgen1_reg: vgen1 { 539 vgen1_reg: vgen1 {
539 regulator-min-microvolt = <800000>; 540 regulator-min-microvolt = <800000>;
540 regulator-max-microvolt = <1550000>; 541 regulator-max-microvolt = <1550000>;
541 }; 542 };
542 543
543 vgen2_reg: vgen2 { 544 vgen2_reg: vgen2 {
544 regulator-min-microvolt = <800000>; 545 regulator-min-microvolt = <800000>;
545 regulator-max-microvolt = <1550000>; 546 regulator-max-microvolt = <1550000>;
546 }; 547 };
547 548
548 vgen3_reg: vgen3 { 549 vgen3_reg: vgen3 {
549 regulator-min-microvolt = <1800000>; 550 regulator-min-microvolt = <1800000>;
550 regulator-max-microvolt = <3300000>; 551 regulator-max-microvolt = <3300000>;
551 }; 552 };
552 553
553 vgen4_reg: vgen4 { 554 vgen4_reg: vgen4 {
554 regulator-min-microvolt = <1800000>; 555 regulator-min-microvolt = <1800000>;
555 regulator-max-microvolt = <3300000>; 556 regulator-max-microvolt = <3300000>;
556 regulator-always-on; 557 regulator-always-on;
557 }; 558 };
558 559
559 vgen5_reg: vgen5 { 560 vgen5_reg: vgen5 {
560 regulator-min-microvolt = <1800000>; 561 regulator-min-microvolt = <1800000>;
561 regulator-max-microvolt = <3300000>; 562 regulator-max-microvolt = <3300000>;
562 regulator-always-on; 563 regulator-always-on;
563 }; 564 };
564 565
565 vgen6_reg: vgen6 { 566 vgen6_reg: vgen6 {
566 regulator-min-microvolt = <1800000>; 567 regulator-min-microvolt = <1800000>;
567 regulator-max-microvolt = <3300000>; 568 regulator-max-microvolt = <3300000>;
568 regulator-always-on; 569 regulator-always-on;
569 }; 570 };
570 }; 571 };
571 }; 572 };
572 573
573 hdmi_edid: edid@50 { 574 hdmi_edid: edid@50 {
574 compatible = "fsl,imx6-hdmi-i2c"; 575 compatible = "fsl,imx6-hdmi-i2c";
575 reg = <0x50>; 576 reg = <0x50>;
576 }; 577 };
577 578
578 ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */ 579 ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */
579 compatible = "ovti,ov564x_mipi"; 580 compatible = "ovti,ov564x_mipi";
580 reg = <0x3c>; 581 reg = <0x3c>;
581 clocks = <&clks 201>; 582 clocks = <&clks 201>;
582 clock-names = "csi_mclk"; 583 clock-names = "csi_mclk";
583 DOVDD-supply = <&vgen4_reg>; /* 1.8v */ 584 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
584 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 585 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
585 rev B board is VGEN5 */ 586 rev B board is VGEN5 */
586 DVDD-supply = <&vgen2_reg>; /* 1.5v*/ 587 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
587 pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */ 588 pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */
588 rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */ 589 rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */
589 csi_id = <1>; 590 csi_id = <1>;
590 mclk = <24000000>; 591 mclk = <24000000>;
591 mclk_source = <0>; 592 mclk_source = <0>;
592 }; 593 };
593 }; 594 };
594 595
595 &i2c3 { 596 &i2c3 {
596 clock-frequency = <100000>; 597 clock-frequency = <100000>;
597 pinctrl-names = "default", "gpio"; 598 pinctrl-names = "default", "gpio";
598 pinctrl-0 = <&pinctrl_i2c3>; 599 pinctrl-0 = <&pinctrl_i2c3>;
599 pinctrl-1 = <&pinctrl_i2c3_gpio>; 600 pinctrl-1 = <&pinctrl_i2c3_gpio>;
600 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 601 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
601 sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 602 sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
602 status = "okay"; 603 status = "okay";
603 604
604 egalax_ts@04 { 605 egalax_ts@04 {
605 compatible = "eeti,egalax_ts"; 606 compatible = "eeti,egalax_ts";
606 reg = <0x04>; 607 reg = <0x04>;
607 pinctrl-names = "default"; 608 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_i2c3_egalax_int>; 609 pinctrl-0 = <&pinctrl_i2c3_egalax_int>;
609 interrupt-parent = <&gpio6>; 610 interrupt-parent = <&gpio6>;
610 interrupts = <7 2>; 611 interrupts = <7 2>;
611 wakeup-gpios = <&gpio6 7 0>; 612 wakeup-gpios = <&gpio6 7 0>;
612 }; 613 };
613 614
614 isl29023@44 { 615 isl29023@44 {
615 compatible = "fsl,isl29023"; 616 compatible = "fsl,isl29023";
616 reg = <0x44>; 617 reg = <0x44>;
617 rext = <499>; 618 rext = <499>;
618 vdd-supply = <&reg_sensor>; 619 vdd-supply = <&reg_sensor>;
619 interrupt-parent = <&gpio3>; 620 interrupt-parent = <&gpio3>;
620 interrupts = <9 2>; 621 interrupts = <9 2>;
621 }; 622 };
622 623
623 mag3110@0e { 624 mag3110@0e {
624 compatible = "fsl,mag3110"; 625 compatible = "fsl,mag3110";
625 reg = <0x0e>; 626 reg = <0x0e>;
626 position = <2>; 627 position = <2>;
627 vdd-supply = <&reg_sensor>; 628 vdd-supply = <&reg_sensor>;
628 vddio-supply = <&reg_sensor>; 629 vddio-supply = <&reg_sensor>;
629 interrupt-parent = <&gpio3>; 630 interrupt-parent = <&gpio3>;
630 interrupts = <16 1>; 631 interrupts = <16 1>;
631 }; 632 };
632 }; 633 };
633 634
634 &iomuxc { 635 &iomuxc {
635 pinctrl-names = "default"; 636 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_hog>; 637 pinctrl-0 = <&pinctrl_hog>;
637 638
638 imx6qdl-sabresd { 639 imx6qdl-sabresd {
639 pinctrl_hog: hoggrp { 640 pinctrl_hog: hoggrp {
640 fsl,pins = < 641 fsl,pins = <
641 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 642 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
642 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 643 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
643 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 644 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
644 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 645 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
645 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 646 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
646 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 647 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
647 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 648 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
648 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 649 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
649 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 650 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
650 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 651 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
651 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 652 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
652 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 653 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
653 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 654 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
654 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 655 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
655 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 656 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
656 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 657 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
657 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 658 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
658 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 659 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
659 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 660 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
660 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 661 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
661 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 662 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
662 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 663 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
663 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 664 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
664 >; 665 >;
665 }; 666 };
666 667
667 pinctrl_audmux: audmuxgrp { 668 pinctrl_audmux: audmuxgrp {
668 fsl,pins = < 669 fsl,pins = <
669 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 670 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
670 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 671 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
671 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 672 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
672 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 673 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
673 >; 674 >;
674 }; 675 };
675 676
676 pinctrl_ecspi1: ecspi1grp { 677 pinctrl_ecspi1: ecspi1grp {
677 fsl,pins = < 678 fsl,pins = <
678 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 679 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
679 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 680 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
680 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 681 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
681 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 682 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
682 >; 683 >;
683 }; 684 };
684 685
685 pinctrl_i2c2_egalax_int: egalax_i2c2_intgrp { 686 pinctrl_i2c2_egalax_int: egalax_i2c2_intgrp {
686 fsl,pins = < 687 fsl,pins = <
687 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 688 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
688 >; 689 >;
689 }; 690 };
690 691
691 pinctrl_i2c3_egalax_int: egalax_i2c3_intgrp { 692 pinctrl_i2c3_egalax_int: egalax_i2c3_intgrp {
692 fsl,pins = < 693 fsl,pins = <
693 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 694 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
694 >; 695 >;
695 }; 696 };
696 697
697 pinctrl_enet: enetgrp { 698 pinctrl_enet: enetgrp {
698 fsl,pins = < 699 fsl,pins = <
699 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 700 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
700 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 701 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
701 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 702 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
702 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 703 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
703 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 704 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
704 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 705 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
705 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 706 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
706 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 707 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
707 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 708 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
708 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 709 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
709 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 710 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
710 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 711 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
711 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 712 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
712 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 713 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
713 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 714 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
714 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 715 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
715 >; 716 >;
716 }; 717 };
717 718
718 pinctrl_enet_irq: enetirqgrp { 719 pinctrl_enet_irq: enetirqgrp {
719 fsl,pins = < 720 fsl,pins = <
720 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 721 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
721 >; 722 >;
722 }; 723 };
723 724
724 pinctrl_gpio_keys: gpio_keysgrp { 725 pinctrl_gpio_keys: gpio_keysgrp {
725 fsl,pins = < 726 fsl,pins = <
726 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 727 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
727 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 728 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
728 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 729 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
729 >; 730 >;
730 }; 731 };
731 732
732 pinctrl_hdmi_cec: hdmicecgrp { 733 pinctrl_hdmi_cec: hdmicecgrp {
733 fsl,pins = < 734 fsl,pins = <
734 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 735 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0
735 >; 736 >;
736 }; 737 };
737 738
738 pinctrl_hdmi_hdcp: hdmihdcpgrp { 739 pinctrl_hdmi_hdcp: hdmihdcpgrp {
739 fsl,pins = < 740 fsl,pins = <
740 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 741 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
741 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 742 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
742 >; 743 >;
743 }; 744 };
744 745
745 pinctrl_i2c1: i2c1grp { 746 pinctrl_i2c1: i2c1grp {
746 fsl,pins = < 747 fsl,pins = <
747 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 748 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
748 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 749 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
749 >; 750 >;
750 }; 751 };
751 752
752 pinctrl_i2c1_gpio: i2c1grp_gpio { 753 pinctrl_i2c1_gpio: i2c1grp_gpio {
753 fsl,pins = < 754 fsl,pins = <
754 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b8b1 755 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b8b1
755 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b8b1 756 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b8b1
756 >; 757 >;
757 }; 758 };
758 759
759 pinctrl_i2c2: i2c2grp { 760 pinctrl_i2c2: i2c2grp {
760 fsl,pins = < 761 fsl,pins = <
761 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 762 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
762 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 763 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
763 >; 764 >;
764 }; 765 };
765 766
766 pinctrl_i2c2_gpio: i2c2_gpio_grp { 767 pinctrl_i2c2_gpio: i2c2_gpio_grp {
767 fsl,pins = < 768 fsl,pins = <
768 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 769 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
769 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 770 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
770 >; 771 >;
771 }; 772 };
772 773
773 pinctrl_i2c3: i2c3grp { 774 pinctrl_i2c3: i2c3grp {
774 fsl,pins = < 775 fsl,pins = <
775 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 776 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
776 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 777 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
777 >; 778 >;
778 }; 779 };
779 780
780 pinctrl_i2c3_gpio: i2c3grp_gpio { 781 pinctrl_i2c3_gpio: i2c3grp_gpio {
781 fsl,pins = < 782 fsl,pins = <
782 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b1 783 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b1
783 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b8b1 784 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b8b1
784 >; 785 >;
785 }; 786 };
786 787
787 pinctrl_ipu1: ipu1grp { 788 pinctrl_ipu1: ipu1grp {
788 fsl,pins = < 789 fsl,pins = <
789 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 790 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
790 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 791 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
791 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 792 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
792 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 793 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
793 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 794 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
794 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 795 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
795 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 796 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
796 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 797 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
797 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 798 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
798 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 799 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
799 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 800 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
800 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 801 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
801 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 802 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
802 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 803 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
803 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 804 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
804 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 805 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
805 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 806 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
806 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 807 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
807 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 808 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
808 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 809 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
809 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 810 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
810 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 811 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
811 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 812 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
812 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 813 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
813 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 814 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
814 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 815 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
815 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 816 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
816 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 817 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
817 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 818 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
818 >; 819 >;
819 }; 820 };
820 821
821 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ 822 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
822 fsl,pins = < 823 fsl,pins = <
823 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 824 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
824 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 825 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
825 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 826 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
826 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 827 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
827 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 828 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
828 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 829 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
829 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 830 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
830 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 831 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
831 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 832 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
832 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 833 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
833 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 834 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
834 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 835 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
835 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000 836 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
836 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 837 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
837 >; 838 >;
838 }; 839 };
839 840
840 pinctrl_ipu1_csi0: ipu1csi0grp { 841 pinctrl_ipu1_csi0: ipu1csi0grp {
841 fsl,pins = < 842 fsl,pins = <
842 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 843 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
843 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 844 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
844 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 845 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
845 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 846 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
846 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 847 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
847 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 848 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
848 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 849 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
849 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 850 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
850 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 851 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
851 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 852 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
852 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 853 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
853 >; 854 >;
854 }; 855 };
855 856
856 pinctrl_ov5640: ov5640grp { 857 pinctrl_ov5640: ov5640grp {
857 fsl,pins = < 858 fsl,pins = <
858 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 859 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
859 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 860 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
860 >; 861 >;
861 }; 862 };
862 863
863 pinctrl_ov5642: ov5642grp { 864 pinctrl_ov5642: ov5642grp {
864 fsl,pins = < 865 fsl,pins = <
865 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 866 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
866 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 867 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
867 >; 868 >;
868 }; 869 };
869 870
870 pinctrl_pcie: pciegrp { 871 pinctrl_pcie: pciegrp {
871 fsl,pins = < 872 fsl,pins = <
872 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 873 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
873 >; 874 >;
874 }; 875 };
875 876
876 pinctrl_pcie_reg: pciereggrp { 877 pinctrl_pcie_reg: pciereggrp {
877 fsl,pins = < 878 fsl,pins = <
878 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 879 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
879 >; 880 >;
880 }; 881 };
881 882
882 pinctrl_pwm1: pwm1grp { 883 pinctrl_pwm1: pwm1grp {
883 fsl,pins = < 884 fsl,pins = <
884 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 885 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
885 >; 886 >;
886 }; 887 };
887 888
888 pinctrl_uart1: uart1grp { 889 pinctrl_uart1: uart1grp {
889 fsl,pins = < 890 fsl,pins = <
890 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 891 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
891 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 892 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
892 >; 893 >;
893 }; 894 };
894 895
895 pinctrl_uart5_1: uart5grp-1 { 896 pinctrl_uart5_1: uart5grp-1 {
896 fsl,pins = < 897 fsl,pins = <
897 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 898 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
898 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 899 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
899 MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 900 MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1
900 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 901 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1
901 >; 902 >;
902 }; 903 };
903 904
904 pinctrl_uart5dte_1: uart5dtegrp-1 { 905 pinctrl_uart5dte_1: uart5dtegrp-1 {
905 fsl,pins = < 906 fsl,pins = <
906 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 907 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
907 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 908 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
908 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 909 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1
909 MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 910 MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1
910 >; 911 >;
911 }; 912 };
912 913
913 pinctrl_usbotg: usbotggrp { 914 pinctrl_usbotg: usbotggrp {
914 fsl,pins = < 915 fsl,pins = <
915 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 916 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
916 >; 917 >;
917 }; 918 };
918 919
919 pinctrl_usdhc2: usdhc2grp { 920 pinctrl_usdhc2: usdhc2grp {
920 fsl,pins = < 921 fsl,pins = <
921 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 922 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
922 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 923 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
923 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 924 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
924 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 925 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
925 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 926 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
926 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 927 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
927 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 928 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
928 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 929 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
929 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 930 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
930 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 931 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
931 >; 932 >;
932 }; 933 };
933 934
934 pinctrl_usdhc3: usdhc3grp { 935 pinctrl_usdhc3: usdhc3grp {
935 fsl,pins = < 936 fsl,pins = <
936 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 937 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
937 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 938 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
938 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 939 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
939 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 940 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
940 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 941 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
941 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 942 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
942 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 943 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
943 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 944 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
944 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 945 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
945 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 946 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
946 >; 947 >;
947 }; 948 };
948 949
949 pinctrl_usdhc4: usdhc4grp { 950 pinctrl_usdhc4: usdhc4grp {
950 fsl,pins = < 951 fsl,pins = <
951 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 952 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
952 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 953 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
953 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 954 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
954 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 955 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
955 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 956 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
956 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 957 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
957 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 958 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
958 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 959 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
959 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 960 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
960 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 961 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
961 >; 962 >;
962 }; 963 };
963 964
964 pinctrl_wdog: wdoggrp { 965 pinctrl_wdog: wdoggrp {
965 fsl,pins = < 966 fsl,pins = <
966 MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 967 MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
967 >; 968 >;
968 }; 969 };
969 }; 970 };
970 971
971 gpio_leds { 972 gpio_leds {
972 pinctrl_gpio_leds: gpioledsgrp { 973 pinctrl_gpio_leds: gpioledsgrp {
973 fsl,pins = < 974 fsl,pins = <
974 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 975 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
975 >; 976 >;
976 }; 977 };
977 }; 978 };
978 }; 979 };
979 980
980 &ldb { 981 &ldb {
981 status = "okay"; 982 status = "okay";
982 983
983 lvds-channel@0 { 984 lvds-channel@0 {
984 fsl,data-mapping = "spwg"; 985 fsl,data-mapping = "spwg";
985 fsl,data-width = <18>; 986 fsl,data-width = <18>;
986 status = "okay"; 987 status = "okay";
987 988
988 display-timings { 989 display-timings {
989 native-mode = <&timing0>; 990 native-mode = <&timing0>;
990 timing0: hsd100pxn1 { 991 timing0: hsd100pxn1 {
991 clock-frequency = <65000000>; 992 clock-frequency = <65000000>;
992 hactive = <1024>; 993 hactive = <1024>;
993 vactive = <768>; 994 vactive = <768>;
994 hback-porch = <220>; 995 hback-porch = <220>;
995 hfront-porch = <40>; 996 hfront-porch = <40>;
996 vback-porch = <21>; 997 vback-porch = <21>;
997 vfront-porch = <7>; 998 vfront-porch = <7>;
998 hsync-len = <60>; 999 hsync-len = <60>;
999 vsync-len = <10>; 1000 vsync-len = <10>;
1000 }; 1001 };
1001 }; 1002 };
1002 }; 1003 };
1003 1004
1004 lvds-channel@1 { 1005 lvds-channel@1 {
1005 fsl,data-mapping = "spwg"; 1006 fsl,data-mapping = "spwg";
1006 fsl,data-width = <18>; 1007 fsl,data-width = <18>;
1007 primary; 1008 primary;
1008 status = "okay"; 1009 status = "okay";
1009 1010
1010 display-timings { 1011 display-timings {
1011 native-mode = <&timing1>; 1012 native-mode = <&timing1>;
1012 timing1: hsd100pxn1 { 1013 timing1: hsd100pxn1 {
1013 clock-frequency = <65000000>; 1014 clock-frequency = <65000000>;
1014 hactive = <1024>; 1015 hactive = <1024>;
1015 vactive = <768>; 1016 vactive = <768>;
1016 hback-porch = <220>; 1017 hback-porch = <220>;
1017 hfront-porch = <40>; 1018 hfront-porch = <40>;
1018 vback-porch = <21>; 1019 vback-porch = <21>;
1019 vfront-porch = <7>; 1020 vfront-porch = <7>;
1020 hsync-len = <60>; 1021 hsync-len = <60>;
1021 vsync-len = <10>; 1022 vsync-len = <10>;
1022 }; 1023 };
1023 }; 1024 };
1024 }; 1025 };
1025 }; 1026 };
1026 1027
1027 &mipi_csi { 1028 &mipi_csi {
1028 status = "okay"; 1029 status = "okay";
1029 ipu_id = <0>; 1030 ipu_id = <0>;
1030 csi_id = <1>; 1031 csi_id = <1>;
1031 v_channel = <0>; 1032 v_channel = <0>;
1032 lanes = <2>; 1033 lanes = <2>;
1033 }; 1034 };
1034 1035
1035 &mipi_dsi { 1036 &mipi_dsi {
1036 dev_id = <0>; 1037 dev_id = <0>;
1037 disp_id = <1>; 1038 disp_id = <1>;
1038 lcd_panel = "TRULY-WVGA"; 1039 lcd_panel = "TRULY-WVGA";
1039 disp-power-on-supply = <&reg_mipi_dsi_pwr_on>; 1040 disp-power-on-supply = <&reg_mipi_dsi_pwr_on>;
1040 reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 1041 reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
1041 reset-delay-us = <50>; 1042 reset-delay-us = <50>;
1042 status = "okay"; 1043 status = "okay";
1043 }; 1044 };
1044 1045
1045 &pcie { 1046 &pcie {
1046 pinctrl-names = "default"; 1047 pinctrl-names = "default";
1047 pinctrl-0 = <&pinctrl_pcie>; 1048 pinctrl-0 = <&pinctrl_pcie>;
1048 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 1049 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
1049 status = "okay"; 1050 status = "okay";
1050 }; 1051 };
1051 1052
1052 &pwm1 { 1053 &pwm1 {
1053 pinctrl-names = "default"; 1054 pinctrl-names = "default";
1054 pinctrl-0 = <&pinctrl_pwm1>; 1055 pinctrl-0 = <&pinctrl_pwm1>;
1055 status = "okay"; 1056 status = "okay";
1056 }; 1057 };
1057 1058
1058 &reg_arm { 1059 &reg_arm {
1059 vin-supply = <&sw1a_reg>; 1060 vin-supply = <&sw1a_reg>;
1060 }; 1061 };
1061 1062
1062 &reg_pu { 1063 &reg_pu {
1063 vin-supply = <&sw1c_reg>; 1064 vin-supply = <&sw1c_reg>;
1064 }; 1065 };
1065 1066
1066 &reg_soc { 1067 &reg_soc {
1067 vin-supply = <&sw1c_reg>; 1068 vin-supply = <&sw1c_reg>;
1068 }; 1069 };
1069 1070
1070 &snvs_poweroff { 1071 &snvs_poweroff {
1071 status = "okay"; 1072 status = "okay";
1072 }; 1073 };
1073 1074
1074 &ssi2 { 1075 &ssi2 {
1075 assigned-clocks = <&clks IMX6QDL_CLK_PLL4>, 1076 assigned-clocks = <&clks IMX6QDL_CLK_PLL4>,
1076 <&clks IMX6QDL_PLL4_BYPASS>, 1077 <&clks IMX6QDL_PLL4_BYPASS>,
1077 <&clks IMX6QDL_CLK_SSI2_SEL>; 1078 <&clks IMX6QDL_CLK_SSI2_SEL>;
1078 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>, 1079 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>,
1079 <&clks IMX6QDL_CLK_PLL4>, 1080 <&clks IMX6QDL_CLK_PLL4>,
1080 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; 1081 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
1081 assigned-clock-rates = <737280000>, <0>, <0>; 1082 assigned-clock-rates = <737280000>, <0>, <0>;
1082 status = "okay"; 1083 status = "okay";
1083 }; 1084 };
1084 1085
1085 &uart1 { 1086 &uart1 {
1086 pinctrl-names = "default"; 1087 pinctrl-names = "default";
1087 pinctrl-0 = <&pinctrl_uart1>; 1088 pinctrl-0 = <&pinctrl_uart1>;
1088 status = "okay"; 1089 status = "okay";
1089 }; 1090 };
1090 1091
1091 &usbh1 { 1092 &usbh1 {
1092 vbus-supply = <&reg_usb_h1_vbus>; 1093 vbus-supply = <&reg_usb_h1_vbus>;
1093 status = "okay"; 1094 status = "okay";
1094 }; 1095 };
1095 1096
1096 &usbotg { 1097 &usbotg {
1097 vbus-supply = <&reg_usb_otg_vbus>; 1098 vbus-supply = <&reg_usb_otg_vbus>;
1098 pinctrl-names = "default"; 1099 pinctrl-names = "default";
1099 pinctrl-0 = <&pinctrl_usbotg>; 1100 pinctrl-0 = <&pinctrl_usbotg>;
1100 disable-over-current; 1101 disable-over-current;
1101 srp-disable; 1102 srp-disable;
1102 hnp-disable; 1103 hnp-disable;
1103 adp-disable; 1104 adp-disable;
1104 status = "okay"; 1105 status = "okay";
1105 }; 1106 };
1106 1107
1107 &usbphy1 { 1108 &usbphy1 {
1108 fsl,tx-d-cal = <106>; 1109 fsl,tx-d-cal = <106>;
1109 }; 1110 };
1110 1111
1111 &usbphy2 { 1112 &usbphy2 {
1112 fsl,tx-d-cal = <106>; 1113 fsl,tx-d-cal = <106>;
1113 }; 1114 };
1114 1115
1115 &usdhc2 { 1116 &usdhc2 {
1116 pinctrl-names = "default"; 1117 pinctrl-names = "default";
1117 pinctrl-0 = <&pinctrl_usdhc2>; 1118 pinctrl-0 = <&pinctrl_usdhc2>;
1118 bus-width = <8>; 1119 bus-width = <8>;
1119 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 1120 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
1120 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 1121 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
1121 no-1-8-v; 1122 no-1-8-v;
1122 keep-power-in-suspend; 1123 keep-power-in-suspend;
1123 enable-sdio-wakeup; 1124 enable-sdio-wakeup;
1124 status = "okay"; 1125 status = "okay";
1125 }; 1126 };
1126 1127
1127 &usdhc3 { 1128 &usdhc3 {
1128 pinctrl-names = "default"; 1129 pinctrl-names = "default";
1129 pinctrl-0 = <&pinctrl_usdhc3>; 1130 pinctrl-0 = <&pinctrl_usdhc3>;
1130 bus-width = <8>; 1131 bus-width = <8>;
1131 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 1132 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
1132 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 1133 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
1133 no-1-8-v; 1134 no-1-8-v;
1134 keep-power-in-suspend; 1135 keep-power-in-suspend;
1135 enable-sdio-wakeup; 1136 enable-sdio-wakeup;
1136 status = "okay"; 1137 status = "okay";
1137 }; 1138 };
1138 1139
1139 &usdhc4 { 1140 &usdhc4 {
1140 pinctrl-names = "default"; 1141 pinctrl-names = "default";
1141 pinctrl-0 = <&pinctrl_usdhc4>; 1142 pinctrl-0 = <&pinctrl_usdhc4>;
1142 bus-width = <8>; 1143 bus-width = <8>;
1143 non-removable; 1144 non-removable;
1144 no-1-8-v; 1145 no-1-8-v;
1145 keep-power-in-suspend; 1146 keep-power-in-suspend;
1146 status = "okay"; 1147 status = "okay";
1147 }; 1148 };
1148 1149
1149 &wdog1 { 1150 &wdog1 {
1150 status = "disabled"; 1151 status = "disabled";
1151 }; 1152 };
1152 1153
1153 &wdog2 { 1154 &wdog2 {
1154 pinctrl-names = "default"; 1155 pinctrl-names = "default";
1155 pinctrl-0 = <&pinctrl_wdog>; 1156 pinctrl-0 = <&pinctrl_wdog>;
1156 fsl,ext-reset-output; 1157 fsl,ext-reset-output;
1157 status = "okay"; 1158 status = "okay";
1158 }; 1159 };
1159 1160