Eric Lee / smarc-uboot

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/*

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/*

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*

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*

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* SPDX-License-Identifier: GPL-2.0+

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* SPDX-License-Identifier: GPL-2.0+

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*/

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*/

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#include <common.h>

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#include <common.h>

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#include <dm.h>

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#include <dm.h>

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#include <malloc.h>

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#include <malloc.h>

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#include <memalign.h>

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#include <memalign.h>

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#include <miiphy.h>

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#include <miiphy.h>

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#include <net.h>

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#include <net.h>

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#include <netdev.h>

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#include <netdev.h>

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#include "fec_mxc.h"

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#include "fec_mxc.h"

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#include <asm/io.h>

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#include <asm/io.h>

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#include <linux/errno.h>

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#include <linux/errno.h>

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#include <linux/compiler.h>

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#include <linux/compiler.h>

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#include <asm/arch/clock.h>

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#include <asm/arch/clock.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/mach-imx/sys_proto.h>

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#include <asm/mach-imx/sys_proto.h>

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DECLARE_GLOBAL_DATA_PTR;

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DECLARE_GLOBAL_DATA_PTR;

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/*

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/*

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* Timeout the transfer after 5 mS. This is usually a bit more, since

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* Timeout the transfer after 5 mS. This is usually a bit more, since

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* the code in the tightloops this timeout is used in adds some overhead.

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* the code in the tightloops this timeout is used in adds some overhead.

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*/

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*/

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#define FEC_XFER_TIMEOUT 5000

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#define FEC_XFER_TIMEOUT 5000

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/*

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/*

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* The standard 32-byte DMA alignment does not work on mx6solox, which requires

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* The standard 32-byte DMA alignment does not work on mx6solox, which requires

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* 64-byte alignment in the DMA RX FEC buffer.

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* 64-byte alignment in the DMA RX FEC buffer.

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* Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also

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* Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also

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* satisfies the alignment on other SoCs (32-bytes)

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* satisfies the alignment on other SoCs (32-bytes)

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*/

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*/

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#define FEC_DMA_RX_MINALIGN 64

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#define FEC_DMA_RX_MINALIGN 64

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#ifndef CONFIG_MII

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#ifndef CONFIG_MII

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#error "CONFIG_MII has to be defined!"

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#error "CONFIG_MII has to be defined!"

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#endif

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#endif

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#ifndef CONFIG_FEC_XCV_TYPE

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#ifndef CONFIG_FEC_XCV_TYPE

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#define CONFIG_FEC_XCV_TYPE MII100

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#define CONFIG_FEC_XCV_TYPE MII100

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#endif

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#endif

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/*

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/*

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* The i.MX28 operates with packets in big endian. We need to swap them before

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* The i.MX28 operates with packets in big endian. We need to swap them before

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* sending and after receiving.

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* sending and after receiving.

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*/

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*/

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#ifdef CONFIG_MX28

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#ifdef CONFIG_MX28

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#define CONFIG_FEC_MXC_SWAP_PACKET

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#define CONFIG_FEC_MXC_SWAP_PACKET

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#endif

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#endif

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#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))

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#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))

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/* Check various alignment issues at compile time */

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/* Check various alignment issues at compile time */

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#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))

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#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))

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#error "ARCH_DMA_MINALIGN must be multiple of 16!"

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#error "ARCH_DMA_MINALIGN must be multiple of 16!"

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#endif

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#endif

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#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \

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#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \

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(PKTALIGN % ARCH_DMA_MINALIGN != 0))

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(PKTALIGN % ARCH_DMA_MINALIGN != 0))

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#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"

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#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"

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#endif

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#endif

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#undef DEBUG

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#undef DEBUG

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#ifdef CONFIG_FEC_MXC_SWAP_PACKET

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#ifdef CONFIG_FEC_MXC_SWAP_PACKET

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static void swap_packet(uint32_t *packet, int length)

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static void swap_packet(uint32_t *packet, int length)

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{

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{

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int i;

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int i;

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for (i = 0; i < DIV_ROUND_UP(length, 4); i++)

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for (i = 0; i < DIV_ROUND_UP(length, 4); i++)

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packet[i] = __swab32(packet[i]);

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packet[i] = __swab32(packet[i]);

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}

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}

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#endif

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#endif

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/* MII-interface related functions */

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/* MII-interface related functions */

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static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,

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static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,

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uint8_t regaddr)

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uint8_t regaddr)

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{

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{

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uint32_t reg; /* convenient holder for the PHY register */

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uint32_t reg; /* convenient holder for the PHY register */

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uint32_t phy; /* convenient holder for the PHY */

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uint32_t phy; /* convenient holder for the PHY */

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uint32_t start;

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uint32_t start;

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int val;

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int val;

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/*

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/*

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* reading from any PHY's register is done by properly

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* reading from any PHY's register is done by properly

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* programming the FEC's MII data register.

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* programming the FEC's MII data register.

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*/

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*/

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writel(FEC_IEVENT_MII, &eth->ievent);

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writel(FEC_IEVENT_MII, &eth->ievent);

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reg = regaddr << FEC_MII_DATA_RA_SHIFT;

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reg = regaddr << FEC_MII_DATA_RA_SHIFT;

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phy = phyaddr << FEC_MII_DATA_PA_SHIFT;

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phy = phyaddr << FEC_MII_DATA_PA_SHIFT;

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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |

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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |

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phy | reg, &eth->mii_data);

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phy | reg, &eth->mii_data);

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/* wait for the related interrupt */

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/* wait for the related interrupt */

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start = get_timer(0);

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start = get_timer(0);

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while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {

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while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {

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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {

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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {

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printf("Read MDIO failed...\n");

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printf("Read MDIO failed...\n");

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return -1;

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return -1;

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}

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}

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}

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}

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/* clear mii interrupt bit */

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/* clear mii interrupt bit */

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writel(FEC_IEVENT_MII, &eth->ievent);

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writel(FEC_IEVENT_MII, &eth->ievent);

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/* it's now safe to read the PHY's register */

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/* it's now safe to read the PHY's register */

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val = (unsigned short)readl(&eth->mii_data);

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val = (unsigned short)readl(&eth->mii_data);

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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,

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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,

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regaddr, val);

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regaddr, val);

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return val;

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return val;

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}

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}

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static void fec_mii_setspeed(struct ethernet_regs *eth)

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static void fec_mii_setspeed(struct ethernet_regs *eth)

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{

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{

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/*

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/*

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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock

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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock

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* and do not drop the Preamble.

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* and do not drop the Preamble.

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*

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*

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* The i.MX28 and i.MX6 types have another field in the MSCR (aka

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* The i.MX28 and i.MX6 types have another field in the MSCR (aka

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* MII_SPEED) register that defines the MDIO output hold time. Earlier

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* MII_SPEED) register that defines the MDIO output hold time. Earlier

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* versions are RAZ there, so just ignore the difference and write the

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* versions are RAZ there, so just ignore the difference and write the

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* register always.

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* register always.

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* The minimal hold time according to IEE802.3 (clause 22) is 10 ns.

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* The minimal hold time according to IEE802.3 (clause 22) is 10 ns.

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* HOLDTIME + 1 is the number of clk cycles the fec is holding the

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* HOLDTIME + 1 is the number of clk cycles the fec is holding the

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* output.

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* output.

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* The HOLDTIME bitfield takes values between 0 and 7 (inclusive).

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* The HOLDTIME bitfield takes values between 0 and 7 (inclusive).

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* Given that ceil(clkrate / 5000000) <= 64, the calculation for

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* Given that ceil(clkrate / 5000000) <= 64, the calculation for

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* holdtime cannot result in a value greater than 3.

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* holdtime cannot result in a value greater than 3.

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*/

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*/

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u32 pclk = imx_get_fecclk();

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u32 pclk = imx_get_fecclk();

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u32 speed = DIV_ROUND_UP(pclk, 5000000);

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u32 speed = DIV_ROUND_UP(pclk, 5000000);

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u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;

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u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;

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#ifdef FEC_QUIRK_ENET_MAC

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#ifdef FEC_QUIRK_ENET_MAC

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speed--;

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speed--;

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#endif

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#endif

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writel(speed << 1 | hold << 8, &eth->mii_speed);

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writel(speed << 1 | hold << 8, &eth->mii_speed);

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debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));

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debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));

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}

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}

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static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,

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static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,

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uint8_t regaddr, uint16_t data)

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uint8_t regaddr, uint16_t data)

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{

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{

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uint32_t reg; /* convenient holder for the PHY register */

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uint32_t reg; /* convenient holder for the PHY register */

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uint32_t phy; /* convenient holder for the PHY */

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uint32_t phy; /* convenient holder for the PHY */

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uint32_t start;

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uint32_t start;

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reg = regaddr << FEC_MII_DATA_RA_SHIFT;

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reg = regaddr << FEC_MII_DATA_RA_SHIFT;

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phy = phyaddr << FEC_MII_DATA_PA_SHIFT;

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phy = phyaddr << FEC_MII_DATA_PA_SHIFT;

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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |

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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |

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FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);

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FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);

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/* wait for the MII interrupt */

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/* wait for the MII interrupt */

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start = get_timer(0);

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start = get_timer(0);

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while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {

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while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {

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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {

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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {

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printf("Write MDIO failed...\n");

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printf("Write MDIO failed...\n");

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return -1;

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return -1;

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}

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}

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}

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}

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/* clear MII interrupt bit */

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/* clear MII interrupt bit */

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writel(FEC_IEVENT_MII, &eth->ievent);

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writel(FEC_IEVENT_MII, &eth->ievent);

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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,

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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,

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regaddr, data);

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regaddr, data);

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return 0;

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return 0;

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}

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}

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static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,

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static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,

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int regaddr)

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int regaddr)

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{

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{

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return fec_mdio_read(bus->priv, phyaddr, regaddr);

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return fec_mdio_read(bus->priv, phyaddr, regaddr);

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}

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}

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static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,

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static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,

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int regaddr, u16 data)

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int regaddr, u16 data)

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{

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{

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return fec_mdio_write(bus->priv, phyaddr, regaddr, data);

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return fec_mdio_write(bus->priv, phyaddr, regaddr, data);

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}

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}

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#ifndef CONFIG_PHYLIB

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#ifndef CONFIG_PHYLIB

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static int miiphy_restart_aneg(struct eth_device *dev)

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static int miiphy_restart_aneg(struct eth_device *dev)

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{

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{

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int ret = 0;

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int ret = 0;

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#if !defined(CONFIG_FEC_MXC_NO_ANEG)

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#if !defined(CONFIG_FEC_MXC_NO_ANEG)

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struct fec_priv *fec = (struct fec_priv *)dev->priv;

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struct fec_priv *fec = (struct fec_priv *)dev->priv;

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struct ethernet_regs *eth = fec->bus->priv;

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struct ethernet_regs *eth = fec->bus->priv;

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/*

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/*

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* Wake up from sleep if necessary

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* Wake up from sleep if necessary

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* Reset PHY, then delay 300ns

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* Reset PHY, then delay 300ns

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*/

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*/

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#ifdef CONFIG_MX27

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#ifdef CONFIG_MX27

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fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);

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fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);

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#endif

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#endif

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fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);

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fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);

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udelay(1000);

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udelay(1000);

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/* Set the auto-negotiation advertisement register bits */

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/* Set the auto-negotiation advertisement register bits */

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fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,

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fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,

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LPA_100FULL | LPA_100HALF | LPA_10FULL |

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LPA_100FULL | LPA_100HALF | LPA_10FULL |

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LPA_10HALF | PHY_ANLPAR_PSB_802_3);

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LPA_10HALF | PHY_ANLPAR_PSB_802_3);

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fec_mdio_write(eth, fec->phy_id, MII_BMCR,

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fec_mdio_write(eth, fec->phy_id, MII_BMCR,

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BMCR_ANENABLE | BMCR_ANRESTART);

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BMCR_ANENABLE | BMCR_ANRESTART);

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if (fec->mii_postcall)

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if (fec->mii_postcall)

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ret = fec->mii_postcall(fec->phy_id);

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ret = fec->mii_postcall(fec->phy_id);

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#endif

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#endif

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return ret;

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return ret;

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}

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}

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#ifndef CONFIG_FEC_FIXED_SPEED

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#ifndef CONFIG_FEC_FIXED_SPEED

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static int miiphy_wait_aneg(struct eth_device *dev)

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static int miiphy_wait_aneg(struct eth_device *dev)

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{

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{

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uint32_t start;

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uint32_t start;

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int status;

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int status;

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struct fec_priv *fec = (struct fec_priv *)dev->priv;

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struct fec_priv *fec = (struct fec_priv *)dev->priv;

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struct ethernet_regs *eth = fec->bus->priv;

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struct ethernet_regs *eth = fec->bus->priv;

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/* Wait for AN completion */

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/* Wait for AN completion */

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start = get_timer(0);

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start = get_timer(0);

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do {

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do {

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if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {

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if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {

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printf("%s: Autonegotiation timeout\n", dev->name);

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printf("%s: Autonegotiation timeout\n", dev->name);

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return -1;

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return -1;

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}

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}

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status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);

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status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);

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if (status < 0) {

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if (status < 0) {

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printf("%s: Autonegotiation failed. status: %d\n",

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printf("%s: Autonegotiation failed. status: %d\n",

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dev->name, status);

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dev->name, status);

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return -1;

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return -1;

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}

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}

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} while (!(status & BMSR_LSTATUS));

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} while (!(status & BMSR_LSTATUS));

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return 0;

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return 0;

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}

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}

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#endif /* CONFIG_FEC_FIXED_SPEED */

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#endif /* CONFIG_FEC_FIXED_SPEED */

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#endif

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#endif

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static int fec_rx_task_enable(struct fec_priv *fec)

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static int fec_rx_task_enable(struct fec_priv *fec)

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{

254

{

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writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);

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writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);

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return 0;

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return 0;

257

}

257

}

258

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static int fec_rx_task_disable(struct fec_priv *fec)

259

static int fec_rx_task_disable(struct fec_priv *fec)

260

{

260

{

261

return 0;

261

return 0;

262

}

262

}

263

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static int fec_tx_task_enable(struct fec_priv *fec)

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static int fec_tx_task_enable(struct fec_priv *fec)

265

{

265

{

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writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);

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writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);

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return 0;

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return 0;

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}

268

}

269

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static int fec_tx_task_disable(struct fec_priv *fec)

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static int fec_tx_task_disable(struct fec_priv *fec)

271

{

271

{

272

return 0;

272

return 0;

273

}

273

}

274

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/**

275

/**

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* Initialize receive task's buffer descriptors

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* Initialize receive task's buffer descriptors

277

* @param[in] fec all we know about the device yet

277

* @param[in] fec all we know about the device yet

278

* @param[in] count receive buffer count to be allocated

278

* @param[in] count receive buffer count to be allocated

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* @param[in] dsize desired size of each receive buffer

279

* @param[in] dsize desired size of each receive buffer

280

* @return 0 on success

280

* @return 0 on success

281

*

281

*

282

* Init all RX descriptors to default values.

282

* Init all RX descriptors to default values.

283

*/

283

*/

284

static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)

284

static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)

285

{

285

{

286

uint32_t size;

286

uint32_t size;

287

ulong data;

287

ulong data;

288

int i;

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int i;

289

290

/*

290

/*

291

* Reload the RX descriptors with default values and wipe

291

* Reload the RX descriptors with default values and wipe

292

* the RX buffers.

292

* the RX buffers.

293

*/

293

*/

294

size = roundup(dsize, ARCH_DMA_MINALIGN);

294

size = roundup(dsize, ARCH_DMA_MINALIGN);

295

for (i = 0; i < count; i++) {

295

for (i = 0; i < count; i++) {

296

data = fec->rbd_base[i].data_pointer;

296

data = fec->rbd_base[i].data_pointer;

297

memset((void *)data, 0, dsize);

297

memset((void *)data, 0, dsize);

298

flush_dcache_range(data, data + size);

298

flush_dcache_range(data, data + size);

299

300

fec->rbd_base[i].status = FEC_RBD_EMPTY;

300

fec->rbd_base[i].status = FEC_RBD_EMPTY;

301

fec->rbd_base[i].data_length = 0;

301

fec->rbd_base[i].data_length = 0;

302

}

302

}

303

304

/* Mark the last RBD to close the ring. */

304

/* Mark the last RBD to close the ring. */

305

fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;

305

fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;

306

fec->rbd_index = 0;

306

fec->rbd_index = 0;

307

308

flush_dcache_range((ulong)fec->rbd_base,

308

flush_dcache_range((ulong)fec->rbd_base,

309

(ulong)fec->rbd_base + size);

309

(ulong)fec->rbd_base + size);

310

}

310

}

311

312

/**

312

/**

313

* Initialize transmit task's buffer descriptors

313

* Initialize transmit task's buffer descriptors

314

* @param[in] fec all we know about the device yet

314

* @param[in] fec all we know about the device yet

315

*

315

*

316

* Transmit buffers are created externally. We only have to init the BDs here.\n

316

* Transmit buffers are created externally. We only have to init the BDs here.\n

317

* Note: There is a race condition in the hardware. When only one BD is in

317

* Note: There is a race condition in the hardware. When only one BD is in

318

* use it must be marked with the WRAP bit to use it for every transmitt.

318

* use it must be marked with the WRAP bit to use it for every transmitt.

319

* This bit in combination with the READY bit results into double transmit

319

* This bit in combination with the READY bit results into double transmit

320

* of each data buffer. It seems the state machine checks READY earlier then

320

* of each data buffer. It seems the state machine checks READY earlier then

321

* resetting it after the first transfer.

321

* resetting it after the first transfer.

322

* Using two BDs solves this issue.

322

* Using two BDs solves this issue.

323

*/

323

*/

324

static void fec_tbd_init(struct fec_priv *fec)

324

static void fec_tbd_init(struct fec_priv *fec)

325

{

325

{

326

ulong addr = (ulong)fec->tbd_base;

326

ulong addr = (ulong)fec->tbd_base;

327

unsigned size = roundup(2 * sizeof(struct fec_bd),

327

unsigned size = roundup(2 * sizeof(struct fec_bd),

328

ARCH_DMA_MINALIGN);

328

ARCH_DMA_MINALIGN);

329

330

memset(fec->tbd_base, 0, size);

330

memset(fec->tbd_base, 0, size);

331

fec->tbd_base[0].status = 0;

331

fec->tbd_base[0].status = 0;

332

fec->tbd_base[1].status = FEC_TBD_WRAP;

332

fec->tbd_base[1].status = FEC_TBD_WRAP;

333

fec->tbd_index = 0;

333

fec->tbd_index = 0;

334

flush_dcache_range(addr, addr + size);

334

flush_dcache_range(addr, addr + size);

335

}

335

}

336

337

/**

337

/**

338

* Mark the given read buffer descriptor as free

338

* Mark the given read buffer descriptor as free

339

* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0

339

* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0

340

* @param[in] prbd buffer descriptor to mark free again

340

* @param[in] prbd buffer descriptor to mark free again

341

*/

341

*/

342

static void fec_rbd_clean(int last, struct fec_bd *prbd)

342

static void fec_rbd_clean(int last, struct fec_bd *prbd)

343

{

343

{

344

unsigned short flags = FEC_RBD_EMPTY;

344

unsigned short flags = FEC_RBD_EMPTY;

345

if (last)

345

if (last)

346

flags |= FEC_RBD_WRAP;

346

flags |= FEC_RBD_WRAP;

347

writew(flags, &prbd->status);

347

writew(flags, &prbd->status);

348

writew(0, &prbd->data_length);

348

writew(0, &prbd->data_length);

349

}

349

}

350

351

static int fec_get_hwaddr(int dev_id, unsigned char *mac)

351

static int fec_get_hwaddr(int dev_id, unsigned char *mac)

352

{

352

{

353

imx_get_mac_from_fuse(dev_id, mac);

353

imx_get_mac_from_fuse(dev_id, mac);

354

return !is_valid_ethaddr(mac);

354

return !is_valid_ethaddr(mac);

355

}

355

}

356

357

#ifdef CONFIG_DM_ETH

357

#ifdef CONFIG_DM_ETH

358

static int fecmxc_set_hwaddr(struct udevice *dev)

358

static int fecmxc_set_hwaddr(struct udevice *dev)

359

#else

359

#else

360

static int fec_set_hwaddr(struct eth_device *dev)

360

static int fec_set_hwaddr(struct eth_device *dev)

361

#endif

361

#endif

362

{

362

{

363

#ifdef CONFIG_DM_ETH

363

#ifdef CONFIG_DM_ETH

364

struct fec_priv *fec = dev_get_priv(dev);

364

struct fec_priv *fec = dev_get_priv(dev);

365

struct eth_pdata *pdata = dev_get_platdata(dev);

365

struct eth_pdata *pdata = dev_get_platdata(dev);

366

uchar *mac = pdata->enetaddr;

366

uchar *mac = pdata->enetaddr;

367

#else

367

#else

368

uchar *mac = dev->enetaddr;

368

uchar *mac = dev->enetaddr;

369

struct fec_priv *fec = (struct fec_priv *)dev->priv;

369

struct fec_priv *fec = (struct fec_priv *)dev->priv;

370

#endif

370

#endif

371

372

writel(0, &fec->eth->iaddr1);

372

writel(0, &fec->eth->iaddr1);

373

writel(0, &fec->eth->iaddr2);

373

writel(0, &fec->eth->iaddr2);

374

writel(0, &fec->eth->gaddr1);

374

writel(0, &fec->eth->gaddr1);

375

writel(0, &fec->eth->gaddr2);

375

writel(0, &fec->eth->gaddr2);

376

377

/* Set physical address */

377

/* Set physical address */

378

writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],

378

writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],

379

&fec->eth->paddr1);

379

&fec->eth->paddr1);

380

writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);

380

writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);

381

382

return 0;

382

return 0;

383

}

383

}

384

385

/* Do initial configuration of the FEC registers */

385

/* Do initial configuration of the FEC registers */

386

static void fec_reg_setup(struct fec_priv *fec)

386

static void fec_reg_setup(struct fec_priv *fec)

387

{

387

{

388

uint32_t rcntrl;

388

uint32_t rcntrl;

389

390

/* Set interrupt mask register */

390

/* Set interrupt mask register */

391

writel(0x00000000, &fec->eth->imask);

391

writel(0x00000000, &fec->eth->imask);

392

393

/* Clear FEC-Lite interrupt event register(IEVENT) */

393

/* Clear FEC-Lite interrupt event register(IEVENT) */

394

writel(0xffffffff, &fec->eth->ievent);

394

writel(0xffffffff, &fec->eth->ievent);

395

396

/* Set FEC-Lite receive control register(R_CNTRL): */

396

/* Set FEC-Lite receive control register(R_CNTRL): */

397

398

/* Start with frame length = 1518, common for all modes. */

398

/* Start with frame length = 1518, common for all modes. */

399

rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;

399

rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;

400

if (fec->xcv_type != SEVENWIRE) /* xMII modes */

400

if (fec->xcv_type != SEVENWIRE) /* xMII modes */

401

rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;

401

rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;

402

if (fec->xcv_type == RGMII)

402

if (fec->xcv_type == RGMII)

403

rcntrl |= FEC_RCNTRL_RGMII;

403

rcntrl |= FEC_RCNTRL_RGMII;

404

else if (fec->xcv_type == RMII)

404

else if (fec->xcv_type == RMII)

405

rcntrl |= FEC_RCNTRL_RMII;

405

rcntrl |= FEC_RCNTRL_RMII;

406

407

writel(rcntrl, &fec->eth->r_cntrl);

407

writel(rcntrl, &fec->eth->r_cntrl);

408

}

408

}

409

410

/**

410

/**

411

* Start the FEC engine

411

* Start the FEC engine

412

* @param[in] dev Our device to handle

412

* @param[in] dev Our device to handle

413

*/

413

*/

414

#ifdef CONFIG_DM_ETH

414

#ifdef CONFIG_DM_ETH

415

static int fec_open(struct udevice *dev)

415

static int fec_open(struct udevice *dev)

416

#else

416

#else

417

static int fec_open(struct eth_device *edev)

417

static int fec_open(struct eth_device *edev)

418

#endif

418

#endif

419

{

419

{

420

#ifdef CONFIG_DM_ETH

420

#ifdef CONFIG_DM_ETH

421

struct fec_priv *fec = dev_get_priv(dev);

421

struct fec_priv *fec = dev_get_priv(dev);

422

#else

422

#else

423

struct fec_priv *fec = (struct fec_priv *)edev->priv;

423

struct fec_priv *fec = (struct fec_priv *)edev->priv;

424

#endif

424

#endif

425

int speed;

425

int speed;

426

ulong addr, size;

426

ulong addr, size;

427

int i;

427

int i;

428

429

debug("fec_open: fec_open(dev)\n");

429

debug("fec_open: fec_open(dev)\n");

430

/* full-duplex, heartbeat disabled */

430

/* full-duplex, heartbeat disabled */

431

writel(1 << 2, &fec->eth->x_cntrl);

431

writel(1 << 2, &fec->eth->x_cntrl);

432

fec->rbd_index = 0;

432

fec->rbd_index = 0;

433

434

/* Invalidate all descriptors */

434

/* Invalidate all descriptors */

435

for (i = 0; i < FEC_RBD_NUM - 1; i++)

435

for (i = 0; i < FEC_RBD_NUM - 1; i++)

436

fec_rbd_clean(0, &fec->rbd_base[i]);

436

fec_rbd_clean(0, &fec->rbd_base[i]);

437

fec_rbd_clean(1, &fec->rbd_base[i]);

437

fec_rbd_clean(1, &fec->rbd_base[i]);

438

439

/* Flush the descriptors into RAM */

439

/* Flush the descriptors into RAM */

440

size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),

440

size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),

441

ARCH_DMA_MINALIGN);

441

ARCH_DMA_MINALIGN);

442

addr = (ulong)fec->rbd_base;

442

addr = (ulong)fec->rbd_base;

443

flush_dcache_range(addr, addr + size);

443

flush_dcache_range(addr, addr + size);

444

445

#ifdef FEC_QUIRK_ENET_MAC

445

#ifdef FEC_QUIRK_ENET_MAC

446

/* Enable ENET HW endian SWAP */

446

/* Enable ENET HW endian SWAP */

447

writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,

447

writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,

448

&fec->eth->ecntrl);

448

&fec->eth->ecntrl);

449

/* Enable ENET store and forward mode */

449

/* Enable ENET store and forward mode */

450

writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,

450

writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,

451

&fec->eth->x_wmrk);

451

&fec->eth->x_wmrk);

452

#endif

452

#endif

453

/* Enable FEC-Lite controller */

453

/* Enable FEC-Lite controller */

454

writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,

454

writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,

455

&fec->eth->ecntrl);

455

&fec->eth->ecntrl);

456

457

#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)

457

#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)

458

udelay(100);

458

udelay(100);

459

460

/* setup the MII gasket for RMII mode */

460

/* setup the MII gasket for RMII mode */

461

/* disable the gasket */

461

/* disable the gasket */

462

writew(0, &fec->eth->miigsk_enr);

462

writew(0, &fec->eth->miigsk_enr);

463

464

/* wait for the gasket to be disabled */

464

/* wait for the gasket to be disabled */

465

while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)

465

while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)

466

udelay(2);

466

udelay(2);

467

468

/* configure gasket for RMII, 50 MHz, no loopback, and no echo */

468

/* configure gasket for RMII, 50 MHz, no loopback, and no echo */

469

writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);

469

writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);

470

471

/* re-enable the gasket */

471

/* re-enable the gasket */

472

writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);

472

writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);

473

474

/* wait until MII gasket is ready */

474

/* wait until MII gasket is ready */

475

int max_loops = 10;

475

int max_loops = 10;

476

while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {

476

while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {

477

if (--max_loops <= 0) {

477

if (--max_loops <= 0) {

478

printf("WAIT for MII Gasket ready timed out\n");

478

printf("WAIT for MII Gasket ready timed out\n");

479

break;

479

break;

480

}

480

}

481

}

481

}

482

#endif

482

#endif

483

484

#ifdef CONFIG_PHYLIB

484

#ifdef CONFIG_PHYLIB

485

{

485

{

486

/* Start up the PHY */

486

/* Start up the PHY */

487

int ret = phy_startup(fec->phydev);

487

int ret = phy_startup(fec->phydev);

488

489

if (ret) {

489

if (ret) {

490

printf("Could not initialize PHY %s\n",

490

printf("Could not initialize PHY %s\n",

491

fec->phydev->dev->name);

491

fec->phydev->dev->name);

492

return ret;

492

return ret;

493

}

493

}

494

speed = fec->phydev->speed;

494

speed = fec->phydev->speed;

495

}

495

}

496

#elif CONFIG_FEC_FIXED_SPEED

496

#elif CONFIG_FEC_FIXED_SPEED

497

speed = CONFIG_FEC_FIXED_SPEED;

497

speed = CONFIG_FEC_FIXED_SPEED;

498

#else

498

#else

499

miiphy_wait_aneg(edev);

499

miiphy_wait_aneg(edev);

500

speed = miiphy_speed(edev->name, fec->phy_id);

500

speed = miiphy_speed(edev->name, fec->phy_id);

501

miiphy_duplex(edev->name, fec->phy_id);

501

miiphy_duplex(edev->name, fec->phy_id);

502

#endif

502

#endif

503

504

#ifdef FEC_QUIRK_ENET_MAC

504

#ifdef FEC_QUIRK_ENET_MAC

505

{

505

{

506

u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;

506

u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;

507

u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;

507

u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;

508

if (speed == _1000BASET)

508

if (speed == _1000BASET)

509

ecr |= FEC_ECNTRL_SPEED;

509

ecr |= FEC_ECNTRL_SPEED;

510

else if (speed != _100BASET)

510

else if (speed != _100BASET)

511

rcr |= FEC_RCNTRL_RMII_10T;

511

rcr |= FEC_RCNTRL_RMII_10T;

512

writel(ecr, &fec->eth->ecntrl);

512

writel(ecr, &fec->eth->ecntrl);

513

writel(rcr, &fec->eth->r_cntrl);

513

writel(rcr, &fec->eth->r_cntrl);

514

}

514

}

515

#endif

515

#endif

516

debug("%s:Speed=%i\n", __func__, speed);

516

debug("%s:Speed=%i\n", __func__, speed);

517

518

/* Enable SmartDMA receive task */

518

/* Enable SmartDMA receive task */

519

fec_rx_task_enable(fec);

519

fec_rx_task_enable(fec);

520

521

udelay(100000);

521

udelay(100000);

522

return 0;

522

return 0;

523

}

523

}

524

525

#ifdef CONFIG_DM_ETH

525

#ifdef CONFIG_DM_ETH

526

static int fecmxc_init(struct udevice *dev)

526

static int fecmxc_init(struct udevice *dev)

527

#else

527

#else

528

static int fec_init(struct eth_device *dev, bd_t *bd)

528

static int fec_init(struct eth_device *dev, bd_t *bd)

529

#endif

529

#endif

530

{

530

{

531

#ifdef CONFIG_DM_ETH

531

#ifdef CONFIG_DM_ETH

532

struct fec_priv *fec = dev_get_priv(dev);

532

struct fec_priv *fec = dev_get_priv(dev);

533

#else

533

#else

534

struct fec_priv *fec = (struct fec_priv *)dev->priv;

534

struct fec_priv *fec = (struct fec_priv *)dev->priv;

535

#endif

535

#endif

536

u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;

536

u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;

537

u8 *i;

537

u8 *i;

538

ulong addr;

538

ulong addr;

539

540

/* Initialize MAC address */

540

/* Initialize MAC address */

541

#ifdef CONFIG_DM_ETH

541

#ifdef CONFIG_DM_ETH

542

fecmxc_set_hwaddr(dev);

542

fecmxc_set_hwaddr(dev);

543

#else

543

#else

544

fec_set_hwaddr(dev);

544

fec_set_hwaddr(dev);

545

#endif

545

#endif

546

547

/* Setup transmit descriptors, there are two in total. */

547

/* Setup transmit descriptors, there are two in total. */

548

fec_tbd_init(fec);

548

fec_tbd_init(fec);

549

550

/* Setup receive descriptors. */

550

/* Setup receive descriptors. */

551

fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);

551

fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);

552

553

fec_reg_setup(fec);

553

fec_reg_setup(fec);

554

555

if (fec->xcv_type != SEVENWIRE)

555

if (fec->xcv_type != SEVENWIRE)

556

fec_mii_setspeed(fec->bus->priv);

556

fec_mii_setspeed(fec->bus->priv);

557

558

/* Set Opcode/Pause Duration Register */

558

/* Set Opcode/Pause Duration Register */

559

writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */

559

writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */

560

writel(0x2, &fec->eth->x_wmrk);

560

writel(0x2, &fec->eth->x_wmrk);

561

562

/* Set multicast address filter */

562

/* Set multicast address filter */

563

writel(0x00000000, &fec->eth->gaddr1);

563

writel(0x00000000, &fec->eth->gaddr1);

564

writel(0x00000000, &fec->eth->gaddr2);

564

writel(0x00000000, &fec->eth->gaddr2);

565

566

/* Do not access reserved register */

566

/* Do not access reserved register */

567

if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {

567

if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {

568

/* clear MIB RAM */

568

/* clear MIB RAM */

569

for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)

569

for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)

570

writel(0, i);

570

writel(0, i);

571

572

/* FIFO receive start register */

572

/* FIFO receive start register */

573

writel(0x520, &fec->eth->r_fstart);

573

writel(0x520, &fec->eth->r_fstart);

574

}

574

}

575

576

/* size and address of each buffer */

576

/* size and address of each buffer */

577

writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);

577

writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);

578

579

addr = (ulong)fec->tbd_base;

579

addr = (ulong)fec->tbd_base;

580

writel((uint32_t)addr, &fec->eth->etdsr);

580

writel((uint32_t)addr, &fec->eth->etdsr);

581

582

addr = (ulong)fec->rbd_base;

582

addr = (ulong)fec->rbd_base;

583

writel((uint32_t)addr, &fec->eth->erdsr);

583

writel((uint32_t)addr, &fec->eth->erdsr);

584

585

#ifndef CONFIG_PHYLIB

585

#ifndef CONFIG_PHYLIB

586

if (fec->xcv_type != SEVENWIRE)

586

if (fec->xcv_type != SEVENWIRE)

587

miiphy_restart_aneg(dev);

587

miiphy_restart_aneg(dev);

588

#endif

588

#endif

589

fec_open(dev);

589

fec_open(dev);

590

return 0;

590

return 0;

591

}

591

}

592

593

/**

593

/**

594

* Halt the FEC engine

594

* Halt the FEC engine

595

* @param[in] dev Our device to handle

595

* @param[in] dev Our device to handle

596

*/

596

*/

597

#ifdef CONFIG_DM_ETH

597

#ifdef CONFIG_DM_ETH

598

static void fecmxc_halt(struct udevice *dev)

598

static void fecmxc_halt(struct udevice *dev)

599

#else

599

#else

600

static void fec_halt(struct eth_device *dev)

600

static void fec_halt(struct eth_device *dev)

601

#endif

601

#endif

602

{

602

{

603

#ifdef CONFIG_DM_ETH

603

#ifdef CONFIG_DM_ETH

604

struct fec_priv *fec = dev_get_priv(dev);

604

struct fec_priv *fec = dev_get_priv(dev);

605

#else

605

#else

606

struct fec_priv *fec = (struct fec_priv *)dev->priv;

606

struct fec_priv *fec = (struct fec_priv *)dev->priv;

607

#endif

607

#endif

608

int counter = 0xffff;

608

int counter = 0xffff;

609

610

/* issue graceful stop command to the FEC transmitter if necessary */

610

/* issue graceful stop command to the FEC transmitter if necessary */

611

writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),

611

writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),

612

&fec->eth->x_cntrl);

612

&fec->eth->x_cntrl);

613

614

debug("eth_halt: wait for stop regs\n");

614

debug("eth_halt: wait for stop regs\n");

615

/* wait for graceful stop to register */

615

/* wait for graceful stop to register */

616

while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))

616

while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))

617

udelay(1);

617

udelay(1);

618

619

/* Disable SmartDMA tasks */

619

/* Disable SmartDMA tasks */

620

fec_tx_task_disable(fec);

620

fec_tx_task_disable(fec);

621

fec_rx_task_disable(fec);

621

fec_rx_task_disable(fec);

622

623

/*

623

/*

624

* Disable the Ethernet Controller

624

* Disable the Ethernet Controller

625

* Note: this will also reset the BD index counter!

625

* Note: this will also reset the BD index counter!

626

*/

626

*/

627

writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,

627

writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,

628

&fec->eth->ecntrl);

628

&fec->eth->ecntrl);

629

fec->rbd_index = 0;

629

fec->rbd_index = 0;

630

fec->tbd_index = 0;

630

fec->tbd_index = 0;

631

debug("eth_halt: done\n");

631

debug("eth_halt: done\n");

632

}

632

}

633

634

/**

634

/**

635

* Transmit one frame

635

* Transmit one frame

636

* @param[in] dev Our ethernet device to handle

636

* @param[in] dev Our ethernet device to handle

637

* @param[in] packet Pointer to the data to be transmitted

637

* @param[in] packet Pointer to the data to be transmitted

638

* @param[in] length Data count in bytes

638

* @param[in] length Data count in bytes

639

* @return 0 on success

639

* @return 0 on success

640

*/

640

*/

641

#ifdef CONFIG_DM_ETH

641

#ifdef CONFIG_DM_ETH

642

static int fecmxc_send(struct udevice *dev, void *packet, int length)

642

static int fecmxc_send(struct udevice *dev, void *packet, int length)

643

#else

643

#else

644

static int fec_send(struct eth_device *dev, void *packet, int length)

644

static int fec_send(struct eth_device *dev, void *packet, int length)

645

#endif

645

#endif

646

{

646

{

647

unsigned int status;

647

unsigned int status;

648

u32 size;

648

u32 size;

649

ulong addr, end;

649

ulong addr, end;

650

int timeout = FEC_XFER_TIMEOUT;

650

int timeout = FEC_XFER_TIMEOUT;

651

int ret = 0;

651

int ret = 0;

652

653

/*

653

/*

654

* This routine transmits one frame. This routine only accepts

654

* This routine transmits one frame. This routine only accepts

655

* 6-byte Ethernet addresses.

655

* 6-byte Ethernet addresses.

656

*/

656

*/

657

#ifdef CONFIG_DM_ETH

657

#ifdef CONFIG_DM_ETH

658

struct fec_priv *fec = dev_get_priv(dev);

658

struct fec_priv *fec = dev_get_priv(dev);

659

#else

659

#else

660

struct fec_priv *fec = (struct fec_priv *)dev->priv;

660

struct fec_priv *fec = (struct fec_priv *)dev->priv;

661

#endif

661

#endif

662

663

/*

663

/*

664

* Check for valid length of data.

664

* Check for valid length of data.

665

*/

665

*/

666

if ((length > 1500) || (length <= 0)) {

666

if ((length > 1500) || (length <= 0)) {

667

printf("Payload (%d) too large\n", length);

667

printf("Payload (%d) too large\n", length);

668

return -1;

668

return -1;

669

}

669

}

670

671

/*

671

/*

672

* Setup the transmit buffer. We are always using the first buffer for

672

* Setup the transmit buffer. We are always using the first buffer for

673

* transmission, the second will be empty and only used to stop the DMA

673

* transmission, the second will be empty and only used to stop the DMA

674

* engine. We also flush the packet to RAM here to avoid cache trouble.

674

* engine. We also flush the packet to RAM here to avoid cache trouble.

675

*/

675

*/

676

#ifdef CONFIG_FEC_MXC_SWAP_PACKET

676

#ifdef CONFIG_FEC_MXC_SWAP_PACKET

677

swap_packet((uint32_t *)packet, length);

677

swap_packet((uint32_t *)packet, length);

678

#endif

678

#endif

679

680

addr = (ulong)packet;

680

addr = (ulong)packet;

681

end = roundup(addr + length, ARCH_DMA_MINALIGN);

681

end = roundup(addr + length, ARCH_DMA_MINALIGN);

682

addr &= ~(ARCH_DMA_MINALIGN - 1);

682

addr &= ~(ARCH_DMA_MINALIGN - 1);

683

flush_dcache_range(addr, end);

683

flush_dcache_range(addr, end);

684

685

writew(length, &fec->tbd_base[fec->tbd_index].data_length);

685

writew(length, &fec->tbd_base[fec->tbd_index].data_length);

686

writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);

686

writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);

687

688

/*

688

/*

689

* update BD's status now

689

* update BD's status now

690

* This block:

690

* This block:

691

* - is always the last in a chain (means no chain)

691

* - is always the last in a chain (means no chain)

692

* - should transmitt the CRC

692

* - should transmitt the CRC

693

* - might be the last BD in the list, so the address counter should

693

* - might be the last BD in the list, so the address counter should

694

* wrap (-> keep the WRAP flag)

694

* wrap (-> keep the WRAP flag)

695

*/

695

*/

696

status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;

696

status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;

697

status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;

697

status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;

698

writew(status, &fec->tbd_base[fec->tbd_index].status);

698

writew(status, &fec->tbd_base[fec->tbd_index].status);

699

700

/*

700

/*

701

* Flush data cache. This code flushes both TX descriptors to RAM.

701

* Flush data cache. This code flushes both TX descriptors to RAM.

702

* After this code, the descriptors will be safely in RAM and we

702

* After this code, the descriptors will be safely in RAM and we

703

* can start DMA.

703

* can start DMA.

704

*/

704

*/

705

size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);

705

size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);

706

addr = (ulong)fec->tbd_base;

706

addr = (ulong)fec->tbd_base;

707

flush_dcache_range(addr, addr + size);

707

flush_dcache_range(addr, addr + size);

708

709

/*

709

/*

710

* Below we read the DMA descriptor's last four bytes back from the

710

* Below we read the DMA descriptor's last four bytes back from the

711

* DRAM. This is important in order to make sure that all WRITE

711

* DRAM. This is important in order to make sure that all WRITE

712

* operations on the bus that were triggered by previous cache FLUSH

712

* operations on the bus that were triggered by previous cache FLUSH

713

* have completed.

713

* have completed.

714

*

714

*

715

* Otherwise, on MX28, it is possible to observe a corruption of the

715

* Otherwise, on MX28, it is possible to observe a corruption of the

716

* DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM

716

* DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM

717

* for the bus structure of MX28. The scenario is as follows:

717

* for the bus structure of MX28. The scenario is as follows:

718

*

718

*

719

* 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going

719

* 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going

720

* to DRAM due to flush_dcache_range()

720

* to DRAM due to flush_dcache_range()

721

* 2) ARM core writes the FEC registers via AHB_ARB2

721

* 2) ARM core writes the FEC registers via AHB_ARB2

722

* 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3

722

* 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3

723

*

723

*

724

* Note that 2) does sometimes finish before 1) due to reordering of

724

* Note that 2) does sometimes finish before 1) due to reordering of

725

* WRITE accesses on the AHB bus, therefore triggering 3) before the

725

* WRITE accesses on the AHB bus, therefore triggering 3) before the

726

* DMA descriptor is fully written into DRAM. This results in occasional

726

* DMA descriptor is fully written into DRAM. This results in occasional

727

* corruption of the DMA descriptor.

727

* corruption of the DMA descriptor.

728

*/

728

*/

729

readl(addr + size - 4);

729

readl(addr + size - 4);

730

731

/* Enable SmartDMA transmit task */

731

/* Enable SmartDMA transmit task */

732

fec_tx_task_enable(fec);

732

fec_tx_task_enable(fec);

733

734

/*

734

/*

735

* Wait until frame is sent. On each turn of the wait cycle, we must

735

* Wait until frame is sent. On each turn of the wait cycle, we must

736

* invalidate data cache to see what's really in RAM. Also, we need

736

* invalidate data cache to see what's really in RAM. Also, we need

737

* barrier here.

737

* barrier here.

738

*/

738

*/

739

while (--timeout) {

739

while (--timeout) {

740

if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))

740

if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))

741

break;

741

break;

742

}

742

}

743

744

if (!timeout) {

744

if (!timeout) {

745

ret = -EINVAL;

745

ret = -EINVAL;

746

goto out;

746

goto out;

747

}

747

}

748

749

/*

749

/*

750

* The TDAR bit is cleared when the descriptors are all out from TX

750

* The TDAR bit is cleared when the descriptors are all out from TX

751

* but on mx6solox we noticed that the READY bit is still not cleared

751

* but on mx6solox we noticed that the READY bit is still not cleared

752

* right after TDAR.

752

* right after TDAR.

753

* These are two distinct signals, and in IC simulation, we found that

753

* These are two distinct signals, and in IC simulation, we found that

754

* TDAR always gets cleared prior than the READY bit of last BD becomes

754

* TDAR always gets cleared prior than the READY bit of last BD becomes

755

* cleared.

755

* cleared.

756

* In mx6solox, we use a later version of FEC IP. It looks like that

756

* In mx6solox, we use a later version of FEC IP. It looks like that

757

* this intrinsic behaviour of TDAR bit has changed in this newer FEC

757

* this intrinsic behaviour of TDAR bit has changed in this newer FEC

758

* version.

758

* version.

759

*

759

*

760

* Fix this by polling the READY bit of BD after the TDAR polling,

760

* Fix this by polling the READY bit of BD after the TDAR polling,

761

* which covers the mx6solox case and does not harm the other SoCs.

761

* which covers the mx6solox case and does not harm the other SoCs.

762

*/

762

*/

763

timeout = FEC_XFER_TIMEOUT;

763

timeout = FEC_XFER_TIMEOUT;

764

while (--timeout) {

764

while (--timeout) {

765

invalidate_dcache_range(addr, addr + size);

765

invalidate_dcache_range(addr, addr + size);

766

if (!(readw(&fec->tbd_base[fec->tbd_index].status) &

766

if (!(readw(&fec->tbd_base[fec->tbd_index].status) &

767

FEC_TBD_READY))

767

FEC_TBD_READY))

768

break;

768

break;

769

}

769

}

770

771

if (!timeout)

771

if (!timeout)

772

ret = -EINVAL;

772

ret = -EINVAL;

773

774

out:

774

out:

775

debug("fec_send: status 0x%x index %d ret %i\n",

775

debug("fec_send: status 0x%x index %d ret %i\n",

776

readw(&fec->tbd_base[fec->tbd_index].status),

776

readw(&fec->tbd_base[fec->tbd_index].status),

777

fec->tbd_index, ret);

777

fec->tbd_index, ret);

778

/* for next transmission use the other buffer */

778

/* for next transmission use the other buffer */

779

if (fec->tbd_index)

779

if (fec->tbd_index)

780

fec->tbd_index = 0;

780

fec->tbd_index = 0;

781

else

781

else

782

fec->tbd_index = 1;

782

fec->tbd_index = 1;

783

784

return ret;

784

return ret;

785

}

785

}

786

787

/**

787

/**

788

* Pull one frame from the card

788

* Pull one frame from the card

789

* @param[in] dev Our ethernet device to handle

789

* @param[in] dev Our ethernet device to handle

790

* @return Length of packet read

790

* @return Length of packet read

791

*/

791

*/

792

#ifdef CONFIG_DM_ETH

792

#ifdef CONFIG_DM_ETH

793

static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)

793

static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)

794

#else

794

#else

795

static int fec_recv(struct eth_device *dev)

795

static int fec_recv(struct eth_device *dev)

796

#endif

796

#endif

797

{

797

{

798

#ifdef CONFIG_DM_ETH

798

#ifdef CONFIG_DM_ETH

799

struct fec_priv *fec = dev_get_priv(dev);

799

struct fec_priv *fec = dev_get_priv(dev);

800

#else

800

#else

801

struct fec_priv *fec = (struct fec_priv *)dev->priv;

801

struct fec_priv *fec = (struct fec_priv *)dev->priv;

802

#endif

802

#endif

803

struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];

803

struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];

804

unsigned long ievent;

804

unsigned long ievent;

805

int frame_length, len = 0;

805

int frame_length, len = 0;

806

uint16_t bd_status;

806

uint16_t bd_status;

807

ulong addr, size, end;

807

ulong addr, size, end;

808

int i;

808

int i;

809

810

#ifdef CONFIG_DM_ETH

810

#ifdef CONFIG_DM_ETH

811

*packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);

811

*packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);

812

if (*packetp == 0) {

812

if (*packetp == 0) {

813

printf("%s: error allocating packetp\n", __func__);

813

printf("%s: error allocating packetp\n", __func__);

814

return -ENOMEM;

814

return -ENOMEM;

815

}

815

}

816

#else

816

#else

817

ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);

817

ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);

818

#endif

818

#endif

819

820

/* Check if any critical events have happened */

820

/* Check if any critical events have happened */

821

ievent = readl(&fec->eth->ievent);

821

ievent = readl(&fec->eth->ievent);

822

writel(ievent, &fec->eth->ievent);

822

writel(ievent, &fec->eth->ievent);

823

debug("fec_recv: ievent 0x%lx\n", ievent);

823

debug("fec_recv: ievent 0x%lx\n", ievent);

824

if (ievent & FEC_IEVENT_BABR) {

824

if (ievent & FEC_IEVENT_BABR) {

825

#ifdef CONFIG_DM_ETH

825

#ifdef CONFIG_DM_ETH

826

fecmxc_halt(dev);

826

fecmxc_halt(dev);

827

fecmxc_init(dev);

827

fecmxc_init(dev);

828

#else

828

#else

829

fec_halt(dev);

829

fec_halt(dev);

830

fec_init(dev, fec->bd);

830

fec_init(dev, fec->bd);

831

#endif

831

#endif

832

printf("some error: 0x%08lx\n", ievent);

832

printf("some error: 0x%08lx\n", ievent);

833

return 0;

833

return 0;

834

}

834

}

835

if (ievent & FEC_IEVENT_HBERR) {

835

if (ievent & FEC_IEVENT_HBERR) {

836

/* Heartbeat error */

836

/* Heartbeat error */

837

writel(0x00000001 | readl(&fec->eth->x_cntrl),

837

writel(0x00000001 | readl(&fec->eth->x_cntrl),

838

&fec->eth->x_cntrl);

838

&fec->eth->x_cntrl);

839

}

839

}

840

if (ievent & FEC_IEVENT_GRA) {

840

if (ievent & FEC_IEVENT_GRA) {

841

/* Graceful stop complete */

841

/* Graceful stop complete */

842

if (readl(&fec->eth->x_cntrl) & 0x00000001) {

842

if (readl(&fec->eth->x_cntrl) & 0x00000001) {

843

#ifdef CONFIG_DM_ETH

843

#ifdef CONFIG_DM_ETH

844

fecmxc_halt(dev);

844

fecmxc_halt(dev);

845

#else

845

#else

846

fec_halt(dev);

846

fec_halt(dev);

847

#endif

847

#endif

848

writel(~0x00000001 & readl(&fec->eth->x_cntrl),

848

writel(~0x00000001 & readl(&fec->eth->x_cntrl),

849

&fec->eth->x_cntrl);

849

&fec->eth->x_cntrl);

850

#ifdef CONFIG_DM_ETH

850

#ifdef CONFIG_DM_ETH

851

fecmxc_init(dev);

851

fecmxc_init(dev);

852

#else

852

#else

853

fec_init(dev, fec->bd);

853

fec_init(dev, fec->bd);

854

#endif

854

#endif

855

}

855

}

856

}

856

}

857

858

/*

858

/*

859

* Read the buffer status. Before the status can be read, the data cache

859

* Read the buffer status. Before the status can be read, the data cache

860

* must be invalidated, because the data in RAM might have been changed

860

* must be invalidated, because the data in RAM might have been changed

861

* by DMA. The descriptors are properly aligned to cachelines so there's

861

* by DMA. The descriptors are properly aligned to cachelines so there's

862

* no need to worry they'd overlap.

862

* no need to worry they'd overlap.

863

*

863

*

864

* WARNING: By invalidating the descriptor here, we also invalidate

864

* WARNING: By invalidating the descriptor here, we also invalidate

865

* the descriptors surrounding this one. Therefore we can NOT change the

865

* the descriptors surrounding this one. Therefore we can NOT change the

866

* contents of this descriptor nor the surrounding ones. The problem is

866

* contents of this descriptor nor the surrounding ones. The problem is

867

* that in order to mark the descriptor as processed, we need to change

867

* that in order to mark the descriptor as processed, we need to change

868

* the descriptor. The solution is to mark the whole cache line when all

868

* the descriptor. The solution is to mark the whole cache line when all

869

* descriptors in the cache line are processed.

869

* descriptors in the cache line are processed.

870

*/

870

*/

871

addr = (ulong)rbd;

871

addr = (ulong)rbd;

872

addr &= ~(ARCH_DMA_MINALIGN - 1);

872

addr &= ~(ARCH_DMA_MINALIGN - 1);

873

size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);

873

size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);

874

invalidate_dcache_range(addr, addr + size);

874

invalidate_dcache_range(addr, addr + size);

875

876

bd_status = readw(&rbd->status);

876

bd_status = readw(&rbd->status);

877

debug("fec_recv: status 0x%x\n", bd_status);

877

debug("fec_recv: status 0x%x\n", bd_status);

878

879

if (!(bd_status & FEC_RBD_EMPTY)) {

879

if (!(bd_status & FEC_RBD_EMPTY)) {

880

if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&

880

if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&

881

((readw(&rbd->data_length) - 4) > 14)) {

881

((readw(&rbd->data_length) - 4) > 14)) {

882

/* Get buffer address and size */

882

/* Get buffer address and size */

883

addr = readl(&rbd->data_pointer);

883

addr = readl(&rbd->data_pointer);

884

frame_length = readw(&rbd->data_length) - 4;

884

frame_length = readw(&rbd->data_length) - 4;

885

/* Invalidate data cache over the buffer */

885

/* Invalidate data cache over the buffer */

886

end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);

886

end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);

887

addr &= ~(ARCH_DMA_MINALIGN - 1);

887

addr &= ~(ARCH_DMA_MINALIGN - 1);

888

invalidate_dcache_range(addr, end);

888

invalidate_dcache_range(addr, end);

889

890

/* Fill the buffer and pass it to upper layers */

890

/* Fill the buffer and pass it to upper layers */

891

#ifdef CONFIG_FEC_MXC_SWAP_PACKET

891

#ifdef CONFIG_FEC_MXC_SWAP_PACKET

892

swap_packet((uint32_t *)addr, frame_length);

892

swap_packet((uint32_t *)addr, frame_length);

893

#endif

893

#endif

894

895

#ifdef CONFIG_DM_ETH

895

#ifdef CONFIG_DM_ETH

896

memcpy(*packetp, (char *)addr, frame_length);

896

memcpy(*packetp, (char *)addr, frame_length);

897

#else

897

#else

898

memcpy(buff, (char *)addr, frame_length);

898

memcpy(buff, (char *)addr, frame_length);

899

net_process_received_packet(buff, frame_length);

899

net_process_received_packet(buff, frame_length);

900

#endif

900

#endif

901

len = frame_length;

901

len = frame_length;

902

} else {

902

} else {

903

if (bd_status & FEC_RBD_ERR)

903

if (bd_status & FEC_RBD_ERR)

904

debug("error frame: 0x%08lx 0x%08x\n",

904

debug("error frame: 0x%08lx 0x%08x\n",

905

addr, bd_status);

905

addr, bd_status);

906

}

906

}

907

908

/*

908

/*

909

* Free the current buffer, restart the engine and move forward

909

* Free the current buffer, restart the engine and move forward

910

* to the next buffer. Here we check if the whole cacheline of

910

* to the next buffer. Here we check if the whole cacheline of

911

* descriptors was already processed and if so, we mark it free

911

* descriptors was already processed and if so, we mark it free

912

* as whole.

912

* as whole.

913

*/

913

*/

914

size = RXDESC_PER_CACHELINE - 1;

914

size = RXDESC_PER_CACHELINE - 1;

915

if ((fec->rbd_index & size) == size) {

915

if ((fec->rbd_index & size) == size) {

916

i = fec->rbd_index - size;

916

i = fec->rbd_index - size;

917

addr = (ulong)&fec->rbd_base[i];

917

addr = (ulong)&fec->rbd_base[i];

918

for (; i <= fec->rbd_index ; i++) {

918

for (; i <= fec->rbd_index ; i++) {

919

fec_rbd_clean(i == (FEC_RBD_NUM - 1),

919

fec_rbd_clean(i == (FEC_RBD_NUM - 1),

920

&fec->rbd_base[i]);

920

&fec->rbd_base[i]);

921

}

921

}

922

flush_dcache_range(addr,

922

flush_dcache_range(addr,

923

addr + ARCH_DMA_MINALIGN);

923

addr + ARCH_DMA_MINALIGN);

924

}

924

}

925

926

fec_rx_task_enable(fec);

926

fec_rx_task_enable(fec);

927

fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;

927

fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;

928

}

928

}

929

debug("fec_recv: stop\n");

929

debug("fec_recv: stop\n");

930

931

return len;

931

return len;

932

}

932

}

933

934

static void fec_set_dev_name(char *dest, int dev_id)

934

static void fec_set_dev_name(char *dest, int dev_id)

935

{

935

{

936

sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);

936

sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);

937

}

937

}

938

939

static int fec_alloc_descs(struct fec_priv *fec)

939

static int fec_alloc_descs(struct fec_priv *fec)

940

{

940

{

941

unsigned int size;

941

unsigned int size;

942

int i;

942

int i;

943

uint8_t *data;

943

uint8_t *data;

944

ulong addr;

944

ulong addr;

945

946

/* Allocate TX descriptors. */

946

/* Allocate TX descriptors. */

947

size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);

947

size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);

948

fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);

948

fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);

949

if (!fec->tbd_base)

949

if (!fec->tbd_base)

950

goto err_tx;

950

goto err_tx;

951

952

/* Allocate RX descriptors. */

952

/* Allocate RX descriptors. */

953

size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);

953

size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);

954

fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);

954

fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);

955

if (!fec->rbd_base)

955

if (!fec->rbd_base)

956

goto err_rx;

956

goto err_rx;

957

958

memset(fec->rbd_base, 0, size);

958

memset(fec->rbd_base, 0, size);

959

960

/* Allocate RX buffers. */

960

/* Allocate RX buffers. */

961

962

/* Maximum RX buffer size. */

962

/* Maximum RX buffer size. */

963

size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);

963

size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);

964

for (i = 0; i < FEC_RBD_NUM; i++) {

964

for (i = 0; i < FEC_RBD_NUM; i++) {

965

data = memalign(FEC_DMA_RX_MINALIGN, size);

965

data = memalign(FEC_DMA_RX_MINALIGN, size);

966

if (!data) {

966

if (!data) {

967

printf("%s: error allocating rxbuf %d\n", __func__, i);

967

printf("%s: error allocating rxbuf %d\n", __func__, i);

968

goto err_ring;

968

goto err_ring;

969

}

969

}

970

971

memset(data, 0, size);

971

memset(data, 0, size);

972

973

addr = (ulong)data;

973

addr = (ulong)data;

974

fec->rbd_base[i].data_pointer = (uint32_t)addr;

974

fec->rbd_base[i].data_pointer = (uint32_t)addr;

975

fec->rbd_base[i].status = FEC_RBD_EMPTY;

975

fec->rbd_base[i].status = FEC_RBD_EMPTY;

976

fec->rbd_base[i].data_length = 0;

976

fec->rbd_base[i].data_length = 0;

977

/* Flush the buffer to memory. */

977

/* Flush the buffer to memory. */

978

flush_dcache_range(addr, addr + size);

978

flush_dcache_range(addr, addr + size);

979

}

979

}

980

981

/* Mark the last RBD to close the ring. */

981

/* Mark the last RBD to close the ring. */

982

fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;

982

fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;

983

984

fec->rbd_index = 0;

984

fec->rbd_index = 0;

985

fec->tbd_index = 0;

985

fec->tbd_index = 0;

986

987

return 0;

987

return 0;

988

989

err_ring:

989

err_ring:

990

for (; i >= 0; i--) {

990

for (; i >= 0; i--) {

991

addr = fec->rbd_base[i].data_pointer;

991

addr = fec->rbd_base[i].data_pointer;

992

free((void *)addr);

992

free((void *)addr);

993

}

993

}

994

free(fec->rbd_base);

994

free(fec->rbd_base);

995

err_rx:

995

err_rx:

996

free(fec->tbd_base);

996

free(fec->tbd_base);

997

err_tx:

997

err_tx:

998

return -ENOMEM;

998

return -ENOMEM;

999

}

999

}

1000

1001

static void fec_free_descs(struct fec_priv *fec)

1001

static void fec_free_descs(struct fec_priv *fec)

1002

{

1002

{

1003

int i;

1003

int i;

1004

ulong addr;

1004

ulong addr;

1005

1006

for (i = 0; i < FEC_RBD_NUM; i++) {

1006

for (i = 0; i < FEC_RBD_NUM; i++) {

1007

addr = fec->rbd_base[i].data_pointer;

1007

addr = fec->rbd_base[i].data_pointer;

1008

free((void *)addr);

1008

free((void *)addr);

1009

}

1009

}

1010

free(fec->rbd_base);

1010

free(fec->rbd_base);

1011

free(fec->tbd_base);

1011

free(fec->tbd_base);

1012

}

1012

}

1013

1014

struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)

1014

struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)

1015

{

1015

{

1016

struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;

1016

struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;

1017

struct mii_dev *bus;

1017

struct mii_dev *bus;

1018

int ret;

1018

int ret;

1019

1020

bus = mdio_alloc();

1020

bus = mdio_alloc();

1021

if (!bus) {

1021

if (!bus) {

1022

printf("mdio_alloc failed\n");

1022

printf("mdio_alloc failed\n");

1023

return NULL;

1023

return NULL;

1024

}

1024

}

1025

bus->read = fec_phy_read;

1025

bus->read = fec_phy_read;

1026

bus->write = fec_phy_write;

1026

bus->write = fec_phy_write;

1027

bus->priv = eth;

1027

bus->priv = eth;

1028

fec_set_dev_name(bus->name, dev_id);

1028

fec_set_dev_name(bus->name, dev_id);

1029

1030

ret = mdio_register(bus);

1030

ret = mdio_register(bus);

1031

if (ret) {

1031

if (ret) {

1032

printf("mdio_register failed\n");

1032

printf("mdio_register failed\n");

1033

free(bus);

1033

free(bus);

1034

return NULL;

1034

return NULL;

1035

}

1035

}

1036

fec_mii_setspeed(eth);

1036

fec_mii_setspeed(eth);

1037

return bus;

1037

return bus;

1038

}

1038

}

1039

1040

#ifndef CONFIG_DM_ETH

1040

#ifndef CONFIG_DM_ETH

1041

#ifdef CONFIG_PHYLIB

1041

#ifdef CONFIG_PHYLIB

1042

int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,

1042

int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,

1043

struct mii_dev *bus, struct phy_device *phydev)

1043

struct mii_dev *bus, struct phy_device *phydev)

1044

#else

1044

#else

1045

static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,

1045

static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,

1046

struct mii_dev *bus, int phy_id)

1046

struct mii_dev *bus, int phy_id)

1047

#endif

1047

#endif

1048

{

1048

{

1049

struct eth_device *edev;

1049

struct eth_device *edev;

1050

struct fec_priv *fec;

1050

struct fec_priv *fec;

1051

unsigned char ethaddr[6];

1051

unsigned char ethaddr[6];

1052

char mac[16];

1052

char mac[16];

1053

uint32_t start;

1053

uint32_t start;

1054

int ret = 0;

1054

int ret = 0;

1055

1056

/* create and fill edev struct */

1056

/* create and fill edev struct */

1057

edev = (struct eth_device *)malloc(sizeof(struct eth_device));

1057

edev = (struct eth_device *)malloc(sizeof(struct eth_device));

1058

if (!edev) {

1058

if (!edev) {

1059

puts("fec_mxc: not enough malloc memory for eth_device\n");

1059

puts("fec_mxc: not enough malloc memory for eth_device\n");

1060

ret = -ENOMEM;

1060

ret = -ENOMEM;

1061

goto err1;

1061

goto err1;

1062

}

1062

}

1063

1064

fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));

1064

fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));

1065

if (!fec) {

1065

if (!fec) {

1066

puts("fec_mxc: not enough malloc memory for fec_priv\n");

1066

puts("fec_mxc: not enough malloc memory for fec_priv\n");

1067

ret = -ENOMEM;

1067

ret = -ENOMEM;

1068

goto err2;

1068

goto err2;

1069

}

1069

}

1070

1071

memset(edev, 0, sizeof(*edev));

1071

memset(edev, 0, sizeof(*edev));

1072

memset(fec, 0, sizeof(*fec));

1072

memset(fec, 0, sizeof(*fec));

1073

1074

ret = fec_alloc_descs(fec);

1074

ret = fec_alloc_descs(fec);

1075

if (ret)

1075

if (ret)

1076

goto err3;

1076

goto err3;

1077

1078

edev->priv = fec;

1078

edev->priv = fec;

1079

edev->init = fec_init;

1079

edev->init = fec_init;

1080

edev->send = fec_send;

1080

edev->send = fec_send;

1081

edev->recv = fec_recv;

1081

edev->recv = fec_recv;

1082

edev->halt = fec_halt;

1082

edev->halt = fec_halt;

1083

edev->write_hwaddr = fec_set_hwaddr;

1083

edev->write_hwaddr = fec_set_hwaddr;

1084

1085

fec->eth = (struct ethernet_regs *)(ulong)base_addr;

1085

fec->eth = (struct ethernet_regs *)(ulong)base_addr;

1086

fec->bd = bd;

1086

fec->bd = bd;

1087

1088

fec->xcv_type = CONFIG_FEC_XCV_TYPE;

1088

fec->xcv_type = CONFIG_FEC_XCV_TYPE;

1089

1090

/* Reset chip. */

1090

/* Reset chip. */

1091

writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);

1091

writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);

1092

start = get_timer(0);

1092

start = get_timer(0);

1093

while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {

1093

while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {

1094

if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {

1094

if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {

1095

printf("FEC MXC: Timeout resetting chip\n");

1095

printf("FEC MXC: Timeout resetting chip\n");

1096

goto err4;

1096

goto err4;

1097

}

1097

}

1098

udelay(10);

1098

udelay(10);

1099

}

1099

}

1100

1101

fec_reg_setup(fec);

1101

fec_reg_setup(fec);

1102

fec_set_dev_name(edev->name, dev_id);

1102

fec_set_dev_name(edev->name, dev_id);

1103

fec->dev_id = (dev_id == -1) ? 0 : dev_id;

1103

fec->dev_id = (dev_id == -1) ? 0 : dev_id;

1104

fec->bus = bus;

1104

fec->bus = bus;

1105

fec_mii_setspeed(bus->priv);

1105

fec_mii_setspeed(bus->priv);

1106

#ifdef CONFIG_PHYLIB

1106

#ifdef CONFIG_PHYLIB

1107

fec->phydev = phydev;

1107

fec->phydev = phydev;

1108

phy_connect_dev(phydev, edev);

1108

phy_connect_dev(phydev, edev);

1109

/* Configure phy */

1109

/* Configure phy */

1110

phy_config(phydev);

1110

phy_config(phydev);

1111

#else

1111

#else

1112

fec->phy_id = phy_id;

1112

fec->phy_id = phy_id;

1113

#endif

1113

#endif

1114

eth_register(edev);

1114

eth_register(edev);

1115

/* only support one eth device, the index number pointed by dev_id */

1115

/* only support one eth device, the index number pointed by dev_id */

1116

edev->index = fec->dev_id;

1116

edev->index = fec->dev_id;

1117

1118

if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {

1118

if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {

1119

debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);

1119

debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);

1120

memcpy(edev->enetaddr, ethaddr, 6);

1120

memcpy(edev->enetaddr, ethaddr, 6);

1121

if (fec->dev_id)

1121

if (fec->dev_id)

1122

sprintf(mac, "eth%daddr", fec->dev_id);

1122

sprintf(mac, "eth%daddr", fec->dev_id);

1123

else

1123

else

1124

strcpy(mac, "ethaddr");

1124

strcpy(mac, "ethaddr");

1125

if (!env_get(mac))

1125

if (!env_get(mac))

1126

eth_env_set_enetaddr(mac, ethaddr);

1126

eth_env_set_enetaddr(mac, ethaddr);

1127

}

1127

}

1128

return ret;

1128

return ret;

1129

err4:

1129

err4:

1130

fec_free_descs(fec);

1130

fec_free_descs(fec);

1131

err3:

1131

err3:

1132

free(fec);

1132

free(fec);

1133

err2:

1133

err2:

1134

free(edev);

1134

free(edev);

1135

err1:

1135

err1:

1136

return ret;

1136

return ret;

1137

}

1137

}

1138

1139

int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)

1139

int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)

1140

{

1140

{

1141

uint32_t base_mii;

1141

uint32_t base_mii;

1142

struct mii_dev *bus = NULL;

1142

struct mii_dev *bus = NULL;

1143

#ifdef CONFIG_PHYLIB

1143

#ifdef CONFIG_PHYLIB

1144

struct phy_device *phydev = NULL;

1144

struct phy_device *phydev = NULL;

1145

#endif

1145

#endif

1146

int ret;

1146

int ret;

1147

1148

#ifdef CONFIG_MX28

1148

#ifdef CONFIG_MX28

1149

/*

1149

/*

1150

* The i.MX28 has two ethernet interfaces, but they are not equal.

1150

* The i.MX28 has two ethernet interfaces, but they are not equal.

1151

* Only the first one can access the MDIO bus.

1151

* Only the first one can access the MDIO bus.

1152

*/

1152

*/

1153

base_mii = MXS_ENET0_BASE;

1153

base_mii = MXS_ENET0_BASE;

1154

#else

1154

#else

1155

base_mii = addr;

1155

base_mii = addr;

1156

#endif

1156

#endif

1157

debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);

1157

debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);

1158

bus = fec_get_miibus((ulong)base_mii, dev_id);

1158

bus = fec_get_miibus((ulong)base_mii, dev_id);

1159

if (!bus)

1159

if (!bus)

1160

return -ENOMEM;

1160

return -ENOMEM;

1161

#ifdef CONFIG_PHYLIB

1161

#ifdef CONFIG_PHYLIB

1162

phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);

1162

phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);

1163

if (!phydev) {

1163

if (!phydev) {

1164

mdio_unregister(bus);

1164

mdio_unregister(bus);

1165

free(bus);

1165

free(bus);

1166

return -ENOMEM;

1166

return -ENOMEM;

1167

}

1167

}

1168

ret = fec_probe(bd, dev_id, addr, bus, phydev);

1168

ret = fec_probe(bd, dev_id, addr, bus, phydev);

1169

#else

1169

#else

1170

ret = fec_probe(bd, dev_id, addr, bus, phy_id);

1170

ret = fec_probe(bd, dev_id, addr, bus, phy_id);

1171

#endif

1171

#endif

1172

if (ret) {

1172

if (ret) {

1173

#ifdef CONFIG_PHYLIB

1173

#ifdef CONFIG_PHYLIB

1174

free(phydev);

1174

free(phydev);

1175

#endif

1175

#endif

1176

mdio_unregister(bus);

1176

mdio_unregister(bus);

1177

free(bus);

1177

free(bus);

1178

}

1178

}

1179

return ret;

1179

return ret;

1180

}

1180

}

1181

1182

#ifdef CONFIG_FEC_MXC_PHYADDR

1182

#ifdef CONFIG_FEC_MXC_PHYADDR

1183

int fecmxc_initialize(bd_t *bd)

1183

int fecmxc_initialize(bd_t *bd)

1184

{

1184

{

1185

return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,

1185

return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,

1186

IMX_FEC_BASE);

1186

IMX_FEC_BASE);

1187

}

1187

}

1188

#endif

1188

#endif

1189

1190

#ifndef CONFIG_PHYLIB

1190

#ifndef CONFIG_PHYLIB

1191

int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))

1191

int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))

1192

{

1192

{

1193

struct fec_priv *fec = (struct fec_priv *)dev->priv;

1193

struct fec_priv *fec = (struct fec_priv *)dev->priv;

1194

fec->mii_postcall = cb;

1194

fec->mii_postcall = cb;

1195

return 0;

1195

return 0;

1196

}

1196

}

1197

#endif

1197

#endif

1198

1199

#else

1199

#else

1200

1201

static int fecmxc_read_rom_hwaddr(struct udevice *dev)

1201

static int fecmxc_read_rom_hwaddr(struct udevice *dev)

1202

{

1202

{

1203

struct fec_priv *priv = dev_get_priv(dev);

1203

struct fec_priv *priv = dev_get_priv(dev);

1204

struct eth_pdata *pdata = dev_get_platdata(dev);

1204

struct eth_pdata *pdata = dev_get_platdata(dev);

1205

1206

return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);

1206

return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);

1207

}

1207

}

1208

1209

static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)

1209

static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)

1210

{

1210

{

1211

if (packet)

1211

if (packet)

1212

free(packet);

1212

free(packet);

1213

1214

return 0;

1214

return 0;

1215

}

1215

}

1216

1217

static const struct eth_ops fecmxc_ops = {

1217

static const struct eth_ops fecmxc_ops = {

1218

.start = fecmxc_init,

1218

.start = fecmxc_init,

1219

.send = fecmxc_send,

1219

.send = fecmxc_send,

1220

.recv = fecmxc_recv,

1220

.recv = fecmxc_recv,

1221

.free_pkt = fecmxc_free_pkt,

1221

.free_pkt = fecmxc_free_pkt,

1222

.stop = fecmxc_halt,

1222

.stop = fecmxc_halt,

1223

.write_hwaddr = fecmxc_set_hwaddr,

1223

.write_hwaddr = fecmxc_set_hwaddr,

1224

.read_rom_hwaddr = fecmxc_read_rom_hwaddr,

1224

.read_rom_hwaddr = fecmxc_read_rom_hwaddr,

1225

};

1225

};

1226

1227

static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)

1227

static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)

1228

{

1228

{

1229

struct phy_device *phydev;

1229

struct phy_device *phydev;

1230

int mask = 0xffffffff;

1230

int mask = 0xffffffff;

1231

1232

#ifdef CONFIG_PHYLIB

1232

#ifdef CONFIG_PHYLIB

1233

mask = 1 << CONFIG_FEC_MXC_PHYADDR;

1233

mask = 1 << CONFIG_FEC_MXC_PHYADDR;

1234

#endif

1234

#endif

1235

1236

phydev = phy_find_by_mask(priv->bus, mask, priv->interface);

1236

phydev = phy_find_by_mask(priv->bus, mask, priv->interface);

1237

if (!phydev)

1237

if (!phydev)

1238

return -ENODEV;

1238

return -ENODEV;

1239

1240

phy_connect_dev(phydev, dev);

1240

phy_connect_dev(phydev, dev);

1241

1242

priv->phydev = phydev;

1242

priv->phydev = phydev;

1243

phy_config(phydev);

1243

phy_config(phydev);

1244

1245

return 0;

1245

return 0;

1246

}

1246

}

1247

1248

static int fecmxc_probe(struct udevice *dev)

1248

static int fecmxc_probe(struct udevice *dev)

1249

{

1249

{

1250

struct eth_pdata *pdata = dev_get_platdata(dev);

1250

struct eth_pdata *pdata = dev_get_platdata(dev);

1251

struct fec_priv *priv = dev_get_priv(dev);

1251

struct fec_priv *priv = dev_get_priv(dev);

1252

struct mii_dev *bus = NULL;

1252

struct mii_dev *bus = NULL;

1253

int dev_id = -1;

1254

uint32_t start;

1253

uint32_t start;

1255

int ret;

1254

int ret;

1256

1255

1257

ret = fec_alloc_descs(priv);

1256

ret = fec_alloc_descs(priv);

1258

if (ret)

1257

if (ret)

1259

return ret;

1258

return ret;

1260

1259

1261

/* Reset chip. */

1260

/* Reset chip. */

1262

writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,

1261

writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,

1263

&priv->eth->ecntrl);

1262

&priv->eth->ecntrl);

1264

start = get_timer(0);

1263

start = get_timer(0);

1265

while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {

1264

while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {

1266

if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {

1265

if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {

1267

printf("FEC MXC: Timeout reseting chip\n");

1266

printf("FEC MXC: Timeout reseting chip\n");

1268

goto err_timeout;

1267

goto err_timeout;

1269

}

1268

}

1270

udelay(10);

1269

udelay(10);

1271

}

1270

}

1272

1271

1273

fec_reg_setup(priv);

1272

fec_reg_setup(priv);

1274

priv->dev_id = (dev_id == -1) ? 0 : dev_id;

1275

1273

1276

bus = fec_get_miibus((ulong)priv->eth, dev_id);

1274

priv->dev_id = dev->seq;

1275

bus = fec_get_miibus((ulong)priv->eth, dev->seq);

1277

if (!bus) {

1276

if (!bus) {

1278

ret = -ENOMEM;

1277

ret = -ENOMEM;

1279

goto err_mii;

1278

goto err_mii;

1280

}

1279

}

1281

1280

1282

priv->bus = bus;

1281

priv->bus = bus;

1283

priv->xcv_type = CONFIG_FEC_XCV_TYPE;

1282

priv->xcv_type = CONFIG_FEC_XCV_TYPE;

1284

priv->interface = pdata->phy_interface;

1283

priv->interface = pdata->phy_interface;

1285

ret = fec_phy_init(priv, dev);

1284

ret = fec_phy_init(priv, dev);

1286

if (ret)

1285

if (ret)

1287

goto err_phy;

1286

goto err_phy;

1288

1287

1289

return 0;

1288

return 0;

1290

1289

1291

err_timeout:

1290

err_timeout:

1292

free(priv->phydev);

1291

free(priv->phydev);

1293

err_phy:

1292

err_phy:

1294

mdio_unregister(bus);

1293

mdio_unregister(bus);

1295

free(bus);

1294

free(bus);

1296

err_mii:

1295

err_mii:

1297

fec_free_descs(priv);

1296

fec_free_descs(priv);

1298

return ret;

1297

return ret;

1299

}

1298

}

1300

1299

1301

static int fecmxc_remove(struct udevice *dev)

1300

static int fecmxc_remove(struct udevice *dev)

1302

{

1301

{

1303

struct fec_priv *priv = dev_get_priv(dev);

1302

struct fec_priv *priv = dev_get_priv(dev);

1304

1303

1305

free(priv->phydev);

1304

free(priv->phydev);

1306

fec_free_descs(priv);

1305

fec_free_descs(priv);

1307

mdio_unregister(priv->bus);

1306

mdio_unregister(priv->bus);

1308

mdio_free(priv->bus);

1307

mdio_free(priv->bus);

1309

1308

1310

return 0;

1309

return 0;

1311

}

1310

}

1312

1311

1313

static int fecmxc_ofdata_to_platdata(struct udevice *dev)

1312

static int fecmxc_ofdata_to_platdata(struct udevice *dev)

1314

{

1313

{

1315

struct eth_pdata *pdata = dev_get_platdata(dev);

1314

struct eth_pdata *pdata = dev_get_platdata(dev);

1316

struct fec_priv *priv = dev_get_priv(dev);

1315

struct fec_priv *priv = dev_get_priv(dev);

1317

const char *phy_mode;

1316

const char *phy_mode;

1318

1317

1319

pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);

1318

pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);

1320

priv->eth = (struct ethernet_regs *)pdata->iobase;

1319

priv->eth = (struct ethernet_regs *)pdata->iobase;

1321

1320

1322

pdata->phy_interface = -1;

1321

pdata->phy_interface = -1;

1323

phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",

1322

phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",

1324

NULL);

1323

NULL);

1325

if (phy_mode)

1324

if (phy_mode)

1326

pdata->phy_interface = phy_get_interface_by_name(phy_mode);

1325

pdata->phy_interface = phy_get_interface_by_name(phy_mode);

1327

if (pdata->phy_interface == -1) {

1326

if (pdata->phy_interface == -1) {

1328

debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);

1327

debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);

1329

return -EINVAL;

1328

return -EINVAL;

1330

}

1329

}

1331

1330

1332

/* TODO

1331

/* TODO

1333

* Need to get the reset-gpio and related properties from DT

1332

* Need to get the reset-gpio and related properties from DT

1334

* and implemet the enet reset code on .probe call

1333

* and implemet the enet reset code on .probe call

1335

*/

1334

*/

1336

1335

1337

return 0;

1336

return 0;

1338

}

1337

}

1339

1338

1340

static const struct udevice_id fecmxc_ids[] = {

1339

static const struct udevice_id fecmxc_ids[] = {

1341

{ .compatible = "fsl,imx6q-fec" },

1340

{ .compatible = "fsl,imx6q-fec" },

1342

{ }

1341

{ }

1343

};

1342

};

1344

1343

1345

U_BOOT_DRIVER(fecmxc_gem) = {

1344

U_BOOT_DRIVER(fecmxc_gem) = {

1346

.name = "fecmxc",

1345

.name = "fecmxc",

1347

.id = UCLASS_ETH,

1346

.id = UCLASS_ETH,

1348

.of_match = fecmxc_ids,

1347

.of_match = fecmxc_ids,

1349

.ofdata_to_platdata = fecmxc_ofdata_to_platdata,

1348

.ofdata_to_platdata = fecmxc_ofdata_to_platdata,

1350

.probe = fecmxc_probe,

1349

.probe = fecmxc_probe,

1351

.remove = fecmxc_remove,

1350

.remove = fecmxc_remove,

1352

.ops = &fecmxc_ops,

1351

.ops = &fecmxc_ops,

1353

.priv_auto_alloc_size = sizeof(struct fec_priv),

1352

.priv_auto_alloc_size = sizeof(struct fec_priv),

1354

.platdata_auto_alloc_size = sizeof(struct eth_pdata),

1353

.platdata_auto_alloc_size = sizeof(struct eth_pdata),

1355

};

1354

};

1356

#endif

1355

#endif

GITLAB

net: fec: set dev->seq to priv->dev_id

 /*
  * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
  * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
  * (C) Copyright 2008 Armadeus Systems nc
  * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <dm.h>
 #include <malloc.h>
 #include <memalign.h>
 #include <miiphy.h>
 #include <net.h>
 #include <netdev.h>
 #include "fec_mxc.h"
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <linux/compiler.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/mach-imx/sys_proto.h>
 DECLARE_GLOBAL_DATA_PTR;
 /*
  * Timeout the transfer after 5 mS. This is usually a bit more, since
  * the code in the tightloops this timeout is used in adds some overhead.
  */
 #define FEC_XFER_TIMEOUT	5000
 /*
  * The standard 32-byte DMA alignment does not work on mx6solox, which requires
  * 64-byte alignment in the DMA RX FEC buffer.
  * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
  * satisfies the alignment on other SoCs (32-bytes)
  */
 #define FEC_DMA_RX_MINALIGN	64
 #ifndef CONFIG_MII
 #error "CONFIG_MII has to be defined!"
 #endif
 #ifndef CONFIG_FEC_XCV_TYPE
 #define CONFIG_FEC_XCV_TYPE MII100
 #endif
 /*
  * The i.MX28 operates with packets in big endian. We need to swap them before
  * sending and after receiving.
  */
 #ifdef CONFIG_MX28
 #define CONFIG_FEC_MXC_SWAP_PACKET
 #endif
 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
 /* Check various alignment issues at compile time */
 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
 #endif
 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
 	(PKTALIGN % ARCH_DMA_MINALIGN != 0))
 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
 #endif
 #undef DEBUG
 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
 static void swap_packet(uint32_t *packet, int length)
 {
 	int i;
 	for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
 		packet[i] = __swab32(packet[i]);
 }
 #endif
 /* MII-interface related functions */
 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
 		uint8_t regaddr)
 {
 	uint32_t reg;		/* convenient holder for the PHY register */
 	uint32_t phy;		/* convenient holder for the PHY */
 	uint32_t start;
 	int val;
 	/*
 	 * reading from any PHY's register is done by properly
 	 * programming the FEC's MII data register.
 	 */
 	writel(FEC_IEVENT_MII, &eth->ievent);
 	reg = regaddr << FEC_MII_DATA_RA_SHIFT;
 	phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
 	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
 			phy | reg, &eth->mii_data);
 	/* wait for the related interrupt */
 	start = get_timer(0);
 	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
 		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
 			printf("Read MDIO failed...\n");
 			return -1;
 		}
 	}
 	/* clear mii interrupt bit */
 	writel(FEC_IEVENT_MII, &eth->ievent);
 	/* it's now safe to read the PHY's register */
 	val = (unsigned short)readl(&eth->mii_data);
 	debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
 	      regaddr, val);
 	return val;
 }
 static void fec_mii_setspeed(struct ethernet_regs *eth)
 {
 	/*
 	 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 	 * and do not drop the Preamble.
 	 *
 	 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
 	 * MII_SPEED) register that defines the MDIO output hold time. Earlier
 	 * versions are RAZ there, so just ignore the difference and write the
 	 * register always.
 	 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
 	 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
 	 * output.
 	 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
 	 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
 	 * holdtime cannot result in a value greater than 3.
 	 */
 	u32 pclk = imx_get_fecclk();
 	u32 speed = DIV_ROUND_UP(pclk, 5000000);
 	u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
 #ifdef FEC_QUIRK_ENET_MAC
 	speed--;
 #endif
 	writel(speed << 1 | hold << 8, &eth->mii_speed);
 	debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
 }
 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
 		uint8_t regaddr, uint16_t data)
 {
 	uint32_t reg;		/* convenient holder for the PHY register */
 	uint32_t phy;		/* convenient holder for the PHY */
 	uint32_t start;
 	reg = regaddr << FEC_MII_DATA_RA_SHIFT;
 	phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
 	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
 		FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
 	/* wait for the MII interrupt */
 	start = get_timer(0);
 	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
 		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
 			printf("Write MDIO failed...\n");
 			return -1;
 		}
 	}
 	/* clear MII interrupt bit */
 	writel(FEC_IEVENT_MII, &eth->ievent);
 	debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
 	      regaddr, data);
 	return 0;
 }
 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
 			int regaddr)
 {
 	return fec_mdio_read(bus->priv, phyaddr, regaddr);
 }
 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
 			 int regaddr, u16 data)
 {
 	return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
 }
 #ifndef CONFIG_PHYLIB
 static int miiphy_restart_aneg(struct eth_device *dev)
 {
 	int ret = 0;
 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 	struct ethernet_regs *eth = fec->bus->priv;
 	/*
 	 * Wake up from sleep if necessary
 	 * Reset PHY, then delay 300ns
 	 */
 #ifdef CONFIG_MX27
 	fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
 #endif
 	fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
 	udelay(1000);
 	/* Set the auto-negotiation advertisement register bits */
 	fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
 		       LPA_100FULL | LPA_100HALF | LPA_10FULL |
 		       LPA_10HALF | PHY_ANLPAR_PSB_802_3);
 	fec_mdio_write(eth, fec->phy_id, MII_BMCR,
 		       BMCR_ANENABLE | BMCR_ANRESTART);
 	if (fec->mii_postcall)
 		ret = fec->mii_postcall(fec->phy_id);
 #endif
 	return ret;
 }
 #ifndef CONFIG_FEC_FIXED_SPEED
 static int miiphy_wait_aneg(struct eth_device *dev)
 {
 	uint32_t start;
 	int status;
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 	struct ethernet_regs *eth = fec->bus->priv;
 	/* Wait for AN completion */
 	start = get_timer(0);
 	do {
 		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
 			printf("%s: Autonegotiation timeout\n", dev->name);
 			return -1;
 		}
 		status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
 		if (status < 0) {
 			printf("%s: Autonegotiation failed. status: %d\n",
 			       dev->name, status);
 			return -1;
 		}
 	} while (!(status & BMSR_LSTATUS));
 	return 0;
 }
 #endif /* CONFIG_FEC_FIXED_SPEED */
 #endif
 static int fec_rx_task_enable(struct fec_priv *fec)
 {
 	writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
 	return 0;
 }
 static int fec_rx_task_disable(struct fec_priv *fec)
 {
 	return 0;
 }
 static int fec_tx_task_enable(struct fec_priv *fec)
 {
 	writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
 	return 0;
 }
 static int fec_tx_task_disable(struct fec_priv *fec)
 {
 	return 0;
 }
 /**
  * Initialize receive task's buffer descriptors
  * @param[in] fec all we know about the device yet
  * @param[in] count receive buffer count to be allocated
  * @param[in] dsize desired size of each receive buffer
  * @return 0 on success
  *
  * Init all RX descriptors to default values.
  */
 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
 {
 	uint32_t size;
 	ulong data;
 	int i;
 	/*
 	 * Reload the RX descriptors with default values and wipe
 	 * the RX buffers.
 	 */
 	size = roundup(dsize, ARCH_DMA_MINALIGN);
 	for (i = 0; i < count; i++) {
 		data = fec->rbd_base[i].data_pointer;
 		memset((void *)data, 0, dsize);
 		flush_dcache_range(data, data + size);
 		fec->rbd_base[i].status = FEC_RBD_EMPTY;
 		fec->rbd_base[i].data_length = 0;
 	}
 	/* Mark the last RBD to close the ring. */
 	fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
 	fec->rbd_index = 0;
 	flush_dcache_range((ulong)fec->rbd_base,
 			   (ulong)fec->rbd_base + size);
 }
 /**
  * Initialize transmit task's buffer descriptors
  * @param[in] fec all we know about the device yet
  *
  * Transmit buffers are created externally. We only have to init the BDs here.\n
  * Note: There is a race condition in the hardware. When only one BD is in
  * use it must be marked with the WRAP bit to use it for every transmitt.
  * This bit in combination with the READY bit results into double transmit
  * of each data buffer. It seems the state machine checks READY earlier then
  * resetting it after the first transfer.
  * Using two BDs solves this issue.
  */
 static void fec_tbd_init(struct fec_priv *fec)
 {
 	ulong addr = (ulong)fec->tbd_base;
 	unsigned size = roundup(2 * sizeof(struct fec_bd),
 				ARCH_DMA_MINALIGN);
 	memset(fec->tbd_base, 0, size);
 	fec->tbd_base[0].status = 0;
 	fec->tbd_base[1].status = FEC_TBD_WRAP;
 	fec->tbd_index = 0;
 	flush_dcache_range(addr, addr + size);
 }
 /**
  * Mark the given read buffer descriptor as free
  * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
  * @param[in] prbd buffer descriptor to mark free again
  */
 static void fec_rbd_clean(int last, struct fec_bd *prbd)
 {
 	unsigned short flags = FEC_RBD_EMPTY;
 	if (last)
 		flags |= FEC_RBD_WRAP;
 	writew(flags, &prbd->status);
 	writew(0, &prbd->data_length);
 }
 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
 {
 	imx_get_mac_from_fuse(dev_id, mac);
 	return !is_valid_ethaddr(mac);
 }
 #ifdef CONFIG_DM_ETH
 static int fecmxc_set_hwaddr(struct udevice *dev)
 #else
 static int fec_set_hwaddr(struct eth_device *dev)
 #endif
 {
 #ifdef CONFIG_DM_ETH
 	struct fec_priv *fec = dev_get_priv(dev);
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	uchar *mac = pdata->enetaddr;
 #else
 	uchar *mac = dev->enetaddr;
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 #endif
 	writel(0, &fec->eth->iaddr1);
 	writel(0, &fec->eth->iaddr2);
 	writel(0, &fec->eth->gaddr1);
 	writel(0, &fec->eth->gaddr2);
 	/* Set physical address */
 	writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
 	       &fec->eth->paddr1);
 	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
 	return 0;
 }
 /* Do initial configuration of the FEC registers */
 static void fec_reg_setup(struct fec_priv *fec)
 {
 	uint32_t rcntrl;
 	/* Set interrupt mask register */
 	writel(0x00000000, &fec->eth->imask);
 	/* Clear FEC-Lite interrupt event register(IEVENT) */
 	writel(0xffffffff, &fec->eth->ievent);
 	/* Set FEC-Lite receive control register(R_CNTRL): */
 	/* Start with frame length = 1518, common for all modes. */
 	rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
 	if (fec->xcv_type != SEVENWIRE)		/* xMII modes */
 		rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
 	if (fec->xcv_type == RGMII)
 		rcntrl |= FEC_RCNTRL_RGMII;
 	else if (fec->xcv_type == RMII)
 		rcntrl |= FEC_RCNTRL_RMII;
 	writel(rcntrl, &fec->eth->r_cntrl);
 }
 /**
  * Start the FEC engine
  * @param[in] dev Our device to handle
  */
 #ifdef CONFIG_DM_ETH
 static int fec_open(struct udevice *dev)
 #else
 static int fec_open(struct eth_device *edev)
 #endif
 {
 #ifdef CONFIG_DM_ETH
 	struct fec_priv *fec = dev_get_priv(dev);
 #else
 	struct fec_priv *fec = (struct fec_priv *)edev->priv;
 #endif
 	int speed;
 	ulong addr, size;
 	int i;
 	debug("fec_open: fec_open(dev)\n");
 	/* full-duplex, heartbeat disabled */
 	writel(1 << 2, &fec->eth->x_cntrl);
 	fec->rbd_index = 0;
 	/* Invalidate all descriptors */
 	for (i = 0; i < FEC_RBD_NUM - 1; i++)
 		fec_rbd_clean(0, &fec->rbd_base[i]);
 	fec_rbd_clean(1, &fec->rbd_base[i]);
 	/* Flush the descriptors into RAM */
 	size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
 			ARCH_DMA_MINALIGN);
 	addr = (ulong)fec->rbd_base;
 	flush_dcache_range(addr, addr + size);
 #ifdef FEC_QUIRK_ENET_MAC
 	/* Enable ENET HW endian SWAP */
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
 	       &fec->eth->ecntrl);
 	/* Enable ENET store and forward mode */
 	writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
 	       &fec->eth->x_wmrk);
 #endif
 	/* Enable FEC-Lite controller */
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
 	       &fec->eth->ecntrl);
 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 	udelay(100);
 	/* setup the MII gasket for RMII mode */
 	/* disable the gasket */
 	writew(0, &fec->eth->miigsk_enr);
 	/* wait for the gasket to be disabled */
 	while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
 		udelay(2);
 	/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
 	writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
 	/* re-enable the gasket */
 	writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
 	/* wait until MII gasket is ready */
 	int max_loops = 10;
 	while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
 		if (--max_loops <= 0) {
 			printf("WAIT for MII Gasket ready timed out\n");
 			break;
 		}
 	}
 #endif
 #ifdef CONFIG_PHYLIB
 	{
 		/* Start up the PHY */
 		int ret = phy_startup(fec->phydev);
 		if (ret) {
 			printf("Could not initialize PHY %s\n",
 			       fec->phydev->dev->name);
 			return ret;
 		}
 		speed = fec->phydev->speed;
 	}
 #elif CONFIG_FEC_FIXED_SPEED
 	speed = CONFIG_FEC_FIXED_SPEED;
 #else
 	miiphy_wait_aneg(edev);
 	speed = miiphy_speed(edev->name, fec->phy_id);
 	miiphy_duplex(edev->name, fec->phy_id);
 #endif
 #ifdef FEC_QUIRK_ENET_MAC
 	{
 		u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
 		u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
 		if (speed == _1000BASET)
 			ecr |= FEC_ECNTRL_SPEED;
 		else if (speed != _100BASET)
 			rcr |= FEC_RCNTRL_RMII_10T;
 		writel(ecr, &fec->eth->ecntrl);
 		writel(rcr, &fec->eth->r_cntrl);
 	}
 #endif
 	debug("%s:Speed=%i\n", __func__, speed);
 	/* Enable SmartDMA receive task */
 	fec_rx_task_enable(fec);
 	udelay(100000);
 	return 0;
 }
 #ifdef CONFIG_DM_ETH
 static int fecmxc_init(struct udevice *dev)
 #else
 static int fec_init(struct eth_device *dev, bd_t *bd)
 #endif
 {
 #ifdef CONFIG_DM_ETH
 	struct fec_priv *fec = dev_get_priv(dev);
 #else
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 #endif
 	u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
 	u8 *i;
 	ulong addr;
 	/* Initialize MAC address */
 #ifdef CONFIG_DM_ETH
 	fecmxc_set_hwaddr(dev);
 #else
 	fec_set_hwaddr(dev);
 #endif
 	/* Setup transmit descriptors, there are two in total. */
 	fec_tbd_init(fec);
 	/* Setup receive descriptors. */
 	fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
 	fec_reg_setup(fec);
 	if (fec->xcv_type != SEVENWIRE)
 		fec_mii_setspeed(fec->bus->priv);
 	/* Set Opcode/Pause Duration Register */
 	writel(0x00010020, &fec->eth->op_pause);	/* FIXME 0xffff0020; */
 	writel(0x2, &fec->eth->x_wmrk);
 	/* Set multicast address filter */
 	writel(0x00000000, &fec->eth->gaddr1);
 	writel(0x00000000, &fec->eth->gaddr2);
 	/* Do not access reserved register */
 	if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
 		/* clear MIB RAM */
 		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
 			writel(0, i);
 		/* FIFO receive start register */
 		writel(0x520, &fec->eth->r_fstart);
 	}
 	/* size and address of each buffer */
 	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
 	addr = (ulong)fec->tbd_base;
 	writel((uint32_t)addr, &fec->eth->etdsr);
 	addr = (ulong)fec->rbd_base;
 	writel((uint32_t)addr, &fec->eth->erdsr);
 #ifndef CONFIG_PHYLIB
 	if (fec->xcv_type != SEVENWIRE)
 		miiphy_restart_aneg(dev);
 #endif
 	fec_open(dev);
 	return 0;
 }
 /**
  * Halt the FEC engine
  * @param[in] dev Our device to handle
  */
 #ifdef CONFIG_DM_ETH
 static void fecmxc_halt(struct udevice *dev)
 #else
 static void fec_halt(struct eth_device *dev)
 #endif
 {
 #ifdef CONFIG_DM_ETH
 	struct fec_priv *fec = dev_get_priv(dev);
 #else
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 #endif
 	int counter = 0xffff;
 	/* issue graceful stop command to the FEC transmitter if necessary */
 	writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
 	       &fec->eth->x_cntrl);
 	debug("eth_halt: wait for stop regs\n");
 	/* wait for graceful stop to register */
 	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
 		udelay(1);
 	/* Disable SmartDMA tasks */
 	fec_tx_task_disable(fec);
 	fec_rx_task_disable(fec);
 	/*
 	 * Disable the Ethernet Controller
 	 * Note: this will also reset the BD index counter!
 	 */
 	writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
 	       &fec->eth->ecntrl);
 	fec->rbd_index = 0;
 	fec->tbd_index = 0;
 	debug("eth_halt: done\n");
 }
 /**
  * Transmit one frame
  * @param[in] dev Our ethernet device to handle
  * @param[in] packet Pointer to the data to be transmitted
  * @param[in] length Data count in bytes
  * @return 0 on success
  */
 #ifdef CONFIG_DM_ETH
 static int fecmxc_send(struct udevice *dev, void *packet, int length)
 #else
 static int fec_send(struct eth_device *dev, void *packet, int length)
 #endif
 {
 	unsigned int status;
 	u32 size;
 	ulong addr, end;
 	int timeout = FEC_XFER_TIMEOUT;
 	int ret = 0;
 	/*
 	 * This routine transmits one frame.  This routine only accepts
 	 * 6-byte Ethernet addresses.
 	 */
 #ifdef CONFIG_DM_ETH
 	struct fec_priv *fec = dev_get_priv(dev);
 #else
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 #endif
 	/*
 	 * Check for valid length of data.
 	 */
 	if ((length > 1500) || (length <= 0)) {
 		printf("Payload (%d) too large\n", length);
 		return -1;
 	}
 	/*
 	 * Setup the transmit buffer. We are always using the first buffer for
 	 * transmission, the second will be empty and only used to stop the DMA
 	 * engine. We also flush the packet to RAM here to avoid cache trouble.
 	 */
 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
 	swap_packet((uint32_t *)packet, length);
 #endif
 	addr = (ulong)packet;
 	end = roundup(addr + length, ARCH_DMA_MINALIGN);
 	addr &= ~(ARCH_DMA_MINALIGN - 1);
 	flush_dcache_range(addr, end);
 	writew(length, &fec->tbd_base[fec->tbd_index].data_length);
 	writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
 	/*
 	 * update BD's status now
 	 * This block:
 	 * - is always the last in a chain (means no chain)
 	 * - should transmitt the CRC
 	 * - might be the last BD in the list, so the address counter should
 	 *   wrap (-> keep the WRAP flag)
 	 */
 	status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
 	status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
 	writew(status, &fec->tbd_base[fec->tbd_index].status);
 	/*
 	 * Flush data cache. This code flushes both TX descriptors to RAM.
 	 * After this code, the descriptors will be safely in RAM and we
 	 * can start DMA.
 	 */
 	size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
 	addr = (ulong)fec->tbd_base;
 	flush_dcache_range(addr, addr + size);
 	/*
 	 * Below we read the DMA descriptor's last four bytes back from the
 	 * DRAM. This is important in order to make sure that all WRITE
 	 * operations on the bus that were triggered by previous cache FLUSH
 	 * have completed.
 	 *
 	 * Otherwise, on MX28, it is possible to observe a corruption of the
 	 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
 	 * for the bus structure of MX28. The scenario is as follows:
 	 *
 	 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
 	 *    to DRAM due to flush_dcache_range()
 	 * 2) ARM core writes the FEC registers via AHB_ARB2
 	 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
 	 *
 	 * Note that 2) does sometimes finish before 1) due to reordering of
 	 * WRITE accesses on the AHB bus, therefore triggering 3) before the
 	 * DMA descriptor is fully written into DRAM. This results in occasional
 	 * corruption of the DMA descriptor.
 	 */
 	readl(addr + size - 4);
 	/* Enable SmartDMA transmit task */
 	fec_tx_task_enable(fec);
 	/*
 	 * Wait until frame is sent. On each turn of the wait cycle, we must
 	 * invalidate data cache to see what's really in RAM. Also, we need
 	 * barrier here.
 	 */
 	while (--timeout) {
 		if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
 			break;
 	}
 	if (!timeout) {
 		ret = -EINVAL;
 		goto out;
 	}
 	/*
 	 * The TDAR bit is cleared when the descriptors are all out from TX
 	 * but on mx6solox we noticed that the READY bit is still not cleared
 	 * right after TDAR.
 	 * These are two distinct signals, and in IC simulation, we found that
 	 * TDAR always gets cleared prior than the READY bit of last BD becomes
 	 * cleared.
 	 * In mx6solox, we use a later version of FEC IP. It looks like that
 	 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
 	 * version.
 	 *
 	 * Fix this by polling the READY bit of BD after the TDAR polling,
 	 * which covers the mx6solox case and does not harm the other SoCs.
 	 */
 	timeout = FEC_XFER_TIMEOUT;
 	while (--timeout) {
 		invalidate_dcache_range(addr, addr + size);
 		if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
 		    FEC_TBD_READY))
 			break;
 	}
 	if (!timeout)
 		ret = -EINVAL;
 out:
 	debug("fec_send: status 0x%x index %d ret %i\n",
 	      readw(&fec->tbd_base[fec->tbd_index].status),
 	      fec->tbd_index, ret);
 	/* for next transmission use the other buffer */
 	if (fec->tbd_index)
 		fec->tbd_index = 0;
 	else
 		fec->tbd_index = 1;
 	return ret;
 }
 /**
  * Pull one frame from the card
  * @param[in] dev Our ethernet device to handle
  * @return Length of packet read
  */
 #ifdef CONFIG_DM_ETH
 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
 #else
 static int fec_recv(struct eth_device *dev)
 #endif
 {
 #ifdef CONFIG_DM_ETH
 	struct fec_priv *fec = dev_get_priv(dev);
 #else
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 #endif
 	struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
 	unsigned long ievent;
 	int frame_length, len = 0;
 	uint16_t bd_status;
 	ulong addr, size, end;
 	int i;
 #ifdef CONFIG_DM_ETH
 	*packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
 	if (*packetp == 0) {
 		printf("%s: error allocating packetp\n", __func__);
 		return -ENOMEM;
 	}
 #else
 	ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
 #endif
 	/* Check if any critical events have happened */
 	ievent = readl(&fec->eth->ievent);
 	writel(ievent, &fec->eth->ievent);
 	debug("fec_recv: ievent 0x%lx\n", ievent);
 	if (ievent & FEC_IEVENT_BABR) {
 #ifdef CONFIG_DM_ETH
 		fecmxc_halt(dev);
 		fecmxc_init(dev);
 #else
 		fec_halt(dev);
 		fec_init(dev, fec->bd);
 #endif
 		printf("some error: 0x%08lx\n", ievent);
 		return 0;
 	}
 	if (ievent & FEC_IEVENT_HBERR) {
 		/* Heartbeat error */
 		writel(0x00000001 | readl(&fec->eth->x_cntrl),
 		       &fec->eth->x_cntrl);
 	}
 	if (ievent & FEC_IEVENT_GRA) {
 		/* Graceful stop complete */
 		if (readl(&fec->eth->x_cntrl) & 0x00000001) {
 #ifdef CONFIG_DM_ETH
 			fecmxc_halt(dev);
 #else
 			fec_halt(dev);
 #endif
 			writel(~0x00000001 & readl(&fec->eth->x_cntrl),
 			       &fec->eth->x_cntrl);
 #ifdef CONFIG_DM_ETH
 			fecmxc_init(dev);
 #else
 			fec_init(dev, fec->bd);
 #endif
 		}
 	}
 	/*
 	 * Read the buffer status. Before the status can be read, the data cache
 	 * must be invalidated, because the data in RAM might have been changed
 	 * by DMA. The descriptors are properly aligned to cachelines so there's
 	 * no need to worry they'd overlap.
 	 *
 	 * WARNING: By invalidating the descriptor here, we also invalidate
 	 * the descriptors surrounding this one. Therefore we can NOT change the
 	 * contents of this descriptor nor the surrounding ones. The problem is
 	 * that in order to mark the descriptor as processed, we need to change
 	 * the descriptor. The solution is to mark the whole cache line when all
 	 * descriptors in the cache line are processed.
 	 */
 	addr = (ulong)rbd;
 	addr &= ~(ARCH_DMA_MINALIGN - 1);
 	size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
 	invalidate_dcache_range(addr, addr + size);
 	bd_status = readw(&rbd->status);
 	debug("fec_recv: status 0x%x\n", bd_status);
 	if (!(bd_status & FEC_RBD_EMPTY)) {
 		if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
 		    ((readw(&rbd->data_length) - 4) > 14)) {
 			/* Get buffer address and size */
 			addr = readl(&rbd->data_pointer);
 			frame_length = readw(&rbd->data_length) - 4;
 			/* Invalidate data cache over the buffer */
 			end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
 			addr &= ~(ARCH_DMA_MINALIGN - 1);
 			invalidate_dcache_range(addr, end);
 			/* Fill the buffer and pass it to upper layers */
 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
 			swap_packet((uint32_t *)addr, frame_length);
 #endif
 #ifdef CONFIG_DM_ETH
 			memcpy(*packetp, (char *)addr, frame_length);
 #else
 			memcpy(buff, (char *)addr, frame_length);
 			net_process_received_packet(buff, frame_length);
 #endif
 			len = frame_length;
 		} else {
 			if (bd_status & FEC_RBD_ERR)
 				debug("error frame: 0x%08lx 0x%08x\n",
 				      addr, bd_status);
 		}
 		/*
 		 * Free the current buffer, restart the engine and move forward
 		 * to the next buffer. Here we check if the whole cacheline of
 		 * descriptors was already processed and if so, we mark it free
 		 * as whole.
 		 */
 		size = RXDESC_PER_CACHELINE - 1;
 		if ((fec->rbd_index & size) == size) {
 			i = fec->rbd_index - size;
 			addr = (ulong)&fec->rbd_base[i];
 			for (; i <= fec->rbd_index ; i++) {
 				fec_rbd_clean(i == (FEC_RBD_NUM - 1),
 					      &fec->rbd_base[i]);
 			}
 			flush_dcache_range(addr,
 					   addr + ARCH_DMA_MINALIGN);
 		}
 		fec_rx_task_enable(fec);
 		fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
 	}
 	debug("fec_recv: stop\n");
 	return len;
 }
 static void fec_set_dev_name(char *dest, int dev_id)
 {
 	sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
 }
 static int fec_alloc_descs(struct fec_priv *fec)
 {
 	unsigned int size;
 	int i;
 	uint8_t *data;
 	ulong addr;
 	/* Allocate TX descriptors. */
 	size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
 	fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
 	if (!fec->tbd_base)
 		goto err_tx;
 	/* Allocate RX descriptors. */
 	size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
 	fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
 	if (!fec->rbd_base)
 		goto err_rx;
 	memset(fec->rbd_base, 0, size);
 	/* Allocate RX buffers. */
 	/* Maximum RX buffer size. */
 	size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
 	for (i = 0; i < FEC_RBD_NUM; i++) {
 		data = memalign(FEC_DMA_RX_MINALIGN, size);
 		if (!data) {
 			printf("%s: error allocating rxbuf %d\n", __func__, i);
 			goto err_ring;
 		}
 		memset(data, 0, size);
 		addr = (ulong)data;
 		fec->rbd_base[i].data_pointer = (uint32_t)addr;
 		fec->rbd_base[i].status = FEC_RBD_EMPTY;
 		fec->rbd_base[i].data_length = 0;
 		/* Flush the buffer to memory. */
 		flush_dcache_range(addr, addr + size);
 	}
 	/* Mark the last RBD to close the ring. */
 	fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
 	fec->rbd_index = 0;
 	fec->tbd_index = 0;
 	return 0;
 err_ring:
 	for (; i >= 0; i--) {
 		addr = fec->rbd_base[i].data_pointer;
 		free((void *)addr);
 	}
 	free(fec->rbd_base);
 err_rx:
 	free(fec->tbd_base);
 err_tx:
 	return -ENOMEM;
 }
 static void fec_free_descs(struct fec_priv *fec)
 {
 	int i;
 	ulong addr;
 	for (i = 0; i < FEC_RBD_NUM; i++) {
 		addr = fec->rbd_base[i].data_pointer;
 		free((void *)addr);
 	}
 	free(fec->rbd_base);
 	free(fec->tbd_base);
 }
 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
 {
 	struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
 	struct mii_dev *bus;
 	int ret;
 	bus = mdio_alloc();
 	if (!bus) {
 		printf("mdio_alloc failed\n");
 		return NULL;
 	}
 	bus->read = fec_phy_read;
 	bus->write = fec_phy_write;
 	bus->priv = eth;
 	fec_set_dev_name(bus->name, dev_id);
 	ret = mdio_register(bus);
 	if (ret) {
 		printf("mdio_register failed\n");
 		free(bus);
 		return NULL;
 	}
 	fec_mii_setspeed(eth);
 	return bus;
 }
 #ifndef CONFIG_DM_ETH
 #ifdef CONFIG_PHYLIB
 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
 		struct mii_dev *bus, struct phy_device *phydev)
 #else
 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
 		struct mii_dev *bus, int phy_id)
 #endif
 {
 	struct eth_device *edev;
 	struct fec_priv *fec;
 	unsigned char ethaddr[6];
 	char mac[16];
 	uint32_t start;
 	int ret = 0;
 	/* create and fill edev struct */
 	edev = (struct eth_device *)malloc(sizeof(struct eth_device));
 	if (!edev) {
 		puts("fec_mxc: not enough malloc memory for eth_device\n");
 		ret = -ENOMEM;
 		goto err1;
 	}
 	fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
 	if (!fec) {
 		puts("fec_mxc: not enough malloc memory for fec_priv\n");
 		ret = -ENOMEM;
 		goto err2;
 	}
 	memset(edev, 0, sizeof(*edev));
 	memset(fec, 0, sizeof(*fec));
 	ret = fec_alloc_descs(fec);
 	if (ret)
 		goto err3;
 	edev->priv = fec;
 	edev->init = fec_init;
 	edev->send = fec_send;
 	edev->recv = fec_recv;
 	edev->halt = fec_halt;
 	edev->write_hwaddr = fec_set_hwaddr;
 	fec->eth = (struct ethernet_regs *)(ulong)base_addr;
 	fec->bd = bd;
 	fec->xcv_type = CONFIG_FEC_XCV_TYPE;
 	/* Reset chip. */
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
 	start = get_timer(0);
 	while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
 		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
 			printf("FEC MXC: Timeout resetting chip\n");
 			goto err4;
 		}
 		udelay(10);
 	}
 	fec_reg_setup(fec);
 	fec_set_dev_name(edev->name, dev_id);
 	fec->dev_id = (dev_id == -1) ? 0 : dev_id;
 	fec->bus = bus;
 	fec_mii_setspeed(bus->priv);
 #ifdef CONFIG_PHYLIB
 	fec->phydev = phydev;
 	phy_connect_dev(phydev, edev);
 	/* Configure phy */
 	phy_config(phydev);
 #else
 	fec->phy_id = phy_id;
 #endif
 	eth_register(edev);
 	/* only support one eth device, the index number pointed by dev_id */
 	edev->index = fec->dev_id;
 	if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
 		debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
 		memcpy(edev->enetaddr, ethaddr, 6);
 		if (fec->dev_id)
 			sprintf(mac, "eth%daddr", fec->dev_id);
 		else
 			strcpy(mac, "ethaddr");
 		if (!env_get(mac))
 			eth_env_set_enetaddr(mac, ethaddr);
 	}
 	return ret;
 err4:
 	fec_free_descs(fec);
 err3:
 	free(fec);
 err2:
 	free(edev);
 err1:
 	return ret;
 }
 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
 {
 	uint32_t base_mii;
 	struct mii_dev *bus = NULL;
 #ifdef CONFIG_PHYLIB
 	struct phy_device *phydev = NULL;
 #endif
 	int ret;
 #ifdef CONFIG_MX28
 	/*
 	 * The i.MX28 has two ethernet interfaces, but they are not equal.
 	 * Only the first one can access the MDIO bus.
 	 */
 	base_mii = MXS_ENET0_BASE;
 #else
 	base_mii = addr;
 #endif
 	debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
 	bus = fec_get_miibus((ulong)base_mii, dev_id);
 	if (!bus)
 		return -ENOMEM;
 #ifdef CONFIG_PHYLIB
 	phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
 	if (!phydev) {
 		mdio_unregister(bus);
 		free(bus);
 		return -ENOMEM;
 	}
 	ret = fec_probe(bd, dev_id, addr, bus, phydev);
 #else
 	ret = fec_probe(bd, dev_id, addr, bus, phy_id);
 #endif
 	if (ret) {
 #ifdef CONFIG_PHYLIB
 		free(phydev);
 #endif
 		mdio_unregister(bus);
 		free(bus);
 	}
 	return ret;
 }
 #ifdef CONFIG_FEC_MXC_PHYADDR
 int fecmxc_initialize(bd_t *bd)
 {
 	return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
 			IMX_FEC_BASE);
 }
 #endif
 #ifndef CONFIG_PHYLIB
 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
 {
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 	fec->mii_postcall = cb;
 	return 0;
 }
 #endif
 #else
 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
 {
 	struct fec_priv *priv = dev_get_priv(dev);
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
 }
 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
 {
 	if (packet)
 		free(packet);
 	return 0;
 }
 static const struct eth_ops fecmxc_ops = {
 	.start			= fecmxc_init,
 	.send			= fecmxc_send,
 	.recv			= fecmxc_recv,
 	.free_pkt		= fecmxc_free_pkt,
 	.stop			= fecmxc_halt,
 	.write_hwaddr		= fecmxc_set_hwaddr,
 	.read_rom_hwaddr	= fecmxc_read_rom_hwaddr,
 };
 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
 {
 	struct phy_device *phydev;
 	int mask = 0xffffffff;
 #ifdef CONFIG_PHYLIB
 	mask = 1 << CONFIG_FEC_MXC_PHYADDR;
 #endif
 	phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
 	if (!phydev)
 		return -ENODEV;
 	phy_connect_dev(phydev, dev);
 	priv->phydev = phydev;
 	phy_config(phydev);
 	return 0;
 }
 static int fecmxc_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct fec_priv *priv = dev_get_priv(dev);
 	struct mii_dev *bus = NULL;
-	int dev_id = -1;
 	uint32_t start;
 	int ret;
 	ret = fec_alloc_descs(priv);
 	if (ret)
 		return ret;
 	/* Reset chip. */
 	writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
 	       &priv->eth->ecntrl);
 	start = get_timer(0);
 	while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
 		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
 			printf("FEC MXC: Timeout reseting chip\n");
 			goto err_timeout;
 		}
 		udelay(10);
 	}
 	fec_reg_setup(priv);
-	priv->dev_id = (dev_id == -1) ? 0 : dev_id;
-	bus = fec_get_miibus((ulong)priv->eth, dev_id);
+	priv->dev_id = dev->seq;
+	bus = fec_get_miibus((ulong)priv->eth, dev->seq);
 	if (!bus) {
 		ret = -ENOMEM;
 		goto err_mii;
 	}
 	priv->bus = bus;
 	priv->xcv_type = CONFIG_FEC_XCV_TYPE;
 	priv->interface = pdata->phy_interface;
 	ret = fec_phy_init(priv, dev);
 	if (ret)
 		goto err_phy;
 	return 0;
 err_timeout:
 	free(priv->phydev);
 err_phy:
 	mdio_unregister(bus);
 	free(bus);
 err_mii:
 	fec_free_descs(priv);
 	return ret;
 }
 static int fecmxc_remove(struct udevice *dev)
 {
 	struct fec_priv *priv = dev_get_priv(dev);
 	free(priv->phydev);
 	fec_free_descs(priv);
 	mdio_unregister(priv->bus);
 	mdio_free(priv->bus);
 	return 0;
 }
 static int fecmxc_ofdata_to_platdata(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct fec_priv *priv = dev_get_priv(dev);
 	const char *phy_mode;
 	pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
 	priv->eth = (struct ethernet_regs *)pdata->iobase;
 	pdata->phy_interface = -1;
 	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
 			       NULL);
 	if (phy_mode)
 		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 	if (pdata->phy_interface == -1) {
 		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 		return -EINVAL;
 	}
 	/* TODO
 	 * Need to get the reset-gpio and related properties from DT
 	 * and implemet the enet reset code on .probe call
 	 */
 	return 0;
 }
 static const struct udevice_id fecmxc_ids[] = {
 	{ .compatible = "fsl,imx6q-fec" },
 	{ }
 };
 U_BOOT_DRIVER(fecmxc_gem) = {
 	.name	= "fecmxc",
 	.id	= UCLASS_ETH,
 	.of_match = fecmxc_ids,
 	.ofdata_to_platdata = fecmxc_ofdata_to_platdata,
 	.probe	= fecmxc_probe,
 	.remove	= fecmxc_remove,
 	.ops	= &fecmxc_ops,
 	.priv_auto_alloc_size = sizeof(struct fec_priv),
 	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
 };
 #endif