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Commit ae02cf03bc47804e88bb2fbc7cae3560618e6547

Authored by Yuantian Tang
Committed by York Sun
1 parent f216ef252e
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

arm64: ls1012a: Add sata distro boot support 

Sata is equipped on ls1012a and can be a boot source. Add sata boot
support as an option if available.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 3 changed files with 11 additions and 19 deletions Inline Diff

include/configs/ls1012a_common.h
Diff comments   View file @ ae02cf0
1 /* 1 /*
2 * Copyright 2016 Freescale Semiconductor 2 * Copyright 2016 Freescale Semiconductor
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __LS1012A_COMMON_H 7 #ifndef __LS1012A_COMMON_H
8 #define __LS1012A_COMMON_H 8 #define __LS1012A_COMMON_H
9 9
10 #define CONFIG_FSL_LAYERSCAPE 10 #define CONFIG_FSL_LAYERSCAPE
11 #define CONFIG_GICV2 11 #define CONFIG_GICV2
12 12
13 #include <asm/arch/config.h> 13 #include <asm/arch/config.h>
14 #include <asm/arch/stream_id_lsch2.h> 14 #include <asm/arch/stream_id_lsch2.h>
15 15
16 #define CONFIG_SUPPORT_RAW_INITRD 16 #define CONFIG_SUPPORT_RAW_INITRD
17 17
18 #define CONFIG_DISPLAY_BOARDINFO_LATE 18 #define CONFIG_DISPLAY_BOARDINFO_LATE
19 19
20 #define CONFIG_SYS_TEXT_BASE 0x40100000 20 #define CONFIG_SYS_TEXT_BASE 0x40100000
21 21
22 #define CONFIG_SYS_CLK_FREQ 125000000 22 #define CONFIG_SYS_CLK_FREQ 125000000
23 23
24 #define CONFIG_SKIP_LOWLEVEL_INIT 24 #define CONFIG_SKIP_LOWLEVEL_INIT
25 25
26 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 26 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
27 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 27 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
28 28
29 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 29 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
30 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 30 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
31 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 31 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
32 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 32 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
33 33
34 /* Generic Timer Definitions */ 34 /* Generic Timer Definitions */
35 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 35 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
36 36
37 /* CSU */ 37 /* CSU */
38 #define CONFIG_LAYERSCAPE_NS_ACCESS 38 #define CONFIG_LAYERSCAPE_NS_ACCESS
39 39
40 /* Size of malloc() pool */ 40 /* Size of malloc() pool */
41 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 41 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
42 42
43 /*SPI device */ 43 /*SPI device */
44 #ifdef CONFIG_QSPI_BOOT 44 #ifdef CONFIG_QSPI_BOOT
45 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 45 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
46 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 46 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
47 #define CONFIG_ENV_SPI_BUS 0 47 #define CONFIG_ENV_SPI_BUS 0
48 #define CONFIG_ENV_SPI_CS 0 48 #define CONFIG_ENV_SPI_CS 0
49 #define CONFIG_ENV_SPI_MAX_HZ 1000000 49 #define CONFIG_ENV_SPI_MAX_HZ 1000000
50 #define CONFIG_ENV_SPI_MODE 0x03 50 #define CONFIG_ENV_SPI_MODE 0x03
51 #define CONFIG_SPI_FLASH_SPANSION 51 #define CONFIG_SPI_FLASH_SPANSION
52 #define CONFIG_FSL_SPI_INTERFACE 52 #define CONFIG_FSL_SPI_INTERFACE
53 #define CONFIG_SF_DATAFLASH 53 #define CONFIG_SF_DATAFLASH
54 54
55 #define CONFIG_FSL_QSPI 55 #define CONFIG_FSL_QSPI
56 #define QSPI0_AMBA_BASE 0x40000000 56 #define QSPI0_AMBA_BASE 0x40000000
57 #define CONFIG_SPI_FLASH_SPANSION 57 #define CONFIG_SPI_FLASH_SPANSION
58 58
59 #define FSL_QSPI_FLASH_SIZE SZ_64M 59 #define FSL_QSPI_FLASH_SIZE SZ_64M
60 #define FSL_QSPI_FLASH_NUM 2 60 #define FSL_QSPI_FLASH_NUM 2
61 61
62 /* 62 /*
63 * Environment 63 * Environment
64 */ 64 */
65 #define CONFIG_ENV_OVERWRITE 65 #define CONFIG_ENV_OVERWRITE
66 66
67 #define CONFIG_ENV_SIZE 0x40000 /* 256KB */ 67 #define CONFIG_ENV_SIZE 0x40000 /* 256KB */
68 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 68 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
69 #define CONFIG_ENV_SECT_SIZE 0x40000 69 #define CONFIG_ENV_SECT_SIZE 0x40000
70 #endif 70 #endif
71 71
72 /* SATA */
73 #define CONFIG_SCSI_AHCI_PLAT
74
75 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
76
77 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
78 #define CONFIG_SYS_SCSI_MAX_LUN 1
79 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
80 CONFIG_SYS_SCSI_MAX_LUN)
81
72 /* I2C */ 82 /* I2C */
73 #define CONFIG_SYS_I2C 83 #define CONFIG_SYS_I2C
74 #define CONFIG_SYS_I2C_MXC 84 #define CONFIG_SYS_I2C_MXC
75 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 85 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
76 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 86 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
77 87
78 #define CONFIG_CONS_INDEX 1 88 #define CONFIG_CONS_INDEX 1
79 #define CONFIG_SYS_NS16550_SERIAL 89 #define CONFIG_SYS_NS16550_SERIAL
80 #define CONFIG_SYS_NS16550_REG_SIZE 1 90 #define CONFIG_SYS_NS16550_REG_SIZE 1
81 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 91 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
82 92
83 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 93 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
84 94
85 #define CONFIG_SYS_HZ 1000 95 #define CONFIG_SYS_HZ 1000
86 96
87 #define CONFIG_HWCONFIG 97 #define CONFIG_HWCONFIG
88 #define HWCONFIG_BUFFER_SIZE 128 98 #define HWCONFIG_BUFFER_SIZE 128
89 99
90 #include <config_distro_defaults.h> 100 #include <config_distro_defaults.h>
91 #ifndef CONFIG_SPL_BUILD 101 #ifndef CONFIG_SPL_BUILD
92 #define BOOT_TARGET_DEVICES(func) \ 102 #define BOOT_TARGET_DEVICES(func) \
103 func(SCSI, scsi, 0) \
93 func(MMC, mmc, 0) \ 104 func(MMC, mmc, 0) \
94 func(USB, usb, 0) 105 func(USB, usb, 0)
95 #include <config_distro_bootcmd.h> 106 #include <config_distro_bootcmd.h>
96 #endif 107 #endif
97 108
98 /* Initial environment variables */ 109 /* Initial environment variables */
99 #define CONFIG_EXTRA_ENV_SETTINGS \ 110 #define CONFIG_EXTRA_ENV_SETTINGS \
100 "verify=no\0" \ 111 "verify=no\0" \
101 "loadaddr=0x80100000\0" \ 112 "loadaddr=0x80100000\0" \
102 "kernel_addr=0x100000\0" \ 113 "kernel_addr=0x100000\0" \
103 "fdt_high=0xffffffffffffffff\0" \ 114 "fdt_high=0xffffffffffffffff\0" \
104 "initrd_high=0xffffffffffffffff\0" \ 115 "initrd_high=0xffffffffffffffff\0" \
105 "kernel_start=0x1000000\0" \ 116 "kernel_start=0x1000000\0" \
106 "kernel_load=0xa0000000\0" \ 117 "kernel_load=0xa0000000\0" \
107 "kernel_size=0x2800000\0" \ 118 "kernel_size=0x2800000\0" \
108 119
109 #undef CONFIG_BOOTCOMMAND 120 #undef CONFIG_BOOTCOMMAND
110 #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ 121 #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
111 "$kernel_start $kernel_size && "\ 122 "$kernel_start $kernel_size && "\
112 "bootm $kernel_load" 123 "bootm $kernel_load"
113 124
114 /* Monitor Command Prompt */ 125 /* Monitor Command Prompt */
115 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 126 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
116 #define CONFIG_SYS_LONGHELP 127 #define CONFIG_SYS_LONGHELP
117 #define CONFIG_AUTO_COMPLETE 128 #define CONFIG_AUTO_COMPLETE
118 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 129 #define CONFIG_SYS_MAXARGS 64 /* max command args */
119 130
120 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 131 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
121 132
122 #include <asm/arch/soc.h> 133 #include <asm/arch/soc.h>
123 134
124 #endif /* __LS1012A_COMMON_H */ 135 #endif /* __LS1012A_COMMON_H */
125 136
include/configs/ls1012aqds.h
Diff comments   View file @ ae02cf0
1 /* 1 /*
2 * Copyright 2016 Freescale Semiconductor, Inc. 2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __LS1012AQDS_H__ 7 #ifndef __LS1012AQDS_H__
8 #define __LS1012AQDS_H__ 8 #define __LS1012AQDS_H__
9 9
10 #include "ls1012a_common.h" 10 #include "ls1012a_common.h"
11 11
12 /* DDR */ 12 /* DDR */
13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
15 #define CONFIG_NR_DRAM_BANKS 2 15 #define CONFIG_NR_DRAM_BANKS 2
16 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 16 #define CONFIG_SYS_SDRAM_SIZE 0x40000000
17 #define CONFIG_CMD_MEMINFO 17 #define CONFIG_CMD_MEMINFO
18 #define CONFIG_CMD_MEMTEST 18 #define CONFIG_CMD_MEMTEST
19 #define CONFIG_SYS_MEMTEST_START 0x80000000 19 #define CONFIG_SYS_MEMTEST_START 0x80000000
20 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 20 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
21 21
22 /* 22 /*
23 * QIXIS Definitions 23 * QIXIS Definitions
24 */ 24 */
25 #define CONFIG_FSL_QIXIS 25 #define CONFIG_FSL_QIXIS
26 26
27 #ifdef CONFIG_FSL_QIXIS 27 #ifdef CONFIG_FSL_QIXIS
28 #define CONFIG_QIXIS_I2C_ACCESS 28 #define CONFIG_QIXIS_I2C_ACCESS
29 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 29 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
30 #define QIXIS_LBMAP_BRDCFG_REG 0x04 30 #define QIXIS_LBMAP_BRDCFG_REG 0x04
31 #define QIXIS_LBMAP_SWITCH 6 31 #define QIXIS_LBMAP_SWITCH 6
32 #define QIXIS_LBMAP_MASK 0x08 32 #define QIXIS_LBMAP_MASK 0x08
33 #define QIXIS_LBMAP_SHIFT 0 33 #define QIXIS_LBMAP_SHIFT 0
34 #define QIXIS_LBMAP_DFLTBANK 0x00 34 #define QIXIS_LBMAP_DFLTBANK 0x00
35 #define QIXIS_LBMAP_ALTBANK 0x08 35 #define QIXIS_LBMAP_ALTBANK 0x08
36 #define QIXIS_RST_CTL_RESET 0x31 36 #define QIXIS_RST_CTL_RESET 0x31
37 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 37 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
38 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 38 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
39 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 39 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
40 #endif 40 #endif
41 41
42 /* 42 /*
43 * I2C bus multiplexer 43 * I2C bus multiplexer
44 */ 44 */
45 #define I2C_MUX_PCA_ADDR_PRI 0x77 45 #define I2C_MUX_PCA_ADDR_PRI 0x77
46 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 46 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
47 #define I2C_RETIMER_ADDR 0x18 47 #define I2C_RETIMER_ADDR 0x18
48 #define I2C_MUX_CH_DEFAULT 0x8 48 #define I2C_MUX_CH_DEFAULT 0x8
49 #define I2C_MUX_CH_CH7301 0xC 49 #define I2C_MUX_CH_CH7301 0xC
50 #define I2C_MUX_CH5 0xD 50 #define I2C_MUX_CH5 0xD
51 #define I2C_MUX_CH7 0xF 51 #define I2C_MUX_CH7 0xF
52 52
53 #define I2C_MUX_CH_VOL_MONITOR 0xa 53 #define I2C_MUX_CH_VOL_MONITOR 0xa
54 54
55 /* 55 /*
56 * RTC configuration 56 * RTC configuration
57 */ 57 */
58 #define RTC 58 #define RTC
59 #define CONFIG_RTC_PCF8563 1 59 #define CONFIG_RTC_PCF8563 1
60 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 60 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
61 61
62 /* EEPROM */ 62 /* EEPROM */
63 #define CONFIG_ID_EEPROM 63 #define CONFIG_ID_EEPROM
64 #define CONFIG_SYS_I2C_EEPROM_NXID 64 #define CONFIG_SYS_I2C_EEPROM_NXID
65 #define CONFIG_SYS_EEPROM_BUS_NUM 0 65 #define CONFIG_SYS_EEPROM_BUS_NUM 0
66 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 66 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
67 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 67 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
68 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 68 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
69 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 69 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
70 70
71 71
72 /* Voltage monitor on channel 2*/ 72 /* Voltage monitor on channel 2*/
73 #define I2C_VOL_MONITOR_ADDR 0x40 73 #define I2C_VOL_MONITOR_ADDR 0x40
74 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 74 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
75 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 75 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
76 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 76 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
77 77
78 /* DSPI */ 78 /* DSPI */
79 #define CONFIG_FSL_DSPI1 79 #define CONFIG_FSL_DSPI1
80 #define CONFIG_DEFAULT_SPI_BUS 1 80 #define CONFIG_DEFAULT_SPI_BUS 1
81 81
82 #define CONFIG_CMD_SPI 82 #define CONFIG_CMD_SPI
83 #define MMAP_DSPI DSPI1_BASE_ADDR 83 #define MMAP_DSPI DSPI1_BASE_ADDR
84 84
85 #define CONFIG_SYS_DSPI_CTAR0 1 85 #define CONFIG_SYS_DSPI_CTAR0 1
86 86
87 #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 87 #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
88 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 88 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
89 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 89 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
90 DSPI_CTAR_DT(0)) 90 DSPI_CTAR_DT(0))
91 #define CONFIG_SPI_FLASH_SST /* cs1 */ 91 #define CONFIG_SPI_FLASH_SST /* cs1 */
92 92
93 #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 93 #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
94 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 94 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
95 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ 95 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
96 DSPI_CTAR_DT(0)) 96 DSPI_CTAR_DT(0))
97 #define CONFIG_SPI_FLASH_STMICRO /* cs2 */ 97 #define CONFIG_SPI_FLASH_STMICRO /* cs2 */
98 98
99 #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 99 #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
100 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 100 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
101 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 101 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
102 DSPI_CTAR_DT(0)) 102 DSPI_CTAR_DT(0))
103 #define CONFIG_SPI_FLASH_EON /* cs3 */ 103 #define CONFIG_SPI_FLASH_EON /* cs3 */
104 104
105 #define CONFIG_SF_DEFAULT_SPEED 10000000 105 #define CONFIG_SF_DEFAULT_SPEED 10000000
106 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 106 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
107 #define CONFIG_SF_DEFAULT_BUS 1 107 #define CONFIG_SF_DEFAULT_BUS 1
108 #define CONFIG_SF_DEFAULT_CS 0 108 #define CONFIG_SF_DEFAULT_CS 0
109 109
110 /* MMC */ 110 /* MMC */
111 #ifdef CONFIG_MMC 111 #ifdef CONFIG_MMC
112 #define CONFIG_FSL_ESDHC 112 #define CONFIG_FSL_ESDHC
113 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 113 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
114 #endif 114 #endif
115 115
116 /* SATA */
117 #define CONFIG_SCSI_AHCI_PLAT
118
119 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
120
121 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
122 #define CONFIG_SYS_SCSI_MAX_LUN 1
123 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
124 CONFIG_SYS_SCSI_MAX_LUN)
125
126 #define CONFIG_PCIE1 /* PCIE controller 1 */ 116 #define CONFIG_PCIE1 /* PCIE controller 1 */
127 117
128 #define CONFIG_PCI_SCAN_SHOW 118 #define CONFIG_PCI_SCAN_SHOW
129 119
130 #define CONFIG_CMD_MEMINFO 120 #define CONFIG_CMD_MEMINFO
131 #define CONFIG_CMD_MEMTEST 121 #define CONFIG_CMD_MEMTEST
132 #define CONFIG_SYS_MEMTEST_START 0x80000000 122 #define CONFIG_SYS_MEMTEST_START 0x80000000
133 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 123 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
134 124
135 #define CONFIG_MISC_INIT_R 125 #define CONFIG_MISC_INIT_R
136 126
137 #endif /* __LS1012AQDS_H__ */ 127 #endif /* __LS1012AQDS_H__ */
138 128
include/configs/ls1012ardb.h
Diff comments   View file @ ae02cf0
1 /* 1 /*
2 * Copyright 2016 Freescale Semiconductor, Inc. 2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __LS1012ARDB_H__ 7 #ifndef __LS1012ARDB_H__
8 #define __LS1012ARDB_H__ 8 #define __LS1012ARDB_H__
9 9
10 #include "ls1012a_common.h" 10 #include "ls1012a_common.h"
11 11
12 /* DDR */ 12 /* DDR */
13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
15 #define CONFIG_NR_DRAM_BANKS 2 15 #define CONFIG_NR_DRAM_BANKS 2
16 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 16 #define CONFIG_SYS_SDRAM_SIZE 0x40000000
17 #define CONFIG_CMD_MEMINFO 17 #define CONFIG_CMD_MEMINFO
18 #define CONFIG_CMD_MEMTEST 18 #define CONFIG_CMD_MEMTEST
19 #define CONFIG_SYS_MEMTEST_START 0x80000000 19 #define CONFIG_SYS_MEMTEST_START 0x80000000
20 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 20 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
21 21
22 22
23 /* 23 /*
24 * I2C IO expander 24 * I2C IO expander
25 */ 25 */
26 26
27 #define I2C_MUX_IO_ADDR 0x24 27 #define I2C_MUX_IO_ADDR 0x24
28 #define I2C_MUX_IO_0 0 28 #define I2C_MUX_IO_0 0
29 #define I2C_MUX_IO_1 1 29 #define I2C_MUX_IO_1 1
30 #define SW_BOOT_MASK 0x03 30 #define SW_BOOT_MASK 0x03
31 #define SW_BOOT_EMU 0x02 31 #define SW_BOOT_EMU 0x02
32 #define SW_BOOT_BANK1 0x00 32 #define SW_BOOT_BANK1 0x00
33 #define SW_BOOT_BANK2 0x01 33 #define SW_BOOT_BANK2 0x01
34 #define SW_REV_MASK 0xF8 34 #define SW_REV_MASK 0xF8
35 #define SW_REV_A 0xF8 35 #define SW_REV_A 0xF8
36 #define SW_REV_B 0xF0 36 #define SW_REV_B 0xF0
37 #define SW_REV_C 0xE8 37 #define SW_REV_C 0xE8
38 #define SW_REV_C1 0xE0 38 #define SW_REV_C1 0xE0
39 #define SW_REV_C2 0xD8 39 #define SW_REV_C2 0xD8
40 #define SW_REV_D 0xD0 40 #define SW_REV_D 0xD0
41 #define SW_REV_E 0xC8 41 #define SW_REV_E 0xC8
42 42
43 /* MMC */ 43 /* MMC */
44 #ifdef CONFIG_MMC 44 #ifdef CONFIG_MMC
45 #define CONFIG_FSL_ESDHC 45 #define CONFIG_FSL_ESDHC
46 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 46 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
47 #endif 47 #endif
48 48
49 /* SATA */
50 #define CONFIG_SCSI_AHCI_PLAT
51
52 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
53
54 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
55 #define CONFIG_SYS_SCSI_MAX_LUN 1
56 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
57 CONFIG_SYS_SCSI_MAX_LUN)
58 49
59 #define CONFIG_PCIE1 /* PCIE controller 1 */ 50 #define CONFIG_PCIE1 /* PCIE controller 1 */
60 51
61 #define CONFIG_PCI_SCAN_SHOW 52 #define CONFIG_PCI_SCAN_SHOW
62 53
63 #define CONFIG_CMD_MEMINFO 54 #define CONFIG_CMD_MEMINFO
64 #define CONFIG_CMD_MEMTEST 55 #define CONFIG_CMD_MEMTEST
65 #define CONFIG_SYS_MEMTEST_START 0x80000000 56 #define CONFIG_SYS_MEMTEST_START 0x80000000
66 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 57 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
67 58
68 #undef CONFIG_EXTRA_ENV_SETTINGS 59 #undef CONFIG_EXTRA_ENV_SETTINGS
69 #define CONFIG_EXTRA_ENV_SETTINGS \ 60 #define CONFIG_EXTRA_ENV_SETTINGS \
70 "verify=no\0" \ 61 "verify=no\0" \
71 "fdt_high=0xffffffffffffffff\0" \ 62 "fdt_high=0xffffffffffffffff\0" \
72 "initrd_high=0xffffffffffffffff\0" \ 63 "initrd_high=0xffffffffffffffff\0" \
73 "fdt_addr=0x00f00000\0" \ 64 "fdt_addr=0x00f00000\0" \
74 "kernel_addr=0x01000000\0" \ 65 "kernel_addr=0x01000000\0" \
75 "scriptaddr=0x80000000\0" \ 66 "scriptaddr=0x80000000\0" \
76 "fdtheader_addr_r=0x80100000\0" \ 67 "fdtheader_addr_r=0x80100000\0" \
77 "kernelheader_addr_r=0x80200000\0" \ 68 "kernelheader_addr_r=0x80200000\0" \
78 "kernel_addr_r=0x81000000\0" \ 69 "kernel_addr_r=0x81000000\0" \
79 "fdt_addr_r=0x90000000\0" \ 70 "fdt_addr_r=0x90000000\0" \
80 "load_addr=0xa0000000\0" \ 71 "load_addr=0xa0000000\0" \
81 "kernel_size=0x2800000\0" \ 72 "kernel_size=0x2800000\0" \
82 "console=ttyS0,115200\0" \ 73 "console=ttyS0,115200\0" \
83 BOOTENV \ 74 BOOTENV \
84 "boot_scripts=ls1012ardb_boot.scr\0" \ 75 "boot_scripts=ls1012ardb_boot.scr\0" \
85 "scan_dev_for_boot_part=" \ 76 "scan_dev_for_boot_part=" \
86 "part list ${devtype} ${devnum} devplist; " \ 77 "part list ${devtype} ${devnum} devplist; " \
87 "env exists devplist || setenv devplist 1; " \ 78 "env exists devplist || setenv devplist 1; " \
88 "for distro_bootpart in ${devplist}; do " \ 79 "for distro_bootpart in ${devplist}; do " \
89 "if fstype ${devtype} " \ 80 "if fstype ${devtype} " \
90 "${devnum}:${distro_bootpart} " \ 81 "${devnum}:${distro_bootpart} " \
91 "bootfstype; then " \ 82 "bootfstype; then " \
92 "run scan_dev_for_boot; " \ 83 "run scan_dev_for_boot; " \
93 "fi; " \ 84 "fi; " \
94 "done\0" \ 85 "done\0" \
95 "scan_dev_for_boot=" \ 86 "scan_dev_for_boot=" \
96 "echo Scanning ${devtype} " \ 87 "echo Scanning ${devtype} " \
97 "${devnum}:${distro_bootpart}...; " \ 88 "${devnum}:${distro_bootpart}...; " \
98 "for prefix in ${boot_prefixes}; do " \ 89 "for prefix in ${boot_prefixes}; do " \
99 "run scan_dev_for_scripts; " \ 90 "run scan_dev_for_scripts; " \
100 "done;" \ 91 "done;" \
101 "\0" \ 92 "\0" \
102 "installer=load mmc 0:2 $load_addr " \ 93 "installer=load mmc 0:2 $load_addr " \
103 "/flex_installer_arm64.itb; " \ 94 "/flex_installer_arm64.itb; " \
104 "bootm $load_addr#$board\0" \ 95 "bootm $load_addr#$board\0" \
105 "qspi_bootcmd=echo Trying load from qspi..;" \ 96 "qspi_bootcmd=echo Trying load from qspi..;" \
106 "sf probe && sf read $load_addr " \ 97 "sf probe && sf read $load_addr " \
107 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" 98 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"
108 99
109 #undef CONFIG_BOOTCOMMAND 100 #undef CONFIG_BOOTCOMMAND
110 #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" 101 #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
111 102
112 #include <asm/fsl_secure_boot.h> 103 #include <asm/fsl_secure_boot.h>
113 104
114 #endif /* __LS1012ARDB_H__ */ 105 #endif /* __LS1012ARDB_H__ */
115 106