Commit b2868187f46ce2d00f90139287661ace1af64ac2
Committed by
Andreas Bießmann
Andreas Bießmann
1 parent
b719a08863
Exists in
v2017.01-smarct4x
and in
37 other branches
ARM: atmel: switch at91sam9263ek to generic board
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Showing 1 changed file with 2 additions and 0 deletions Inline Diff
include/configs/at91sam9263ek.h
| 1 | /* | 1 | /* |
| 2 | * (C) Copyright 2007-2008 | 2 | * (C) Copyright 2007-2008 |
| 3 | * Stelian Pop <stelian@popies.net> | 3 | * Stelian Pop <stelian@popies.net> |
| 4 | * Lead Tech Design <www.leadtechdesign.com> | 4 | * Lead Tech Design <www.leadtechdesign.com> |
| 5 | * | 5 | * |
| 6 | * Configuation settings for the AT91SAM9263EK board. | 6 | * Configuation settings for the AT91SAM9263EK board. |
| 7 | * | 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #ifndef __CONFIG_H | 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H | 12 | #define __CONFIG_H |
| 13 | 13 | ||
| 14 | /* | 14 | /* |
| 15 | * SoC must be defined first, before hardware.h is included. | 15 | * SoC must be defined first, before hardware.h is included. |
| 16 | * In this case SoC is defined in boards.cfg. | 16 | * In this case SoC is defined in boards.cfg. |
| 17 | */ | 17 | */ |
| 18 | #include <asm/hardware.h> | 18 | #include <asm/hardware.h> |
| 19 | 19 | ||
| 20 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH | 20 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH |
| 21 | #define CONFIG_SYS_TEXT_BASE 0x21F00000 | 21 | #define CONFIG_SYS_TEXT_BASE 0x21F00000 |
| 22 | #else | 22 | #else |
| 23 | #define CONFIG_SYS_TEXT_BASE 0x0000000 | 23 | #define CONFIG_SYS_TEXT_BASE 0x0000000 |
| 24 | #endif | 24 | #endif |
| 25 | 25 | ||
| 26 | /* ARM asynchronous clock */ | 26 | /* ARM asynchronous clock */ |
| 27 | #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ | 27 | #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ |
| 28 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 | 28 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
| 29 | 29 | ||
| 30 | #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ | 30 | #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ |
| 31 | 31 | ||
| 32 | #define CONFIG_ARCH_CPU_INIT | 32 | #define CONFIG_ARCH_CPU_INIT |
| 33 | 33 | ||
| 34 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | 34 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 35 | #define CONFIG_SETUP_MEMORY_TAGS 1 | 35 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
| 36 | #define CONFIG_INITRD_TAG 1 | 36 | #define CONFIG_INITRD_TAG 1 |
| 37 | 37 | ||
| 38 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH | 38 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH |
| 39 | #define CONFIG_SKIP_LOWLEVEL_INIT | 39 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 40 | #else | 40 | #else |
| 41 | #define CONFIG_SYS_USE_NORFLASH | 41 | #define CONFIG_SYS_USE_NORFLASH |
| 42 | #endif | 42 | #endif |
| 43 | 43 | ||
| 44 | #define CONFIG_BOARD_EARLY_INIT_F | 44 | #define CONFIG_BOARD_EARLY_INIT_F |
| 45 | 45 | ||
| 46 | #define CONFIG_DISPLAY_CPUINFO | 46 | #define CONFIG_DISPLAY_CPUINFO |
| 47 | 47 | ||
| 48 | #define CONFIG_CMD_BOOTZ | 48 | #define CONFIG_CMD_BOOTZ |
| 49 | #define CONFIG_OF_LIBFDT | 49 | #define CONFIG_OF_LIBFDT |
| 50 | 50 | ||
| 51 | #define CONFIG_SYS_GENERIC_BOARD | ||
| 52 | |||
| 51 | /* | 53 | /* |
| 52 | * Hardware drivers | 54 | * Hardware drivers |
| 53 | */ | 55 | */ |
| 54 | #define CONFIG_ATMEL_LEGACY | 56 | #define CONFIG_ATMEL_LEGACY |
| 55 | #define CONFIG_AT91_GPIO 1 | 57 | #define CONFIG_AT91_GPIO 1 |
| 56 | #define CONFIG_AT91_GPIO_PULLUP 1 | 58 | #define CONFIG_AT91_GPIO_PULLUP 1 |
| 57 | 59 | ||
| 58 | /* serial console */ | 60 | /* serial console */ |
| 59 | #define CONFIG_ATMEL_USART | 61 | #define CONFIG_ATMEL_USART |
| 60 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | 62 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 61 | #define CONFIG_USART_ID ATMEL_ID_SYS | 63 | #define CONFIG_USART_ID ATMEL_ID_SYS |
| 62 | #define CONFIG_BAUDRATE 115200 | 64 | #define CONFIG_BAUDRATE 115200 |
| 63 | 65 | ||
| 64 | /* LCD */ | 66 | /* LCD */ |
| 65 | #define CONFIG_LCD 1 | 67 | #define CONFIG_LCD 1 |
| 66 | #define LCD_BPP LCD_COLOR8 | 68 | #define LCD_BPP LCD_COLOR8 |
| 67 | #define CONFIG_LCD_LOGO 1 | 69 | #define CONFIG_LCD_LOGO 1 |
| 68 | #undef LCD_TEST_PATTERN | 70 | #undef LCD_TEST_PATTERN |
| 69 | #define CONFIG_LCD_INFO 1 | 71 | #define CONFIG_LCD_INFO 1 |
| 70 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | 72 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 |
| 71 | #define CONFIG_SYS_WHITE_ON_BLACK 1 | 73 | #define CONFIG_SYS_WHITE_ON_BLACK 1 |
| 72 | #define CONFIG_ATMEL_LCD 1 | 74 | #define CONFIG_ATMEL_LCD 1 |
| 73 | #define CONFIG_ATMEL_LCD_BGR555 1 | 75 | #define CONFIG_ATMEL_LCD_BGR555 1 |
| 74 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | 76 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
| 75 | 77 | ||
| 76 | /* LED */ | 78 | /* LED */ |
| 77 | #define CONFIG_AT91_LED | 79 | #define CONFIG_AT91_LED |
| 78 | #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ | 80 | #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ |
| 79 | #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ | 81 | #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ |
| 80 | #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ | 82 | #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ |
| 81 | 83 | ||
| 82 | #define CONFIG_BOOTDELAY 3 | 84 | #define CONFIG_BOOTDELAY 3 |
| 83 | 85 | ||
| 84 | /* | 86 | /* |
| 85 | * BOOTP options | 87 | * BOOTP options |
| 86 | */ | 88 | */ |
| 87 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | 89 | #define CONFIG_BOOTP_BOOTFILESIZE 1 |
| 88 | #define CONFIG_BOOTP_BOOTPATH 1 | 90 | #define CONFIG_BOOTP_BOOTPATH 1 |
| 89 | #define CONFIG_BOOTP_GATEWAY 1 | 91 | #define CONFIG_BOOTP_GATEWAY 1 |
| 90 | #define CONFIG_BOOTP_HOSTNAME 1 | 92 | #define CONFIG_BOOTP_HOSTNAME 1 |
| 91 | 93 | ||
| 92 | /* | 94 | /* |
| 93 | * Command line configuration. | 95 | * Command line configuration. |
| 94 | */ | 96 | */ |
| 95 | #include <config_cmd_default.h> | 97 | #include <config_cmd_default.h> |
| 96 | #undef CONFIG_CMD_BDI | 98 | #undef CONFIG_CMD_BDI |
| 97 | #undef CONFIG_CMD_FPGA | 99 | #undef CONFIG_CMD_FPGA |
| 98 | #undef CONFIG_CMD_IMI | 100 | #undef CONFIG_CMD_IMI |
| 99 | #undef CONFIG_CMD_IMLS | 101 | #undef CONFIG_CMD_IMLS |
| 100 | #undef CONFIG_CMD_LOADS | 102 | #undef CONFIG_CMD_LOADS |
| 101 | #undef CONFIG_CMD_SOURCE | 103 | #undef CONFIG_CMD_SOURCE |
| 102 | 104 | ||
| 103 | #define CONFIG_CMD_PING 1 | 105 | #define CONFIG_CMD_PING 1 |
| 104 | #define CONFIG_CMD_DHCP 1 | 106 | #define CONFIG_CMD_DHCP 1 |
| 105 | #define CONFIG_CMD_NAND 1 | 107 | #define CONFIG_CMD_NAND 1 |
| 106 | #define CONFIG_CMD_MMC | 108 | #define CONFIG_CMD_MMC |
| 107 | #define CONFIG_CMD_USB 1 | 109 | #define CONFIG_CMD_USB 1 |
| 108 | 110 | ||
| 109 | /* SDRAM */ | 111 | /* SDRAM */ |
| 110 | #define CONFIG_NR_DRAM_BANKS 1 | 112 | #define CONFIG_NR_DRAM_BANKS 1 |
| 111 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 | 113 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 112 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 | 114 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 |
| 113 | 115 | ||
| 114 | #define CONFIG_SYS_INIT_SP_ADDR \ | 116 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 115 | (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) | 117 | (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) |
| 116 | 118 | ||
| 117 | /* DataFlash */ | 119 | /* DataFlash */ |
| 118 | #define CONFIG_ATMEL_DATAFLASH_SPI | 120 | #define CONFIG_ATMEL_DATAFLASH_SPI |
| 119 | #define CONFIG_HAS_DATAFLASH 1 | 121 | #define CONFIG_HAS_DATAFLASH 1 |
| 120 | #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) | 122 | #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) |
| 121 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 | 123 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 |
| 122 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ | 124 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ |
| 123 | #define AT91_SPI_CLK 15000000 | 125 | #define AT91_SPI_CLK 15000000 |
| 124 | #define DATAFLASH_TCSS (0x1a << 16) | 126 | #define DATAFLASH_TCSS (0x1a << 16) |
| 125 | #define DATAFLASH_TCHS (0x1 << 24) | 127 | #define DATAFLASH_TCHS (0x1 << 24) |
| 126 | 128 | ||
| 127 | /* MMC */ | 129 | /* MMC */ |
| 128 | #ifdef CONFIG_CMD_MMC | 130 | #ifdef CONFIG_CMD_MMC |
| 129 | #define CONFIG_MMC | 131 | #define CONFIG_MMC |
| 130 | #define CONFIG_GENERIC_MMC | 132 | #define CONFIG_GENERIC_MMC |
| 131 | #define CONFIG_GENERIC_ATMEL_MCI | 133 | #define CONFIG_GENERIC_ATMEL_MCI |
| 132 | #endif | 134 | #endif |
| 133 | 135 | ||
| 134 | /* FAT */ | 136 | /* FAT */ |
| 135 | #ifdef CONFIG_CMD_FAT | 137 | #ifdef CONFIG_CMD_FAT |
| 136 | #define CONFIG_DOS_PARTITION | 138 | #define CONFIG_DOS_PARTITION |
| 137 | #endif | 139 | #endif |
| 138 | 140 | ||
| 139 | /* NOR flash, if populated */ | 141 | /* NOR flash, if populated */ |
| 140 | #ifdef CONFIG_SYS_USE_NORFLASH | 142 | #ifdef CONFIG_SYS_USE_NORFLASH |
| 141 | #define CONFIG_SYS_FLASH_CFI 1 | 143 | #define CONFIG_SYS_FLASH_CFI 1 |
| 142 | #define CONFIG_FLASH_CFI_DRIVER 1 | 144 | #define CONFIG_FLASH_CFI_DRIVER 1 |
| 143 | #define PHYS_FLASH_1 0x10000000 | 145 | #define PHYS_FLASH_1 0x10000000 |
| 144 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | 146 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 145 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | 147 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 146 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | 148 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 147 | 149 | ||
| 148 | #define CONFIG_SYS_MONITOR_SEC 1:0-3 | 150 | #define CONFIG_SYS_MONITOR_SEC 1:0-3 |
| 149 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | 151 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 150 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | 152 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) |
| 151 | #define CONFIG_ENV_IS_IN_FLASH 1 | 153 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 152 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) | 154 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) |
| 153 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) | 155 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) |
| 154 | 156 | ||
| 155 | /* Address and size of Primary Environment Sector */ | 157 | /* Address and size of Primary Environment Sector */ |
| 156 | #define CONFIG_ENV_SIZE 0x10000 | 158 | #define CONFIG_ENV_SIZE 0x10000 |
| 157 | 159 | ||
| 158 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 160 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 159 | "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ | 161 | "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ |
| 160 | "update=" \ | 162 | "update=" \ |
| 161 | "protect off ${monitor_base} +${filesize};" \ | 163 | "protect off ${monitor_base} +${filesize};" \ |
| 162 | "erase ${monitor_base} +${filesize};" \ | 164 | "erase ${monitor_base} +${filesize};" \ |
| 163 | "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ | 165 | "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ |
| 164 | "protect on ${monitor_base} +${filesize}\0" | 166 | "protect on ${monitor_base} +${filesize}\0" |
| 165 | 167 | ||
| 166 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | 168 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 167 | #define MASTER_PLL_MUL 171 | 169 | #define MASTER_PLL_MUL 171 |
| 168 | #define MASTER_PLL_DIV 14 | 170 | #define MASTER_PLL_DIV 14 |
| 169 | #define MASTER_PLL_OUT 3 | 171 | #define MASTER_PLL_OUT 3 |
| 170 | 172 | ||
| 171 | /* clocks */ | 173 | /* clocks */ |
| 172 | #define CONFIG_SYS_MOR_VAL \ | 174 | #define CONFIG_SYS_MOR_VAL \ |
| 173 | (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) | 175 | (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) |
| 174 | #define CONFIG_SYS_PLLAR_VAL \ | 176 | #define CONFIG_SYS_PLLAR_VAL \ |
| 175 | (AT91_PMC_PLLAR_29 | \ | 177 | (AT91_PMC_PLLAR_29 | \ |
| 176 | AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ | 178 | AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ |
| 177 | AT91_PMC_PLLXR_PLLCOUNT(63) | \ | 179 | AT91_PMC_PLLXR_PLLCOUNT(63) | \ |
| 178 | AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ | 180 | AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ |
| 179 | AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) | 181 | AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) |
| 180 | 182 | ||
| 181 | /* PCK/2 = MCK Master Clock from PLLA */ | 183 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 182 | #define CONFIG_SYS_MCKR1_VAL \ | 184 | #define CONFIG_SYS_MCKR1_VAL \ |
| 183 | (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ | 185 | (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ |
| 184 | AT91_PMC_MCKR_MDIV_2) | 186 | AT91_PMC_MCKR_MDIV_2) |
| 185 | 187 | ||
| 186 | /* PCK/2 = MCK Master Clock from PLLA */ | 188 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 187 | #define CONFIG_SYS_MCKR2_VAL \ | 189 | #define CONFIG_SYS_MCKR2_VAL \ |
| 188 | (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ | 190 | (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ |
| 189 | AT91_PMC_MCKR_MDIV_2) | 191 | AT91_PMC_MCKR_MDIV_2) |
| 190 | 192 | ||
| 191 | /* define PDC[31:16] as DATA[31:16] */ | 193 | /* define PDC[31:16] as DATA[31:16] */ |
| 192 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 | 194 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 |
| 193 | /* no pull-up for D[31:16] */ | 195 | /* no pull-up for D[31:16] */ |
| 194 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 | 196 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 |
| 195 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ | 197 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ |
| 196 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ | 198 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ |
| 197 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ | 199 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ |
| 198 | AT91_MATRIX_CSA_EBI_CS1A) | 200 | AT91_MATRIX_CSA_EBI_CS1A) |
| 199 | 201 | ||
| 200 | /* SDRAM */ | 202 | /* SDRAM */ |
| 201 | /* SDRAMC_MR Mode register */ | 203 | /* SDRAMC_MR Mode register */ |
| 202 | #define CONFIG_SYS_SDRC_MR_VAL1 0 | 204 | #define CONFIG_SYS_SDRC_MR_VAL1 0 |
| 203 | /* SDRAMC_TR - Refresh Timer register */ | 205 | /* SDRAMC_TR - Refresh Timer register */ |
| 204 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C | 206 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C |
| 205 | /* SDRAMC_CR - Configuration register*/ | 207 | /* SDRAMC_CR - Configuration register*/ |
| 206 | #define CONFIG_SYS_SDRC_CR_VAL \ | 208 | #define CONFIG_SYS_SDRC_CR_VAL \ |
| 207 | (AT91_SDRAMC_NC_9 | \ | 209 | (AT91_SDRAMC_NC_9 | \ |
| 208 | AT91_SDRAMC_NR_13 | \ | 210 | AT91_SDRAMC_NR_13 | \ |
| 209 | AT91_SDRAMC_NB_4 | \ | 211 | AT91_SDRAMC_NB_4 | \ |
| 210 | AT91_SDRAMC_CAS_3 | \ | 212 | AT91_SDRAMC_CAS_3 | \ |
| 211 | AT91_SDRAMC_DBW_32 | \ | 213 | AT91_SDRAMC_DBW_32 | \ |
| 212 | (1 << 8) | /* Write Recovery Delay */ \ | 214 | (1 << 8) | /* Write Recovery Delay */ \ |
| 213 | (7 << 12) | /* Row Cycle Delay */ \ | 215 | (7 << 12) | /* Row Cycle Delay */ \ |
| 214 | (2 << 16) | /* Row Precharge Delay */ \ | 216 | (2 << 16) | /* Row Precharge Delay */ \ |
| 215 | (2 << 20) | /* Row to Column Delay */ \ | 217 | (2 << 20) | /* Row to Column Delay */ \ |
| 216 | (5 << 24) | /* Active to Precharge Delay */ \ | 218 | (5 << 24) | /* Active to Precharge Delay */ \ |
| 217 | (1 << 28)) /* Exit Self Refresh to Active Delay */ | 219 | (1 << 28)) /* Exit Self Refresh to Active Delay */ |
| 218 | 220 | ||
| 219 | /* Memory Device Register -> SDRAM */ | 221 | /* Memory Device Register -> SDRAM */ |
| 220 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM | 222 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM |
| 221 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE | 223 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE |
| 222 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ | 224 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ |
| 223 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH | 225 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH |
| 224 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ | 226 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ |
| 225 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ | 227 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ |
| 226 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ | 228 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ |
| 227 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ | 229 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ |
| 228 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ | 230 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ |
| 229 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ | 231 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ |
| 230 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ | 232 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ |
| 231 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ | 233 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ |
| 232 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR | 234 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR |
| 233 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ | 235 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ |
| 234 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL | 236 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL |
| 235 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ | 237 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ |
| 236 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ | 238 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ |
| 237 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ | 239 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ |
| 238 | 240 | ||
| 239 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ | 241 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ |
| 240 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ | 242 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ |
| 241 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ | 243 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ |
| 242 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) | 244 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) |
| 243 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ | 245 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
| 244 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ | 246 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ |
| 245 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) | 247 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) |
| 246 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ | 248 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
| 247 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) | 249 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
| 248 | #define CONFIG_SYS_SMC0_MODE0_VAL \ | 250 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
| 249 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ | 251 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
| 250 | AT91_SMC_MODE_DBW_16 | \ | 252 | AT91_SMC_MODE_DBW_16 | \ |
| 251 | AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) | 253 | AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) |
| 252 | 254 | ||
| 253 | /* user reset enable */ | 255 | /* user reset enable */ |
| 254 | #define CONFIG_SYS_RSTC_RMR_VAL \ | 256 | #define CONFIG_SYS_RSTC_RMR_VAL \ |
| 255 | (AT91_RSTC_KEY | \ | 257 | (AT91_RSTC_KEY | \ |
| 256 | AT91_RSTC_MR_URSTEN | \ | 258 | AT91_RSTC_MR_URSTEN | \ |
| 257 | AT91_RSTC_MR_ERSTL(15)) | 259 | AT91_RSTC_MR_ERSTL(15)) |
| 258 | 260 | ||
| 259 | /* Disable Watchdog */ | 261 | /* Disable Watchdog */ |
| 260 | #define CONFIG_SYS_WDTC_WDMR_VAL \ | 262 | #define CONFIG_SYS_WDTC_WDMR_VAL \ |
| 261 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ | 263 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
| 262 | AT91_WDT_MR_WDV(0xfff) | \ | 264 | AT91_WDT_MR_WDV(0xfff) | \ |
| 263 | AT91_WDT_MR_WDDIS | \ | 265 | AT91_WDT_MR_WDDIS | \ |
| 264 | AT91_WDT_MR_WDD(0xfff)) | 266 | AT91_WDT_MR_WDD(0xfff)) |
| 265 | 267 | ||
| 266 | #endif | 268 | #endif |
| 267 | 269 | ||
| 268 | #else | 270 | #else |
| 269 | #define CONFIG_SYS_NO_FLASH 1 | 271 | #define CONFIG_SYS_NO_FLASH 1 |
| 270 | #endif | 272 | #endif |
| 271 | 273 | ||
| 272 | /* NAND flash */ | 274 | /* NAND flash */ |
| 273 | #ifdef CONFIG_CMD_NAND | 275 | #ifdef CONFIG_CMD_NAND |
| 274 | #define CONFIG_NAND_ATMEL | 276 | #define CONFIG_NAND_ATMEL |
| 275 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | 277 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 276 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 | 278 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
| 277 | #define CONFIG_SYS_NAND_DBW_8 1 | 279 | #define CONFIG_SYS_NAND_DBW_8 1 |
| 278 | /* our ALE is AD21 */ | 280 | /* our ALE is AD21 */ |
| 279 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | 281 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 280 | /* our CLE is AD22 */ | 282 | /* our CLE is AD22 */ |
| 281 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | 283 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 282 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 | 284 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 |
| 283 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 | 285 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 |
| 284 | #endif | 286 | #endif |
| 285 | 287 | ||
| 286 | /* Ethernet */ | 288 | /* Ethernet */ |
| 287 | #define CONFIG_MACB 1 | 289 | #define CONFIG_MACB 1 |
| 288 | #define CONFIG_RMII 1 | 290 | #define CONFIG_RMII 1 |
| 289 | #define CONFIG_NET_RETRY_COUNT 20 | 291 | #define CONFIG_NET_RETRY_COUNT 20 |
| 290 | #define CONFIG_RESET_PHY_R 1 | 292 | #define CONFIG_RESET_PHY_R 1 |
| 291 | #define CONFIG_AT91_WANTS_COMMON_PHY | 293 | #define CONFIG_AT91_WANTS_COMMON_PHY |
| 292 | 294 | ||
| 293 | /* USB */ | 295 | /* USB */ |
| 294 | #define CONFIG_USB_ATMEL | 296 | #define CONFIG_USB_ATMEL |
| 295 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB | 297 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
| 296 | #define CONFIG_USB_OHCI_NEW 1 | 298 | #define CONFIG_USB_OHCI_NEW 1 |
| 297 | #define CONFIG_DOS_PARTITION 1 | 299 | #define CONFIG_DOS_PARTITION 1 |
| 298 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | 300 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
| 299 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ | 301 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ |
| 300 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" | 302 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" |
| 301 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | 303 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
| 302 | #define CONFIG_USB_STORAGE 1 | 304 | #define CONFIG_USB_STORAGE 1 |
| 303 | #define CONFIG_CMD_FAT 1 | 305 | #define CONFIG_CMD_FAT 1 |
| 304 | 306 | ||
| 305 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ | 307 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| 306 | 308 | ||
| 307 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | 309 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 308 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 | 310 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
| 309 | 311 | ||
| 310 | #ifdef CONFIG_SYS_USE_DATAFLASH | 312 | #ifdef CONFIG_SYS_USE_DATAFLASH |
| 311 | 313 | ||
| 312 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | 314 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
| 313 | #define CONFIG_ENV_IS_IN_DATAFLASH 1 | 315 | #define CONFIG_ENV_IS_IN_DATAFLASH 1 |
| 314 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) | 316 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
| 315 | #define CONFIG_ENV_OFFSET 0x4200 | 317 | #define CONFIG_ENV_OFFSET 0x4200 |
| 316 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) | 318 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) |
| 317 | #define CONFIG_ENV_SIZE 0x4200 | 319 | #define CONFIG_ENV_SIZE 0x4200 |
| 318 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" | 320 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" |
| 319 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | 321 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
| 320 | "root=/dev/mtdblock0 " \ | 322 | "root=/dev/mtdblock0 " \ |
| 321 | "mtdparts=atmel_nand:-(root) "\ | 323 | "mtdparts=atmel_nand:-(root) "\ |
| 322 | "rw rootfstype=jffs2" | 324 | "rw rootfstype=jffs2" |
| 323 | 325 | ||
| 324 | #elif CONFIG_SYS_USE_NANDFLASH | 326 | #elif CONFIG_SYS_USE_NANDFLASH |
| 325 | 327 | ||
| 326 | /* bootstrap + u-boot + env + linux in nandflash */ | 328 | /* bootstrap + u-boot + env + linux in nandflash */ |
| 327 | #define CONFIG_ENV_IS_IN_NAND 1 | 329 | #define CONFIG_ENV_IS_IN_NAND 1 |
| 328 | #define CONFIG_ENV_OFFSET 0xc0000 | 330 | #define CONFIG_ENV_OFFSET 0xc0000 |
| 329 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 | 331 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 |
| 330 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ | 332 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
| 331 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" | 333 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" |
| 332 | #define CONFIG_BOOTARGS \ | 334 | #define CONFIG_BOOTARGS \ |
| 333 | "console=ttyS0,115200 earlyprintk " \ | 335 | "console=ttyS0,115200 earlyprintk " \ |
| 334 | "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ | 336 | "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ |
| 335 | "256k(env),256k(env_redundant),256k(spare)," \ | 337 | "256k(env),256k(env_redundant),256k(spare)," \ |
| 336 | "512k(dtb),6M(kernel)ro,-(rootfs) " \ | 338 | "512k(dtb),6M(kernel)ro,-(rootfs) " \ |
| 337 | "root=/dev/mtdblock7 rw rootfstype=jffs2" | 339 | "root=/dev/mtdblock7 rw rootfstype=jffs2" |
| 338 | #endif | 340 | #endif |
| 339 | 341 | ||
| 340 | #define CONFIG_SYS_PROMPT "U-Boot> " | 342 | #define CONFIG_SYS_PROMPT "U-Boot> " |
| 341 | #define CONFIG_SYS_CBSIZE 256 | 343 | #define CONFIG_SYS_CBSIZE 256 |
| 342 | #define CONFIG_SYS_MAXARGS 16 | 344 | #define CONFIG_SYS_MAXARGS 16 |
| 343 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | 345 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 344 | #define CONFIG_SYS_LONGHELP 1 | 346 | #define CONFIG_SYS_LONGHELP 1 |
| 345 | #define CONFIG_CMDLINE_EDITING 1 | 347 | #define CONFIG_CMDLINE_EDITING 1 |
| 346 | #define CONFIG_AUTO_COMPLETE | 348 | #define CONFIG_AUTO_COMPLETE |
| 347 | #define CONFIG_SYS_HUSH_PARSER | 349 | #define CONFIG_SYS_HUSH_PARSER |
| 348 | 350 | ||
| 349 | /* | 351 | /* |
| 350 | * Size of malloc() pool | 352 | * Size of malloc() pool |
| 351 | */ | 353 | */ |
| 352 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) | 354 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
| 353 | 355 | ||
| 354 | #endif | 356 | #endif |
| 355 | 357 |