Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit b3a7ea0a131b082dd5aad6f2355a7172cf9cf981

Authored by Hou Zhiqiang
Committed by Priyanka Jain
1 parent 8ea9c15b8e
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

board: lx2160a: Make sure the RD tables address align to 64KB 

As the lower 16bit of the redistributor pending table is reserved
for describing the memory attributes, we must give a 64KB aligned
address to the GIC LPI initialization function.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Showing 1 changed file with 2 additions and 1 deletions Inline Diff

board/freescale/lx2160a/lx2160a.c
Diff comments   View file @ b3a7ea0
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018-2020 NXP 3 * Copyright 2018-2020 NXP
4 */ 4 */
5 5
6 #include <common.h> 6 #include <common.h>
7 #include <clock_legacy.h> 7 #include <clock_legacy.h>
8 #include <dm.h> 8 #include <dm.h>
9 #include <dm/platform_data/serial_pl01x.h> 9 #include <dm/platform_data/serial_pl01x.h>
10 #include <i2c.h> 10 #include <i2c.h>
11 #include <malloc.h> 11 #include <malloc.h>
12 #include <errno.h> 12 #include <errno.h>
13 #include <netdev.h> 13 #include <netdev.h>
14 #include <fsl_ddr.h> 14 #include <fsl_ddr.h>
15 #include <fsl_sec.h> 15 #include <fsl_sec.h>
16 #include <asm/io.h> 16 #include <asm/io.h>
17 #include <fdt_support.h> 17 #include <fdt_support.h>
18 #include <linux/libfdt.h> 18 #include <linux/libfdt.h>
19 #include <linux/delay.h> 19 #include <linux/delay.h>
20 #include <linux/sizes.h>
20 #include <fsl-mc/fsl_mc.h> 21 #include <fsl-mc/fsl_mc.h>
21 #include <env_internal.h> 22 #include <env_internal.h>
22 #include <efi_loader.h> 23 #include <efi_loader.h>
23 #include <asm/arch/mmu.h> 24 #include <asm/arch/mmu.h>
24 #include <hwconfig.h> 25 #include <hwconfig.h>
25 #include <asm/arch/clock.h> 26 #include <asm/arch/clock.h>
26 #include <asm/arch/config.h> 27 #include <asm/arch/config.h>
27 #include <asm/arch/fsl_serdes.h> 28 #include <asm/arch/fsl_serdes.h>
28 #include <asm/arch/soc.h> 29 #include <asm/arch/soc.h>
29 #include "../common/qixis.h" 30 #include "../common/qixis.h"
30 #include "../common/vid.h" 31 #include "../common/vid.h"
31 #include <fsl_immap.h> 32 #include <fsl_immap.h>
32 #include <asm/arch-fsl-layerscape/fsl_icid.h> 33 #include <asm/arch-fsl-layerscape/fsl_icid.h>
33 #include <asm/gic-v3.h> 34 #include <asm/gic-v3.h>
34 #include <cpu_func.h> 35 #include <cpu_func.h>
35 36
36 #ifdef CONFIG_EMC2305 37 #ifdef CONFIG_EMC2305
37 #include "../common/emc2305.h" 38 #include "../common/emc2305.h"
38 #endif 39 #endif
39 40
40 #define GIC_LPI_SIZE 0x200000 41 #define GIC_LPI_SIZE 0x200000
41 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 42 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
42 #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) 43 #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
43 #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) 44 #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
44 #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value) 45 #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
45 #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value) 46 #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
46 #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value) 47 #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
47 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value) 48 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
48 #define SDHC1_BASE_PMUX_DSPI 2 49 #define SDHC1_BASE_PMUX_DSPI 2
49 #define SDHC2_BASE_PMUX_DSPI 2 50 #define SDHC2_BASE_PMUX_DSPI 2
50 #define IIC5_PMUX_SPI3 3 51 #define IIC5_PMUX_SPI3 3
51 #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */ 52 #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
52 53
53 DECLARE_GLOBAL_DATA_PTR; 54 DECLARE_GLOBAL_DATA_PTR;
54 55
55 static struct pl01x_serial_platdata serial0 = { 56 static struct pl01x_serial_platdata serial0 = {
56 #if CONFIG_CONS_INDEX == 0 57 #if CONFIG_CONS_INDEX == 0
57 .base = CONFIG_SYS_SERIAL0, 58 .base = CONFIG_SYS_SERIAL0,
58 #elif CONFIG_CONS_INDEX == 1 59 #elif CONFIG_CONS_INDEX == 1
59 .base = CONFIG_SYS_SERIAL1, 60 .base = CONFIG_SYS_SERIAL1,
60 #else 61 #else
61 #error "Unsupported console index value." 62 #error "Unsupported console index value."
62 #endif 63 #endif
63 .type = TYPE_PL011, 64 .type = TYPE_PL011,
64 }; 65 };
65 66
66 U_BOOT_DEVICE(nxp_serial0) = { 67 U_BOOT_DEVICE(nxp_serial0) = {
67 .name = "serial_pl01x", 68 .name = "serial_pl01x",
68 .platdata = &serial0, 69 .platdata = &serial0,
69 }; 70 };
70 71
71 static struct pl01x_serial_platdata serial1 = { 72 static struct pl01x_serial_platdata serial1 = {
72 .base = CONFIG_SYS_SERIAL1, 73 .base = CONFIG_SYS_SERIAL1,
73 .type = TYPE_PL011, 74 .type = TYPE_PL011,
74 }; 75 };
75 76
76 U_BOOT_DEVICE(nxp_serial1) = { 77 U_BOOT_DEVICE(nxp_serial1) = {
77 .name = "serial_pl01x", 78 .name = "serial_pl01x",
78 .platdata = &serial1, 79 .platdata = &serial1,
79 }; 80 };
80 81
81 int select_i2c_ch_pca9547(u8 ch) 82 int select_i2c_ch_pca9547(u8 ch)
82 { 83 {
83 int ret; 84 int ret;
84 85
85 #ifndef CONFIG_DM_I2C 86 #ifndef CONFIG_DM_I2C
86 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 87 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
87 #else 88 #else
88 struct udevice *dev; 89 struct udevice *dev;
89 90
90 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); 91 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
91 if (!ret) 92 if (!ret)
92 ret = dm_i2c_write(dev, 0, &ch, 1); 93 ret = dm_i2c_write(dev, 0, &ch, 1);
93 #endif 94 #endif
94 if (ret) { 95 if (ret) {
95 puts("PCA: failed to select proper channel\n"); 96 puts("PCA: failed to select proper channel\n");
96 return ret; 97 return ret;
97 } 98 }
98 99
99 return 0; 100 return 0;
100 } 101 }
101 102
102 int select_i2c_ch_pca9547_sec(u8 ch) 103 int select_i2c_ch_pca9547_sec(u8 ch)
103 { 104 {
104 int ret; 105 int ret;
105 106
106 #ifndef CONFIG_DM_I2C 107 #ifndef CONFIG_DM_I2C
107 ret = i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &ch, 1); 108 ret = i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &ch, 1);
108 #else 109 #else
109 struct udevice *dev; 110 struct udevice *dev;
110 111
111 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_SEC, 1, &dev); 112 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_SEC, 1, &dev);
112 if (!ret) 113 if (!ret)
113 ret = dm_i2c_write(dev, 0, &ch, 1); 114 ret = dm_i2c_write(dev, 0, &ch, 1);
114 #endif 115 #endif
115 if (ret) { 116 if (ret) {
116 puts("PCA: failed to select proper channel\n"); 117 puts("PCA: failed to select proper channel\n");
117 return ret; 118 return ret;
118 } 119 }
119 120
120 return 0; 121 return 0;
121 } 122 }
122 123
123 static void uart_get_clock(void) 124 static void uart_get_clock(void)
124 { 125 {
125 serial0.clock = get_serial_clock(); 126 serial0.clock = get_serial_clock();
126 serial1.clock = get_serial_clock(); 127 serial1.clock = get_serial_clock();
127 } 128 }
128 129
129 int board_early_init_f(void) 130 int board_early_init_f(void)
130 { 131 {
131 #ifdef CONFIG_SYS_I2C_EARLY_INIT 132 #ifdef CONFIG_SYS_I2C_EARLY_INIT
132 i2c_early_init_f(); 133 i2c_early_init_f();
133 #endif 134 #endif
134 /* get required clock for UART IP */ 135 /* get required clock for UART IP */
135 uart_get_clock(); 136 uart_get_clock();
136 137
137 #ifdef CONFIG_EMC2305 138 #ifdef CONFIG_EMC2305
138 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305); 139 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
139 emc2305_init(I2C_EMC2305_ADDR); 140 emc2305_init(I2C_EMC2305_ADDR);
140 set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR); 141 set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
141 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 142 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
142 #endif 143 #endif
143 144
144 fsl_lsch3_early_init_f(); 145 fsl_lsch3_early_init_f();
145 return 0; 146 return 0;
146 } 147 }
147 148
148 #ifdef CONFIG_OF_BOARD_FIXUP 149 #ifdef CONFIG_OF_BOARD_FIXUP
149 int board_fix_fdt(void *fdt) 150 int board_fix_fdt(void *fdt)
150 { 151 {
151 char *reg_names, *reg_name; 152 char *reg_names, *reg_name;
152 int names_len, old_name_len, new_name_len, remaining_names_len; 153 int names_len, old_name_len, new_name_len, remaining_names_len;
153 struct str_map { 154 struct str_map {
154 char *old_str; 155 char *old_str;
155 char *new_str; 156 char *new_str;
156 } reg_names_map[] = { 157 } reg_names_map[] = {
157 { "ccsr", "dbi" }, 158 { "ccsr", "dbi" },
158 { "pf_ctrl", "ctrl" } 159 { "pf_ctrl", "ctrl" }
159 }; 160 };
160 int off = -1, i = 0; 161 int off = -1, i = 0;
161 162
162 if (IS_SVR_REV(get_svr(), 1, 0)) 163 if (IS_SVR_REV(get_svr(), 1, 0))
163 return 0; 164 return 0;
164 165
165 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie"); 166 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
166 while (off != -FDT_ERR_NOTFOUND) { 167 while (off != -FDT_ERR_NOTFOUND) {
167 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie", 168 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
168 strlen("fsl,ls-pcie") + 1); 169 strlen("fsl,ls-pcie") + 1);
169 170
170 reg_names = (char *)fdt_getprop(fdt, off, "reg-names", 171 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
171 &names_len); 172 &names_len);
172 if (!reg_names) 173 if (!reg_names)
173 continue; 174 continue;
174 175
175 reg_name = reg_names; 176 reg_name = reg_names;
176 remaining_names_len = names_len - (reg_name - reg_names); 177 remaining_names_len = names_len - (reg_name - reg_names);
177 i = 0; 178 i = 0;
178 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) { 179 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
179 old_name_len = strlen(reg_names_map[i].old_str); 180 old_name_len = strlen(reg_names_map[i].old_str);
180 new_name_len = strlen(reg_names_map[i].new_str); 181 new_name_len = strlen(reg_names_map[i].new_str);
181 if (memcmp(reg_name, reg_names_map[i].old_str, 182 if (memcmp(reg_name, reg_names_map[i].old_str,
182 old_name_len) == 0) { 183 old_name_len) == 0) {
183 /* first only leave required bytes for new_str 184 /* first only leave required bytes for new_str
184 * and copy rest of the string after it 185 * and copy rest of the string after it
185 */ 186 */
186 memcpy(reg_name + new_name_len, 187 memcpy(reg_name + new_name_len,
187 reg_name + old_name_len, 188 reg_name + old_name_len,
188 remaining_names_len - old_name_len); 189 remaining_names_len - old_name_len);
189 /* Now copy new_str */ 190 /* Now copy new_str */
190 memcpy(reg_name, reg_names_map[i].new_str, 191 memcpy(reg_name, reg_names_map[i].new_str,
191 new_name_len); 192 new_name_len);
192 names_len -= old_name_len; 193 names_len -= old_name_len;
193 names_len += new_name_len; 194 names_len += new_name_len;
194 i++; 195 i++;
195 } 196 }
196 197
197 reg_name = memchr(reg_name, '\0', remaining_names_len); 198 reg_name = memchr(reg_name, '\0', remaining_names_len);
198 if (!reg_name) 199 if (!reg_name)
199 break; 200 break;
200 201
201 reg_name += 1; 202 reg_name += 1;
202 203
203 remaining_names_len = names_len - 204 remaining_names_len = names_len -
204 (reg_name - reg_names); 205 (reg_name - reg_names);
205 } 206 }
206 207
207 fdt_setprop(fdt, off, "reg-names", reg_names, names_len); 208 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
208 off = fdt_node_offset_by_compatible(fdt, off, 209 off = fdt_node_offset_by_compatible(fdt, off,
209 "fsl,lx2160a-pcie"); 210 "fsl,lx2160a-pcie");
210 } 211 }
211 212
212 return 0; 213 return 0;
213 } 214 }
214 #endif 215 #endif
215 216
216 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 217 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
217 void esdhc_dspi_status_fixup(void *blob) 218 void esdhc_dspi_status_fixup(void *blob)
218 { 219 {
219 const char esdhc0_path[] = "/soc/esdhc@2140000"; 220 const char esdhc0_path[] = "/soc/esdhc@2140000";
220 const char esdhc1_path[] = "/soc/esdhc@2150000"; 221 const char esdhc1_path[] = "/soc/esdhc@2150000";
221 const char dspi0_path[] = "/soc/spi@2100000"; 222 const char dspi0_path[] = "/soc/spi@2100000";
222 const char dspi1_path[] = "/soc/spi@2110000"; 223 const char dspi1_path[] = "/soc/spi@2110000";
223 const char dspi2_path[] = "/soc/spi@2120000"; 224 const char dspi2_path[] = "/soc/spi@2120000";
224 225
225 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 226 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
226 u32 sdhc1_base_pmux; 227 u32 sdhc1_base_pmux;
227 u32 sdhc2_base_pmux; 228 u32 sdhc2_base_pmux;
228 u32 iic5_pmux; 229 u32 iic5_pmux;
229 230
230 /* Check RCW field sdhc1_base_pmux to enable/disable 231 /* Check RCW field sdhc1_base_pmux to enable/disable
231 * esdhc0/dspi0 DT node 232 * esdhc0/dspi0 DT node
232 */ 233 */
233 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 234 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
234 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; 235 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
235 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; 236 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
236 237
237 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { 238 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
238 do_fixup_by_path(blob, dspi0_path, "status", "okay", 239 do_fixup_by_path(blob, dspi0_path, "status", "okay",
239 sizeof("okay"), 1); 240 sizeof("okay"), 1);
240 do_fixup_by_path(blob, esdhc0_path, "status", "disabled", 241 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
241 sizeof("disabled"), 1); 242 sizeof("disabled"), 1);
242 } else { 243 } else {
243 do_fixup_by_path(blob, esdhc0_path, "status", "okay", 244 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
244 sizeof("okay"), 1); 245 sizeof("okay"), 1);
245 do_fixup_by_path(blob, dspi0_path, "status", "disabled", 246 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
246 sizeof("disabled"), 1); 247 sizeof("disabled"), 1);
247 } 248 }
248 249
249 /* Check RCW field sdhc2_base_pmux to enable/disable 250 /* Check RCW field sdhc2_base_pmux to enable/disable
250 * esdhc1/dspi1 DT node 251 * esdhc1/dspi1 DT node
251 */ 252 */
252 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) 253 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
253 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; 254 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
254 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; 255 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
255 256
256 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { 257 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
257 do_fixup_by_path(blob, dspi1_path, "status", "okay", 258 do_fixup_by_path(blob, dspi1_path, "status", "okay",
258 sizeof("okay"), 1); 259 sizeof("okay"), 1);
259 do_fixup_by_path(blob, esdhc1_path, "status", "disabled", 260 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
260 sizeof("disabled"), 1); 261 sizeof("disabled"), 1);
261 } else { 262 } else {
262 do_fixup_by_path(blob, esdhc1_path, "status", "okay", 263 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
263 sizeof("okay"), 1); 264 sizeof("okay"), 1);
264 do_fixup_by_path(blob, dspi1_path, "status", "disabled", 265 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
265 sizeof("disabled"), 1); 266 sizeof("disabled"), 1);
266 } 267 }
267 268
268 /* Check RCW field IIC5 to enable dspi2 DT node */ 269 /* Check RCW field IIC5 to enable dspi2 DT node */
269 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 270 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
270 & FSL_CHASSIS3_IIC5_PMUX_MASK; 271 & FSL_CHASSIS3_IIC5_PMUX_MASK;
271 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; 272 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
272 273
273 if (iic5_pmux == IIC5_PMUX_SPI3) 274 if (iic5_pmux == IIC5_PMUX_SPI3)
274 do_fixup_by_path(blob, dspi2_path, "status", "okay", 275 do_fixup_by_path(blob, dspi2_path, "status", "okay",
275 sizeof("okay"), 1); 276 sizeof("okay"), 1);
276 else 277 else
277 do_fixup_by_path(blob, dspi2_path, "status", "disabled", 278 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
278 sizeof("disabled"), 1); 279 sizeof("disabled"), 1);
279 } 280 }
280 #endif 281 #endif
281 282
282 int esdhc_status_fixup(void *blob, const char *compat) 283 int esdhc_status_fixup(void *blob, const char *compat)
283 { 284 {
284 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 285 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
285 /* Enable esdhc and dspi DT nodes based on RCW fields */ 286 /* Enable esdhc and dspi DT nodes based on RCW fields */
286 esdhc_dspi_status_fixup(blob); 287 esdhc_dspi_status_fixup(blob);
287 #else 288 #else
288 /* Enable both esdhc DT nodes for LX2160ARDB */ 289 /* Enable both esdhc DT nodes for LX2160ARDB */
289 do_fixup_by_compat(blob, compat, "status", "okay", 290 do_fixup_by_compat(blob, compat, "status", "okay",
290 sizeof("okay"), 1); 291 sizeof("okay"), 1);
291 #endif 292 #endif
292 return 0; 293 return 0;
293 } 294 }
294 295
295 #if defined(CONFIG_VID) 296 #if defined(CONFIG_VID)
296 int i2c_multiplexer_select_vid_channel(u8 channel) 297 int i2c_multiplexer_select_vid_channel(u8 channel)
297 { 298 {
298 return select_i2c_ch_pca9547(channel); 299 return select_i2c_ch_pca9547(channel);
299 } 300 }
300 301
301 int init_func_vid(void) 302 int init_func_vid(void)
302 { 303 {
303 int set_vid; 304 int set_vid;
304 305
305 if (IS_SVR_REV(get_svr(), 1, 0)) 306 if (IS_SVR_REV(get_svr(), 1, 0))
306 set_vid = adjust_vdd(800); 307 set_vid = adjust_vdd(800);
307 else 308 else
308 set_vid = adjust_vdd(0); 309 set_vid = adjust_vdd(0);
309 310
310 if (set_vid < 0) 311 if (set_vid < 0)
311 printf("core voltage not adjusted\n"); 312 printf("core voltage not adjusted\n");
312 313
313 return 0; 314 return 0;
314 } 315 }
315 #endif 316 #endif
316 317
317 int checkboard(void) 318 int checkboard(void)
318 { 319 {
319 enum boot_src src = get_boot_src(); 320 enum boot_src src = get_boot_src();
320 char buf[64]; 321 char buf[64];
321 u8 sw; 322 u8 sw;
322 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 323 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
323 int clock; 324 int clock;
324 static const char *const freq[] = {"100", "125", "156.25", 325 static const char *const freq[] = {"100", "125", "156.25",
325 "161.13", "322.26", "", "", "", 326 "161.13", "322.26", "", "", "",
326 "", "", "", "", "", "", "", 327 "", "", "", "", "", "", "",
327 "100 separate SSCG"}; 328 "100 separate SSCG"};
328 #endif 329 #endif
329 330
330 cpu_name(buf); 331 cpu_name(buf);
331 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 332 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
332 printf("Board: %s-QDS, ", buf); 333 printf("Board: %s-QDS, ", buf);
333 #else 334 #else
334 printf("Board: %s-RDB, ", buf); 335 printf("Board: %s-RDB, ", buf);
335 #endif 336 #endif
336 337
337 sw = QIXIS_READ(arch); 338 sw = QIXIS_READ(arch);
338 printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); 339 printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
339 340
340 if (src == BOOT_SOURCE_SD_MMC) { 341 if (src == BOOT_SOURCE_SD_MMC) {
341 puts("SD\n"); 342 puts("SD\n");
342 } else if (src == BOOT_SOURCE_SD_MMC2) { 343 } else if (src == BOOT_SOURCE_SD_MMC2) {
343 puts("eMMC\n"); 344 puts("eMMC\n");
344 } else { 345 } else {
345 sw = QIXIS_READ(brdcfg[0]); 346 sw = QIXIS_READ(brdcfg[0]);
346 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; 347 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
347 switch (sw) { 348 switch (sw) {
348 case 0: 349 case 0:
349 case 4: 350 case 4:
350 puts("FlexSPI DEV#0\n"); 351 puts("FlexSPI DEV#0\n");
351 break; 352 break;
352 case 1: 353 case 1:
353 puts("FlexSPI DEV#1\n"); 354 puts("FlexSPI DEV#1\n");
354 break; 355 break;
355 case 2: 356 case 2:
356 case 3: 357 case 3:
357 puts("FlexSPI EMU\n"); 358 puts("FlexSPI EMU\n");
358 break; 359 break;
359 default: 360 default:
360 printf("invalid setting, xmap: %d\n", sw); 361 printf("invalid setting, xmap: %d\n", sw);
361 break; 362 break;
362 } 363 }
363 } 364 }
364 #if defined(CONFIG_TARGET_LX2160ARDB) 365 #if defined(CONFIG_TARGET_LX2160ARDB)
365 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 366 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
366 367
367 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); 368 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
368 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); 369 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
369 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); 370 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
370 #else 371 #else
371 printf("FPGA: v%d (%s), build %d", 372 printf("FPGA: v%d (%s), build %d",
372 (int)QIXIS_READ(scver), qixis_read_tag(buf), 373 (int)QIXIS_READ(scver), qixis_read_tag(buf),
373 (int)qixis_read_minor()); 374 (int)qixis_read_minor());
374 /* the timestamp string contains "\n" at the end */ 375 /* the timestamp string contains "\n" at the end */
375 printf(" on %s", qixis_read_time(buf)); 376 printf(" on %s", qixis_read_time(buf));
376 377
377 puts("SERDES1 Reference : "); 378 puts("SERDES1 Reference : ");
378 sw = QIXIS_READ(brdcfg[2]); 379 sw = QIXIS_READ(brdcfg[2]);
379 clock = sw >> 4; 380 clock = sw >> 4;
380 printf("Clock1 = %sMHz ", freq[clock]); 381 printf("Clock1 = %sMHz ", freq[clock]);
381 #if defined(CONFIG_TARGET_LX2160AQDS) 382 #if defined(CONFIG_TARGET_LX2160AQDS)
382 clock = sw & 0x0f; 383 clock = sw & 0x0f;
383 printf("Clock2 = %sMHz", freq[clock]); 384 printf("Clock2 = %sMHz", freq[clock]);
384 #endif 385 #endif
385 sw = QIXIS_READ(brdcfg[3]); 386 sw = QIXIS_READ(brdcfg[3]);
386 puts("\nSERDES2 Reference : "); 387 puts("\nSERDES2 Reference : ");
387 clock = sw >> 4; 388 clock = sw >> 4;
388 printf("Clock1 = %sMHz ", freq[clock]); 389 printf("Clock1 = %sMHz ", freq[clock]);
389 clock = sw & 0x0f; 390 clock = sw & 0x0f;
390 printf("Clock2 = %sMHz\n", freq[clock]); 391 printf("Clock2 = %sMHz\n", freq[clock]);
391 #if defined(CONFIG_TARGET_LX2160AQDS) 392 #if defined(CONFIG_TARGET_LX2160AQDS)
392 sw = QIXIS_READ(brdcfg[12]); 393 sw = QIXIS_READ(brdcfg[12]);
393 puts("SERDES3 Reference : "); 394 puts("SERDES3 Reference : ");
394 clock = sw >> 4; 395 clock = sw >> 4;
395 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); 396 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
396 #endif 397 #endif
397 #endif 398 #endif
398 return 0; 399 return 0;
399 } 400 }
400 401
401 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 402 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
402 /* 403 /*
403 * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. 404 * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
404 */ 405 */
405 u8 qixis_esdhc_detect_quirk(void) 406 u8 qixis_esdhc_detect_quirk(void)
406 { 407 {
407 /* 408 /*
408 * SDHC1 Card ID: 409 * SDHC1 Card ID:
409 * Specifies the type of card installed in the SDHC1 adapter slot. 410 * Specifies the type of card installed in the SDHC1 adapter slot.
410 * 000= (reserved) 411 * 000= (reserved)
411 * 001= eMMC V4.5 adapter is installed. 412 * 001= eMMC V4.5 adapter is installed.
412 * 010= SD/MMC 3.3V adapter is installed. 413 * 010= SD/MMC 3.3V adapter is installed.
413 * 011= eMMC V4.4 adapter is installed. 414 * 011= eMMC V4.4 adapter is installed.
414 * 100= eMMC V5.0 adapter is installed. 415 * 100= eMMC V5.0 adapter is installed.
415 * 101= MMC card/Legacy (3.3V) adapter is installed. 416 * 101= MMC card/Legacy (3.3V) adapter is installed.
416 * 110= SDCard V2/V3 adapter installed. 417 * 110= SDCard V2/V3 adapter installed.
417 * 111= no adapter is installed. 418 * 111= no adapter is installed.
418 */ 419 */
419 return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) != 420 return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
420 QIXIS_ESDHC_NO_ADAPTER); 421 QIXIS_ESDHC_NO_ADAPTER);
421 } 422 }
422 423
423 static void esdhc_adapter_card_ident(void) 424 static void esdhc_adapter_card_ident(void)
424 { 425 {
425 u8 card_id, val; 426 u8 card_id, val;
426 427
427 val = QIXIS_READ(sdhc1); 428 val = QIXIS_READ(sdhc1);
428 card_id = val & QIXIS_SDID_MASK; 429 card_id = val & QIXIS_SDID_MASK;
429 430
430 switch (card_id) { 431 switch (card_id) {
431 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 432 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
432 /* Power cycle to card */ 433 /* Power cycle to card */
433 val &= ~QIXIS_SDHC1_S1V3; 434 val &= ~QIXIS_SDHC1_S1V3;
434 QIXIS_WRITE(sdhc1, val); 435 QIXIS_WRITE(sdhc1, val);
435 mdelay(1); 436 mdelay(1);
436 val |= QIXIS_SDHC1_S1V3; 437 val |= QIXIS_SDHC1_S1V3;
437 QIXIS_WRITE(sdhc1, val); 438 QIXIS_WRITE(sdhc1, val);
438 /* Route to SDHC1_VS */ 439 /* Route to SDHC1_VS */
439 val = QIXIS_READ(brdcfg[11]); 440 val = QIXIS_READ(brdcfg[11]);
440 val |= QIXIS_SDHC1_VS; 441 val |= QIXIS_SDHC1_VS;
441 QIXIS_WRITE(brdcfg[11], val); 442 QIXIS_WRITE(brdcfg[11], val);
442 break; 443 break;
443 default: 444 default:
444 break; 445 break;
445 } 446 }
446 } 447 }
447 448
448 int config_board_mux(void) 449 int config_board_mux(void)
449 { 450 {
450 u8 reg11, reg5, reg13; 451 u8 reg11, reg5, reg13;
451 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 452 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
452 u32 sdhc1_base_pmux; 453 u32 sdhc1_base_pmux;
453 u32 sdhc2_base_pmux; 454 u32 sdhc2_base_pmux;
454 u32 iic5_pmux; 455 u32 iic5_pmux;
455 456
456 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}. 457 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
457 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}. 458 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
458 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}. 459 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
459 * Qixis and remote systems are isolated from the I2C1 bus. 460 * Qixis and remote systems are isolated from the I2C1 bus.
460 * Processor connections are still available. 461 * Processor connections are still available.
461 * SPI2 CS2_B controls EN25S64 SPI memory device. 462 * SPI2 CS2_B controls EN25S64 SPI memory device.
462 * SPI3 CS2_B controls EN25S64 SPI memory device. 463 * SPI3 CS2_B controls EN25S64 SPI memory device.
463 * EC2 connects to PHY #2 using RGMII protocol. 464 * EC2 connects to PHY #2 using RGMII protocol.
464 * CLK_OUT connects to FPGA for clock measurement. 465 * CLK_OUT connects to FPGA for clock measurement.
465 */ 466 */
466 467
467 reg5 = QIXIS_READ(brdcfg[5]); 468 reg5 = QIXIS_READ(brdcfg[5]);
468 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40); 469 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
469 QIXIS_WRITE(brdcfg[5], reg5); 470 QIXIS_WRITE(brdcfg[5], reg5);
470 471
471 /* Check RCW field sdhc1_base_pmux 472 /* Check RCW field sdhc1_base_pmux
472 * esdhc0 : sdhc1_base_pmux = 0 473 * esdhc0 : sdhc1_base_pmux = 0
473 * dspi0 : sdhc1_base_pmux = 2 474 * dspi0 : sdhc1_base_pmux = 2
474 */ 475 */
475 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 476 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
476 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; 477 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
477 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; 478 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
478 479
479 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { 480 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
480 reg11 = QIXIS_READ(brdcfg[11]); 481 reg11 = QIXIS_READ(brdcfg[11]);
481 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40); 482 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
482 QIXIS_WRITE(brdcfg[11], reg11); 483 QIXIS_WRITE(brdcfg[11], reg11);
483 } else { 484 } else {
484 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot. 485 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
485 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot. 486 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
486 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot. 487 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
487 */ 488 */
488 reg11 = QIXIS_READ(brdcfg[11]); 489 reg11 = QIXIS_READ(brdcfg[11]);
489 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11); 490 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
490 QIXIS_WRITE(brdcfg[11], reg11); 491 QIXIS_WRITE(brdcfg[11], reg11);
491 } 492 }
492 493
493 /* Check RCW field sdhc2_base_pmux 494 /* Check RCW field sdhc2_base_pmux
494 * esdhc1 : sdhc2_base_pmux = 0 (default) 495 * esdhc1 : sdhc2_base_pmux = 0 (default)
495 * dspi1 : sdhc2_base_pmux = 2 496 * dspi1 : sdhc2_base_pmux = 2
496 */ 497 */
497 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) 498 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
498 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; 499 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
499 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; 500 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
500 501
501 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { 502 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
502 reg13 = QIXIS_READ(brdcfg[13]); 503 reg13 = QIXIS_READ(brdcfg[13]);
503 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01); 504 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
504 QIXIS_WRITE(brdcfg[13], reg13); 505 QIXIS_WRITE(brdcfg[13], reg13);
505 } else { 506 } else {
506 reg13 = QIXIS_READ(brdcfg[13]); 507 reg13 = QIXIS_READ(brdcfg[13]);
507 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00); 508 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
508 QIXIS_WRITE(brdcfg[13], reg13); 509 QIXIS_WRITE(brdcfg[13], reg13);
509 } 510 }
510 511
511 /* Check RCW field IIC5 to enable dspi2 DT nodei 512 /* Check RCW field IIC5 to enable dspi2 DT nodei
512 * dspi2: IIC5 = 3 513 * dspi2: IIC5 = 3
513 */ 514 */
514 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 515 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
515 & FSL_CHASSIS3_IIC5_PMUX_MASK; 516 & FSL_CHASSIS3_IIC5_PMUX_MASK;
516 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; 517 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
517 518
518 if (iic5_pmux == IIC5_PMUX_SPI3) { 519 if (iic5_pmux == IIC5_PMUX_SPI3) {
519 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */ 520 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
520 reg11 = QIXIS_READ(brdcfg[11]); 521 reg11 = QIXIS_READ(brdcfg[11]);
521 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10); 522 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
522 QIXIS_WRITE(brdcfg[11], reg11); 523 QIXIS_WRITE(brdcfg[11], reg11);
523 524
524 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere. 525 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
525 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }. 526 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
526 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}. 527 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
527 */ 528 */
528 reg11 = QIXIS_READ(brdcfg[11]); 529 reg11 = QIXIS_READ(brdcfg[11]);
529 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01); 530 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
530 QIXIS_WRITE(brdcfg[11], reg11); 531 QIXIS_WRITE(brdcfg[11], reg11);
531 } else { 532 } else {
532 /* 533 /*
533 * If {SDHC1_DAT4} has been configured to route to SDHC1_VS, 534 * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
534 * do not change it. 535 * do not change it.
535 * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot. 536 * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
536 */ 537 */
537 reg11 = QIXIS_READ(brdcfg[11]); 538 reg11 = QIXIS_READ(brdcfg[11]);
538 if ((reg11 & 0x30) != 0x30) { 539 if ((reg11 & 0x30) != 0x30) {
539 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00); 540 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
540 QIXIS_WRITE(brdcfg[11], reg11); 541 QIXIS_WRITE(brdcfg[11], reg11);
541 } 542 }
542 543
543 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot. 544 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
544 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot. 545 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
545 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot. 546 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
546 */ 547 */
547 reg11 = QIXIS_READ(brdcfg[11]); 548 reg11 = QIXIS_READ(brdcfg[11]);
548 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00); 549 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
549 QIXIS_WRITE(brdcfg[11], reg11); 550 QIXIS_WRITE(brdcfg[11], reg11);
550 } 551 }
551 552
552 return 0; 553 return 0;
553 } 554 }
554 555
555 int board_early_init_r(void) 556 int board_early_init_r(void)
556 { 557 {
557 esdhc_adapter_card_ident(); 558 esdhc_adapter_card_ident();
558 return 0; 559 return 0;
559 } 560 }
560 #elif defined(CONFIG_TARGET_LX2160ARDB) 561 #elif defined(CONFIG_TARGET_LX2160ARDB)
561 int config_board_mux(void) 562 int config_board_mux(void)
562 { 563 {
563 u8 brdcfg; 564 u8 brdcfg;
564 565
565 brdcfg = QIXIS_READ(brdcfg[4]); 566 brdcfg = QIXIS_READ(brdcfg[4]);
566 /* The BRDCFG4 register controls general board configuration. 567 /* The BRDCFG4 register controls general board configuration.
567 *|-------------------------------------------| 568 *|-------------------------------------------|
568 *|Field | Function | 569 *|Field | Function |
569 *|-------------------------------------------| 570 *|-------------------------------------------|
570 *|5 | CAN I/O Enable (net CFG_CAN_EN_B):| 571 *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
571 *|CAN_EN | 0= CAN transceivers are disabled. | 572 *|CAN_EN | 0= CAN transceivers are disabled. |
572 *| | 1= CAN transceivers are enabled. | 573 *| | 1= CAN transceivers are enabled. |
573 *|-------------------------------------------| 574 *|-------------------------------------------|
574 */ 575 */
575 brdcfg |= BIT_MASK(5); 576 brdcfg |= BIT_MASK(5);
576 QIXIS_WRITE(brdcfg[4], brdcfg); 577 QIXIS_WRITE(brdcfg[4], brdcfg);
577 578
578 return 0; 579 return 0;
579 } 580 }
580 #else 581 #else
581 int config_board_mux(void) 582 int config_board_mux(void)
582 { 583 {
583 return 0; 584 return 0;
584 } 585 }
585 #endif 586 #endif
586 587
587 unsigned long get_board_sys_clk(void) 588 unsigned long get_board_sys_clk(void)
588 { 589 {
589 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 590 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
590 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 591 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
591 592
592 switch (sysclk_conf & 0x03) { 593 switch (sysclk_conf & 0x03) {
593 case QIXIS_SYSCLK_100: 594 case QIXIS_SYSCLK_100:
594 return 100000000; 595 return 100000000;
595 case QIXIS_SYSCLK_125: 596 case QIXIS_SYSCLK_125:
596 return 125000000; 597 return 125000000;
597 case QIXIS_SYSCLK_133: 598 case QIXIS_SYSCLK_133:
598 return 133333333; 599 return 133333333;
599 } 600 }
600 return 100000000; 601 return 100000000;
601 #else 602 #else
602 return 100000000; 603 return 100000000;
603 #endif 604 #endif
604 } 605 }
605 606
606 unsigned long get_board_ddr_clk(void) 607 unsigned long get_board_ddr_clk(void)
607 { 608 {
608 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 609 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
609 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 610 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
610 611
611 switch ((ddrclk_conf & 0x30) >> 4) { 612 switch ((ddrclk_conf & 0x30) >> 4) {
612 case QIXIS_DDRCLK_100: 613 case QIXIS_DDRCLK_100:
613 return 100000000; 614 return 100000000;
614 case QIXIS_DDRCLK_125: 615 case QIXIS_DDRCLK_125:
615 return 125000000; 616 return 125000000;
616 case QIXIS_DDRCLK_133: 617 case QIXIS_DDRCLK_133:
617 return 133333333; 618 return 133333333;
618 } 619 }
619 return 100000000; 620 return 100000000;
620 #else 621 #else
621 return 100000000; 622 return 100000000;
622 #endif 623 #endif
623 } 624 }
624 625
625 int board_init(void) 626 int board_init(void)
626 { 627 {
627 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) 628 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
628 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 629 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
629 #endif 630 #endif
630 #ifdef CONFIG_ENV_IS_NOWHERE 631 #ifdef CONFIG_ENV_IS_NOWHERE
631 gd->env_addr = (ulong)&default_environment[0]; 632 gd->env_addr = (ulong)&default_environment[0];
632 #endif 633 #endif
633 634
634 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 635 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
635 636
636 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) 637 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
637 /* invert AQR107 IRQ pins polarity */ 638 /* invert AQR107 IRQ pins polarity */
638 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); 639 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
639 #endif 640 #endif
640 641
641 #ifdef CONFIG_FSL_CAAM 642 #ifdef CONFIG_FSL_CAAM
642 sec_init(); 643 sec_init();
643 #endif 644 #endif
644 645
645 return 0; 646 return 0;
646 } 647 }
647 648
648 void detail_board_ddr_info(void) 649 void detail_board_ddr_info(void)
649 { 650 {
650 int i; 651 int i;
651 u64 ddr_size = 0; 652 u64 ddr_size = 0;
652 653
653 puts("\nDDR "); 654 puts("\nDDR ");
654 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 655 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
655 ddr_size += gd->bd->bi_dram[i].size; 656 ddr_size += gd->bd->bi_dram[i].size;
656 print_size(ddr_size, ""); 657 print_size(ddr_size, "");
657 print_ddr_info(0); 658 print_ddr_info(0);
658 } 659 }
659 660
660 #ifdef CONFIG_MISC_INIT_R 661 #ifdef CONFIG_MISC_INIT_R
661 int misc_init_r(void) 662 int misc_init_r(void)
662 { 663 {
663 config_board_mux(); 664 config_board_mux();
664 665
665 return 0; 666 return 0;
666 } 667 }
667 #endif 668 #endif
668 669
669 #ifdef CONFIG_FSL_MC_ENET 670 #ifdef CONFIG_FSL_MC_ENET
670 extern int fdt_fixup_board_phy(void *fdt); 671 extern int fdt_fixup_board_phy(void *fdt);
671 672
672 void fdt_fixup_board_enet(void *fdt) 673 void fdt_fixup_board_enet(void *fdt)
673 { 674 {
674 int offset; 675 int offset;
675 676
676 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 677 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
677 678
678 if (offset < 0) 679 if (offset < 0)
679 offset = fdt_path_offset(fdt, "/fsl-mc"); 680 offset = fdt_path_offset(fdt, "/fsl-mc");
680 681
681 if (offset < 0) { 682 if (offset < 0) {
682 printf("%s: fsl-mc node not found in device tree (error %d)\n", 683 printf("%s: fsl-mc node not found in device tree (error %d)\n",
683 __func__, offset); 684 __func__, offset);
684 return; 685 return;
685 } 686 }
686 687
687 if (get_mc_boot_status() == 0 && 688 if (get_mc_boot_status() == 0 &&
688 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { 689 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
689 fdt_status_okay(fdt, offset); 690 fdt_status_okay(fdt, offset);
690 fdt_fixup_board_phy(fdt); 691 fdt_fixup_board_phy(fdt);
691 } else { 692 } else {
692 fdt_status_fail(fdt, offset); 693 fdt_status_fail(fdt, offset);
693 } 694 }
694 } 695 }
695 696
696 void board_quiesce_devices(void) 697 void board_quiesce_devices(void)
697 { 698 {
698 fsl_mc_ldpaa_exit(gd->bd); 699 fsl_mc_ldpaa_exit(gd->bd);
699 } 700 }
700 #endif 701 #endif
701 702
702 #ifdef CONFIG_GIC_V3_ITS 703 #ifdef CONFIG_GIC_V3_ITS
703 void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base) 704 void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
704 { 705 {
705 u32 phandle; 706 u32 phandle;
706 int err; 707 int err;
707 struct fdt_memory gic_lpi; 708 struct fdt_memory gic_lpi;
708 709
709 gic_lpi.start = gic_lpi_base; 710 gic_lpi.start = gic_lpi_base;
710 gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1; 711 gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
711 err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle); 712 err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
712 if (err < 0) 713 if (err < 0)
713 debug("failed to add reserved memory: %d\n", err); 714 debug("failed to add reserved memory: %d\n", err);
714 } 715 }
715 #endif 716 #endif
716 717
717 #ifdef CONFIG_OF_BOARD_SETUP 718 #ifdef CONFIG_OF_BOARD_SETUP
718 int ft_board_setup(void *blob, bd_t *bd) 719 int ft_board_setup(void *blob, bd_t *bd)
719 { 720 {
720 int i; 721 int i;
721 u16 mc_memory_bank = 0; 722 u16 mc_memory_bank = 0;
722 723
723 u64 *base; 724 u64 *base;
724 u64 *size; 725 u64 *size;
725 u64 mc_memory_base = 0; 726 u64 mc_memory_base = 0;
726 u64 mc_memory_size = 0; 727 u64 mc_memory_size = 0;
727 u16 total_memory_banks; 728 u16 total_memory_banks;
728 u64 gic_lpi_base; 729 u64 gic_lpi_base;
729 int ret; 730 int ret;
730 731
731 ft_cpu_setup(blob, bd); 732 ft_cpu_setup(blob, bd);
732 733
733 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); 734 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
734 735
735 if (mc_memory_base != 0) 736 if (mc_memory_base != 0)
736 mc_memory_bank++; 737 mc_memory_bank++;
737 738
738 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; 739 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
739 740
740 base = calloc(total_memory_banks, sizeof(u64)); 741 base = calloc(total_memory_banks, sizeof(u64));
741 size = calloc(total_memory_banks, sizeof(u64)); 742 size = calloc(total_memory_banks, sizeof(u64));
742 743
743 /* fixup DT for the three GPP DDR banks */ 744 /* fixup DT for the three GPP DDR banks */
744 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 745 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
745 base[i] = gd->bd->bi_dram[i].start; 746 base[i] = gd->bd->bi_dram[i].start;
746 size[i] = gd->bd->bi_dram[i].size; 747 size[i] = gd->bd->bi_dram[i].size;
747 } 748 }
748 749
749 #ifdef CONFIG_GIC_V3_ITS 750 #ifdef CONFIG_GIC_V3_ITS
750 gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE; 751 gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
751 ret = fdt_fixup_gic_lpi_memory(blob, gic_lpi_base); 752 ret = fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
752 if (!ret && gic_lpi_tables_init(gic_lpi_base, cpu_numcores())) 753 if (!ret && gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
753 debug("%s: failed to init gic-lpi-tables\n", __func__); 754 debug("%s: failed to init gic-lpi-tables\n", __func__);
754 #endif 755 #endif
755 756
756 #ifdef CONFIG_RESV_RAM 757 #ifdef CONFIG_RESV_RAM
757 /* reduce size if reserved memory is within this bank */ 758 /* reduce size if reserved memory is within this bank */
758 if (gd->arch.resv_ram >= base[0] && 759 if (gd->arch.resv_ram >= base[0] &&
759 gd->arch.resv_ram < base[0] + size[0]) 760 gd->arch.resv_ram < base[0] + size[0])
760 size[0] = gd->arch.resv_ram - base[0]; 761 size[0] = gd->arch.resv_ram - base[0];
761 else if (gd->arch.resv_ram >= base[1] && 762 else if (gd->arch.resv_ram >= base[1] &&
762 gd->arch.resv_ram < base[1] + size[1]) 763 gd->arch.resv_ram < base[1] + size[1])
763 size[1] = gd->arch.resv_ram - base[1]; 764 size[1] = gd->arch.resv_ram - base[1];
764 else if (gd->arch.resv_ram >= base[2] && 765 else if (gd->arch.resv_ram >= base[2] &&
765 gd->arch.resv_ram < base[2] + size[2]) 766 gd->arch.resv_ram < base[2] + size[2])
766 size[2] = gd->arch.resv_ram - base[2]; 767 size[2] = gd->arch.resv_ram - base[2];
767 #endif 768 #endif
768 769
769 if (mc_memory_base != 0) { 770 if (mc_memory_base != 0) {
770 for (i = 0; i <= total_memory_banks; i++) { 771 for (i = 0; i <= total_memory_banks; i++) {
771 if (base[i] == 0 && size[i] == 0) { 772 if (base[i] == 0 && size[i] == 0) {
772 base[i] = mc_memory_base; 773 base[i] = mc_memory_base;
773 size[i] = mc_memory_size; 774 size[i] = mc_memory_size;
774 break; 775 break;
775 } 776 }
776 } 777 }
777 } 778 }
778 779
779 fdt_fixup_memory_banks(blob, base, size, total_memory_banks); 780 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
780 781
781 #ifdef CONFIG_USB 782 #ifdef CONFIG_USB
782 fsl_fdt_fixup_dr_usb(blob, bd); 783 fsl_fdt_fixup_dr_usb(blob, bd);
783 #endif 784 #endif
784 785
785 #ifdef CONFIG_FSL_MC_ENET 786 #ifdef CONFIG_FSL_MC_ENET
786 fdt_fsl_mc_fixup_iommu_map_entry(blob); 787 fdt_fsl_mc_fixup_iommu_map_entry(blob);
787 fdt_fixup_board_enet(blob); 788 fdt_fixup_board_enet(blob);
788 #endif 789 #endif
789 fdt_fixup_icid(blob); 790 fdt_fixup_icid(blob);
790 791
791 return 0; 792 return 0;
792 } 793 }
793 #endif 794 #endif
794 795
795 void qixis_dump_switch(void) 796 void qixis_dump_switch(void)
796 { 797 {
797 int i, nr_of_cfgsw; 798 int i, nr_of_cfgsw;
798 799
799 QIXIS_WRITE(cms[0], 0x00); 800 QIXIS_WRITE(cms[0], 0x00);
800 nr_of_cfgsw = QIXIS_READ(cms[1]); 801 nr_of_cfgsw = QIXIS_READ(cms[1]);
801 802
802 puts("DIP switch settings dump:\n"); 803 puts("DIP switch settings dump:\n");
803 for (i = 1; i <= nr_of_cfgsw; i++) { 804 for (i = 1; i <= nr_of_cfgsw; i++) {
804 QIXIS_WRITE(cms[0], i); 805 QIXIS_WRITE(cms[0], i);
805 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 806 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
806 } 807 }
807 } 808 }
808 809