Eric Lee / smarc-uboot

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Commit b3e03ee2ecbd6207bea52342c16f46883f3222dc

Authored by Eric Lee
1 parent c3778a6b4e
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga

Minor Fixed

Showing 2 changed files with 3 additions and 2 deletions Inline Diff

board/embedian/smarcimx8mm/spl.c
Diff comments   View file @ b3e03ee
1 /* 1 /*
2 * Copyright 2018-2019 NXP 2 * Copyright 2018-2019 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <spl.h> 8 #include <spl.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 #include <errno.h> 10 #include <errno.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <asm/mach-imx/iomux-v3.h> 12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/arch/imx8mm_pins.h> 13 #include <asm/arch/imx8mm_pins.h>
14 #include <asm/arch/sys_proto.h> 14 #include <asm/arch/sys_proto.h>
15 #include <power/pmic.h> 15 #include <power/pmic.h>
16 #include <power/bd71837.h> 16 #include <power/bd71837.h>
17 #include <asm/arch/clock.h> 17 #include <asm/arch/clock.h>
18 #include <asm/mach-imx/gpio.h> 18 #include <asm/mach-imx/gpio.h>
19 #include <asm/mach-imx/mxc_i2c.h> 19 #include <asm/mach-imx/mxc_i2c.h>
20 #include <fsl_esdhc.h> 20 #include <fsl_esdhc.h>
21 #include <mmc.h> 21 #include <mmc.h>
22 #include <asm/arch/imx8m_ddr.h> 22 #include <asm/arch/imx8m_ddr.h>
23 23
24 DECLARE_GLOBAL_DATA_PTR; 24 DECLARE_GLOBAL_DATA_PTR;
25 25
26 void spl_dram_init(void) 26 void spl_dram_init(void)
27 { 27 {
28 ddr_init(&dram_timing); 28 ddr_init(&dram_timing);
29 } 29 }
30 30
31 #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) 31 #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
32 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) 32 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
33 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 33 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
34 struct i2c_pads_info i2c_pad_info1 = { 34 struct i2c_pads_info i2c_pad_info1 = {
35 .scl = { 35 .scl = {
36 .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC, 36 .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
37 .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC, 37 .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
38 .gp = IMX_GPIO_NR(5, 14), 38 .gp = IMX_GPIO_NR(5, 14),
39 }, 39 },
40 .sda = { 40 .sda = {
41 .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC, 41 .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
42 .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC, 42 .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
43 .gp = IMX_GPIO_NR(5, 15), 43 .gp = IMX_GPIO_NR(5, 15),
44 }, 44 },
45 }; 45 };
46 46
47 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) 47 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
48 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18) 48 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
49 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) 49 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
50 50
51 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \ 51 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
52 PAD_CTL_FSEL2) 52 PAD_CTL_FSEL2)
53 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) 53 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
54 54
55 static iomux_v3_cfg_t const usdhc1_pads[] = { 55 static iomux_v3_cfg_t const usdhc1_pads[] = {
56 IMX8MM_PAD_SD1_CLK_USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 56 IMX8MM_PAD_SD1_CLK_USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 IMX8MM_PAD_SD1_CMD_USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 57 IMX8MM_PAD_SD1_CMD_USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 58 IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 59 IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 60 IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 61 IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
62 IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 62 IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
63 IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 63 IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
64 IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 64 IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
65 IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 65 IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
66 IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
67 IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 67 IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
68 }; 68 };
69 69
70 static iomux_v3_cfg_t const usdhc2_pads[] = { 70 static iomux_v3_cfg_t const usdhc2_pads[] = {
71 IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71 IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 72 IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 77 IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
78 IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 78 IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
79 }; 79 };
80 80
81 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 81 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
82 {USDHC1_BASE_ADDR, 0, 8}, 82 {USDHC1_BASE_ADDR, 0, 8},
83 {USDHC2_BASE_ADDR, 0, 4}, 83 {USDHC2_BASE_ADDR, 0, 4},
84 }; 84 };
85 85
86 int board_mmc_init(bd_t *bis) 86 int board_mmc_init(bd_t *bis)
87 { 87 {
88 int i, ret; 88 int i, ret;
89 /* 89 /*
90 * According to the board_mmc_init() the following map is done: 90 * According to the board_mmc_init() the following map is done:
91 * (U-Boot device node) (Physical Port) 91 * (U-Boot device node) (Physical Port)
92 * mmc0 USDHC1 92 * mmc0 USDHC1
93 * mmc1 USDHC2 93 * mmc1 USDHC2
94 */ 94 */
95 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 95 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
96 switch (i) { 96 switch (i) {
97 case 0: 97 case 0:
98 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 98 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
99 imx_iomux_v3_setup_multiple_pads( 99 imx_iomux_v3_setup_multiple_pads(
100 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 100 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
101 gpio_request(USDHC2_PWR_GPIO, "usdhc1_reset"); 101 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
102 gpio_direction_output(USDHC1_PWR_GPIO, 0); 102 gpio_direction_output(USDHC1_PWR_GPIO, 0);
103 udelay(500); 103 udelay(500);
104 gpio_direction_output(USDHC1_PWR_GPIO, 1); 104 gpio_direction_output(USDHC1_PWR_GPIO, 1);
105 break; 105 break;
106 case 1: 106 case 1:
107 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 107 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
108 imx_iomux_v3_setup_multiple_pads( 108 imx_iomux_v3_setup_multiple_pads(
109 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 109 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
110 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); 110 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
111 gpio_direction_output(USDHC2_PWR_GPIO, 0); 111 gpio_direction_output(USDHC2_PWR_GPIO, 0);
112 udelay(500); 112 udelay(500);
113 gpio_direction_output(USDHC2_PWR_GPIO, 1); 113 gpio_direction_output(USDHC2_PWR_GPIO, 1);
114 break; 114 break;
115 default: 115 default:
116 printf("Warning: you configured more USDHC controllers" 116 printf("Warning: you configured more USDHC controllers"
117 "(%d) than supported by the board\n", i + 1); 117 "(%d) than supported by the board\n", i + 1);
118 return -EINVAL; 118 return -EINVAL;
119 } 119 }
120 120
121 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 121 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
122 if (ret) 122 if (ret)
123 return ret; 123 return ret;
124 } 124 }
125 125
126 return 0; 126 return 0;
127 } 127 }
128 128
129 int board_mmc_getcd(struct mmc *mmc) 129 int board_mmc_getcd(struct mmc *mmc)
130 { 130 {
131 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 131 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
132 int ret = 0; 132 int ret = 0;
133 133
134 switch (cfg->esdhc_base) { 134 switch (cfg->esdhc_base) {
135 case USDHC1_BASE_ADDR: 135 case USDHC1_BASE_ADDR:
136 ret = 1; 136 ret = 1;
137 break; 137 break;
138 case USDHC2_BASE_ADDR: 138 case USDHC2_BASE_ADDR:
139 gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); 139 gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
140 gpio_direction_input(USDHC2_CD_GPIO); 140 gpio_direction_input(USDHC2_CD_GPIO);
141 ret = !gpio_get_value(USDHC2_CD_GPIO); 141 ret = !gpio_get_value(USDHC2_CD_GPIO);
142 return ret; 142 return ret;
143 } 143 }
144 144
145 return 1; 145 return 1;
146 } 146 }
147 147
148 /* RESET_OUT */ 148 /* RESET_OUT */
149 static iomux_v3_cfg_t const reset_out_pads[] = { 149 static iomux_v3_cfg_t const reset_out_pads[] = {
150 IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), 150 IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
151 }; 151 };
152 152
153 static void setup_iomux_reset_out(void) 153 static void setup_iomux_reset_out(void)
154 { 154 {
155 imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads)); 155 imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));
156 156
157 /* Set CPU RESET_OUT as Output */ 157 /* Set CPU RESET_OUT as Output */
158 gpio_request(IMX_GPIO_NR(3, 12), "CPU_RESET"); 158 gpio_request(IMX_GPIO_NR(3, 12), "CPU_RESET");
159 gpio_direction_output(IMX_GPIO_NR(3, 12) , 0); 159 gpio_direction_output(IMX_GPIO_NR(3, 12) , 0);
160 } 160 }
161 161
162 #ifdef CONFIG_POWER 162 #ifdef CONFIG_POWER
163 #define I2C_PMIC 0 163 #define I2C_PMIC 0
164 int power_init_board(void) 164 int power_init_board(void)
165 { 165 {
166 struct pmic *p; 166 struct pmic *p;
167 int ret; 167 int ret;
168 168
169 ret = power_bd71837_init(I2C_PMIC); 169 ret = power_bd71837_init(I2C_PMIC);
170 if (ret) 170 if (ret)
171 printf("power init failed"); 171 printf("power init failed");
172 172
173 p = pmic_get("BD71837"); 173 p = pmic_get("BD71837");
174 pmic_probe(p); 174 pmic_probe(p);
175 175
176 176
177 /* decrease RESET key long push time from the default 10s to 10ms */ 177 /* decrease RESET key long push time from the default 10s to 10ms */
178 pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0); 178 pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0);
179 179
180 /* unlock the PMIC regs */ 180 /* unlock the PMIC regs */
181 pmic_reg_write(p, BD71837_REGLOCK, 0x1); 181 pmic_reg_write(p, BD71837_REGLOCK, 0x1);
182 182
183 /* increase VDD_SOC to typical value 0.85v before first DRAM access */ 183 /* increase VDD_SOC to typical value 0.85v before first DRAM access */
184 pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); 184 pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f);
185 185
186 /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ 186 /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
187 pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83); 187 pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83);
188 188
189 #ifndef CONFIG_IMX8M_LPDDR4 189 #ifndef CONFIG_IMX8M_LPDDR4
190 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ 190 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
191 pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); 191 pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
192 #endif 192 #endif
193 193
194 /* lock the PMIC regs */ 194 /* lock the PMIC regs */
195 pmic_reg_write(p, BD71837_REGLOCK, 0x11); 195 pmic_reg_write(p, BD71837_REGLOCK, 0x11);
196 196
197 return 0; 197 return 0;
198 } 198 }
199 #endif 199 #endif
200 200
201 void spl_board_init(void) 201 void spl_board_init(void)
202 { 202 {
203 #ifndef CONFIG_SPL_USB_SDP_SUPPORT 203 #ifndef CONFIG_SPL_USB_SDP_SUPPORT
204 /* Serial download mode */ 204 /* Serial download mode */
205 if (is_usb_boot()) { 205 if (is_usb_boot()) {
206 puts("Back to ROM, SDP\n"); 206 puts("Back to ROM, SDP\n");
207 restore_boot_params(); 207 restore_boot_params();
208 } 208 }
209 #endif 209 #endif
210 puts("Normal Boot\n"); 210 puts("Normal Boot\n");
211 setup_iomux_reset_out(); 211 setup_iomux_reset_out();
212 } 212 }
213 213
214 #ifdef CONFIG_SPL_LOAD_FIT 214 #ifdef CONFIG_SPL_LOAD_FIT
215 int board_fit_config_name_match(const char *name) 215 int board_fit_config_name_match(const char *name)
216 { 216 {
217 /* Just empty function now - can't decide what to choose */ 217 /* Just empty function now - can't decide what to choose */
218 debug("%s: %s\n", __func__, name); 218 debug("%s: %s\n", __func__, name);
219 219
220 return 0; 220 return 0;
221 } 221 }
222 #endif 222 #endif
223 223
224 void board_init_f(ulong dummy) 224 void board_init_f(ulong dummy)
225 { 225 {
226 int ret; 226 int ret;
227 227
228 /* Clear global data */ 228 /* Clear global data */
229 memset((void *)gd, 0, sizeof(gd_t)); 229 memset((void *)gd, 0, sizeof(gd_t));
230 230
231 arch_cpu_init(); 231 arch_cpu_init();
232 232
233 board_early_init_f(); 233 board_early_init_f();
234 234
235 timer_init(); 235 timer_init();
236 236
237 preloader_console_init(); 237 preloader_console_init();
238 238
239 /* Clear the BSS. */ 239 /* Clear the BSS. */
240 memset(__bss_start, 0, __bss_end - __bss_start); 240 memset(__bss_start, 0, __bss_end - __bss_start);
241 241
242 ret = spl_init(); 242 ret = spl_init();
243 if (ret) { 243 if (ret) {
244 debug("spl_init() failed: %d\n", ret); 244 debug("spl_init() failed: %d\n", ret);
245 hang(); 245 hang();
246 } 246 }
247 247
248 enable_tzc380(); 248 enable_tzc380();
249 249
250 /* Adjust pmic voltage to 1.0V for 800M */ 250 /* Adjust pmic voltage to 1.0V for 800M */
251 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 251 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
252 252
253 power_init_board(); 253 power_init_board();
254 254
255 /* DDR initialization */ 255 /* DDR initialization */
256 spl_dram_init(); 256 spl_dram_init();
257 257
258 board_init_r(NULL, 0); 258 board_init_r(NULL, 0);
259 } 259 }
260 260
include/configs/smarcimx8mm.h
Diff comments   View file @ b3e03ee
1 /* 1 /*
2 * Copyright 2018 NXP 2 * Copyright 2018 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __SMARCIMX8MM_H 7 #ifndef __SMARCIMX8MM_H
8 #define __SMARCIMX8MM_H 8 #define __SMARCIMX8MM_H
9 9
10 #include <linux/sizes.h> 10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 12
13 #include "imx_env.h" 13 #include "imx_env.h"
14 14
15 #ifdef CONFIG_SECURE_BOOT 15 #ifdef CONFIG_SECURE_BOOT
16 #define CONFIG_CSF_SIZE 0x2000 /* 8K region */ 16 #define CONFIG_CSF_SIZE 0x2000 /* 8K region */
17 #endif 17 #endif
18 18
19 #define CONFIG_SPL_MAX_SIZE (148 * 1024) 19 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
20 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 20 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
22 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 22 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
23 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 23 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
24 #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) 24 #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
25 25
26 #ifdef CONFIG_SPL_BUILD 26 #ifdef CONFIG_SPL_BUILD
27 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ 27 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
28 #define CONFIG_SPL_WATCHDOG_SUPPORT 28 #define CONFIG_SPL_WATCHDOG_SUPPORT
29 #define CONFIG_SPL_POWER_SUPPORT 29 #define CONFIG_SPL_POWER_SUPPORT
30 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 30 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
31 #define CONFIG_SPL_I2C_SUPPORT 31 #define CONFIG_SPL_I2C_SUPPORT
32 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 32 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
33 #define CONFIG_SPL_STACK 0x91fff0 33 #define CONFIG_SPL_STACK 0x91fff0
34 #define CONFIG_SPL_LIBCOMMON_SUPPORT 34 #define CONFIG_SPL_LIBCOMMON_SUPPORT
35 #define CONFIG_SPL_LIBGENERIC_SUPPORT 35 #define CONFIG_SPL_LIBGENERIC_SUPPORT
36 #define CONFIG_SPL_SERIAL_SUPPORT 36 #define CONFIG_SPL_SERIAL_SUPPORT
37 #define CONFIG_SPL_GPIO_SUPPORT 37 #define CONFIG_SPL_GPIO_SUPPORT
38 #define CONFIG_SPL_BSS_START_ADDR 0x00910000 38 #define CONFIG_SPL_BSS_START_ADDR 0x00910000
39 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ 39 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
40 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 40 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
41 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ 41 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
42 #define CONFIG_SYS_ICACHE_OFF 42 #define CONFIG_SYS_ICACHE_OFF
43 #define CONFIG_SYS_DCACHE_OFF 43 #define CONFIG_SYS_DCACHE_OFF
44 44
45 #define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 45 #define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
46 46
47 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ 47 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
48 48
49 #undef CONFIG_DM_MMC 49 #undef CONFIG_DM_MMC
50 #undef CONFIG_DM_PMIC 50 #undef CONFIG_DM_PMIC
51 #undef CONFIG_DM_PMIC_PFUZE100 51 #undef CONFIG_DM_PMIC_PFUZE100
52 52
53 #define CONFIG_POWER 53 #define CONFIG_POWER
54 #define CONFIG_POWER_I2C 54 #define CONFIG_POWER_I2C
55 #define CONFIG_POWER_BD71837 55 #define CONFIG_POWER_BD71837
56 56
57 #define CONFIG_SYS_I2C 57 #define CONFIG_SYS_I2C
58 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 58 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
59 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 59 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
60 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 60 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
61 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 61 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
62 62
63 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 63 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
64 64
65 #if defined(CONFIG_NAND_BOOT) 65 #if defined(CONFIG_NAND_BOOT)
66 #define CONFIG_SPL_NAND_SUPPORT 66 #define CONFIG_SPL_NAND_SUPPORT
67 #define CONFIG_SPL_DMA_SUPPORT 67 #define CONFIG_SPL_DMA_SUPPORT
68 #define CONFIG_SPL_NAND_MXS 68 #define CONFIG_SPL_NAND_MXS
69 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ 69 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
70 70
71 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ 71 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
72 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ 72 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
73 (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) 73 (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
74 #endif 74 #endif
75 75
76 #endif 76 #endif
77 77
78 #define CONFIG_CMD_READ 78 #define CONFIG_CMD_READ
79 #define CONFIG_SERIAL_TAG 79 #define CONFIG_SERIAL_TAG
80 #define CONFIG_FASTBOOT_USB_DEV 0 80 #define CONFIG_FASTBOOT_USB_DEV 0
81 81
82 #define CONFIG_REMAKE_ELF 82 #define CONFIG_REMAKE_ELF
83 83
84 #define CONFIG_BOARD_EARLY_INIT_F 84 #define CONFIG_BOARD_EARLY_INIT_F
85 #define CONFIG_BOARD_POSTCLK_INIT 85 #define CONFIG_BOARD_POSTCLK_INIT
86 #define CONFIG_BOARD_LATE_INIT 86 #define CONFIG_BOARD_LATE_INIT
87 87
88 /* Flat Device Tree Definitions */ 88 /* Flat Device Tree Definitions */
89 #define CONFIG_OF_BOARD_SETUP 89 #define CONFIG_OF_BOARD_SETUP
90 90
91 #undef CONFIG_CMD_EXPORTENV 91 #undef CONFIG_CMD_EXPORTENV
92 #undef CONFIG_CMD_IMLS 92 #undef CONFIG_CMD_IMLS
93 93
94 #undef CONFIG_CMD_CRC32 94 #undef CONFIG_CMD_CRC32
95 #undef CONFIG_BOOTM_NETBSD 95 #undef CONFIG_BOOTM_NETBSD
96 96
97 /* ENET Config */ 97 /* ENET Config */
98 /* ENET1 */ 98 /* ENET1 */
99 #if defined(CONFIG_CMD_NET) 99 #if defined(CONFIG_CMD_NET)
100 #define CONFIG_CMD_PING 100 #define CONFIG_CMD_PING
101 #define CONFIG_CMD_DHCP 101 #define CONFIG_CMD_DHCP
102 #define CONFIG_CMD_MII 102 #define CONFIG_CMD_MII
103 #define CONFIG_MII 103 #define CONFIG_MII
104 #define CONFIG_ETHPRIME "FEC" 104 #define CONFIG_ETHPRIME "FEC"
105 105
106 #define CONFIG_FEC_MXC 106 #define CONFIG_FEC_MXC
107 #define CONFIG_FEC_XCV_TYPE RGMII 107 #define CONFIG_FEC_XCV_TYPE RGMII
108 #define CONFIG_FEC_MXC_PHYADDR 6 108 #define CONFIG_FEC_MXC_PHYADDR 6
109 #define FEC_QUIRK_ENET_MAC 109 #define FEC_QUIRK_ENET_MAC
110 110
111 #define CONFIG_PHY_GIGE 111 #define CONFIG_PHY_GIGE
112 #define IMX_FEC_BASE 0x30BE0000 112 #define IMX_FEC_BASE 0x30BE0000
113 113
114 #define CONFIG_PHYLIB 114 #define CONFIG_PHYLIB
115 #define CONFIG_PHY_ATHEROS 115 #define CONFIG_PHY_ATHEROS
116 #endif 116 #endif
117 117
118 /* 118 /*
119 * Another approach is add the clocks for inmates into clks_init_on 119 * Another approach is add the clocks for inmates into clks_init_on
120 * in clk-imx8mm.c, then clk_ingore_unused could be removed. 120 * in clk-imx8mm.c, then clk_ingore_unused could be removed.
121 */ 121 */
122 #define JAILHOUSE_ENV \ 122 #define JAILHOUSE_ENV \
123 "jh_clk= \0 " \ 123 "jh_clk= \0 " \
124 "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb;" \ 124 "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb;" \
125 "setenv jh_clk clk_ignore_unused; " \ 125 "setenv jh_clk clk_ignore_unused; " \
126 "if run loadimage; then " \ 126 "if run loadimage; then " \
127 "run mmcboot; " \ 127 "run mmcboot; " \
128 "else run jh_netboot; fi; \0" \ 128 "else run jh_netboot; fi; \0" \
129 "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " 129 "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
130 130
131 #ifdef CONFIG_NAND_BOOT 131 #ifdef CONFIG_NAND_BOOT
132 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) " 132 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
133 #endif 133 #endif
134 134
135 #define CONFIG_MFG_ENV_SETTINGS \ 135 #define CONFIG_MFG_ENV_SETTINGS \
136 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 136 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
137 "initrd_addr=0x43800000\0" \ 137 "initrd_addr=0x43800000\0" \
138 "initrd_high=0xffffffffffffffff\0" \ 138 "initrd_high=0xffffffffffffffff\0" \
139 "emmc_dev=0\0"\ 139 "emmc_dev=0\0"\
140 "sd_dev=1\0" \ 140 "sd_dev=1\0" \
141 141
142 /* Initial environment variables */ 142 /* Initial environment variables */
143 #if defined(CONFIG_NAND_BOOT) 143 #if defined(CONFIG_NAND_BOOT)
144 #define CONFIG_EXTRA_ENV_SETTINGS \ 144 #define CONFIG_EXTRA_ENV_SETTINGS \
145 CONFIG_MFG_ENV_SETTINGS \ 145 CONFIG_MFG_ENV_SETTINGS \
146 "fdt_addr=0x43000000\0" \ 146 "fdt_addr=0x43000000\0" \
147 "fdt_high=0xffffffffffffffff\0" \ 147 "fdt_high=0xffffffffffffffff\0" \
148 "mtdparts=" MFG_NAND_PARTITION "\0" \ 148 "mtdparts=" MFG_NAND_PARTITION "\0" \
149 "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ 149 "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
150 "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=5 " \ 150 "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=5 " \
151 "root=ubi0:nandrootfs rootfstype=ubifs " \ 151 "root=ubi0:nandrootfs rootfstype=ubifs " \
152 MFG_NAND_PARTITION \ 152 MFG_NAND_PARTITION \
153 "\0" \ 153 "\0" \
154 "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ 154 "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
155 "nand read ${fdt_addr} 0x7000000 0x100000;"\ 155 "nand read ${fdt_addr} 0x7000000 0x100000;"\
156 "booti ${loadaddr} - ${fdt_addr}" 156 "booti ${loadaddr} - ${fdt_addr}"
157 157
158 #else 158 #else
159 #define CONFIG_EXTRA_ENV_SETTINGS \ 159 #define CONFIG_EXTRA_ENV_SETTINGS \
160 CONFIG_MFG_ENV_SETTINGS \ 160 CONFIG_MFG_ENV_SETTINGS \
161 JAILHOUSE_ENV \ 161 JAILHOUSE_ENV \
162 "script=boot.scr\0" \ 162 "script=boot.scr\0" \
163 "image=Image\0" \ 163 "image=Image\0" \
164 "console=ttymxc2,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ 164 "console=ttymxc2,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
165 "fdt_addr=0x43000000\0" \ 165 "fdt_addr=0x43000000\0" \
166 "fdt_high=0xffffffffffffffff\0" \ 166 "fdt_high=0xffffffffffffffff\0" \
167 "boot_fdt=try\0" \ 167 "boot_fdt=try\0" \
168 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ 168 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
169 "initrd_addr=0x43800000\0" \ 169 "initrd_addr=0x43800000\0" \
170 "initrd_high=0xffffffffffffffff\0" \ 170 "initrd_high=0xffffffffffffffff\0" \
171 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 171 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
172 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 172 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
173 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 173 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
174 "usbroot=/dev/sda2 rootwait ro\0" \ 174 "usbroot=/dev/sda2 rootwait ro\0" \
175 "mmcrootfstype=ext4 rootwait\0" \ 175 "mmcrootfstype=ext4 rootwait\0" \
176 "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \ 176 "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \
177 "loadusbbootenv=fatload usb 0:1 ${loadaddr} uEnv.txt\0" \ 177 "loadusbbootenv=fatload usb 0:1 ${loadaddr} uEnv.txt\0" \
178 "mmcautodetect=yes\0" \ 178 "mmcautodetect=yes\0" \
179 "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \ 179 "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \
180 "env import -t $loadaddr $filesize\0" \ 180 "env import -t $loadaddr $filesize\0" \
181 "importusbbootenv=echo Importing environment from USB (uEnv.txt)...; " \ 181 "importusbbootenv=echo Importing environment from USB (uEnv.txt)...; " \
182 "env import -t $loadaddr $filesize\0" \ 182 "env import -t $loadaddr $filesize\0" \
183 "mmcargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \ 183 "mmcargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \
184 "rootfstype=${mmcrootfstype} root=${mmcroot}\0 " \ 184 "rootfstype=${mmcrootfstype} root=${mmcroot}\0 " \
185 "usbargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \ 185 "usbargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \
186 "rootfstype=${mmcrootfstype} root=${usbroot}\0 " \ 186 "rootfstype=${mmcrootfstype} root=${usbroot}\0 " \
187 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 187 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
188 "bootscript=echo Running bootscript from mmc ...; " \ 188 "bootscript=echo Running bootscript from mmc ...; " \
189 "source\0" \ 189 "source\0" \
190 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 190 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
191 "loadusbimage=fatload usb 0:1 ${loadaddr} ${image}\0" \
191 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \ 192 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \
192 "loadusbfdt=fatload usb 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \ 193 "loadusbfdt=fatload usb 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \
193 "mmcboot=echo Booting from mmc ...; " \ 194 "mmcboot=echo Booting from mmc ...; " \
194 "run mmcargs; " \ 195 "run mmcargs; " \
195 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 196 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
196 "if run loadfdt; then " \ 197 "if run loadfdt; then " \
197 "booti ${loadaddr} - ${fdt_addr}; " \ 198 "booti ${loadaddr} - ${fdt_addr}; " \
198 "else " \ 199 "else " \
199 "echo WARN: Cannot load the DT; " \ 200 "echo WARN: Cannot load the DT; " \
200 "fi; " \ 201 "fi; " \
201 "else " \ 202 "else " \
202 "echo wait for boot; " \ 203 "echo wait for boot; " \
203 "fi;\0" \ 204 "fi;\0" \
204 "usbboot=echo Booting from USB ...; " \ 205 "usbboot=echo Booting from USB ...; " \
205 "run usbargs; " \ 206 "run usbargs; " \
206 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 207 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
207 "if run loadusbfdt; then " \ 208 "if run loadusbfdt; then " \
208 "booti ${loadaddr} - ${fdt_addr}; " \ 209 "booti ${loadaddr} - ${fdt_addr}; " \
209 "else " \ 210 "else " \
210 "echo WARN: Cannot load the DT; " \ 211 "echo WARN: Cannot load the DT; " \
211 "fi; " \ 212 "fi; " \
212 "else " \ 213 "else " \
213 "echo wait for boot; " \ 214 "echo wait for boot; " \
214 "fi;\0" \ 215 "fi;\0" \
215 "netargs=setenv bootargs ${jh_clk} console=${console} " \ 216 "netargs=setenv bootargs ${jh_clk} console=${console} " \
216 "root=/dev/nfs " \ 217 "root=/dev/nfs " \
217 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 218 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
218 "netboot=echo Booting from net ...; " \ 219 "netboot=echo Booting from net ...; " \
219 "run netargs; " \ 220 "run netargs; " \
220 "if test ${ip_dyn} = yes; then " \ 221 "if test ${ip_dyn} = yes; then " \
221 "setenv get_cmd dhcp; " \ 222 "setenv get_cmd dhcp; " \
222 "else " \ 223 "else " \
223 "setenv get_cmd tftp; " \ 224 "setenv get_cmd tftp; " \
224 "fi; " \ 225 "fi; " \
225 "${get_cmd} ${loadaddr} ${image}; " \ 226 "${get_cmd} ${loadaddr} ${image}; " \
226 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 227 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
227 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 228 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
228 "booti ${loadaddr} - ${fdt_addr}; " \ 229 "booti ${loadaddr} - ${fdt_addr}; " \
229 "else " \ 230 "else " \
230 "echo WARN: Cannot load the DT; " \ 231 "echo WARN: Cannot load the DT; " \
231 "fi; " \ 232 "fi; " \
232 "else " \ 233 "else " \
233 "booti; " \ 234 "booti; " \
234 "fi;\0" 235 "fi;\0"
235 236
236 #define CONFIG_BOOTCOMMAND \ 237 #define CONFIG_BOOTCOMMAND \
237 "mmc dev ${mmcdev}; if mmc rescan; then " \ 238 "mmc dev ${mmcdev}; if mmc rescan; then " \
238 "echo Checking for: uEnv.txt ...; " \ 239 "echo Checking for: uEnv.txt ...; " \
239 "if test -e mmc ${bootpart} /uEnv.txt; then " \ 240 "if test -e mmc ${bootpart} /uEnv.txt; then " \
240 "if run loadbootenv; then " \ 241 "if run loadbootenv; then " \
241 "echo Loaded environment from uEnv.txt;" \ 242 "echo Loaded environment from uEnv.txt;" \
242 "run importbootenv;" \ 243 "run importbootenv;" \
243 "fi;" \ 244 "fi;" \
244 "echo Checking if uenvcmd is set ...;" \ 245 "echo Checking if uenvcmd is set ...;" \
245 "if test -n ${uenvcmd}; then " \ 246 "if test -n ${uenvcmd}; then " \
246 "echo Running uenvcmd ...;" \ 247 "echo Running uenvcmd ...;" \
247 "run uenvcmd;" \ 248 "run uenvcmd;" \
248 "fi;" \ 249 "fi;" \
249 "fi; " \ 250 "fi; " \
250 "if run loadimage; then " \ 251 "if run loadimage; then " \
251 "run mmcboot; " \ 252 "run mmcboot; " \
252 "else run netboot; " \ 253 "else run netboot; " \
253 "fi; " \ 254 "fi; " \
254 "booti ${loadaddr} - ${fdt_addr}; fi;" 255 "booti ${loadaddr} - ${fdt_addr}; fi;"
255 #endif 256 #endif
256 257
257 /* Link Definitions */ 258 /* Link Definitions */
258 #define CONFIG_LOADADDR 0x40480000 259 #define CONFIG_LOADADDR 0x40480000
259 260
260 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 261 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
261 262
262 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 263 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
263 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 264 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
264 #define CONFIG_SYS_INIT_SP_OFFSET \ 265 #define CONFIG_SYS_INIT_SP_OFFSET \
265 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 266 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
266 #define CONFIG_SYS_INIT_SP_ADDR \ 267 #define CONFIG_SYS_INIT_SP_ADDR \
267 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 268 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
268 269
269 #define CONFIG_ENV_OVERWRITE 270 #define CONFIG_ENV_OVERWRITE
270 #if defined(CONFIG_ENV_IS_IN_MMC) 271 #if defined(CONFIG_ENV_IS_IN_MMC)
271 #define CONFIG_ENV_OFFSET (64 * SZ_64K) 272 #define CONFIG_ENV_OFFSET (64 * SZ_64K)
272 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) 273 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
273 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024) 274 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
274 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 275 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
275 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 276 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
276 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 277 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
277 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 278 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
278 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 279 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
279 #elif defined(CONFIG_ENV_IS_IN_NAND) 280 #elif defined(CONFIG_ENV_IS_IN_NAND)
280 #define CONFIG_ENV_OFFSET (60 << 20) 281 #define CONFIG_ENV_OFFSET (60 << 20)
281 #endif 282 #endif
282 #define CONFIG_ENV_SIZE 0x1000 283 #define CONFIG_ENV_SIZE 0x1000
283 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 284 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
284 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 285 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
285 286
286 /* Size of malloc() pool */ 287 /* Size of malloc() pool */
287 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) 288 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
288 289
289 #define CONFIG_SYS_SDRAM_BASE 0x40000000 290 #define CONFIG_SYS_SDRAM_BASE 0x40000000
290 #define PHYS_SDRAM 0x40000000 291 #define PHYS_SDRAM 0x40000000
291 #ifdef CONFIG_2GB_LPDDR4 292 #ifdef CONFIG_2GB_LPDDR4
292 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ 293 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
293 #else 294 #else
294 #define PHYS_SDRAM_SIZE 0xc0000000 /* 4GB DDR, temporary workaround */ 295 #define PHYS_SDRAM_SIZE 0xc0000000 /* 4GB DDR, temporary workaround */
295 #endif 296 #endif
296 #define CONFIG_NR_DRAM_BANKS 1 297 #define CONFIG_NR_DRAM_BANKS 1
297 298
298 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 299 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
299 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) 300 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
300 301
301 #define CONFIG_BAUDRATE 115200 302 #define CONFIG_BAUDRATE 115200
302 303
303 #define CONFIG_MXC_UART 304 #define CONFIG_MXC_UART
304 305
305 #ifdef CONFIG_CONSOLE_SER0 306 #ifdef CONFIG_CONSOLE_SER0
306 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR 307 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
307 #define CONSOLE_DEV "ttymxc0" 308 #define CONSOLE_DEV "ttymxc0"
308 #endif 309 #endif
309 310
310 #ifdef CONFIG_CONSOLE_SER1 311 #ifdef CONFIG_CONSOLE_SER1
311 #define CONFIG_MXC_UART_BASE UART4_BASE_ADDR 312 #define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
312 #define CONSOLE_DEV "ttymxc3" 313 #define CONSOLE_DEV "ttymxc3"
313 #endif 314 #endif
314 315
315 #ifdef CONFIG_CONSOLE_SER2 316 #ifdef CONFIG_CONSOLE_SER2
316 #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR 317 #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
317 #define CONSOLE_DEV "ttymxc2" 318 #define CONSOLE_DEV "ttymxc2"
318 #endif 319 #endif
319 320
320 #ifdef CONFIG_CONSOLE_SER3 321 #ifdef CONFIG_CONSOLE_SER3
321 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR 322 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
322 #define CONSOLE_DEV "ttymxc1" 323 #define CONSOLE_DEV "ttymxc1"
323 #endif 324 #endif
324 325
325 /* Monitor Command Prompt */ 326 /* Monitor Command Prompt */
326 #undef CONFIG_SYS_PROMPT 327 #undef CONFIG_SYS_PROMPT
327 #define CONFIG_SYS_PROMPT "u-boot$ " 328 #define CONFIG_SYS_PROMPT "u-boot$ "
328 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 329 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
329 #define CONFIG_SYS_CBSIZE 2048 330 #define CONFIG_SYS_CBSIZE 2048
330 #define CONFIG_SYS_MAXARGS 64 331 #define CONFIG_SYS_MAXARGS 64
331 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 332 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
332 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 333 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
333 sizeof(CONFIG_SYS_PROMPT) + 16) 334 sizeof(CONFIG_SYS_PROMPT) + 16)
334 335
335 #define CONFIG_IMX_BOOTAUX 336 #define CONFIG_IMX_BOOTAUX
336 337
337 /* USDHC */ 338 /* USDHC */
338 #define CONFIG_CMD_MMC 339 #define CONFIG_CMD_MMC
339 #define CONFIG_FSL_ESDHC 340 #define CONFIG_FSL_ESDHC
340 #define CONFIG_FSL_USDHC 341 #define CONFIG_FSL_USDHC
341 342
342 #ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK 343 #ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
343 #define CONFIG_SYS_FSL_USDHC_NUM 1 344 #define CONFIG_SYS_FSL_USDHC_NUM 1
344 #else 345 #else
345 #define CONFIG_SYS_FSL_USDHC_NUM 2 346 #define CONFIG_SYS_FSL_USDHC_NUM 2
346 #endif 347 #endif
347 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 348 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
348 349
349 #define CONFIG_CMD_PART 350 #define CONFIG_CMD_PART
350 #define CONFIG_CMD_FS_GENERIC 351 #define CONFIG_CMD_FS_GENERIC
351 352
352 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 353 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
353 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 354 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
354 355
355 #ifdef CONFIG_FSL_FSPI 356 #ifdef CONFIG_FSL_FSPI
356 #define CONFIG_SF_DEFAULT_BUS 0 357 #define CONFIG_SF_DEFAULT_BUS 0
357 #define CONFIG_SF_DEFAULT_CS 0 358 #define CONFIG_SF_DEFAULT_CS 0
358 #define CONFIG_SF_DEFAULT_SPEED 40000000 359 #define CONFIG_SF_DEFAULT_SPEED 40000000
359 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 360 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
360 #define FSL_FSPI_FLASH_SIZE SZ_32M 361 #define FSL_FSPI_FLASH_SIZE SZ_32M
361 #define FSL_FSPI_FLASH_NUM 1 362 #define FSL_FSPI_FLASH_NUM 1
362 #define FSPI0_BASE_ADDR 0x30bb0000 363 #define FSPI0_BASE_ADDR 0x30bb0000
363 #define FSPI0_AMBA_BASE 0x0 364 #define FSPI0_AMBA_BASE 0x0
364 #define CONFIG_SPI_FLASH_BAR 365 #define CONFIG_SPI_FLASH_BAR
365 #define CONFIG_FSPI_QUAD_SUPPORT 366 #define CONFIG_FSPI_QUAD_SUPPORT
366 367
367 #define CONFIG_SYS_FSL_FSPI_AHB 368 #define CONFIG_SYS_FSL_FSPI_AHB
368 #endif 369 #endif
369 370
370 /* Enable SPI */ 371 /* Enable SPI */
371 #ifndef CONFIG_NAND_MXS 372 #ifndef CONFIG_NAND_MXS
372 #ifndef CONFIG_FSL_FSPI 373 #ifndef CONFIG_FSL_FSPI
373 #ifdef CONFIG_CMD_SF 374 #ifdef CONFIG_CMD_SF
374 #define CONFIG_SPI_FLASH 375 #define CONFIG_SPI_FLASH
375 #define CONFIG_SPI_FLASH_MACRONIX 376 #define CONFIG_SPI_FLASH_MACRONIX
376 #define CONFIG_MXC_SPI 377 #define CONFIG_MXC_SPI
377 #define CONFIG_SF_DEFAULT_BUS 0 378 #define CONFIG_SF_DEFAULT_BUS 0
378 #define CONFIG_SF_DEFAULT_SPEED 20000000 379 #define CONFIG_SF_DEFAULT_SPEED 20000000
379 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 380 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
380 #endif 381 #endif
381 #endif 382 #endif
382 #endif 383 #endif
383 384
384 #ifdef CONFIG_CMD_NAND 385 #ifdef CONFIG_CMD_NAND
385 #define CONFIG_NAND_MXS 386 #define CONFIG_NAND_MXS
386 #define CONFIG_CMD_NAND_TRIMFFS 387 #define CONFIG_CMD_NAND_TRIMFFS
387 388
388 /* NAND stuff */ 389 /* NAND stuff */
389 #define CONFIG_SYS_MAX_NAND_DEVICE 1 390 #define CONFIG_SYS_MAX_NAND_DEVICE 1
390 #define CONFIG_SYS_NAND_BASE 0x20000000 391 #define CONFIG_SYS_NAND_BASE 0x20000000
391 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 392 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
392 #define CONFIG_SYS_NAND_ONFI_DETECTION 393 #define CONFIG_SYS_NAND_ONFI_DETECTION
393 394
394 /* DMA stuff, needed for GPMI/MXS NAND support */ 395 /* DMA stuff, needed for GPMI/MXS NAND support */
395 #define CONFIG_APBH_DMA 396 #define CONFIG_APBH_DMA
396 #define CONFIG_APBH_DMA_BURST 397 #define CONFIG_APBH_DMA_BURST
397 #define CONFIG_APBH_DMA_BURST8 398 #define CONFIG_APBH_DMA_BURST8
398 399
399 #ifdef CONFIG_CMD_UBI 400 #ifdef CONFIG_CMD_UBI
400 #define CONFIG_MTD_PARTITIONS 401 #define CONFIG_MTD_PARTITIONS
401 #define CONFIG_MTD_DEVICE 402 #define CONFIG_MTD_DEVICE
402 #endif 403 #endif
403 #endif /* CONFIG_CMD_NAND */ 404 #endif /* CONFIG_CMD_NAND */
404 405
405 406
406 #define CONFIG_MXC_GPIO 407 #define CONFIG_MXC_GPIO
407 408
408 #define CONFIG_MXC_OCOTP 409 #define CONFIG_MXC_OCOTP
409 #define CONFIG_CMD_FUSE 410 #define CONFIG_CMD_FUSE
410 411
411 #ifndef CONFIG_DM_I2C 412 #ifndef CONFIG_DM_I2C
412 #define CONFIG_SYS_I2C 413 #define CONFIG_SYS_I2C
413 #endif 414 #endif
414 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 415 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
415 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 416 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
416 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 417 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
417 #define CONFIG_SYS_I2C_SPEED 100000 418 #define CONFIG_SYS_I2C_SPEED 100000
418 419
419 /* USB configs */ 420 /* USB configs */
420 #ifndef CONFIG_SPL_BUILD 421 #ifndef CONFIG_SPL_BUILD
421 #define CONFIG_CMD_USB 422 #define CONFIG_CMD_USB
422 #define CONFIG_USB_STORAGE 423 #define CONFIG_USB_STORAGE
423 #define CONFIG_USBD_HS 424 #define CONFIG_USBD_HS
424 425
425 #define CONFIG_CMD_USB_MASS_STORAGE 426 #define CONFIG_CMD_USB_MASS_STORAGE
426 #define CONFIG_USB_GADGET_MASS_STORAGE 427 #define CONFIG_USB_GADGET_MASS_STORAGE
427 #define CONFIG_USB_FUNCTION_MASS_STORAGE 428 #define CONFIG_USB_FUNCTION_MASS_STORAGE
428 429
429 #endif 430 #endif
430 431
431 #define CONFIG_USB_GADGET_DUALSPEED 432 #define CONFIG_USB_GADGET_DUALSPEED
432 #define CONFIG_USB_GADGET_VBUS_DRAW 2 433 #define CONFIG_USB_GADGET_VBUS_DRAW 2
433 434
434 #define CONFIG_CI_UDC 435 #define CONFIG_CI_UDC
435 436
436 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 437 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
437 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 438 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
438 439
439 #ifdef CONFIG_VIDEO 440 #ifdef CONFIG_VIDEO
440 #define CONFIG_VIDEO_MXS 441 #define CONFIG_VIDEO_MXS
441 #define CONFIG_VIDEO_LOGO 442 #define CONFIG_VIDEO_LOGO
442 #define CONFIG_SPLASH_SCREEN 443 #define CONFIG_SPLASH_SCREEN
443 #define CONFIG_SPLASH_SCREEN_ALIGN 444 #define CONFIG_SPLASH_SCREEN_ALIGN
444 #define CONFIG_CMD_BMP 445 #define CONFIG_CMD_BMP
445 #define CONFIG_BMP_16BPP 446 #define CONFIG_BMP_16BPP
446 #define CONFIG_VIDEO_BMP_RLE8 447 #define CONFIG_VIDEO_BMP_RLE8
447 #define CONFIG_VIDEO_BMP_LOGO 448 #define CONFIG_VIDEO_BMP_LOGO
448 #define CONFIG_IMX_VIDEO_SKIP 449 #define CONFIG_IMX_VIDEO_SKIP
449 #define CONFIG_RM67191 450 #define CONFIG_RM67191
450 #endif 451 #endif
451 452
452 #define CONFIG_OF_SYSTEM_SETUP 453 #define CONFIG_OF_SYSTEM_SETUP
453 454
454 #if defined(CONFIG_ANDROID_SUPPORT) 455 #if defined(CONFIG_ANDROID_SUPPORT)
455 #include "smarcimx8mm_android.h" 456 #include "smarcimx8mm_android.h"
456 #endif 457 #endif
457 #endif 458 #endif
458 459