Eric Lee / smarc-uboot

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Commit b4bc642c6255ee1e3abc6f15b2dcabcccf1b55c1

Authored by Ye Li
1 parent 139a6f95be
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12884 mx7dsabresd: Fix LCD_PWR_EN output setting 

LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
is actually 1.2V.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

board/freescale/mx7dsabresd/mx7dsabresd.c
Diff comments   View file @ b4bc642
1 /* 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <asm/arch/clock.h> 7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h> 8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h> 9 #include <asm/arch/mx7-pins.h>
10 #include <asm/arch/sys_proto.h> 10 #include <asm/arch/sys_proto.h>
11 #include <asm/gpio.h> 11 #include <asm/gpio.h>
12 #include <asm/imx-common/iomux-v3.h> 12 #include <asm/imx-common/iomux-v3.h>
13 #include <asm/imx-common/boot_mode.h> 13 #include <asm/imx-common/boot_mode.h>
14 #include <asm/io.h> 14 #include <asm/io.h>
15 #include <linux/sizes.h> 15 #include <linux/sizes.h>
16 #include <common.h> 16 #include <common.h>
17 #include <fsl_esdhc.h> 17 #include <fsl_esdhc.h>
18 #include <mmc.h> 18 #include <mmc.h>
19 #include <miiphy.h> 19 #include <miiphy.h>
20 #include <netdev.h> 20 #include <netdev.h>
21 #include <power/pmic.h> 21 #include <power/pmic.h>
22 #include <power/pfuze3000_pmic.h> 22 #include <power/pfuze3000_pmic.h>
23 #include "../common/pfuze.h" 23 #include "../common/pfuze.h"
24 #include <i2c.h> 24 #include <i2c.h>
25 #include <asm/imx-common/mxc_i2c.h> 25 #include <asm/imx-common/mxc_i2c.h>
26 #include <asm/arch/crm_regs.h> 26 #include <asm/arch/crm_regs.h>
27 #include <usb.h> 27 #include <usb.h>
28 #include <usb/ehci-fsl.h> 28 #include <usb/ehci-fsl.h>
29 #if defined(CONFIG_MXC_EPDC) 29 #if defined(CONFIG_MXC_EPDC)
30 #include <lcd.h> 30 #include <lcd.h>
31 #include <mxc_epdc_fb.h> 31 #include <mxc_epdc_fb.h>
32 #endif 32 #endif
33 #include <asm/imx-common/video.h> 33 #include <asm/imx-common/video.h>
34 34
35 #ifdef CONFIG_FSL_FASTBOOT 35 #ifdef CONFIG_FSL_FASTBOOT
36 #include <fsl_fastboot.h> 36 #include <fsl_fastboot.h>
37 #ifdef CONFIG_ANDROID_RECOVERY 37 #ifdef CONFIG_ANDROID_RECOVERY
38 #include <recovery.h> 38 #include <recovery.h>
39 #endif 39 #endif
40 #endif /*CONFIG_FSL_FASTBOOT*/ 40 #endif /*CONFIG_FSL_FASTBOOT*/
41 41
42 DECLARE_GLOBAL_DATA_PTR; 42 DECLARE_GLOBAL_DATA_PTR;
43 43
44 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 44 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
45 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 45 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
46 46
47 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 47 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
48 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 48 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
49 49
50 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 50 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
51 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 51 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
52 52
53 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 53 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
54 54
55 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 55 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
56 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) 56 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
57 57
58 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 58 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
59 PAD_CTL_DSE_3P3V_49OHM) 59 PAD_CTL_DSE_3P3V_49OHM)
60 60
61 #define QSPI_PAD_CTRL \ 61 #define QSPI_PAD_CTRL \
62 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 62 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
63 63
64 #define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 64 #define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
65 65
66 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM) 66 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM)
67 67
68 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 68 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
69 69
70 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 70 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
71 71
72 #define EPDC_PAD_CTRL 0x0 72 #define EPDC_PAD_CTRL 0x0
73 73
74 #ifdef CONFIG_SYS_I2C_MXC 74 #ifdef CONFIG_SYS_I2C_MXC
75 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 75 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
76 /* I2C1 for PMIC */ 76 /* I2C1 for PMIC */
77 static struct i2c_pads_info i2c_pad_info1 = { 77 static struct i2c_pads_info i2c_pad_info1 = {
78 .scl = { 78 .scl = {
79 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, 79 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
80 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, 80 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
81 .gp = IMX_GPIO_NR(4, 8), 81 .gp = IMX_GPIO_NR(4, 8),
82 }, 82 },
83 .sda = { 83 .sda = {
84 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, 84 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
85 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, 85 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
86 .gp = IMX_GPIO_NR(4, 9), 86 .gp = IMX_GPIO_NR(4, 9),
87 }, 87 },
88 }; 88 };
89 89
90 /* I2C3 */ 90 /* I2C3 */
91 static struct i2c_pads_info i2c_pad_info3 = { 91 static struct i2c_pads_info i2c_pad_info3 = {
92 .scl = { 92 .scl = {
93 .i2c_mode = MX7D_PAD_I2C3_SCL__I2C3_SCL | PC, 93 .i2c_mode = MX7D_PAD_I2C3_SCL__I2C3_SCL | PC,
94 .gpio_mode = MX7D_PAD_I2C3_SCL__GPIO4_IO12 | PC, 94 .gpio_mode = MX7D_PAD_I2C3_SCL__GPIO4_IO12 | PC,
95 .gp = IMX_GPIO_NR(4, 12), 95 .gp = IMX_GPIO_NR(4, 12),
96 }, 96 },
97 .sda = { 97 .sda = {
98 .i2c_mode = MX7D_PAD_I2C3_SDA__I2C3_SDA | PC, 98 .i2c_mode = MX7D_PAD_I2C3_SDA__I2C3_SDA | PC,
99 .gpio_mode = MX7D_PAD_I2C3_SDA__GPIO4_IO13 | PC, 99 .gpio_mode = MX7D_PAD_I2C3_SDA__GPIO4_IO13 | PC,
100 .gp = IMX_GPIO_NR(4, 13), 100 .gp = IMX_GPIO_NR(4, 13),
101 }, 101 },
102 }; 102 };
103 #endif 103 #endif
104 104
105 int dram_init(void) 105 int dram_init(void)
106 { 106 {
107 gd->ram_size = PHYS_SDRAM_SIZE; 107 gd->ram_size = PHYS_SDRAM_SIZE;
108 108
109 return 0; 109 return 0;
110 } 110 }
111 111
112 static iomux_v3_cfg_t const wdog_pads[] = { 112 static iomux_v3_cfg_t const wdog_pads[] = {
113 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 113 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
114 }; 114 };
115 115
116 static iomux_v3_cfg_t const uart1_pads[] = { 116 static iomux_v3_cfg_t const uart1_pads[] = {
117 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 117 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
118 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 118 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
119 }; 119 };
120 120
121 static iomux_v3_cfg_t const usdhc1_pads[] = { 121 static iomux_v3_cfg_t const usdhc1_pads[] = {
122 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 122 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 126 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 127 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 128
129 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 129 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 }; 131 };
132 132
133 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 133 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
134 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 141 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 142 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 145
146 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 146 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 }; 147 };
148 148
149 #define IOX_SDI IMX_GPIO_NR(1, 9) 149 #define IOX_SDI IMX_GPIO_NR(1, 9)
150 #define IOX_STCP IMX_GPIO_NR(1, 12) 150 #define IOX_STCP IMX_GPIO_NR(1, 12)
151 #define IOX_SHCP IMX_GPIO_NR(1, 13) 151 #define IOX_SHCP IMX_GPIO_NR(1, 13)
152 152
153 static iomux_v3_cfg_t const iox_pads[] = { 153 static iomux_v3_cfg_t const iox_pads[] = {
154 /* IOX_SDI */ 154 /* IOX_SDI */
155 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), 155 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
156 /* IOX_STCP */ 156 /* IOX_STCP */
157 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 157 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
158 /* IOX_SHCP */ 158 /* IOX_SHCP */
159 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), 159 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
160 }; 160 };
161 161
162 /* 162 /*
163 * PCIE_DIS_B --> Q0 163 * PCIE_DIS_B --> Q0
164 * PCIE_RST_B --> Q1 164 * PCIE_RST_B --> Q1
165 * HDMI_RST_B --> Q2 165 * HDMI_RST_B --> Q2
166 * PERI_RST_B --> Q3 166 * PERI_RST_B --> Q3
167 * SENSOR_RST_B --> Q4 167 * SENSOR_RST_B --> Q4
168 * ENET_RST_B --> Q5 168 * ENET_RST_B --> Q5
169 * PERI_3V3_EN --> Q6 169 * PERI_3V3_EN --> Q6
170 * LCD_PWR_EN --> Q7 170 * LCD_PWR_EN --> Q7
171 */ 171 */
172 enum qn { 172 enum qn {
173 PCIE_DIS_B, 173 PCIE_DIS_B,
174 PCIE_RST_B, 174 PCIE_RST_B,
175 HDMI_RST_B, 175 HDMI_RST_B,
176 PERI_RST_B, 176 PERI_RST_B,
177 SENSOR_RST_B, 177 SENSOR_RST_B,
178 ENET_RST_B, 178 ENET_RST_B,
179 PERI_3V3_EN, 179 PERI_3V3_EN,
180 LCD_PWR_EN, 180 LCD_PWR_EN,
181 }; 181 };
182 182
183 enum qn_func { 183 enum qn_func {
184 qn_reset, 184 qn_reset,
185 qn_enable, 185 qn_enable,
186 qn_disable, 186 qn_disable,
187 }; 187 };
188 188
189 enum qn_level { 189 enum qn_level {
190 qn_low = 0, 190 qn_low = 0,
191 qn_high = 1, 191 qn_high = 1,
192 }; 192 };
193 193
194 static enum qn_level seq[3][2] = { 194 static enum qn_level seq[3][2] = {
195 {0, 1}, {1, 1}, {0, 0} 195 {0, 1}, {1, 1}, {0, 0}
196 }; 196 };
197 197
198 static enum qn_func qn_output[8] = { 198 static enum qn_func qn_output[8] = {
199 qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, 199 qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
200 qn_enable 200 qn_disable
201 }; 201 };
202 202
203 static void iox74lv_init(void) 203 static void iox74lv_init(void)
204 { 204 {
205 int i; 205 int i;
206 206
207 for (i = 7; i >= 0; i--) { 207 for (i = 7; i >= 0; i--) {
208 gpio_direction_output(IOX_SHCP, 0); 208 gpio_direction_output(IOX_SHCP, 0);
209 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 209 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
210 udelay(500); 210 udelay(500);
211 gpio_direction_output(IOX_SHCP, 1); 211 gpio_direction_output(IOX_SHCP, 1);
212 udelay(500); 212 udelay(500);
213 } 213 }
214 214
215 gpio_direction_output(IOX_STCP, 0); 215 gpio_direction_output(IOX_STCP, 0);
216 udelay(500); 216 udelay(500);
217 /* 217 /*
218 * shift register will be output to pins 218 * shift register will be output to pins
219 */ 219 */
220 gpio_direction_output(IOX_STCP, 1); 220 gpio_direction_output(IOX_STCP, 1);
221 221
222 for (i = 7; i >= 0; i--) { 222 for (i = 7; i >= 0; i--) {
223 gpio_direction_output(IOX_SHCP, 0); 223 gpio_direction_output(IOX_SHCP, 0);
224 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 224 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
225 udelay(500); 225 udelay(500);
226 gpio_direction_output(IOX_SHCP, 1); 226 gpio_direction_output(IOX_SHCP, 1);
227 udelay(500); 227 udelay(500);
228 } 228 }
229 gpio_direction_output(IOX_STCP, 0); 229 gpio_direction_output(IOX_STCP, 0);
230 udelay(500); 230 udelay(500);
231 /* 231 /*
232 * shift register will be output to pins 232 * shift register will be output to pins
233 */ 233 */
234 gpio_direction_output(IOX_STCP, 1); 234 gpio_direction_output(IOX_STCP, 1);
235 }; 235 };
236 236
237 void iox74lv_set(int index) 237 void iox74lv_set(int index)
238 { 238 {
239 int i; 239 int i;
240 for (i = 7; i >= 0; i--) { 240 for (i = 7; i >= 0; i--) {
241 gpio_direction_output(IOX_SHCP, 0); 241 gpio_direction_output(IOX_SHCP, 0);
242 242
243 if (i == index) 243 if (i == index)
244 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 244 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
245 else 245 else
246 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 246 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
247 udelay(500); 247 udelay(500);
248 gpio_direction_output(IOX_SHCP, 1); 248 gpio_direction_output(IOX_SHCP, 1);
249 udelay(500); 249 udelay(500);
250 } 250 }
251 251
252 gpio_direction_output(IOX_STCP, 0); 252 gpio_direction_output(IOX_STCP, 0);
253 udelay(500); 253 udelay(500);
254 /* 254 /*
255 * shift register will be output to pins 255 * shift register will be output to pins
256 */ 256 */
257 gpio_direction_output(IOX_STCP, 1); 257 gpio_direction_output(IOX_STCP, 1);
258 258
259 for (i = 7; i >= 0; i--) { 259 for (i = 7; i >= 0; i--) {
260 gpio_direction_output(IOX_SHCP, 0); 260 gpio_direction_output(IOX_SHCP, 0);
261 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 261 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
262 udelay(500); 262 udelay(500);
263 gpio_direction_output(IOX_SHCP, 1); 263 gpio_direction_output(IOX_SHCP, 1);
264 udelay(500); 264 udelay(500);
265 } 265 }
266 266
267 gpio_direction_output(IOX_STCP, 0); 267 gpio_direction_output(IOX_STCP, 0);
268 udelay(500); 268 udelay(500);
269 /* 269 /*
270 * shift register will be output to pins 270 * shift register will be output to pins
271 */ 271 */
272 gpio_direction_output(IOX_STCP, 1); 272 gpio_direction_output(IOX_STCP, 1);
273 }; 273 };
274 274
275 #define BOARD_REV_C 0x300 275 #define BOARD_REV_C 0x300
276 #define BOARD_REV_B 0x200 276 #define BOARD_REV_B 0x200
277 #define BOARD_REV_A 0x100 277 #define BOARD_REV_A 0x100
278 278
279 static int mx7sabre_rev(void) 279 static int mx7sabre_rev(void)
280 { 280 {
281 /* 281 /*
282 * Get Board ID information from OCOTP_GP1[15:8] 282 * Get Board ID information from OCOTP_GP1[15:8]
283 * i.MX7D SDB RevA: 0x41 283 * i.MX7D SDB RevA: 0x41
284 * i.MX7D SDB RevB: 0x42 284 * i.MX7D SDB RevB: 0x42
285 */ 285 */
286 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 286 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
287 struct fuse_bank *bank = &ocotp->bank[14]; 287 struct fuse_bank *bank = &ocotp->bank[14];
288 int reg = readl(&bank->fuse_regs[0]); 288 int reg = readl(&bank->fuse_regs[0]);
289 int ret; 289 int ret;
290 290
291 if (reg != 0) { 291 if (reg != 0) {
292 switch (reg >> 8 & 0x0F) { 292 switch (reg >> 8 & 0x0F) {
293 case 0x3: 293 case 0x3:
294 ret = BOARD_REV_C; 294 ret = BOARD_REV_C;
295 break; 295 break;
296 case 0x02: 296 case 0x02:
297 ret = BOARD_REV_B; 297 ret = BOARD_REV_B;
298 break; 298 break;
299 case 0x01: 299 case 0x01:
300 default: 300 default:
301 ret = BOARD_REV_A; 301 ret = BOARD_REV_A;
302 break; 302 break;
303 } 303 }
304 } else { 304 } else {
305 /* If the gp1 fuse is not burn, we have to use TO rev for the board rev */ 305 /* If the gp1 fuse is not burn, we have to use TO rev for the board rev */
306 if (is_soc_rev(CHIP_REV_1_0)) 306 if (is_soc_rev(CHIP_REV_1_0))
307 ret = BOARD_REV_A; 307 ret = BOARD_REV_A;
308 else if (is_soc_rev(CHIP_REV_1_1)) 308 else if (is_soc_rev(CHIP_REV_1_1))
309 ret = BOARD_REV_B; 309 ret = BOARD_REV_B;
310 else 310 else
311 ret = BOARD_REV_C; 311 ret = BOARD_REV_C;
312 } 312 }
313 313
314 return ret; 314 return ret;
315 } 315 }
316 316
317 u32 get_board_rev(void) 317 u32 get_board_rev(void)
318 { 318 {
319 int rev = mx7sabre_rev(); 319 int rev = mx7sabre_rev();
320 320
321 return (get_cpu_rev() & ~(0xF << 8)) | rev; 321 return (get_cpu_rev() & ~(0xF << 8)) | rev;
322 } 322 }
323 323
324 #ifdef CONFIG_NAND_MXS 324 #ifdef CONFIG_NAND_MXS
325 static iomux_v3_cfg_t const gpmi_pads[] = { 325 static iomux_v3_cfg_t const gpmi_pads[] = {
326 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 326 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
327 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 327 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
328 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 328 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
329 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 329 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
330 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 330 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
331 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 331 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
332 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 332 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
333 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 333 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
334 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 334 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
335 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 335 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
336 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 336 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
337 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 337 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
338 MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 338 MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
339 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 339 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
340 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 340 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
341 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 341 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
342 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 342 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
343 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), 343 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
344 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 344 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
345 }; 345 };
346 346
347 static void setup_gpmi_nand(void) 347 static void setup_gpmi_nand(void)
348 { 348 {
349 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 349 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
350 350
351 /* NAND_USDHC_BUS_CLK is set in rom */ 351 /* NAND_USDHC_BUS_CLK is set in rom */
352 set_clk_nand(); 352 set_clk_nand();
353 } 353 }
354 #endif 354 #endif
355 355
356 #ifdef CONFIG_VIDEO_MXS 356 #ifdef CONFIG_VIDEO_MXS
357 static iomux_v3_cfg_t const lcd_pads[] = { 357 static iomux_v3_cfg_t const lcd_pads[] = {
358 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 358 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
359 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 359 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
360 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 360 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
361 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 361 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
362 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 362 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
363 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 363 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
364 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 364 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
365 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 365 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
366 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 366 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
367 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 367 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
368 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 368 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
369 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 369 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
370 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 370 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
371 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 371 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
372 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 372 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
373 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 373 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
374 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 374 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
375 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 375 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
376 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 376 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
377 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 377 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
378 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 378 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
379 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 379 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
380 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 380 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
381 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 381 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
382 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 382 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
383 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 383 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
384 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 384 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
385 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 385 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
386 386
387 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 387 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
388 }; 388 };
389 389
390 static iomux_v3_cfg_t const pwm_pads[] = { 390 static iomux_v3_cfg_t const pwm_pads[] = {
391 /* Use GPIO for Brightness adjustment, duty cycle = period */ 391 /* Use GPIO for Brightness adjustment, duty cycle = period */
392 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 392 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
393 }; 393 };
394 394
395 void do_enable_parallel_lcd(struct display_info_t const *dev) 395 void do_enable_parallel_lcd(struct display_info_t const *dev)
396 { 396 {
397 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 397 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
398 398
399 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); 399 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
400 400
401 /* Reset LCD */ 401 /* Reset LCD */
402 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); 402 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
403 udelay(500); 403 udelay(500);
404 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); 404 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
405 405
406 /* Set Brightness to high */ 406 /* Set Brightness to high */
407 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); 407 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
408 } 408 }
409 409
410 struct display_info_t const displays[] = {{ 410 struct display_info_t const displays[] = {{
411 .bus = ELCDIF1_IPS_BASE_ADDR, 411 .bus = ELCDIF1_IPS_BASE_ADDR,
412 .addr = 0, 412 .addr = 0,
413 .pixfmt = 24, 413 .pixfmt = 24,
414 .detect = NULL, 414 .detect = NULL,
415 .enable = do_enable_parallel_lcd, 415 .enable = do_enable_parallel_lcd,
416 .mode = { 416 .mode = {
417 .name = "TFT43AB", 417 .name = "TFT43AB",
418 .xres = 480, 418 .xres = 480,
419 .yres = 272, 419 .yres = 272,
420 .pixclock = 108695, 420 .pixclock = 108695,
421 .left_margin = 8, 421 .left_margin = 8,
422 .right_margin = 4, 422 .right_margin = 4,
423 .upper_margin = 2, 423 .upper_margin = 2,
424 .lower_margin = 4, 424 .lower_margin = 4,
425 .hsync_len = 41, 425 .hsync_len = 41,
426 .vsync_len = 10, 426 .vsync_len = 10,
427 .sync = 0, 427 .sync = 0,
428 .vmode = FB_VMODE_NONINTERLACED 428 .vmode = FB_VMODE_NONINTERLACED
429 } } }; 429 } } };
430 size_t display_count = ARRAY_SIZE(displays); 430 size_t display_count = ARRAY_SIZE(displays);
431 #endif 431 #endif
432 432
433 static void setup_iomux_uart(void) 433 static void setup_iomux_uart(void)
434 { 434 {
435 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 435 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
436 } 436 }
437 437
438 #ifdef CONFIG_FSL_ESDHC 438 #ifdef CONFIG_FSL_ESDHC
439 439
440 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) 440 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
441 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) 441 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
442 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) 442 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
443 443
444 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 444 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
445 {USDHC1_BASE_ADDR, 0, 4}, 445 {USDHC1_BASE_ADDR, 0, 4},
446 {USDHC3_BASE_ADDR}, 446 {USDHC3_BASE_ADDR},
447 }; 447 };
448 448
449 int board_mmc_get_env_dev(int devno) 449 int board_mmc_get_env_dev(int devno)
450 { 450 {
451 if (devno == 2) 451 if (devno == 2)
452 devno--; 452 devno--;
453 453
454 return devno; 454 return devno;
455 } 455 }
456 456
457 int mmc_map_to_kernel_blk(int dev_no) 457 int mmc_map_to_kernel_blk(int dev_no)
458 { 458 {
459 if (dev_no == 1) 459 if (dev_no == 1)
460 dev_no++; 460 dev_no++;
461 461
462 return dev_no; 462 return dev_no;
463 } 463 }
464 464
465 int board_mmc_getcd(struct mmc *mmc) 465 int board_mmc_getcd(struct mmc *mmc)
466 { 466 {
467 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 467 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
468 int ret = 0; 468 int ret = 0;
469 469
470 switch (cfg->esdhc_base) { 470 switch (cfg->esdhc_base) {
471 case USDHC1_BASE_ADDR: 471 case USDHC1_BASE_ADDR:
472 ret = !gpio_get_value(USDHC1_CD_GPIO); 472 ret = !gpio_get_value(USDHC1_CD_GPIO);
473 break; 473 break;
474 case USDHC3_BASE_ADDR: 474 case USDHC3_BASE_ADDR:
475 ret = 1; /* Assume uSDHC3 emmc is always present */ 475 ret = 1; /* Assume uSDHC3 emmc is always present */
476 break; 476 break;
477 } 477 }
478 478
479 return ret; 479 return ret;
480 } 480 }
481 481
482 int board_mmc_init(bd_t *bis) 482 int board_mmc_init(bd_t *bis)
483 { 483 {
484 int i, ret; 484 int i, ret;
485 /* 485 /*
486 * According to the board_mmc_init() the following map is done: 486 * According to the board_mmc_init() the following map is done:
487 * (U-Boot device node) (Physical Port) 487 * (U-Boot device node) (Physical Port)
488 * mmc0 USDHC1 488 * mmc0 USDHC1
489 * mmc2 USDHC3 (eMMC) 489 * mmc2 USDHC3 (eMMC)
490 */ 490 */
491 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 491 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
492 switch (i) { 492 switch (i) {
493 case 0: 493 case 0:
494 imx_iomux_v3_setup_multiple_pads( 494 imx_iomux_v3_setup_multiple_pads(
495 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 495 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
496 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 496 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
497 gpio_direction_input(USDHC1_CD_GPIO); 497 gpio_direction_input(USDHC1_CD_GPIO);
498 gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); 498 gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
499 gpio_direction_output(USDHC1_PWR_GPIO, 0); 499 gpio_direction_output(USDHC1_PWR_GPIO, 0);
500 udelay(500); 500 udelay(500);
501 gpio_direction_output(USDHC1_PWR_GPIO, 1); 501 gpio_direction_output(USDHC1_PWR_GPIO, 1);
502 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 502 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
503 break; 503 break;
504 case 1: 504 case 1:
505 imx_iomux_v3_setup_multiple_pads( 505 imx_iomux_v3_setup_multiple_pads(
506 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); 506 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
507 gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); 507 gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
508 gpio_direction_output(USDHC3_PWR_GPIO, 0); 508 gpio_direction_output(USDHC3_PWR_GPIO, 0);
509 udelay(500); 509 udelay(500);
510 gpio_direction_output(USDHC3_PWR_GPIO, 1); 510 gpio_direction_output(USDHC3_PWR_GPIO, 1);
511 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 511 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
512 break; 512 break;
513 default: 513 default:
514 printf("Warning: you configured more USDHC controllers" 514 printf("Warning: you configured more USDHC controllers"
515 "(%d) than supported by the board\n", i + 1); 515 "(%d) than supported by the board\n", i + 1);
516 return -EINVAL; 516 return -EINVAL;
517 } 517 }
518 518
519 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 519 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
520 if (ret) 520 if (ret)
521 return ret; 521 return ret;
522 } 522 }
523 523
524 return 0; 524 return 0;
525 } 525 }
526 #endif 526 #endif
527 527
528 iomux_v3_cfg_t const fec2_en_pads[] = { 528 iomux_v3_cfg_t const fec2_en_pads[] = {
529 MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL), 529 MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
530 }; 530 };
531 #ifdef CONFIG_FEC_MXC 531 #ifdef CONFIG_FEC_MXC
532 static iomux_v3_cfg_t const fec1_pads[] = { 532 static iomux_v3_cfg_t const fec1_pads[] = {
533 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 533 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
534 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 534 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
535 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 535 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
536 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 536 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
537 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 537 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
538 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 538 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
539 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 539 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
540 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 540 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
541 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 541 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
542 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 542 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
543 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 543 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
544 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 544 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
545 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 545 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
546 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 546 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
547 }; 547 };
548 548
549 static iomux_v3_cfg_t const fec2_pads[] = { 549 static iomux_v3_cfg_t const fec2_pads[] = {
550 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 550 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
551 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 551 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
552 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 552 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
553 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 553 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
554 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 554 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
555 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 555 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
556 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 556 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
557 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 557 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
558 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 558 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
559 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 559 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
560 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 560 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
561 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 561 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
562 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 562 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
563 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 563 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
564 }; 564 };
565 565
566 static void setup_iomux_fec(void) 566 static void setup_iomux_fec(void)
567 { 567 {
568 if (0 == CONFIG_FEC_ENET_DEV) { 568 if (0 == CONFIG_FEC_ENET_DEV) {
569 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 569 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
570 } else { 570 } else {
571 if (mx7sabre_rev() >= BOARD_REV_B) { 571 if (mx7sabre_rev() >= BOARD_REV_B) {
572 /* On RevB, GPIO1_IO04 is used for ENET2 EN, 572 /* On RevB, GPIO1_IO04 is used for ENET2 EN,
573 * so set its output to low to enable ENET2 signals 573 * so set its output to low to enable ENET2 signals
574 */ 574 */
575 imx_iomux_v3_setup_multiple_pads(fec2_en_pads, 575 imx_iomux_v3_setup_multiple_pads(fec2_en_pads,
576 ARRAY_SIZE(fec2_en_pads)); 576 ARRAY_SIZE(fec2_en_pads));
577 gpio_direction_output(IMX_GPIO_NR(1, 4), 0); 577 gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
578 } 578 }
579 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); 579 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
580 } 580 }
581 } 581 }
582 582
583 int board_eth_init(bd_t *bis) 583 int board_eth_init(bd_t *bis)
584 { 584 {
585 int ret; 585 int ret;
586 586
587 setup_iomux_fec(); 587 setup_iomux_fec();
588 588
589 ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, 589 ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
590 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 590 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
591 if (ret) 591 if (ret)
592 printf("FEC1 MXC: %s:failed\n", __func__); 592 printf("FEC1 MXC: %s:failed\n", __func__);
593 593
594 return ret; 594 return ret;
595 } 595 }
596 596
597 static int setup_fec(int fec_id) 597 static int setup_fec(int fec_id)
598 { 598 {
599 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 599 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
600 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 600 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
601 601
602 if (0 == fec_id) { 602 if (0 == fec_id) {
603 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ 603 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
604 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 604 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
605 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | 605 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
606 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); 606 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
607 } else { 607 } else {
608 /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/ 608 /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/
609 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 609 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
610 (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | 610 (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
611 IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0); 611 IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
612 } 612 }
613 613
614 return set_clk_enet(ENET_125MHz); 614 return set_clk_enet(ENET_125MHz);
615 615
616 } 616 }
617 617
618 618
619 int board_phy_config(struct phy_device *phydev) 619 int board_phy_config(struct phy_device *phydev)
620 { 620 {
621 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 621 /* enable rgmii rxc skew and phy mode select to RGMII copper */
622 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); 622 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
623 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); 623 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
624 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); 624 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
625 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); 625 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
626 626
627 if (phydev->drv->config) 627 if (phydev->drv->config)
628 phydev->drv->config(phydev); 628 phydev->drv->config(phydev);
629 return 0; 629 return 0;
630 } 630 }
631 #endif 631 #endif
632 632
633 #ifdef CONFIG_FSL_QSPI 633 #ifdef CONFIG_FSL_QSPI
634 static iomux_v3_cfg_t const quadspi_pads[] = { 634 static iomux_v3_cfg_t const quadspi_pads[] = {
635 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 635 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
636 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 636 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
637 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 637 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
638 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 638 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
639 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), 639 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
640 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), 640 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
641 }; 641 };
642 642
643 int board_qspi_init(void) 643 int board_qspi_init(void)
644 { 644 {
645 /* Set the iomux */ 645 /* Set the iomux */
646 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 646 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
647 ARRAY_SIZE(quadspi_pads)); 647 ARRAY_SIZE(quadspi_pads));
648 648
649 /* Set the clock */ 649 /* Set the clock */
650 set_clk_qspi(); 650 set_clk_qspi();
651 651
652 return 0; 652 return 0;
653 } 653 }
654 #endif 654 #endif
655 655
656 #ifdef CONFIG_MXC_EPDC 656 #ifdef CONFIG_MXC_EPDC
657 static iomux_v3_cfg_t const epdc_enable_pads[] = { 657 static iomux_v3_cfg_t const epdc_enable_pads[] = {
658 MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 658 MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
659 MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 659 MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
660 MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 660 MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
661 MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 661 MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
662 MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 662 MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
663 MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 663 MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
664 MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 664 MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
665 MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 665 MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
666 MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), 666 MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
667 MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), 667 MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
668 MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), 668 MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
669 MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), 669 MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
670 MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 670 MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
671 MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 671 MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
672 MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), 672 MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
673 MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), 673 MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
674 MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), 674 MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
675 MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), 675 MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
676 MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 676 MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
677 MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 677 MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
678 }; 678 };
679 679
680 static iomux_v3_cfg_t const epdc_disable_pads[] = { 680 static iomux_v3_cfg_t const epdc_disable_pads[] = {
681 MX7D_PAD_EPDC_DATA00__GPIO2_IO0, 681 MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
682 MX7D_PAD_EPDC_DATA01__GPIO2_IO1, 682 MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
683 MX7D_PAD_EPDC_DATA02__GPIO2_IO2, 683 MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
684 MX7D_PAD_EPDC_DATA03__GPIO2_IO3, 684 MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
685 MX7D_PAD_EPDC_DATA04__GPIO2_IO4, 685 MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
686 MX7D_PAD_EPDC_DATA05__GPIO2_IO5, 686 MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
687 MX7D_PAD_EPDC_DATA06__GPIO2_IO6, 687 MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
688 MX7D_PAD_EPDC_DATA07__GPIO2_IO7, 688 MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
689 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, 689 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
690 MX7D_PAD_EPDC_SDLE__GPIO2_IO17, 690 MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
691 MX7D_PAD_EPDC_SDOE__GPIO2_IO18, 691 MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
692 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, 692 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
693 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, 693 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
694 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, 694 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
695 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, 695 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
696 MX7D_PAD_EPDC_GDOE__GPIO2_IO25, 696 MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
697 MX7D_PAD_EPDC_GDRL__GPIO2_IO26, 697 MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
698 MX7D_PAD_EPDC_GDSP__GPIO2_IO27, 698 MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
699 MX7D_PAD_EPDC_BDR0__GPIO2_IO28, 699 MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
700 MX7D_PAD_EPDC_BDR1__GPIO2_IO29, 700 MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
701 }; 701 };
702 702
703 vidinfo_t panel_info = { 703 vidinfo_t panel_info = {
704 .vl_refresh = 85, 704 .vl_refresh = 85,
705 .vl_col = 1024, 705 .vl_col = 1024,
706 .vl_row = 758, 706 .vl_row = 758,
707 .vl_pixclock = 40000000, 707 .vl_pixclock = 40000000,
708 .vl_left_margin = 12, 708 .vl_left_margin = 12,
709 .vl_right_margin = 76, 709 .vl_right_margin = 76,
710 .vl_upper_margin = 4, 710 .vl_upper_margin = 4,
711 .vl_lower_margin = 5, 711 .vl_lower_margin = 5,
712 .vl_hsync = 12, 712 .vl_hsync = 12,
713 .vl_vsync = 2, 713 .vl_vsync = 2,
714 .vl_sync = 0, 714 .vl_sync = 0,
715 .vl_mode = 0, 715 .vl_mode = 0,
716 .vl_flag = 0, 716 .vl_flag = 0,
717 .vl_bpix = 3, 717 .vl_bpix = 3,
718 .cmap = 0, 718 .cmap = 0,
719 }; 719 };
720 720
721 struct epdc_timing_params panel_timings = { 721 struct epdc_timing_params panel_timings = {
722 .vscan_holdoff = 4, 722 .vscan_holdoff = 4,
723 .sdoed_width = 10, 723 .sdoed_width = 10,
724 .sdoed_delay = 20, 724 .sdoed_delay = 20,
725 .sdoez_width = 10, 725 .sdoez_width = 10,
726 .sdoez_delay = 20, 726 .sdoez_delay = 20,
727 .gdclk_hp_offs = 524, 727 .gdclk_hp_offs = 524,
728 .gdsp_offs = 327, 728 .gdsp_offs = 327,
729 .gdoe_offs = 0, 729 .gdoe_offs = 0,
730 .gdclk_offs = 19, 730 .gdclk_offs = 19,
731 .num_ce = 1, 731 .num_ce = 1,
732 }; 732 };
733 733
734 static void setup_epdc_power(void) 734 static void setup_epdc_power(void)
735 { 735 {
736 /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ 736 /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
737 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 737 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
738 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 738 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
739 739
740 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 740 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
741 IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); 741 IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
742 742
743 /* Setup epdc voltage */ 743 /* Setup epdc voltage */
744 744
745 /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ 745 /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
746 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | 746 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
747 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 747 MUX_PAD_CTRL(EPDC_PAD_CTRL));
748 gpio_direction_input(IMX_GPIO_NR(2, 31)); 748 gpio_direction_input(IMX_GPIO_NR(2, 31));
749 749
750 /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ 750 /* EPDC_VCOM0 - GPIO4[14] for VCOM control */
751 imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | 751 imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
752 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 752 MUX_PAD_CTRL(EPDC_PAD_CTRL));
753 753
754 /* Set as output */ 754 /* Set as output */
755 gpio_direction_output(IMX_GPIO_NR(4, 14), 1); 755 gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
756 756
757 /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */ 757 /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */
758 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | 758 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
759 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 759 MUX_PAD_CTRL(EPDC_PAD_CTRL));
760 /* Set as output */ 760 /* Set as output */
761 gpio_direction_output(IMX_GPIO_NR(2, 23), 1); 761 gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
762 762
763 /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */ 763 /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */
764 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | 764 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
765 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 765 MUX_PAD_CTRL(EPDC_PAD_CTRL));
766 /* Set as output */ 766 /* Set as output */
767 gpio_direction_output(IMX_GPIO_NR(2, 30), 1); 767 gpio_direction_output(IMX_GPIO_NR(2, 30), 1);
768 } 768 }
769 769
770 static void epdc_enable_pins(void) 770 static void epdc_enable_pins(void)
771 { 771 {
772 /* epdc iomux settings */ 772 /* epdc iomux settings */
773 imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, 773 imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
774 ARRAY_SIZE(epdc_enable_pads)); 774 ARRAY_SIZE(epdc_enable_pads));
775 } 775 }
776 776
777 static void epdc_disable_pins(void) 777 static void epdc_disable_pins(void)
778 { 778 {
779 /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ 779 /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
780 imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, 780 imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
781 ARRAY_SIZE(epdc_disable_pads)); 781 ARRAY_SIZE(epdc_disable_pads));
782 } 782 }
783 783
784 static void setup_epdc(void) 784 static void setup_epdc(void)
785 { 785 {
786 /*** epdc Maxim PMIC settings ***/ 786 /*** epdc Maxim PMIC settings ***/
787 787
788 /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ 788 /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
789 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | 789 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
790 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 790 MUX_PAD_CTRL(EPDC_PAD_CTRL));
791 791
792 /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ 792 /* EPDC_VCOM0 - GPIO4[14] for VCOM control */
793 imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | 793 imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
794 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 794 MUX_PAD_CTRL(EPDC_PAD_CTRL));
795 795
796 /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ 796 /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
797 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | 797 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
798 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 798 MUX_PAD_CTRL(EPDC_PAD_CTRL));
799 799
800 /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ 800 /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
801 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | 801 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
802 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 802 MUX_PAD_CTRL(EPDC_PAD_CTRL));
803 803
804 /* Set pixel clock rates for EPDC in clock.c */ 804 /* Set pixel clock rates for EPDC in clock.c */
805 805
806 panel_info.epdc_data.wv_modes.mode_init = 0; 806 panel_info.epdc_data.wv_modes.mode_init = 0;
807 panel_info.epdc_data.wv_modes.mode_du = 1; 807 panel_info.epdc_data.wv_modes.mode_du = 1;
808 panel_info.epdc_data.wv_modes.mode_gc4 = 3; 808 panel_info.epdc_data.wv_modes.mode_gc4 = 3;
809 panel_info.epdc_data.wv_modes.mode_gc8 = 2; 809 panel_info.epdc_data.wv_modes.mode_gc8 = 2;
810 panel_info.epdc_data.wv_modes.mode_gc16 = 2; 810 panel_info.epdc_data.wv_modes.mode_gc16 = 2;
811 panel_info.epdc_data.wv_modes.mode_gc32 = 2; 811 panel_info.epdc_data.wv_modes.mode_gc32 = 2;
812 812
813 panel_info.epdc_data.epdc_timings = panel_timings; 813 panel_info.epdc_data.epdc_timings = panel_timings;
814 814
815 setup_epdc_power(); 815 setup_epdc_power();
816 } 816 }
817 817
818 void epdc_power_on(void) 818 void epdc_power_on(void)
819 { 819 {
820 unsigned int reg; 820 unsigned int reg;
821 struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; 821 struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
822 822
823 /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ 823 /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
824 gpio_set_value(IMX_GPIO_NR(2, 30), 1); 824 gpio_set_value(IMX_GPIO_NR(2, 30), 1);
825 udelay(1000); 825 udelay(1000);
826 826
827 /* Enable epdc signal pin */ 827 /* Enable epdc signal pin */
828 epdc_enable_pins(); 828 epdc_enable_pins();
829 829
830 /* Set PMIC Wakeup to high - enable Display power */ 830 /* Set PMIC Wakeup to high - enable Display power */
831 gpio_set_value(IMX_GPIO_NR(2, 23), 1); 831 gpio_set_value(IMX_GPIO_NR(2, 23), 1);
832 832
833 /* Wait for PWRGOOD == 1 */ 833 /* Wait for PWRGOOD == 1 */
834 while (1) { 834 while (1) {
835 reg = readl(&gpio_regs->gpio_psr); 835 reg = readl(&gpio_regs->gpio_psr);
836 if (!(reg & (1 << 31))) 836 if (!(reg & (1 << 31)))
837 break; 837 break;
838 838
839 udelay(100); 839 udelay(100);
840 } 840 }
841 841
842 /* Enable VCOM */ 842 /* Enable VCOM */
843 gpio_set_value(IMX_GPIO_NR(4, 14), 1); 843 gpio_set_value(IMX_GPIO_NR(4, 14), 1);
844 844
845 udelay(500); 845 udelay(500);
846 } 846 }
847 847
848 void epdc_power_off(void) 848 void epdc_power_off(void)
849 { 849 {
850 /* Set PMIC Wakeup to low - disable Display power */ 850 /* Set PMIC Wakeup to low - disable Display power */
851 gpio_set_value(IMX_GPIO_NR(2, 23), 0); 851 gpio_set_value(IMX_GPIO_NR(2, 23), 0);
852 852
853 /* Disable VCOM */ 853 /* Disable VCOM */
854 gpio_set_value(IMX_GPIO_NR(4, 14), 0); 854 gpio_set_value(IMX_GPIO_NR(4, 14), 0);
855 855
856 epdc_disable_pins(); 856 epdc_disable_pins();
857 857
858 /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ 858 /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
859 gpio_set_value(IMX_GPIO_NR(2, 30), 0); 859 gpio_set_value(IMX_GPIO_NR(2, 30), 0);
860 } 860 }
861 #endif 861 #endif
862 862
863 #ifdef CONFIG_USB_EHCI_MX7 863 #ifdef CONFIG_USB_EHCI_MX7
864 static iomux_v3_cfg_t const usb_otg1_pads[] = { 864 static iomux_v3_cfg_t const usb_otg1_pads[] = {
865 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 865 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
866 }; 866 };
867 867
868 static iomux_v3_cfg_t const usb_otg2_pads[] = { 868 static iomux_v3_cfg_t const usb_otg2_pads[] = {
869 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 869 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
870 }; 870 };
871 871
872 /* On RevB board, the GPIO_IO07 is muxed for OTG2 PWR */ 872 /* On RevB board, the GPIO_IO07 is muxed for OTG2 PWR */
873 iomux_v3_cfg_t const usb_otg2_revB_pads[] = { 873 iomux_v3_cfg_t const usb_otg2_revB_pads[] = {
874 MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 874 MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
875 }; 875 };
876 876
877 static void setup_usb(void) 877 static void setup_usb(void)
878 { 878 {
879 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, 879 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
880 ARRAY_SIZE(usb_otg1_pads)); 880 ARRAY_SIZE(usb_otg1_pads));
881 881
882 if (mx7sabre_rev() >= BOARD_REV_B) 882 if (mx7sabre_rev() >= BOARD_REV_B)
883 imx_iomux_v3_setup_multiple_pads(usb_otg2_revB_pads, 883 imx_iomux_v3_setup_multiple_pads(usb_otg2_revB_pads,
884 ARRAY_SIZE(usb_otg2_revB_pads)); 884 ARRAY_SIZE(usb_otg2_revB_pads));
885 else 885 else
886 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 886 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
887 ARRAY_SIZE(usb_otg2_pads)); 887 ARRAY_SIZE(usb_otg2_pads));
888 } 888 }
889 889
890 int board_usb_phy_mode(int port) 890 int board_usb_phy_mode(int port)
891 { 891 {
892 if (port == 0) 892 if (port == 0)
893 return usb_phy_mode(port); 893 return usb_phy_mode(port);
894 else 894 else
895 return USB_INIT_HOST; 895 return USB_INIT_HOST;
896 } 896 }
897 #endif 897 #endif
898 898
899 int board_early_init_f(void) 899 int board_early_init_f(void)
900 { 900 {
901 setup_iomux_uart(); 901 setup_iomux_uart();
902 902
903 #ifdef CONFIG_SYS_I2C_MXC 903 #ifdef CONFIG_SYS_I2C_MXC
904 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 904 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
905 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); 905 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
906 #endif 906 #endif
907 907
908 #ifdef CONFIG_USB_EHCI_MX7 908 #ifdef CONFIG_USB_EHCI_MX7
909 setup_usb(); 909 setup_usb();
910 #endif 910 #endif
911 911
912 return 0; 912 return 0;
913 } 913 }
914 914
915 int board_init(void) 915 int board_init(void)
916 { 916 {
917 /* address of boot parameters */ 917 /* address of boot parameters */
918 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 918 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
919 919
920 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 920 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
921 921
922 iox74lv_init(); 922 iox74lv_init();
923 923
924 #ifdef CONFIG_FEC_MXC 924 #ifdef CONFIG_FEC_MXC
925 setup_fec(CONFIG_FEC_ENET_DEV); 925 setup_fec(CONFIG_FEC_ENET_DEV);
926 #endif 926 #endif
927 927
928 #ifdef CONFIG_NAND_MXS 928 #ifdef CONFIG_NAND_MXS
929 setup_gpmi_nand(); 929 setup_gpmi_nand();
930 #endif 930 #endif
931 931
932 #ifdef CONFIG_FSL_QSPI 932 #ifdef CONFIG_FSL_QSPI
933 board_qspi_init(); 933 board_qspi_init();
934 #endif 934 #endif
935 935
936 #ifdef CONFIG_MXC_EPDC 936 #ifdef CONFIG_MXC_EPDC
937 if (mx7sabre_rev() >= BOARD_REV_B) { 937 if (mx7sabre_rev() >= BOARD_REV_B) {
938 /* On RevB, GPIO1_IO04 is used for ENET2 EN, 938 /* On RevB, GPIO1_IO04 is used for ENET2 EN,
939 * so set its output to high to isolate the ENET2 signals for EPDC 939 * so set its output to high to isolate the ENET2 signals for EPDC
940 */ 940 */
941 imx_iomux_v3_setup_multiple_pads(fec2_en_pads, 941 imx_iomux_v3_setup_multiple_pads(fec2_en_pads,
942 ARRAY_SIZE(fec2_en_pads)); 942 ARRAY_SIZE(fec2_en_pads));
943 gpio_direction_output(IMX_GPIO_NR(1, 4), 1); 943 gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
944 } else { 944 } else {
945 qn_output[5] = qn_disable; 945 qn_output[5] = qn_disable;
946 iox74lv_set(5); 946 iox74lv_set(5);
947 } 947 }
948 setup_epdc(); 948 setup_epdc();
949 #endif 949 #endif
950 950
951 return 0; 951 return 0;
952 } 952 }
953 953
954 #ifdef CONFIG_CMD_BMODE 954 #ifdef CONFIG_CMD_BMODE
955 static const struct boot_mode board_boot_modes[] = { 955 static const struct boot_mode board_boot_modes[] = {
956 /* 4 bit bus width */ 956 /* 4 bit bus width */
957 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 957 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
958 {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, 958 {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
959 /* TODO: Nand */ 959 /* TODO: Nand */
960 {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, 960 {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
961 {NULL, 0}, 961 {NULL, 0},
962 }; 962 };
963 #endif 963 #endif
964 964
965 #ifdef CONFIG_POWER 965 #ifdef CONFIG_POWER
966 #define I2C_PMIC 0 966 #define I2C_PMIC 0
967 int power_init_board(void) 967 int power_init_board(void)
968 { 968 {
969 struct pmic *p; 969 struct pmic *p;
970 int ret; 970 int ret;
971 unsigned int reg, rev_id; 971 unsigned int reg, rev_id;
972 972
973 ret = power_pfuze3000_init(I2C_PMIC); 973 ret = power_pfuze3000_init(I2C_PMIC);
974 if (ret) 974 if (ret)
975 return ret; 975 return ret;
976 976
977 p = pmic_get("PFUZE3000"); 977 p = pmic_get("PFUZE3000");
978 ret = pmic_probe(p); 978 ret = pmic_probe(p);
979 if (ret) 979 if (ret)
980 return ret; 980 return ret;
981 981
982 pmic_reg_read(p, PFUZE3000_DEVICEID, &reg); 982 pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
983 pmic_reg_read(p, PFUZE3000_REVID, &rev_id); 983 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
984 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 984 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
985 985
986 /* disable Low Power Mode during standby mode */ 986 /* disable Low Power Mode during standby mode */
987 pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg); 987 pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
988 reg |= 0x1; 988 reg |= 0x1;
989 pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); 989 pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
990 990
991 /* SW1A/1B mode set to APS/APS */ 991 /* SW1A/1B mode set to APS/APS */
992 reg = 0x8; 992 reg = 0x8;
993 pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); 993 pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
994 pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); 994 pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
995 995
996 /* SW1A/1B standby voltage set to 0.975V */ 996 /* SW1A/1B standby voltage set to 0.975V */
997 reg = 0xb; 997 reg = 0xb;
998 pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); 998 pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
999 pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); 999 pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
1000 1000
1001 /* decrease SW1B normal voltage to 0.975V */ 1001 /* decrease SW1B normal voltage to 0.975V */
1002 pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg); 1002 pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
1003 reg &= ~0x1f; 1003 reg &= ~0x1f;
1004 reg |= PFUZE3000_SW1AB_SETP(975); 1004 reg |= PFUZE3000_SW1AB_SETP(975);
1005 pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); 1005 pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
1006 1006
1007 return 0; 1007 return 0;
1008 } 1008 }
1009 #endif 1009 #endif
1010 1010
1011 int board_late_init(void) 1011 int board_late_init(void)
1012 { 1012 {
1013 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 1013 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
1014 #ifdef CONFIG_CMD_BMODE 1014 #ifdef CONFIG_CMD_BMODE
1015 add_board_boot_modes(board_boot_modes); 1015 add_board_boot_modes(board_boot_modes);
1016 #endif 1016 #endif
1017 1017
1018 #ifdef CONFIG_ENV_IS_IN_MMC 1018 #ifdef CONFIG_ENV_IS_IN_MMC
1019 board_late_mmc_env_init(); 1019 board_late_mmc_env_init();
1020 #endif 1020 #endif
1021 1021
1022 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 1022 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
1023 1023
1024 set_wdog_reset(wdog); 1024 set_wdog_reset(wdog);
1025 1025
1026 return 0; 1026 return 0;
1027 } 1027 }
1028 1028
1029 int checkboard(void) 1029 int checkboard(void)
1030 { 1030 {
1031 int rev = mx7sabre_rev(); 1031 int rev = mx7sabre_rev();
1032 char *revname; 1032 char *revname;
1033 1033
1034 switch (rev) { 1034 switch (rev) {
1035 case BOARD_REV_C: 1035 case BOARD_REV_C:
1036 revname = "C"; 1036 revname = "C";
1037 break; 1037 break;
1038 case BOARD_REV_B: 1038 case BOARD_REV_B:
1039 revname = "B"; 1039 revname = "B";
1040 break; 1040 break;
1041 case BOARD_REV_A: 1041 case BOARD_REV_A:
1042 default: 1042 default:
1043 revname = "A"; 1043 revname = "A";
1044 break; 1044 break;
1045 } 1045 }
1046 1046
1047 printf("Board: i.MX7D SABRESD Rev%s\n", revname); 1047 printf("Board: i.MX7D SABRESD Rev%s\n", revname);
1048 1048
1049 return 0; 1049 return 0;
1050 } 1050 }
1051 1051
1052 #ifdef CONFIG_FSL_FASTBOOT 1052 #ifdef CONFIG_FSL_FASTBOOT
1053 void board_fastboot_setup(void) 1053 void board_fastboot_setup(void)
1054 { 1054 {
1055 switch (get_boot_device()) { 1055 switch (get_boot_device()) {
1056 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 1056 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
1057 case SD1_BOOT: 1057 case SD1_BOOT:
1058 case MMC1_BOOT: 1058 case MMC1_BOOT:
1059 if (!getenv("fastboot_dev")) 1059 if (!getenv("fastboot_dev"))
1060 setenv("fastboot_dev", "mmc0"); 1060 setenv("fastboot_dev", "mmc0");
1061 if (!getenv("bootcmd")) 1061 if (!getenv("bootcmd"))
1062 setenv("bootcmd", "boota mmc0"); 1062 setenv("bootcmd", "boota mmc0");
1063 break; 1063 break;
1064 case SD3_BOOT: 1064 case SD3_BOOT:
1065 case MMC3_BOOT: 1065 case MMC3_BOOT:
1066 if (!getenv("fastboot_dev")) 1066 if (!getenv("fastboot_dev"))
1067 setenv("fastboot_dev", "mmc1"); 1067 setenv("fastboot_dev", "mmc1");
1068 if (!getenv("bootcmd")) 1068 if (!getenv("bootcmd"))
1069 setenv("bootcmd", "boota mmc1"); 1069 setenv("bootcmd", "boota mmc1");
1070 break; 1070 break;
1071 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 1071 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
1072 default: 1072 default:
1073 printf("unsupported boot devices\n"); 1073 printf("unsupported boot devices\n");
1074 break; 1074 break;
1075 } 1075 }
1076 } 1076 }
1077 1077
1078 #ifdef CONFIG_ANDROID_RECOVERY 1078 #ifdef CONFIG_ANDROID_RECOVERY
1079 1079
1080 /* Use S3 button for recovery key */ 1080 /* Use S3 button for recovery key */
1081 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10) 1081 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10)
1082 iomux_v3_cfg_t const recovery_key_pads[] = { 1082 iomux_v3_cfg_t const recovery_key_pads[] = {
1083 (MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)), 1083 (MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)),
1084 }; 1084 };
1085 1085
1086 int check_recovery_cmd_file(void) 1086 int check_recovery_cmd_file(void)
1087 { 1087 {
1088 int button_pressed = 0; 1088 int button_pressed = 0;
1089 int recovery_mode = 0; 1089 int recovery_mode = 0;
1090 1090
1091 recovery_mode = recovery_check_and_clean_flag(); 1091 recovery_mode = recovery_check_and_clean_flag();
1092 1092
1093 /* Check Recovery Combo Button press or not. */ 1093 /* Check Recovery Combo Button press or not. */
1094 imx_iomux_v3_setup_multiple_pads(recovery_key_pads, 1094 imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
1095 ARRAY_SIZE(recovery_key_pads)); 1095 ARRAY_SIZE(recovery_key_pads));
1096 1096
1097 gpio_direction_input(GPIO_VOL_DN_KEY); 1097 gpio_direction_input(GPIO_VOL_DN_KEY);
1098 1098
1099 if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ 1099 if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
1100 button_pressed = 1; 1100 button_pressed = 1;
1101 printf("Recovery key pressed\n"); 1101 printf("Recovery key pressed\n");
1102 } 1102 }
1103 1103
1104 return recovery_mode || button_pressed; 1104 return recovery_mode || button_pressed;
1105 } 1105 }
1106 1106
1107 void board_recovery_setup(void) 1107 void board_recovery_setup(void)
1108 { 1108 {
1109 int bootdev = get_boot_device(); 1109 int bootdev = get_boot_device();
1110 1110
1111 switch (bootdev) { 1111 switch (bootdev) {
1112 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 1112 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
1113 case SD1_BOOT: 1113 case SD1_BOOT:
1114 case MMC1_BOOT: 1114 case MMC1_BOOT:
1115 if (!getenv("bootcmd_android_recovery")) 1115 if (!getenv("bootcmd_android_recovery"))
1116 setenv("bootcmd_android_recovery", "boota mmc0 recovery"); 1116 setenv("bootcmd_android_recovery", "boota mmc0 recovery");
1117 break; 1117 break;
1118 case SD3_BOOT: 1118 case SD3_BOOT:
1119 case MMC3_BOOT: 1119 case MMC3_BOOT:
1120 if (!getenv("bootcmd_android_recovery")) 1120 if (!getenv("bootcmd_android_recovery"))
1121 setenv("bootcmd_android_recovery", "boota mmc1 recovery"); 1121 setenv("bootcmd_android_recovery", "boota mmc1 recovery");
1122 break; 1122 break;
1123 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 1123 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
1124 default: 1124 default:
1125 printf("Unsupported bootup device for recovery: dev: %d\n", 1125 printf("Unsupported bootup device for recovery: dev: %d\n",
1126 bootdev); 1126 bootdev);
1127 return; 1127 return;
1128 } 1128 }
1129 1129
1130 printf("setup env for recovery..\n"); 1130 printf("setup env for recovery..\n");
1131 setenv("bootcmd", "run bootcmd_android_recovery"); 1131 setenv("bootcmd", "run bootcmd_android_recovery");
1132 } 1132 }
1133 #endif /*CONFIG_ANDROID_RECOVERY*/ 1133 #endif /*CONFIG_ANDROID_RECOVERY*/
1134 1134
1135 #endif /*CONFIG_FSL_FASTBOOT*/ 1135 #endif /*CONFIG_FSL_FASTBOOT*/
1136 1136
1137 1137