Eric Lee / smarc-uboot | Embedian Git Server

Commit b60eff31f3bd71a6f14b6c6efc8ad5fb3705de6d

Authored by Albert ARIBAUD 2014-02-23 00:53:43 +0800

Exists in master and in 49 other branches

arm: remove unneeded symbol offsets and _TEXT_BASE

Remove the last uses of symbol offsets in ARM U-Boot.
Remove some needless uses of _TEXT_BASE.
Remove all _TEXT_BASE definitions.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>

Showing 26 changed files with 24 additions and 369 deletions Inline Diff

README
arch/arm/cpu/arm1136/start.S
arch/arm/cpu/arm1176/start.S
arch/arm/cpu/arm720t/start.S
arch/arm/cpu/arm920t/start.S
arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
arch/arm/cpu/arm926ejs/mxs/start.S
arch/arm/cpu/arm926ejs/start.S
arch/arm/cpu/arm946es/start.S
arch/arm/cpu/arm_intcm/start.S
arch/arm/cpu/armv7/omap3/lowlevel_init.S
arch/arm/cpu/armv7/start.S
arch/arm/cpu/pxa/start.S
arch/arm/cpu/sa1100/start.S
arch/arm/lib/board.c
board/armltd/integrator/lowlevel_init.S
board/cm4008/flash.c
board/cm41xx/flash.c
board/mpl/vcma9/lowlevel_init.S
board/samsung/goni/lowlevel_init.S
board/samsung/smdk2410/lowlevel_init.S
board/samsung/smdkc100/lowlevel_init.S
board/ti/omap5912osk/lowlevel_init.S
common/board_f.c
common/board_r.c
include/asm-generic/sections.h

README

Diff comments View file @ b60eff3

 #
 # (C) Copyright 2000 - 2013
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 Summary:
 ========
 This directory contains the source code for U-Boot, a boot loader for
 Embedded boards based on PowerPC, ARM, MIPS and several other
 processors, which can be installed in a boot ROM and used to
 initialize and test the hardware or to download and run application
 code.
 The development of U-Boot is closely related to Linux: some parts of
 the source code originate in the Linux source tree, we have some
 header files in common, and special provision has been made to
 support booting of Linux images.
 Some attention has been paid to make this software easily
 configurable and extendable. For instance, all monitor commands are
 implemented with the same call interface, so that it's very easy to
 add new commands. Also, instead of permanently adding rarely used
 code (for instance hardware test utilities) to the monitor, you can
 load and run it dynamically.
 Status:
 =======
 In general, all boards for which a configuration option exists in the
 Makefile have been tested to some extent and can be considered
 "working". In fact, many of them are used in production systems.
 In case of problems see the CHANGELOG and CREDITS files to find out
 who contributed the specific port. The boards.cfg file lists board
 maintainers.
 Note: There is no CHANGELOG file in the actual U-Boot source tree;
 it can be created dynamically from the Git log using:
 	make CHANGELOG
 Where to get help:
 ==================
 In case you have questions about, problems with or contributions for
 U-Boot you should send a message to the U-Boot mailing list at
 <u-boot@lists.denx.de>. There is also an archive of previous traffic
 on the mailing list - please search the archive before asking FAQ's.
 Please see http://lists.denx.de/pipermail/u-boot and
 http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
 Where to get source code:
 =========================
 The U-Boot source code is maintained in the git repository at
 git://www.denx.de/git/u-boot.git ; you can browse it online at
 http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
 The "snapshot" links on this page allow you to download tarballs of
 any version you might be interested in. Official releases are also
 available for FTP download from the ftp://ftp.denx.de/pub/u-boot/
 directory.
 Pre-built (and tested) images are available from
 ftp://ftp.denx.de/pub/u-boot/images/
 Where we come from:
 ===================
 - start from 8xxrom sources
 - create PPCBoot project (http://sourceforge.net/projects/ppcboot)
 - clean up code
 - make it easier to add custom boards
 - make it possible to add other [PowerPC] CPUs
 - extend functions, especially:
   * Provide extended interface to Linux boot loader
   * S-Record download
   * network boot
   * PCMCIA / CompactFlash / ATA disk / SCSI ... boot
 - create ARMBoot project (http://sourceforge.net/projects/armboot)
 - add other CPU families (starting with ARM)
 - create U-Boot project (http://sourceforge.net/projects/u-boot)
 - current project page: see http://www.denx.de/wiki/U-Boot
 Names and Spelling:
 ===================
 The "official" name of this project is "Das U-Boot". The spelling
 "U-Boot" shall be used in all written text (documentation, comments
 in source files etc.). Example:
 	This is the README file for the U-Boot project.
 File names etc. shall be based on the string "u-boot". Examples:
 	include/asm-ppc/u-boot.h
 	#include <asm/u-boot.h>
 Variable names, preprocessor constants etc. shall be either based on
 the string "u_boot" or on "U_BOOT". Example:
 	U_BOOT_VERSION		u_boot_logo
 	IH_OS_U_BOOT		u_boot_hush_start
 Versioning:
 ===========
 Starting with the release in October 2008, the names of the releases
 were changed from numerical release numbers without deeper meaning
 into a time stamp based numbering. Regular releases are identified by
 names consisting of the calendar year and month of the release date.
 Additional fields (if present) indicate release candidates or bug fix
 releases in "stable" maintenance trees.
 Examples:
 	U-Boot v2009.11	    - Release November 2009
 	U-Boot v2009.11.1   - Release 1 in version November 2009 stable tree
 	U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
 Directory Hierarchy:
 ====================
 /arch			Architecture specific files
   /arm			Files generic to ARM architecture
     /cpu		CPU specific files
       /arm720t		Files specific to ARM 720 CPUs
       /arm920t		Files specific to ARM 920 CPUs
 	/at91		Files specific to Atmel AT91RM9200 CPU
 	/imx		Files specific to Freescale MC9328 i.MX CPUs
 	/s3c24x0	Files specific to Samsung S3C24X0 CPUs
       /arm926ejs	Files specific to ARM 926 CPUs
       /arm1136		Files specific to ARM 1136 CPUs
       /pxa		Files specific to Intel XScale PXA CPUs
       /sa1100		Files specific to Intel StrongARM SA1100 CPUs
     /lib		Architecture specific library files
   /avr32		Files generic to AVR32 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /blackfin		Files generic to Analog Devices Blackfin architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /m68k			Files generic to m68k architecture
     /cpu		CPU specific files
       /mcf52x2		Files specific to Freescale ColdFire MCF52x2 CPUs
       /mcf5227x		Files specific to Freescale ColdFire MCF5227x CPUs
       /mcf532x		Files specific to Freescale ColdFire MCF5329 CPUs
       /mcf5445x		Files specific to Freescale ColdFire MCF5445x CPUs
       /mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
     /lib		Architecture specific library files
   /microblaze		Files generic to microblaze architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /mips			Files generic to MIPS architecture
     /cpu		CPU specific files
       /mips32		Files specific to MIPS32 CPUs
       /xburst		Files specific to Ingenic XBurst CPUs
     /lib		Architecture specific library files
   /nds32		Files generic to NDS32 architecture
     /cpu		CPU specific files
       /n1213		Files specific to Andes Technology N1213 CPUs
     /lib		Architecture specific library files
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /openrisc		Files generic to OpenRISC architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
   /powerpc		Files generic to PowerPC architecture
     /cpu		CPU specific files
       /74xx_7xx		Files specific to Freescale MPC74xx and 7xx CPUs
       /mpc5xx		Files specific to Freescale MPC5xx CPUs
       /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
       /mpc8xx		Files specific to Freescale MPC8xx CPUs
       /mpc824x		Files specific to Freescale MPC824x CPUs
       /mpc8260		Files specific to Freescale MPC8260 CPUs
       /mpc85xx		Files specific to Freescale MPC85xx CPUs
       /ppc4xx		Files specific to AMCC PowerPC 4xx CPUs
     /lib		Architecture specific library files
   /sh			Files generic to SH architecture
     /cpu		CPU specific files
       /sh2		Files specific to sh2 CPUs
       /sh3		Files specific to sh3 CPUs
       /sh4		Files specific to sh4 CPUs
     /lib		Architecture specific library files
   /sparc		Files generic to SPARC architecture
     /cpu		CPU specific files
       /leon2		Files specific to Gaisler LEON2 SPARC CPU
       /leon3		Files specific to Gaisler LEON3 SPARC CPU
     /lib		Architecture specific library files
   /x86			Files generic to x86 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
 /api			Machine/arch independent API for external apps
 /board			Board dependent files
 /common			Misc architecture independent functions
 /disk			Code for disk drive partition handling
 /doc			Documentation (don't expect too much)
 /drivers		Commonly used device drivers
 /dts			Contains Makefile for building internal U-Boot fdt.
 /examples		Example code for standalone applications, etc.
 /fs			Filesystem code (cramfs, ext2, jffs2, etc.)
 /include		Header Files
 /lib			Files generic to all architectures
   /libfdt		Library files to support flattened device trees
   /lzma			Library files to support LZMA decompression
   /lzo			Library files to support LZO decompression
 /net			Networking code
 /post			Power On Self Test
 /spl			Secondary Program Loader framework
 /tools			Tools to build S-Record or U-Boot images, etc.
 Software Configuration:
 =======================
 Configuration is usually done using C preprocessor defines; the
 rationale behind that is to avoid dead code whenever possible.
 There are two classes of configuration variables:
 * Configuration _OPTIONS_:
   These are selectable by the user and have names beginning with
   "CONFIG_".
 * Configuration _SETTINGS_:
   These depend on the hardware etc. and should not be meddled with if
   you don't know what you're doing; they have names beginning with
   "CONFIG_SYS_".
 Later we will add a configuration tool - probably similar to or even
 identical to what's used for the Linux kernel. Right now, we have to
 do the configuration by hand, which means creating some symbolic
 links and editing some configuration files. We use the TQM8xxL boards
 as an example here.
 Selection of Processor Architecture and Board Type:
 ---------------------------------------------------
 For all supported boards there are ready-to-use default
 configurations available; just type "make <board_name>_config".
 Example: For a TQM823L module type:
 	cd u-boot
 	make TQM823L_config
 For the Cogent platform, you need to specify the CPU type as well;
 e.g. "make cogent_mpc8xx_config". And also configure the cogent
 directory according to the instructions in cogent/README.
 Configuration Options:
 ----------------------
 Configuration depends on the combination of board and CPU type; all
 such information is kept in a configuration file
 "include/configs/<board_name>.h".
 Example: For a TQM823L module, all configuration settings are in
 "include/configs/TQM823L.h".
 Many of the options are named exactly as the corresponding Linux
 kernel configuration options. The intention is to make it easier to
 build a config tool - later.
 The following options need to be configured:
 - CPU Type:	Define exactly one, e.g. CONFIG_MPC85XX.
 - Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
 		Define exactly one, e.g. CONFIG_ATSTK1002
 - CPU Module Type: (if CONFIG_COGENT is defined)
 		Define exactly one of
 		CONFIG_CMA286_60_OLD
 --- FIXME --- not tested yet:
 		CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P,
 		CONFIG_CMA287_23, CONFIG_CMA287_50
 - Motherboard Type: (if CONFIG_COGENT is defined)
 		Define exactly one of
 		CONFIG_CMA101, CONFIG_CMA102
 - Motherboard I/O Modules: (if CONFIG_COGENT is defined)
 		Define one or more of
 		CONFIG_CMA302
 - Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
 		Define one or more of
 		CONFIG_LCD_HEARTBEAT	- update a character position on
 					  the LCD display every second with
 					  a "rotator" |\-/|\-/
 - Board flavour: (if CONFIG_MPC8260ADS is defined)
 		CONFIG_ADSTYPE
 		Possible values are:
 			CONFIG_SYS_8260ADS	- original MPC8260ADS
 			CONFIG_SYS_8266ADS	- MPC8266ADS
 			CONFIG_SYS_PQ2FADS	- PQ2FADS-ZU or PQ2FADS-VR
 			CONFIG_SYS_8272ADS	- MPC8272ADS
 - Marvell Family Member
 		CONFIG_SYS_MVFS		- define it if you want to enable
 					  multiple fs option at one time
 					  for marvell soc family
 - MPC824X Family Member (if CONFIG_MPC824X is defined)
 		Define exactly one of
 		CONFIG_MPC8240, CONFIG_MPC8245
 - 8xx CPU Options: (if using an MPC8xx CPU)
 		CONFIG_8xx_GCLK_FREQ	- deprecated: CPU clock if
 					  get_gclk_freq() cannot work
 					  e.g. if there is no 32KHz
 					  reference PIT/RTC clock
 		CONFIG_8xx_OSCLK	- PLL input clock (either EXTCLK
 					  or XTAL/EXTAL)
 - 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
 		CONFIG_SYS_8xx_CPUCLK_MIN
 		CONFIG_SYS_8xx_CPUCLK_MAX
 		CONFIG_8xx_CPUCLK_DEFAULT
 			See doc/README.MPC866
 		CONFIG_SYS_MEASURE_CPUCLK
 		Define this to measure the actual CPU clock instead
 		of relying on the correctness of the configured
 		values. Mostly useful for board bringup to make sure
 		the PLL is locked at the intended frequency. Note
 		that this requires a (stable) reference clock (32 kHz
 		RTC clock or CONFIG_SYS_8XX_XIN)
 		CONFIG_SYS_DELAYED_ICACHE
 		Define this option if you want to enable the
 		ICache only when Code runs from RAM.
 - 85xx CPU Options:
 		CONFIG_SYS_PPC64
 		Specifies that the core is a 64-bit PowerPC implementation (implements
 		the "64" category of the Power ISA). This is necessary for ePAPR
 		compliance, among other possible reasons.
 		CONFIG_SYS_FSL_TBCLK_DIV
 		Defines the core time base clock divider ratio compared to the
 		system clock.  On most PQ3 devices this is 8, on newer QorIQ
 		devices it can be 16 or 32.  The ratio varies from SoC to Soc.
 		CONFIG_SYS_FSL_PCIE_COMPAT
 		Defines the string to utilize when trying to match PCIe device
 		tree nodes for the given platform.
 		CONFIG_SYS_PPC_E500_DEBUG_TLB
 		Enables a temporary TLB entry to be used during boot to work
 		around limitations in e500v1 and e500v2 external debugger
 		support. This reduces the portions of the boot code where
 		breakpoints and single stepping do not work.  The value of this
 		symbol should be set to the TLB1 entry to be used for this
 		purpose.
 		CONFIG_SYS_FSL_ERRATUM_A004510
 		Enables a workaround for erratum A004510.  If set,
 		then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
 		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
 		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
 		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
 		Defines one or two SoC revisions (low 8 bits of SVR)
 		for which the A004510 workaround should be applied.
 		The rest of SVR is either not relevant to the decision
 		of whether the erratum is present (e.g. p2040 versus
 		p2041) or is implied by the build target, which controls
 		whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
 		See Freescale App Note 4493 for more information about
 		this erratum.
 		CONFIG_A003399_NOR_WORKAROUND
 		Enables a workaround for IFC erratum A003399. It is only
 		requred during NOR boot.
 		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 		This is the value to write into CCSR offset 0x18600
 		according to the A004510 workaround.
 		CONFIG_SYS_FSL_DSP_DDR_ADDR
 		This value denotes start offset of DDR memory which is
 		connected exclusively to the DSP cores.
 		CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
 		This value denotes start offset of M2 memory
 		which is directly connected to the DSP core.
 		CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
 		This value denotes start offset of M3 memory which is directly
 		connected to the DSP core.
 		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 		This value denotes start offset of DSP CCSR space.
 		CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 		Single Source Clock is clocking mode present in some of FSL SoC's.
 		In this mode, a single differential clock is used to supply
 		clocks to the sysclock, ddrclock and usbclock.
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 		Defines the endianess of the CPU. Implementation of those
 		values is arch specific.
 		CONFIG_SYS_FSL_DDR
 		Freescale DDR driver in use. This type of DDR controller is
 		found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
 		SoCs.
 		CONFIG_SYS_FSL_DDR_ADDR
 		Freescale DDR memory-mapped register base.
 		CONFIG_SYS_FSL_DDR_EMU
 		Specify emulator support for DDR. Some DDR features such as
 		deskew training are not available.
 		CONFIG_SYS_FSL_DDRC_GEN1
 		Freescale DDR1 controller.
 		CONFIG_SYS_FSL_DDRC_GEN2
 		Freescale DDR2 controller.
 		CONFIG_SYS_FSL_DDRC_GEN3
 		Freescale DDR3 controller.
 		CONFIG_SYS_FSL_DDRC_ARM_GEN3
 		Freescale DDR3 controller for ARM-based SoCs.
 		CONFIG_SYS_FSL_DDR1
 		Board config to use DDR1. It can be enabled for SoCs with
 		Freescale DDR1 or DDR2 controllers, depending on the board
 		implemetation.
 		CONFIG_SYS_FSL_DDR2
 		Board config to use DDR2. It can be eanbeld for SoCs with
 		Freescale DDR2 or DDR3 controllers, depending on the board
 		implementation.
 		CONFIG_SYS_FSL_DDR3
 		Board config to use DDR3. It can be enabled for SoCs with
 		Freescale DDR3 controllers.
 		CONFIG_SYS_FSL_IFC_BE
 		Defines the IFC controller register space as Big Endian
 		CONFIG_SYS_FSL_IFC_LE
 		Defines the IFC controller register space as Little Endian
 		CONFIG_SYS_FSL_PBL_PBI
 		It enables addition of RCW (Power on reset configuration) in built image.
 		Please refer doc/README.pblimage for more details
 		CONFIG_SYS_FSL_PBL_RCW
 		It adds PBI(pre-boot instructions) commands in u-boot build image.
 		PBI commands can be used to configure SoC before it starts the execution.
 		Please refer doc/README.pblimage for more details
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 		Defines the Monahans run mode to oscillator
 		ratio. Valid values are 8, 16, 24, 31. The core
 		frequency is this value multiplied by 13 MHz.
 		CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
 		Defines the Monahans turbo mode to oscillator
 		ratio. Valid values are 1 (default if undefined) and
 		2. The core frequency as calculated above is multiplied
 		by this value.
 - MIPS CPU options:
 		CONFIG_SYS_INIT_SP_OFFSET
 		Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
 		pointer. This is needed for the temporary stack before
 		relocation.
 		CONFIG_SYS_MIPS_CACHE_MODE
 		Cache operation mode for the MIPS CPU.
 		See also arch/mips/include/asm/mipsregs.h.
 		Possible values are:
 			CONF_CM_CACHABLE_NO_WA
 			CONF_CM_CACHABLE_WA
 			CONF_CM_UNCACHED
 			CONF_CM_CACHABLE_NONCOHERENT
 			CONF_CM_CACHABLE_CE
 			CONF_CM_CACHABLE_COW
 			CONF_CM_CACHABLE_CUW
 			CONF_CM_CACHABLE_ACCELERATED
 		CONFIG_SYS_XWAY_EBU_BOOTCFG
 		Special option for Lantiq XWAY SoCs for booting from NOR flash.
 		See also arch/mips/cpu/mips32/start.S.
 		CONFIG_XWAY_SWAP_BYTES
 		Enable compilation of tools/xway-swap-bytes needed for Lantiq
 		XWAY SoCs for booting from NOR flash. The U-Boot image needs to
 		be swapped if a flash programmer is used.
 - ARM options:
 		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 		Select high exception vectors of the ARM core, e.g., do not
 		clear the V bit of the c1 register of CP15.
 		CONFIG_SYS_THUMB_BUILD
 		Use this flag to build U-Boot using the Thumb instruction
 		set for ARM architectures. Thumb instruction set provides
 		better code density. For ARM architectures that support
 		Thumb2 this flag will result in Thumb2 code generated by
 		GCC.
 		CONFIG_ARM_ERRATA_716044
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
 		workarounds to be applied; no CPU-type/version detection
 		exists, unlike the similar options in the Linux kernel. Do not
 		set these options unless they apply!
 - CPU timer options:
 		CONFIG_SYS_HZ
 		The frequency of the timer returned by get_timer().
 		get_timer() must operate in milliseconds and this CONFIG
 		option must be set to 1000.
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 		U-Boot stores all clock information in Hz
 		internally. For binary compatibility with older Linux
 		kernels (which expect the clocks passed in the
 		bd_info data to be in MHz) the environment variable
 		"clocks_in_mhz" can be defined so that U-Boot
 		converts clock data to MHZ before passing it to the
 		Linux kernel.
 		When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
 		"clocks_in_mhz=1" is automatically included in the
 		default environment.
 		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
 		When transferring memsize parameter to linux, some versions
 		expect it to be in bytes, others in MB.
 		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
 		CONFIG_OF_LIBFDT
 		New kernel versions are expecting firmware settings to be
 		passed using flattened device trees (based on open firmware
 		concepts).
 		CONFIG_OF_LIBFDT
 		 * New libfdt-based support
 		 * Adds the "fdt" command
 		 * The bootm command automatically updates the fdt
 		OF_CPU - The proper name of the cpus node (only required for
 			MPC512X and MPC5xxx based boards).
 		OF_SOC - The proper name of the soc node (only required for
 			MPC512X and MPC5xxx based boards).
 		OF_TBCLK - The timebase frequency.
 		OF_STDOUT_PATH - The path to the console device
 		boards with QUICC Engines require OF_QE to set UCC MAC
 		addresses
 		CONFIG_OF_BOARD_SETUP
 		Board code has addition modification that it wants to make
 		to the flat device tree before handing it off to the kernel
 		CONFIG_OF_BOOT_CPU
 		This define fills in the correct boot CPU in the boot
 		param header, the default value is zero if undefined.
 		CONFIG_OF_IDE_FIXUP
 		U-Boot can detect if an IDE device is present or not.
 		If not, and this new config option is activated, U-Boot
 		removes the ATA node from the DTS before booting Linux,
 		so the Linux IDE driver does not probe the device and
 		crash. This is needed for buggy hardware (uc101) where
 		no pull down resistor is connected to the signal IDE5V_DD7.
 		CONFIG_MACH_TYPE	[relevant for ARM only][mandatory]
 		This setting is mandatory for all boards that have only one
 		machine type and must be used to specify the machine type
 		number as it appears in the ARM machine registry
 		(see http://www.arm.linux.org.uk/developer/machines/).
 		Only boards that have multiple machine types supported
 		in a single configuration file and the machine type is
 		runtime discoverable, do not have to use this setting.
 - vxWorks boot parameters:
 		bootvx constructs a valid bootline using the following
 		environments variables: bootfile, ipaddr, serverip, hostname.
 		It loads the vxWorks image pointed bootfile.
 		CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name
 		CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address
 		CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server
 		CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters
 		CONFIG_SYS_VXWORKS_ADD_PARAMS
 		Add it at the end of the bootline. E.g "u=username pw=secret"
 		Note: If a "bootargs" environment is defined, it will overwride
 		the defaults discussed just above.
 - Cache Configuration:
 		CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
 		CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
 		CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
 - Cache Configuration for ARM:
 		CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
 				      controller
 		CONFIG_SYS_PL310_BASE - Physical base address of PL310
 					controller register space
 - Serial Ports:
 		CONFIG_PL010_SERIAL
 		Define this if you want support for Amba PrimeCell PL010 UARTs.
 		CONFIG_PL011_SERIAL
 		Define this if you want support for Amba PrimeCell PL011 UARTs.
 		CONFIG_PL011_CLOCK
 		If you have Amba PrimeCell PL011 UARTs, set this variable to
 		the clock speed of the UARTs.
 		CONFIG_PL01x_PORTS
 		If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
 		define this to a list of base addresses for each (supported)
 		port. See e.g. include/configs/versatile.h
 		CONFIG_PL011_SERIAL_RLCR
 		Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500)
 		have separate receive and transmit line control registers.  Set
 		this variable to initialize the extra register.
 		CONFIG_PL011_SERIAL_FLUSH_ON_INIT
 		On some platforms (e.g. U8500) U-Boot is loaded by a second stage
 		boot loader that has already initialized the UART.  Define this
 		variable to flush the UART at init time.
 - Console Interface:
 		Depending on board, define exactly one serial port
 		(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
 		CONFIG_8xx_CONS_SCC1, ...), or switch off the serial
 		console by defining CONFIG_8xx_CONS_NONE
 		Note: if CONFIG_8xx_CONS_NONE is defined, the serial
 		port routines must be defined elsewhere
 		(i.e. serial_init(), serial_getc(), ...)
 		CONFIG_CFB_CONSOLE
 		Enables console device for a color framebuffer. Needs following
 		defines (cf. smiLynxEM, i8042)
 			VIDEO_FB_LITTLE_ENDIAN	graphic memory organisation
 						(default big endian)
 			VIDEO_HW_RECTFILL	graphic chip supports
 						rectangle fill
 						(cf. smiLynxEM)
 			VIDEO_HW_BITBLT		graphic chip supports
 						bit-blit (cf. smiLynxEM)
 			VIDEO_VISIBLE_COLS	visible pixel columns
 						(cols=pitch)
 			VIDEO_VISIBLE_ROWS	visible pixel rows
 			VIDEO_PIXEL_SIZE	bytes per pixel
 			VIDEO_DATA_FORMAT	graphic data format
 						(0-5, cf. cfb_console.c)
 			VIDEO_FB_ADRS		framebuffer address
 			VIDEO_KBD_INIT_FCT	keyboard int fct
 						(i.e. i8042_kbd_init())
 			VIDEO_TSTC_FCT		test char fct
 						(i.e. i8042_tstc)
 			VIDEO_GETC_FCT		get char fct
 						(i.e. i8042_getc)
 			CONFIG_CONSOLE_CURSOR	cursor drawing on/off
 						(requires blink timer
 						cf. i8042.c)
 			CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
 			CONFIG_CONSOLE_TIME	display time/date info in
 						upper right corner
 						(requires CONFIG_CMD_DATE)
 			CONFIG_VIDEO_LOGO	display Linux logo in
 						upper left corner
 			CONFIG_VIDEO_BMP_LOGO	use bmp_logo.h instead of
 						linux_logo.h for logo.
 						Requires CONFIG_VIDEO_LOGO
 			CONFIG_CONSOLE_EXTRA_INFO
 						additional board info beside
 						the logo
 		When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
 		a limited number of ANSI escape sequences (cursor control,
 		erase functions and limited graphics rendition control).
 		When CONFIG_CFB_CONSOLE is defined, video console is
 		default i/o. Serial console can be forced with
 		environment 'console=serial'.
 		When CONFIG_SILENT_CONSOLE is defined, all console
 		messages (by U-Boot and Linux!) can be silenced with
 		the "silent" environment variable. See
 		doc/README.silent for more information.
 		CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
 			is 0x00.
 		CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
 			is 0xa0.
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
 		CONFIG_SYS_BAUDRATE_TABLE, see below.
 		CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
 - Console Rx buffer length
 		With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
 		the maximum receive buffer length for the SMC.
 		This option is actual only for 82xx and 8xx possible.
 		If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
 		must be defined, to setup the maximum idle timeout for
 		the SMC.
 - Pre-Console Buffer:
 		Prior to the console being initialised (i.e. serial UART
 		initialised etc) all console output is silently discarded.
 		Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
 		buffer any console messages prior to the console being
 		initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
 		bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
 		a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
 		bytes are output before the console is initialised, the
 		earlier bytes are discarded.
 		'Sane' compilers will generate smaller code if
 		CONFIG_PRE_CON_BUF_SZ is a power of 2
 - Safe printf() functions
 		Define CONFIG_SYS_VSNPRINTF to compile in safe versions of
 		the printf() functions. These are defined in
 		include/vsprintf.h and include snprintf(), vsnprintf() and
 		so on. Code size increase is approximately 300-500 bytes.
 		If this option is not given then these functions will
 		silently discard their buffer size argument - this means
 		you are not getting any overflow checking in this case.
 - Boot Delay:	CONFIG_BOOTDELAY - in seconds
 		Delay before automatically booting the default image;
 		set to -1 to disable autoboot.
 		set to -2 to autoboot with no delay and not check for abort
 		(even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
 		See doc/README.autoboot for these options that
 		work with CONFIG_BOOTDELAY. None are required.
 		CONFIG_BOOT_RETRY_TIME
 		CONFIG_BOOT_RETRY_MIN
 		CONFIG_AUTOBOOT_KEYED
 		CONFIG_AUTOBOOT_PROMPT
 		CONFIG_AUTOBOOT_DELAY_STR
 		CONFIG_AUTOBOOT_STOP_STR
 		CONFIG_AUTOBOOT_DELAY_STR2
 		CONFIG_AUTOBOOT_STOP_STR2
 		CONFIG_ZERO_BOOTDELAY_CHECK
 		CONFIG_RESET_TO_RETRY
 - Autoboot Command:
 		CONFIG_BOOTCOMMAND
 		Only needed when CONFIG_BOOTDELAY is enabled;
 		define a command string that is automatically executed
 		when no character is read on the console interface
 		within "Boot Delay" after reset.
 		CONFIG_BOOTARGS
 		This can be used to pass arguments to the bootm
 		command. The value of CONFIG_BOOTARGS goes into the
 		environment value "bootargs".
 		CONFIG_RAMBOOT and CONFIG_NFSBOOT
 		The value of these goes into the environment as
 		"ramboot" and "nfsboot" respectively, and can be used
 		as a convenience, when switching between booting from
 		RAM and NFS.
 - Bootcount:
 		CONFIG_BOOTCOUNT_LIMIT
 		Implements a mechanism for detecting a repeating reboot
 		cycle, see:
 		http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
 		CONFIG_BOOTCOUNT_ENV
 		If no softreset save registers are found on the hardware
 		"bootcount" is stored in the environment. To prevent a
 		saveenv on all reboots, the environment variable
 		"upgrade_available" is used. If "upgrade_available" is
 		0, "bootcount" is always 0, if "upgrade_available" is
 		1 "bootcount" is incremented in the environment.
 		So the Userspace Applikation must set the "upgrade_available"
 		and "bootcount" variable to 0, if a boot was successfully.
 - Pre-Boot Commands:
 		CONFIG_PREBOOT
 		When this option is #defined, the existence of the
 		environment variable "preboot" will be checked
 		immediately before starting the CONFIG_BOOTDELAY
 		countdown and/or running the auto-boot command resp.
 		entering interactive mode.
 		This feature is especially useful when "preboot" is
 		automatically generated or modified. For an example
 		see the LWMON board specific code: here "preboot" is
 		modified when the user holds down a certain
 		combination of keys on the (special) keyboard when
 		booting the systems
 - Serial Download Echo Mode:
 		CONFIG_LOADS_ECHO
 		If defined to 1, all characters received during a
 		serial download (using the "loads" command) are
 		echoed back. This might be needed by some terminal
 		emulations (like "cu"), but may as well just take
 		time on others. This setting #define's the initial
 		value of the "loads_echo" environment variable.
 - Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
 		CONFIG_KGDB_BAUDRATE
 		Select one of the baudrates listed in
 		CONFIG_SYS_BAUDRATE_TABLE, see below.
 - Monitor Functions:
 		Monitor commands can be included or excluded
 		from the build by using the #include files
 		<config_cmd_all.h> and #undef'ing unwanted
 		commands, or using <config_cmd_default.h>
 		and augmenting with additional #define's
 		for wanted commands.
 		The default command configuration includes all commands
 		except those marked below with a "*".
 		CONFIG_CMD_ASKENV	* ask for env variable
 		CONFIG_CMD_BDI		  bdinfo
 		CONFIG_CMD_BEDBUG	* Include BedBug Debugger
 		CONFIG_CMD_BMP		* BMP support
 		CONFIG_CMD_BSP		* Board specific commands
 		CONFIG_CMD_BOOTD	  bootd
 		CONFIG_CMD_CACHE	* icache, dcache
 		CONFIG_CMD_CLK   	* clock command support
 		CONFIG_CMD_CONSOLE	  coninfo
 		CONFIG_CMD_CRC32	* crc32
 		CONFIG_CMD_DATE		* support for RTC, date/time...
 		CONFIG_CMD_DHCP		* DHCP support
 		CONFIG_CMD_DIAG		* Diagnostics
 		CONFIG_CMD_DS4510	* ds4510 I2C gpio commands
 		CONFIG_CMD_DS4510_INFO	* ds4510 I2C info command
 		CONFIG_CMD_DS4510_MEM	* ds4510 I2C eeprom/sram commansd
 		CONFIG_CMD_DS4510_RST	* ds4510 I2C rst command
 		CONFIG_CMD_DTT		* Digital Therm and Thermostat
 		CONFIG_CMD_ECHO		  echo arguments
 		CONFIG_CMD_EDITENV	  edit env variable
 		CONFIG_CMD_EEPROM	* EEPROM read/write support
 		CONFIG_CMD_ELF		* bootelf, bootvx
 		CONFIG_CMD_ENV_CALLBACK	* display details about env callbacks
 		CONFIG_CMD_ENV_FLAGS	* display details about env flags
 		CONFIG_CMD_ENV_EXISTS	* check existence of env variable
 		CONFIG_CMD_EXPORTENV	* export the environment
 		CONFIG_CMD_EXT2		* ext2 command support
 		CONFIG_CMD_EXT4		* ext4 command support
 		CONFIG_CMD_FS_GENERIC	* filesystem commands (e.g. load, ls)
 					  that work for multiple fs types
 		CONFIG_CMD_SAVEENV	  saveenv
 		CONFIG_CMD_FDC		* Floppy Disk Support
 		CONFIG_CMD_FAT		* FAT command support
 		CONFIG_CMD_FDOS		* Dos diskette Support
 		CONFIG_CMD_FLASH	  flinfo, erase, protect
 		CONFIG_CMD_FPGA		  FPGA device initialization support
 		CONFIG_CMD_FUSE		* Device fuse support
 		CONFIG_CMD_GETTIME	* Get time since boot
 		CONFIG_CMD_GO		* the 'go' command (exec code)
 		CONFIG_CMD_GREPENV	* search environment
 		CONFIG_CMD_HASH		* calculate hash / digest
 		CONFIG_CMD_HWFLOW	* RTS/CTS hw flow control
 		CONFIG_CMD_I2C		* I2C serial bus support
 		CONFIG_CMD_IDE		* IDE harddisk support
 		CONFIG_CMD_IMI		  iminfo
 		CONFIG_CMD_IMLS		  List all images found in NOR flash
 		CONFIG_CMD_IMLS_NAND	* List all images found in NAND flash
 		CONFIG_CMD_IMMAP	* IMMR dump support
 		CONFIG_CMD_IMPORTENV	* import an environment
 		CONFIG_CMD_INI		* import data from an ini file into the env
 		CONFIG_CMD_IRQ		* irqinfo
 		CONFIG_CMD_ITEST	  Integer/string test of 2 values
 		CONFIG_CMD_JFFS2	* JFFS2 Support
 		CONFIG_CMD_KGDB		* kgdb
 		CONFIG_CMD_LDRINFO	* ldrinfo (display Blackfin loader)
 		CONFIG_CMD_LINK_LOCAL	* link-local IP address auto-configuration
 					  (169.254.*.*)
 		CONFIG_CMD_LOADB	  loadb
 		CONFIG_CMD_LOADS	  loads
 		CONFIG_CMD_MD5SUM	* print md5 message digest
 					  (requires CONFIG_CMD_MEMORY and CONFIG_MD5)
 		CONFIG_CMD_MEMINFO	* Display detailed memory information
 		CONFIG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 					  loop, loopw
 		CONFIG_CMD_MEMTEST	* mtest
 		CONFIG_CMD_MISC		  Misc functions like sleep etc
 		CONFIG_CMD_MMC		* MMC memory mapped support
 		CONFIG_CMD_MII		* MII utility commands
 		CONFIG_CMD_MTDPARTS	* MTD partition support
 		CONFIG_CMD_NAND		* NAND support
 		CONFIG_CMD_NET		  bootp, tftpboot, rarpboot
 		CONFIG_CMD_NFS		  NFS support
 		CONFIG_CMD_PCA953X	* PCA953x I2C gpio commands
 		CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
 		CONFIG_CMD_PCI		* pciinfo
 		CONFIG_CMD_PCMCIA		* PCMCIA support
 		CONFIG_CMD_PING		* send ICMP ECHO_REQUEST to network
 					  host
 		CONFIG_CMD_PORTIO	* Port I/O
 		CONFIG_CMD_READ		* Read raw data from partition
 		CONFIG_CMD_REGINFO	* Register dump
 		CONFIG_CMD_RUN		  run command in env variable
 		CONFIG_CMD_SANDBOX	* sb command to access sandbox features
 		CONFIG_CMD_SAVES	* save S record dump
 		CONFIG_CMD_SCSI		* SCSI Support
 		CONFIG_CMD_SDRAM	* print SDRAM configuration information
 					  (requires CONFIG_CMD_I2C)
 		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
 					  (4xx only)
 		CONFIG_CMD_SF		* Read/write/erase SPI NOR flash
 		CONFIG_CMD_SHA1SUM	* print sha1 memory digest
 					  (requires CONFIG_CMD_MEMORY)
 		CONFIG_CMD_SOFTSWITCH	* Soft switch setting command for BF60x
 		CONFIG_CMD_SOURCE	  "source" command Support
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_TFTPSRV	* TFTP transfer in server mode
 		CONFIG_CMD_TFTPPUT	* TFTP put command (upload)
 		CONFIG_CMD_TIME		* run command and report execution time (ARM specific)
 		CONFIG_CMD_TIMER	* access to the system tick timer
 		CONFIG_CMD_USB		* USB support
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_MFSL		* Microblaze FSL support
 		CONFIG_CMD_XIMG		  Load part of Multi Image
 		EXAMPLE: If you want all functions except of network
 		support you can write:
 		#include "config_cmd_all.h"
 		#undef CONFIG_CMD_NET
 	Other Commands:
 		fdt (flattened device tree) command: CONFIG_OF_LIBFDT
 	Note:	Don't enable the "icache" and "dcache" commands
 		(configuration option CONFIG_CMD_CACHE) unless you know
 		what you (and your U-Boot users) are doing. Data
 		cache cannot be enabled on systems like the 8xx or
 		8260 (where accesses to the IMMR region must be
 		uncached), and it cannot be disabled on all other
 		systems where we (mis-) use the data cache to hold an
 		initial stack and some data.
 		XXX - this list needs to get updated!
 - Regular expression support:
 		CONFIG_REGEX
 		If this variable is defined, U-Boot is linked against
 		the SLRE (Super Light Regular Expression) library,
 		which adds regex support to some commands, as for
 		example "env grep" and "setexpr".
 - Device tree:
 		CONFIG_OF_CONTROL
 		If this variable is defined, U-Boot will use a device tree
 		to configure its devices, instead of relying on statically
 		compiled #defines in the board file. This option is
 		experimental and only available on a few boards. The device
 		tree is available in the global data as gd->fdt_blob.
 		U-Boot needs to get its device tree from somewhere. This can
 		be done using one of the two options below:
 		CONFIG_OF_EMBED
 		If this variable is defined, U-Boot will embed a device tree
 		binary in its image. This device tree file should be in the
 		board directory and called <soc>-<board>.dts. The binary file
 		is then picked up in board_init_f() and made available through
 		the global data structure as gd->blob.
 		CONFIG_OF_SEPARATE
 		If this variable is defined, U-Boot will build a device tree
 		binary. It will be called u-boot.dtb. Architecture-specific
 		code will locate it at run-time. Generally this works by:
 			cat u-boot.bin u-boot.dtb >image.bin
 		and in fact, U-Boot does this for you, creating a file called
 		u-boot-dtb.bin which is useful in the common case. You can
 		still use the individual files if you need something more
 		exotic.
 - Watchdog:
 		CONFIG_WATCHDOG
 		If this variable is defined, it enables watchdog
 		support for the SoC. There must be support in the SoC
 		specific code for a watchdog. For the 8xx and 8260
 		CPUs, the SIU Watchdog feature is enabled in the SYPCR
 		register.  When supported for a specific SoC is
 		available, then no further board specific code should
 		be needed to use it.
 		CONFIG_HW_WATCHDOG
 		When using a watchdog circuitry external to the used
 		SoC, then define this variable and provide board
 		specific code for the "hw_watchdog_reset" function.
 - U-Boot Version:
 		CONFIG_VERSION_VARIABLE
 		If this variable is defined, an environment variable
 		named "ver" is created by U-Boot showing the U-Boot
 		version as printed by the "version" command.
 		Any change to this variable will be reverted at the
 		next reset.
 - Real-Time Clock:
 		When CONFIG_CMD_DATE is selected, the type of the RTC
 		has to be selected, too. Define exactly one of the
 		following options:
 		CONFIG_RTC_MPC8xx	- use internal RTC of MPC8xx
 		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
 		CONFIG_RTC_MC13XXX	- use MC13783 or MC13892 RTC
 		CONFIG_RTC_MC146818	- use MC146818 RTC
 		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
 		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
 		CONFIG_RTC_ISL1208	- use Intersil ISL1208 RTC
 		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC
 		CONFIG_SYS_RTC_DS1337_NOOSC	- Turn off the OSC output for DS1337
 		CONFIG_SYS_RV3029_TCR	- enable trickle charger on
 					  RV3029 RTC.
 		Note that if the RTC uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 - GPIO Support:
 		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
 		The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
 		chip-ngpio pairs that tell the PCA953X driver the number of
 		pins supported by a particular chip.
 		Note that if the GPIO device uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 - Timestamp Support:
 		When CONFIG_TIMESTAMP is selected, the timestamp
 		(date and time) of an image is printed by image
 		commands like bootm or iminfo. This option is
 		automatically enabled when you select CONFIG_CMD_DATE .
 - Partition Labels (disklabels) Supported:
 		Zero or more of the following:
 		CONFIG_MAC_PARTITION   Apple's MacOS partition table.
 		CONFIG_DOS_PARTITION   MS Dos partition table, traditional on the
 				       Intel architecture, USB sticks, etc.
 		CONFIG_ISO_PARTITION   ISO partition table, used on CDROM etc.
 		CONFIG_EFI_PARTITION   GPT partition table, common when EFI is the
 				       bootloader.  Note 2TB partition limit; see
 				       disk/part_efi.c
 		CONFIG_MTD_PARTITIONS  Memory Technology Device partition table.
 		If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
 		CONFIG_CMD_SCSI) you must configure support for at
 		least one non-MTD partition type as well.
 - IDE Reset method:
 		CONFIG_IDE_RESET_ROUTINE - this is defined in several
 		board configurations files but used nowhere!
 		CONFIG_IDE_RESET - is this is defined, IDE Reset will
 		be performed by calling the function
 			ide_set_reset(int reset)
 		which has to be defined in a board specific file
 - ATAPI Support:
 		CONFIG_ATAPI
 		Set this to enable ATAPI support.
 - LBA48 Support
 		CONFIG_LBA48
 		Set this to enable support for disks larger than 137GB
 		Also look at CONFIG_SYS_64BIT_LBA.
 		Whithout these , LBA48 support uses 32bit variables and will 'only'
 		support disks up to 2.1TB.
 		CONFIG_SYS_64BIT_LBA:
 			When enabled, makes the IDE subsystem use 64bit sector addresses.
 			Default is 32bit.
 - SCSI Support:
 		At the moment only there is only support for the
 		SYM53C8XX SCSI controller; define
 		CONFIG_SCSI_SYM53C8XX to enable it.
 		CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
 		CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
 		CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
 		maximum numbers of LUNs, SCSI ID's and target
 		devices.
 		CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
 		The environment variable 'scsidevs' is set to the number of
 		SCSI devices found during the last scan.
 - NETWORK Support (PCI):
 		CONFIG_E1000
 		Support for Intel 8254x/8257x gigabit chips.
 		CONFIG_E1000_SPI
 		Utility code for direct access to the SPI bus on Intel 8257x.
 		This does not do anything useful unless you set at least one
 		of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.
 		CONFIG_E1000_SPI_GENERIC
 		Allow generic access to the SPI bus on the Intel 8257x, for
 		example with the "sspi" command.
 		CONFIG_CMD_E1000
 		Management command for E1000 devices.  When used on devices
 		with SPI support you can reprogram the EEPROM from U-Boot.
 		CONFIG_E1000_FALLBACK_MAC
 		default MAC for empty EEPROM after production.
 		CONFIG_EEPRO100
 		Support for Intel 82557/82559/82559ER chips.
 		Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
 		write routine for first time initialisation.
 		CONFIG_TULIP
 		Support for Digital 2114x chips.
 		Optional CONFIG_TULIP_SELECT_MEDIA for board specific
 		modem chip initialisation (KS8761/QS6611).
 		CONFIG_NATSEMI
 		Support for National dp83815 chips.
 		CONFIG_NS8382X
 		Support for National dp8382[01] gigabit chips.
 - NETWORK Support (other):
 		CONFIG_DRIVER_AT91EMAC
 		Support for AT91RM9200 EMAC.
 			CONFIG_RMII
 			Define this to use reduced MII inteface
 			CONFIG_DRIVER_AT91EMAC_QUIET
 			If this defined, the driver is quiet.
 			The driver doen't show link status messages.
 		CONFIG_CALXEDA_XGMAC
 		Support for the Calxeda XGMAC device
 		CONFIG_LAN91C96
 		Support for SMSC's LAN91C96 chips.
 			CONFIG_LAN91C96_BASE
 			Define this to hold the physical address
 			of the LAN91C96's I/O space
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 		CONFIG_SMC91111
 		Support for SMSC's LAN91C111 chip
 			CONFIG_SMC91111_BASE
 			Define this to hold the physical address
 			of the device (I/O space)
 			CONFIG_SMC_USE_32_BIT
 			Define this if data bus is 32 bits
 			CONFIG_SMC_USE_IOFUNCS
 			Define this to use i/o functions instead of macros
 			(some hardware wont work with macros)
 		CONFIG_DRIVER_TI_EMAC
 		Support for davinci emac
 			CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
 			Define this if you have more then 3 PHYs.
 		CONFIG_FTGMAC100
 		Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
 			CONFIG_FTGMAC100_EGIGA
 			Define this to use GE link update with gigabit PHY.
 			Define this if FTGMAC100 is connected to gigabit PHY.
 			If your system has 10/100 PHY only, it might not occur
 			wrong behavior. Because PHY usually return timeout or
 			useless data when polling gigabit status and gigabit
 			control registers. This behavior won't affect the
 			correctnessof 10/100 link speed update.
 		CONFIG_SMC911X
 		Support for SMSC's LAN911x and LAN921x chips
 			CONFIG_SMC911X_BASE
 			Define this to hold the physical address
 			of the device (I/O space)
 			CONFIG_SMC911X_32_BIT
 			Define this if data bus is 32 bits
 			CONFIG_SMC911X_16_BIT
 			Define this if data bus is 16 bits. If your processor
 			automatically converts one 32 bit word to two 16 bit
 			words you may also try CONFIG_SMC911X_32_BIT.
 		CONFIG_SH_ETHER
 		Support for Renesas on-chip Ethernet controller
 			CONFIG_SH_ETHER_USE_PORT
 			Define the number of ports to be used
 			CONFIG_SH_ETHER_PHY_ADDR
 			Define the ETH PHY's address
 			CONFIG_SH_ETHER_CACHE_WRITEBACK
 			If this option is set, the driver enables cache flush.
 - TPM Support:
 		CONFIG_TPM
 		Support TPM devices.
 		CONFIG_TPM_TIS_I2C
 		Support for i2c bus TPM devices. Only one device
 		per system is supported at this time.
 			CONFIG_TPM_TIS_I2C_BUS_NUMBER
 			Define the the i2c bus number for the TPM device
 			CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS
 			Define the TPM's address on the i2c bus
 			CONFIG_TPM_TIS_I2C_BURST_LIMITATION
 			Define the burst count bytes upper limit
 		CONFIG_TPM_ATMEL_TWI
 		Support for Atmel TWI TPM device. Requires I2C support.
 		CONFIG_TPM_TIS_LPC
 		Support for generic parallel port TPM devices. Only one device
 		per system is supported at this time.
 			CONFIG_TPM_TIS_BASE_ADDRESS
 			Base address where the generic TPM device is mapped
 			to. Contemporary x86 systems usually map it at
 			0xfed40000.
 		CONFIG_CMD_TPM
 		Add tpm monitor functions.
 		Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also
 		provides monitor access to authorized functions.
 		CONFIG_TPM
 		Define this to enable the TPM support library which provides
 		functional interfaces to some TPM commands.
 		Requires support for a TPM device.
 		CONFIG_TPM_AUTH_SESSIONS
 		Define this to enable authorized functions in the TPM library.
 		Requires CONFIG_TPM and CONFIG_SHA1.
 - USB Support:
 		At the moment only the UHCI host controller is
 		supported (PIP405, MIP405, MPC5200); define
 		CONFIG_USB_UHCI to enable it.
 		define CONFIG_USB_KEYBOARD to enable the USB Keyboard
 		and define CONFIG_USB_STORAGE to enable the USB
 		storage devices.
 		Note:
 		Supported are USB Keyboards and USB Floppy drives
 		(TEAC FD-05PUB).
 		MPC5200 USB requires additional defines:
 			CONFIG_USB_CLOCK
 				for 528 MHz Clock: 0x0001bbbb
 			CONFIG_PSC3_USB
 				for USB on PSC3
 			CONFIG_USB_CONFIG
 				for differential drivers: 0x00001000
 				for single ended drivers: 0x00005000
 				for differential drivers on PSC3: 0x00000100
 				for single ended drivers on PSC3: 0x00004100
 			CONFIG_SYS_USB_EVENT_POLL
 				May be defined to allow interrupt polling
 				instead of using asynchronous interrupts
 		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
 		txfilltuning field in the EHCI controller on reset.
 		CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
 		interval for usb hub power-on delay.(minimum 100msec)
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the
 		command "setenv stdin usbtty; setenv stdout usbtty" and
 		attach your USB cable. The Unix command "dmesg" should print
 		it has found a new device. The environment variable usbtty
 		can be set to gserial or cdc_acm to enable your device to
 		appear to a USB host as a Linux gserial device or a
 		Common Device Class Abstract Control Model serial device.
 		If you select usbtty = gserial you should be able to enumerate
 		a Linux host by
 		# modprobe usbserial vendor=0xVendorID product=0xProductID
 		else if using cdc_acm, simply setting the environment
 		variable usbtty to be cdc_acm should suffice. The following
 		might be defined in YourBoardName.h
 			CONFIG_USB_DEVICE
 			Define this to build a UDC device
 			CONFIG_USB_TTY
 			Define this to have a tty type of device available to
 			talk to the UDC device
 			CONFIG_USBD_HS
 			Define this to enable the high speed support for usb
 			device and usbtty. If this feature is enabled, a routine
 			int is_usbd_high_speed(void)
 			also needs to be defined by the driver to dynamically poll
 			whether the enumeration has succeded at high speed or full
 			speed.
 			CONFIG_SYS_CONSOLE_IS_IN_ENV
 			Define this if you want stdin, stdout &/or stderr to
 			be set to usbtty.
 			mpc8xx:
 				CONFIG_SYS_USB_EXTC_CLK 0xBLAH
 				Derive USB clock from external clock "blah"
 				- CONFIG_SYS_USB_EXTC_CLK 0x02
 				CONFIG_SYS_USB_BRG_CLK 0xBLAH
 				Derive USB clock from brgclk
 				- CONFIG_SYS_USB_BRG_CLK 0x04
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
 		CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME,
 		CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot
 		should pretend to be a Linux device to it's target host.
 			CONFIG_USBD_MANUFACTURER
 			Define this string as the name of your company for
 			- CONFIG_USBD_MANUFACTURER "my company"
 			CONFIG_USBD_PRODUCT_NAME
 			Define this string as the name of your product
 			- CONFIG_USBD_PRODUCT_NAME "acme usb device"
 			CONFIG_USBD_VENDORID
 			Define this as your assigned Vendor ID from the USB
 			Implementors Forum. This *must* be a genuine Vendor ID
 			to avoid polluting the USB namespace.
 			- CONFIG_USBD_VENDORID 0xFFFF
 			CONFIG_USBD_PRODUCTID
 			Define this as the unique Product ID
 			for your device
 			- CONFIG_USBD_PRODUCTID 0xFFFF
 		Some USB device drivers may need to check USB cable attachment.
 		In this case you can enable following config in BoardName.h:
 			CONFIG_USB_CABLE_CHECK
 			This enables function definition:
 			- usb_cable_connected() in include/usb.h
 			Implementation of this function is board-specific.
 - ULPI Layer Support:
 		The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
 		the generic ULPI layer. The generic layer accesses the ULPI PHY
 		via the platform viewport, so you need both the genric layer and
 		the viewport enabled. Currently only Chipidea/ARC based
 		viewport is supported.
 		To enable the ULPI layer support, define CONFIG_USB_ULPI and
 		CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
 		If your ULPI phy needs a different reference clock than the
 		standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
 		the appropriate value in Hz.
 - MMC Support:
 		The MMC controller on the Intel PXA is supported. To
 		enable this define CONFIG_MMC. The MMC can be
 		accessed from the boot prompt by mapping the device
 		to physical memory similar to flash. Command line is
 		enabled with CONFIG_CMD_MMC. The MMC driver also works with
 		the FAT fs. This is enabled with CONFIG_CMD_FAT.
 		CONFIG_SH_MMCIF
 		Support for Renesas on-chip MMCIF controller
 			CONFIG_SH_MMCIF_ADDR
 			Define the base address of MMCIF registers
 			CONFIG_SH_MMCIF_CLK
 			Define the clock frequency for MMCIF
 - USB Device Firmware Update (DFU) class support:
 		CONFIG_DFU_FUNCTION
 		This enables the USB portion of the DFU USB class
 		CONFIG_CMD_DFU
 		This enables the command "dfu" which is used to have
 		U-Boot create a DFU class device via USB.  This command
 		requires that the "dfu_alt_info" environment variable be
 		set and define the alt settings to expose to the host.
 		CONFIG_DFU_MMC
 		This enables support for exposing (e)MMC devices via DFU.
 		CONFIG_DFU_NAND
 		This enables support for exposing NAND devices via DFU.
 		CONFIG_DFU_RAM
 		This enables support for exposing RAM via DFU.
 		Note: DFU spec refer to non-volatile memory usage, but
 		allow usages beyond the scope of spec - here RAM usage,
 		one that would help mostly the developer.
 		CONFIG_SYS_DFU_DATA_BUF_SIZE
 		Dfu transfer uses a buffer before writing data to the
 		raw storage device. Make the size (in bytes) of this buffer
 		configurable. The size of this buffer is also configurable
 		through the "dfu_bufsiz" environment variable.
 		CONFIG_SYS_DFU_MAX_FILE_SIZE
 		When updating files rather than the raw storage device,
 		we use a static buffer to copy the file into and then write
 		the buffer once we've been given the whole file.  Define
 		this to the maximum filesize (in bytes) for the buffer.
 		Default is 4 MiB if undefined.
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
 		CONFIG_JFFS2_NAND_DEV
 		Define these for a default partition on a NAND device
 		CONFIG_SYS_JFFS2_FIRST_SECTOR,
 		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
 		Define these for a default partition on a NOR device
 		CONFIG_SYS_JFFS_CUSTOM_PART
 		Define this to create an own partition. You have to provide a
 		function struct part_info* jffs2_part_info(int part_num)
 		If you define only one JFFS2 partition you may also want to
 		#define CONFIG_SYS_JFFS_SINGLE_PART	1
 		to disable the command chpart. This is the default when you
 		have not defined a custom partition
 - FAT(File Allocation Table) filesystem write function support:
 		CONFIG_FAT_WRITE
 		Define this to enable support for saving memory data as a
 		file in FAT formatted partition.
 		This will also enable the command "fatwrite" enabling the
 		user to write files to FAT.
 CBFS (Coreboot Filesystem) support
 		CONFIG_CMD_CBFS
 		Define this to enable support for reading from a Coreboot
 		filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
 		and cbfsload.
 - Keyboard Support:
 		CONFIG_ISA_KEYBOARD
 		Define this to enable standard (PC-Style) keyboard
 		support
 		CONFIG_I8042_KBD
 		Standard PC keyboard driver with US (is default) and
 		GERMAN key layout (switch via environment 'keymap=de') support.
 		Export function i8042_kbd_init, i8042_tstc and i8042_getc
 		for cfb_console. Supports cursor blinking.
 		CONFIG_CROS_EC_KEYB
 		Enables a Chrome OS keyboard using the CROS_EC interface.
 		This uses CROS_EC to communicate with a second microcontroller
 		which provides key scans on request.
 - Video support:
 		CONFIG_VIDEO
 		Define this to enable video support (for output to
 		video).
 		CONFIG_VIDEO_CT69000
 		Enable Chips & Technologies 69000 Video chip
 		CONFIG_VIDEO_SMI_LYNXEM
 		Enable Silicon Motion SMI 712/710/810 Video chip. The
 		video output is selected via environment 'videoout'
 		(1 = LCD and 2 = CRT). If videoout is undefined, CRT is
 		assumed.
 		For the CT69000 and SMI_LYNXEM drivers, videomode is
 		selected via environment 'videomode'. Two different ways
 		are possible:
 		- "videomode=num"   'num' is a standard LiLo mode numbers.
 		Following standard modes are supported	(* is default):
 		      Colors	640x480 800x600 1024x768 1152x864 1280x1024
 		-------------+---------------------------------------------
 		      8 bits |	0x301*	0x303	 0x305	  0x161	    0x307
 		     15 bits |	0x310	0x313	 0x316	  0x162	    0x319
 		     16 bits |	0x311	0x314	 0x317	  0x163	    0x31A
 		     24 bits |	0x312	0x315	 0x318	    ?	    0x31B
 		-------------+---------------------------------------------
 		(i.e. setenv videomode 317; saveenv; reset;)
 		- "videomode=bootargs" all the video parameters are parsed
 		from the bootargs. (See drivers/video/videomodes.c)
 		CONFIG_VIDEO_SED13806
 		Enable Epson SED13806 driver. This driver supports 8bpp
 		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
 		or CONFIG_VIDEO_SED13806_16BPP
 		CONFIG_FSL_DIU_FB
 		Enable the Freescale DIU video driver.	Reference boards for
 		SOCs that have a DIU should define this macro to enable DIU
 		support, and should also define these other macros:
 			CONFIG_SYS_DIU_ADDR
 			CONFIG_VIDEO
 			CONFIG_CMD_BMP
 			CONFIG_CFB_CONSOLE
 			CONFIG_VIDEO_SW_CURSOR
 			CONFIG_VGA_AS_SINGLE_DEVICE
 			CONFIG_VIDEO_LOGO
 			CONFIG_VIDEO_BMP_LOGO
 		The DIU driver will look for the 'video-mode' environment
 		variable, and if defined, enable the DIU as a console during
 		boot.  See the documentation file README.video for a
 		description of this variable.
 		CONFIG_VIDEO_VGA
 		Enable the VGA video / BIOS for x86. The alternative if you
 		are using coreboot is to use the coreboot frame buffer
 		driver.
 - Keyboard Support:
 		CONFIG_KEYBOARD
 		Define this to enable a custom keyboard support.
 		This simply calls drv_keyboard_init() which must be
 		defined in your board-specific files.
 		The only board using this so far is RBC823.
 - LCD Support:	CONFIG_LCD
 		Define this to enable LCD support (for output to LCD
 		display); also select one of the supported displays
 		by defining one of these:
 		CONFIG_ATMEL_LCD:
 			HITACHI TX09D70VM1CCA, 3.5", 240x320.
 		CONFIG_NEC_NL6448AC33:
 			NEC NL6448AC33-18. Active, color, single scan.
 		CONFIG_NEC_NL6448BC20
 			NEC NL6448BC20-08. 6.5", 640x480.
 			Active, color, single scan.
 		CONFIG_NEC_NL6448BC33_54
 			NEC NL6448BC33-54. 10.4", 640x480.
 			Active, color, single scan.
 		CONFIG_SHARP_16x9
 			Sharp 320x240. Active, color, single scan.
 			It isn't 16x9, and I am not sure what it is.
 		CONFIG_SHARP_LQ64D341
 			Sharp LQ64D341 display, 640x480.
 			Active, color, single scan.
 		CONFIG_HLD1045
 			HLD1045 display, 640x480.
 			Active, color, single scan.
 		CONFIG_OPTREX_BW
 			Optrex	 CBL50840-2 NF-FW 99 22 M5
 			or
 			Hitachi	 LMG6912RPFC-00T
 			or
 			Hitachi	 SP14Q002
 			320x240. Black & white.
 		Normally display is black on white background; define
 		CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
 		CONFIG_LCD_ALIGNMENT
 		Normally the LCD is page-aligned (tyically 4KB). If this is
 		defined then the LCD will be aligned to this value instead.
 		For ARM it is sometimes useful to use MMU_SECTION_SIZE
 		here, since it is cheaper to change data cache settings on
 		a per-section basis.
 		CONFIG_CONSOLE_SCROLL_LINES
 		When the console need to be scrolled, this is the number of
 		lines to scroll by. It defaults to 1. Increasing this makes
 		the console jump but can help speed up operation when scrolling
 		is slow.
 		CONFIG_LCD_BMP_RLE8
 		Support drawing of RLE8-compressed bitmaps on the LCD.
 		CONFIG_I2C_EDID
 		Enables an 'i2c edid' command which can read EDID
 		information over I2C from an attached LCD display.
 - Splash Screen Support: CONFIG_SPLASH_SCREEN
 		If this option is set, the environment is checked for
 		a variable "splashimage". If found, the usual display
 		of logo, copyright and system information on the LCD
 		is suppressed and the BMP image at the address
 		specified in "splashimage" is loaded instead. The
 		console is redirected to the "nulldev", too. This
 		allows for a "silent" boot where a splash screen is
 		loaded very quickly after power-on.
 		CONFIG_SPLASHIMAGE_GUARD
 		If this option is set, then U-Boot will prevent the environment
 		variable "splashimage" from being set to a problematic address
 		(see README.displaying-bmps and README.arm-unaligned-accesses).
 		This option is useful for targets where, due to alignment
 		restrictions, an improperly aligned BMP image will cause a data
 		abort. If you think you will not have problems with unaligned
 		accesses (for example because your toolchain prevents them)
 		there is no need to set this option.
 		CONFIG_SPLASH_SCREEN_ALIGN
 		If this option is set the splash image can be freely positioned
 		on the screen. Environment variable "splashpos" specifies the
 		position as "x,y". If a positive number is given it is used as
 		number of pixel from left/top. If a negative number is given it
 		is used as number of pixel from right/bottom. You can also
 		specify 'm' for centering the image.
 		Example:
 		setenv splashpos m,m
 			=> image at center of screen
 		setenv splashpos 30,20
 			=> image at x = 30 and y = 20
 		setenv splashpos -10,m
 			=> vertically centered image
 			   at x = dspWidth - bmpWidth - 9
 - Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
 		If this option is set, additionally to standard BMP
 		images, gzipped BMP images can be displayed via the
 		splashscreen support or the bmp command.
 - Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
 		If this option is set, 8-bit RLE compressed BMP images
 		can be displayed via the splashscreen support or the
 		bmp command.
 - Do compresssing for memory range:
 		CONFIG_CMD_ZIP
 		If this option is set, it would use zlib deflate method
 		to compress the specified memory at its best effort.
 - Compression support:
 		CONFIG_GZIP
 		Enabled by default to support gzip compressed images.
 		CONFIG_BZIP2
 		If this option is set, support for bzip2 compressed
 		images is included. If not, only uncompressed and gzip
 		compressed images are supported.
 		NOTE: the bzip2 algorithm requires a lot of RAM, so
 		the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
 		be at least 4MB.
 		CONFIG_LZMA
 		If this option is set, support for lzma compressed
 		images is included.
 		Note: The LZMA algorithm adds between 2 and 4KB of code and it
 		requires an amount of dynamic memory that is given by the
 		formula:
 			(1846 + 768 << (lc + lp)) * sizeof(uint16)
 		Where lc and lp stand for, respectively, Literal context bits
 		and Literal pos bits.
 		This value is upper-bounded by 14MB in the worst case. Anyway,
 		for a ~4MB large kernel image, we have lc=3 and lp=0 for a
 		total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is
 		a very small buffer.
 		Use the lzmainfo tool to determinate the lc and lp values and
 		then calculate the amount of needed dynamic memory (ensuring
 		the appropriate CONFIG_SYS_MALLOC_LEN value).
 		CONFIG_LZO
 		If this option is set, support for LZO compressed images
 		is included.
 - MII/PHY support:
 		CONFIG_PHY_ADDR
 		The address of PHY on MII bus.
 		CONFIG_PHY_CLOCK_FREQ (ppc4xx)
 		The clock frequency of the MII bus
 		CONFIG_PHY_GIGE
 		If this option is set, support for speed/duplex
 		detection of gigabit PHY is included.
 		CONFIG_PHY_RESET_DELAY
 		Some PHY like Intel LXT971A need extra delay after
 		reset before any MII register access is possible.
 		For such PHY, set this option to the usec delay
 		required. (minimum 300usec for LXT971A)
 		CONFIG_PHY_CMD_DELAY (ppc4xx)
 		Some PHY like Intel LXT971A need extra delay after
 		command issued before MII status register can be read
 - Ethernet address:
 		CONFIG_ETHADDR
 		CONFIG_ETH1ADDR
 		CONFIG_ETH2ADDR
 		CONFIG_ETH3ADDR
 		CONFIG_ETH4ADDR
 		CONFIG_ETH5ADDR
 		Define a default value for Ethernet address to use
 		for the respective Ethernet interface, in case this
 		is not determined automatically.
 - IP address:
 		CONFIG_IPADDR
 		Define a default value for the IP address to use for
 		the default Ethernet interface, in case this is not
 		determined through e.g. bootp.
 		(Environment variable "ipaddr")
 - Server IP address:
 		CONFIG_SERVERIP
 		Defines a default value for the IP address of a TFTP
 		server to contact when using the "tftboot" command.
 		(Environment variable "serverip")
 		CONFIG_KEEP_SERVERADDR
 		Keeps the server's MAC address, in the env 'serveraddr'
 		for passing to bootargs (like Linux's netconsole option)
 - Gateway IP address:
 		CONFIG_GATEWAYIP
 		Defines a default value for the IP address of the
 		default router where packets to other networks are
 		sent to.
 		(Environment variable "gatewayip")
 - Subnet mask:
 		CONFIG_NETMASK
 		Defines a default value for the subnet mask (or
 		routing prefix) which is used to determine if an IP
 		address belongs to the local subnet or needs to be
 		forwarded through a router.
 		(Environment variable "netmask")
 - Multicast TFTP Mode:
 		CONFIG_MCAST_TFTP
 		Defines whether you want to support multicast TFTP as per
 		rfc-2090; for example to work with atftp.  Lets lots of targets
 		tftp down the same boot image concurrently.  Note: the Ethernet
 		driver in use must provide a function: mcast() to join/leave a
 		multicast group.
 - BOOTP Recovery Mode:
 		CONFIG_BOOTP_RANDOM_DELAY
 		If you have many targets in a network that try to
 		boot using BOOTP, you may want to avoid that all
 		systems send out BOOTP requests at precisely the same
 		moment (which would happen for instance at recovery
 		from a power failure, when all systems will try to
 		boot, thus flooding the BOOTP server. Defining
 		CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
 		inserted before sending out BOOTP requests. The
 		following delays are inserted then:
 		1st BOOTP request:	delay 0 ... 1 sec
 		2nd BOOTP request:	delay 0 ... 2 sec
 		3rd BOOTP request:	delay 0 ... 4 sec
 		4th and following
 		BOOTP requests:		delay 0 ... 8 sec
 - DHCP Advanced Options:
 		You can fine tune the DHCP functionality by defining
 		CONFIG_BOOTP_* symbols:
 		CONFIG_BOOTP_SUBNETMASK
 		CONFIG_BOOTP_GATEWAY
 		CONFIG_BOOTP_HOSTNAME
 		CONFIG_BOOTP_NISDOMAIN
 		CONFIG_BOOTP_BOOTPATH
 		CONFIG_BOOTP_BOOTFILESIZE
 		CONFIG_BOOTP_DNS
 		CONFIG_BOOTP_DNS2
 		CONFIG_BOOTP_SEND_HOSTNAME
 		CONFIG_BOOTP_NTPSERVER
 		CONFIG_BOOTP_TIMEOFFSET
 		CONFIG_BOOTP_VENDOREX
 		CONFIG_BOOTP_MAY_FAIL
 		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
 		environment variable, not the BOOTP server.
 		CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
 		after the configured retry count, the call will fail
 		instead of starting over.  This can be used to fail over
 		to Link-local IP address configuration if the DHCP server
 		is not available.
 		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
 		serverip from a DHCP server, it is possible that more
 		than one DNS serverip is offered to the client.
 		If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
 		serverip will be stored in the additional environment
 		variable "dnsip2". The first DNS serverip is always
 		stored in the variable "dnsip", when CONFIG_BOOTP_DNS
 		is defined.
 		CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
 		to do a dynamic update of a DNS server. To do this, they
 		need the hostname of the DHCP requester.
 		If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
 		of the "hostname" environment variable is passed as
 		option 12 to the DHCP server.
 		CONFIG_BOOTP_DHCP_REQUEST_DELAY
 		A 32bit value in microseconds for a delay between
 		receiving a "DHCP Offer" and sending the "DHCP Request".
 		This fixes a problem with certain DHCP servers that don't
 		respond 100% of the time to a "DHCP request". E.g. On an
 		AT91RM9200 processor running at 180MHz, this delay needed
 		to be *at least* 15,000 usec before a Windows Server 2003
 		DHCP server would reply 100% of the time. I recommend at
 		least 50,000 usec to be safe. The alternative is to hope
 		that one of the retries will be successful but note that
 		the DHCP timeout and retry process takes a longer than
 		this delay.
  - Link-local IP address negotiation:
 		Negotiate with other link-local clients on the local network
 		for an address that doesn't require explicit configuration.
 		This is especially useful if a DHCP server cannot be guaranteed
 		to exist in all environments that the device must operate.
 		See doc/README.link-local for more information.
  - CDP Options:
 		CONFIG_CDP_DEVICE_ID
 		The device id used in CDP trigger frames.
 		CONFIG_CDP_DEVICE_ID_PREFIX
 		A two character string which is prefixed to the MAC address
 		of the device.
 		CONFIG_CDP_PORT_ID
 		A printf format string which contains the ascii name of
 		the port. Normally is set to "eth%d" which sets
 		eth0 for the first Ethernet, eth1 for the second etc.
 		CONFIG_CDP_CAPABILITIES
 		A 32bit integer which indicates the device capabilities;
 		0x00000010 for a normal host which does not forwards.
 		CONFIG_CDP_VERSION
 		An ascii string containing the version of the software.
 		CONFIG_CDP_PLATFORM
 		An ascii string containing the name of the platform.
 		CONFIG_CDP_TRIGGER
 		A 32bit integer sent on the trigger.
 		CONFIG_CDP_POWER_CONSUMPTION
 		A 16bit integer containing the power consumption of the
 		device in .1 of milliwatts.
 		CONFIG_CDP_APPLIANCE_VLAN_TYPE
 		A byte containing the id of the VLAN.
 - Status LED:	CONFIG_STATUS_LED
 		Several configurations allow to display the current
 		status using a LED. For instance, the LED will blink
 		fast while running U-Boot code, stop blinking as
 		soon as a reply to a BOOTP request was received, and
 		start blinking slow once the Linux kernel is running
 		(supported by a status LED driver in the Linux
 		kernel). Defining CONFIG_STATUS_LED enables this
 		feature in U-Boot.
 		Additional options:
 		CONFIG_GPIO_LED
 		The status LED can be connected to a GPIO pin.
 		In such cases, the gpio_led driver can be used as a
 		status LED backend implementation. Define CONFIG_GPIO_LED
 		to include the gpio_led driver in the U-Boot binary.
 		CONFIG_GPIO_LED_INVERTED_TABLE
 		Some GPIO connected LEDs may have inverted polarity in which
 		case the GPIO high value corresponds to LED off state and
 		GPIO low value corresponds to LED on state.
 		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
 		with a list of GPIO LEDs that have inverted polarity.
 - CAN Support:	CONFIG_CAN_DRIVER
 		Defining CONFIG_CAN_DRIVER enables CAN driver support
 		on those systems that support this (optional)
 		feature, like the TQM8xxL modules.
 - I2C Support:	CONFIG_SYS_I2C
 		This enable the NEW i2c subsystem, and will allow you to use
 		i2c commands at the u-boot command line (as long as you set
 		CONFIG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c
 		based realtime clock chips or other i2c devices. See
 		common/cmd_i2c.c for a description of the command line
 		interface.
 		ported i2c driver to the new framework:
 		- drivers/i2c/soft_i2c.c:
 		  - activate first bus with CONFIG_SYS_I2C_SOFT define
 		    CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
 		    for defining speed and slave address
 		  - activate second bus with I2C_SOFT_DECLARATIONS2 define
 		    CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
 		    for defining speed and slave address
 		  - activate third bus with I2C_SOFT_DECLARATIONS3 define
 		    CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
 		    for defining speed and slave address
 		  - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
 		    CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
 		    for defining speed and slave address
 		- drivers/i2c/fsl_i2c.c:
 		  - activate i2c driver with CONFIG_SYS_I2C_FSL
 		    define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
 		    offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
 		    CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
 		    bus.
 		  - If your board supports a second fsl i2c bus, define
 		    CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
 		    CONFIG_SYS_FSL_I2C2_SPEED for the speed and
 		    CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
 		    second bus.
 		- drivers/i2c/tegra_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_TEGRA
 		  - This driver adds 4 i2c buses with a fix speed from
 		    100000 and the slave addr 0!
 		- drivers/i2c/ppc4xx_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_PPC4XX
 		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
 		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
 		- drivers/i2c/i2c_mxc.c
 		  - activate this driver with CONFIG_SYS_I2C_MXC
 		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
 		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
 		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
 		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
 		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
 		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
 		If thoses defines are not set, default value is 100000
 		for speed, and 0 for slave.
 		- drivers/i2c/rcar_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_RCAR
 		  - This driver adds 4 i2c buses
 		  - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
 		  - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
 		  - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
 		  - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
 		  - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
 		  - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
 		  - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
 		  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
 		  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
 		- drivers/i2c/sh_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_SH
 		  - This driver adds from 2 to 5 i2c buses
 		  - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
 		  - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
 		  - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
 		  - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
 		  - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
 		  - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
 		  - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
 		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
 		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
 		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
 		  - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
 		  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
 		  - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
 		- drivers/i2c/omap24xx_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_OMAP24XX
 		  - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
 		  - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
 		  - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
 		  - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
 		  - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
 		- drivers/i2c/zynq_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_ZYNQ
 		  - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
 		  - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
 		- drivers/i2c/s3c24x0_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_S3C24X0
 		  - This driver adds i2c buses (11 for Exynos5250, Exynos5420
 		    9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
 		    with a fix speed from 100000 and the slave addr 0!
 		additional defines:
 		CONFIG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c busses you want to use. If you
 		don't use/have i2c muxes on your i2c bus, this
 		is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
 		omit this define.
 		CONFIG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
 		if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
 		omit this define.
 		CONFIG_SYS_I2C_MAX_HOPS
 		define how many muxes are maximal consecutively connected
 		on one i2c bus. If you not use i2c muxes, omit this
 		define.
 		CONFIG_SYS_I2C_BUSES
 		hold a list of busses you want to use, only used if
 		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
 		a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
 		CONFIG_SYS_NUM_I2C_BUSES = 9:
 		 CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 4}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 5}}}, \
 					{1, {I2C_NULL_HOP}}, \
 					{1, {{I2C_MUX_PCA9544, 0x72, 1}}}, \
 					{1, {{I2C_MUX_PCA9544, 0x72, 2}}}, \
 					}
 		which defines
 			bus 0 on adapter 0 without a mux
 			bus 1 on adapter 0 with a PCA9547 on address 0x70 port 1
 			bus 2 on adapter 0 with a PCA9547 on address 0x70 port 2
 			bus 3 on adapter 0 with a PCA9547 on address 0x70 port 3
 			bus 4 on adapter 0 with a PCA9547 on address 0x70 port 4
 			bus 5 on adapter 0 with a PCA9547 on address 0x70 port 5
 			bus 6 on adapter 1 without a mux
 			bus 7 on adapter 1 with a PCA9544 on address 0x72 port 1
 			bus 8 on adapter 1 with a PCA9544 on address 0x72 port 2
 		If you do not have i2c muxes on your board, omit this define.
 - Legacy I2C Support:	CONFIG_HARD_I2C
 		NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
 		provides the following compelling advantages:
 		- more than one i2c adapter is usable
 		- approved multibus support
 		- better i2c mux support
 		** Please consider updating your I2C driver now. **
 		These enable legacy I2C serial bus commands. Defining
 		CONFIG_HARD_I2C will include the appropriate I2C driver
 		for the selected CPU.
 		This will allow you to use i2c commands at the u-boot
 		command line (as long as you set CONFIG_CMD_I2C in
 		CONFIG_COMMANDS) and communicate with i2c based realtime
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 		CONFIG_HARD_I2C selects a hardware I2C controller.
 		There are several other quantities that must also be
 		defined when you define CONFIG_HARD_I2C.
 		In both cases you will need to define CONFIG_SYS_I2C_SPEED
 		to be the frequency (in Hz) at which you wish your i2c bus
 		to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
 		the CPU's i2c node address).
 		Now, the u-boot i2c code for the mpc8xx
 		(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
 		and so its address should therefore be cleared to 0 (See,
 		eg, MPC823e User's Manual p.16-473). So, set
 		CONFIG_SYS_I2C_SLAVE to 0.
 		CONFIG_SYS_I2C_INIT_MPC5XXX
 		When a board is reset during an i2c bus transfer
 		chips might think that the current transfer is still
 		in progress.  Reset the slave devices by sending start
 		commands until the slave device responds.
 		That's all that's required for CONFIG_HARD_I2C.
 		If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
 		then the following macros need to be defined (examples are
 		from include/configs/lwmon.h):
 		I2C_INIT
 		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.
 		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
 		I2C_PORT
 		(Only for MPC8260 CPU). The I/O port to use (the code
 		assumes both bits are on the same port). Valid values
 		are 0..3 for ports A..D.
 		I2C_ACTIVE
 		The code necessary to make the I2C data line active
 		(driven).  If the data line is open collector, this
 		define can be null.
 		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)
 		I2C_TRISTATE
 		The code necessary to make the I2C data line tri-stated
 		(inactive).  If the data line is open collector, this
 		define can be null.
 		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 		I2C_READ
 		Code that returns true if the I2C data line is high,
 		false if it is low.
 		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 		I2C_SDA(bit)
 		If <bit> is true, sets the I2C data line high. If it
 		is false, it clears it (low).
 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
 		I2C_SCL(bit)
 		If <bit> is true, sets the I2C clock line high. If it
 		is false, it clears it (low).
 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 		I2C_DELAY
 		This delay is invoked four times per clock cycle so this
 		controls the rate of data transfer.  The data rate thus
 		is 1 / (I2C_DELAY * 4). Often defined to be something
 		like:
 		#define I2C_DELAY  udelay(2)
 		CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
 		If your arch supports the generic GPIO framework (asm/gpio.h),
 		then you may alternatively define the two GPIOs that are to be
 		used as SCL / SDA.  Any of the previous I2C_xxx macros will
 		have GPIO-based defaults assigned to them as appropriate.
 		You should define these to the GPIO value as given directly to
 		the generic GPIO functions.
 		CONFIG_SYS_I2C_INIT_BOARD
 		When a board is reset during an i2c bus transfer
 		chips might think that the current transfer is still
 		in progress. On some boards it is possible to access
 		the i2c SCLK line directly, either by using the
 		processor pin as a GPIO or by having a second pin
 		connected to the bus. If this option is defined a
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.
 		CONFIG_SYS_I2C_BOARD_LATE_INIT
 		An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
 		defined a custom i2c_board_late_init() routine in
 		boards/xxx/board.c is run AFTER the operations in i2c_init()
 		is completed. This callpoint can be used to unreset i2c bus
 		using CPU i2c controller register accesses for CPUs whose i2c
 		controller provide such a method. It is called at the end of
 		i2c_init() to allow i2c_init operations to setup the i2c bus
 		controller on the CPU (e.g. setting bus speed & slave address).
 		CONFIG_I2CFAST (PPC405GP|PPC405EP only)
 		This option enables configuration of bi_iic_fast[] flags
 		in u-boot bd_info structure based on u-boot environment
 		variable "i2cfast". (see also i2cfast)
 		CONFIG_I2C_MULTI_BUS
 		This option allows the use of multiple I2C buses, each of which
 		must have a controller.	 At any point in time, only one bus is
 		active.	 To switch to a different bus, use the 'i2c dev' command.
 		Note that bus numbering is zero-based.
 		CONFIG_SYS_I2C_NOPROBES
 		This option specifies a list of I2C devices that will be skipped
 		when the 'i2c probe' command is issued.	 If CONFIG_I2C_MULTI_BUS
 		is set, specify a list of bus-device pairs.  Otherwise, specify
 		a 1D array of device addresses
 		e.g.
 			#undef	CONFIG_I2C_MULTI_BUS
 			#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 			#define CONFIG_I2C_MULTI_BUS
 			#define CONFIG_SYS_I2C_MULTI_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 		CONFIG_SYS_SPD_BUS_NUM
 		If defined, then this indicates the I2C bus number for DDR SPD.
 		If not defined, then U-Boot assumes that SPD is on I2C bus 0.
 		CONFIG_SYS_RTC_BUS_NUM
 		If defined, then this indicates the I2C bus number for the RTC.
 		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
 		CONFIG_SYS_DTT_BUS_NUM
 		If defined, then this indicates the I2C bus number for the DTT.
 		If not defined, then U-Boot assumes that DTT is on I2C bus 0.
 		CONFIG_SYS_I2C_DTT_ADDR:
 		If defined, specifies the I2C address of the DTT device.
 		If not defined, then U-Boot uses predefined value for
 		specified DTT device.
 		CONFIG_SOFT_I2C_READ_REPEATED_START
 		defining this will force the i2c_read() function in
 		the soft_i2c driver to perform an I2C repeated start
 		between writing the address pointer and reading the
 		data.  If this define is omitted the default behaviour
 		of doing a stop-start sequence will be used.  Most I2C
 		devices can use either method, but some require one or
 		the other.
 - SPI Support:	CONFIG_SPI
 		Enables SPI driver (so far only tested with
 		SPI EEPROM, also an instance works with Crystal A/D and
 		D/As on the SACSng board)
 		CONFIG_SH_SPI
 		Enables the driver for SPI controller on SuperH. Currently
 		only SH7757 is supported.
 		CONFIG_SPI_X
 		Enables extended (16-bit) SPI EEPROM addressing.
 		(symmetrical to CONFIG_I2C_X)
 		CONFIG_SOFT_SPI
 		Enables a software (bit-bang) SPI driver rather than
 		using hardware support. This is a general purpose
 		driver that only requires three general I/O port pins
 		(two outputs, one input) to function. If this is
 		defined, the board configuration must define several
 		SPI configuration items (port pins to use, etc). For
 		an example, see include/configs/sacsng.h.
 		CONFIG_HARD_SPI
 		Enables a hardware SPI driver for general-purpose reads
 		and writes.  As with CONFIG_SOFT_SPI, the board configuration
 		must define a list of chip-select function pointers.
 		Currently supported on some MPC8xxx processors.	 For an
 		example, see include/configs/mpc8349emds.h.
 		CONFIG_MXC_SPI
 		Enables the driver for the SPI controllers on i.MX and MXC
 		SoCs. Currently i.MX31/35/51 are supported.
 - FPGA Support: CONFIG_FPGA
 		Enables FPGA subsystem.
 		CONFIG_FPGA_<vendor>
 		Enables support for specific chip vendors.
 		(ALTERA, XILINX)
 		CONFIG_FPGA_<family>
 		Enables support for FPGA family.
 		(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
 		CONFIG_FPGA_COUNT
 		Specify the number of FPGA devices to support.
 		CONFIG_SYS_FPGA_PROG_FEEDBACK
 		Enable printing of hash marks during FPGA configuration.
 		CONFIG_SYS_FPGA_CHECK_BUSY
 		Enable checks on FPGA configuration interface busy
 		status by the configuration function. This option
 		will require a board or device specific function to
 		be written.
 		CONFIG_FPGA_DELAY
 		If defined, a function that provides delays in the FPGA
 		configuration driver.
 		CONFIG_SYS_FPGA_CHECK_CTRLC
 		Allow Control-C to interrupt FPGA configuration
 		CONFIG_SYS_FPGA_CHECK_ERROR
 		Check for configuration errors during FPGA bitfile
 		loading. For example, abort during Virtex II
 		configuration if the INIT_B line goes low (which
 		indicated a CRC error).
 		CONFIG_SYS_FPGA_WAIT_INIT
 		Maximum time to wait for the INIT_B line to deassert
 		after PROB_B has been deasserted during a Virtex II
 		FPGA configuration sequence. The default time is 500
 		ms.
 		CONFIG_SYS_FPGA_WAIT_BUSY
 		Maximum time to wait for BUSY to deassert during
 		Virtex II FPGA configuration. The default is 5 ms.
 		CONFIG_SYS_FPGA_WAIT_CONFIG
 		Time to wait after FPGA configuration. The default is
 		200 ms.
 - Configuration Management:
 		CONFIG_IDENT_STRING
 		If defined, this string will be added to the U-Boot
 		version information (U_BOOT_VERSION)
 - Vendor Parameter Protection:
 		U-Boot considers the values of the environment
 		variables "serial#" (Board Serial Number) and
 		"ethaddr" (Ethernet Address) to be parameters that
 		are set once by the board vendor / manufacturer, and
 		protects these variables from casual modification by
 		the user. Once set, these variables are read-only,
 		and write or delete attempts are rejected. You can
 		change this behaviour:
 		If CONFIG_ENV_OVERWRITE is #defined in your config
 		file, the write protection for vendor parameters is
 		completely disabled. Anybody can change or delete
 		these parameters.
 		Alternatively, if you #define _both_ CONFIG_ETHADDR
 		_and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
 		Ethernet address is installed in the environment,
 		which can be changed exactly ONCE by the user. [The
 		serial# is unaffected by this, i. e. it remains
 		read-only.]
 		The same can be accomplished in a more flexible way
 		for any variable by configuring the type of access
 		to allow for those variables in the ".flags" variable
 		or define CONFIG_ENV_FLAGS_LIST_STATIC.
 - Protected RAM:
 		CONFIG_PRAM
 		Define this variable to enable the reservation of
 		"protected RAM", i. e. RAM which is not overwritten
 		by U-Boot. Define CONFIG_PRAM to hold the number of
 		kB you want to reserve for pRAM. You can overwrite
 		this default value by defining an environment
 		variable "pram" to the number of kB you want to
 		reserve. Note that the board info structure will
 		still show the full amount of RAM. If pRAM is
 		reserved, a new environment variable "mem" will
 		automatically be defined to hold the amount of
 		remaining RAM in a form that can be passed as boot
 		argument to Linux, for instance like that:
 			setenv bootargs ... mem=\${mem}
 			saveenv
 		This way you can tell Linux not to use this memory,
 		either, which results in a memory region that will
 		not be affected by reboots.
 		*WARNING* If your board configuration uses automatic
 		detection of the RAM size, you must make sure that
 		this memory test is non-destructive. So far, the
 		following board configurations are known to be
 		"pRAM-clean":
 			IVMS8, IVML24, SPD8xx, TQM8xxL,
 			HERMES, IP860, RPXlite, LWMON,
 			FLAGADM, TQM8260
 - Access to physical memory region (> 4GB)
 		Some basic support is provided for operations on memory not
 		normally accessible to U-Boot - e.g. some architectures
 		support access to more than 4GB of memory on 32-bit
 		machines using physical address extension or similar.
 		Define CONFIG_PHYSMEM to access this basic support, which
 		currently only supports clearing the memory.
 - Error Recovery:
 		CONFIG_PANIC_HANG
 		Define this variable to stop the system in case of a
 		fatal error, so that you have to reset it manually.
 		This is probably NOT a good idea for an embedded
 		system where you want the system to reboot
 		automatically as fast as possible, but it may be
 		useful during development since you can try to debug
 		the conditions that lead to the situation.
 		CONFIG_NET_RETRY_COUNT
 		This variable defines the number of retries for
 		network operations like ARP, RARP, TFTP, or BOOTP
 		before giving up the operation. If not defined, a
 		default value of 5 is used.
 		CONFIG_ARP_TIMEOUT
 		Timeout waiting for an ARP reply in milliseconds.
 		CONFIG_NFS_TIMEOUT
 		Timeout in milliseconds used in NFS protocol.
 		If you encounter "ERROR: Cannot umount" in nfs command,
 		try longer timeout such as
 		#define CONFIG_NFS_TIMEOUT 10000UL
 - Command Interpreter:
 		CONFIG_AUTO_COMPLETE
 		Enable auto completion of commands using TAB.
 		Note that this feature has NOT been implemented yet
 		for the "hush" shell.
 		CONFIG_SYS_HUSH_PARSER
 		Define this variable to enable the "hush" shell (from
 		Busybox) as command line interpreter, thus enabling
 		powerful command line syntax like
 		if...then...else...fi conditionals or `&&' and '||'
 		constructs ("shell scripts").
 		If undefined, you get the old, much simpler behaviour
 		with a somewhat smaller memory footprint.
 		CONFIG_SYS_PROMPT_HUSH_PS2
 		This defines the secondary prompt string, which is
 		printed when the command interpreter needs more input
 		to complete a command. Usually "> ".
 	Note:
 		In the current implementation, the local variables
 		space and global environment variables space are
 		separated. Local variables are those you define by
 		simply typing `name=value'. To access a local
 		variable later on, you have write `$name' or
 		`${name}'; to execute the contents of a variable
 		directly type `$name' at the command prompt.
 		Global environment variables are those you use
 		setenv/printenv to work with. To run a command stored
 		in such a variable, you need to use the run command,
 		and you must not use the '$' sign to access them.
 		To store commands and special characters in a
 		variable, please use double quotation marks
 		surrounding the whole text of the variable, instead
 		of the backslashes before semicolons and special
 		symbols.
 - Commandline Editing and History:
 		CONFIG_CMDLINE_EDITING
 		Enable editing and History functions for interactive
 		commandline input operations
 - Default Environment:
 		CONFIG_EXTRA_ENV_SETTINGS
 		Define this to contain any number of null terminated
 		strings (variable = value pairs) that will be part of
 		the default environment compiled into the boot image.
 		For example, place something like this in your
 		board's config file:
 		#define CONFIG_EXTRA_ENV_SETTINGS \
 			"myvar1=value1\0" \
 			"myvar2=value2\0"
 		Warning: This method is based on knowledge about the
 		internal format how the environment is stored by the
 		U-Boot code. This is NOT an official, exported
 		interface! Although it is unlikely that this format
 		will change soon, there is no guarantee either.
 		You better know what you are doing here.
 		Note: overly (ab)use of the default environment is
 		discouraged. Make sure to check other ways to preset
 		the environment like the "source" command or the
 		boot command first.
 		CONFIG_ENV_VARS_UBOOT_CONFIG
 		Define this in order to add variables describing the
 		U-Boot build configuration to the default environment.
 		These will be named arch, cpu, board, vendor, and soc.
 		Enabling this option will cause the following to be defined:
 		- CONFIG_SYS_ARCH
 		- CONFIG_SYS_CPU
 		- CONFIG_SYS_BOARD
 		- CONFIG_SYS_VENDOR
 		- CONFIG_SYS_SOC
 		CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 		Define this in order to add variables describing certain
 		run-time determined information about the hardware to the
 		environment.  These will be named board_name, board_rev.
 		CONFIG_DELAY_ENVIRONMENT
 		Normally the environment is loaded when the board is
 		intialised so that it is available to U-Boot. This inhibits
 		that so that the environment is not available until
 		explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
 		this is instead controlled by the value of
 		/config/load-environment.
 - DataFlash Support:
 		CONFIG_HAS_DATAFLASH
 		Defining this option enables DataFlash features and
 		allows to read/write in Dataflash via the standard
 		commands cp, md...
 - Serial Flash support
 		CONFIG_CMD_SF
 		Defining this option enables SPI flash commands
 		'sf probe/read/write/erase/update'.
 		Usage requires an initial 'probe' to define the serial
 		flash parameters, followed by read/write/erase/update
 		commands.
 		The following defaults may be provided by the platform
 		to handle the common case when only a single serial
 		flash is present on the system.
 		CONFIG_SF_DEFAULT_BUS		Bus identifier
 		CONFIG_SF_DEFAULT_CS		Chip-select
 		CONFIG_SF_DEFAULT_MODE 		(see include/spi.h)
 		CONFIG_SF_DEFAULT_SPEED		in Hz
 		CONFIG_CMD_SF_TEST
 		Define this option to include a destructive SPI flash
 		test ('sf test').
 		CONFIG_SPI_FLASH_BAR		Ban/Extended Addr Reg
 		Define this option to use the Bank addr/Extended addr
 		support on SPI flashes which has size > 16Mbytes.
 		CONFIG_SF_DUAL_FLASH		Dual flash memories
 		Define this option to use dual flash support where two flash
 		memories can be connected with a given cs line.
 		currently Xilinx Zynq qspi support these type of connections.
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 		Adding this option adds support for Xilinx SystemACE
 		chips attached via some sort of local bus. The address
 		of the chip must also be defined in the
 		CONFIG_SYS_SYSTEMACE_BASE macro. For example:
 		#define CONFIG_SYSTEMACE
 		#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
 		When SystemACE support is added, the "ace" device type
 		becomes available to the fat commands, i.e. fatls.
 - TFTP Fixed UDP Port:
 		CONFIG_TFTP_PORT
 		If this is defined, the environment variable tftpsrcp
 		is used to supply the TFTP UDP source port value.
 		If tftpsrcp isn't defined, the normal pseudo-random port
 		number generator is used.
 		Also, the environment variable tftpdstp is used to supply
 		the TFTP UDP destination port value.  If tftpdstp isn't
 		defined, the normal port 69 is used.
 		The purpose for tftpsrcp is to allow a TFTP server to
 		blindly start the TFTP transfer using the pre-configured
 		target IP address and UDP port. This has the effect of
 		"punching through" the (Windows XP) firewall, allowing
 		the remainder of the TFTP transfer to proceed normally.
 		A better solution is to properly configure the firewall,
 		but sometimes that is not allowed.
 - Hashing support:
 		CONFIG_CMD_HASH
 		This enables a generic 'hash' command which can produce
 		hashes / digests from a few algorithms (e.g. SHA1, SHA256).
 		CONFIG_HASH_VERIFY
 		Enable the hash verify command (hash -v). This adds to code
 		size a little.
 		CONFIG_SHA1 - support SHA1 hashing
 		CONFIG_SHA256 - support SHA256 hashing
 		Note: There is also a sha1sum command, which should perhaps
 		be deprecated in favour of 'hash sha1'.
 - Freescale i.MX specific commands:
 		CONFIG_CMD_HDMIDETECT
 		This enables 'hdmidet' command which returns true if an
 		HDMI monitor is detected.  This command is i.MX 6 specific.
 		CONFIG_CMD_BMODE
 		This enables the 'bmode' (bootmode) command for forcing
 		a boot from specific media.
 		This is useful for forcing the ROM's usb downloader to
 		activate upon a watchdog reset which is nice when iterating
 		on U-Boot.  Using the reset button or running bmode normal
 		will set it back to normal.  This command currently
 		supports i.MX53 and i.MX6.
 - Signing support:
 		CONFIG_RSA
 		This enables the RSA algorithm used for FIT image verification
 		in U-Boot. See doc/uImage.FIT/signature.txt for more information.
 		The signing part is build into mkimage regardless of this
 		option.
 - Show boot progress:
 		CONFIG_SHOW_BOOT_PROGRESS
 		Defining this option allows to add some board-
 		specific code (calling a user-provided function
 		"show_boot_progress(int)") that enables you to show
 		the system's boot progress on some display (for
 		example, some LED's) on your board. At the moment,
 		the following checkpoints are implemented:
 - Detailed boot stage timing
 		CONFIG_BOOTSTAGE
 		Define this option to get detailed timing of each stage
 		of the boot process.
 		CONFIG_BOOTSTAGE_USER_COUNT
 		This is the number of available user bootstage records.
 		Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
 		a new ID will be allocated from this stash. If you exceed
 		the limit, recording will stop.
 		CONFIG_BOOTSTAGE_REPORT
 		Define this to print a report before boot, similar to this:
 		Timer summary in microseconds:
 		       Mark    Elapsed  Stage
 			  0          0  reset
 		  3,575,678  3,575,678  board_init_f start
 		  3,575,695         17  arch_cpu_init A9
 		  3,575,777         82  arch_cpu_init done
 		  3,659,598     83,821  board_init_r start
 		  3,910,375    250,777  main_loop
 		 29,916,167 26,005,792  bootm_start
 		 30,361,327    445,160  start_kernel
 		CONFIG_CMD_BOOTSTAGE
 		Add a 'bootstage' command which supports printing a report
 		and un/stashing of bootstage data.
 		CONFIG_BOOTSTAGE_FDT
 		Stash the bootstage information in the FDT. A root 'bootstage'
 		node is created with each bootstage id as a child. Each child
 		has a 'name' property and either 'mark' containing the
 		mark time in microsecond, or 'accum' containing the
 		accumulated time for that bootstage id in microseconds.
 		For example:
 		bootstage {
 			154 {
 				name = "board_init_f";
 				mark = <3575678>;
 			};
 			170 {
 				name = "lcd";
 				accum = <33482>;
 			};
 		};
 		Code in the Linux kernel can find this in /proc/devicetree.
 Legacy uImage format:
   Arg	Where			When
     1	common/cmd_bootm.c	before attempting to boot an image
    -1	common/cmd_bootm.c	Image header has bad	 magic number
     2	common/cmd_bootm.c	Image header has correct magic number
    -2	common/cmd_bootm.c	Image header has bad	 checksum
     3	common/cmd_bootm.c	Image header has correct checksum
    -3	common/cmd_bootm.c	Image data   has bad	 checksum
     4	common/cmd_bootm.c	Image data   has correct checksum
    -4	common/cmd_bootm.c	Image is for unsupported architecture
     5	common/cmd_bootm.c	Architecture check OK
    -5	common/cmd_bootm.c	Wrong Image Type (not kernel, multi)
     6	common/cmd_bootm.c	Image Type check OK
    -6	common/cmd_bootm.c	gunzip uncompression error
    -7	common/cmd_bootm.c	Unimplemented compression type
     7	common/cmd_bootm.c	Uncompression OK
     8	common/cmd_bootm.c	No uncompress/copy overwrite error
    -9	common/cmd_bootm.c	Unsupported OS (not Linux, BSD, VxWorks, QNX)
     9	common/image.c		Start initial ramdisk verification
   -10	common/image.c		Ramdisk header has bad	   magic number
   -11	common/image.c		Ramdisk header has bad	   checksum
    10	common/image.c		Ramdisk header is OK
   -12	common/image.c		Ramdisk data   has bad	   checksum
    11	common/image.c		Ramdisk data   has correct checksum
    12	common/image.c		Ramdisk verification complete, start loading
   -13	common/image.c		Wrong Image Type (not PPC Linux ramdisk)
    13	common/image.c		Start multifile image verification
    14	common/image.c		No initial ramdisk, no multifile, continue.
    15	arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
   -30	arch/powerpc/lib/board.c	Fatal error, hang the system
   -31	post/post.c		POST test failed, detected by post_output_backlog()
   -32	post/post.c		POST test failed, detected by post_run_single()
    34	common/cmd_doc.c	before loading a Image from a DOC device
   -35	common/cmd_doc.c	Bad usage of "doc" command
    35	common/cmd_doc.c	correct usage of "doc" command
   -36	common/cmd_doc.c	No boot device
    36	common/cmd_doc.c	correct boot device
   -37	common/cmd_doc.c	Unknown Chip ID on boot device
    37	common/cmd_doc.c	correct chip ID found, device available
   -38	common/cmd_doc.c	Read Error on boot device
    38	common/cmd_doc.c	reading Image header from DOC device OK
   -39	common/cmd_doc.c	Image header has bad magic number
    39	common/cmd_doc.c	Image header has correct magic number
   -40	common/cmd_doc.c	Error reading Image from DOC device
    40	common/cmd_doc.c	Image header has correct magic number
    41	common/cmd_ide.c	before loading a Image from a IDE device
   -42	common/cmd_ide.c	Bad usage of "ide" command
    42	common/cmd_ide.c	correct usage of "ide" command
   -43	common/cmd_ide.c	No boot device
    43	common/cmd_ide.c	boot device found
   -44	common/cmd_ide.c	Device not available
    44	common/cmd_ide.c	Device available
   -45	common/cmd_ide.c	wrong partition selected
    45	common/cmd_ide.c	partition selected
   -46	common/cmd_ide.c	Unknown partition table
    46	common/cmd_ide.c	valid partition table found
   -47	common/cmd_ide.c	Invalid partition type
    47	common/cmd_ide.c	correct partition type
   -48	common/cmd_ide.c	Error reading Image Header on boot device
    48	common/cmd_ide.c	reading Image Header from IDE device OK
   -49	common/cmd_ide.c	Image header has bad magic number
    49	common/cmd_ide.c	Image header has correct magic number
   -50	common/cmd_ide.c	Image header has bad	 checksum
    50	common/cmd_ide.c	Image header has correct checksum
   -51	common/cmd_ide.c	Error reading Image from IDE device
    51	common/cmd_ide.c	reading Image from IDE device OK
    52	common/cmd_nand.c	before loading a Image from a NAND device
   -53	common/cmd_nand.c	Bad usage of "nand" command
    53	common/cmd_nand.c	correct usage of "nand" command
   -54	common/cmd_nand.c	No boot device
    54	common/cmd_nand.c	boot device found
   -55	common/cmd_nand.c	Unknown Chip ID on boot device
    55	common/cmd_nand.c	correct chip ID found, device available
   -56	common/cmd_nand.c	Error reading Image Header on boot device
    56	common/cmd_nand.c	reading Image Header from NAND device OK
   -57	common/cmd_nand.c	Image header has bad magic number
    57	common/cmd_nand.c	Image header has correct magic number
   -58	common/cmd_nand.c	Error reading Image from NAND device
    58	common/cmd_nand.c	reading Image from NAND device OK
   -60	common/env_common.c	Environment has a bad CRC, using default
    64	net/eth.c		starting with Ethernet configuration.
   -64	net/eth.c		no Ethernet found.
    65	net/eth.c		Ethernet found.
   -80	common/cmd_net.c	usage wrong
    80	common/cmd_net.c	before calling NetLoop()
   -81	common/cmd_net.c	some error in NetLoop() occurred
    81	common/cmd_net.c	NetLoop() back without error
   -82	common/cmd_net.c	size == 0 (File with size 0 loaded)
    82	common/cmd_net.c	trying automatic boot
    83	common/cmd_net.c	running "source" command
   -83	common/cmd_net.c	some error in automatic boot or "source" command
    84	common/cmd_net.c	end without errors
 FIT uImage format:
   Arg	Where			When
   100	common/cmd_bootm.c	Kernel FIT Image has correct format
  -100	common/cmd_bootm.c	Kernel FIT Image has incorrect format
   101	common/cmd_bootm.c	No Kernel subimage unit name, using configuration
  -101	common/cmd_bootm.c	Can't get configuration for kernel subimage
   102	common/cmd_bootm.c	Kernel unit name specified
  -103	common/cmd_bootm.c	Can't get kernel subimage node offset
   103	common/cmd_bootm.c	Found configuration node
   104	common/cmd_bootm.c	Got kernel subimage node offset
  -104	common/cmd_bootm.c	Kernel subimage hash verification failed
   105	common/cmd_bootm.c	Kernel subimage hash verification OK
  -105	common/cmd_bootm.c	Kernel subimage is for unsupported architecture
   106	common/cmd_bootm.c	Architecture check OK
  -106	common/cmd_bootm.c	Kernel subimage has wrong type
   107	common/cmd_bootm.c	Kernel subimage type OK
  -107	common/cmd_bootm.c	Can't get kernel subimage data/size
   108	common/cmd_bootm.c	Got kernel subimage data/size
  -108	common/cmd_bootm.c	Wrong image type (not legacy, FIT)
  -109	common/cmd_bootm.c	Can't get kernel subimage type
  -110	common/cmd_bootm.c	Can't get kernel subimage comp
  -111	common/cmd_bootm.c	Can't get kernel subimage os
  -112	common/cmd_bootm.c	Can't get kernel subimage load address
  -113	common/cmd_bootm.c	Image uncompress/copy overwrite error
   120	common/image.c		Start initial ramdisk verification
  -120	common/image.c		Ramdisk FIT image has incorrect format
   121	common/image.c		Ramdisk FIT image has correct format
   122	common/image.c		No ramdisk subimage unit name, using configuration
  -122	common/image.c		Can't get configuration for ramdisk subimage
   123	common/image.c		Ramdisk unit name specified
  -124	common/image.c		Can't get ramdisk subimage node offset
   125	common/image.c		Got ramdisk subimage node offset
  -125	common/image.c		Ramdisk subimage hash verification failed
   126	common/image.c		Ramdisk subimage hash verification OK
  -126	common/image.c		Ramdisk subimage for unsupported architecture
   127	common/image.c		Architecture check OK
  -127	common/image.c		Can't get ramdisk subimage data/size
   128	common/image.c		Got ramdisk subimage data/size
   129	common/image.c		Can't get ramdisk load address
  -129	common/image.c		Got ramdisk load address
  -130	common/cmd_doc.c	Incorrect FIT image format
   131	common/cmd_doc.c	FIT image format OK
  -140	common/cmd_ide.c	Incorrect FIT image format
   141	common/cmd_ide.c	FIT image format OK
  -150	common/cmd_nand.c	Incorrect FIT image format
   151	common/cmd_nand.c	FIT image format OK
 - FIT image support:
 		CONFIG_FIT
 		Enable support for the FIT uImage format.
 		CONFIG_FIT_BEST_MATCH
 		When no configuration is explicitly selected, default to the
 		one whose fdt's compatibility field best matches that of
 		U-Boot itself. A match is considered "best" if it matches the
 		most specific compatibility entry of U-Boot's fdt's root node.
 		The order of entries in the configuration's fdt is ignored.
 		CONFIG_FIT_SIGNATURE
 		This option enables signature verification of FIT uImages,
 		using a hash signed and verified using RSA. See
 		doc/uImage.FIT/signature.txt for more details.
 - Standalone program support:
 		CONFIG_STANDALONE_LOAD_ADDR
 		This option defines a board specific value for the
 		address where standalone program gets loaded, thus
 		overwriting the architecture dependent default
 		settings.
 - Frame Buffer Address:
 		CONFIG_FB_ADDR
 		Define CONFIG_FB_ADDR if you want to use specific
 		address for frame buffer.  This is typically the case
 		when using a graphics controller has separate video
 		memory.  U-Boot will then place the frame buffer at
 		the given address instead of dynamically reserving it
 		in system RAM by calling lcd_setmem(), which grabs
 		the memory for the frame buffer depending on the
 		configured panel size.
 		Please see board_init_f function.
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
 		CONFIG_UPDATE_TFTP_MSEC_MAX
 		These options enable and control the auto-update feature;
 		for a more detailed description refer to doc/README.update.
 - MTD Support (mtdparts command, UBI support)
 		CONFIG_MTD_DEVICE
 		Adds the MTD device infrastructure from the Linux kernel.
 		Needed for mtdparts command support.
 		CONFIG_MTD_PARTITIONS
 		Adds the MTD partitioning infrastructure from the Linux
 		kernel. Needed for UBI support.
 - UBI support
 		CONFIG_CMD_UBI
 		Adds commands for interacting with MTD partitions formatted
 		with the UBI flash translation layer
 		Requires also defining CONFIG_RBTREE
 		CONFIG_UBI_SILENCE_MSG
 		Make the verbose messages from UBI stop printing.  This leaves
 		warnings and errors enabled.
 - UBIFS support
 		CONFIG_CMD_UBIFS
 		Adds commands for interacting with UBI volumes formatted as
 		UBIFS.  UBIFS is read-only in u-boot.
 		Requires UBI support as well as CONFIG_LZO
 		CONFIG_UBIFS_SILENCE_MSG
 		Make the verbose messages from UBIFS stop printing.  This leaves
 		warnings and errors enabled.
 - SPL framework
 		CONFIG_SPL
 		Enable building of SPL globally.
 		CONFIG_SPL_LDSCRIPT
 		LDSCRIPT for linking the SPL binary.
 		CONFIG_SPL_MAX_FOOTPRINT
 		Maximum size in memory allocated to the SPL, BSS included.
 		When defined, the linker checks that the actual memory
 		used by SPL from _start to __bss_end does not exceed it.
 		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
 		must not be both defined at the same time.
 		CONFIG_SPL_MAX_SIZE
 		Maximum size of the SPL image (text, data, rodata, and
 		linker lists sections), BSS excluded.
 		When defined, the linker checks that the actual size does
 		not exceed it.
 		CONFIG_SPL_TEXT_BASE
 		TEXT_BASE for linking the SPL binary.
 		CONFIG_SPL_RELOC_TEXT_BASE
 		Address to relocate to.  If unspecified, this is equal to
 		CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
 		CONFIG_SPL_BSS_START_ADDR
 		Link address for the BSS within the SPL binary.
 		CONFIG_SPL_BSS_MAX_SIZE
 		Maximum size in memory allocated to the SPL BSS.
 		When defined, the linker checks that the actual memory used
 		by SPL from __bss_start to __bss_end does not exceed it.
 		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
 		must not be both defined at the same time.
 		CONFIG_SPL_STACK
 		Adress of the start of the stack SPL will use
 		CONFIG_SPL_RELOC_STACK
 		Adress of the start of the stack SPL will use after
 		relocation.  If unspecified, this is equal to
 		CONFIG_SPL_STACK.
 		CONFIG_SYS_SPL_MALLOC_START
 		Starting address of the malloc pool used in SPL.
 		CONFIG_SYS_SPL_MALLOC_SIZE
 		The size of the malloc pool used in SPL.
 		CONFIG_SPL_FRAMEWORK
 		Enable the SPL framework under common/.  This framework
 		supports MMC, NAND and YMODEM loading of U-Boot and NAND
 		NAND loading of the Linux Kernel.
 		CONFIG_SPL_DISPLAY_PRINT
 		For ARM, enable an optional function to print more information
 		about the running system.
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 		CONFIG_SPL_LIBCOMMON_SUPPORT
 		Support for common/libcommon.o in SPL binary
 		CONFIG_SPL_LIBDISK_SUPPORT
 		Support for disk/libdisk.o in SPL binary
 		CONFIG_SPL_I2C_SUPPORT
 		Support for drivers/i2c/libi2c.o in SPL binary
 		CONFIG_SPL_GPIO_SUPPORT
 		Support for drivers/gpio/libgpio.o in SPL binary
 		CONFIG_SPL_MMC_SUPPORT
 		Support for drivers/mmc/libmmc.o in SPL binary
 		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
 		CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
 		CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION
 		Address, size and partition on the MMC to load U-Boot from
 		when the MMC is being used in raw mode.
 		CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
 		Sector to load kernel uImage from when MMC is being
 		used in raw mode (for Falcon mode)
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
 		Sector and number of sectors to load kernel argument
 		parameters from when MMC is being used in raw mode
 		(for falcon mode)
 		CONFIG_SPL_FAT_SUPPORT
 		Support for fs/fat/libfat.o in SPL binary
 		CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
 		Filename to read to load U-Boot when reading from FAT
 		CONFIG_SPL_FAT_LOAD_KERNEL_NAME
 		Filename to read to load kernel uImage when reading
 		from FAT (for Falcon mode)
 		CONFIG_SPL_FAT_LOAD_ARGS_NAME
 		Filename to read to load kernel argument parameters
 		when reading from FAT (for Falcon mode)
 		CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
 		Set this for NAND SPL on PPC mpc83xx targets, so that
 		start.S waits for the rest of the SPL to load before
 		continuing (the hardware starts execution after just
 		loading the first page rather than the full 4K).
 		CONFIG_SPL_NAND_BASE
 		Include nand_base.c in the SPL.  Requires
 		CONFIG_SPL_NAND_DRIVERS.
 		CONFIG_SPL_NAND_DRIVERS
 		SPL uses normal NAND drivers, not minimal drivers.
 		CONFIG_SPL_NAND_ECC
 		Include standard software ECC in the SPL
 		CONFIG_SPL_NAND_SIMPLE
 		Support for NAND boot using simple NAND drivers that
 		expose the cmd_ctrl() interface.
 		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 		Set for the SPL on PPC mpc8xxx targets, support for
 		drivers/ddr/fsl/libddr.o in SPL binary.
 		CONFIG_SPL_COMMON_INIT_DDR
 		Set for common ddr init with serial presence detect in
 		SPL binary.
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
 		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
 		CONFIG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 		CONFIG_SPL_NAND_BOOT
 		Add support NAND boot
 		CONFIG_SYS_NAND_U_BOOT_OFFS
 		Location in NAND to read U-Boot from
 		CONFIG_SYS_NAND_U_BOOT_DST
 		Location in memory to load U-Boot to
 		CONFIG_SYS_NAND_U_BOOT_SIZE
 		Size of image to load
 		CONFIG_SYS_NAND_U_BOOT_START
 		Entry point in loaded image to jump to
 		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 		Define this if you need to first read the OOB and then the
 		data. This is used for example on davinci plattforms.
 		CONFIG_SPL_OMAP3_ID_NAND
 		Support for an OMAP3-specific set of functions to return the
 		ID and MFR of the first attached NAND chip, if present.
 		CONFIG_SPL_SERIAL_SUPPORT
 		Support for drivers/serial/libserial.o in SPL binary
 		CONFIG_SPL_SPI_FLASH_SUPPORT
 		Support for drivers/mtd/spi/libspi_flash.o in SPL binary
 		CONFIG_SPL_SPI_SUPPORT
 		Support for drivers/spi/libspi.o in SPL binary
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 		CONFIG_SPL_ENV_SUPPORT
 		Support for the environment operating in SPL binary
 		CONFIG_SPL_NET_SUPPORT
 		Support for the net/libnet.o in SPL binary.
 		It conflicts with SPL env from storage medium specified by
 		CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
 		CONFIG_SPL_PAD_TO
 		Image offset to which the SPL should be padded before appending
 		the SPL payload. By default, this is defined as
 		CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
 		CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
 		payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
 		CONFIG_SPL_TARGET
 		Final target image containing SPL and payload.  Some SPLs
 		use an arch-specific makefile fragment instead, for
 		example if more than one image needs to be produced.
 		CONFIG_FIT_SPL_PRINT
 		Printing information about a FIT image adds quite a bit of
 		code to SPL. So this is normally disabled in SPL. Use this
 		option to re-enable it. This will affect the output of the
 		bootm command when booting a FIT image.
 - TPL framework
 		CONFIG_TPL
 		Enable building of TPL globally.
 		CONFIG_TPL_PAD_TO
 		Image offset to which the TPL should be padded before appending
 		the TPL payload. By default, this is defined as
 		CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
 		CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
 		payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
 Modem Support:
 --------------
 [so far only for SMDK2400 boards]
 - Modem support enable:
 		CONFIG_MODEM_SUPPORT
 - RTS/CTS Flow control enable:
 		CONFIG_HWFLOW
 - Modem debug support:
 		CONFIG_MODEM_SUPPORT_DEBUG
 		Enables debugging stuff (char screen[1024], dbg())
 		for modem support. Useful only with BDI2000.
 - Interrupt support (PPC):
 		There are common interrupt_init() and timer_interrupt()
 		for all PPC archs. interrupt_init() calls interrupt_init_cpu()
 		for CPU specific initialization. interrupt_init_cpu()
 		should set decrementer_count to appropriate value. If
 		CPU resets decrementer automatically after interrupt
 		(ppc4xx) it should set decrementer_count to zero.
 		timer_interrupt() calls timer_interrupt_cpu() for CPU
 		specific handling. If board has watchdog / status_led
 		/ other_activity_monitor it works automatically from
 		general timer_interrupt().
 - General:
 		In the target system modem support is enabled when a
 		specific key (key combination) is pressed during
 		power-on. Otherwise U-Boot will boot normally
 		(autoboot). The key_pressed() function is called from
 		board_init(). Currently key_pressed() is a dummy
 		function, returning 1 and thus enabling modem
 		initialization.
 		If there are no modem init strings in the
 		environment, U-Boot proceed to autoboot; the
 		previous output (banner, info printfs) will be
 		suppressed, though.
 		See also: doc/README.Modem
 Board initialization settings:
 ------------------------------
 During Initialization u-boot calls a number of board specific functions
 to allow the preparation of board specific prerequisites, e.g. pin setup
 before drivers are initialized. To enable these callbacks the
 following configuration macros have to be defined. Currently this is
 architecture specific, so please check arch/your_architecture/lib/board.c
 typically in board_init_f() and board_init_r().
 - CONFIG_BOARD_EARLY_INIT_F: Call board_early_init_f()
 - CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r()
 - CONFIG_BOARD_LATE_INIT: Call board_late_init()
 - CONFIG_BOARD_POSTCLK_INIT: Call board_postclk_init()
 Configuration Settings:
 -----------------------
 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
 		undefine this when you're short of memory.
 - CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
 		width of the commands listed in the 'help' command output.
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
 		prompt for user input.
 - CONFIG_SYS_CBSIZE:	Buffer size for input from the Console
 - CONFIG_SYS_PBSIZE:	Buffer size for Console output
 - CONFIG_SYS_MAXARGS:	max. Number of arguments accepted for monitor commands
 - CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
 		the application (usually a Linux kernel) when it is
 		booted
 - CONFIG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 - CONFIG_SYS_CONSOLE_INFO_QUIET
 		Suppress display of console information at boot.
 - CONFIG_SYS_CONSOLE_IS_IN_ENV
 		If the board specific function
 			extern int overwrite_console (void);
 		returns 1, the stdin, stderr and stdout are switched to the
 		serial port, else the settings in the environment are used.
 - CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 		Enable the call to overwrite_console().
 - CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 		Enable overwrite of previous console environment settings.
 - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
 		Begin and End addresses of the area used by the
 		simple memory test.
 - CONFIG_SYS_ALT_MEMTEST:
 		Enable an alternate, more extensive memory test.
 - CONFIG_SYS_MEMTEST_SCRATCH:
 		Scratch address used by the alternate memory test
 		You only need to set this if address zero isn't writeable
 - CONFIG_SYS_MEM_TOP_HIDE (PPC only):
 		If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
 		this specified memory area will get subtracted from the top
 		(end) of RAM and won't get "touched" at all by U-Boot. By
 		fixing up gd->ram_size the Linux kernel should gets passed
 		the now "corrected" memory size and won't touch it either.
 		This should work for arch/ppc and arch/powerpc. Only Linux
 		board ports in arch/powerpc with bootwrapper support that
 		recalculate the memory size from the SDRAM controller setup
 		will have to get fixed in Linux additionally.
 		This option can be used as a workaround for the 440EPx/GRx
 		CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
 		be touched.
 		WARNING: Please make sure that this value is a multiple of
 		the Linux page size (normally 4k). If this is not the case,
 		then the end address of the Linux memory will be located at a
 		non page size aligned address and this could cause major
 		problems.
 - CONFIG_SYS_LOADS_BAUD_CHANGE:
 		Enable temporary baudrate change while serial download
 - CONFIG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 - CONFIG_SYS_MBIO_BASE:
 		Physical start address of Motherboard I/O (if using a
 		Cogent motherboard)
 - CONFIG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 - CONFIG_SYS_MONITOR_BASE:
 		Physical start address of boot monitor code (set by
 		make config files to be same as the text base address
 		(CONFIG_SYS_TEXT_BASE) used when linking) - same as
 		CONFIG_SYS_FLASH_BASE when booting from flash.
 - CONFIG_SYS_MONITOR_LEN:
 		Size of memory reserved for monitor code, used to
 		determine _at_compile_time_ (!) if the environment is
 		embedded within the U-Boot image, or in a separate
 		flash sector.
 - CONFIG_SYS_MALLOC_LEN:
 		Size of DRAM reserved for malloc() use.
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,
 		you can define CONFIG_SYS_BOOTM_LEN in your board config file
 		to adjust this setting to your needs.
 - CONFIG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
 		the Linux kernel (bd_info, boot arguments, FDT blob if
 		used) must be put below this limit, unless "bootm_low"
 		environment variable is defined and non-zero. In such case
 		all data for the Linux kernel must be between "bootm_low"
 		and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.	 The environment
 		variable "bootm_mapsize" will override the value of
 		CONFIG_SYS_BOOTMAPSZ.  If CONFIG_SYS_BOOTMAPSZ is undefined,
 		then the value in "bootm_size" will be used instead.
 - CONFIG_SYS_BOOT_RAMDISK_HIGH:
 		Enable initrd_high functionality.  If defined then the
 		initrd_high feature is enabled and the bootm ramdisk subcommand
 		is enabled.
 - CONFIG_SYS_BOOT_GET_CMDLINE:
 		Enables allocating and saving kernel cmdline in space between
 		"bootm_low" and "bootm_low" + BOOTMAPSZ.
 - CONFIG_SYS_BOOT_GET_KBD:
 		Enables allocating and saving a kernel copy of the bd_info in
 		space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
 - CONFIG_SYS_MAX_FLASH_BANKS:
 		Max number of Flash memory banks
 - CONFIG_SYS_MAX_FLASH_SECT:
 		Max number of sectors on a Flash chip
 - CONFIG_SYS_FLASH_ERASE_TOUT:
 		Timeout for Flash erase operations (in ms)
 - CONFIG_SYS_FLASH_WRITE_TOUT:
 		Timeout for Flash write operations (in ms)
 - CONFIG_SYS_FLASH_LOCK_TOUT
 		Timeout for Flash set sector lock bit operation (in ms)
 - CONFIG_SYS_FLASH_UNLOCK_TOUT
 		Timeout for Flash clear lock bits operation (in ms)
 - CONFIG_SYS_FLASH_PROTECTION
 		If defined, hardware flash sectors protection is used
 		instead of U-Boot software protection.
 - CONFIG_SYS_DIRECT_FLASH_TFTP:
 		Enable TFTP transfers directly to flash memory;
 		without this option such a download has to be
 		performed in two steps: (1) download to RAM, and (2)
 		copy from RAM to flash.
 		The two-step approach is usually more reliable, since
 		you can check if the download worked before you erase
 		the flash, but in some situations (when system RAM is
 		too limited to allow for a temporary copy of the
 		downloaded image) this option may be very useful.
 - CONFIG_SYS_FLASH_CFI:
 		Define if the flash driver uses extra elements in the
 		common flash structure for storing flash geometry.
 - CONFIG_FLASH_CFI_DRIVER
 		This option also enables the building of the cfi_flash driver
 		in the drivers directory
 - CONFIG_FLASH_CFI_MTD
 		This option enables the building of the cfi_mtd driver
 		in the drivers directory. The driver exports CFI flash
 		to the MTD layer.
 - CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 		Use buffered writes to flash.
 - CONFIG_FLASH_SPANSION_S29WS_N
 		s29ws-n MirrorBit flash has non-standard addresses for buffered
 		write commands.
 - CONFIG_SYS_FLASH_QUIET_TEST
 		If this option is defined, the common CFI flash doesn't
 		print it's warning upon not recognized FLASH banks. This
 		is useful, if some of the configured banks are only
 		optionally available.
 - CONFIG_FLASH_SHOW_PROGRESS
 		If defined (must be an integer), print out countdown
 		digits and dots.  Recommended value: 45 (9..1) for 80
 		column displays, 15 (3..1) for 40 column displays.
 - CONFIG_FLASH_VERIFY
 		If defined, the content of the flash (destination) is compared
 		against the source after the write operation. An error message
 		will be printed when the contents are not identical.
 		Please note that this option is useless in nearly all cases,
 		since such flash programming errors usually are detected earlier
 		while unprotecting/erasing/programming. Please only enable
 		this option if you really know what you are doing.
 - CONFIG_SYS_RX_ETH_BUFFER:
 		Defines the number of Ethernet receive buffers. On some
 		Ethernet controllers it is recommended to set this value
 		to 8 or even higher (EEPRO100 or 405 EMAC), since all
 		buffers can be full shortly after enabling the interface
 		on high Ethernet traffic.
 		Defaults to 4 if not defined.
 - CONFIG_ENV_MAX_ENTRIES
 	Maximum number of entries in the hash table that is used
 	internally to store the environment settings. The default
 	setting is supposed to be generous and should work in most
 	cases. This setting can be used to tune behaviour; see
 	lib/hashtable.c for details.
 - CONFIG_ENV_FLAGS_LIST_DEFAULT
 - CONFIG_ENV_FLAGS_LIST_STATIC
 	Enable validation of the values given to environment variables when
 	calling env set.  Variables can be restricted to only decimal,
 	hexadecimal, or boolean.  If CONFIG_CMD_NET is also defined,
 	the variables can also be restricted to IP address or MAC address.
 	The format of the list is:
 		type_attribute = [s|d|x|b|i|m]
 		access_atribute = [a|r|o|c]
 		attributes = type_attribute[access_atribute]
 		entry = variable_name[:attributes]
 		list = entry[,list]
 	The type attributes are:
 		s - String (default)
 		d - Decimal
 		x - Hexadecimal
 		b - Boolean ([1yYtT|0nNfF])
 		i - IP address
 		m - MAC address
 	The access attributes are:
 		a - Any (default)
 		r - Read-only
 		o - Write-once
 		c - Change-default
 	- CONFIG_ENV_FLAGS_LIST_DEFAULT
 		Define this to a list (string) to define the ".flags"
 		envirnoment variable in the default or embedded environment.
 	- CONFIG_ENV_FLAGS_LIST_STATIC
 		Define this to a list (string) to define validation that
 		should be done if an entry is not found in the ".flags"
 		environment variable.  To override a setting in the static
 		list, simply add an entry for the same variable name to the
 		".flags" variable.
 - CONFIG_ENV_ACCESS_IGNORE_FORCE
 	If defined, don't allow the -f switch to env set override variable
 	access flags.
 - CONFIG_SYS_GENERIC_BOARD
 	This selects the architecture-generic board system instead of the
 	architecture-specific board files. It is intended to move boards
 	to this new framework over time. Defining this will disable the
 	arch/foo/lib/board.c file and use common/board_f.c and
 	common/board_r.c instead. To use this option your architecture
 	must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in
 	its config.mk file). If you find problems enabling this option on
 	your board please report the problem and send patches!
-- CONFIG_SYS_SYM_OFFSETS
-	This is set by architectures that use offsets for link symbols
-	instead of absolute values. So bss_start is obtained using an
-	offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
-	directly. You should not need to touch this setting.
 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
 	This is set by OMAP boards for the max time that reset should
 	be asserted. See doc/README.omap-reset-time for details on how
 	the value can be calulated on a given board.
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
 - CONFIG_BUILD_ENVCRC:
 	Builds up envcrc with the target environment so that external utils
 	may easily extract it and embed it in final U-Boot images.
 - CONFIG_ENV_IS_IN_FLASH:
 	Define this if the environment is in flash memory.
 	a) The environment occupies one whole flash sector, which is
 	   "embedded" in the text segment with the U-Boot code. This
 	   happens usually with "bottom boot sector" or "top boot
 	   sector" type flash chips, which have several smaller
 	   sectors at the start or the end. For instance, such a
 	   layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
 	   such a case you would place the environment in one of the
 	   4 kB sectors - with U-Boot code before and after it. With
 	   "top boot sector" type flash chips, you would put the
 	   environment in one of the last sectors, leaving a gap
 	   between U-Boot and the environment.
 	- CONFIG_ENV_OFFSET:
 	   Offset of environment data (variable area) to the
 	   beginning of flash memory; for instance, with bottom boot
 	   type flash chips the second sector can be used: the offset
 	   for this sector is given here.
 	   CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
 	- CONFIG_ENV_ADDR:
 	   This is just another way to specify the start address of
 	   the flash sector containing the environment (instead of
 	   CONFIG_ENV_OFFSET).
 	- CONFIG_ENV_SECT_SIZE:
 	   Size of the sector containing the environment.
 	b) Sometimes flash chips have few, equal sized, BIG sectors.
 	   In such a case you don't want to spend a whole sector for
 	   the environment.
 	- CONFIG_ENV_SIZE:
 	   If you use this in combination with CONFIG_ENV_IS_IN_FLASH
 	   and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
 	   of this flash sector for the environment. This saves
 	   memory for the RAM copy of the environment.
 	   It may also save flash memory if you decide to use this
 	   when your environment is "embedded" within U-Boot code,
 	   since then the remainder of the flash sector could be used
 	   for U-Boot code. It should be pointed out that this is
 	   STRONGLY DISCOURAGED from a robustness point of view:
 	   updating the environment in flash makes it always
 	   necessary to erase the WHOLE sector. If something goes
 	   wrong before the contents has been restored from a copy in
 	   RAM, your target system will be dead.
 	- CONFIG_ENV_ADDR_REDUND
 	  CONFIG_ENV_SIZE_REDUND
 	   These settings describe a second storage area used to hold
 	   a redundant copy of the environment data, so that there is
 	   a valid backup copy in case there is a power failure during
 	   a "saveenv" operation.
 BE CAREFUL! Any changes to the flash layout, and some changes to the
 source code will make it necessary to adapt <board>/u-boot.lds*
 accordingly!
 - CONFIG_ENV_IS_IN_NVRAM:
 	Define this if you have some non-volatile memory device
 	(NVRAM, battery buffered SRAM) which you want to use for the
 	environment.
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These two #defines are used to determine the memory area you
 	  want to use for environment. It is assumed that this memory
 	  can just be read and written to, without any special
 	  provision.
 BE CAREFUL! The first access to the environment happens quite early
 in U-Boot initalization (when we try to get the setting of for the
 console baudrate). You *MUST* have mapped your NVRAM area then, or
 U-Boot will hang.
 Please note that even with NVRAM we still use a copy of the
 environment in RAM: we could work on NVRAM directly, but we want to
 keep settings there always unmodified except somebody uses "saveenv"
 to save the current settings.
 - CONFIG_ENV_IS_IN_EEPROM:
 	Use this if you have an EEPROM or similar serial access
 	device and a driver for it.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the
 	  environment area within the total memory of your EEPROM.
 	- CONFIG_SYS_I2C_EEPROM_ADDR:
 	  If defined, specified the chip address of the EEPROM device.
 	  The default address is zero.
 	- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
 	  If defined, the number of bits used to address bytes in a
 	  single page in the EEPROM device.  A 64 byte page, for example
 	  would require six bits.
 	- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
 	  If defined, the number of milliseconds to delay between
 	  page writes.	The default is zero milliseconds.
 	- CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
 	  The length in bytes of the EEPROM memory array address.  Note
 	  that this is NOT the chip address length!
 	- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
 	  EEPROM chips that implement "address overflow" are ones
 	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 	  address and the extra bits end up in the "chip address" bit
 	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
 	  byte chips.
 	  Note that we consider the length of the address field to
 	  still be one byte because the extra address bits are hidden
 	  in the chip address.
 	- CONFIG_SYS_EEPROM_SIZE:
 	  The size in bytes of the EEPROM device.
 	- CONFIG_ENV_EEPROM_IS_ON_I2C
 	  define this, if you have I2C and SPI activated, and your
 	  EEPROM, which holds the environment, is on the I2C bus.
 	- CONFIG_I2C_ENV_EEPROM_BUS
 	  if you have an Environment on an EEPROM reached over
 	  I2C muxes, you can define here, how to reach this
 	  EEPROM. For example:
 	  #define CONFIG_I2C_ENV_EEPROM_BUS	  1
 	  EEPROM which holds the environment, is reached over
 	  a pca9547 i2c mux with address 0x70, channel 3.
 - CONFIG_ENV_IS_IN_DATAFLASH:
 	Define this if you have a DataFlash memory device which you
 	want to use for the environment.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These three #defines specify the offset and size of the
 	  environment area within the total memory of your DataFlash placed
 	  at the specified address.
 - CONFIG_ENV_IS_IN_REMOTE:
 	Define this if you have a remote memory space which you
 	want to use for the local device's environment.
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the address and size of the
 	  environment area within the remote memory space. The
 	  local device can get the environment from remote memory
 	  space by SRIO or PCIE links.
 BE CAREFUL! For some special cases, the local device can not use
 "saveenv" command. For example, the local device will get the
 environment stored in a remote NOR flash by SRIO or PCIE link,
 but it can not erase, write this NOR flash by SRIO or PCIE interface.
 - CONFIG_ENV_IS_IN_NAND:
 	Define this if you have a NAND device which you want to use
 	for the environment.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the environment
 	  area within the first NAND device.  CONFIG_ENV_OFFSET must be
 	  aligned to an erase block boundary.
 	- CONFIG_ENV_OFFSET_REDUND (optional):
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
 	  during a "saveenv" operation.	 CONFIG_ENV_OFFSET_RENDUND must be
 	  aligned to an erase block boundary.
 	- CONFIG_ENV_RANGE (optional):
 	  Specifies the length of the region in which the environment
 	  can be written.  This should be a multiple of the NAND device's
 	  block size.  Specifying a range with more erase blocks than
 	  are needed to hold CONFIG_ENV_SIZE allows bad blocks within
 	  the range to be avoided.
 	- CONFIG_ENV_OFFSET_OOB (optional):
 	  Enables support for dynamically retrieving the offset of the
 	  environment from block zero's out-of-band data.  The
 	  "nand env.oob" command can be used to record this offset.
 	  Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
 	  using CONFIG_ENV_OFFSET_OOB.
 - CONFIG_NAND_ENV_DST
 	Defines address in RAM to which the nand_spl code should copy the
 	environment. If redundant environment is used, it will be copied to
 	CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
 - CONFIG_ENV_IS_IN_UBI:
 	Define this if you have an UBI volume that you want to use for the
 	environment.  This has the benefit of wear-leveling the environment
 	accesses, which is important on NAND.
 	- CONFIG_ENV_UBI_PART:
 	  Define this to a string that is the mtd partition containing the UBI.
 	- CONFIG_ENV_UBI_VOLUME:
 	  Define this to the name of the volume that you want to store the
 	  environment in.
 	- CONFIG_ENV_UBI_VOLUME_REDUND:
 	  Define this to the name of another volume to store a second copy of
 	  the environment in.  This will enable redundant environments in UBI.
 	  It is assumed that both volumes are in the same MTD partition.
 	- CONFIG_UBI_SILENCE_MSG
 	- CONFIG_UBIFS_SILENCE_MSG
 	  You will probably want to define these to avoid a really noisy system
 	  when storing the env in UBI.
 - CONFIG_ENV_IS_IN_MMC:
 	Define this if you have an MMC device which you want to use for the
 	environment.
 	- CONFIG_SYS_MMC_ENV_DEV:
 	  Specifies which MMC device the environment is stored in.
 	- CONFIG_SYS_MMC_ENV_PART (optional):
 	  Specifies which MMC partition the environment is stored in. If not
 	  set, defaults to partition 0, the user area. Common values might be
 	  1 (first MMC boot partition), 2 (second MMC boot partition).
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the environment
 	  area within the specified MMC device.
 	  If offset is positive (the usual case), it is treated as relative to
 	  the start of the MMC partition. If offset is negative, it is treated
 	  as relative to the end of the MMC partition. This can be useful if
 	  your board may be fitted with different MMC devices, which have
 	  different sizes for the MMC partitions, and you always want the
 	  environment placed at the very end of the partition, to leave the
 	  maximum possible space before it, to store other data.
 	  These two values are in units of bytes, but must be aligned to an
 	  MMC sector boundary.
 	- CONFIG_ENV_OFFSET_REDUND (optional):
 	  Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
 	  hold a redundant copy of the environment data. This provides a
 	  valid backup copy in case the other copy is corrupted, e.g. due
 	  to a power failure during a "saveenv" operation.
 	  This value may also be positive or negative; this is handled in the
 	  same way as CONFIG_ENV_OFFSET.
 	  This value is also in units of bytes, but must also be aligned to
 	  an MMC sector boundary.
 	- CONFIG_ENV_SIZE_REDUND (optional):
 	  This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
 	  set. If this value is set, it must be set to the same value as
 	  CONFIG_ENV_SIZE.
 - CONFIG_SYS_SPI_INIT_OFFSET
 	Defines offset to the initial SPI buffer area in DPRAM. The
 	area is used at an early stage (ROM part) if the environment
 	is configured to reside in the SPI EEPROM: We need a 520 byte
 	scratch DPRAM area. It is used between the two initialization
 	calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
 	to be a good choice since it makes it far enough from the
 	start of the data area as well as from the stack pointer.
 Please note that the environment is read-only until the monitor
 has been relocated to RAM and a RAM copy of the environment has been
 created; also, when using EEPROM you will have to use getenv_f()
 until then to read environment variables.
 The environment is protected by a CRC32 checksum. Before the monitor
 is relocated into RAM, as a result of a bad CRC you will be working
 with the compiled-in default environment - *silently*!!! [This is
 necessary, because the first environment variable we need is the
 "baudrate" setting for the console - if we have a bad CRC, we don't
 have any device yet where we could complain.]
 Note: once the monitor has been relocated, then it will complain if
 the default environment is used; a new CRC is computed as soon as you
 use the "saveenv" command to store a valid environment.
 - CONFIG_SYS_FAULT_ECHO_LINK_DOWN:
 		Echo the inverted Ethernet link state to the fault LED.
 		Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR
 		      also needs to be defined.
 - CONFIG_SYS_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.
 - CONFIG_NS16550_MIN_FUNCTIONS:
 		Define this if you desire to only have use of the NS16550_init
 		and NS16550_putc functions for the serial driver located at
 		drivers/serial/ns16550.c.  This option is useful for saving
 		space for already greatly restricted images, including but not
 		limited to NAND_SPL configurations.
 - CONFIG_DISPLAY_BOARDINFO
 		Display information about the board that U-Boot is running on
 		when U-Boot starts up. The board function checkboard() is called
 		to do this.
 - CONFIG_DISPLAY_BOARDINFO_LATE
 		Similar to the previous option, but display this information
 		later, once stdio is running and output goes to the LCD, if
 		present.
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 - CONFIG_SYS_CACHELINE_SIZE:
 		Cache Line Size of the CPU.
 - CONFIG_SYS_DEFAULT_IMMR:
 		Default address of the IMMR after system reset.
 		Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
 		and RPXsuper) to be able to adjust the position of
 		the IMMR register after a reset.
 - CONFIG_SYS_CCSRBAR_DEFAULT:
 		Default (power-on reset) physical address of CCSR on Freescale
 		PowerPC SOCs.
 - CONFIG_SYS_CCSRBAR:
 		Virtual address of CCSR.  On a 32-bit build, this is typically
 		the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
 		CONFIG_SYS_DEFAULT_IMMR must also be set to this value,
 		for cross-platform code that uses that macro instead.
 - CONFIG_SYS_CCSRBAR_PHYS:
 		Physical address of CCSR.  CCSR can be relocated to a new
 		physical address, if desired.  In this case, this macro should
 		be set to that address.	 Otherwise, it should be set to the
 		same value as CONFIG_SYS_CCSRBAR_DEFAULT.  For example, CCSR
 		is typically relocated on 36-bit builds.  It is recommended
 		that this macro be defined via the _HIGH and _LOW macros:
 		#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
 			* 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
 - CONFIG_SYS_CCSRBAR_PHYS_HIGH:
 		Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS.	This value is typically
 		either 0 (32-bit build) or 0xF (36-bit build).	This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 - CONFIG_SYS_CCSRBAR_PHYS_LOW:
 		Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS.  This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 - CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
 		If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
 		forced to a value that ensures that CCSR is not relocated.
 - Floppy Disk Support:
 		CONFIG_SYS_FDC_DRIVE_NUMBER
 		the default drive number (default value 0)
 		CONFIG_SYS_ISA_IO_STRIDE
 		defines the spacing between FDC chipset registers
 		(default value 1)
 		CONFIG_SYS_ISA_IO_OFFSET
 		defines the offset of register from address. It
 		depends on which part of the data bus is connected to
 		the FDC chipset. (default value 0)
 		If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and
 		CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their
 		default value.
 		if CONFIG_SYS_FDC_HW_INIT is defined, then the function
 		fdc_hw_init() is called at the beginning of the FDC
 		setup. fdc_hw_init() must be provided by the board
 		source code. It is used to make hardware dependant
 		initializations.
 - CONFIG_IDE_AHB:
 		Most IDE controllers were designed to be connected with PCI
 		interface. Only few of them were designed for AHB interface.
 		When software is doing ATA command and data transfer to
 		IDE devices through IDE-AHB controller, some additional
 		registers accessing to these kind of IDE-AHB controller
 		is requierd.
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx/82xx systems only]
 - CONFIG_SYS_INIT_RAM_ADDR:
 		Start address of memory area that can be used for
 		initial data and stack; please note that this must be
 		writable memory that is working WITHOUT special
 		initialization, i. e. you CANNOT use normal RAM which
 		will become available only after programming the
 		memory controller and running certain initialization
 		sequences.
 		U-Boot uses the following memory types:
 		- MPC8xx and MPC8260: IMMR (internal memory of the CPU)
 		- MPC824X: data cache
 		- PPC4xx:  data cache
 - CONFIG_SYS_GBL_DATA_OFFSET:
 		Offset of the initial data structure in the memory
 		area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
 		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
 		data is located at the end of the available space
 		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
 		CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
 		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
 		CONFIG_SYS_GBL_DATA_OFFSET) downward.
 	Note:
 		On the MPC824X (or other systems that use the data
 		cache for initial memory) the address chosen for
 		CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
 		point to an otherwise UNUSED address space between
 		the top of RAM and the start of the PCI space.
 - CONFIG_SYS_SIUMCR:	SIU Module Configuration (11-6)
 - CONFIG_SYS_SYPCR:	System Protection Control (11-9)
 - CONFIG_SYS_TBSCR:	Time Base Status and Control (11-26)
 - CONFIG_SYS_PISCR:	Periodic Interrupt Status and Control (11-31)
 - CONFIG_SYS_PLPRCR:	PLL, Low-Power, and Reset Control Register (15-30)
 - CONFIG_SYS_SCCR:	System Clock and reset Control Register (15-27)
 - CONFIG_SYS_OR_TIMING_SDRAM:
 		SDRAM timing
 - CONFIG_SYS_MAMR_PTA:
 		periodic timer for refresh
 - CONFIG_SYS_DER:	Debug Event Register (37-47)
 - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
   CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
   CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
   CONFIG_SYS_BR1_PRELIM:
 		Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
 - SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
   CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
   CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
 		Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
 - CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
   CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
 		Machine Mode Register and Memory Periodic Timer
 		Prescaler definitions (SDRAM timing)
 - CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]:
 		enable I2C microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [DSP2]
 - CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]:
 		enable SMC microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SMC1]
 - CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]:
 		enable SPI microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SCC4]
 - CONFIG_SYS_USE_OSCCLK:
 		Use OSCM clock mode on MBX8xx board. Be careful,
 		wrong setting might damage your board. Read
 		doc/README.MBX before setting this variable!
 - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
 		Offset of the bootmode word in DPRAM used by post
 		(Power On Self Tests). This definition overrides
 		#define'd default value in commproc.h resp.
 		cpm_8260.h.
 - CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
   CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
   CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
   CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
   CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
   CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
   CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
   CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
 		Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
 - CONFIG_PCI_DISABLE_PCIE:
 		Disable PCI-Express on systems where it is supported but not
 		required.
 - CONFIG_PCI_ENUM_ONLY
 		Only scan through and get the devices on the busses.
 		Don't do any setup work, presumably because someone or
 		something has already done it, and we don't need to do it
 		a second time.	Useful for platforms that are pre-booted
 		by coreboot or similar.
 - CONFIG_PCI_INDIRECT_BRIDGE:
 		Enable support for indirect PCI bridges.
 - CONFIG_SYS_SRIO:
 		Chip has SRIO or not
 - CONFIG_SRIO1:
 		Board has SRIO 1 port available
 - CONFIG_SRIO2:
 		Board has SRIO 2 port available
 - CONFIG_SRIO_PCIE_BOOT_MASTER
 		Board can support master function for Boot from SRIO and PCIE
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region
 - CONFIG_SYS_SRIOn_MEM_PHYS:
 		Physical Address of SRIO port 'n' memory region
 - CONFIG_SYS_SRIOn_MEM_SIZE:
 		Size of SRIO port 'n' memory region
 - CONFIG_SYS_NAND_BUSWIDTH_16BIT
 		Defined to tell the NAND controller that the NAND chip is using
 		a 16 bit bus.
 		Not all NAND drivers use this symbol.
 		Example of drivers that use it:
 		- drivers/mtd/nand/ndfc.c
 		- drivers/mtd/nand/mxc_nand.c
 - CONFIG_SYS_NDFC_EBC0_CFG
 		Sets the EBC0_CFG register for the NDFC. If not defined
 		a default value will be used.
 - CONFIG_SPD_EEPROM
 		Get DDR timing information from an I2C EEPROM. Common
 		with pluggable memory modules such as SODIMMs
   SPD_EEPROM_ADDRESS
 		I2C address of the SPD EEPROM
 - CONFIG_SYS_SPD_BUS_NUM
 		If SPD EEPROM is on an I2C bus other than the first
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 - CONFIG_SYS_DDR_RAW_TIMING
 		Get DDR timing information from other than SPD. Common with
 		soldered DDR chips onboard without SPD. DDR raw timing
 		parameters are extracted from datasheet and hard-coded into
 		header files or board specific files.
 - CONFIG_FSL_DDR_INTERACTIVE
 		Enable interactive DDR debugging. See doc/README.fsl-ddr.
 - CONFIG_SYS_83XX_DDR_USES_CS0
 		Only for 83xx systems. If specified, then DDR should
 		be configured using CS0 and CS1 instead of CS2 and CS3.
 - CONFIG_ETHER_ON_FEC[12]
 		Define to enable FEC[12] on a 8xx series processor.
 - CONFIG_FEC[12]_PHY
 		Define to the hardcoded PHY address which corresponds
 		to the given FEC; i. e.
 			#define CONFIG_FEC1_PHY 4
 		means that the PHY with address 4 is connected to FEC1
 		When set to -1, means to probe for first available.
 - CONFIG_FEC[12]_PHY_NORXERR
 		The PHY does not have a RXERR line (RMII only).
 		(so program the FEC to ignore it).
 - CONFIG_RMII
 		Enable RMII mode for all FECs.
 		Note that this is a global option, we can't
 		have one FEC in standard MII mode and another in RMII mode.
 - CONFIG_CRC32_VERIFY
 		Add a verify option to the crc32 command.
 		The syntax is:
 		=> crc32 -v <address> <count> <crc32>
 		Where address/count indicate a memory area
 		and crc32 is the correct crc32 which the
 		area should have.
 - CONFIG_LOOPW
 		Add the "loopw" memory command. This only takes effect if
 		the memory commands are activated globally (CONFIG_CMD_MEM).
 - CONFIG_MX_CYCLIC
 		Add the "mdc" and "mwc" memory commands. These are cyclic
 		"md/mw" commands.
 		Examples:
 		=> mdc.b 10 4 500
 		This command will print 4 bytes (10,11,12,13) each 500 ms.
 		=> mwc.l 100 12345678 10
 		This command will write 12345678 to address 100 all 10 ms.
 		This only takes effect if the memory commands are activated
 		globally (CONFIG_CMD_MEM).
 - CONFIG_SKIP_LOWLEVEL_INIT
 		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
 		Normally this variable MUST NOT be defined. The only
 		exception is when U-Boot is loaded (to RAM) by some
 		other boot loader or by a debugger which performs
 		these initializations itself.
 - CONFIG_SPL_BUILD
 		Modifies the behaviour of start.S when compiling a loader
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
 - CONFIG_TPL_BUILD
 		Modifies the behaviour of start.S  when compiling a loader
 		that is executed after the SPL and before the actual U-Boot.
 		It is loaded by the SPL.
 - CONFIG_SYS_MPC85XX_NO_RESETVEC
 		Only for 85xx systems. If this variable is specified, the section
 		.resetvec is not kept and the section .bootpg is placed in the
 		previous 4k of the .text section.
 - CONFIG_ARCH_MAP_SYSMEM
 		Generally U-Boot (and in particular the md command) uses
 		effective address. It is therefore not necessary to regard
 		U-Boot address as virtual addresses that need to be translated
 		to physical addresses. However, sandbox requires this, since
 		it maintains its own little RAM buffer which contains all
 		addressable memory. This option causes some memory accesses
 		to be mapped through map_sysmem() / unmap_sysmem().
 - CONFIG_USE_ARCH_MEMCPY
   CONFIG_USE_ARCH_MEMSET
 		If these options are used a optimized version of memcpy/memset will
 		be used if available. These functions may be faster under some
 		conditions but may increase the binary size.
 - CONFIG_X86_RESET_VECTOR
 		If defined, the x86 reset vector code is included. This is not
 		needed when U-Boot is running from Coreboot.
 - CONFIG_SYS_MPUCLK
 		Defines the MPU clock speed (in MHz).
 		NOTE : currently only supported on AM335x platforms.
 - CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
 		Enables the RTC32K OSC on AM33xx based plattforms
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
 loading of "firmware", which is encoded in the QE firmware binary format.
 This firmware often needs to be loaded during U-Boot booting, so macros
 are used to identify the storage device (NOR flash, SPI, etc) and the address
 within that device.
 - CONFIG_SYS_QE_FMAN_FW_ADDR
 	The address in the storage device where the firmware is located.  The
 	meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
 	is also specified.
 - CONFIG_SYS_QE_FMAN_FW_LENGTH
 	The maximum possible size of the firmware.  The firmware binary format
 	has a field that specifies the actual size of the firmware, but it
 	might not be possible to read any part of the firmware unless some
 	local storage is allocated to hold the entire firmware first.
 - CONFIG_SYS_QE_FMAN_FW_IN_NOR
 	Specifies that QE/FMAN firmware is located in NOR flash, mapped as
 	normal addressable memory via the LBC.  CONFIG_SYS_FMAN_FW_ADDR is the
 	virtual address in NOR flash.
 - CONFIG_SYS_QE_FMAN_FW_IN_NAND
 	Specifies that QE/FMAN firmware is located in NAND flash.
 	CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
 - CONFIG_SYS_QE_FMAN_FW_IN_MMC
 	Specifies that QE/FMAN firmware is located on the primary SD/MMC
 	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 - CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
 	Specifies that QE/FMAN firmware is located on the primary SPI
 	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 	Specifies that QE/FMAN firmware is located in the remote (master)
 	memory space.	CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
 	can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
 	window->master inbound window->master LAW->the ucode address in
 	master's memory space.
 Building the Software:
 ======================
 Building U-Boot has been tested in several native build environments
 and in many different cross environments. Of course we cannot support
 all possibly existing versions of cross development tools in all
 (potentially obsolete) versions. In case of tool chain problems we
 recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK)
 which is extensively used to build and test U-Boot.
 If you are not using a native environment, it is assumed that you
 have GNU cross compiling tools available in your path. In this case,
 you must set the environment variable CROSS_COMPILE in your shell.
 Note that no changes to the Makefile or any other source files are
 necessary. For example using the ELDK on a 4xx CPU, please enter:
 	$ CROSS_COMPILE=ppc_4xx-
 	$ export CROSS_COMPILE
 Note: If you wish to generate Windows versions of the utilities in
       the tools directory you can use the MinGW toolchain
       (http://www.mingw.org).  Set your HOST tools to the MinGW
       toolchain and execute 'make tools'.  For example:
        $ make HOSTCC=i586-mingw32msvc-gcc HOSTSTRIP=i586-mingw32msvc-strip tools
       Binaries such as tools/mkimage.exe will be created which can
       be executed on computers running Windows.
 U-Boot is intended to be simple to build. After installing the
 sources you must configure U-Boot for one specific board type. This
 is done by typing:
 	make NAME_config
 where "NAME_config" is the name of one of the existing configu-
 rations; see boards.cfg for supported names.
 Note: for some board special configuration names may exist; check if
       additional information is available from the board vendor; for
       instance, the TQM823L systems are available without (standard)
       or with LCD support. You can select such additional "features"
       when choosing the configuration, i. e.
       make TQM823L_config
 	- will configure for a plain TQM823L, i. e. no LCD support
       make TQM823L_LCD_config
 	- will configure for a TQM823L with U-Boot console on LCD
       etc.
 Finally, type "make all", and you should get some working U-Boot
 images ready for download to / installation on your system:
 - "u-boot.bin" is a raw binary image
 - "u-boot" is an image in ELF binary format
 - "u-boot.srec" is in Motorola S-Record format
 By default the build is performed locally and the objects are saved
 in the source directory. One of the two methods can be used to change
 this behavior and build U-Boot to some external directory:
 1. Add O= to the make command line invocations:
 	make O=/tmp/build distclean
 	make O=/tmp/build NAME_config
 	make O=/tmp/build all
 2. Set environment variable BUILD_DIR to point to the desired location:
 	export BUILD_DIR=/tmp/build
 	make distclean
 	make NAME_config
 	make all
 Note that the command line "O=" setting overrides the BUILD_DIR environment
 variable.
 Please be aware that the Makefiles assume you are using GNU make, so
 for instance on NetBSD you might need to use "gmake" instead of
 native "make".
 If the system board that you have is not listed, then you will need
 to port U-Boot to your hardware platform. To do this, follow these
 steps:
 1.  Add a new configuration option for your board to the toplevel
     "boards.cfg" file, using the existing entries as examples.
     Follow the instructions there to keep the boards in order.
 2.  Create a new directory to hold your board specific code. Add any
     files you need. In your board directory, you will need at least
     the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
 3.  Create a new configuration file "include/configs/<board>.h" for
     your board
 3.  If you're porting U-Boot to a new CPU, then also create a new
     directory to hold your CPU specific code. Add any files you need.
 4.  Run "make <board>_config" with your new name.
 5.  Type "make", and you should get a working "u-boot.srec" file
     to be installed on your target system.
 6.  Debug and solve any problems that might arise.
     [Of course, this last step is much harder than it sounds.]
 Testing of U-Boot Modifications, Ports to New Hardware, etc.:
 ==============================================================
 If you have modified U-Boot sources (for instance added a new board
 or support for new devices, a new CPU, etc.) you are expected to
 provide feedback to the other developers. The feedback normally takes
 the form of a "patch", i. e. a context diff against a certain (latest
 official or latest in the git repository) version of U-Boot sources.
 But before you submit such a patch, please verify that your modifi-
 cation did not break existing code. At least make sure that *ALL* of
 the supported boards compile WITHOUT ANY compiler warnings. To do so,
 just run the "MAKEALL" script, which will configure and build U-Boot
 for ALL supported system. Be warned, this will take a while. You can
 select which (cross) compiler to use by passing a `CROSS_COMPILE'
 environment variable to the script, i. e. to use the ELDK cross tools
 you can type
 	CROSS_COMPILE=ppc_8xx- MAKEALL
 or to build on a native PowerPC system you can type
 	CROSS_COMPILE=' ' MAKEALL
 When using the MAKEALL script, the default behaviour is to build
 U-Boot in the source directory. This location can be changed by
 setting the BUILD_DIR environment variable. Also, for each target
 built, the MAKEALL script saves two log files (<target>.ERR and
 <target>.MAKEALL) in the <source dir>/LOG directory. This default
 location can be changed by setting the MAKEALL_LOGDIR environment
 variable. For example:
 	export BUILD_DIR=/tmp/build
 	export MAKEALL_LOGDIR=/tmp/log
 	CROSS_COMPILE=ppc_8xx- MAKEALL
 With the above settings build objects are saved in the /tmp/build,
 log files are saved in the /tmp/log and the source tree remains clean
 during the whole build process.
 See also "U-Boot Porting Guide" below.
 Monitor Commands - Overview:
 ============================
 go	- start application at address 'addr'
 run	- run commands in an environment variable
 bootm	- boot application image from memory
 bootp	- boot image via network using BootP/TFTP protocol
 bootz   - boot zImage from memory
 tftpboot- boot image via network using TFTP protocol
 	       and env variables "ipaddr" and "serverip"
 	       (and eventually "gatewayip")
 tftpput - upload a file via network using TFTP protocol
 rarpboot- boot image via network using RARP/TFTP protocol
 diskboot- boot from IDE devicebootd   - boot default, i.e., run 'bootcmd'
 loads	- load S-Record file over serial line
 loadb	- load binary file over serial line (kermit mode)
 md	- memory display
 mm	- memory modify (auto-incrementing)
 nm	- memory modify (constant address)
 mw	- memory write (fill)
 cp	- memory copy
 cmp	- memory compare
 crc32	- checksum calculation
 i2c	- I2C sub-system
 sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
 setenv	- set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection
 erase	- erase FLASH memory
 flinfo	- print FLASH memory information
 nand	- NAND memory operations (see doc/README.nand)
 bdinfo	- print Board Info structure
 iminfo	- print header information for application image
 coninfo - print console devices and informations
 ide	- IDE sub-system
 loop	- infinite loop on address range
 loopw	- infinite write loop on address range
 mtest	- simple RAM test
 icache	- enable or disable instruction cache
 dcache	- enable or disable data cache
 reset	- Perform RESET of the CPU
 echo	- echo args to console
 version - print monitor version
 help	- print online help
 ?	- alias for 'help'
 Monitor Commands - Detailed Description:
 ========================================
 TODO.
 For now: just type "help <command>".
 Environment Variables:
 ======================
 U-Boot supports user configuration using Environment Variables which
 can be made persistent by saving to Flash memory.
 Environment Variables are set using "setenv", printed using
 "printenv", and saved to Flash using "saveenv". Using "setenv"
 without a value can be used to delete a variable from the
 environment. As long as you don't save the environment you are
 working with an in-memory copy. In case the Flash area containing the
 environment is erased by accident, a default environment is provided.
 Some configuration options can be set using Environment Variables.
 List of environment variables (most likely not complete):
   baudrate	- see CONFIG_BAUDRATE
   bootdelay	- see CONFIG_BOOTDELAY
   bootcmd	- see CONFIG_BOOTCOMMAND
   bootargs	- Boot arguments when booting an RTOS image
   bootfile	- Name of the image to load with TFTP
   bootm_low	- Memory range available for image processing in the bootm
 		  command can be restricted. This variable is given as
 		  a hexadecimal number and defines lowest address allowed
 		  for use by the bootm command. See also "bootm_size"
 		  environment variable. Address defined by "bootm_low" is
 		  also the base of the initial memory mapping for the Linux
 		  kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
 		  bootm_mapsize.
   bootm_mapsize - Size of the initial memory mapping for the Linux kernel.
 		  This variable is given as a hexadecimal number and it
 		  defines the size of the memory region starting at base
 		  address bootm_low that is accessible by the Linux kernel
 		  during early boot.  If unset, CONFIG_SYS_BOOTMAPSZ is used
 		  as the default value if it is defined, and bootm_size is
 		  used otherwise.
   bootm_size	- Memory range available for image processing in the bootm
 		  command can be restricted. This variable is given as
 		  a hexadecimal number and defines the size of the region
 		  allowed for use by the bootm command. See also "bootm_low"
 		  environment variable.
   updatefile	- Location of the software update file on a TFTP server, used
 		  by the automatic software update feature. Please refer to
 		  documentation in doc/README.update for more details.
   autoload	- if set to "no" (any string beginning with 'n'),
 		  "bootp" will just load perform a lookup of the
 		  configuration from the BOOTP server, but not try to
 		  load any image using TFTP
   autostart	- if set to "yes", an image loaded using the "bootp",
 		  "rarpboot", "tftpboot" or "diskboot" commands will
 		  be automatically started (by internally calling
 		  "bootm")
 		  If set to "no", a standalone image passed to the
 		  "bootm" command will be copied to the load address
 		  (and eventually uncompressed), but NOT be started.
 		  This can be used to load and uncompress arbitrary
 		  data.
   fdt_high	- if set this restricts the maximum address that the
 		  flattened device tree will be copied into upon boot.
 		  For example, if you have a system with 1 GB memory
 		  at physical address 0x10000000, while Linux kernel
 		  only recognizes the first 704 MB as low memory, you
 		  may need to set fdt_high as 0x3C000000 to have the
 		  device tree blob be copied to the maximum address
 		  of the 704 MB low memory, so that Linux kernel can
 		  access it during the boot procedure.
 		  If this is set to the special value 0xFFFFFFFF then
 		  the fdt will not be copied at all on boot.  For this
 		  to work it must reside in writable memory, have
 		  sufficient padding on the end of it for u-boot to
 		  add the information it needs into it, and the memory
 		  must be accessible by the kernel.
   fdtcontroladdr- if set this is the address of the control flattened
 		  device tree used by U-Boot when CONFIG_OF_CONTROL is
 		  defined.
   i2cfast	- (PPC405GP|PPC405EP only)
 		  if set to 'y' configures Linux I2C driver for fast
 		  mode (400kHZ). This environment variable is used in
 		  initialization code. So, for changes to be effective
 		  it must be saved and board must be reset.
   initrd_high	- restrict positioning of initrd images:
 		  If this variable is not set, initrd images will be
 		  copied to the highest possible address in RAM; this
 		  is usually what you want since it allows for
 		  maximum initrd size. If for some reason you want to
 		  make sure that the initrd image is loaded below the
 		  CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
 		  variable to a value of "no" or "off" or "0".
 		  Alternatively, you can set it to a maximum upper
 		  address to use (U-Boot will still check that it
 		  does not overwrite the U-Boot stack and data).
 		  For instance, when you have a system with 16 MB
 		  RAM, and want to reserve 4 MB from use by Linux,
 		  you can do this by adding "mem=12M" to the value of
 		  the "bootargs" variable. However, now you must make
 		  sure that the initrd image is placed in the first
 		  12 MB as well - this can be done with
 		  setenv initrd_high 00c00000
 		  If you set initrd_high to 0xFFFFFFFF, this is an
 		  indication to U-Boot that all addresses are legal
 		  for the Linux kernel, including addresses in flash
 		  memory. In this case U-Boot will NOT COPY the
 		  ramdisk at all. This may be useful to reduce the
 		  boot time on your system, but requires that this
 		  feature is supported by your Linux kernel.
   ipaddr	- IP address; needed for tftpboot command
   loadaddr	- Default load address for commands like "bootp",
 		  "rarpboot", "tftpboot", "loadb" or "diskboot"
   loads_echo	- see CONFIG_LOADS_ECHO
   serverip	- TFTP server IP address; needed for tftpboot command
   bootretry	- see CONFIG_BOOT_RETRY_TIME
   bootdelaykey	- see CONFIG_AUTOBOOT_DELAY_STR
   bootstopkey	- see CONFIG_AUTOBOOT_STOP_STR
   ethprime	- controls which interface is used first.
   ethact	- controls which interface is currently active.
 		  For example you can do the following
 		  => setenv ethact FEC
 		  => ping 192.168.0.1 # traffic sent on FEC
 		  => setenv ethact SCC
 		  => ping 10.0.0.1 # traffic sent on SCC
   ethrotate	- When set to "no" U-Boot does not go through all
 		  available network interfaces.
 		  It just stays at the currently selected interface.
   netretry	- When set to "no" each network operation will
 		  either succeed or fail without retrying.
 		  When set to "once" the network operation will
 		  fail when all the available network interfaces
 		  are tried once without success.
 		  Useful on scripts which control the retry operation
 		  themselves.
   npe_ucode	- set load address for the NPE microcode
   silent_linux  - If set then linux will be told to boot silently, by
 		  changing the console to be empty. If "yes" it will be
 		  made silent. If "no" it will not be made silent. If
 		  unset, then it will be made silent if the U-Boot console
 		  is silent.
   tftpsrcport	- If this is set, the value is used for TFTP's
 		  UDP source port.
   tftpdstport	- If this is set, the value is used for TFTP's UDP
 		  destination port instead of the Well Know Port 69.
   tftpblocksize - Block size to use for TFTP transfers; if not set,
 		  we use the TFTP server's default block size
   tftptimeout	- Retransmission timeout for TFTP packets (in milli-
 		  seconds, minimum value is 1000 = 1 second). Defines
 		  when a packet is considered to be lost so it has to
 		  be retransmitted. The default is 5000 = 5 seconds.
 		  Lowering this value may make downloads succeed
 		  faster in networks with high packet loss rates or
 		  with unreliable TFTP servers.
   vlan		- When set to a value < 4095 the traffic over
 		  Ethernet is encapsulated/received over 802.1q
 		  VLAN tagged frames.
 The following image location variables contain the location of images
 used in booting. The "Image" column gives the role of the image and is
 not an environment variable name. The other columns are environment
 variable names. "File Name" gives the name of the file on a TFTP
 server, "RAM Address" gives the location in RAM the image will be
 loaded to, and "Flash Location" gives the image's address in NOR
 flash or offset in NAND flash.
 *Note* - these variables don't have to be defined for all boards, some
 boards currenlty use other variables for these purposes, and some
 boards use these variables for other purposes.
 Image		    File Name	     RAM Address       Flash Location
 -----		    ---------	     -----------       --------------
 u-boot		    u-boot	     u-boot_addr_r     u-boot_addr
 Linux kernel	    bootfile	     kernel_addr_r     kernel_addr
 device tree blob    fdtfile	     fdt_addr_r	       fdt_addr
 ramdisk		    ramdiskfile	     ramdisk_addr_r    ramdisk_addr
 The following environment variables may be used and automatically
 updated by the network boot commands ("bootp" and "rarpboot"),
 depending the information provided by your boot server:
   bootfile	- see above
   dnsip		- IP address of your Domain Name Server
   dnsip2	- IP address of your secondary Domain Name Server
   gatewayip	- IP address of the Gateway (Router) to use
   hostname	- Target hostname
   ipaddr	- see above
   netmask	- Subnet Mask
   rootpath	- Pathname of the root filesystem on the NFS server
   serverip	- see above
 There are two special Environment Variables:
   serial#	- contains hardware identification information such
 		  as type string and/or serial number
   ethaddr	- Ethernet address
 These variables can be set only once (usually during manufacturing of
 the board). U-Boot refuses to delete or overwrite these variables
 once they have been set once.
 Further special Environment Variables:
   ver		- Contains the U-Boot version string as printed
 		  with the "version" command. This variable is
 		  readonly (see CONFIG_VERSION_VARIABLE).
 Please note that changes to some configuration parameters may take
 only effect after the next boot (yes, that's just like Windoze :-).
 Callback functions for environment variables:
 ---------------------------------------------
 For some environment variables, the behavior of u-boot needs to change
 when their values are changed.  This functionailty allows functions to
 be associated with arbitrary variables.  On creation, overwrite, or
 deletion, the callback will provide the opportunity for some side
 effect to happen or for the change to be rejected.
 The callbacks are named and associated with a function using the
 U_BOOT_ENV_CALLBACK macro in your board or driver code.
 These callbacks are associated with variables in one of two ways.  The
 static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
 in the board configuration to a string that defines a list of
 associations.  The list must be in the following format:
 	entry = variable_name[:callback_name]
 	list = entry[,list]
 If the callback name is not specified, then the callback is deleted.
 Spaces are also allowed anywhere in the list.
 Callbacks can also be associated by defining the ".callbacks" variable
 with the same list format above.  Any association in ".callbacks" will
 override any association in the static list. You can define
 CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
 ".callbacks" envirnoment variable in the default or embedded environment.
 Command Line Parsing:
 =====================
 There are two different command line parsers available with U-Boot:
 the old "simple" one, and the much more powerful "hush" shell:
 Old, simple command line parser:
 --------------------------------
 - supports environment variables (through setenv / saveenv commands)
 - several commands on one line, separated by ';'
 - variable substitution using "... ${name} ..." syntax
 - special characters ('$', ';') can be escaped by prefixing with '\',
   for example:
 	setenv bootcmd bootm \${address}
 - You can also escape text by enclosing in single apostrophes, for example:
 	setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off'
 Hush shell:
 -----------
 - similar to Bourne shell, with control structures like
   if...then...else...fi, for...do...done; while...do...done,
   until...do...done, ...
 - supports environment ("global") variables (through setenv / saveenv
   commands) and local shell variables (through standard shell syntax
   "name=value"); only environment variables can be used with "run"
   command
 General rules:
 --------------
 (1) If a command line (or an environment variable executed by a "run"
     command) contains several commands separated by semicolon, and
     one of these commands fails, then the remaining commands will be
     executed anyway.
 (2) If you execute several variables with one call to run (i. e.
     calling run with a list of variables as arguments), any failing
     command will cause "run" to terminate, i. e. the remaining
     variables are not executed.
 Note for Redundant Ethernet Interfaces:
 =======================================
 Some boards come with redundant Ethernet interfaces; U-Boot supports
 such configurations and is capable of automatic selection of a
 "working" interface when needed. MAC assignment works as follows:
 Network interfaces are numbered eth0, eth1, eth2, ... Corresponding
 MAC addresses can be stored in the environment as "ethaddr" (=>eth0),
 "eth1addr" (=>eth1), "eth2addr", ...
 If the network interface stores some valid MAC address (for instance
 in SROM), this is used as default address if there is NO correspon-
 ding setting in the environment; if the corresponding environment
 variable is set, this overrides the settings in the card; that means:
 o If the SROM has a valid MAC address, and there is no address in the
   environment, the SROM's address is used.
 o If there is no valid address in the SROM, and a definition in the
   environment exists, then the value from the environment variable is
   used.
 o If both the SROM and the environment contain a MAC address, and
   both addresses are the same, this MAC address is used.
 o If both the SROM and the environment contain a MAC address, and the
   addresses differ, the value from the environment is used and a
   warning is printed.
 o If neither SROM nor the environment contain a MAC address, an error
   is raised.
 If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
 will be programmed into hardware as part of the initialization process.	 This
 may be skipped by setting the appropriate 'ethmacskip' environment variable.
 The naming convention is as follows:
 "ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc.
 Image Formats:
 ==============
 U-Boot is capable of booting (and performing other auxiliary operations on)
 images in two formats:
 New uImage format (FIT)
 -----------------------
 Flexible and powerful format based on Flattened Image Tree -- FIT (similar
 to Flattened Device Tree). It allows the use of images with multiple
 components (several kernels, ramdisks, etc.), with contents protected by
 SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
 Old uImage format
 -----------------
 Old image format is based on binary files which can be basically anything,
 preceded by a special header; see the definitions in include/image.h for
 details; basically, the header defines the following image properties:
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
   LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
   IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
 * Image Name
 * Image Timestamp
 The header is marked by a special Magic Number, and both the header
 and the data portions of the image are secured against corruption by
 CRC32 checksums.
 Linux Support:
 ==============
 Although U-Boot should support any OS or standalone application
 easily, the main focus has always been on Linux during the design of
 U-Boot.
 U-Boot includes many features that so far have been part of some
 special "boot loader" code within the Linux kernel. Also, any
 "initrd" images to be used are no longer part of one big Linux image;
 instead, kernel and "initrd" are separate images. This implementation
 serves several purposes:
 - the same features can be used for other OS or standalone
   applications (for instance: using compressed images to reduce the
   Flash memory footprint)
 - it becomes much easier to port new Linux kernel versions because
   lots of low-level, hardware dependent stuff are done by U-Boot
 - the same Linux kernel image can now be used with different "initrd"
   images; of course this also means that different kernel images can
   be run with the same "initrd". This makes testing easier (you don't
   have to build a new "zImage.initrd" Linux image when you just
   change a file in your "initrd"). Also, a field-upgrade of the
   software is easier now.
 Linux HOWTO:
 ============
 Porting Linux to U-Boot based systems:
 ---------------------------------------
 U-Boot cannot save you from doing all the necessary modifications to
 configure the Linux device drivers for use with your target hardware
 (no, we don't intend to provide a full virtual machine interface to
 Linux :-).
 But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot).
 Just make sure your machine specific header file (for instance
 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
 Information structure as we define in include/asm-<arch>/u-boot.h,
 and make sure that your definition of IMAP_ADDR uses the same value
 as your U-Boot configuration in CONFIG_SYS_IMMR.
 Configuring the Linux kernel:
 -----------------------------
 No specific requirements for U-Boot. Make sure you have some root
 device (initial ramdisk, NFS) for your target system.
 Building a Linux Image:
 -----------------------
 With U-Boot, "normal" build targets like "zImage" or "bzImage" are
 not used. If you use recent kernel source, a new build target
 "uImage" will exist which automatically builds an image usable by
 U-Boot. Most older kernels also have support for a "pImage" target,
 which was introduced for our predecessor project PPCBoot and uses a
 100% compatible format.
 Example:
 	make TQM850L_config
 	make oldconfig
 	make dep
 	make uImage
 The "uImage" build target uses a special tool (in 'tools/mkimage') to
 encapsulate a compressed Linux kernel image with header	 information,
 CRC32 checksum etc. for use with U-Boot. This is what we are doing:
 * build a standard "vmlinux" kernel image (in ELF binary format):
 * convert the kernel into a raw binary image:
 	${CROSS_COMPILE}-objcopy -O binary \
 				 -R .note -R .comment \
 				 -S vmlinux linux.bin
 * compress the binary image:
 	gzip -9 linux.bin
 * package compressed binary image for U-Boot:
 	mkimage -A ppc -O linux -T kernel -C gzip \
 		-a 0 -e 0 -n "Linux Kernel Image" \
 		-d linux.bin.gz uImage
 The "mkimage" tool can also be used to create ramdisk images for use
 with U-Boot, either separated from the Linux kernel image, or
 combined into one file. "mkimage" encapsulates the images with a 64
 byte header containing information about target architecture,
 operating system, image type, compression method, entry points, time
 stamp, CRC32 checksums, etc.
 "mkimage" can be called in two ways: to verify existing images and
 print the header information, or to build new images.
 In the first form (with "-l" option) mkimage lists the information
 contained in the header of an existing U-Boot image; this includes
 checksum verification:
 	tools/mkimage -l image
 	  -l ==> list image header information
 The second form (with "-d" option) is used to build a U-Boot image
 from a "data file" which is used as image payload:
 	tools/mkimage -A arch -O os -T type -C comp -a addr -e ep \
 		      -n name -d data_file image
 	  -A ==> set architecture to 'arch'
 	  -O ==> set operating system to 'os'
 	  -T ==> set image type to 'type'
 	  -C ==> set compression type 'comp'
 	  -a ==> set load address to 'addr' (hex)
 	  -e ==> set entry point to 'ep' (hex)
 	  -n ==> set image name to 'name'
 	  -d ==> use image data from 'datafile'
 Right now, all Linux kernels for PowerPC systems use the same load
 address (0x00000000), but the entry point address depends on the
 kernel version:
 - 2.2.x kernels have the entry point at 0x0000000C,
 - 2.3.x and later kernels have the entry point at 0x00000000.
 So a typical call to build a U-Boot image would read:
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
 	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \
 	> examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (gzip compressed)
 	Data Size:    335725 Bytes = 327.86 kB = 0.32 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 To verify the contents of the image (or check for corruption):
 	-> tools/mkimage -l examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (gzip compressed)
 	Data Size:    335725 Bytes = 327.86 kB = 0.32 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 NOTE: for embedded systems where boot time is critical you can trade
 speed for memory and install an UNCOMPRESSED image instead: this
 needs more space in Flash, but boots much faster since it does not
 need to be uncompressed:
 	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C none -a 0 -e 0 \
 	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \
 	> examples/uImage.TQM850L-uncompressed
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (uncompressed)
 	Data Size:    792160 Bytes = 773.59 kB = 0.76 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 Similar you can build U-Boot images from a 'ramdisk.image.gz' file
 when your kernel is intended to use an initial ramdisk:
 	-> tools/mkimage -n 'Simple Ramdisk Image' \
 	> -A ppc -O linux -T ramdisk -C gzip \
 	> -d /LinuxPPC/images/SIMPLE-ramdisk.image.gz examples/simple-initrd
 	Image Name:   Simple Ramdisk Image
 	Created:      Wed Jan 12 14:01:50 2000
 	Image Type:   PowerPC Linux RAMDisk Image (gzip compressed)
 	Data Size:    566530 Bytes = 553.25 kB = 0.54 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i"
 option performs the converse operation of the mkimage's second form (the "-d"
 option). Given an image built by mkimage, the dumpimage extracts a "data file"
 from the image:
 	tools/dumpimage -i image -p position data_file
 	  -i ==> extract from the 'image' a specific 'data_file', \
 	   indexed by 'position'
 Installing a Linux Image:
 -------------------------
 To downloading a U-Boot image over the serial (console) interface,
 you must convert the image to S-Record format:
 	objcopy -I binary -O srec examples/image examples/image.srec
 The 'objcopy' does not understand the information in the U-Boot
 image header, so the resulting S-Record file will be relative to
 address 0x00000000. To load it to a given address, you need to
 specify the target address as 'offset' parameter with the 'loads'
 command.
 Example: install the image to address 0x40100000 (which on the
 TQM8xxL is in the first Flash bank):
 	=> erase 40100000 401FFFFF
 	.......... done
 	Erased 8 sectors
 	=> loads 40100000
 	## Ready for S-Record download ...
 	~>examples/image.srec
 	1 2 3 4 5 6 7 8 9 10 11 12 13 ...
 	...
 	15989 15990 15991 15992
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00000000
 You can check the success of the download using the 'iminfo' command;
 this includes a checksum verification so you can be sure no data
 corruption happened:
 	=> imi 40100000
 	## Checking Image at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 Boot Linux:
 -----------
 The "bootm" command is used to boot an application that is stored in
 memory (RAM or Flash). In case of a Linux kernel image, the contents
 of the "bootargs" environment variable is passed to the kernel as
 parameters. You can check and modify this variable using the
 "printenv" and "setenv" commands:
 	=> printenv bootargs
 	bootargs=root=/dev/ram
 	=> setenv bootargs root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	=> printenv bootargs
 	bootargs=root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	=> bootm 40020000
 	## Booting Linux kernel at 40020000 ...
 	   Image Name:	 2.2.13 for NFS on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 381681 Bytes = 372 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	   Uncompressing Kernel Image ... OK
 	Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:35:17 MEST 2000
 	Boot arguments: root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	time_init: decrementer frequency = 187500000/60
 	Calibrating delay loop... 49.77 BogoMIPS
 	Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000]
 	...
 If you want to boot a Linux kernel with initial RAM disk, you pass
 the memory addresses of both the kernel and the initrd image (PPBCOOT
 format!) to the "bootm" command:
 	=> imi 40100000 40200000
 	## Checking Image at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	## Checking Image at 40200000 ...
 	   Image Name:	 Simple Ramdisk Image
 	   Image Type:	 PowerPC Linux RAMDisk Image (gzip compressed)
 	   Data Size:	 566530 Bytes = 553 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 00000000
 	   Verifying Checksum ... OK
 	=> bootm 40100000 40200000
 	## Booting Linux kernel at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	   Uncompressing Kernel Image ... OK
 	## Loading RAMDisk Image at 40200000 ...
 	   Image Name:	 Simple Ramdisk Image
 	   Image Type:	 PowerPC Linux RAMDisk Image (gzip compressed)
 	   Data Size:	 566530 Bytes = 553 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 00000000
 	   Verifying Checksum ... OK
 	   Loading Ramdisk ... OK
 	Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:32:08 MEST 2000
 	Boot arguments: root=/dev/ram
 	time_init: decrementer frequency = 187500000/60
 	Calibrating delay loop... 49.77 BogoMIPS
 	...
 	RAMDISK: Compressed image found at block 0
 	VFS: Mounted root (ext2 filesystem).
 	bash#
 Boot Linux and pass a flat device tree:
 -----------
 First, U-Boot must be compiled with the appropriate defines. See the section
 titled "Linux Kernel Interface" above for a more in depth explanation. The
 following is an example of how to start a kernel and pass an updated
 flat device tree:
 => print oftaddr
 oftaddr=0x300000
 => print oft
 oft=oftrees/mpc8540ads.dtb
 => tftp $oftaddr $oft
 Speed: 1000, full duplex
 Using TSEC0 device
 TFTP from server 192.168.1.1; our IP address is 192.168.1.101
 Filename 'oftrees/mpc8540ads.dtb'.
 Load address: 0x300000
 Loading: #
 done
 Bytes transferred = 4106 (100a hex)
 => tftp $loadaddr $bootfile
 Speed: 1000, full duplex
 Using TSEC0 device
 TFTP from server 192.168.1.1; our IP address is 192.168.1.2
 Filename 'uImage'.
 Load address: 0x200000
 Loading:############
 done
 Bytes transferred = 1029407 (fb51f hex)
 => print loadaddr
 loadaddr=200000
 => print oftaddr
 oftaddr=0x300000
 => bootm $loadaddr - $oftaddr
 ## Booting image at 00200000 ...
    Image Name:	 Linux-2.6.17-dirty
    Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
    Data Size:	 1029343 Bytes = 1005.2 kB
    Load Address: 00000000
    Entry Point:	 00000000
    Verifying Checksum ... OK
    Uncompressing Kernel Image ... OK
 Booting using flat device tree at 0x300000
 Using MPC85xx ADS machine description
 Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
 [snip]
 More About U-Boot Image Types:
 ------------------------------
 U-Boot supports the following image types:
    "Standalone Programs" are directly runnable in the environment
 	provided by U-Boot; it is expected that (if they behave
 	well) you can continue to work in U-Boot after return from
 	the Standalone Program.
    "OS Kernel Images" are usually images of some Embedded OS which
 	will take over control completely. Usually these programs
 	will install their own set of exception handlers, device
 	drivers, set up the MMU, etc. - this means, that you cannot
 	expect to re-enter U-Boot except by resetting the CPU.
    "RAMDisk Images" are more or less just data blocks, and their
 	parameters (address, size) are passed to an OS kernel that is
 	being started.
    "Multi-File Images" contain several images, typically an OS
 	(Linux) kernel image and one or more data images like
 	RAMDisks. This construct is useful for instance when you want
 	to boot over the network using BOOTP etc., where the boot
 	server provides just a single image file, but you want to get
 	for instance an OS kernel and a RAMDisk image.
 	"Multi-File Images" start with a list of image sizes, each
 	image size (in bytes) specified by an "uint32_t" in network
 	byte order. This list is terminated by an "(uint32_t)0".
 	Immediately after the terminating 0 follow the images, one by
 	one, all aligned on "uint32_t" boundaries (size rounded up to
 	a multiple of 4 bytes).
    "Firmware Images" are binary images containing firmware (like
 	U-Boot or FPGA images) which usually will be programmed to
 	flash memory.
    "Script files" are command sequences that will be executed by
 	U-Boot's command interpreter; this feature is especially
 	useful when you configure U-Boot to use a real shell (hush)
 	as command interpreter.
 Booting the Linux zImage:
 -------------------------
 On some platforms, it's possible to boot Linux zImage. This is done
 using the "bootz" command. The syntax of "bootz" command is the same
 as the syntax of "bootm" command.
 Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
 kernel with raw initrd images. The syntax is slightly different, the
 address of the initrd must be augmented by it's size, in the following
 format: "<initrd addres>:<initrd size>".
 Standalone HOWTO:
 =================
 One of the features of U-Boot is that you can dynamically load and
 run "standalone" applications, which can use some resources of
 U-Boot like console I/O functions or interrupt services.
 Two simple examples are included with the sources:
 "Hello World" Demo:
 -------------------
 'examples/hello_world.c' contains a small "Hello World" Demo
 application; it is automatically compiled when you build U-Boot.
 It's configured to run at address 0x00040004, so you can play with it
 like that:
 	=> loads
 	## Ready for S-Record download ...
 	~>examples/hello_world.srec
 	1 2 3 4 5 6 7 8 9 10 11 ...
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00040004
 	=> go 40004 Hello World! This is a test.
 	## Starting application at 0x00040004 ...
 	Hello World
 	argc = 7
 	argv[0] = "40004"
 	argv[1] = "Hello"
 	argv[2] = "World!"
 	argv[3] = "This"
 	argv[4] = "is"
 	argv[5] = "a"
 	argv[6] = "test."
 	argv[7] = "<NULL>"
 	Hit any key to exit ...
 	## Application terminated, rc = 0x0
 Another example, which demonstrates how to register a CPM interrupt
 handler with the U-Boot code, can be found in 'examples/timer.c'.
 Here, a CPM timer is set up to generate an interrupt every second.
 The interrupt service routine is trivial, just printing a '.'
 character, but this is just a demo program. The application can be
 controlled by the following keys:
 	? - print current values og the CPM Timer registers
 	b - enable interrupts and start timer
 	e - stop timer and disable interrupts
 	q - quit application
 	=> loads
 	## Ready for S-Record download ...
 	~>examples/timer.srec
 	1 2 3 4 5 6 7 8 9 10 11 ...
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00040004
 	=> go 40004
 	## Starting application at 0x00040004 ...
 	TIMERS=0xfff00980
 	Using timer 1
 	  tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0xfff009b0
 Hit 'b':
 	[q, b, e, ?] Set interval 1000000 us
 	Enabling timer
 Hit '?':
 	[q, b, e, ?] ........
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0
 Hit 'e':
 	[q, b, e, ?] ...Stopping timer
 Hit 'q':
 	[q, b, e, ?] ## Application terminated, rc = 0x0
 Minicom warning:
 ================
 Over time, many people have reported problems when trying to use the
 "minicom" terminal emulation program for serial download. I (wd)
 consider minicom to be broken, and recommend not to use it. Under
 Unix, I recommend to use C-Kermit for general purpose use (and
 especially for kermit binary protocol download ("loadb" command), and
 use "cu" for S-Record download ("loads" command).  See
 http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
 for help with kermit.
 Nevertheless, if you absolutely want to use it try adding this
 configuration to your "File transfer protocols" section:
 	   Name	   Program			Name U/D FullScr IO-Red. Multi
 	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
 	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N
 NetBSD Notes:
 =============
 Starting at version 0.9.2, U-Boot supports NetBSD both as host
 (build U-Boot) and target system (boots NetBSD/mpc8xx).
 Building requires a cross environment; it is known to work on
 NetBSD/i386 with the cross-powerpc-netbsd-1.3 package (you will also
 need gmake since the Makefiles are not compatible with BSD make).
 Note that the cross-powerpc package does not install include files;
 attempting to build U-Boot will fail because <machine/ansi.h> is
 missing.  This file has to be installed and patched manually:
 	# cd /usr/pkg/cross/powerpc-netbsd/include
 	# mkdir powerpc
 	# ln -s powerpc machine
 	# cp /usr/src/sys/arch/powerpc/include/ansi.h powerpc/ansi.h
 	# ${EDIT} powerpc/ansi.h	## must remove __va_list, _BSD_VA_LIST
 Native builds *don't* work due to incompatibilities between native
 and U-Boot include files.
 Booting assumes that (the first part of) the image booted is a
 stage-2 loader which in turn loads and then invokes the kernel
 proper. Loader sources will eventually appear in the NetBSD source
 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the
 meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz
 Implementation Internals:
 =========================
 The following is not intended to be a complete description of every
 implementation detail. However, it should help to understand the
 inner workings of U-Boot and make it easier to port it to custom
 hardware.
 Initial Stack, Global Data:
 ---------------------------
 The implementation of U-Boot is complicated by the fact that U-Boot
 starts running out of ROM (flash memory), usually without access to
 system RAM (because the memory controller is not initialized yet).
 This means that we don't have writable Data or BSS segments, and BSS
 is not initialized as zero. To be able to get a C environment working
 at all, we have to allocate at least a minimal stack. Implementation
 options for this are defined and restricted by the CPU used: Some CPU
 models provide on-chip memory (like the IMMR area on MPC8xx and
 MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.
 	Chris Hallinan posted a good summary of these issues to the
 	U-Boot mailing list:
 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
 	From: "Chris Hallinan" <clh@net1plus.com>
 	Date: Mon, 10 Feb 2003 16:43:46 -0500 (22:43 MET)
 	...
 	Correct me if I'm wrong, folks, but the way I understand it
 	is this: Using DCACHE as initial RAM for Stack, etc, does not
 	require any physical RAM backing up the cache. The cleverness
 	is that the cache is being used as a temporary supply of
 	necessary storage before the SDRAM controller is setup. It's
 	beyond the scope of this list to explain the details, but you
 	can see how this works by studying the cache architecture and
 	operation in the architecture and processor-specific manuals.
 	OCM is On Chip Memory, which I believe the 405GP has 4K. It
 	is another option for the system designer to use as an
 	initial stack/RAM area prior to SDRAM being available. Either
 	option should work for you. Using CS 4 should be fine if your
 	board designers haven't used it for something that would
 	cause you grief during the initial boot! It is frequently not
 	used.
 	CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
 	with your processor/board/system design. The default value
 	you will find in any recent u-boot distribution in
 	walnut.h should work for you. I'd set it to a value larger
 	than your SDRAM module. If you have a 64MB SDRAM module, set
 	it above 400_0000. Just make sure your board has no resources
 	that are supposed to respond to that address! That code in
 	start.S has been around a while and should work as is when
 	you get the config right.
 	-Chris Hallinan
 	DS4.COM, Inc.
 It is essential to remember this, since it has some impact on the C
 code for the initialization procedures:
 * Initialized global data (data segment) is read-only. Do not attempt
   to write it.
 * Do not use any uninitialized global data (or implicitely initialized
   as zero data - BSS segment) at all - this is undefined, initiali-
   zation is performed later (when relocating to RAM).
 * Stack space is very limited. Avoid big data buffers or things like
   that.
 Having only the stack as writable memory limits means we cannot use
 normal global data to share information beween the code. But it
 turned out that the implementation of U-Boot can be greatly
 simplified by making a global data structure (gd_t) available to all
 functions. We could pass a pointer to this data as argument to _all_
 functions, but this would bloat the code. Instead we use a feature of
 the GCC compiler (Global Register Variables) to share the data: we
 place a pointer (gd) to the global data into a register which we
 reserve for this purpose.
 When choosing a register for such a purpose we are restricted by the
 relevant  (E)ABI  specifications for the current architecture, and by
 GCC's implementation.
 For PowerPC, the following registers have specific use:
 	R1:	stack pointer
 	R2:	reserved for system use
 	R3-R4:	parameter passing and return values
 	R5-R10: parameter passing
 	R13:	small data area pointer
 	R30:	GOT pointer
 	R31:	frame pointer
 	(U-Boot also uses R12 as internal GOT pointer. r12
 	is a volatile register so r12 needs to be reset when
 	going back and forth between asm and C)
     ==> U-Boot will use R2 to hold a pointer to the global data
     Note: on PPC, we could use a static initializer (since the
     address of the global data structure is known at compile time),
     but it turned out that reserving a register results in somewhat
     smaller code - although the code savings are not that big (on
     average for all boards 752 bytes for the whole U-Boot image,
     624 text + 127 data).
 On Blackfin, the normal C ABI (except for P3) is followed as documented here:
 	http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
     ==> U-Boot will use P3 to hold a pointer to the global data
 On ARM, the following registers are used:
 	R0:	function argument word/integer result
 	R1-R3:	function argument word
 	R9:	platform specific
 	R10:	stack limit (used only if stack checking is enabled)
 	R11:	argument (frame) pointer
 	R12:	temporary workspace
 	R13:	stack pointer
 	R14:	link register
 	R15:	program counter
     ==> U-Boot will use R9 to hold a pointer to the global data
     Note: on ARM, only R_ARM_RELATIVE relocations are supported.
 On Nios II, the ABI is documented here:
 	http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
     ==> U-Boot will use gp to hold a pointer to the global data
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 On NDS32, the following registers are used:
 	R0-R1:	argument/return
 	R2-R5:	argument
 	R15:	temporary register for assembler
 	R16:	trampoline register
 	R28:	frame pointer (FP)
 	R29:	global pointer (GP)
 	R30:	link register (LP)
 	R31:	stack pointer (SP)
 	PC:	program counter (PC)
     ==> U-Boot will use R10 to hold a pointer to the global data
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 Memory Management:
 ------------------
 U-Boot runs in system state and uses physical addresses, i.e. the
 MMU is not used either for address mapping nor for memory protection.
 The available memory is mapped to fixed addresses using the memory
 controller. In this process, a contiguous block is formed for each
 memory type (Flash, SDRAM, SRAM), even when it consists of several
 physical memory banks.
 U-Boot is installed in the first 128 kB of the first Flash bank (on
 TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After
 booting and sizing and initializing DRAM, the code relocates itself
 to the upper end of DRAM. Immediately below the U-Boot code some
 memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN
 configuration setting]. Below that, a structure with global Board
 Info data is placed, followed by the stack (growing downward).
 Additionally, some exception handler code is copied to the low 8 kB
 of DRAM (0x00000000 ... 0x00001FFF).
 So a typical memory configuration with 16 MB of DRAM could look like
 this:
 	0x0000 0000	Exception Vector code
 	      :
 	0x0000 1FFF
 	0x0000 2000	Free for Application Use
 	      :
 	      :
 	      :
 	      :
 	0x00FB FF20	Monitor Stack (Growing downward)
 	0x00FB FFAC	Board Info Data and permanent copy of global data
 	0x00FC 0000	Malloc Arena
 	      :
 	0x00FD FFFF
 	0x00FE 0000	RAM Copy of Monitor Code
 	...		eventually: LCD or video framebuffer
 	...		eventually: pRAM (Protected RAM - unchanged by reset)
 	0x00FF FFFF	[End of RAM]
 System Initialization:
 ----------------------
 In the reset configuration, U-Boot starts at the reset entry point
 (on most PowerPC systems at address 0x00000100). Because of the reset
 configuration for CS0# this is a mirror of the onboard Flash memory.
 To be able to re-map memory U-Boot then jumps to its link address.
 To be able to implement the initialization code in C, a (small!)
 initial stack is set up in the internal Dual Ported RAM (in case CPUs
 which provide such a feature like MPC8xx or MPC8260), or in a locked
 part of the data cache. After that, U-Boot initializes the CPU core,
 the caches and the SIU.
 Next, all (potentially) available memory banks are mapped using a
 preliminary mapping. For example, we put them on 512 MB boundaries
 (multiples of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash
 on 0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is
 programmed for SDRAM access. Using the temporary configuration, a
 simple memory test is run that determines the size of the SDRAM
 banks.
 When there is more than one SDRAM bank, and the banks are of
 different size, the largest is mapped first. For equal size, the first
 bank (CS2#) is mapped first. The first mapping is always for address
 0x00000000, with any additional banks following immediately to create
 contiguous memory starting from 0.
 Then, the monitor installs itself at the upper end of the SDRAM area
 and allocates memory for use by malloc() and for the global Board
 Info data; also, the exception vector code is copied to the low RAM
 pages, and the final stack is set up.
 Only after this relocation will you have a "normal" C environment;
 until that you are restricted in several ways, mostly because you are
 running from ROM, and because the code will have to be relocated to a
 new address in RAM.
 U-Boot Porting Guide:
 ----------------------
 [Based on messages by Jerry Van Baren in the U-Boot-Users mailing
 list, October 2002]
 int main(int argc, char *argv[])
 {
 	sighandler_t no_more_time;
 	signal(SIGALRM, no_more_time);
 	alarm(PROJECT_DEADLINE - toSec (3 * WEEK));
 	if (available_money > available_manpower) {
 		Pay consultant to port U-Boot;
 		return 0;
 	}
 	Download latest U-Boot source;
 	Subscribe to u-boot mailing list;
 	if (clueless)
 		email("Hi, I am new to U-Boot, how do I get started?");
 	while (learning) {
 		Read the README file in the top level directory;
 		Read http://www.denx.de/twiki/bin/view/DULG/Manual;
 		Read applicable doc/*.README;
 		Read the source, Luke;
 		/* find . -name "*.[chS]" | xargs grep -i <keyword> */
 	}
 	if (available_money > toLocalCurrency ($2500))
 		Buy a BDI3000;
 	else
 		Add a lot of aggravation and time;
 	if (a similar board exists) {	/* hopefully... */
 		cp -a board/<similar> board/<myboard>
 		cp include/configs/<similar>.h include/configs/<myboard>.h
 	} else {
 		Create your own board support subdirectory;
 		Create your own board include/configs/<myboard>.h file;
 	}
 	Edit new board/<myboard> files
 	Edit new include/configs/<myboard>.h
 	while (!accepted) {
 		while (!running) {
 			do {
 				Add / modify source code;
 			} until (compiles);
 			Debug;
 			if (clueless)
 				email("Hi, I am having problems...");
 		}
 		Send patch file to the U-Boot email list;
 		if (reasonable critiques)
 			Incorporate improvements from email list code review;
 		else
 			Defend code as written;
 	}
 	return 0;
 }
 void no_more_time (int sig)
 {
       hire_a_guru();
 }
 Coding Standards:
 -----------------
 All contributions to U-Boot should conform to the Linux kernel
 coding style; see the file "Documentation/CodingStyle" and the script
 "scripts/Lindent" in your Linux kernel source directory.
 Source files originating from a different project (for example the
 MTD subsystem) are generally exempt from these guidelines and are not
 reformated to ease subsequent migration to newer versions of those
 sources.
 Please note that U-Boot is implemented in C (and to some small parts in
 Assembler); no C++ is used, so please do not use C++ style comments (//)
 in your code.
 Please also stick to the following formatting rules:
 - remove any trailing white space
 - use TAB characters for indentation and vertical alignment, not spaces
 - make sure NOT to use DOS '\r\n' line feeds
 - do not add more than 2 consecutive empty lines to source files
 - do not add trailing empty lines to source files
 Submissions which do not conform to the standards may be returned
 with a request to reformat the changes.
 Submitting Patches:
 -------------------
 Since the number of patches for U-Boot is growing, we need to
 establish some rules. Submissions which do not conform to these rules
 may be rejected, even when they contain important and valuable stuff.
 Please see http://www.denx.de/wiki/U-Boot/Patches for details.
 Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
 see http://lists.denx.de/mailman/listinfo/u-boot
 When you send a patch, please include the following information with
 it:
 * For bug fixes: a description of the bug and how your patch fixes
   this bug. Please try to include a way of demonstrating that the
   patch actually fixes something.
 * For new features: a description of the feature and your
   implementation.
 * A CHANGELOG entry as plaintext (separate from the patch)
 * For major contributions, your entry to the CREDITS file
 * When you add support for a new board, don't forget to add a
   maintainer e-mail address to the boards.cfg file, too.
 * If your patch adds new configuration options, don't forget to
   document these in the README file.
 * The patch itself. If you are using git (which is *strongly*
   recommended) you can easily generate the patch using the
   "git format-patch". If you then use "git send-email" to send it to
   the U-Boot mailing list, you will avoid most of the common problems
   with some other mail clients.
   If you cannot use git, use "diff -purN OLD NEW". If your version of
   diff does not support these options, then get the latest version of
   GNU diff.
   The current directory when running this command shall be the parent
   directory of the U-Boot source tree (i. e. please make sure that
   your patch includes sufficient directory information for the
   affected files).
   We prefer patches as plain text. MIME attachments are discouraged,
   and compressed attachments must not be used.
 * If one logical set of modifications affects or creates several
   files, all these changes shall be submitted in a SINGLE patch file.
 * Changesets that contain different, unrelated modifications shall be
   submitted as SEPARATE patches, one patch per changeset.
 Notes:
 * Before sending the patch, run the MAKEALL script on your patched
   source tree and make sure that no errors or warnings are reported
   for any of the boards.
 * Keep your modifications to the necessary minimum: A patch
   containing several unrelated changes or arbitrary reformats will be
   returned with a request to re-formatting / split it.
 * If you modify existing code, make sure that your new code does not
   add to the memory footprint of the code ;-) Small is beautiful!
   When adding new features, these should compile conditionally only
   (using #ifdef), and the resulting code with the new feature
   disabled must not need more memory than the old code without your
   modification.
 * Remember that there is a size limit of 100 kB per message on the
   u-boot mailing list. Bigger patches will be moderated. If they are
   reasonable and not too big, they will be acknowledged. But patches
   bigger than the size limit should be avoided.

arch/arm/cpu/arm1136/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
  *
  *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
  *
  *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
  *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
  *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
  *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
  *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 .globl _start
 _start: b	reset
 #ifdef CONFIG_SPL_BUILD
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 _hang:
 	.word	do_hang
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678	/* now 16*4=64 */
 #else
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
 _data_abort:		.word data_abort
 _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #endif	/* CONFIG_SPL_BUILD */
 .global _end_vect
 _end_vect:
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
  * setup Memory and board specific bits prior to relocation.
  * relocate armboot to ram
  * setup stack
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 reset:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
 	mrs	r0,cpsr
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl  cpu_init_crit
 #endif
 	bl	_main
 /*------------------------------------------------------------------------------*/
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 	bx	lr
 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
 	 */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
 	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
 	/*
 	 * disable MMU stuff and caches
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
 	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
 	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 	/*
 	 * Jump to board specific initialization... The Mask ROM will have already initialized
 	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
 	 */
 	mov	ip, lr		/* persevere link reg across call */
 	bl	lowlevel_init	/* go setup pll,mux,memory */
 	mov	lr, ip		/* restore link */
 	mov	pc, lr		/* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 #ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC 0x13
 #define I_BIT	 0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
 	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
 	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
 	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
 	mov	r0, sp				@ save current stack into r0 (param register)
 	.endm
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 	stmdb	r8, {sp, lr}^			@ Calling SP, LR
 	str	lr, [r8, #0]			@ Save calling PC
 	mrs	r6, spsr
 	str	r6, [r8, #4]			@ Save CPSR
 	str	r0, [r8, #8]			@ Save OLD_R0
 	mov	r0, sp
 	.endm
 	.macro	irq_restore_user_regs
 	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
 	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
 	str	lr, [r13]			@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr			@ get the spsr
 	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
 	mov	r13, #MODE_SVC			@ prepare SVC-Mode
 	@ msr	spsr_c, r13
 	msr	spsr, r13			@ switch modes, make sure moves will execute
 	mov	lr, pc				@ capture return pc
 	movs	pc, lr				@ jump to next instruction & switch modes.
 	.endm
 	.macro get_bad_stack_swi
 	sub	r13, r13, #4			@ space on current stack for scratch reg.
 	str	r0, [r13]			@ save R0's value.
 	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
 	str	lr, [r0]			@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr			@ get the spsr
 	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
 	ldr	lr, [r0]			@ restore lr
 	ldr	r0, [r13]			@ restore r0
 	add	r13, r13, #4			@ pop stack entry
 	.endm
 	.macro get_irq_stack			@ setup IRQ stack
 	ldr	sp, IRQ_STACK_START
 	.endm
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
 #endif	/* CONFIG_SPL_BUILD */
 /*
  * exception handlers
  */
 #ifdef CONFIG_SPL_BUILD
 	.align	5
 do_hang:
-	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
 	bl	hang				/* hang and never return */
 #else	/* !CONFIG_SPL_BUILD */
 	.align	5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 software_interrupt:
 	get_bad_stack_swi
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 #ifdef CONFIG_USE_IRQ
 	.align	5
 irq:
 	get_irq_stack
 	irq_save_user_regs
 	bl	do_irq
 	irq_restore_user_regs
 	.align	5
 fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
 	bl	do_fiq
 	irq_restore_user_regs
 #else
 	.align	5
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif
 	.align 5
 .global arm1136_cache_flush
 arm1136_cache_flush:
 #if !defined(CONFIG_SYS_ICACHE_OFF)
 		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
 #endif
 #if !defined(CONFIG_SYS_DCACHE_OFF)
 		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
 #endif
 		mov	pc, lr			@ back to caller
 #endif	/* CONFIG_SPL_BUILD */

arch/arm/cpu/arm1176/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for ARM1176 CPU-core
  *
  * Copyright (c) 2007	Samsung Electronics
  *
  * Copyright (C) 2008
  * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
  * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
  * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
  * jsgood (jsgood.yang@samsung.com)
  * Base codes by scsuh (sc.suh)
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
 #define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
 #endif
 /*
  *************************************************************************
  *
  * Jump vector table as in table 3.1 in [1]
  *
  *************************************************************************
  */
 .globl _start
 _start: b	reset
 #ifndef CONFIG_SPL_BUILD
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 _undefined_instruction:
 	.word undefined_instruction
 _software_interrupt:
 	.word software_interrupt
 _prefetch_abort:
 	.word prefetch_abort
 _data_abort:
 	.word data_abort
 _not_used:
 	.word not_used
 _irq:
 	.word irq
 _fiq:
 	.word fiq
 _pad:
 	.word 0x12345678 /* now 16*4=64 */
 #else
 	. = _start + 64
 #endif
 .global _end_vect
 _end_vect:
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
  * setup Memory and board specific bits prior to relocation.
  * relocate armboot to ram
  * setup stack
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 reset:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
 	mrs	r0, cpsr
 	bic	r0, r0, #0x3f
 	orr	r0, r0, #0xd3
 	msr	cpsr, r0
 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
 cpu_init_crit:
 	/*
 	 * When booting from NAND - it has definitely been a reset, so, no need
 	 * to flush caches and disable the MMU
 	 */
 #ifndef CONFIG_SPL_BUILD
 	/*
 	 * flush v4 I/D caches
 	 */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
 	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
 	/*
 	 * disable MMU stuff and caches
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
 	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
 	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	/* Prepare to disable the MMU */
 	adr	r2, mmu_disable_phys
 	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
 	b	mmu_disable
 	.align 5
 	/* Run in a single cache-line */
 mmu_disable:
 	mcr	p15, 0, r0, c1, c0, 0
 	nop
 	nop
 	mov	pc, r2
 mmu_disable_phys:
 #ifdef CONFIG_DISABLE_TCM
 	/*
 	 * Disable the TCMs
 	 */
 	mrc	p15, 0, r0, c0, c0, 2	/* Return TCM details */
 	cmp	r0, #0
 	beq	skip_tcmdisable
 	mov	r1, #0
 	mov	r2, #1
 	tst	r0, r2
 	mcrne	p15, 0, r1, c9, c1, 1	/* Disable Instruction TCM if present*/
 	tst	r0, r2, LSL #16
 	mcrne	p15, 0, r1, c9, c1, 0	/* Disable Data TCM if present*/
 skip_tcmdisable:
 #endif
 #endif
 #ifdef CONFIG_PERIPORT_REMAP
 	/* Peri port setup */
 	ldr	r0, =CONFIG_PERIPORT_BASE
 	orr	r0, r0, #CONFIG_PERIPORT_SIZE
 	mcr	p15,0,r0,c15,c2,4
 #endif
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
 	bl	lowlevel_init		/* go setup pll,mux,memory */
 	bl	_main
 /*------------------------------------------------------------------------------*/
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 	mov	pc, lr
 #ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC 0x13
 #define I_BIT	 0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  */
 	.macro	bad_save_user_regs
 	/* carve out a frame on current user stack */
 	sub	sp, sp, #S_FRAME_SIZE
 	/* Save user registers (now in svc mode) r0-r12 */
 	stmia	sp, {r0 - r12}
 	ldr	r2, IRQ_STACK_START_IN
 	/* get values for "aborted" pc and cpsr (into parm regs) */
 	ldmia	r2, {r2 - r3}
 	/* grab pointer to old stack */
 	add	r0, sp, #S_FRAME_SIZE
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	/* save sp_SVC, lr_SVC, pc, cpsr */
 	stmia	r5, {r0 - r3}
 	/* save current stack into r0 (param register) */
 	mov	r0, sp
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
 	/* save caller lr in position 0 of saved stack */
 	str	lr, [r13]
 	/* get the spsr */
 	mrs	lr, spsr
 	/* save spsr in position 1 of saved stack */
 	str	lr, [r13, #4]
 	/* prepare SVC-Mode */
 	mov	r13, #MODE_SVC
 	@ msr	spsr_c, r13
 	/* switch modes, make sure moves will execute */
 	msr	spsr, r13
 	/* capture return pc */
 	mov	lr, pc
 	/* jump to next instruction & switch modes. */
 	movs	pc, lr
 	.endm
 	.macro get_bad_stack_swi
 	/* space on current stack for scratch reg. */
 	sub	r13, r13, #4
 	/* save R0's value. */
 	str	r0, [r13]
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
 	/* save caller lr in position 0 of saved stack */
 	str	lr, [r0]
 	/* get the spsr */
 	mrs	lr, spsr
 	/* save spsr in position 1 of saved stack */
 	str	lr, [r0, #4]
 	/* restore lr */
 	ldr	lr, [r0]
 	/* restore r0 */
 	ldr	r0, [r13]
 	/* pop stack entry */
 	add	r13, r13, #4
 	.endm
 /*
  * exception handlers
  */
 	.align	5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 software_interrupt:
 	get_bad_stack_swi
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 	.align	5
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif /* CONFIG_SPL_BUILD */

arch/arm/cpu/arm720t/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for ARM720 CPU-core
  *
  *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
  *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 #include <asm/hardware.h>
 /*
  *************************************************************************
  *
  * Jump vector table as in table 3.1 in [1]
  *
  *************************************************************************
  */
 .globl _start
 _start: b	reset
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 #ifdef CONFIG_SPL_BUILD
 _undefined_instruction: .word _undefined_instruction
 _software_interrupt:	.word _software_interrupt
 _prefetch_abort:	.word _prefetch_abort
 _data_abort:		.word _data_abort
 _not_used:		.word _not_used
 _irq:			.word _irq
 _fiq:			.word _fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #else
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
 _data_abort:		.word data_abort
 _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #endif	/* CONFIG_SPL_BUILD */
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from RAM!
  * relocate armboot to ram
  * setup stack
  * jump to second stage
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 reset:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
 	mrs	r0,cpsr
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 	bl	_main
 /*------------------------------------------------------------------------------*/
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 	mov	pc, lr
 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	mov	ip, lr
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependent, you will
 	 * find a lowlevel_init.S in your board directory.
 	 */
 	bl	lowlevel_init
 	mov	lr, ip
 	mov	pc, lr
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 #ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC 0x13
 #define I_BIT	 0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add	r8, sp, #S_PC
 	ldr	r2, IRQ_STACK_START_IN
 	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
 	mov	r0, sp
 	.endm
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add	r8, sp, #S_PC
 	stmdb	r8, {sp, lr}^			@ Calling SP, LR
 	str	lr, [r8, #0]			@ Save calling PC
 	mrs	r6, spsr
 	str	r6, [r8, #4]			@ Save CPSR
 	str	r0, [r8, #8]			@ Save OLD_R0
 	mov	r0, sp
 	.endm
 	.macro	irq_restore_user_regs
 	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
 	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
 	str	lr, [r13, #4]
 	mov	r13, #MODE_SVC			@ prepare SVC-Mode
 	msr	spsr_c, r13
 	mov	lr, pc
 	movs	pc, lr
 	.endm
 	.macro get_irq_stack			@ setup IRQ stack
 	ldr	sp, IRQ_STACK_START
 	.endm
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
 /*
  * exception handlers
  */
 	.align	5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 #ifdef CONFIG_USE_IRQ
 	.align	5
 irq:
 	get_irq_stack
 	irq_save_user_regs
 	bl	do_irq
 	irq_restore_user_regs
 	.align	5
 fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
 	bl	do_fiq
 	irq_restore_user_regs
 #else
 	.align	5
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif
 #endif /* CONFIG_SPL_BUILD */

arch/arm/cpu/arm920t/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for ARM920 CPU-core
  *
  *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
  *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
  *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <common.h>
 #include <config.h>
 /*
  *************************************************************************
  *
  * Jump vector table as in table 3.1 in [1]
  *
  *************************************************************************
  */
 .globl _start
 _start:	b	start_code
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 _undefined_instruction:	.word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
 _data_abort:		.word data_abort
 _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *
  * Startup Code (called from the ARM reset exception vector)
  *
  * do important init only if we don't start from memory!
  * relocate armboot to ram
  * setup stack
  * jump to second stage
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual start code
  */
 start_code:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
 	mrs	r0, cpsr
 	bic	r0, r0, #0x1f
 	orr	r0, r0, #0xd3
 	msr	cpsr, r0
 #if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
 	/*
 	 * relocate exception table
 	 */
 	ldr	r0, =_start
 	ldr	r1, =0x0
 	mov	r2, #16
 copyex:
 	subs	r2, r2, #1
 	ldr	r3, [r0], #4
 	str	r3, [r1], #4
 	bne	copyex
 #endif
 #ifdef CONFIG_S3C24X0
 	/* turn off the watchdog */
 # if defined(CONFIG_S3C2400)
 #  define pWTCON	0x15300000
 #  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
 #  define CLKDIVN	0x14800014	/* clock divisor register */
 #else
 #  define pWTCON	0x53000000
 #  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
 #  define INTSUBMSK	0x4A00001C
 #  define CLKDIVN	0x4C000014	/* clock divisor register */
 # endif
 	ldr	r0, =pWTCON
 	mov	r1, #0x0
 	str	r1, [r0]
 	/*
 	 * mask all IRQs by setting all bits in the INTMR - default
 	 */
 	mov	r1, #0xffffffff
 	ldr	r0, =INTMSK
 	str	r1, [r0]
 # if defined(CONFIG_S3C2410)
 	ldr	r1, =0x3ff
 	ldr	r0, =INTSUBMSK
 	str	r1, [r0]
 # endif
 	/* FCLK:HCLK:PCLK = 1:2:4 */
 	/* default FCLK is 120 MHz ! */
 	ldr	r0, =CLKDIVN
 	mov	r1, #3
 	str	r1, [r0]
 #endif	/* CONFIG_S3C24X0 */
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 	bl	_main
 /*------------------------------------------------------------------------------*/
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 	mov	pc, lr
 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
 	 */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
 	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
 	/*
 	 * disable MMU stuff and caches
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
 	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
 	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependend, you will
 	 * find a lowlevel_init.S in your board directory.
 	 */
 	mov	ip, lr
 	bl	lowlevel_init
 	mov	lr, ip
 	mov	pc, lr
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC	0x13
 #define I_BIT		0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	ldr	r2, IRQ_STACK_START_IN
 	ldmia	r2, {r2 - r3}			@ get pc, cpsr
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
 	mov	r0, sp
 	.endm
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add	r7, sp, #S_PC
 	stmdb	r7, {sp, lr}^			@ Calling SP, LR
 	str	lr, [r7, #0]			@ Save calling PC
 	mrs	r6, spsr
 	str	r6, [r7, #4]			@ Save CPSR
 	str	r0, [r7, #8]			@ Save OLD_R0
 	mov	r0, sp
 	.endm
 	.macro	irq_restore_user_regs
 	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
 	/* return & move spsr_svc into cpsr */
 	subs	pc, lr, #4
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
 	str	lr, [r13, #4]
 	mov	r13, #MODE_SVC			@ prepare SVC-Mode
 	@ msr	spsr_c, r13
 	msr	spsr, r13
 	mov	lr, pc
 	movs	pc, lr
 	.endm
 	.macro get_irq_stack			@ setup IRQ stack
 	ldr	sp, IRQ_STACK_START
 	.endm
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
 /*
  * exception handlers
  */
 	.align  5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 #ifdef CONFIG_USE_IRQ
 	.align	5
 irq:
 	get_irq_stack
 	irq_save_user_regs
 	bl	do_irq
 	irq_restore_user_regs
 	.align	5
 fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
 	bl	do_fiq
 	irq_restore_user_regs
 #else
 	.align	5
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif

arch/arm/cpu/arm926ejs/at91/lowlevel_init.S

Diff comments View file @ b60eff3

 /*
  * Memory Setup stuff - taken from blob memsetup.S
  *
  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  *
  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_wdt.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91sam9_sdramc.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_rstc.h>
 #ifdef CONFIG_ATMEL_LEGACY
 #include <asm/arch/at91sam9_matrix.h>
 #endif
 #ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
 #define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
 #endif
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
 .globl lowlevel_init
 .type lowlevel_init,function
 lowlevel_init:
-	mov	r5, pc		/* r5 = POS1 + 4 current */
 POS1:
+	adr	r5, POS1	/* r5 = POS1 run time */
 	ldr	r0, =POS1	/* r0 = POS1 compile */
-	ldr	r2, _TEXT_BASE
-	sub	r0, r0, r2	/* r0 = POS1-_TEXT_BASE (POS1 relative) */
 	sub	r5, r5, r0	/* r0 = CONFIG_SYS_TEXT_BASE-1 */
-	sub	r5, r5, #4	/* r1 = text base - current */
 	/* memory control configuration 1 */
 	ldr	r0, =SMRDATA
 	ldr	r2, =SMRDATA1
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
 	add	r0, r0, r5
 	add	r2, r2, r5
 0:
 	/* the address */
 	ldr	r1, [r0], #4
 	/* the value */
 	ldr	r3, [r0], #4
 	str	r3, [r1]
 	cmp	r2, r0
 	bne	0b
 /* ----------------------------------------------------------------------------
  * PMC Init Step 1.
  * ----------------------------------------------------------------------------
  * - Check if the PLL is already initialized
  * ----------------------------------------------------------------------------
  */
 	ldr	r1, =(AT91_ASM_PMC_MCKR)
 	ldr	r0, [r1]
 	and	r0, r0, #3
 	cmp	r0, #0
 	bne	PLL_setup_end
 /* ---------------------------------------------------------------------------
  * - Enable the Main Oscillator
  * ---------------------------------------------------------------------------
  */
 	ldr	r1, =(AT91_ASM_PMC_MOR)
 	ldr	r2, =(AT91_ASM_PMC_SR)
 	/* Main oscillator Enable register PMC_MOR: */
 	ldr	r0, =CONFIG_SYS_MOR_VAL
 	str	r0, [r1]
 	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
 	mov	r4, #AT91_PMC_IXR_MOSCS
 MOSCS_Loop:
 	ldr	r3, [r2]
 	and	r3, r4, r3
 	cmp	r3, #AT91_PMC_IXR_MOSCS
 	bne	MOSCS_Loop
 /* ----------------------------------------------------------------------------
  * PMC Init Step 2.
  * ----------------------------------------------------------------------------
  * Setup PLLA
  * ----------------------------------------------------------------------------
  */
 	ldr	r1, =(AT91_ASM_PMC_PLLAR)
 	ldr	r0, =CONFIG_SYS_PLLAR_VAL
 	str	r0, [r1]
 	/* Reading the PMC Status register to detect when the PLLA is locked */
 	mov	r4, #AT91_PMC_IXR_LOCKA
 MOSCS_Loop1:
 	ldr	r3, [r2]
 	and	r3, r4, r3
 	cmp	r3, #AT91_PMC_IXR_LOCKA
 	bne	MOSCS_Loop1
 /* ----------------------------------------------------------------------------
  * PMC Init Step 3.
  * ----------------------------------------------------------------------------
  * - Switch on the Main Oscillator
  * ----------------------------------------------------------------------------
  */
 	ldr	r1, =(AT91_ASM_PMC_MCKR)
 	/* -Master Clock Controller register PMC_MCKR */
 	ldr	r0, =CONFIG_SYS_MCKR1_VAL
 	str	r0, [r1]
 	/* Reading the PMC Status to detect when the Master clock is ready */
 	mov	r4, #AT91_PMC_IXR_MCKRDY
 MCKRDY_Loop:
 	ldr	r3, [r2]
 	and	r3, r4, r3
 	cmp	r3, #AT91_PMC_IXR_MCKRDY
 	bne	MCKRDY_Loop
 	ldr	r0, =CONFIG_SYS_MCKR2_VAL
 	str	r0, [r1]
 	/* Reading the PMC Status to detect when the Master clock is ready */
 	mov	r4, #AT91_PMC_IXR_MCKRDY
 MCKRDY_Loop1:
 	ldr	r3, [r2]
 	and	r3, r4, r3
 	cmp	r3, #AT91_PMC_IXR_MCKRDY
 	bne	MCKRDY_Loop1
 PLL_setup_end:
 /* ----------------------------------------------------------------------------
  * - memory control configuration 2
  * ----------------------------------------------------------------------------
  */
 	ldr	r0, =(AT91_ASM_SDRAMC_TR)
 	ldr	r1, [r0]
 	cmp	r1, #0
 	bne	SDRAM_setup_end
 	ldr	r0, =SMRDATA1
 	ldr	r2, =SMRDATA2
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
 	add	r0, r0, r5
 	add	r2, r2, r5
 2:
 	/* the address */
 	ldr	r1, [r0], #4
 	/* the value */
 	ldr	r3, [r0], #4
 	str	r3, [r1]
 	cmp	r2, r0
 	bne	2b
 SDRAM_setup_end:
 	/* everything is fine now */
 	mov	pc, lr
 	.ltorg
 SMRDATA:
 	.word AT91_ASM_WDT_MR
 	.word CONFIG_SYS_WDTC_WDMR_VAL
 	/* configure PIOx as EBI0 D[16-31] */
 #if defined(CONFIG_AT91SAM9263)
 	.word AT91_ASM_PIOD_PDR
 	.word CONFIG_SYS_PIOD_PDR_VAL1
 	.word AT91_ASM_PIOD_PUDR
 	.word CONFIG_SYS_PIOD_PPUDR_VAL
 	.word AT91_ASM_PIOD_ASR
 	.word CONFIG_SYS_PIOD_PPUDR_VAL
 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
 	|| defined(CONFIG_AT91SAM9G20)
 	.word AT91_ASM_PIOC_PDR
 	.word CONFIG_SYS_PIOC_PDR_VAL1
 	.word AT91_ASM_PIOC_PUDR
 	.word CONFIG_SYS_PIOC_PPUDR_VAL
 #endif
 	.word AT91_ASM_MATRIX_CSA0
 	.word CONFIG_SYS_MATRIX_EBICSA_VAL
 	/* flash */
 	.word AT91_ASM_SMC_MODE0
 	.word CONFIG_SYS_SMC0_MODE0_VAL
 	.word AT91_ASM_SMC_CYCLE0
 	.word CONFIG_SYS_SMC0_CYCLE0_VAL
 	.word AT91_ASM_SMC_PULSE0
 	.word CONFIG_SYS_SMC0_PULSE0_VAL
 	.word AT91_ASM_SMC_SETUP0
 	.word CONFIG_SYS_SMC0_SETUP0_VAL
 SMRDATA1:
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL1
 	.word AT91_ASM_SDRAMC_TR
 	.word CONFIG_SYS_SDRC_TR_VAL1
 	.word AT91_ASM_SDRAMC_CR
 	.word CONFIG_SYS_SDRC_CR_VAL
 	.word AT91_ASM_SDRAMC_MDR
 	.word CONFIG_SYS_SDRC_MDR_VAL
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL2
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL1
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL3
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL2
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL3
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL4
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL5
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL6
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL7
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL8
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL9
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL4
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL10
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL5
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL11
 	.word AT91_ASM_SDRAMC_TR
 	.word CONFIG_SYS_SDRC_TR_VAL2
 	.word CONFIG_SYS_SDRAM_BASE
 	.word CONFIG_SYS_SDRAM_VAL12
 	/* User reset enable*/
 	.word AT91_ASM_RSTC_MR
 	.word CONFIG_SYS_RSTC_RMR_VAL
 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
 	/* MATRIX_MCFG - REMAP all masters */
 	.word AT91_ASM_MATRIX_MCFG
 	.word 0x1FF
 #endif
 SMRDATA2:
 	.word 0

arch/arm/cpu/arm926ejs/mxs/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for ARM926EJS CPU-core
  *
  *  Copyright (c) 2003  Texas Instruments
  *
  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  *
  *  Copyright (c) 2001	Marius Groger <mag@sysgo.de>
  *  Copyright (c) 2002	Alex Zupke <azu@sysgo.de>
  *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
  *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
  *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
  *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
  *
  * Change to support call back into iMX28 bootrom
  * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <common.h>
 #include <version.h>
 /*
  *************************************************************************
  *
  * Jump vector table as in table 3.1 in [1]
  *
  *************************************************************************
  */
 .globl _start
 _start:
 	b	reset
 	b	undefined_instruction
 	b	software_interrupt
 	b	prefetch_abort
 	b	data_abort
 	b	not_used
 	b	irq
 	b	fiq
 /*
  * Vector table, located at address 0x20.
  * This table allows the code running AFTER SPL, the U-Boot, to install it's
  * interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
  * including it's interrupt vectoring table and the table at 0x0 is still the
  * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
  * is still used.
  */
 _vt_reset:
 	.word	_reset
 _vt_undefined_instruction:
 	.word	_hang
 _vt_software_interrupt:
 	.word	_hang
 _vt_prefetch_abort:
 	.word	_hang
 _vt_data_abort:
 	.word	_hang
 _vt_not_used:
 	.word	_reset
 _vt_irq:
 	.word	_hang
 _vt_fiq:
 	.word	_hang
 reset:
 	ldr	pc, _vt_reset
 undefined_instruction:
 	ldr	pc, _vt_undefined_instruction
 software_interrupt:
 	ldr	pc, _vt_software_interrupt
 prefetch_abort:
 	ldr	pc, _vt_prefetch_abort
 data_abort:
 	ldr	pc, _vt_data_abort
 not_used:
 	ldr	pc, _vt_not_used
 irq:
 	ldr	pc, _vt_irq
 fiq:
 	ldr	pc, _vt_fiq
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
  * setup Memory and board specific bits prior to relocation.
  * relocate armboot to ram
  * setup stack
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#ifdef CONFIG_SPL_TEXT_BASE
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 _reset:
 	/*
 	 * If the CPU is configured in "Wait JTAG connection mode", the stack
 	 * pointer is not configured and is zero. This will cause crash when
 	 * trying to push data onto stack right below here. Load the SP and make
 	 * it point to the end of OCRAM if the SP is zero.
 	 */
 	cmp	sp, #0x00000000
 	ldreq	sp, =CONFIG_SYS_INIT_SP_ADDR
 	/*
 	 * Store all registers on old stack pointer, this will allow us later to
 	 * return to the BootROM and let the BootROM load U-Boot into RAM.
 	 *
 	 * WARNING: Register r0 and r1 are used by the BootROM to pass data
 	 *          to the called code. Register r0 will contain arbitrary
 	 *          data that are set in the BootStream. In case this code
 	 *          was started with CALL instruction, register r1 will contain
 	 *          pointer to the return value this function can then set.
 	 *          The code below MUST NOT CHANGE register r0 and r1 !
 	 */
 	push	{r0-r12,r14}
 	/* Save control register c1 */
 	mrc	p15, 0, r2, c1, c0, 0
 	push	{r2}
 	/* Set the cpu to SVC32 mode and store old CPSR register content. */
 	mrs	r2, cpsr
 	push	{r2}
 	bic	r2, r2, #0x1f
 	orr	r2, r2, #0xd3
 	msr	cpsr, r2
 	bl	board_init_ll
 	/* Restore BootROM's CPU mode (especially FIQ). */
 	pop	{r2}
 	msr	cpsr,r2
 	/*
 	 * Restore c1 register. Especially set exception vector location
 	 * back to BootROM space which is required by bootrom for USB boot.
 	 */
 	pop	{r2}
 	mcr	p15, 0, r2, c1, c0, 0
 	pop	{r0-r12,r14}
 	/*
 	 * In case this code was started by the CALL instruction, the register
 	 * r0 is examined by the BootROM after this code returns. The value in
 	 * r0 must be set to 0 to indicate successful return.
 	 */
 	mov r0, #0
 	bx	lr
 _hang:
-	ldr	sp, _TEXT_BASE			/* switch to abort stack */
 1:
 	bl	1b				/* hang and never return */

arch/arm/cpu/arm926ejs/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for ARM926EJS CPU-core
  *
  *  Copyright (c) 2003  Texas Instruments
  *
  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  *
  *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
  *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
  *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
  *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
  *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
  *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <common.h>
 #include <version.h>
 /*
  *************************************************************************
  *
  * Jump vector table as in table 3.1 in [1]
  *
  *************************************************************************
  */
 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
 .globl _start
 _start:
 .globl _NOR_BOOT_CFG
 _NOR_BOOT_CFG:
 	.word	CONFIG_SYS_DV_NOR_BOOT_CFG
 	b	reset
 #else
 .globl _start
 _start:
 	b	reset
 #endif
 #ifdef CONFIG_SPL_BUILD
 /* No exception handlers in preloader */
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 _hang:
 	.word	do_hang
 /* pad to 64 byte boundary */
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 #else
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 _undefined_instruction:
 	.word undefined_instruction
 _software_interrupt:
 	.word software_interrupt
 _prefetch_abort:
 	.word prefetch_abort
 _data_abort:
 	.word data_abort
 _not_used:
 	.word not_used
 _irq:
 	.word irq
 _fiq:
 	.word fiq
 #endif	/* CONFIG_SPL_BUILD */
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
  * setup Memory and board specific bits prior to relocation.
  * relocate armboot to ram
  * setup stack
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 reset:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
 	mrs	r0,cpsr
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 	bl	_main
 /*------------------------------------------------------------------------------*/
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 	bx	lr
 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush D cache before disabling it
 	 */
 	mov	r0, #0
 flush_dcache:
 	mrc	p15, 0, r15, c7, c10, 3
 	bne	flush_dcache
 	mcr	p15, 0, r0, c8, c7, 0	/* invalidate TLB */
 	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I Cache */
 	/*
 	 * disable MMU and D cache
 	 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
 #ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
 #else
 	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
 #endif
 	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
 #ifndef CONFIG_SYS_ICACHE_OFF
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
 #endif
 	mcr	p15, 0, r0, c1, c0, 0
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
 	mov	ip, lr		/* perserve link reg across call */
 	bl	lowlevel_init	/* go setup pll,mux,memory */
 	mov	lr, ip		/* restore link */
 	mov	pc, lr		/* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 #ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC 0x13
 #define I_BIT	 0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */
 	.macro	bad_save_user_regs
 	@ carve out a frame on current user stack
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
 	ldr	r2, IRQ_STACK_START_IN
 	@ get values for "aborted" pc and cpsr (into parm regs)
 	ldmia	r2, {r2 - r3}
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
 	mov	r0, sp		@ save current stack into r0 (param register)
 	.endm
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 	add	r8, sp, #S_PC
 	stmdb	r8, {sp, lr}^		@ Calling SP, LR
 	str	lr, [r8, #0]		@ Save calling PC
 	mrs	r6, spsr
 	str	r6, [r8, #4]		@ Save CPSR
 	str	r0, [r8, #8]		@ Save OLD_R0
 	mov	r0, sp
 	.endm
 	.macro	irq_restore_user_regs
 	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
 	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
 	str	lr, [r13]	@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr	@ get the spsr
 	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
 	mov	r13, #MODE_SVC	@ prepare SVC-Mode
 	@ msr	spsr_c, r13
 	msr	spsr, r13	@ switch modes, make sure moves will execute
 	mov	lr, pc		@ capture return pc
 	movs	pc, lr		@ jump to next instruction & switch modes.
 	.endm
 	.macro get_irq_stack			@ setup IRQ stack
 	ldr	sp, IRQ_STACK_START
 	.endm
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
 #endif	/* CONFIG_SPL_BUILD */
 /*
  * exception handlers
  */
 #ifdef CONFIG_SPL_BUILD
 	.align	5
 do_hang:
-	ldr	sp, _TEXT_BASE			/* switch to abort stack */
 1:
 	bl	1b				/* hang and never return */
 #else	/* !CONFIG_SPL_BUILD */
 	.align  5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 #ifdef CONFIG_USE_IRQ
 	.align	5
 irq:
 	get_irq_stack
 	irq_save_user_regs
 	bl	do_irq
 	irq_restore_user_regs
 	.align	5
 fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
 	bl	do_fiq
 	irq_restore_user_regs
 #else
 	.align	5
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif
 #endif	/* CONFIG_SPL_BUILD */

arch/arm/cpu/arm946es/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for ARM926EJS CPU-core
  *
  *  Copyright (c) 2003  Texas Instruments
  *
  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  *
  *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
  *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
  *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
  *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
  *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
  *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 /*
  *************************************************************************
  *
  * Jump vector table as in table 3.1 in [1]
  *
  *************************************************************************
  */
 .globl _start
 _start:
 	b	reset
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 _undefined_instruction:
 	.word undefined_instruction
 _software_interrupt:
 	.word software_interrupt
 _prefetch_abort:
 	.word prefetch_abort
 _data_abort:
 	.word data_abort
 _not_used:
 	.word not_used
 _irq:
 	.word irq
 _fiq:
 	.word fiq
 	.balignl 16,0xdeadbeef
 _vectors_end:
 /*
  *************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
  * setup Memory and board specific bits prior to relocation.
  * relocate armboot to ram
  * setup stack
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 reset:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
 	mrs	r0,cpsr
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 	bl	_main
 /*------------------------------------------------------------------------------*/
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 	mov	pc, lr
 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
 	 */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c5, 0	/* flush v4 I-cache */
 	mcr	p15, 0, r0, c7, c6, 0	/* flush v4 D-cache */
 	/*
 	 * disable MMU stuff and caches
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
 	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
 	mcr	p15, 0, r0, c1, c0, 0
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
 	mov	ip, lr		/* perserve link reg across call */
 	bl	lowlevel_init	/* go setup memory */
 	mov	lr, ip		/* restore link */
 	mov	pc, lr		/* back to my caller */
 #endif
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC 0x13
 #define I_BIT	 0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */
 	.macro	bad_save_user_regs
 	@ carve out a frame on current user stack
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
 	ldr	r2, IRQ_STACK_START_IN
 	@ get values for "aborted" pc and cpsr (into parm regs)
 	ldmia	r2, {r2 - r3}
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
 	mov	r0, sp		@ save current stack into r0 (param register)
 	.endm
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 	add	r8, sp, #S_PC
 	stmdb	r8, {sp, lr}^		@ Calling SP, LR
 	str	lr, [r8, #0]		@ Save calling PC
 	mrs	r6, spsr
 	str	r6, [r8, #4]		@ Save CPSR
 	str	r0, [r8, #8]		@ Save OLD_R0
 	mov	r0, sp
 	.endm
 	.macro	irq_restore_user_regs
 	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
 	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
 	str	lr, [r13]	@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr	@ get the spsr
 	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
 	mov	r13, #MODE_SVC	@ prepare SVC-Mode
 	@ msr	spsr_c, r13
 	msr	spsr, r13	@ switch modes, make sure moves will execute
 	mov	lr, pc		@ capture return pc
 	movs	pc, lr		@ jump to next instruction & switch modes.
 	.endm
 	.macro get_irq_stack			@ setup IRQ stack
 	ldr	sp, IRQ_STACK_START
 	.endm
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
 /*
  * exception handlers
  */
 	.align  5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 #ifdef CONFIG_USE_IRQ
 	.align	5
 irq:
 	get_irq_stack
 	irq_save_user_regs
 	bl	do_irq
 	irq_restore_user_regs
 	.align	5
 fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
 	bl	do_fiq
 	irq_restore_user_regs
 #else
 	.align	5
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif
 # ifdef CONFIG_INTEGRATOR
 	/* Satisfied by general board level routine */
 #else
 	.align	5
 .globl reset_cpu
 reset_cpu:
 	ldr	r1, rstctl1	/* get clkm1 reset ctl */
 	mov	r3, #0x0
 	strh	r3, [r1]	/* clear it */
 	mov	r3, #0x8
 	strh	r3, [r1]	/* force dsp+arm reset */
 _loop_forever:
 	b	_loop_forever
 rstctl1:
 	.word	0xfffece10
 #endif	/* #ifdef CONFIG_INTEGRATOR */

arch/arm/cpu/arm_intcm/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for ARM926EJS CPU-core
  *
  *  Copyright (c) 2003  Texas Instruments
  *
  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  *
  *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
  *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
  *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
  *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
  *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 /*
  *************************************************************************
  *
  * Jump vector table
  *
  *************************************************************************
  */
 .globl _start
 _start:
 	b	reset
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 _undefined_instruction:
 	.word undefined_instruction
 _software_interrupt:
 	.word software_interrupt
 _prefetch_abort:
 	.word prefetch_abort
 _data_abort:
 	.word data_abort
 _not_used:
 	.word not_used
 _irq:
 	.word irq
 _fiq:
 	.word fiq
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
  * setup memory and board specific bits prior to relocation.
  * relocate armboot to ram
  * setup stack
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 reset:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
 	mrs	r0,cpsr
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 	bl	_main
 /*------------------------------------------------------------------------------*/
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 	mov	pc, lr
 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*  arm_int_generic assumes the ARM boot monitor, or user software,
 	 * has initialized the platform
 	 */
 	mov	pc, lr		/* back to my caller */
 #endif
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC 0x13
 #define I_BIT	 0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */
 	.macro	bad_save_user_regs
 	@ carve out a frame on current user stack
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
 	ldr	r2, IRQ_STACK_START_IN
 	@ get values for "aborted" pc and cpsr (into parm regs)
 	ldmia	r2, {r2 - r3}
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
 	mov	r0, sp		@ save current stack into r0 (param register)
 	.endm
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 	add	r8, sp, #S_PC
 	stmdb	r8, {sp, lr}^		@ Calling SP, LR
 	str	lr, [r8, #0]		@ Save calling PC
 	mrs	r6, spsr
 	str	r6, [r8, #4]		@ Save CPSR
 	str	r0, [r8, #8]		@ Save OLD_R0
 	mov	r0, sp
 	.endm
 	.macro	irq_restore_user_regs
 	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
 	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
 	str	lr, [r13]	@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr	@ get the spsr
 	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
 	mov	r13, #MODE_SVC	@ prepare SVC-Mode
 	@ msr	spsr_c, r13
 	msr	spsr, r13	@ switch modes, make sure moves will execute
 	mov	lr, pc		@ capture return pc
 	movs	pc, lr		@ jump to next instruction & switch modes.
 	.endm
 	.macro get_irq_stack			@ setup IRQ stack
 	ldr	sp, IRQ_STACK_START
 	.endm
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
 /*
  * exception handlers
  */
 	.align  5
 .globl undefined_instruction
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 .globl software_interrupt
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 .globl prefetch_abort
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 .globl data_abort
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 .globl not_used
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 #ifdef CONFIG_USE_IRQ
 	.align	5
 .globl irq
 irq:
 	get_irq_stack
 	irq_save_user_regs
 	bl	do_irq
 	irq_restore_user_regs
 	.align	5
 .globl fiq
 fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
 	bl	do_fiq
 	irq_restore_user_regs
 #else
 	.align	5
 .globl irq
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 .globl fiq
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif

arch/arm/cpu/armv7/omap3/lowlevel_init.S

Diff comments View file @ b60eff3

 /*
  * Board specific setup info
  *
  * (C) Copyright 2008
  * Texas Instruments, <www.ti.com>
  *
  * Initial Code by:
  * Richard Woodruff <r-woodruff2@ti.com>
  * Syed Mohammed Khasim <khasim@ti.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
 #include <version.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/clocks_omap3.h>
 #include <linux/linkage.h>
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
 #ifdef CONFIG_SPL_BUILD
 ENTRY(save_boot_params)
 	ldr	r4, =omap3_boot_device
 	ldr	r5, [r0, #0x4]
 	and	r5, r5, #0xff
 	str	r5, [r4]
 	bx	lr
 ENDPROC(save_boot_params)
 #endif
 ENTRY(omap3_gp_romcode_call)
 	PUSH {r4-r12, lr} @ Save all registers from ROM code!
 	MOV r12, r0	@ Copy the Service ID in R12
 	MOV r0, r1	@ Copy parameter to R0
 	mcr     p15, 0, r0, c7, c10, 4	@ DSB
 	mcr     p15, 0, r0, c7, c10, 5	@ DMB
 	.word	0xe1600070	@ SMC #0 to enter monitor - hand assembled
 				@ because we use -march=armv5
 	POP {r4-r12, pc}
 ENDPROC(omap3_gp_romcode_call)
 /*
  * Funtion for making PPA HAL API calls in secure devices
  * Input:
  *	R0 - Service ID
  *	R1 - paramer list
  */
 ENTRY(do_omap3_emu_romcode_call)
 	PUSH {r4-r12, lr} @ Save all registers from ROM code!
 	MOV r12, r0	@ Copy the Secure Service ID in R12
 	MOV r3, r1	@ Copy the pointer to va_list in R3
 	MOV r1, #0	@ Process ID - 0
 	MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL	@ Copy the pointer
 							@ to va_list in R3
 	MOV r6, #0xFF	@ Indicate new Task call
 	mcr     p15, 0, r0, c7, c10, 4	@ DSB
 	mcr     p15, 0, r0, c7, c10, 5	@ DMB
 	.word	0xe1600071	@ SMC #1 to call PPA service - hand assembled
 				@ because we use -march=armv5
 	POP {r4-r12, pc}
 ENDPROC(do_omap3_emu_romcode_call)
 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
 /**************************************************************************
  * cpy_clk_code: relocates clock code into SRAM where its safer to execute
  * R1 = SRAM destination address.
  *************************************************************************/
 ENTRY(cpy_clk_code)
 	/* Copy DPLL code into SRAM */
 	adr	r0, go_to_speed		/* copy from start of go_to_speed... */
 	adr	r2, lowlevel_init	/* ... up to start of low_level_init */
 next2:
 	ldmia	r0!, {r3 - r10}		/* copy from source address [r0] */
 	stmia	r1!, {r3 - r10}		/* copy to   target address [r1] */
 	cmp	r0, r2			/* until source end address [r2] */
 	blo	next2
 	mov	pc, lr			/* back to caller */
 ENDPROC(cpy_clk_code)
 /* ***************************************************************************
  *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
  *               -executed from SRAM.
  *  R0 = CM_CLKEN_PLL-bypass value
  *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
  *  R2 = CM_CLKSEL_CORE-divider values
  *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
  *
  *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
  *        confused.  A reset of the controller gets it back.  Taking away its
  *        L3 when its not in self refresh seems bad for it.  Normally, this
  *	  code runs from flash before SDR is init so that should be ok.
  ****************************************************************************/
 ENTRY(go_to_speed)
 	stmfd sp!, {r4 - r6}
 	/* move into fast relock bypass */
 	ldr	r4, pll_ctl_add
 	str	r0, [r4]
 wait1:
 	ldr	r5, [r3]		/* get status */
 	and	r5, r5, #0x1		/* isolate core status */
 	cmp	r5, #0x1		/* still locked? */
 	beq	wait1			/* if lock, loop */
 	/* set new dpll dividers _after_ in bypass */
 	ldr	r5, pll_div_add1
 	str	r1, [r5]		/* set m, n, m2 */
 	ldr	r5, pll_div_add2
 	str	r2, [r5]		/* set l3/l4/.. dividers*/
 	ldr	r5, pll_div_add3	/* wkup */
 	ldr	r2, pll_div_val3	/* rsm val */
 	str	r2, [r5]
 	ldr	r5, pll_div_add4	/* gfx */
 	ldr	r2, pll_div_val4
 	str	r2, [r5]
 	ldr	r5, pll_div_add5	/* emu */
 	ldr	r2, pll_div_val5
 	str	r2, [r5]
 	/* now prepare GPMC (flash) for new dpll speed */
 	/* flash needs to be stable when we jump back to it */
 	ldr	r5, flash_cfg3_addr
 	ldr	r2, flash_cfg3_val
 	str	r2, [r5]
 	ldr	r5, flash_cfg4_addr
 	ldr	r2, flash_cfg4_val
 	str	r2, [r5]
 	ldr	r5, flash_cfg5_addr
 	ldr	r2, flash_cfg5_val
 	str	r2, [r5]
 	ldr	r5, flash_cfg1_addr
 	ldr	r2, [r5]
 	orr	r2, r2, #0x3		/* up gpmc divider */
 	str	r2, [r5]
 	/* lock DPLL3 and wait a bit */
 	orr	r0, r0, #0x7	/* set up for lock mode */
 	str	r0, [r4]	/* lock */
 	nop			/* ARM slow at this point working at sys_clk */
 	nop
 	nop
 	nop
 wait2:
 	ldr	r5, [r3]	/* get status */
 	and	r5, r5, #0x1	/* isolate core status */
 	cmp	r5, #0x1	/* still locked? */
 	bne	wait2		/* if lock, loop */
 	nop
 	nop
 	nop
 	nop
 	ldmfd	sp!, {r4 - r6}
 	mov	pc, lr		/* back to caller, locked */
 ENDPROC(go_to_speed)
 _go_to_speed: .word go_to_speed
 /* these constants need to be close for PIC code */
 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
 flash_cfg1_addr:
 	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
 flash_cfg3_addr:
 	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
 flash_cfg3_val:
 	.word STNOR_GPMC_CONFIG3
 flash_cfg4_addr:
 	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
 flash_cfg4_val:
 	.word STNOR_GPMC_CONFIG4
 flash_cfg5_val:
 	.word STNOR_GPMC_CONFIG5
 flash_cfg5_addr:
 	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
 pll_ctl_add:
 	.word CM_CLKEN_PLL
 pll_div_add1:
 	.word CM_CLKSEL1_PLL
 pll_div_add2:
 	.word CM_CLKSEL_CORE
 pll_div_add3:
 	.word CM_CLKSEL_WKUP
 pll_div_val3:
 	.word (WKUP_RSM << 1)
 pll_div_add4:
 	.word CM_CLKSEL_GFX
 pll_div_val4:
 	.word (GFX_DIV << 0)
 pll_div_add5:
 	.word CM_CLKSEL1_EMU
 pll_div_val5:
 	.word CLSEL1_EMU_VAL
 #endif
 ENTRY(lowlevel_init)
 	ldr	sp, SRAM_STACK
 	str	ip, [sp]	/* stash ip register */
 	mov	ip, lr		/* save link reg across call */
 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
 /*
  * No need to copy/exec the clock code - DPLL adjust already done
  * in NAND/oneNAND Boot.
  */
 	ldr	r1, =SRAM_CLK_CODE
 	bl	cpy_clk_code
 #endif /* NAND Boot */
 	mov	lr, ip		/* restore link reg */
 	ldr	ip, [sp]	/* restore save ip */
 	/* tail-call s_init to setup pll, mux, memory */
 	b	s_init
 ENDPROC(lowlevel_init)
 	/* the literal pools origin */
 	.ltorg
 REG_CONTROL_STATUS:
 	.word CONTROL_STATUS
 SRAM_STACK:
 	.word LOW_LEVEL_SRAM_STACK
 /* DPLL(1-4) PARAM TABLES */
 /*
  * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
  * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
  * The values are defined for all possible sysclk and for ES1 and ES2.
  */
 mpu_dpll_param:
 /* 12MHz */
 /* ES1 */
 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
 /* ES2 */
 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
 /* 3410 */
 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
 /* 13MHz */
 /* ES1 */
 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
 /* ES2 */
 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
 /* 3410 */
 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
 /* 19.2MHz */
 /* ES1 */
 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
 /* ES2 */
 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
 /* 3410 */
 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
 /* 26MHz */
 /* ES1 */
 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
 /* ES2 */
 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
 /* 3410 */
 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
 /* 38.4MHz */
 /* ES1 */
 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
 /* ES2 */
 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
 /* 3410 */
 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
 .globl get_mpu_dpll_param
 get_mpu_dpll_param:
 	adr	r0, mpu_dpll_param
 	mov	pc, lr
 iva_dpll_param:
 /* 12MHz */
 /* ES1 */
 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
 /* ES2 */
 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
 /* 3410 */
 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
 /* 13MHz */
 /* ES1 */
 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
 /* ES2 */
 .word IVA_M_13_ES2, IVA_N_13_ES2,  IVA_FSEL_13_ES2, IVA_M2_13_ES2
 /* 3410 */
 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
 /* 19.2MHz */
 /* ES1 */
 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
 /* ES2 */
 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
 /* 3410 */
 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
 /* 26MHz */
 /* ES1 */
 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
 /* ES2 */
 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
 /* 3410 */
 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
 /* 38.4MHz */
 /* ES1 */
 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
 /* ES2 */
 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
 /* 3410 */
 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
 .globl get_iva_dpll_param
 get_iva_dpll_param:
 	adr	r0, iva_dpll_param
 	mov	pc, lr
 /* Core DPLL targets for L3 at 166 & L133 */
 core_dpll_param:
 /* 12MHz */
 /* ES1 */
 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
 /* ES2 */
 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
 /* 3410 */
 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
 /* 13MHz */
 /* ES1 */
 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
 /* ES2 */
 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
 /* 3410 */
 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
 /* 19.2MHz */
 /* ES1 */
 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
 /* ES2 */
 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
 /* 3410 */
 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
 /* 26MHz */
 /* ES1 */
 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
 /* ES2 */
 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
 /* 3410 */
 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
 /* 38.4MHz */
 /* ES1 */
 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
 /* ES2 */
 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
 /* 3410 */
 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
 .globl get_core_dpll_param
 get_core_dpll_param:
 	adr	r0, core_dpll_param
 	mov	pc, lr
 /* PER DPLL values are same for both ES1 and ES2 */
 per_dpll_param:
 /* 12MHz */
 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
 /* 13MHz */
 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
 /* 19.2MHz */
 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
 /* 26MHz */
 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
 /* 38.4MHz */
 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
 .globl get_per_dpll_param
 get_per_dpll_param:
 	adr	r0, per_dpll_param
 	mov	pc, lr
 /* PER2 DPLL values */
 per2_dpll_param:
 /* 12MHz */
 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
 /* 13MHz */
 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
 /* 19.2MHz */
 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
 /* 26MHz */
 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
 /* 38.4MHz */
 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
 .globl get_per2_dpll_param
 get_per2_dpll_param:
 	adr	r0, per2_dpll_param
 	mov	pc, lr
 /*
  * Tables for 36XX/37XX devices
  *
  */
 mpu_36x_dpll_param:
 /* 12MHz */
 .word 50, 0, 0, 1
 /* 13MHz */
 .word 600, 12, 0, 1
 /* 19.2MHz */
 .word 125, 3, 0, 1
 /* 26MHz */
 .word 300, 12, 0, 1
 /* 38.4MHz */
 .word 125, 7, 0, 1
 iva_36x_dpll_param:
 /* 12MHz */
 .word 130, 2, 0, 1
 /* 13MHz */
 .word 20, 0, 0, 1
 /* 19.2MHz */
 .word 325, 11, 0, 1
 /* 26MHz */
 .word 10, 0, 0, 1
 /* 38.4MHz */
 .word 325, 23, 0, 1
 core_36x_dpll_param:
 /* 12MHz */
 .word 100, 2, 0, 1
 /* 13MHz */
 .word 400, 12, 0, 1
 /* 19.2MHz */
 .word 375, 17, 0, 1
 /* 26MHz */
 .word 200, 12, 0, 1
 /* 38.4MHz */
 .word 375, 35, 0, 1
 per_36x_dpll_param:
 /*    SYSCLK    M       N      M2      M3      M4     M5      M6      m2DIV */
 .word 12000,    360,    4,     9,      16,     5,     4,      3,      1
 .word 13000,    864,   12,     9,      16,     9,     4,      3,      1
 .word 19200,    360,    7,     9,      16,     5,     4,      3,      1
 .word 26000,    432,   12,     9,      16,     9,     4,      3,      1
 .word 38400,    360,   15,     9,      16,     5,     4,      3,      1
 per2_36x_dpll_param:
 /* 12MHz */
 .word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
 /* 13MHz */
 .word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
 /* 19.2MHz */
 .word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
 /* 26MHz */
 .word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
 /* 38.4MHz */
 .word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
 ENTRY(get_36x_mpu_dpll_param)
 	adr	r0, mpu_36x_dpll_param
 	mov	pc, lr
 ENDPROC(get_36x_mpu_dpll_param)
 ENTRY(get_36x_iva_dpll_param)
 	adr	r0, iva_36x_dpll_param
 	mov	pc, lr
 ENDPROC(get_36x_iva_dpll_param)
 ENTRY(get_36x_core_dpll_param)
 	adr	r0, core_36x_dpll_param
 	mov	pc, lr
 ENDPROC(get_36x_core_dpll_param)
 ENTRY(get_36x_per_dpll_param)
 	adr	r0, per_36x_dpll_param
 	mov	pc, lr
 ENDPROC(get_36x_per_dpll_param)
 ENTRY(get_36x_per2_dpll_param)
 	adr	r0, per2_36x_dpll_param
 	mov	pc, lr
 ENDPROC(get_36x_per2_dpll_param)

arch/arm/cpu/armv7/start.S

Diff comments View file @ b60eff3

 /*
  * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
  *
  * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
  *
  * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
  * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
  * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
  * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
  * Copyright (c) 2003	Kshitij <kshitij@ti.com>
  * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 #include <asm/system.h>
 #include <linux/linkage.h>
 .globl _start
 _start: b	reset
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 #ifdef CONFIG_SPL_BUILD
 _undefined_instruction: .word _undefined_instruction
 _software_interrupt:	.word _software_interrupt
 _prefetch_abort:	.word _prefetch_abort
 _data_abort:		.word _data_abort
 _not_used:		.word _not_used
 _irq:			.word _irq
 _fiq:			.word _fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #else
 .globl _undefined_instruction
 _undefined_instruction: .word undefined_instruction
 .globl _software_interrupt
 _software_interrupt:	.word software_interrupt
 .globl _prefetch_abort
 _prefetch_abort:	.word prefetch_abort
 .globl _data_abort
 _data_abort:		.word data_abort
 .globl _not_used
 _not_used:		.word not_used
 .globl _irq
 _irq:			.word irq
 .globl _fiq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #endif	/* CONFIG_SPL_BUILD */
 .global _end_vect
 _end_vect:
 	.balignl 16,0xdeadbeef
 /*************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
  * setup Memory and board specific bits prior to relocation.
  * relocate armboot to ram
  * setup stack
  *
  *************************************************************************/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 reset:
 	bl	save_boot_params
 	/*
 	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
 	 * except if in HYP mode already
 	 */
 	mrs	r0, cpsr
 	and	r1, r0, #0x1f		@ mask mode bits
 	teq	r1, #0x1a		@ test for HYP mode
 	bicne	r0, r0, #0x1f		@ clear all mode bits
 	orrne	r0, r0, #0x13		@ set SVC mode
 	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
 	msr	cpsr,r0
 /*
  * Setup vector:
  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
  * Continue to use ROM code vector only in OMAP4 spl)
  */
 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
 	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
 	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
 	bic	r0, #CR_V		@ V = 0
 	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register
 	/* Set vector address in CP15 VBAR register */
 	ldr	r0, =_start
 	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
 #endif
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_cp15
 	bl	cpu_init_crit
 #endif
 	bl	_main
 /*------------------------------------------------------------------------------*/
 ENTRY(c_runtime_cpu_setup)
 /*
  * If I-cache is enabled invalidate it
  */
 #ifndef CONFIG_SYS_ICACHE_OFF
 	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
 	mcr     p15, 0, r0, c7, c10, 4	@ DSB
 	mcr     p15, 0, r0, c7, c5, 4	@ ISB
 #endif
 /*
  * Move vector table
  */
 	/* Set vector address in CP15 VBAR register */
 	ldr     r0, =_start
 	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
 	bx	lr
 ENDPROC(c_runtime_cpu_setup)
 /*************************************************************************
  *
  * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
  *	__attribute__((weak));
  *
  * Stack pointer is not yet initialized at this moment
  * Don't save anything to stack even if compiled with -O0
  *
  *************************************************************************/
 ENTRY(save_boot_params)
 	bx	lr			@ back to my caller
 ENDPROC(save_boot_params)
 	.weak	save_boot_params
 /*************************************************************************
  *
  * cpu_init_cp15
  *
  * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
  * CONFIG_SYS_ICACHE_OFF is defined.
  *
  *************************************************************************/
 ENTRY(cpu_init_cp15)
 	/*
 	 * Invalidate L1 I/D
 	 */
 	mov	r0, #0			@ set up for MCR
 	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
 	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
 	mcr     p15, 0, r0, c7, c10, 4	@ DSB
 	mcr     p15, 0, r0, c7, c5, 4	@ ISB
 	/*
 	 * disable MMU stuff and caches
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
 	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
 	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
 	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
 #ifdef CONFIG_SYS_ICACHE_OFF
 	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
 #else
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
 #endif
 	mcr	p15, 0, r0, c1, c0, 0
 #ifdef CONFIG_ARM_ERRATA_716044
 	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
 	orr	r0, r0, #1 << 11	@ set bit #11
 	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
 #endif
 #ifdef CONFIG_ARM_ERRATA_742230
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 4		@ set bit #4
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
 #ifdef CONFIG_ARM_ERRATA_743622
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 6		@ set bit #6
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
 #ifdef CONFIG_ARM_ERRATA_751472
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 11	@ set bit #11
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 /*************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************/
 ENTRY(cpu_init_crit)
 	/*
 	 * Jump to board specific initialization...
 	 * The Mask ROM will have already initialized
 	 * basic memory. Go here to bump up clock rate and handle
 	 * wake up conditions.
 	 */
 	b	lowlevel_init		@ go setup pll,mux,memory
 ENDPROC(cpu_init_crit)
 #endif
 #ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC 0x13
 #define I_BIT	 0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
 						@ user stack
 	stmia	sp, {r0 - r12}			@ Save user registers (now in
 						@ svc mode) r0-r12
 	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort
 						@ stack
 	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
 						@ and cpsr (into parm regs)
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
 	mov	r0, sp				@ save current stack into r0
 						@ (param register)
 	.endm
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
 						@ a reserved stack spot would
 						@ be good.
 	stmdb	r8, {sp, lr}^			@ Calling SP, LR
 	str	lr, [r8, #0]			@ Save calling PC
 	mrs	r6, spsr
 	str	r6, [r8, #4]			@ Save CPSR
 	str	r0, [r8, #8]			@ Save OLD_R0
 	mov	r0, sp
 	.endm
 	.macro	irq_restore_user_regs
 	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
 	subs	pc, lr, #4			@ return & move spsr_svc into
 						@ cpsr
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter
 						@ in banked mode)
 	str	lr, [r13]			@ save caller lr in position 0
 						@ of saved stack
 	mrs	lr, spsr			@ get the spsr
 	str	lr, [r13, #4]			@ save spsr in position 1 of
 						@ saved stack
 	mov	r13, #MODE_SVC			@ prepare SVC-Mode
 	@ msr	spsr_c, r13
 	msr	spsr, r13			@ switch modes, make sure
 						@ moves will execute
 	mov	lr, pc				@ capture return pc
 	movs	pc, lr				@ jump to next instruction &
 						@ switch modes.
 	.endm
 	.macro get_bad_stack_swi
 	sub	r13, r13, #4			@ space on current stack for
 						@ scratch reg.
 	str	r0, [r13]			@ save R0's value.
 	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
 						@ spots for abort stack
 	str	lr, [r0]			@ save caller lr in position 0
 						@ of saved stack
 	mrs	lr, spsr			@ get the spsr
 	str	lr, [r0, #4]			@ save spsr in position 1 of
 						@ saved stack
 	ldr	lr, [r0]			@ restore lr
 	ldr	r0, [r13]			@ restore r0
 	add	r13, r13, #4			@ pop stack entry
 	.endm
 	.macro get_irq_stack			@ setup IRQ stack
 	ldr	sp, IRQ_STACK_START
 	.endm
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
 /*
  * exception handlers
  */
 	.align	5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 software_interrupt:
 	get_bad_stack_swi
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 #ifdef CONFIG_USE_IRQ
 	.align	5
 irq:
 	get_irq_stack
 	irq_save_user_regs
 	bl	do_irq
 	irq_restore_user_regs
 	.align	5
 fiq:
 	get_fiq_stack
 	/* someone ought to write a more effective fiq_save_user_regs */
 	irq_save_user_regs
 	bl	do_fiq
 	irq_restore_user_regs
 #else
 	.align	5
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif /* CONFIG_USE_IRQ */
 #endif /* CONFIG_SPL_BUILD */

arch/arm/cpu/pxa/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for XScale CPU-core
  *
  *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
  *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
  *  Copyright (C) 2001	Alex Zuepke <azu@sysgo.de>
  *  Copyright (C) 2001	Marius Groger <mag@sysgo.de>
  *  Copyright (C) 2002	Alex Zupke <azu@sysgo.de>
  *  Copyright (C) 2002	Gary Jennejohn <garyj@denx.de>
  *  Copyright (C) 2002	Kyle Harris <kharris@nexus-tech.net>
  *  Copyright (C) 2003	Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
  *  Copyright (C) 2003	Kshitij <kshitij@ti.com>
  *  Copyright (C) 2003	Richard Woodruff <r-woodruff2@ti.com>
  *  Copyright (C) 2003	Robert Schwebel <r.schwebel@pengutronix.de>
  *  Copyright (C) 2004	Texas Instruments <r-woodruff2@ti.com>
  *  Copyright (C) 2010	Marek Vasut <marek.vasut@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 #ifdef CONFIG_CPU_PXA25X
 #if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
 #error "Init SP address must be set to 0xfffff800 for PXA250"
 #endif
 #endif
 .globl _start
 _start: b	reset
 #ifdef CONFIG_SPL_BUILD
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 	ldr	pc, _hang
 _hang:
 	.word	do_hang
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678
 	.word	0x12345678	/* now 16*4=64 */
 #else
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
 _data_abort:		.word data_abort
 _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #endif	/* CONFIG_SPL_BUILD */
 .global _end_vect
 _end_vect:
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
  * setup Memory and board specific bits prior to relocation.
  * relocate armboot to ram
  * setup stack
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 reset:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
 	mrs	r0,cpsr
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl  cpu_init_crit
 #endif
 #ifdef	CONFIG_CPU_PXA25X
 	bl	lock_cache_for_stack
 #endif
 	bl	_main
 /*------------------------------------------------------------------------------*/
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 #ifdef CONFIG_CPU_PXA25X
 	/*
 	 * Unlock (actually, disable) the cache now that board_init_f
 	 * is done. We could do this earlier but we would need to add
 	 * a new C runtime hook, whereas c_runtime_cpu_setup already
 	 * exists.
 	 * As this routine is just a call to cpu_init_crit, let us
 	 * tail-optimize and do a simple branch here.
 	 */
 	b	cpu_init_crit
 #else
 	bx	lr
 #endif
 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */
 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
 	 */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
 	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
 	/*
 	 * disable MMU stuff and caches
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00003300	@ clear bits 13:12, 9:8 (--VI --RS)
 	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
 	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
 	mcr	p15, 0, r0, c1, c0, 0
 	mov	pc, lr		/* back to my caller */
 #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
 #ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC 0x13
 #define I_BIT	 0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
 	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
 	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
 	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
 	mov	r0, sp				@ save current stack into r0 (param register)
 	.endm
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 	stmdb	r8, {sp, lr}^			@ Calling SP, LR
 	str	lr, [r8, #0]			@ Save calling PC
 	mrs	r6, spsr
 	str	r6, [r8, #4]			@ Save CPSR
 	str	r0, [r8, #8]			@ Save OLD_R0
 	mov	r0, sp
 	.endm
 	.macro	irq_restore_user_regs
 	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
 	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
 	str	lr, [r13]			@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr			@ get the spsr
 	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
 	mov	r13, #MODE_SVC			@ prepare SVC-Mode
 	@ msr	spsr_c, r13
 	msr	spsr, r13			@ switch modes, make sure moves will execute
 	mov	lr, pc				@ capture return pc
 	movs	pc, lr				@ jump to next instruction & switch modes.
 	.endm
 	.macro get_bad_stack_swi
 	sub	r13, r13, #4			@ space on current stack for scratch reg.
 	str	r0, [r13]			@ save R0's value.
 	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
 	str	lr, [r0]			@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr			@ get the spsr
 	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
 	ldr	lr, [r0]			@ restore lr
 	ldr	r0, [r13]			@ restore r0
 	add	r13, r13, #4			@ pop stack entry
 	.endm
 	.macro get_irq_stack			@ setup IRQ stack
 	ldr	sp, IRQ_STACK_START
 	.endm
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
 #endif	/* CONFIG_SPL_BUILD */
 /*
  * exception handlers
  */
 #ifdef CONFIG_SPL_BUILD
 	.align	5
 do_hang:
-	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
 	bl	hang				/* hang and never return */
 #else	/* !CONFIG_SPL_BUILD */
 	.align	5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 software_interrupt:
 	get_bad_stack_swi
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 #ifdef CONFIG_USE_IRQ
 	.align	5
 irq:
 	get_irq_stack
 	irq_save_user_regs
 	bl	do_irq
 	irq_restore_user_regs
 	.align	5
 fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
 	bl	do_fiq
 	irq_restore_user_regs
 #else
 	.align	5
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif
 	.align 5
 #endif	/* CONFIG_SPL_BUILD */
 /*
  * Enable MMU to use DCache as DRAM.
  *
  * This is useful on PXA25x and PXA26x in early bootstages, where there is no
  * other possible memory available to hold stack.
  */
 #ifdef CONFIG_CPU_PXA25X
 .macro CPWAIT reg
 	mrc	p15, 0, \reg, c2, c0, 0
 	mov	\reg, \reg
 	sub	pc, pc, #4
 .endm
 lock_cache_for_stack:
 	/* Domain access -- enable for all CPs */
 	ldr	r0, =0x0000ffff
 	mcr	p15, 0, r0, c3, c0, 0
 	/* Point TTBR to MMU table */
 	ldr	r0, =mmutable
 	mcr	p15, 0, r0, c2, c0, 0
 	/* Kick in MMU, ICache, DCache, BTB */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, #0x1b00
 	bic	r0, #0x0087
 	orr	r0, #0x1800
 	orr	r0, #0x0005
 	mcr	p15, 0, r0, c1, c0, 0
 	CPWAIT	r0
 	/* Unlock Icache, Dcache */
 	mcr	p15, 0, r0, c9, c1, 1
 	mcr	p15, 0, r0, c9, c2, 1
 	/* Flush Icache, Dcache, BTB */
 	mcr	p15, 0, r0, c7, c7, 0
 	/* Unlock I-TLB, D-TLB */
 	mcr	p15, 0, r0, c10, c4, 1
 	mcr	p15, 0, r0, c10, c8, 1
 	/* Flush TLB */
 	mcr	p15, 0, r0, c8, c7, 0
 	/* Allocate 4096 bytes of Dcache as RAM */
 	/* Drain pending loads and stores */
 	mcr	p15, 0, r0, c7, c10, 4
 	mov	r4, #0x00
 	mov	r5, #0x00
 	mov	r2, #0x01
 	mcr	p15, 0, r0, c9, c2, 0
 	CPWAIT	r0
 	/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
 	mov	r0, #128
 	ldr	r1, =0xfffff000
 alloc:
 	mcr	p15, 0, r1, c7, c2, 5
 	/* Drain pending loads and stores */
 	mcr	p15, 0, r0, c7, c10, 4
 	strd	r4, [r1], #8
 	strd	r4, [r1], #8
 	strd	r4, [r1], #8
 	strd	r4, [r1], #8
 	subs	r0, #0x01
 	bne	alloc
 	/* Drain pending loads and stores */
 	mcr	p15, 0, r0, c7, c10, 4
 	mov	r2, #0x00
 	mcr	p15, 0, r2, c9, c2, 0
 	CPWAIT	r0
 	mov	pc, lr
 .section .mmutable, "a"
 mmutable:
 	.align	14
 	/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
 	.set	__base, 0
 	.rept	0xfff
 	.word	(__base << 20) | 0xc12
 	.set	__base, __base + 1
 	.endr
 	/* 0xfff00000 : 1:1, cached mapping */
 	.word	(0xfff << 20) | 0x1c1e
 #endif	/* CONFIG_CPU_PXA25X */

arch/arm/cpu/sa1100/start.S

Diff comments View file @ b60eff3

 /*
  *  armboot - Startup Code for SA1100 CPU
  *
  *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
  *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
  *  Copyright (c) 2001	Alex Züpke <azu@sysgo.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 /*
  *************************************************************************
  *
  * Jump vector table as in table 3.1 in [1]
  *
  *************************************************************************
  */
 .globl _start
 _start:	b       reset
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
 _undefined_instruction:	.word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
 _data_abort:		.word data_abort
 _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
  * relocate armboot to ram
  * setup stack
  * jump to second stage
  *
  *************************************************************************
  */
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
 IRQ_STACK_START:
 	.word	0x0badc0de
 /* IRQ stack memory (calculated at run-time) */
 .globl FIQ_STACK_START
 FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 /*
  * the actual reset code
  */
 reset:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
 	mrs	r0,cpsr
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 	bl	_main
 /*------------------------------------------------------------------------------*/
 	.globl	c_runtime_cpu_setup
 c_runtime_cpu_setup:
 	mov	pc, lr
 /*
  *************************************************************************
  *
  * CPU_init_critical registers
  *
  * setup important registers
  * setup memory timing
  *
  *************************************************************************
  */
 /* Interrupt-Controller base address */
 IC_BASE:	.word	0x90050000
 #define ICMR	0x04
 /* Reset-Controller */
 RST_BASE:		.word   0x90030000
 #define RSRR	0x00
 #define RCSR	0x04
 /* PWR */
 PWR_BASE:		.word   0x90020000
 #define PSPR    0x08
 #define PPCR    0x14
 cpuspeed:		.word   CONFIG_SYS_CPUSPEED
 cpu_init_crit:
 	/*
 	 * mask all IRQs
 	 */
 	ldr	r0, IC_BASE
 	mov	r1, #0x00
 	str	r1, [r0, #ICMR]
 	/* set clock speed */
 	ldr	r0, PWR_BASE
 	ldr	r1, cpuspeed
 	str	r1, [r0, #PPCR]
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependend, you will
 	 * find a lowlevel_init.S in your board directory.
 	 */
 	mov	ip,	lr
 	bl	lowlevel_init
 	mov	lr,	ip
 	/*
 	 * disable MMU stuff and enable I-cache
 	 */
 	mrc	p15,0,r0,c1,c0
 	bic	r0, r0, #0x00002000	@ clear bit 13 (X)
 	bic	r0, r0, #0x0000000f	@ clear bits 3-0 (WCAM)
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) Icache
 	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
 	mcr	p15,0,r0,c1,c0
 	/*
 	 * flush v4 I/D caches
 	 */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
 	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
 	mov	pc, lr
 /*
  *************************************************************************
  *
  * Interrupt handling
  *
  *************************************************************************
  */
 @
 @ IRQ stack frame.
 @
 #define S_FRAME_SIZE	72
 #define S_OLD_R0	68
 #define S_PSR		64
 #define S_PC		60
 #define S_LR		56
 #define S_SP		52
 #define S_IP		48
 #define S_FP		44
 #define S_R10		40
 #define S_R9		36
 #define S_R8		32
 #define S_R7		28
 #define S_R6		24
 #define S_R5		20
 #define S_R4		16
 #define S_R3		12
 #define S_R2		8
 #define S_R1		4
 #define S_R0		0
 #define MODE_SVC 0x13
 #define I_BIT	 0x80
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  */
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add     r8, sp, #S_PC
 	ldr	r2, IRQ_STACK_START_IN
 	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 	add	r5, sp, #S_SP
 	mov	r1, lr
 	stmia	r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
 	mov	r0, sp
 	.endm
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add     r8, sp, #S_PC
 	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 	str     lr, [r8, #0]                    @ Save calling PC
 	mrs     r6, spsr
 	str     r6, [r8, #4]                    @ Save CPSR
 	str     r0, [r8, #8]                    @ Save OLD_R0
 	mov	r0, sp
 	.endm
 	.macro	irq_restore_user_regs
 	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
 	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
 	.endm
 	.macro get_bad_stack
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
 	str     lr, [r13, #4]
 	mov	r13, #MODE_SVC			@ prepare SVC-Mode
 	msr	spsr_c, r13
 	mov	lr, pc
 	movs	pc, lr
 	.endm
 	.macro get_irq_stack			@ setup IRQ stack
 	ldr	sp, IRQ_STACK_START
 	.endm
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
 /*
  * exception handlers
  */
 	.align  5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_undefined_instruction
 	.align	5
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_software_interrupt
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_prefetch_abort
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_data_abort
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_not_used
 #ifdef CONFIG_USE_IRQ
 	.align	5
 irq:
 	get_irq_stack
 	irq_save_user_regs
 	bl	do_irq
 	irq_restore_user_regs
 	.align	5
 fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
 	bl	do_fiq
 	irq_restore_user_regs
 #else
 	.align	5
 irq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_irq
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
 #endif
 	.align	5
 .globl reset_cpu
 reset_cpu:
 	ldr	r0, RST_BASE
 	mov	r1, #0x0			@ set bit 3-0 ...
 	str	r1, [r0, #RCSR]			@ ... to clear in RCSR
 	mov	r1, #0x1
 	str	r1, [r0, #RSRR]			@ and perform reset
 	b	reset_cpu			@ silly, but repeat endlessly

arch/arm/lib/board.c

Diff comments View file @ b60eff3

1	/*	1	/*
2	* (C) Copyright 2002-2006	2	* (C) Copyright 2002-2006
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* (C) Copyright 2002	5	* (C) Copyright 2002
6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7	* Marius Groeger <mgroeger@sysgo.de>	7	* Marius Groeger <mgroeger@sysgo.de>
8	*	8	*
9	* SPDX-License-Identifier: GPL-2.0+	9	* SPDX-License-Identifier: GPL-2.0+
10	*/	10	*/
11		11
12	/*	12	/*
13	* To match the U-Boot user interface on ARM platforms to the U-Boot	13	* To match the U-Boot user interface on ARM platforms to the U-Boot
14	* standard (as on PPC platforms), some messages with debug character	14	* standard (as on PPC platforms), some messages with debug character
15	* are removed from the default U-Boot build.	15	* are removed from the default U-Boot build.
16	*	16	*
17	* Define DEBUG here if you want additional info as shown below	17	* Define DEBUG here if you want additional info as shown below
18	* printed upon startup:	18	* printed upon startup:
19	*	19	*
20	* U-Boot code: 00F00000 -> 00F3C774 BSS: -> 00FC3274	20	* U-Boot code: 00F00000 -> 00F3C774 BSS: -> 00FC3274
21	* IRQ Stack: 00ebff7c	21	* IRQ Stack: 00ebff7c
22	* FIQ Stack: 00ebef7c	22	* FIQ Stack: 00ebef7c
23	*/	23	*/
24		24
25	#include <common.h>	25	#include <common.h>
26	#include <command.h>	26	#include <command.h>
27	#include <environment.h>	27	#include <environment.h>
28	#include <malloc.h>	28	#include <malloc.h>
29	#include <stdio_dev.h>	29	#include <stdio_dev.h>
30	#include <version.h>	30	#include <version.h>
31	#include <net.h>	31	#include <net.h>
32	#include <serial.h>	32	#include <serial.h>
33	#include <nand.h>	33	#include <nand.h>
34	#include <onenand_uboot.h>	34	#include <onenand_uboot.h>
35	#include <mmc.h>	35	#include <mmc.h>
36	#include <libfdt.h>	36	#include <libfdt.h>
37	#include <fdtdec.h>	37	#include <fdtdec.h>
38	#include <post.h>	38	#include <post.h>
39	#include <logbuff.h>	39	#include <logbuff.h>
40	#include <asm/sections.h>	40	#include <asm/sections.h>
41		41
42	#ifdef CONFIG_BITBANGMII	42	#ifdef CONFIG_BITBANGMII
43	#include <miiphy.h>	43	#include <miiphy.h>
44	#endif	44	#endif
45		45
46	DECLARE_GLOBAL_DATA_PTR;	46	DECLARE_GLOBAL_DATA_PTR;
47		47
48	ulong monitor_flash_len;	48	ulong monitor_flash_len;
49		49
50	#ifdef CONFIG_HAS_DATAFLASH	50	#ifdef CONFIG_HAS_DATAFLASH
51	extern int AT91F_DataflashInit(void);	51	extern int AT91F_DataflashInit(void);
52	extern void dataflash_print_info(void);	52	extern void dataflash_print_info(void);
53	#endif	53	#endif
54		54
55	#if defined(CONFIG_HARD_I2C) \|\| \	55	#if defined(CONFIG_HARD_I2C) \|\| \
56	defined(CONFIG_SYS_I2C)	56	defined(CONFIG_SYS_I2C)
57	#include <i2c.h>	57	#include <i2c.h>
58	#endif	58	#endif
59		59
60	/************************************************************************	60	/************************************************************************
61	* Coloured LED functionality	61	* Coloured LED functionality
62	************************************************************************	62	************************************************************************
63	* May be supplied by boards if desired	63	* May be supplied by boards if desired
64	*/	64	*/
65	inline void __coloured_LED_init(void) {}	65	inline void __coloured_LED_init(void) {}
66	void coloured_LED_init(void)	66	void coloured_LED_init(void)
67	__attribute__((weak, alias("__coloured_LED_init")));	67	__attribute__((weak, alias("__coloured_LED_init")));
68	inline void __red_led_on(void) {}	68	inline void __red_led_on(void) {}
69	void red_led_on(void) __attribute__((weak, alias("__red_led_on")));	69	void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
70	inline void __red_led_off(void) {}	70	inline void __red_led_off(void) {}
71	void red_led_off(void) __attribute__((weak, alias("__red_led_off")));	71	void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
72	inline void __green_led_on(void) {}	72	inline void __green_led_on(void) {}
73	void green_led_on(void) __attribute__((weak, alias("__green_led_on")));	73	void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
74	inline void __green_led_off(void) {}	74	inline void __green_led_off(void) {}
75	void green_led_off(void) __attribute__((weak, alias("__green_led_off")));	75	void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
76	inline void __yellow_led_on(void) {}	76	inline void __yellow_led_on(void) {}
77	void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));	77	void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
78	inline void __yellow_led_off(void) {}	78	inline void __yellow_led_off(void) {}
79	void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));	79	void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
80	inline void __blue_led_on(void) {}	80	inline void __blue_led_on(void) {}
81	void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));	81	void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
82	inline void __blue_led_off(void) {}	82	inline void __blue_led_off(void) {}
83	void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));	83	void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
84		84
85	/*	85	/*
86	************************************************************************	86	************************************************************************
87	* Init Utilities *	87	* Init Utilities *
88	************************************************************************	88	************************************************************************
89	* Some of this code should be moved into the core functions,	89	* Some of this code should be moved into the core functions,
90	* or dropped completely,	90	* or dropped completely,
91	* but let's get it working (again) first...	91	* but let's get it working (again) first...
92	*/	92	*/
93		93
94	#if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE)	94	#if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE)
95	#define CONFIG_BAUDRATE 115200	95	#define CONFIG_BAUDRATE 115200
96	#endif	96	#endif
97		97
98	static int init_baudrate(void)	98	static int init_baudrate(void)
99	{	99	{
100	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);	100	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
101	return 0;	101	return 0;
102	}	102	}
103		103
104	static int display_banner(void)	104	static int display_banner(void)
105	{	105	{
106	printf("\n\n%s\n\n", version_string);	106	printf("\n\n%s\n\n", version_string);
107	debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",	107	debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
108	_TEXT_BASE,	108	(ulong)&_start,
109	_bss_start_ofs + _TEXT_BASE, _bss_end_ofs + _TEXT_BASE);	109	(ulong)&__bss_start, (ulong)&__bss_end);
110	#ifdef CONFIG_MODEM_SUPPORT	110	#ifdef CONFIG_MODEM_SUPPORT
111	debug("Modem Support enabled\n");	111	debug("Modem Support enabled\n");
112	#endif	112	#endif
113	#ifdef CONFIG_USE_IRQ	113	#ifdef CONFIG_USE_IRQ
114	debug("IRQ Stack: %08lx\n", IRQ_STACK_START);	114	debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
115	debug("FIQ Stack: %08lx\n", FIQ_STACK_START);	115	debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
116	#endif	116	#endif
117		117
118	return (0);	118	return (0);
119	}	119	}
120		120
121	/*	121	/*
122	* WARNING: this code looks "cleaner" than the PowerPC version, but	122	* WARNING: this code looks "cleaner" than the PowerPC version, but
123	* has the disadvantage that you either get nothing, or everything.	123	* has the disadvantage that you either get nothing, or everything.
124	* On PowerPC, you might see "DRAM: " before the system hangs - which	124	* On PowerPC, you might see "DRAM: " before the system hangs - which
125	* gives a simple yet clear indication which part of the	125	* gives a simple yet clear indication which part of the
126	* initialization if failing.	126	* initialization if failing.
127	*/	127	*/
128	static int display_dram_config(void)	128	static int display_dram_config(void)
129	{	129	{
130	int i;	130	int i;
131		131
132	#ifdef DEBUG	132	#ifdef DEBUG
133	puts("RAM Configuration:\n");	133	puts("RAM Configuration:\n");
134		134
135	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {	135	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
136	printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);	136	printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
137	print_size(gd->bd->bi_dram[i].size, "\n");	137	print_size(gd->bd->bi_dram[i].size, "\n");
138	}	138	}
139	#else	139	#else
140	ulong size = 0;	140	ulong size = 0;
141		141
142	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)	142	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
143	size += gd->bd->bi_dram[i].size;	143	size += gd->bd->bi_dram[i].size;
144		144
145	puts("DRAM: ");	145	puts("DRAM: ");
146	print_size(size, "\n");	146	print_size(size, "\n");
147	#endif	147	#endif
148		148
149	return (0);	149	return (0);
150	}	150	}
151		151
152	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SYS_I2C)	152	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SYS_I2C)
153	static int init_func_i2c(void)	153	static int init_func_i2c(void)
154	{	154	{
155	puts("I2C: ");	155	puts("I2C: ");
156	#ifdef CONFIG_SYS_I2C	156	#ifdef CONFIG_SYS_I2C
157	i2c_init_all();	157	i2c_init_all();
158	#else	158	#else
159	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);	159	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
160	#endif	160	#endif
161	puts("ready\n");	161	puts("ready\n");
162	return (0);	162	return (0);
163	}	163	}
164	#endif	164	#endif
165		165
166	#if defined(CONFIG_CMD_PCI) \|\| defined (CONFIG_PCI)	166	#if defined(CONFIG_CMD_PCI) \|\| defined (CONFIG_PCI)
167	#include <pci.h>	167	#include <pci.h>
168	static int arm_pci_init(void)	168	static int arm_pci_init(void)
169	{	169	{
170	pci_init();	170	pci_init();
171	return 0;	171	return 0;
172	}	172	}
173	#endif /* CONFIG_CMD_PCI \|\| CONFIG_PCI */	173	#endif /* CONFIG_CMD_PCI \|\| CONFIG_PCI */
174		174
175	/*	175	/*
176	* Breathe some life into the board...	176	* Breathe some life into the board...
177	*	177	*
178	* Initialize a serial port as console, and carry out some hardware	178	* Initialize a serial port as console, and carry out some hardware
179	* tests.	179	* tests.
180	*	180	*
181	* The first part of initialization is running from Flash memory;	181	* The first part of initialization is running from Flash memory;
182	* its main purpose is to initialize the RAM so that we	182	* its main purpose is to initialize the RAM so that we
183	* can relocate the monitor code to RAM.	183	* can relocate the monitor code to RAM.
184	*/	184	*/
185		185
186	/*	186	/*
187	* All attempts to come up with a "common" initialization sequence	187	* All attempts to come up with a "common" initialization sequence
188	* that works for all boards and architectures failed: some of the	188	* that works for all boards and architectures failed: some of the
189	* requirements are just _too_ different. To get rid of the resulting	189	* requirements are just _too_ different. To get rid of the resulting
190	* mess of board dependent #ifdef'ed code we now make the whole	190	* mess of board dependent #ifdef'ed code we now make the whole
191	* initialization sequence configurable to the user.	191	* initialization sequence configurable to the user.
192	*	192	*
193	* The requirements for any new initalization function is simple: it	193	* The requirements for any new initalization function is simple: it
194	* receives a pointer to the "global data" structure as it's only	194	* receives a pointer to the "global data" structure as it's only
195	* argument, and returns an integer return code, where 0 means	195	* argument, and returns an integer return code, where 0 means
196	* "continue" and != 0 means "fatal error, hang the system".	196	* "continue" and != 0 means "fatal error, hang the system".
197	*/	197	*/
198	typedef int (init_fnc_t) (void);	198	typedef int (init_fnc_t) (void);
199		199
200	void __dram_init_banksize(void)	200	void __dram_init_banksize(void)
201	{	201	{
202	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;	202	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
203	gd->bd->bi_dram[0].size = gd->ram_size;	203	gd->bd->bi_dram[0].size = gd->ram_size;
204	}	204	}
205	void dram_init_banksize(void)	205	void dram_init_banksize(void)
206	__attribute__((weak, alias("__dram_init_banksize")));	206	__attribute__((weak, alias("__dram_init_banksize")));
207		207
208	int __arch_cpu_init(void)	208	int __arch_cpu_init(void)
209	{	209	{
210	return 0;	210	return 0;
211	}	211	}
212	int arch_cpu_init(void)	212	int arch_cpu_init(void)
213	__attribute__((weak, alias("__arch_cpu_init")));	213	__attribute__((weak, alias("__arch_cpu_init")));
214		214
215	int __power_init_board(void)	215	int __power_init_board(void)
216	{	216	{
217	return 0;	217	return 0;
218	}	218	}
219	int power_init_board(void)	219	int power_init_board(void)
220	__attribute__((weak, alias("__power_init_board")));	220	__attribute__((weak, alias("__power_init_board")));
221		221
222	/* Record the board_init_f() bootstage (after arch_cpu_init()) */	222	/* Record the board_init_f() bootstage (after arch_cpu_init()) */
223	static int mark_bootstage(void)	223	static int mark_bootstage(void)
224	{	224	{
225	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");	225	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
226		226
227	return 0;	227	return 0;
228	}	228	}
229		229
230	init_fnc_t *init_sequence[] = {	230	init_fnc_t *init_sequence[] = {
231	arch_cpu_init, /* basic arch cpu dependent setup */	231	arch_cpu_init, /* basic arch cpu dependent setup */
232	mark_bootstage,	232	mark_bootstage,
233	#ifdef CONFIG_OF_CONTROL	233	#ifdef CONFIG_OF_CONTROL
234	fdtdec_check_fdt,	234	fdtdec_check_fdt,
235	#endif	235	#endif
236	#if defined(CONFIG_BOARD_EARLY_INIT_F)	236	#if defined(CONFIG_BOARD_EARLY_INIT_F)
237	board_early_init_f,	237	board_early_init_f,
238	#endif	238	#endif
239	timer_init, /* initialize timer */	239	timer_init, /* initialize timer */
240	#ifdef CONFIG_BOARD_POSTCLK_INIT	240	#ifdef CONFIG_BOARD_POSTCLK_INIT
241	board_postclk_init,	241	board_postclk_init,
242	#endif	242	#endif
243	#ifdef CONFIG_FSL_ESDHC	243	#ifdef CONFIG_FSL_ESDHC
244	get_clocks,	244	get_clocks,
245	#endif	245	#endif
246	env_init, /* initialize environment */	246	env_init, /* initialize environment */
247	init_baudrate, /* initialze baudrate settings */	247	init_baudrate, /* initialze baudrate settings */
248	serial_init, /* serial communications setup */	248	serial_init, /* serial communications setup */
249	console_init_f, /* stage 1 init of console */	249	console_init_f, /* stage 1 init of console */
250	display_banner, /* say that we are here */	250	display_banner, /* say that we are here */
251	print_cpuinfo, /* display cpu info (and speed) */	251	print_cpuinfo, /* display cpu info (and speed) */
252	#if defined(CONFIG_DISPLAY_BOARDINFO)	252	#if defined(CONFIG_DISPLAY_BOARDINFO)
253	checkboard, /* display board info */	253	checkboard, /* display board info */
254	#endif	254	#endif
255	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SYS_I2C)	255	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SYS_I2C)
256	init_func_i2c,	256	init_func_i2c,
257	#endif	257	#endif
258	dram_init, /* configure available RAM banks */	258	dram_init, /* configure available RAM banks */
259	NULL,	259	NULL,
260	};	260	};
261		261
262	void board_init_f(ulong bootflag)	262	void board_init_f(ulong bootflag)
263	{	263	{
264	bd_t *bd;	264	bd_t *bd;
265	init_fnc_t **init_fnc_ptr;	265	init_fnc_t **init_fnc_ptr;
266	gd_t *id;	266	gd_t *id;
267	ulong addr, addr_sp;	267	ulong addr, addr_sp;
268	#ifdef CONFIG_PRAM	268	#ifdef CONFIG_PRAM
269	ulong reg;	269	ulong reg;
270	#endif	270	#endif
271	void *new_fdt = NULL;	271	void *new_fdt = NULL;
272	size_t fdt_size = 0;	272	size_t fdt_size = 0;
273		273
274	memset((void *)gd, 0, sizeof(gd_t));	274	memset((void *)gd, 0, sizeof(gd_t));
275		275
276	gd->mon_len = _bss_end_ofs;	276	gd->mon_len = (ulong)&__bss_end - (ulong)_start;
277	#ifdef CONFIG_OF_EMBED	277	#ifdef CONFIG_OF_EMBED
278	/* Get a pointer to the FDT */	278	/* Get a pointer to the FDT */
279	gd->fdt_blob = __dtb_db_begin;	279	gd->fdt_blob = __dtb_db_begin;
280	#elif defined CONFIG_OF_SEPARATE	280	#elif defined CONFIG_OF_SEPARATE
281	/* FDT is at end of image */	281	/* FDT is at end of image */
282	gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE);	282	gd->fdt_blob = &_end;
283	#endif	283	#endif
284	/* Allow the early environment to override the fdt address */	284	/* Allow the early environment to override the fdt address */
285	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,	285	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
286	(uintptr_t)gd->fdt_blob);	286	(uintptr_t)gd->fdt_blob);
287		287
288	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {	288	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
289	if ((*init_fnc_ptr)() != 0) {	289	if ((*init_fnc_ptr)() != 0) {
290	hang ();	290	hang ();
291	}	291	}
292	}	292	}
293		293
294	#ifdef CONFIG_OF_CONTROL	294	#ifdef CONFIG_OF_CONTROL
295	/* For now, put this check after the console is ready */	295	/* For now, put this check after the console is ready */
296	if (fdtdec_prepare_fdt()) {	296	if (fdtdec_prepare_fdt()) {
297	panic("** CONFIG_OF_CONTROL defined but no FDT - please see "	297	panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
298	"doc/README.fdt-control");	298	"doc/README.fdt-control");
299	}	299	}
300	#endif	300	#endif
301		301
302	debug("monitor len: %08lX\n", gd->mon_len);	302	debug("monitor len: %08lX\n", gd->mon_len);
303	/*	303	/*
304	* Ram is setup, size stored in gd !!	304	* Ram is setup, size stored in gd !!
305	*/	305	*/
306	debug("ramsize: %08lX\n", gd->ram_size);	306	debug("ramsize: %08lX\n", gd->ram_size);
307	#if defined(CONFIG_SYS_MEM_TOP_HIDE)	307	#if defined(CONFIG_SYS_MEM_TOP_HIDE)
308	/*	308	/*
309	* Subtract specified amount of memory to hide so that it won't	309	* Subtract specified amount of memory to hide so that it won't
310	* get "touched" at all by U-Boot. By fixing up gd->ram_size	310	* get "touched" at all by U-Boot. By fixing up gd->ram_size
311	* the Linux kernel should now get passed the now "corrected"	311	* the Linux kernel should now get passed the now "corrected"
312	* memory size and won't touch it either. This should work	312	* memory size and won't touch it either. This should work
313	* for arch/ppc and arch/powerpc. Only Linux board ports in	313	* for arch/ppc and arch/powerpc. Only Linux board ports in
314	* arch/powerpc with bootwrapper support, that recalculate the	314	* arch/powerpc with bootwrapper support, that recalculate the
315	* memory size from the SDRAM controller setup will have to	315	* memory size from the SDRAM controller setup will have to
316	* get fixed.	316	* get fixed.
317	*/	317	*/
318	gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;	318	gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
319	#endif	319	#endif
320		320
321	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;	321	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
322		322
323	#ifdef CONFIG_LOGBUFFER	323	#ifdef CONFIG_LOGBUFFER
324	#ifndef CONFIG_ALT_LB_ADDR	324	#ifndef CONFIG_ALT_LB_ADDR
325	/* reserve kernel log buffer */	325	/* reserve kernel log buffer */
326	addr -= (LOGBUFF_RESERVE);	326	addr -= (LOGBUFF_RESERVE);
327	debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,	327	debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
328	addr);	328	addr);
329	#endif	329	#endif
330	#endif	330	#endif
331		331
332	#ifdef CONFIG_PRAM	332	#ifdef CONFIG_PRAM
333	/*	333	/*
334	* reserve protected RAM	334	* reserve protected RAM
335	*/	335	*/
336	reg = getenv_ulong("pram", 10, CONFIG_PRAM);	336	reg = getenv_ulong("pram", 10, CONFIG_PRAM);
337	addr -= (reg << 10); /* size is in kB */	337	addr -= (reg << 10); /* size is in kB */
338	debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);	338	debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
339	#endif /* CONFIG_PRAM */	339	#endif /* CONFIG_PRAM */
340		340
341	#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))	341	#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
342	/* reserve TLB table */	342	/* reserve TLB table */
343	gd->arch.tlb_size = PGTABLE_SIZE;	343	gd->arch.tlb_size = PGTABLE_SIZE;
344	addr -= gd->arch.tlb_size;	344	addr -= gd->arch.tlb_size;
345		345
346	/* round down to next 64 kB limit */	346	/* round down to next 64 kB limit */
347	addr &= ~(0x10000 - 1);	347	addr &= ~(0x10000 - 1);
348		348
349	gd->arch.tlb_addr = addr;	349	gd->arch.tlb_addr = addr;
350	debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);	350	debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
351	#endif	351	#endif
352		352
353	/* round down to next 4 kB limit */	353	/* round down to next 4 kB limit */
354	addr &= ~(4096 - 1);	354	addr &= ~(4096 - 1);
355	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);	355	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
356		356
357	#ifdef CONFIG_LCD	357	#ifdef CONFIG_LCD
358	#ifdef CONFIG_FB_ADDR	358	#ifdef CONFIG_FB_ADDR
359	gd->fb_base = CONFIG_FB_ADDR;	359	gd->fb_base = CONFIG_FB_ADDR;
360	#else	360	#else
361	/* reserve memory for LCD display (always full pages) */	361	/* reserve memory for LCD display (always full pages) */
362	addr = lcd_setmem(addr);	362	addr = lcd_setmem(addr);
363	gd->fb_base = addr;	363	gd->fb_base = addr;
364	#endif /* CONFIG_FB_ADDR */	364	#endif /* CONFIG_FB_ADDR */
365	#endif /* CONFIG_LCD */	365	#endif /* CONFIG_LCD */
366		366
367	/*	367	/*
368	* reserve memory for U-Boot code, data & bss	368	* reserve memory for U-Boot code, data & bss
369	* round down to next 4 kB limit	369	* round down to next 4 kB limit
370	*/	370	*/
371	addr -= gd->mon_len;	371	addr -= gd->mon_len;
372	addr &= ~(4096 - 1);	372	addr &= ~(4096 - 1);
373		373
374	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);	374	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
375		375
376	#ifndef CONFIG_SPL_BUILD	376	#ifndef CONFIG_SPL_BUILD
377	/*	377	/*
378	* reserve memory for malloc() arena	378	* reserve memory for malloc() arena
379	*/	379	*/
380	addr_sp = addr - TOTAL_MALLOC_LEN;	380	addr_sp = addr - TOTAL_MALLOC_LEN;
381	debug("Reserving %dk for malloc() at: %08lx\n",	381	debug("Reserving %dk for malloc() at: %08lx\n",
382	TOTAL_MALLOC_LEN >> 10, addr_sp);	382	TOTAL_MALLOC_LEN >> 10, addr_sp);
383	/*	383	/*
384	* (permanently) allocate a Board Info struct	384	* (permanently) allocate a Board Info struct
385	* and a permanent copy of the "global" data	385	* and a permanent copy of the "global" data
386	*/	386	*/
387	addr_sp -= sizeof (bd_t);	387	addr_sp -= sizeof (bd_t);
388	bd = (bd_t *) addr_sp;	388	bd = (bd_t *) addr_sp;
389	gd->bd = bd;	389	gd->bd = bd;
390	debug("Reserving %zu Bytes for Board Info at: %08lx\n",	390	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
391	sizeof (bd_t), addr_sp);	391	sizeof (bd_t), addr_sp);
392		392
393	#ifdef CONFIG_MACH_TYPE	393	#ifdef CONFIG_MACH_TYPE
394	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */	394	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
395	#endif	395	#endif
396		396
397	addr_sp -= sizeof (gd_t);	397	addr_sp -= sizeof (gd_t);
398	id = (gd_t *) addr_sp;	398	id = (gd_t *) addr_sp;
399	debug("Reserving %zu Bytes for Global Data at: %08lx\n",	399	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
400	sizeof (gd_t), addr_sp);	400	sizeof (gd_t), addr_sp);
401		401
402	#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)	402	#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
403	/*	403	/*
404	* If the device tree is sitting immediate above our image then we	404	* If the device tree is sitting immediate above our image then we
405	* must relocate it. If it is embedded in the data section, then it	405	* must relocate it. If it is embedded in the data section, then it
406	* will be relocated with other data.	406	* will be relocated with other data.
407	*/	407	*/
408	if (gd->fdt_blob) {	408	if (gd->fdt_blob) {
409	fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);	409	fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
410		410
411	addr_sp -= fdt_size;	411	addr_sp -= fdt_size;
412	new_fdt = (void *)addr_sp;	412	new_fdt = (void *)addr_sp;
413	debug("Reserving %zu Bytes for FDT at: %08lx\n",	413	debug("Reserving %zu Bytes for FDT at: %08lx\n",
414	fdt_size, addr_sp);	414	fdt_size, addr_sp);
415	}	415	}
416	#endif	416	#endif
417		417
418	#ifndef CONFIG_ARM64	418	#ifndef CONFIG_ARM64
419	/* setup stackpointer for exeptions */	419	/* setup stackpointer for exeptions */
420	gd->irq_sp = addr_sp;	420	gd->irq_sp = addr_sp;
421	#ifdef CONFIG_USE_IRQ	421	#ifdef CONFIG_USE_IRQ
422	addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);	422	addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);
423	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",	423	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
424	CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);	424	CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
425	#endif	425	#endif
426	/* leave 3 words for abort-stack */	426	/* leave 3 words for abort-stack */
427	addr_sp -= 12;	427	addr_sp -= 12;
428		428
429	/* 8-byte alignment for ABI compliance */	429	/* 8-byte alignment for ABI compliance */
430	addr_sp &= ~0x07;	430	addr_sp &= ~0x07;
431	#else /* CONFIG_ARM64 */	431	#else /* CONFIG_ARM64 */
432	/* 16-byte alignment for ABI compliance */	432	/* 16-byte alignment for ABI compliance */
433	addr_sp &= ~0x0f;	433	addr_sp &= ~0x0f;
434	#endif /* CONFIG_ARM64 */	434	#endif /* CONFIG_ARM64 */
435	#else	435	#else
436	addr_sp += 128; /* leave 32 words for abort-stack */	436	addr_sp += 128; /* leave 32 words for abort-stack */
437	gd->irq_sp = addr_sp;	437	gd->irq_sp = addr_sp;
438	#endif	438	#endif
439		439
440	debug("New Stack Pointer is: %08lx\n", addr_sp);	440	debug("New Stack Pointer is: %08lx\n", addr_sp);
441		441
442	#ifdef CONFIG_POST	442	#ifdef CONFIG_POST
443	post_bootmode_init();	443	post_bootmode_init();
444	post_run(NULL, POST_ROM \| post_bootmode_get(0));	444	post_run(NULL, POST_ROM \| post_bootmode_get(0));
445	#endif	445	#endif
446		446
447	gd->bd->bi_baudrate = gd->baudrate;	447	gd->bd->bi_baudrate = gd->baudrate;
448	/* Ram ist board specific, so move it to board code ... */	448	/* Ram ist board specific, so move it to board code ... */
449	dram_init_banksize();	449	dram_init_banksize();
450	display_dram_config(); /* and display it */	450	display_dram_config(); /* and display it */
451		451
452	gd->relocaddr = addr;	452	gd->relocaddr = addr;
453	gd->start_addr_sp = addr_sp;	453	gd->start_addr_sp = addr_sp;
454	gd->reloc_off = addr - _TEXT_BASE;	454	gd->reloc_off = addr - (ulong)&_start;
455	debug("relocation Offset is: %08lx\n", gd->reloc_off);	455	debug("relocation Offset is: %08lx\n", gd->reloc_off);
456	if (new_fdt) {	456	if (new_fdt) {
457	memcpy(new_fdt, gd->fdt_blob, fdt_size);	457	memcpy(new_fdt, gd->fdt_blob, fdt_size);
458	gd->fdt_blob = new_fdt;	458	gd->fdt_blob = new_fdt;
459	}	459	}
460	memcpy(id, (void *)gd, sizeof(gd_t));	460	memcpy(id, (void *)gd, sizeof(gd_t));
461	}	461	}
462		462
463	#if !defined(CONFIG_SYS_NO_FLASH)	463	#if !defined(CONFIG_SYS_NO_FLASH)
464	static char failed = " failed *\n";	464	static char failed = " failed *\n";
465	#endif	465	#endif
466		466
467	/*	467	/*
468	* Tell if it's OK to load the environment early in boot.	468	* Tell if it's OK to load the environment early in boot.
469	*	469	*
470	* If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see	470	* If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
471	* if this is OK (defaulting to saying it's not OK).	471	* if this is OK (defaulting to saying it's not OK).
472	*	472	*
473	* NOTE: Loading the environment early can be a bad idea if security is	473	* NOTE: Loading the environment early can be a bad idea if security is
474	* important, since no verification is done on the environment.	474	* important, since no verification is done on the environment.
475	*	475	*
476	* @return 0 if environment should not be loaded, !=0 if it is ok to load	476	* @return 0 if environment should not be loaded, !=0 if it is ok to load
477	*/	477	*/
478	static int should_load_env(void)	478	static int should_load_env(void)
479	{	479	{
480	#ifdef CONFIG_OF_CONTROL	480	#ifdef CONFIG_OF_CONTROL
481	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);	481	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
482	#elif defined CONFIG_DELAY_ENVIRONMENT	482	#elif defined CONFIG_DELAY_ENVIRONMENT
483	return 0;	483	return 0;
484	#else	484	#else
485	return 1;	485	return 1;
486	#endif	486	#endif
487	}	487	}
488		488
489	#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL)	489	#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL)
490	static void display_fdt_model(const void *blob)	490	static void display_fdt_model(const void *blob)
491	{	491	{
492	const char *model;	492	const char *model;
493		493
494	model = (char *)fdt_getprop(blob, 0, "model", NULL);	494	model = (char *)fdt_getprop(blob, 0, "model", NULL);
495	printf("Model: %s\n", model ? model : "<unknown>");	495	printf("Model: %s\n", model ? model : "<unknown>");
496	}	496	}
497	#endif	497	#endif
498		498
499	/************************************************************************	499	/************************************************************************
500	*	500	*
501	* This is the next part if the initialization sequence: we are now	501	* This is the next part if the initialization sequence: we are now
502	* running from RAM and have a "normal" C environment, i. e. global	502	* running from RAM and have a "normal" C environment, i. e. global
503	* data can be written, BSS has been cleared, the stack size in not	503	* data can be written, BSS has been cleared, the stack size in not
504	* that critical any more, etc.	504	* that critical any more, etc.
505	*	505	*
506	************************************************************************	506	************************************************************************
507	*/	507	*/
508		508
509	void board_init_r(gd_t *id, ulong dest_addr)	509	void board_init_r(gd_t *id, ulong dest_addr)
510	{	510	{
511	ulong malloc_start;	511	ulong malloc_start;
512	#if !defined(CONFIG_SYS_NO_FLASH)	512	#if !defined(CONFIG_SYS_NO_FLASH)
513	ulong flash_size;	513	ulong flash_size;
514	#endif	514	#endif
515		515
516	gd->flags \|= GD_FLG_RELOC; /* tell others: relocation done */	516	gd->flags \|= GD_FLG_RELOC; /* tell others: relocation done */
517	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");	517	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
518		518
519	monitor_flash_len = _end_ofs;	519	monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start;
520		520
521	/* Enable caches */	521	/* Enable caches */
522	enable_caches();	522	enable_caches();
523		523
524	debug("monitor flash len: %08lX\n", monitor_flash_len);	524	debug("monitor flash len: %08lX\n", monitor_flash_len);
525	board_init(); /* Setup chipselects */	525	board_init(); /* Setup chipselects */
526	/*	526	/*
527	* TODO: printing of the clock inforamtion of the board is now	527	* TODO: printing of the clock inforamtion of the board is now
528	* implemented as part of bdinfo command. Currently only support for	528	* implemented as part of bdinfo command. Currently only support for
529	* davinci SOC's is added. Remove this check once all the board	529	* davinci SOC's is added. Remove this check once all the board
530	* implement this.	530	* implement this.
531	*/	531	*/
532	#ifdef CONFIG_CLOCKS	532	#ifdef CONFIG_CLOCKS
533	set_cpu_clk_info(); /* Setup clock information */	533	set_cpu_clk_info(); /* Setup clock information */
534	#endif	534	#endif
535	serial_initialize();	535	serial_initialize();
536		536
537	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);	537	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
538		538
539	#ifdef CONFIG_LOGBUFFER	539	#ifdef CONFIG_LOGBUFFER
540	logbuff_init_ptrs();	540	logbuff_init_ptrs();
541	#endif	541	#endif
542	#ifdef CONFIG_POST	542	#ifdef CONFIG_POST
543	post_output_backlog();	543	post_output_backlog();
544	#endif	544	#endif
545		545
546	/* The Malloc area is immediately below the monitor copy in DRAM */	546	/* The Malloc area is immediately below the monitor copy in DRAM */
547	malloc_start = dest_addr - TOTAL_MALLOC_LEN;	547	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
548	mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);	548	mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
549		549
550	#ifdef CONFIG_ARCH_EARLY_INIT_R	550	#ifdef CONFIG_ARCH_EARLY_INIT_R
551	arch_early_init_r();	551	arch_early_init_r();
552	#endif	552	#endif
553	power_init_board();	553	power_init_board();
554		554
555	#if !defined(CONFIG_SYS_NO_FLASH)	555	#if !defined(CONFIG_SYS_NO_FLASH)
556	puts("Flash: ");	556	puts("Flash: ");
557		557
558	flash_size = flash_init();	558	flash_size = flash_init();
559	if (flash_size > 0) {	559	if (flash_size > 0) {
560	# ifdef CONFIG_SYS_FLASH_CHECKSUM	560	# ifdef CONFIG_SYS_FLASH_CHECKSUM
561	print_size(flash_size, "");	561	print_size(flash_size, "");
562	/*	562	/*
563	* Compute and print flash CRC if flashchecksum is set to 'y'	563	* Compute and print flash CRC if flashchecksum is set to 'y'
564	*	564	*
565	* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX	565	* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
566	*/	566	*/
567	if (getenv_yesno("flashchecksum") == 1) {	567	if (getenv_yesno("flashchecksum") == 1) {
568	printf(" CRC: %08X", crc32(0,	568	printf(" CRC: %08X", crc32(0,
569	(const unsigned char *) CONFIG_SYS_FLASH_BASE,	569	(const unsigned char *) CONFIG_SYS_FLASH_BASE,
570	flash_size));	570	flash_size));
571	}	571	}
572	putc('\n');	572	putc('\n');
573	# else /* !CONFIG_SYS_FLASH_CHECKSUM */	573	# else /* !CONFIG_SYS_FLASH_CHECKSUM */
574	print_size(flash_size, "\n");	574	print_size(flash_size, "\n");
575	# endif /* CONFIG_SYS_FLASH_CHECKSUM */	575	# endif /* CONFIG_SYS_FLASH_CHECKSUM */
576	} else {	576	} else {
577	puts(failed);	577	puts(failed);
578	hang();	578	hang();
579	}	579	}
580	#endif	580	#endif
581		581
582	#if defined(CONFIG_CMD_NAND)	582	#if defined(CONFIG_CMD_NAND)
583	puts("NAND: ");	583	puts("NAND: ");
584	nand_init(); /* go init the NAND */	584	nand_init(); /* go init the NAND */
585	#endif	585	#endif
586		586
587	#if defined(CONFIG_CMD_ONENAND)	587	#if defined(CONFIG_CMD_ONENAND)
588	onenand_init();	588	onenand_init();
589	#endif	589	#endif
590		590
591	#ifdef CONFIG_GENERIC_MMC	591	#ifdef CONFIG_GENERIC_MMC
592	puts("MMC: ");	592	puts("MMC: ");
593	mmc_initialize(gd->bd);	593	mmc_initialize(gd->bd);
594	#endif	594	#endif
595		595
596	#ifdef CONFIG_HAS_DATAFLASH	596	#ifdef CONFIG_HAS_DATAFLASH
597	AT91F_DataflashInit();	597	AT91F_DataflashInit();
598	dataflash_print_info();	598	dataflash_print_info();
599	#endif	599	#endif
600		600
601	/* initialize environment */	601	/* initialize environment */
602	if (should_load_env())	602	if (should_load_env())
603	env_relocate();	603	env_relocate();
604	else	604	else
605	set_default_env(NULL);	605	set_default_env(NULL);
606		606
607	#if defined(CONFIG_CMD_PCI) \|\| defined(CONFIG_PCI)	607	#if defined(CONFIG_CMD_PCI) \|\| defined(CONFIG_PCI)
608	arm_pci_init();	608	arm_pci_init();
609	#endif	609	#endif
610		610
611	stdio_init(); /* get the devices list going. */	611	stdio_init(); /* get the devices list going. */
612		612
613	jumptable_init();	613	jumptable_init();
614		614
615	#if defined(CONFIG_API)	615	#if defined(CONFIG_API)
616	/* Initialize API */	616	/* Initialize API */
617	api_init();	617	api_init();
618	#endif	618	#endif
619		619
620	console_init_r(); /* fully init console as a device */	620	console_init_r(); /* fully init console as a device */
621		621
622	#ifdef CONFIG_DISPLAY_BOARDINFO_LATE	622	#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
623	# ifdef CONFIG_OF_CONTROL	623	# ifdef CONFIG_OF_CONTROL
624	/* Put this here so it appears on the LCD, now it is ready */	624	/* Put this here so it appears on the LCD, now it is ready */
625	display_fdt_model(gd->fdt_blob);	625	display_fdt_model(gd->fdt_blob);
626	# else	626	# else
627	checkboard();	627	checkboard();
628	# endif	628	# endif
629	#endif	629	#endif
630		630
631	#if defined(CONFIG_ARCH_MISC_INIT)	631	#if defined(CONFIG_ARCH_MISC_INIT)
632	/* miscellaneous arch dependent initialisations */	632	/* miscellaneous arch dependent initialisations */
633	arch_misc_init();	633	arch_misc_init();
634	#endif	634	#endif
635	#if defined(CONFIG_MISC_INIT_R)	635	#if defined(CONFIG_MISC_INIT_R)
636	/* miscellaneous platform dependent initialisations */	636	/* miscellaneous platform dependent initialisations */
637	misc_init_r();	637	misc_init_r();
638	#endif	638	#endif
639		639
640	/* set up exceptions */	640	/* set up exceptions */
641	interrupt_init();	641	interrupt_init();
642	/* enable exceptions */	642	/* enable exceptions */
643	enable_interrupts();	643	enable_interrupts();
644		644
645	/* Initialize from environment */	645	/* Initialize from environment */
646	load_addr = getenv_ulong("loadaddr", 16, load_addr);	646	load_addr = getenv_ulong("loadaddr", 16, load_addr);
647		647
648	#ifdef CONFIG_BOARD_LATE_INIT	648	#ifdef CONFIG_BOARD_LATE_INIT
649	board_late_init();	649	board_late_init();
650	#endif	650	#endif
651		651
652	#ifdef CONFIG_BITBANGMII	652	#ifdef CONFIG_BITBANGMII
653	bb_miiphy_init();	653	bb_miiphy_init();
654	#endif	654	#endif
655	#if defined(CONFIG_CMD_NET)	655	#if defined(CONFIG_CMD_NET)
656	puts("Net: ");	656	puts("Net: ");
657	eth_initialize(gd->bd);	657	eth_initialize(gd->bd);
658	#if defined(CONFIG_RESET_PHY_R)	658	#if defined(CONFIG_RESET_PHY_R)
659	debug("Reset Ethernet PHY\n");	659	debug("Reset Ethernet PHY\n");
660	reset_phy();	660	reset_phy();
661	#endif	661	#endif
662	#endif	662	#endif
663		663
664	#ifdef CONFIG_POST	664	#ifdef CONFIG_POST
665	post_run(NULL, POST_RAM \| post_bootmode_get(0));	665	post_run(NULL, POST_RAM \| post_bootmode_get(0));
666	#endif	666	#endif
667		667
668	#if defined(CONFIG_PRAM) \|\| defined(CONFIG_LOGBUFFER)	668	#if defined(CONFIG_PRAM) \|\| defined(CONFIG_LOGBUFFER)
669	/*	669	/*
670	* Export available size of memory for Linux,	670	* Export available size of memory for Linux,
671	* taking into account the protected RAM at top of memory	671	* taking into account the protected RAM at top of memory
672	*/	672	*/
673	{	673	{
674	ulong pram = 0;	674	ulong pram = 0;
675	uchar memsz[32];	675	uchar memsz[32];
676		676
677	#ifdef CONFIG_PRAM	677	#ifdef CONFIG_PRAM
678	pram = getenv_ulong("pram", 10, CONFIG_PRAM);	678	pram = getenv_ulong("pram", 10, CONFIG_PRAM);
679	#endif	679	#endif
680	#ifdef CONFIG_LOGBUFFER	680	#ifdef CONFIG_LOGBUFFER
681	#ifndef CONFIG_ALT_LB_ADDR	681	#ifndef CONFIG_ALT_LB_ADDR
682	/* Also take the logbuffer into account (pram is in kB) */	682	/* Also take the logbuffer into account (pram is in kB) */
683	pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;	683	pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
684	#endif	684	#endif
685	#endif	685	#endif
686	sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);	686	sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
687	setenv("mem", (char *)memsz);	687	setenv("mem", (char *)memsz);
688	}	688	}
689	#endif	689	#endif
690		690
691	/* main_loop() can return to retry autoboot, if so just run it again. */	691	/* main_loop() can return to retry autoboot, if so just run it again. */
692	for (;;) {	692	for (;;) {
693	main_loop();	693	main_loop();
694	}	694	}
695		695
696	/* NOTREACHED - no way out of command loop except booting */	696	/* NOTREACHED - no way out of command loop except booting */
697	}	697	}
698		698

board/armltd/integrator/lowlevel_init.S

Diff comments View file @ b60eff3

1	/*	1	/*
2	* Board specific setup info	2	* Board specific setup info
3	*	3	*
4	* (C) Copyright 2004, ARM Ltd.	4	* (C) Copyright 2004, ARM Ltd.
5	* Philippe Robin, <philippe.robin@arm.com>	5	* Philippe Robin, <philippe.robin@arm.com>
6	*	6	*
7	* SPDX-License-Identifier: GPL-2.0+	7	* SPDX-License-Identifier: GPL-2.0+
8	*/	8	*/
9		9
10	#include <config.h>	10	#include <config.h>
11	#include <version.h>	11	#include <version.h>
12		12
13	/* Reset using CM control register */	13	/* Reset using CM control register */
14	.global reset_cpu	14	.global reset_cpu
15	reset_cpu:	15	reset_cpu:
16	mov r0, #CM_BASE	16	mov r0, #CM_BASE
17	ldr r1,[r0,#OS_CTRL]	17	ldr r1,[r0,#OS_CTRL]
18	orr r1,r1,#CMMASK_RESET	18	orr r1,r1,#CMMASK_RESET
19	str r1,[r0,#OS_CTRL]	19	str r1,[r0,#OS_CTRL]
20		20
21	reset_failed:	21	reset_failed:
22	b reset_failed	22	b reset_failed
23		23
24	/* Set up the platform, once the cpu has been initialized */	24	/* Set up the platform, once the cpu has been initialized */
25	.globl lowlevel_init	25	.globl lowlevel_init
26	lowlevel_init:	26	lowlevel_init:
27	/* If U-Boot has been run after the ARM boot monitor	27	/* If U-Boot has been run after the ARM boot monitor
28	* then all the necessary actions have been done	28	* then all the necessary actions have been done
29	* otherwise we are running from user flash mapped to 0x00000000	29	* otherwise we are running from user flash mapped to 0x00000000
30	* --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --	30	* --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
31	* Changes to the (possibly soft) reset defaults of the processor	31	* Changes to the (possibly soft) reset defaults of the processor
32	* itself should be performed in cpu/arm<>/start.S	32	* itself should be performed in cpu/arm<>/start.S
33	* This function affects only the core module or board settings	33	* This function affects only the core module or board settings
34	*/	34	*/
35		35
36	#ifdef CONFIG_CM_INIT	36	#ifdef CONFIG_CM_INIT
37	/* CM has an initialization register	37	/* CM has an initialization register
38	* - bits in it are wired into test-chip pins to force	38	* - bits in it are wired into test-chip pins to force
39	* reset defaults	39	* reset defaults
40	* - may need to change its contents for U-Boot	40	* - may need to change its contents for U-Boot
41	*/	41	*/
42		42
43	/* set the desired CM specific value */	43	/* set the desired CM specific value */
44	mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */	44	mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
45		45
46	#if defined (CONFIG_CM10200E) \|\| defined (CONFIG_CM10220E)	46	#if defined (CONFIG_CM10200E) \|\| defined (CONFIG_CM10220E)
47	orr r2,r2,#CMMASK_INIT_102	47	orr r2,r2,#CMMASK_INIT_102
48	#else	48	#else
49		49
50	#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \	50	#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
51	!defined (CONFIG_CM940T)	51	!defined (CONFIG_CM940T)
52		52
53	#ifdef CONFIG_CM_MULTIPLE_SSRAM	53	#ifdef CONFIG_CM_MULTIPLE_SSRAM
54	/* set simple mapping */	54	/* set simple mapping */
55	and r2,r2,#CMMASK_MAP_SIMPLE	55	and r2,r2,#CMMASK_MAP_SIMPLE
56	#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */	56	#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
57		57
58	#ifdef CONFIG_CM_TCRAM	58	#ifdef CONFIG_CM_TCRAM
59	/* disable TCRAM */	59	/* disable TCRAM */
60	and r2,r2,#CMMASK_TCRAM_DISABLE	60	and r2,r2,#CMMASK_TCRAM_DISABLE
61	#endif /* #ifdef CONFIG_CM_TCRAM */	61	#endif /* #ifdef CONFIG_CM_TCRAM */
62		62
63	#if defined (CONFIG_CM926EJ_S) \|\| defined (CONFIG_CM1026EJ_S) \|\| \	63	#if defined (CONFIG_CM926EJ_S) \|\| defined (CONFIG_CM1026EJ_S) \|\| \
64	defined (CONFIG_CM1136JF_S)	64	defined (CONFIG_CM1136JF_S)
65		65
66	and r2,r2,#CMMASK_LE	66	and r2,r2,#CMMASK_LE
67		67
68	#endif /* cpu with little endian initialization */	68	#endif /* cpu with little endian initialization */
69		69
70	orr r2,r2,#CMMASK_CMxx6_COMMON	70	orr r2,r2,#CMMASK_CMxx6_COMMON
71		71
72	#endif /* CMxx6 code */	72	#endif /* CMxx6 code */
73		73
74	#endif /* ARM102xxE value */	74	#endif /* ARM102xxE value */
75		75
76	/* read CM_INIT */	76	/* read CM_INIT */
77	mov r0, #CM_BASE	77	mov r0, #CM_BASE
78	ldr r1, [r0, #OS_INIT]	78	ldr r1, [r0, #OS_INIT]
79	/* check against desired bit setting */	79	/* check against desired bit setting */
80	and r3,r1,r2	80	and r3,r1,r2
81	cmp r3,r2	81	cmp r3,r2
82	beq init_reg_OK	82	beq init_reg_OK
83		83
84	/* lock for change */	84	/* lock for change */
85	mov r3, #CMVAL_LOCK1	85	mov r3, #CMVAL_LOCK1
86	add r3,r3,#CMVAL_LOCK2	86	add r3,r3,#CMVAL_LOCK2
87	str r3, [r0, #OS_LOCK]	87	str r3, [r0, #OS_LOCK]
88	/* set desired value */	88	/* set desired value */
89	orr r1,r1,r2	89	orr r1,r1,r2
90	/* write & relock CM_INIT */	90	/* write & relock CM_INIT */
91	str r1, [r0, #OS_INIT]	91	str r1, [r0, #OS_INIT]
92	mov r1, #CMVAL_UNLOCK	92	mov r1, #CMVAL_UNLOCK
93	str r1, [r0, #OS_LOCK]	93	str r1, [r0, #OS_LOCK]
94		94
95	/* soft reset so new values used */	95	/* soft reset so new values used */
96	b reset_cpu	96	b reset_cpu
97		97
98	init_reg_OK:	98	init_reg_OK:
99		99
100	#endif /* CONFIG_CM_INIT */	100	#endif /* CONFIG_CM_INIT */
101		101
102	mov pc, lr	102	mov pc, lr
103		103
104	#ifdef CONFIG_CM_SPD_DETECT	104	#ifdef CONFIG_CM_SPD_DETECT
105	/* Fast memory is available for the DRAM data	105	/* Fast memory is available for the DRAM data
106	* - ensure it has been transferred, then summarize the data	106	* - ensure it has been transferred, then summarize the data
107	* into a CM register	107	* into a CM register
108	*/	108	*/
109	.globl dram_query	109	.globl dram_query
110	dram_query:	110	dram_query:
111	stmfd r13!,{r4-r6,lr}	111	stmfd r13!,{r4-r6,lr}
112	/* set up SDRAM info */	112	/* set up SDRAM info */
113	/* - based on example code from the CM User Guide */	113	/* - based on example code from the CM User Guide */
114	mov r0, #CM_BASE	114	mov r0, #CM_BASE
115		115
116	readspdbit:	116	readspdbit:
117	ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */	117	ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
118	and r1, r1, #0x20 /* mask SPD bit (5) */	118	and r1, r1, #0x20 /* mask SPD bit (5) */
119	cmp r1, #0x20 /* test if set */	119	cmp r1, #0x20 /* test if set */
120	bne readspdbit	120	bne readspdbit
121		121
122	setupsdram:	122	setupsdram:
123	add r0, r0, #OS_SPD /* address the copy of the SDP data */	123	add r0, r0, #OS_SPD /* address the copy of the SDP data */
124	ldrb r1, [r0, #3] /* number of row address lines */	124	ldrb r1, [r0, #3] /* number of row address lines */
125	ldrb r2, [r0, #4] /* number of column address lines */	125	ldrb r2, [r0, #4] /* number of column address lines */
126	ldrb r3, [r0, #5] /* number of banks */	126	ldrb r3, [r0, #5] /* number of banks */
127	ldrb r4, [r0, #31] /* module bank density */	127	ldrb r4, [r0, #31] /* module bank density */
128	mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */	128	mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
129	mov r5, r5, ASL#2 /* size in MB */	129	mov r5, r5, ASL#2 /* size in MB */
130	mov r0, #CM_BASE /* reload for later code */	130	mov r0, #CM_BASE /* reload for later code */
131	cmp r5, #0x10 /* is it 16MB? */	131	cmp r5, #0x10 /* is it 16MB? */
132	bne not16	132	bne not16
133	mov r6, #0x2 /* store size and CAS latency of 2 */	133	mov r6, #0x2 /* store size and CAS latency of 2 */
134	b writesize	134	b writesize
135		135
136	not16:	136	not16:
137	cmp r5, #0x20 /* is it 32MB? */	137	cmp r5, #0x20 /* is it 32MB? */
138	bne not32	138	bne not32
139	mov r6, #0x6	139	mov r6, #0x6
140	b writesize	140	b writesize
141		141
142	not32:	142	not32:
143	cmp r5, #0x40 /* is it 64MB? */	143	cmp r5, #0x40 /* is it 64MB? */
144	bne not64	144	bne not64
145	mov r6, #0xa	145	mov r6, #0xa
146	b writesize	146	b writesize
147		147
148	not64:	148	not64:
149	cmp r5, #0x80 /* is it 128MB? */	149	cmp r5, #0x80 /* is it 128MB? */
150	bne not128	150	bne not128
151	mov r6, #0xe	151	mov r6, #0xe
152	b writesize	152	b writesize
153		153
154	not128:	154	not128:
155	/* if it is none of these sizes then it is either 256MB, or	155	/* if it is none of these sizes then it is either 256MB, or
156	* there is no SDRAM fitted so default to 256MB	156	* there is no SDRAM fitted so default to 256MB
157	*/	157	*/
158	mov r6, #0x12	158	mov r6, #0x12
159		159
160	writesize:	160	writesize:
161	mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */	161	mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
162	orr r2, r1, r2, ASL#12 /* OR in column address lines */	162	orr r2, r1, r2, ASL#12 /* OR in column address lines */
163	orr r3, r2, r3, ASL#16 /* OR in number of banks */	163	orr r3, r2, r3, ASL#16 /* OR in number of banks */
164	orr r6, r6, r3 /* OR in size and CAS latency */	164	orr r6, r6, r3 /* OR in size and CAS latency */
165	str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */	165	str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
166		166
167	#endif /* #ifdef CONFIG_CM_SPD_DETECT */	167	#endif /* #ifdef CONFIG_CM_SPD_DETECT */
168		168
169	ldmfd r13!,{r4-r6,pc} /* back to caller */	169	ldmfd r13!,{r4-r6,pc} /* back to caller */
170		170
171	#ifdef CONFIG_CM_REMAP	171	#ifdef CONFIG_CM_REMAP
172	/* CM remap bit is operational	172	/* CM remap bit is operational
173	* - use it to map writeable memory at 0x00000000, in place of flash	173	* - use it to map writeable memory at 0x00000000, in place of flash
174	*/	174	*/
175	.globl cm_remap	175	.globl cm_remap
176	cm_remap:	176	cm_remap:
177	stmfd r13!,{r4-r10,lr}	177	stmfd r13!,{r4-r10,lr}
178		178
179	mov r0, #CM_BASE	179	mov r0, #CM_BASE
180	ldr r1, [r0, #OS_CTRL]	180	ldr r1, [r0, #OS_CTRL]
181	orr r1, r1, #CMMASK_REMAP /* set remap and led bits */	181	orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
182	str r1, [r0, #OS_CTRL]	182	str r1, [r0, #OS_CTRL]
183		183
184	/* Now 0x00000000 is writeable, replace the vectors */	184	/* Now 0x00000000 is writeable, replace the vectors */
185	ldr r0, =_start /* r0 <- start of vectors */	185	ldr r0, =_start /* r0 <- start of vectors */
186	ldr r2, =_TEXT_BASE /* r2 <- past vectors */	186	add r2, r0, #64 /* r2 <- past vectors */
187	sub r1,r1,r1 /* destination 0x00000000 */	187	sub r1,r1,r1 /* destination 0x00000000 */
188		188
189	copy_vec:	189	copy_vec:
190	ldmia r0!, {r3-r10} /* copy from source address [r0] */	190	ldmia r0!, {r3-r10} /* copy from source address [r0] */
191	stmia r1!, {r3-r10} /* copy to target address [r1] */	191	stmia r1!, {r3-r10} /* copy to target address [r1] */
192	cmp r0, r2 /* until source end address [r2] */	192	cmp r0, r2 /* until source end address [r2] */
193	ble copy_vec	193	ble copy_vec
194		194
195	ldmfd r13!,{r4-r10,pc} /* back to caller */	195	ldmfd r13!,{r4-r10,pc} /* back to caller */
196		196
197	#endif /* #ifdef CONFIG_CM_REMAP */	197	#endif /* #ifdef CONFIG_CM_REMAP */
198		198

board/cm4008/flash.c

Diff comments View file @ b60eff3

1	/*	1	/*
2	* (C) Copyright 2005	2	* (C) Copyright 2005
3	* Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com	3	* Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
4	*	4	*
5	* (C) Copyright 2001	5	* (C) Copyright 2001
6	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net	6	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
7	*	7	*
8	* (C) Copyright 2001	8	* (C) Copyright 2001
9	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	9	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10	*	10	*
11	* SPDX-License-Identifier: GPL-2.0+	11	* SPDX-License-Identifier: GPL-2.0+
12	*/	12	*/
13		13
14	#include <common.h>	14	#include <common.h>
15	#include <linux/byteorder/swab.h>	15	#include <linux/byteorder/swab.h>
16	#include <asm/sections.h>	16	#include <asm/sections.h>
17		17
18		18
19	flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */	19	flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
20		20
21	#define mb() __asm__ __volatile__ ("" : : : "memory")	21	#define mb() __asm__ __volatile__ ("" : : : "memory")
22		22
23	/*-----------------------------------------------------------------------	23	/*-----------------------------------------------------------------------
24	* Functions	24	* Functions
25	*/	25	*/
26	static ulong flash_get_size (unsigned char * addr, flash_info_t * info);	26	static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
27	static int write_data (flash_info_t * info, ulong dest, unsigned char data);	27	static int write_data (flash_info_t * info, ulong dest, unsigned char data);
28	static void flash_get_offsets (ulong base, flash_info_t * info);	28	static void flash_get_offsets (ulong base, flash_info_t * info);
29	void inline spin_wheel (void);	29	void inline spin_wheel (void);
30		30
31	/*-----------------------------------------------------------------------	31	/*-----------------------------------------------------------------------
32	*/	32	*/
33		33
34	unsigned long flash_init (void)	34	unsigned long flash_init (void)
35	{	35	{
36	int i;	36	int i;
37	ulong size = 0;	37	ulong size = 0;
38		38
39	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {	39	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
40	switch (i) {	40	switch (i) {
41	case 0:	41	case 0:
42	flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);	42	flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
43	flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);	43	flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
44	break;	44	break;
45	case 1:	45	case 1:
46	/* ignore for now */	46	/* ignore for now */
47	flash_info[i].flash_id = FLASH_UNKNOWN;	47	flash_info[i].flash_id = FLASH_UNKNOWN;
48	break;	48	break;
49	default:	49	default:
50	panic ("configured too many flash banks!\n");	50	panic ("configured too many flash banks!\n");
51	break;	51	break;
52	}	52	}
53	size += flash_info[i].size;	53	size += flash_info[i].size;
54	}	54	}
55		55
56	/* Protect monitor and environment sectors	56	/* Protect monitor and environment sectors
57	*/	57	*/
58	flash_protect (FLAG_PROTECT_SET,	58	flash_protect (FLAG_PROTECT_SET,
59	CONFIG_SYS_FLASH_BASE,	59	CONFIG_SYS_FLASH_BASE,
60	CONFIG_SYS_FLASH_BASE + _bss_start_ofs,	60	CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
61	&flash_info[0]);	61	&flash_info[0]);
62		62
63	return size;	63	return size;
64	}	64	}
65		65
66	/*-----------------------------------------------------------------------	66	/*-----------------------------------------------------------------------
67	*/	67	*/
68	static void flash_get_offsets (ulong base, flash_info_t * info)	68	static void flash_get_offsets (ulong base, flash_info_t * info)
69	{	69	{
70	int i;	70	int i;
71		71
72	if (info->flash_id == FLASH_UNKNOWN)	72	if (info->flash_id == FLASH_UNKNOWN)
73	return;	73	return;
74		74
75	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {	75	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
76	for (i = 0; i < info->sector_count; i++) {	76	for (i = 0; i < info->sector_count; i++) {
77	info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);	77	info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
78	info->protect[i] = 0;	78	info->protect[i] = 0;
79	}	79	}
80	}	80	}
81	}	81	}
82		82
83	/*-----------------------------------------------------------------------	83	/*-----------------------------------------------------------------------
84	*/	84	*/
85	void flash_print_info (flash_info_t * info)	85	void flash_print_info (flash_info_t * info)
86	{	86	{
87	int i;	87	int i;
88		88
89	if (info->flash_id == FLASH_UNKNOWN) {	89	if (info->flash_id == FLASH_UNKNOWN) {
90	printf ("missing or unknown FLASH type\n");	90	printf ("missing or unknown FLASH type\n");
91	return;	91	return;
92	}	92	}
93		93
94	switch (info->flash_id & FLASH_VENDMASK) {	94	switch (info->flash_id & FLASH_VENDMASK) {
95	case FLASH_MAN_INTEL:	95	case FLASH_MAN_INTEL:
96	printf ("INTEL ");	96	printf ("INTEL ");
97	break;	97	break;
98	default:	98	default:
99	printf ("Unknown Vendor ");	99	printf ("Unknown Vendor ");
100	break;	100	break;
101	}	101	}
102		102
103	switch (info->flash_id & FLASH_TYPEMASK) {	103	switch (info->flash_id & FLASH_TYPEMASK) {
104	case FLASH_28F128J3A:	104	case FLASH_28F128J3A:
105	printf ("28F128J3A\n");	105	printf ("28F128J3A\n");
106	break;	106	break;
107	default:	107	default:
108	printf ("Unknown Chip Type\n");	108	printf ("Unknown Chip Type\n");
109	break;	109	break;
110	}	110	}
111		111
112	printf (" Size: %ld MB in %d Sectors\n",	112	printf (" Size: %ld MB in %d Sectors\n",
113	info->size >> 20, info->sector_count);	113	info->size >> 20, info->sector_count);
114		114
115	printf (" Sector Start Addresses:");	115	printf (" Sector Start Addresses:");
116	for (i = 0; i < info->sector_count; ++i) {	116	for (i = 0; i < info->sector_count; ++i) {
117	if ((i % 5) == 0)	117	if ((i % 5) == 0)
118	printf ("\n ");	118	printf ("\n ");
119	printf (" %08lX%s",	119	printf (" %08lX%s",
120	info->start[i], info->protect[i] ? " (RO)" : " ");	120	info->start[i], info->protect[i] ? " (RO)" : " ");
121	}	121	}
122	printf ("\n");	122	printf ("\n");
123	return;	123	return;
124	}	124	}
125		125
126	/*	126	/*
127	* The following code cannot be run from FLASH!	127	* The following code cannot be run from FLASH!
128	*/	128	*/
129	static ulong flash_get_size (unsigned char * addr, flash_info_t * info)	129	static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
130	{	130	{
131	volatile unsigned char value;	131	volatile unsigned char value;
132		132
133	/* Write auto select command: read Manufacturer ID */	133	/* Write auto select command: read Manufacturer ID */
134	addr[0x5555] = 0xAA;	134	addr[0x5555] = 0xAA;
135	addr[0x2AAA] = 0x55;	135	addr[0x2AAA] = 0x55;
136	addr[0x5555] = 0x90;	136	addr[0x5555] = 0x90;
137		137
138	mb ();	138	mb ();
139	value = addr[0];	139	value = addr[0];
140		140
141	switch (value) {	141	switch (value) {
142		142
143	case (unsigned char)INTEL_MANUFACT:	143	case (unsigned char)INTEL_MANUFACT:
144	info->flash_id = FLASH_MAN_INTEL;	144	info->flash_id = FLASH_MAN_INTEL;
145	break;	145	break;
146		146
147	default:	147	default:
148	info->flash_id = FLASH_UNKNOWN;	148	info->flash_id = FLASH_UNKNOWN;
149	info->sector_count = 0;	149	info->sector_count = 0;
150	info->size = 0;	150	info->size = 0;
151	addr[0] = 0xFF; /* restore read mode */	151	addr[0] = 0xFF; /* restore read mode */
152	return (0); /* no or unknown flash */	152	return (0); /* no or unknown flash */
153	}	153	}
154		154
155	mb ();	155	mb ();
156	value = addr[2]; /* device ID */	156	value = addr[2]; /* device ID */
157		157
158	switch (value) {	158	switch (value) {
159		159
160	case (unsigned char)INTEL_ID_28F640J3A:	160	case (unsigned char)INTEL_ID_28F640J3A:
161	info->flash_id += FLASH_28F640J3A;	161	info->flash_id += FLASH_28F640J3A;
162	info->sector_count = 64;	162	info->sector_count = 64;
163	info->size = 0x00800000;	163	info->size = 0x00800000;
164	break; /* => 8 MB */	164	break; /* => 8 MB */
165		165
166	case (unsigned char)INTEL_ID_28F128J3A:	166	case (unsigned char)INTEL_ID_28F128J3A:
167	info->flash_id += FLASH_28F128J3A;	167	info->flash_id += FLASH_28F128J3A;
168	info->sector_count = 128;	168	info->sector_count = 128;
169	info->size = 0x01000000;	169	info->size = 0x01000000;
170	break; /* => 16 MB */	170	break; /* => 16 MB */
171		171
172	default:	172	default:
173	info->flash_id = FLASH_UNKNOWN;	173	info->flash_id = FLASH_UNKNOWN;
174	break;	174	break;
175	}	175	}
176		176
177	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {	177	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
178	printf (" ERROR: sector count %d > max (%d) \n",	178	printf (" ERROR: sector count %d > max (%d) \n",
179	info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);	179	info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
180	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;	180	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
181	}	181	}
182		182
183	addr[0] = 0xFF; /* restore read mode */	183	addr[0] = 0xFF; /* restore read mode */
184		184
185	return (info->size);	185	return (info->size);
186	}	186	}
187		187
188		188
189	/*-----------------------------------------------------------------------	189	/*-----------------------------------------------------------------------
190	*/	190	*/
191		191
192	int flash_erase (flash_info_t * info, int s_first, int s_last)	192	int flash_erase (flash_info_t * info, int s_first, int s_last)
193	{	193	{
194	int prot, sect;	194	int prot, sect;
195	ulong type;	195	ulong type;
196	int rcode = 0;	196	int rcode = 0;
197	ulong start;	197	ulong start;
198		198
199	if ((s_first < 0) \|\| (s_first > s_last)) {	199	if ((s_first < 0) \|\| (s_first > s_last)) {
200	if (info->flash_id == FLASH_UNKNOWN) {	200	if (info->flash_id == FLASH_UNKNOWN) {
201	printf ("- missing\n");	201	printf ("- missing\n");
202	} else {	202	} else {
203	printf ("- no sectors to erase\n");	203	printf ("- no sectors to erase\n");
204	}	204	}
205	return 1;	205	return 1;
206	}	206	}
207		207
208	type = (info->flash_id & FLASH_VENDMASK);	208	type = (info->flash_id & FLASH_VENDMASK);
209	if ((type != FLASH_MAN_INTEL)) {	209	if ((type != FLASH_MAN_INTEL)) {
210	printf ("Can't erase unknown flash type %08lx - aborted\n",	210	printf ("Can't erase unknown flash type %08lx - aborted\n",
211	info->flash_id);	211	info->flash_id);
212	return 1;	212	return 1;
213	}	213	}
214		214
215	prot = 0;	215	prot = 0;
216	for (sect = s_first; sect <= s_last; ++sect) {	216	for (sect = s_first; sect <= s_last; ++sect) {
217	if (info->protect[sect]) {	217	if (info->protect[sect]) {
218	prot++;	218	prot++;
219	}	219	}
220	}	220	}
221		221
222	if (prot)	222	if (prot)
223	printf ("- Warning: %d protected sectors will not be erased!\n", prot);	223	printf ("- Warning: %d protected sectors will not be erased!\n", prot);
224	else	224	else
225	printf ("\n");	225	printf ("\n");
226		226
227	/* Disable interrupts which might cause a timeout here */	227	/* Disable interrupts which might cause a timeout here */
228	disable_interrupts();	228	disable_interrupts();
229		229
230	/* Start erase on unprotected sectors */	230	/* Start erase on unprotected sectors */
231	for (sect = s_first; sect <= s_last; sect++) {	231	for (sect = s_first; sect <= s_last; sect++) {
232	if (info->protect[sect] == 0) { /* not protected */	232	if (info->protect[sect] == 0) { /* not protected */
233	volatile unsigned char *addr;	233	volatile unsigned char *addr;
234	unsigned char status;	234	unsigned char status;
235		235
236	printf ("Erasing sector %2d ... ", sect);	236	printf ("Erasing sector %2d ... ", sect);
237		237
238	/* arm simple, non interrupt dependent timer */	238	/* arm simple, non interrupt dependent timer */
239	start = get_timer(0);	239	start = get_timer(0);
240		240
241	addr = (volatile unsigned char *) (info->start[sect]);	241	addr = (volatile unsigned char *) (info->start[sect]);
242	addr = 0x50; / clear status register */	242	addr = 0x50; / clear status register */
243	addr = 0x20; / erase setup */	243	addr = 0x20; / erase setup */
244	addr = 0xD0; / erase confirm */	244	addr = 0xD0; / erase confirm */
245		245
246	while (((status = *addr) & 0x80) != 0x80) {	246	while (((status = *addr) & 0x80) != 0x80) {
247	if (get_timer(start) >	247	if (get_timer(start) >
248	CONFIG_SYS_FLASH_ERASE_TOUT) {	248	CONFIG_SYS_FLASH_ERASE_TOUT) {
249	printf ("Timeout\n");	249	printf ("Timeout\n");
250	addr = 0xB0; / suspend erase */	250	addr = 0xB0; / suspend erase */
251	addr = 0xFF; / reset to read mode */	251	addr = 0xFF; / reset to read mode */
252	rcode = 1;	252	rcode = 1;
253	break;	253	break;
254	}	254	}
255	}	255	}
256		256
257	addr = 0x50; / clear status register cmd */	257	addr = 0x50; / clear status register cmd */
258	addr = 0xFF; / resest to read mode */	258	addr = 0xFF; / resest to read mode */
259		259
260	printf (" done\n");	260	printf (" done\n");
261	}	261	}
262	}	262	}
263	return rcode;	263	return rcode;
264	}	264	}
265		265
266	/*-----------------------------------------------------------------------	266	/*-----------------------------------------------------------------------
267	* Copy memory to flash, returns:	267	* Copy memory to flash, returns:
268	* 0 - OK	268	* 0 - OK
269	* 1 - write timeout	269	* 1 - write timeout
270	* 2 - Flash not erased	270	* 2 - Flash not erased
271	* 4 - Flash not identified	271	* 4 - Flash not identified
272	*/	272	*/
273		273
274	int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)	274	int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
275	{	275	{
276	ulong cp, wp;	276	ulong cp, wp;
277	unsigned char data;	277	unsigned char data;
278	int count, i, l, rc, port_width;	278	int count, i, l, rc, port_width;
279		279
280	if (info->flash_id == FLASH_UNKNOWN)	280	if (info->flash_id == FLASH_UNKNOWN)
281	return 4;	281	return 4;
282		282
283	wp = addr;	283	wp = addr;
284	port_width = 1;	284	port_width = 1;
285		285
286	/*	286	/*
287	* handle unaligned start bytes	287	* handle unaligned start bytes
288	*/	288	*/
289	if ((l = addr - wp) != 0) {	289	if ((l = addr - wp) != 0) {
290	data = 0;	290	data = 0;
291	for (i = 0, cp = wp; i < l; ++i, ++cp) {	291	for (i = 0, cp = wp; i < l; ++i, ++cp) {
292	data = (data << 8) \| ((uchar ) cp);	292	data = (data << 8) \| ((uchar ) cp);
293	}	293	}
294	for (; i < port_width && cnt > 0; ++i) {	294	for (; i < port_width && cnt > 0; ++i) {
295	data = (data << 8) \| *src++;	295	data = (data << 8) \| *src++;
296	--cnt;	296	--cnt;
297	++cp;	297	++cp;
298	}	298	}
299	for (; cnt == 0 && i < port_width; ++i, ++cp) {	299	for (; cnt == 0 && i < port_width; ++i, ++cp) {
300	data = (data << 8) \| ((uchar ) cp);	300	data = (data << 8) \| ((uchar ) cp);
301	}	301	}
302		302
303	if ((rc = write_data (info, wp, data)) != 0) {	303	if ((rc = write_data (info, wp, data)) != 0) {
304	return (rc);	304	return (rc);
305	}	305	}
306	wp += port_width;	306	wp += port_width;
307	}	307	}
308		308
309	/*	309	/*
310	* handle word aligned part	310	* handle word aligned part
311	*/	311	*/
312	count = 0;	312	count = 0;
313	while (cnt >= port_width) {	313	while (cnt >= port_width) {
314	data = 0;	314	data = 0;
315	for (i = 0; i < port_width; ++i) {	315	for (i = 0; i < port_width; ++i) {
316	data = (data << 8) \| *src++;	316	data = (data << 8) \| *src++;
317	}	317	}
318	if ((rc = write_data (info, wp, data)) != 0) {	318	if ((rc = write_data (info, wp, data)) != 0) {
319	return (rc);	319	return (rc);
320	}	320	}
321	wp += port_width;	321	wp += port_width;
322	cnt -= port_width;	322	cnt -= port_width;
323	if (count++ > 0x800) {	323	if (count++ > 0x800) {
324	spin_wheel ();	324	spin_wheel ();
325	count = 0;	325	count = 0;
326	}	326	}
327	}	327	}
328		328
329	if (cnt == 0) {	329	if (cnt == 0) {
330	return (0);	330	return (0);
331	}	331	}
332		332
333	/*	333	/*
334	* handle unaligned tail bytes	334	* handle unaligned tail bytes
335	*/	335	*/
336	data = 0;	336	data = 0;
337	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {	337	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
338	data = (data << 8) \| *src++;	338	data = (data << 8) \| *src++;
339	--cnt;	339	--cnt;
340	}	340	}
341	for (; i < port_width; ++i, ++cp) {	341	for (; i < port_width; ++i, ++cp) {
342	data = (data << 8) \| ((uchar ) cp);	342	data = (data << 8) \| ((uchar ) cp);
343	}	343	}
344		344
345	return (write_data (info, wp, data));	345	return (write_data (info, wp, data));
346	}	346	}
347		347
348	/*-----------------------------------------------------------------------	348	/*-----------------------------------------------------------------------
349	* Write a word or halfword to Flash, returns:	349	* Write a word or halfword to Flash, returns:
350	* 0 - OK	350	* 0 - OK
351	* 1 - write timeout	351	* 1 - write timeout
352	* 2 - Flash not erased	352	* 2 - Flash not erased
353	*/	353	*/
354	static int write_data (flash_info_t * info, ulong dest, unsigned char data)	354	static int write_data (flash_info_t * info, ulong dest, unsigned char data)
355	{	355	{
356	volatile unsigned char addr = (volatile unsigned char ) dest;	356	volatile unsigned char addr = (volatile unsigned char ) dest;
357	ulong status;	357	ulong status;
358	ulong start;	358	ulong start;
359		359
360	/* Check if Flash is (sufficiently) erased */	360	/* Check if Flash is (sufficiently) erased */
361	if ((*addr & data) != data) {	361	if ((*addr & data) != data) {
362	printf ("not erased at %08lx (%lx)\n", (ulong) addr,	362	printf ("not erased at %08lx (%lx)\n", (ulong) addr,
363	(ulong) * addr);	363	(ulong) * addr);
364	return (2);	364	return (2);
365	}	365	}
366	/* Disable interrupts which might cause a timeout here */	366	/* Disable interrupts which might cause a timeout here */
367	disable_interrupts();	367	disable_interrupts();
368		368
369	addr = 0x40; / write setup */	369	addr = 0x40; / write setup */
370	*addr = data;	370	*addr = data;
371		371
372	/* arm simple, non interrupt dependent timer */	372	/* arm simple, non interrupt dependent timer */
373	start = get_timer(0);	373	start = get_timer(0);
374		374
375	/* wait while polling the status register */	375	/* wait while polling the status register */
376	while (((status = *addr) & 0x80) != 0x80) {	376	while (((status = *addr) & 0x80) != 0x80) {
377	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {	377	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
378	addr = 0xFF; / restore read mode */	378	addr = 0xFF; / restore read mode */
379	return (1);	379	return (1);
380	}	380	}
381	}	381	}
382		382
383	addr = 0xFF; / restore read mode */	383	addr = 0xFF; / restore read mode */
384		384
385	return (0);	385	return (0);
386	}	386	}
387		387
388	void inline spin_wheel (void)	388	void inline spin_wheel (void)
389	{	389	{
390	static int p = 0;	390	static int p = 0;
391	static char w[] = "\\/-";	391	static char w[] = "\\/-";
392		392
393	printf ("\010%c", w[p]);	393	printf ("\010%c", w[p]);
394	(++p == 3) ? (p = 0) : 0;	394	(++p == 3) ? (p = 0) : 0;
395	}	395	}
396		396

board/cm41xx/flash.c

Diff comments View file @ b60eff3

1	/*	1	/*
2	* (C) Copyright 2005	2	* (C) Copyright 2005
3	* Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com	3	* Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
4	*	4	*
5	* (C) Copyright 2001	5	* (C) Copyright 2001
6	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net	6	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
7	*	7	*
8	* (C) Copyright 2001	8	* (C) Copyright 2001
9	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	9	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10	*	10	*
11	* SPDX-License-Identifier: GPL-2.0+	11	* SPDX-License-Identifier: GPL-2.0+
12	*/	12	*/
13		13
14	#include <common.h>	14	#include <common.h>
15	#include <linux/byteorder/swab.h>	15	#include <linux/byteorder/swab.h>
16	#include <asm/sections.h>	16	#include <asm/sections.h>
17		17
18		18
19	flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */	19	flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
20		20
21	#define mb() __asm__ __volatile__ ("" : : : "memory")	21	#define mb() __asm__ __volatile__ ("" : : : "memory")
22		22
23	/*-----------------------------------------------------------------------	23	/*-----------------------------------------------------------------------
24	* Functions	24	* Functions
25	*/	25	*/
26	static ulong flash_get_size (unsigned char * addr, flash_info_t * info);	26	static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
27	static int write_data (flash_info_t * info, ulong dest, unsigned char data);	27	static int write_data (flash_info_t * info, ulong dest, unsigned char data);
28	static void flash_get_offsets (ulong base, flash_info_t * info);	28	static void flash_get_offsets (ulong base, flash_info_t * info);
29	void inline spin_wheel (void);	29	void inline spin_wheel (void);
30		30
31	/*-----------------------------------------------------------------------	31	/*-----------------------------------------------------------------------
32	*/	32	*/
33		33
34	unsigned long flash_init (void)	34	unsigned long flash_init (void)
35	{	35	{
36	int i;	36	int i;
37	ulong size = 0;	37	ulong size = 0;
38		38
39	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {	39	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
40	switch (i) {	40	switch (i) {
41	case 0:	41	case 0:
42	flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);	42	flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
43	flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);	43	flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
44	break;	44	break;
45	case 1:	45	case 1:
46	/* ignore for now */	46	/* ignore for now */
47	flash_info[i].flash_id = FLASH_UNKNOWN;	47	flash_info[i].flash_id = FLASH_UNKNOWN;
48	break;	48	break;
49	default:	49	default:
50	panic ("configured too many flash banks!\n");	50	panic ("configured too many flash banks!\n");
51	break;	51	break;
52	}	52	}
53	size += flash_info[i].size;	53	size += flash_info[i].size;
54	}	54	}
55		55
56	/* Protect monitor and environment sectors	56	/* Protect monitor and environment sectors
57	*/	57	*/
58	flash_protect (FLAG_PROTECT_SET,	58	flash_protect (FLAG_PROTECT_SET,
59	CONFIG_SYS_FLASH_BASE,	59	CONFIG_SYS_FLASH_BASE,
60	CONFIG_SYS_FLASH_BASE + _bss_start_ofs,	60	CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
61	&flash_info[0]);	61	&flash_info[0]);
62		62
63	return size;	63	return size;
64	}	64	}
65		65
66	/*-----------------------------------------------------------------------	66	/*-----------------------------------------------------------------------
67	*/	67	*/
68	static void flash_get_offsets (ulong base, flash_info_t * info)	68	static void flash_get_offsets (ulong base, flash_info_t * info)
69	{	69	{
70	int i;	70	int i;
71		71
72	if (info->flash_id == FLASH_UNKNOWN)	72	if (info->flash_id == FLASH_UNKNOWN)
73	return;	73	return;
74		74
75	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {	75	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
76	for (i = 0; i < info->sector_count; i++) {	76	for (i = 0; i < info->sector_count; i++) {
77	info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);	77	info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
78	info->protect[i] = 0;	78	info->protect[i] = 0;
79	}	79	}
80	}	80	}
81	}	81	}
82		82
83	/*-----------------------------------------------------------------------	83	/*-----------------------------------------------------------------------
84	*/	84	*/
85	void flash_print_info (flash_info_t * info)	85	void flash_print_info (flash_info_t * info)
86	{	86	{
87	int i;	87	int i;
88		88
89	if (info->flash_id == FLASH_UNKNOWN) {	89	if (info->flash_id == FLASH_UNKNOWN) {
90	printf ("missing or unknown FLASH type\n");	90	printf ("missing or unknown FLASH type\n");
91	return;	91	return;
92	}	92	}
93		93
94	switch (info->flash_id & FLASH_VENDMASK) {	94	switch (info->flash_id & FLASH_VENDMASK) {
95	case FLASH_MAN_INTEL:	95	case FLASH_MAN_INTEL:
96	printf ("INTEL ");	96	printf ("INTEL ");
97	break;	97	break;
98	default:	98	default:
99	printf ("Unknown Vendor ");	99	printf ("Unknown Vendor ");
100	break;	100	break;
101	}	101	}
102		102
103	switch (info->flash_id & FLASH_TYPEMASK) {	103	switch (info->flash_id & FLASH_TYPEMASK) {
104	case FLASH_28F128J3A:	104	case FLASH_28F128J3A:
105	printf ("28F128J3A\n");	105	printf ("28F128J3A\n");
106	break;	106	break;
107	default:	107	default:
108	printf ("Unknown Chip Type\n");	108	printf ("Unknown Chip Type\n");
109	break;	109	break;
110	}	110	}
111		111
112	printf (" Size: %ld MB in %d Sectors\n",	112	printf (" Size: %ld MB in %d Sectors\n",
113	info->size >> 20, info->sector_count);	113	info->size >> 20, info->sector_count);
114		114
115	printf (" Sector Start Addresses:");	115	printf (" Sector Start Addresses:");
116	for (i = 0; i < info->sector_count; ++i) {	116	for (i = 0; i < info->sector_count; ++i) {
117	if ((i % 5) == 0)	117	if ((i % 5) == 0)
118	printf ("\n ");	118	printf ("\n ");
119	printf (" %08lX%s",	119	printf (" %08lX%s",
120	info->start[i], info->protect[i] ? " (RO)" : " ");	120	info->start[i], info->protect[i] ? " (RO)" : " ");
121	}	121	}
122	printf ("\n");	122	printf ("\n");
123	return;	123	return;
124	}	124	}
125		125
126	/*	126	/*
127	* The following code cannot be run from FLASH!	127	* The following code cannot be run from FLASH!
128	*/	128	*/
129	static ulong flash_get_size (unsigned char * addr, flash_info_t * info)	129	static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
130	{	130	{
131	volatile unsigned char value;	131	volatile unsigned char value;
132		132
133	/* Write auto select command: read Manufacturer ID */	133	/* Write auto select command: read Manufacturer ID */
134	addr[0x5555] = 0xAA;	134	addr[0x5555] = 0xAA;
135	addr[0x2AAA] = 0x55;	135	addr[0x2AAA] = 0x55;
136	addr[0x5555] = 0x90;	136	addr[0x5555] = 0x90;
137		137
138	mb ();	138	mb ();
139	value = addr[0];	139	value = addr[0];
140		140
141	switch (value) {	141	switch (value) {
142		142
143	case (unsigned char)INTEL_MANUFACT:	143	case (unsigned char)INTEL_MANUFACT:
144	info->flash_id = FLASH_MAN_INTEL;	144	info->flash_id = FLASH_MAN_INTEL;
145	break;	145	break;
146		146
147	default:	147	default:
148	info->flash_id = FLASH_UNKNOWN;	148	info->flash_id = FLASH_UNKNOWN;
149	info->sector_count = 0;	149	info->sector_count = 0;
150	info->size = 0;	150	info->size = 0;
151	addr[0] = 0xFF; /* restore read mode */	151	addr[0] = 0xFF; /* restore read mode */
152	return (0); /* no or unknown flash */	152	return (0); /* no or unknown flash */
153	}	153	}
154		154
155	mb ();	155	mb ();
156	value = addr[2]; /* device ID */	156	value = addr[2]; /* device ID */
157		157
158	switch (value) {	158	switch (value) {
159		159
160	case (unsigned char)INTEL_ID_28F640J3A:	160	case (unsigned char)INTEL_ID_28F640J3A:
161	info->flash_id += FLASH_28F640J3A;	161	info->flash_id += FLASH_28F640J3A;
162	info->sector_count = 64;	162	info->sector_count = 64;
163	info->size = 0x00800000;	163	info->size = 0x00800000;
164	break; /* => 8 MB */	164	break; /* => 8 MB */
165		165
166	case (unsigned char)INTEL_ID_28F128J3A:	166	case (unsigned char)INTEL_ID_28F128J3A:
167	info->flash_id += FLASH_28F128J3A;	167	info->flash_id += FLASH_28F128J3A;
168	info->sector_count = 128;	168	info->sector_count = 128;
169	info->size = 0x01000000;	169	info->size = 0x01000000;
170	break; /* => 16 MB */	170	break; /* => 16 MB */
171		171
172	default:	172	default:
173	info->flash_id = FLASH_UNKNOWN;	173	info->flash_id = FLASH_UNKNOWN;
174	break;	174	break;
175	}	175	}
176		176
177	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {	177	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
178	printf (" ERROR: sector count %d > max (%d) \n",	178	printf (" ERROR: sector count %d > max (%d) \n",
179	info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);	179	info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
180	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;	180	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
181	}	181	}
182		182
183	addr[0] = 0xFF; /* restore read mode */	183	addr[0] = 0xFF; /* restore read mode */
184		184
185	return (info->size);	185	return (info->size);
186	}	186	}
187		187
188		188
189	/*-----------------------------------------------------------------------	189	/*-----------------------------------------------------------------------
190	*/	190	*/
191		191
192	int flash_erase (flash_info_t * info, int s_first, int s_last)	192	int flash_erase (flash_info_t * info, int s_first, int s_last)
193	{	193	{
194	int prot, sect;	194	int prot, sect;
195	ulong type;	195	ulong type;
196	int rcode = 0;	196	int rcode = 0;
197	ulong start;	197	ulong start;
198		198
199	if ((s_first < 0) \|\| (s_first > s_last)) {	199	if ((s_first < 0) \|\| (s_first > s_last)) {
200	if (info->flash_id == FLASH_UNKNOWN) {	200	if (info->flash_id == FLASH_UNKNOWN) {
201	printf ("- missing\n");	201	printf ("- missing\n");
202	} else {	202	} else {
203	printf ("- no sectors to erase\n");	203	printf ("- no sectors to erase\n");
204	}	204	}
205	return 1;	205	return 1;
206	}	206	}
207		207
208	type = (info->flash_id & FLASH_VENDMASK);	208	type = (info->flash_id & FLASH_VENDMASK);
209	if ((type != FLASH_MAN_INTEL)) {	209	if ((type != FLASH_MAN_INTEL)) {
210	printf ("Can't erase unknown flash type %08lx - aborted\n",	210	printf ("Can't erase unknown flash type %08lx - aborted\n",
211	info->flash_id);	211	info->flash_id);
212	return 1;	212	return 1;
213	}	213	}
214		214
215	prot = 0;	215	prot = 0;
216	for (sect = s_first; sect <= s_last; ++sect) {	216	for (sect = s_first; sect <= s_last; ++sect) {
217	if (info->protect[sect]) {	217	if (info->protect[sect]) {
218	prot++;	218	prot++;
219	}	219	}
220	}	220	}
221		221
222	if (prot)	222	if (prot)
223	printf ("- Warning: %d protected sectors will not be erased!\n", prot);	223	printf ("- Warning: %d protected sectors will not be erased!\n", prot);
224	else	224	else
225	printf ("\n");	225	printf ("\n");
226		226
227	/* Disable interrupts which might cause a timeout here */	227	/* Disable interrupts which might cause a timeout here */
228	disable_interrupts();	228	disable_interrupts();
229		229
230	/* Start erase on unprotected sectors */	230	/* Start erase on unprotected sectors */
231	for (sect = s_first; sect <= s_last; sect++) {	231	for (sect = s_first; sect <= s_last; sect++) {
232	if (info->protect[sect] == 0) { /* not protected */	232	if (info->protect[sect] == 0) { /* not protected */
233	volatile unsigned char *addr;	233	volatile unsigned char *addr;
234	unsigned char status;	234	unsigned char status;
235		235
236	printf ("Erasing sector %2d ... ", sect);	236	printf ("Erasing sector %2d ... ", sect);
237		237
238	/* arm simple, non interrupt dependent timer */	238	/* arm simple, non interrupt dependent timer */
239	start = get_timer(0);	239	start = get_timer(0);
240		240
241	addr = (volatile unsigned char *) (info->start[sect]);	241	addr = (volatile unsigned char *) (info->start[sect]);
242	addr = 0x50; / clear status register */	242	addr = 0x50; / clear status register */
243	addr = 0x20; / erase setup */	243	addr = 0x20; / erase setup */
244	addr = 0xD0; / erase confirm */	244	addr = 0xD0; / erase confirm */
245		245
246	while (((status = *addr) & 0x80) != 0x80) {	246	while (((status = *addr) & 0x80) != 0x80) {
247	if (get_timer(start) >	247	if (get_timer(start) >
248	CONFIG_SYS_FLASH_ERASE_TOUT) {	248	CONFIG_SYS_FLASH_ERASE_TOUT) {
249	printf ("Timeout\n");	249	printf ("Timeout\n");
250	addr = 0xB0; / suspend erase */	250	addr = 0xB0; / suspend erase */
251	addr = 0xFF; / reset to read mode */	251	addr = 0xFF; / reset to read mode */
252	rcode = 1;	252	rcode = 1;
253	break;	253	break;
254	}	254	}
255	}	255	}
256		256
257	addr = 0x50; / clear status register cmd */	257	addr = 0x50; / clear status register cmd */
258	addr = 0xFF; / resest to read mode */	258	addr = 0xFF; / resest to read mode */
259		259
260	printf (" done\n");	260	printf (" done\n");
261	}	261	}
262	}	262	}
263	return rcode;	263	return rcode;
264	}	264	}
265		265
266	/*-----------------------------------------------------------------------	266	/*-----------------------------------------------------------------------
267	* Copy memory to flash, returns:	267	* Copy memory to flash, returns:
268	* 0 - OK	268	* 0 - OK
269	* 1 - write timeout	269	* 1 - write timeout
270	* 2 - Flash not erased	270	* 2 - Flash not erased
271	* 4 - Flash not identified	271	* 4 - Flash not identified
272	*/	272	*/
273		273
274	int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)	274	int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
275	{	275	{
276	ulong cp, wp;	276	ulong cp, wp;
277	unsigned char data;	277	unsigned char data;
278	int count, i, l, rc, port_width;	278	int count, i, l, rc, port_width;
279		279
280	if (info->flash_id == FLASH_UNKNOWN)	280	if (info->flash_id == FLASH_UNKNOWN)
281	return 4;	281	return 4;
282		282
283	wp = addr;	283	wp = addr;
284	port_width = 1;	284	port_width = 1;
285		285
286	/*	286	/*
287	* handle unaligned start bytes	287	* handle unaligned start bytes
288	*/	288	*/
289	if ((l = addr - wp) != 0) {	289	if ((l = addr - wp) != 0) {
290	data = 0;	290	data = 0;
291	for (i = 0, cp = wp; i < l; ++i, ++cp) {	291	for (i = 0, cp = wp; i < l; ++i, ++cp) {
292	data = (data << 8) \| ((uchar ) cp);	292	data = (data << 8) \| ((uchar ) cp);
293	}	293	}
294	for (; i < port_width && cnt > 0; ++i) {	294	for (; i < port_width && cnt > 0; ++i) {
295	data = (data << 8) \| *src++;	295	data = (data << 8) \| *src++;
296	--cnt;	296	--cnt;
297	++cp;	297	++cp;
298	}	298	}
299	for (; cnt == 0 && i < port_width; ++i, ++cp) {	299	for (; cnt == 0 && i < port_width; ++i, ++cp) {
300	data = (data << 8) \| ((uchar ) cp);	300	data = (data << 8) \| ((uchar ) cp);
301	}	301	}
302		302
303	if ((rc = write_data (info, wp, data)) != 0) {	303	if ((rc = write_data (info, wp, data)) != 0) {
304	return (rc);	304	return (rc);
305	}	305	}
306	wp += port_width;	306	wp += port_width;
307	}	307	}
308		308
309	/*	309	/*
310	* handle word aligned part	310	* handle word aligned part
311	*/	311	*/
312	count = 0;	312	count = 0;
313	while (cnt >= port_width) {	313	while (cnt >= port_width) {
314	data = 0;	314	data = 0;
315	for (i = 0; i < port_width; ++i) {	315	for (i = 0; i < port_width; ++i) {
316	data = (data << 8) \| *src++;	316	data = (data << 8) \| *src++;
317	}	317	}
318	if ((rc = write_data (info, wp, data)) != 0) {	318	if ((rc = write_data (info, wp, data)) != 0) {
319	return (rc);	319	return (rc);
320	}	320	}
321	wp += port_width;	321	wp += port_width;
322	cnt -= port_width;	322	cnt -= port_width;
323	if (count++ > 0x800) {	323	if (count++ > 0x800) {
324	spin_wheel ();	324	spin_wheel ();
325	count = 0;	325	count = 0;
326	}	326	}
327	}	327	}
328		328
329	if (cnt == 0) {	329	if (cnt == 0) {
330	return (0);	330	return (0);
331	}	331	}
332		332
333	/*	333	/*
334	* handle unaligned tail bytes	334	* handle unaligned tail bytes
335	*/	335	*/
336	data = 0;	336	data = 0;
337	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {	337	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
338	data = (data << 8) \| *src++;	338	data = (data << 8) \| *src++;
339	--cnt;	339	--cnt;
340	}	340	}
341	for (; i < port_width; ++i, ++cp) {	341	for (; i < port_width; ++i, ++cp) {
342	data = (data << 8) \| ((uchar ) cp);	342	data = (data << 8) \| ((uchar ) cp);
343	}	343	}
344		344
345	return (write_data (info, wp, data));	345	return (write_data (info, wp, data));
346	}	346	}
347		347
348	/*-----------------------------------------------------------------------	348	/*-----------------------------------------------------------------------
349	* Write a word or halfword to Flash, returns:	349	* Write a word or halfword to Flash, returns:
350	* 0 - OK	350	* 0 - OK
351	* 1 - write timeout	351	* 1 - write timeout
352	* 2 - Flash not erased	352	* 2 - Flash not erased
353	*/	353	*/
354	static int write_data (flash_info_t * info, ulong dest, unsigned char data)	354	static int write_data (flash_info_t * info, ulong dest, unsigned char data)
355	{	355	{
356	volatile unsigned char addr = (volatile unsigned char ) dest;	356	volatile unsigned char addr = (volatile unsigned char ) dest;
357	ulong status;	357	ulong status;
358	ulong start;	358	ulong start;
359		359
360	/* Check if Flash is (sufficiently) erased */	360	/* Check if Flash is (sufficiently) erased */
361	if ((*addr & data) != data) {	361	if ((*addr & data) != data) {
362	printf ("not erased at %08lx (%lx)\n", (ulong) addr,	362	printf ("not erased at %08lx (%lx)\n", (ulong) addr,
363	(ulong) * addr);	363	(ulong) * addr);
364	return (2);	364	return (2);
365	}	365	}
366	/* Disable interrupts which might cause a timeout here */	366	/* Disable interrupts which might cause a timeout here */
367	disable_interrupts();	367	disable_interrupts();
368		368
369	addr = 0x40; / write setup */	369	addr = 0x40; / write setup */
370	*addr = data;	370	*addr = data;
371		371
372	/* arm simple, non interrupt dependent timer */	372	/* arm simple, non interrupt dependent timer */
373	start = get_timer(0);	373	start = get_timer(0);
374		374
375	/* wait while polling the status register */	375	/* wait while polling the status register */
376	while (((status = *addr) & 0x80) != 0x80) {	376	while (((status = *addr) & 0x80) != 0x80) {
377	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {	377	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
378	addr = 0xFF; / restore read mode */	378	addr = 0xFF; / restore read mode */
379	return (1);	379	return (1);
380	}	380	}
381	}	381	}
382		382
383	addr = 0xFF; / restore read mode */	383	addr = 0xFF; / restore read mode */
384		384
385	return (0);	385	return (0);
386	}	386	}
387		387
388	void inline spin_wheel (void)	388	void inline spin_wheel (void)
389	{	389	{
390	static int p = 0;	390	static int p = 0;
391	static char w[] = "\\/-";	391	static char w[] = "\\/-";
392		392
393	printf ("\010%c", w[p]);	393	printf ("\010%c", w[p]);
394	(++p == 3) ? (p = 0) : 0;	394	(++p == 3) ? (p = 0) : 0;
395	}	395	}
396		396

board/mpl/vcma9/lowlevel_init.S

Diff comments View file @ b60eff3

 /*
  * Memory Setup stuff - taken from blob memsetup.S
  *
  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  *
  * Modified for MPL VCMA9 by
  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  * (C) Copyright 2002, 2003, 2004, 2005
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
 #include <version.h>
 /* register definitions */
 #define PLD_BASE	0x28000000
 #define MISC_REG	0x103
 #define SDRAM_REG	0x106
 #define BWSCON		0x48000000
 #define CLKBASE		0x4C000000
 #define LOCKTIME	0x0
 #define MPLLCON		0x4
 #define UPLLCON		0x8
 #define GPIOBASE	0x56000000
 #define GSTATUS1	0xB0
 #define FASTCPU		0x02
 /* some parameters for the board */
 /* BWSCON */
 #define DW8			(0x0)
 #define DW16			(0x1)
 #define DW32			(0x2)
 #define WAIT			(0x1<<2)
 #define UBLB			(0x1<<3)
 /* BANKSIZE */
 #define BURST_EN		(0x1<<7)
 /* BANK0CON 200 */
 #define B0_Tacs_200		0x0	/*  0clk  (or 0x1 1clk) */
 #define B0_Tcos_200		0x1	/*  1clk  (or 0x2 2clk) */
 #define B0_Tacc_200		0x5	/*  8clk  (or 0x6 10clk) */
 #define B0_Tcoh_200		0x0	/*  0clk */
 #define B0_Tcah_200		0x3	/*  4clk  (or0x01 1clk) */
 #define B0_Tacp_200		0x0     /* page mode is not used */
 #define B0_PMC_200		0x0	/* page mode disabled */
 /* BANK0CON 250 */
 #define B0_Tacs_250		0x0	/*  0clk  (or 0x1 1clk) */
 #define B0_Tcos_250		0x1	/*  1clk  (or 0x2 2clk) */
 #define B0_Tacc_250		0x5	/*  8clk  (or 0x7 14clk) */
 #define B0_Tcoh_250		0x0	/*  0clk */
 #define B0_Tcah_250		0x3	/*  4clk  (or 0x1 1clk) */
 #define B0_Tacp_250		0x0     /* page mode is not used */
 #define B0_PMC_250		0x0	/* page mode disabled */
 /* BANK0CON 266 */
 #define B0_Tacs_266		0x0	/*  0clk  (or 0x1 1clk) */
 #define B0_Tcos_266		0x1	/*  1clk  (or 0x2 2clk) */
 #define B0_Tacc_266		0x6	/*  10clk (or 0x7 14clk) */
 #define B0_Tcoh_266		0x0	/*  0clk */
 #define B0_Tcah_266		0x3	/*  4clk  (or 0x1 1clk) */
 #define B0_Tacp_266		0x0     /* page mode is not used */
 #define B0_PMC_266		0x0	/* page mode disabled */
 /* BANK1CON 200 */
 #define B1_Tacs_200		0x0	/*  0clk  (or 0x1 1clk) */
 #define B1_Tcos_200		0x1	/*  1clk  (or 0x2 2clk) */
 #define B1_Tacc_200		0x5	/*  8clk  (or 0x6 10clk) */
 #define B1_Tcoh_200		0x0	/*  0clk */
 #define B1_Tcah_200		0x3	/*  4clk  (or 0x1 1clk) */
 #define B1_Tacp_200		0x0     /* page mode is not used */
 #define B1_PMC_200		0x0	/* page mode disabled */
 /* BANK1CON 250 */
 #define B1_Tacs_250		0x0	/*  0clk  (or 0x1 1clk) */
 #define B1_Tcos_250		0x1	/*  1clk  (or 0x2 2clk) */
 #define B1_Tacc_250		0x5	/*  8clk  (or 0x7 14clk) */
 #define B1_Tcoh_250		0x0	/*  0clk */
 #define B1_Tcah_250		0x3	/*  4clk  (or 0x1 1clk) */
 #define B1_Tacp_250		0x0     /* page mode is not used */
 #define B1_PMC_250		0x0	/* page mode disabled */
 /* BANK1CON 266 */
 #define B1_Tacs_266		0x0	/*  0clk  (or 0x1 1clk) */
 #define B1_Tcos_266		0x1	/*  1clk  (or 0x2 2clk) */
 #define B1_Tacc_266		0x6	/*  10clk (or 0x7 14clk) */
 #define B1_Tcoh_266		0x0	/*  0clk */
 #define B1_Tcah_266		0x3	/*  4clk  (or 0x1 1clk) */
 #define B1_Tacp_266		0x0     /* page mode is not used */
 #define B1_PMC_266		0x0	/* page mode disabled */
 /* BANK2CON 200 + 250 + 266 */
 #define B2_Tacs			0x3	/*  4clk */
 #define B2_Tcos			0x3	/*  4clk */
 #define B2_Tacc			0x7     /* 14clk */
 #define B2_Tcoh			0x3	/*  4clk */
 #define B2_Tcah			0x3	/*  4clk */
 #define B2_Tacp			0x0	/* page mode is not used */
 #define B2_PMC			0x0     /* page mode disabled */
 /* BANK3CON 200 + 250 + 266 */
 #define B3_Tacs			0x3	/*  4clk */
 #define B3_Tcos			0x3	/*  4clk */
 #define B3_Tacc			0x7     /* 14clk */
 #define B3_Tcoh			0x3	/*  4clk */
 #define B3_Tcah			0x3	/*  4clk */
 #define B3_Tacp			0x0	/* page mode is not used */
 #define B3_PMC			0x0     /* page mode disabled */
 /* BANK4CON 200 */
 #define B4_Tacs_200		0x1	/*  1clk */
 #define B4_Tcos_200		0x3	/*  4clk */
 #define B4_Tacc_200		0x7	/* 14clk */
 #define B4_Tcoh_200		0x3	/*  4clk */
 #define B4_Tcah_200		0x2	/*  2clk */
 #define B4_Tacp_200		0x0     /* page mode is not used */
 #define B4_PMC_200		0x0	/* page mode disabled */
 /* BANK4CON 250 */
 #define B4_Tacs_250		0x1	/*  1clk */
 #define B4_Tcos_250		0x3	/*  4clk */
 #define B4_Tacc_250		0x7	/* 14clk */
 #define B4_Tcoh_250		0x3	/*  4clk */
 #define B4_Tcah_250		0x2	/*  2clk */
 #define B4_Tacp_250		0x0     /* page mode is not used */
 #define B4_PMC_250		0x0	/* page mode disabled */
 /* BANK4CON 266 */
 #define B4_Tacs_266		0x1	/*  1clk */
 #define B4_Tcos_266		0x3	/*  4clk */
 #define B4_Tacc_266		0x7	/* 14clk */
 #define B4_Tcoh_266		0x3	/*  4clk */
 #define B4_Tcah_266		0x2	/*  2clk */
 #define B4_Tacp_266		0x0     /* page mode is not used */
 #define B4_PMC_266		0x0	/* page mode disabled */
 /* BANK5CON 200 */
 #define B5_Tacs_200		0x0	/*  0clk */
 #define B5_Tcos_200		0x3	/*  4clk */
 #define B5_Tacc_200		0x4	/*  6clk */
 #define B5_Tcoh_200		0x3	/*  4clk */
 #define B5_Tcah_200		0x1	/*  1clk */
 #define B5_Tacp_200		0x0     /* page mode is not used */
 #define B5_PMC_200		0x0	/* page mode disabled */
 /* BANK5CON 250 */
 #define B5_Tacs_250		0x0	/*  0clk */
 #define B5_Tcos_250		0x3	/*  4clk */
 #define B5_Tacc_250		0x5	/*  8clk */
 #define B5_Tcoh_250		0x3	/*  4clk */
 #define B5_Tcah_250		0x1	/*  1clk */
 #define B5_Tacp_250		0x0     /* page mode is not used */
 #define B5_PMC_250		0x0	/* page mode disabled */
 /* BANK5CON 266 */
 #define B5_Tacs_266		0x0	/*  0clk */
 #define B5_Tcos_266		0x3	/*  4clk */
 #define B5_Tacc_266		0x5	/*  8clk */
 #define B5_Tcoh_266		0x3	/*  4clk */
 #define B5_Tcah_266		0x1	/*  1clk */
 #define B5_Tacp_266		0x0     /* page mode is not used */
 #define B5_PMC_266		0x0	/* page mode disabled */
 #define B6_MT			0x3	/* SDRAM */
 #define B6_Trcd_200		0x0	/* 2clk */
 #define B6_Trcd_250		0x1	/* 3clk */
 #define B6_Trcd_266		0x1	/* 3clk */
 #define B6_SCAN			0x2	/* 10bit */
 #define B7_MT			0x3	/* SDRAM */
 #define B7_Trcd_200		0x0	/* 2clk */
 #define B7_Trcd_250		0x1	/* 3clk */
 #define B7_Trcd_266		0x1	/* 3clk */
 #define B7_SCAN			0x2	/* 10bit */
 /* REFRESH parameter */
 #define REFEN			0x1	/* Refresh enable */
 #define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
 #define Trp_200			0x0	/* 2clk */
 #define Trp_250			0x1	/* 3clk */
 #define Trp_266			0x1	/* 3clk */
 #define Tsrc_200		0x1	/* 5clk */
 #define Tsrc_250		0x2	/* 6clk */
 #define Tsrc_266		0x3	/* 7clk */
 /* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
 #define REFCNT_200		489
 /* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
 #define REFCNT_250		99
 /* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
 #define REFCNT_266		0
 /**************************************/
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
 .globl lowlevel_init
 lowlevel_init:
 	/* use r0 to relocate DATA read/write to flash rather than memory ! */
-	ldr	r0, _TEXT_BASE
+	ldr	r0, =CONFIG_SYS_TEXT_BASE
 	ldr	r13, =BWSCON
 	/* enable minimal access to PLD */
 	ldr	r1, [r13]			/* load default BWSCON */
 	orr	r1, r1, #(DW8 + UBLB) << 20	/* set necessary CS attrs */
 	str	r1, [r13]			/* set BWSCON */
 	ldr	r1, =0x7FF0			/* select slowest timing */
 	str	r1, [r13, #0x18]		/* set BANKCON5 */
 	ldr	r1, =PLD_BASE
 	ldr	r2, =SETUPDATA
 	ldrb	r1, [r1, #MISC_REG]
 	sub	r2, r2, r0
 	tst	r1, #FASTCPU			/* FASTCPU available ? */
 	addeq	r2, r2, #SETUPENTRY_SIZE
 	/* memory control configuration */
 	/* r2 = pointer into timing table */
 	/* r13 = pointer to MEM controller regs (starting with BWSCON) */
 	add     r3, r2, #CSDATA_OFFSET
 	add     r4, r3, #CSDATAENTRY_SIZE
 0:
 	ldr     r1, [r3], #4
 	str     r1, [r13], #4
 	cmp     r3, r4
 	bne     0b
 	/* PLD access is now possible */
 	/* r3 = SDRAMDATA
 	/* r13 = pointer to MEM controller regs */
 	ldr	r1, =PLD_BASE
 	mov	r4, #SDRAMENTRY_SIZE
 	ldrb	r1, [r1, #SDRAM_REG]
 	/* calculate start and end point */
 	mla	r3, r4, r1, r3
 	add     r4, r3, r4
 0:
 	ldr     r1, [r3], #4
 	str     r1, [r13], #4
 	cmp     r3, r4
 	bne     0b
 	/* setup MPLL registers */
 	ldr	r1, =CLKBASE
 	ldr	r4, =0xFFFFFF
 	add	r3, r2, #4		/* r3 points to PLL values */
 	str	r4, [r1, #LOCKTIME]
 	ldmia	r3, {r4,r5}
 	str	r5, [r1, #UPLLCON]	/* writing PLL register */
 					/* !! order seems to be important !! */
 	/* a little delay */
 	ldr	r3, =0x4000
 0:
 	subs	r3, r3, #1
 	bne	0b
 	str	r4, [r1, #MPLLCON]	/* writing PLL register */
 					/* !! order seems to be important !! */
 	/* a little delay */
 	ldr	r3, =0x4000
 0:
 	subs	r3, r3, #1
 	bne	0b
 	/* everything is fine now */
 	mov	pc, lr
 	.ltorg
 /* the literal pools origin */
 #define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
 	((bws1) << 4) + \
 	((bws2) << 8) + \
 	((bws3) << 12) + \
 	((bws4) << 16) + \
 	((bws5) << 20) + \
 	((bws6) << 24) + \
 	((bws7) << 28)
 #define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
 	((tacs) << 13) + \
 	((tcos) << 11) + \
 	((tacc) << 8) + \
 	((tcoh) << 6) + \
 	((tcah) << 4) + \
 	((tacp) << 2) + \
 	(pmc)
 #define MK_BANKCON_SDRAM(trcd, scan) \
 	((0x03) << 15) + \
 	((trcd) << 2) + \
 	(scan)
 #define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
 	((enable) << 23) + \
 	((trefmd) << 22) + \
 	((trp) << 20) + \
 	((tsrc) << 18) + \
 	(cnt)
 SETUPDATA:
 	.word 0x32410002
 	/* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
 	.word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
 	/* PLL values for USB clock */
 	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
 	/* timing for 250 MHz*/
 0:
 	.equiv CSDATA_OFFSET, (. - SETUPDATA)
 	.word MK_BWSCON(DW16, \
 			DW32, \
 			DW32, \
 			DW16 + WAIT + UBLB, \
 			DW8 + UBLB, \
 			DW32, \
 			DW32)
 	.word MK_BANKCON(B0_Tacs_250, \
 			 B0_Tcos_250, \
 			 B0_Tacc_250, \
 			 B0_Tcoh_250, \
 			 B0_Tcah_250, \
 			 B0_Tacp_250, \
 			 B0_PMC_250)
 	.word MK_BANKCON(B1_Tacs_250, \
 			 B1_Tcos_250, \
 			 B1_Tacc_250, \
 			 B1_Tcoh_250, \
 			 B1_Tcah_250, \
 			 B1_Tacp_250, \
 			 B1_PMC_250)
 	.word MK_BANKCON(B2_Tacs, \
 			 B2_Tcos, \
 			 B2_Tacc, \
 			 B2_Tcoh, \
 			 B2_Tcah, \
 			 B2_Tacp, \
 			 B2_PMC)
 	.word MK_BANKCON(B3_Tacs, \
 			 B3_Tcos, \
 			 B3_Tacc, \
 			 B3_Tcoh, \
 			 B3_Tcah, \
 			 B3_Tacp, \
 			 B3_PMC)
 	.word MK_BANKCON(B4_Tacs_250, \
 			 B4_Tcos_250, \
 			 B4_Tacc_250, \
 			 B4_Tcoh_250, \
 			 B4_Tcah_250, \
 			 B4_Tacp_250, \
 			 B4_PMC_250)
 	.word MK_BANKCON(B5_Tacs_250, \
 			 B5_Tcos_250, \
 			 B5_Tacc_250, \
 			 B5_Tcoh_250, \
 			 B5_Tcah_250, \
 			 B5_Tacp_250, \
 			 B5_PMC_250)
 	.equiv CSDATAENTRY_SIZE, (. - 0b)
 	/* 4Mx8x4 */
 0:
 	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
 	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
 	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
 	.word 0x32 + BURST_EN
 	.word 0x30
 	.word 0x30
 	.equiv SDRAMENTRY_SIZE, (. - 0b)
 	/* 8Mx8x4 */
 	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
 	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
 	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
 	.word 0x32 + BURST_EN
 	.word 0x30
 	.word 0x30
 	/* 2Mx8x4 */
 	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
 	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
 	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
 	.word 0x32 + BURST_EN
 	.word 0x30
 	.word 0x30
 	/* 4Mx8x2 */
 	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
 	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
 	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
 	.word 0x32 + BURST_EN
 	.word 0x30
 	.word 0x30
 	.equiv SETUPENTRY_SIZE, (. - SETUPDATA)
 	.word 0x32410000
 	/* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
 	.word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
 	/* PLL values for USB clock */
 	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
 	/* timing for 200 MHz and default*/
 	.word MK_BWSCON(DW16, \
 			DW32, \
 			DW32, \
 			DW16 + WAIT + UBLB, \
 			DW8 + UBLB, \
 			DW32, \
 			DW32)
 	.word MK_BANKCON(B0_Tacs_200, \
 			 B0_Tcos_200, \
 			 B0_Tacc_200, \
 			 B0_Tcoh_200, \
 			 B0_Tcah_200, \
 			 B0_Tacp_200, \
 			 B0_PMC_200)
 	.word MK_BANKCON(B1_Tacs_200, \
 			 B1_Tcos_200, \
 			 B1_Tacc_200, \
 			 B1_Tcoh_200, \
 			 B1_Tcah_200, \
 			 B1_Tacp_200, \
 			 B1_PMC_200)
 	.word MK_BANKCON(B2_Tacs, \
 			 B2_Tcos, \
 			 B2_Tacc, \
 			 B2_Tcoh, \
 			 B2_Tcah, \
 			 B2_Tacp, \
 			 B2_PMC)
 	.word MK_BANKCON(B3_Tacs, \
 			 B3_Tcos, \
 			 B3_Tacc, \
 			 B3_Tcoh, \
 			 B3_Tcah, \
 			 B3_Tacp, \
 			 B3_PMC)
 	.word MK_BANKCON(B4_Tacs_200, \
 			 B4_Tcos_200, \
 			 B4_Tacc_200, \
 			 B4_Tcoh_200, \
 			 B4_Tcah_200, \
 			 B4_Tacp_200, \
 			 B4_PMC_200)
 	.word MK_BANKCON(B5_Tacs_200, \
 			 B5_Tcos_200, \
 			 B5_Tacc_200, \
 			 B5_Tcoh_200, \
 			 B5_Tcah_200, \
 			 B5_Tacp_200, \
 			 B5_PMC_200)
 	/* 4Mx8x4 */
 	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
 	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
 	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
 	.word 0x32 + BURST_EN
 	.word 0x30
 	.word 0x30
 	/* 8Mx8x4 */
 	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
 	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
 	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
 	.word 0x32 + BURST_EN
 	.word 0x30
 	.word 0x30
 	/* 2Mx8x4 */
 	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
 	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
 	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
 	.word 0x32 + BURST_EN
 	.word 0x30
 	.word 0x30
 	/* 4Mx8x2 */
 	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
 	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
 	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
 	.word 0x32 + BURST_EN
 	.word 0x30
 	.word 0x30
 	.equiv SETUPDATA_SIZE, (. - SETUPDATA)

board/samsung/goni/lowlevel_init.S

Diff comments View file @ b60eff3

 /*
  * Memory Setup stuff - taken from blob memsetup.S
  *
  * Copyright (C) 2009 Samsung Electronics
  * Kyungmin Park <kyungmin.park@samsung.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
 #include <version.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/power.h>
 /*
  * Register usages:
  *
  * r5 has zero always
  * r7 has S5PC100 GPIO base, 0xE0300000
  * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
  * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
  */
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
 	.globl lowlevel_init
 lowlevel_init:
 	mov	r11, lr
 	/* r5 has always zero */
 	mov	r5, #0
 	ldr	r7, =S5PC100_GPIO_BASE
 	ldr	r8, =S5PC100_GPIO_BASE
 	/* Read CPU ID */
 	ldr	r2, =S5PC110_PRO_ID
 	ldr	r0, [r2]
 	mov	r1, #0x00010000
 	and	r0, r0, r1
 	cmp	r0, r5
 	beq	100f
 	ldr	r8, =S5PC110_GPIO_BASE
 100:
 	/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
 	cmp	r7, r8
 	beq	skip_check_didle			@ Support C110 only
 	ldr	r0, =S5PC110_RST_STAT
 	ldr	r1, [r0]
 	and	r1, r1, #0x000D0000
 	cmp	r1, #(0x1 << 19)			@ DEEPIDLE_WAKEUP
 	beq	didle_wakeup
 	cmp	r7, r8
 skip_check_didle:
 	addeq	r0, r8, #0x280				@ S5PC100_GPIO_J4
 	addne	r0, r8, #0x2C0				@ S5PC110_GPIO_J4
 	ldr	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
 	bic	r1, r1, #(0xf << 4)			@ 1 * 4-bit
 	orr	r1, r1, #(0x1 << 4)
 	str	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
 	ldr	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
 	bic	r1, r1, #(1 << 1)
 	str	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
 	/* Don't setup at s5pc100 */
 	beq	100f
 	/*
 	 * Initialize Async Register Setting for EVT1
 	 * Because we are setting EVT1 as the default value of EVT0,
 	 * setting EVT0 as well does not make things worse.
 	 * Thus, for the simplicity, we set for EVT0, too
 	 *
 	 * The "Async Registers" are:
 	 *	0xE0F0_0000
 	 *	0xE1F0_0000
 	 *	0xF180_0000
 	 *	0xF190_0000
 	 *	0xF1A0_0000
 	 *	0xF1B0_0000
 	 *	0xF1C0_0000
 	 *	0xF1D0_0000
 	 *	0xF1E0_0000
 	 *	0xF1F0_0000
 	 *	0xFAF0_0000
 	 */
 	ldr     r0, =0xe0f00000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xe1f00000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xf1800000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xf1900000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xf1a00000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xf1b00000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xf1c00000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xf1d00000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xf1e00000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xf1f00000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	ldr     r0, =0xfaf00000
 	ldr     r1, [r0]
 	bic     r1, r1, #0x1
 	str     r1, [r0]
 	/*
 	 * Diable ABB block to reduce sleep current at low temperature
 	 * Note that it's hidden register setup don't modify it
 	 */
 	ldr	r0, =0xE010C300
 	ldr	r1, =0x00800000
 	str	r1, [r0]
 100:
 	/* IO retension release */
 	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
 	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
 	ldr	r1, [r0]
 	ldreq	r2, =(1 << 31)				@ IO_RET_REL
 	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
 	orr	r1, r1, r2
 	/* Do not release retention here for S5PC110 */
 	streq	r1, [r0]
 	/* Disable Watchdog */
 	ldreq	r0, =S5PC100_WATCHDOG_BASE		@ 0xEA200000
 	ldrne	r0, =S5PC110_WATCHDOG_BASE		@ 0xE2700000
 	str	r5, [r0]
 	/* setting SRAM */
 	ldreq	r0, =S5PC100_SROMC_BASE
 	ldrne	r0, =S5PC110_SROMC_BASE
 	ldr	r1, =0x9
 	str	r1, [r0]
 	/* S5PC100 has 3 groups of interrupt sources */
 	ldreq	r0, =S5PC100_VIC0_BASE			@ 0xE4000000
 	ldrne	r0, =S5PC110_VIC0_BASE			@ 0xF2000000
 	add	r1, r0, #0x00100000
 	add	r2, r0, #0x00200000
 	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
 	mvn	r3, #0x0
 	str	r3, [r0, #0x14]				@ INTENCLEAR
 	str	r3, [r1, #0x14]				@ INTENCLEAR
 	str	r3, [r2, #0x14]				@ INTENCLEAR
 	/* Set all interrupts as IRQ */
 	str	r5, [r0, #0xc]				@ INTSELECT
 	str	r5, [r1, #0xc]				@ INTSELECT
 	str	r5, [r2, #0xc]				@ INTSELECT
 	/* Pending Interrupt Clear */
 	str	r5, [r0, #0xf00]			@ INTADDRESS
 	str	r5, [r1, #0xf00]			@ INTADDRESS
 	str	r5, [r2, #0xf00]			@ INTADDRESS
 	/* for UART */
 	bl	uart_asm_init
 	bl	internal_ram_init
 	cmp	r7, r8
 	/* Clear wakeup status register */
 	ldreq	r0, =S5PC100_WAKEUP_STAT
 	ldrne	r0, =S5PC110_WAKEUP_STAT
 	ldr	r1, [r0]
 	str	r1, [r0]
 	/* IO retension release */
 	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
 	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
 	ldr	r1, [r0]
 	ldreq	r2, =(1 << 31)				@ IO_RET_REL
 	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
 	orr	r1, r1, r2
 	str	r1, [r0]
 	b	1f
 didle_wakeup:
 	/* Wait when APLL is locked */
 	ldr	r0, =0xE0100100			@ S5PC110_APLL_CON
 lockloop:
 	ldr	r1, [r0]
 	and	r1, r1, #(1 << 29)
 	cmp	r1, #(1 << 29)
 	bne	lockloop
 	ldr	r0, =S5PC110_INFORM0
 	ldr	r1, [r0]
 	mov	pc, r1
 	nop
 	nop
 	nop
 	nop
 	nop
 1:
 	mov	lr, r11
 	mov	pc, lr
 /*
  * system_clock_init: Initialize core clock and bus clock.
  * void system_clock_init(void)
  */
 system_clock_init:
 	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
 	/* Check S5PC100 */
 	cmp	r7, r8
 	bne	110f
 100:
 	/* Set Lock Time */
 	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
 	str	r1, [r0, #0x000]		@ S5PC100_APLL_LOCK
 	str	r1, [r0, #0x004]		@ S5PC100_MPLL_LOCK
 	str	r1, [r0, #0x008]		@ S5PC100_EPLL_LOCK
 	str	r1, [r0, #0x00C]		@ S5PC100_HPLL_LOCK
 	/* S5P_APLL_CON */
 	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
 	str	r1, [r0, #0x100]
 	/* S5P_MPLL_CON */
 	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
 	str	r1, [r0, #0x104]
 	/* S5P_EPLL_CON */
 	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
 	str	r1, [r0, #0x108]
 	/* S5P_HPLL_CON */
 	ldr	r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96
 	str	r1, [r0, #0x10C]
 	ldr     r1, [r0, #0x300]
 	ldr     r2, =0x00003fff
 	bic     r1, r1, r2
 	ldr     r2, =0x00011301
 	orr	r1, r1, r2
 	str	r1, [r0, #0x300]
 	ldr     r1, [r0, #0x304]
 	ldr     r2, =0x00011110
 	orr     r1, r1, r2
 	str     r1, [r0, #0x304]
 	ldr     r1, =0x00000001
 	str     r1, [r0, #0x308]
 	/* Set Source Clock */
 	ldr	r1, =0x00001111			@ A, M, E, HPLL Muxing
 	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
 	b	200f
 110:
 	ldr	r0, =0xE010C000			@ S5PC110_PWR_CFG
 	/* Set OSC_FREQ value */
 	ldr	r1, =0xf
 	str	r1, [r0, #0x100]		@ S5PC110_OSC_FREQ
 	/* Set MTC_STABLE value */
 	ldr	r1, =0xffffffff
 	str	r1, [r0, #0x110]		@ S5PC110_MTC_STABLE
 	/* Set CLAMP_STABLE value */
 	ldr	r1, =0x3ff03ff
 	str	r1, [r0, #0x114]		@ S5PC110_CLAMP_STABLE
 	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
 	/* Set Clock divider */
 	ldr	r1, =0x14131330			@ 1:1:4:4, 1:4:5
 	str	r1, [r0, #0x300]
 	ldr	r1, =0x11110111			@ UART[3210]: MMC[3210]
 	str	r1, [r0, #0x310]
 	/* Set Lock Time */
 	ldr	r1, =0x2cf			@ Locktime : 30us
 	str	r1, [r0, #0x000]		@ S5PC110_APLL_LOCK
 	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
 	str	r1, [r0, #0x008]		@ S5PC110_MPLL_LOCK
 	str	r1, [r0, #0x010]		@ S5PC110_EPLL_LOCK
 	str	r1, [r0, #0x020]		@ S5PC110_VPLL_LOCK
 	/* S5PC110_APLL_CON */
 	ldr	r1, =0x80C80601			@ 800MHz
 	str	r1, [r0, #0x100]
 	/* S5PC110_MPLL_CON */
 	ldr	r1, =0x829B0C01			@ 667MHz
 	str	r1, [r0, #0x108]
 	/* S5PC110_EPLL_CON */
 	ldr	r1, =0x80600602			@  96MHz VSEL 0 P 6 M 96 S 2
 	str	r1, [r0, #0x110]
 	/* S5PC110_VPLL_CON */
 	ldr	r1, =0x806C0603			@  54MHz
 	str	r1, [r0, #0x120]
 	/* Set Source Clock */
 	ldr	r1, =0x10001111			@ A, M, E, VPLL Muxing
 	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
 	/* OneDRAM(DMC0) clock setting */
 	ldr	r1, =0x01000000			@ ONEDRAM_SEL[25:24] 1 SCLKMPLL
 	str	r1, [r0, #0x218]		@ S5PC110_CLK_SRC6
 	ldr	r1, =0x30000000			@ ONEDRAM_RATIO[31:28] 3 + 1
 	str	r1, [r0, #0x318]		@ S5PC110_CLK_DIV6
 	/* XCLKOUT = XUSBXTI 24MHz */
 	add	r2, r0, #0xE000			@ S5PC110_OTHERS
 	ldr     r1, [r2]
 	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
 	str	r1, [r2]
 	/* CLK_IP0 */
 	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
 	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
 	/* CLK_IP1 */
 	ldr	r1, =0xe9fdf0f9			@ FIMD[0] USBOTG[16]
 						@ NANDXL[24]
 	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
 	/* CLK_IP2 */
 	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
 						@ HOSTIF[10] HSMMC0[16]
 						@ HSMMC2[18] VIC[27:24]
 	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
 	/* CLK_IP3 */
 	ldr	r1, =0x8eff038c			@ I2C[8:6]
 						@ SYSTIMER[16] UART0[17]
 						@ UART1[18] UART2[19]
 						@ UART3[20] WDT[22]
 						@ PWM[23] GPIO[26] SYSCON[27]
 	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
 	/* CLK_IP4 */
 	ldr	r1, =0xfffffff1			@ CHIP_ID[0] TZPC[8:5]
 	str	r1, [r0, #0x470]		@ S5PC110_CLK_IP3
 200:
 	/* wait at least 200us to stablize all clock */
 	mov	r2, #0x10000
 1:	subs	r2, r2, #1
 	bne	1b
 	mov	pc, lr
 internal_ram_init:
 	ldreq	r0, =0xE3800000
 	ldrne	r0, =0xF1500000
 	ldr	r1, =0x0
 	str	r1, [r0]
 	mov	pc, lr
 /*
  * uart_asm_init: Initialize UART's pins
  */
 uart_asm_init:
 	/* set GPIO to enable UART0-UART4 */
 	mov	r0, r8
 	ldr	r1, =0x22222222
 	str	r1, [r0, #0x0]			@ S5PC100_GPIO_A0_OFFSET
 	ldr	r1, =0x00002222
 	str	r1, [r0, #0x20]			@ S5PC100_GPIO_A1_OFFSET
 	/* Check S5PC100 */
 	cmp	r7, r8
 	bne	110f
 	/* UART_SEL GPK0[5] at S5PC100 */
 	add	r0, r8, #0x2A0			@ S5PC100_GPIO_K0_OFFSET
 	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
 	bic	r1, r1, #(0xf << 20)		@ 20 = 5 * 4-bit
 	orr	r1, r1, #(0x1 << 20)		@ Output
 	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
 	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
 	bic	r1, r1, #(0x3 << 10)		@ 10 = 5 * 2-bit
 	orr	r1, r1, #(0x2 << 10)		@ Pull-up enabled
 	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
 	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
 	orr	r1, r1, #(1 << 5)		@ 5 = 5 * 1-bit
 	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
 	b	200f
 110:
 	/*
 	 * Note that the following address
 	 * 0xE020'0360 is reserved address at S5PC100
 	 */
 	/* UART_SEL MP0_5[7] at S5PC110 */
 	add	r0, r8, #0x360			@ S5PC110_GPIO_MP0_5_OFFSET
 	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
 	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
 	orr	r1, r1, #(0x1 << 28)		@ Output
 	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
 	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
 	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
 	orr	r1, r1, #(0x2 << 14)		@ Pull-up enabled
 	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
 	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
 	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
 	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
 200:
 	mov	pc, lr

board/samsung/smdk2410/lowlevel_init.S

Diff comments View file @ b60eff3

 /*
  * Memory Setup stuff - taken from blob memsetup.S
  *
  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  *
  * Modified for the Samsung SMDK2410 by
  * (C) Copyright 2002
  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
 #include <version.h>
 /* some parameters for the board */
 /*
  *
  * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
  *
  * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
  *
  */
 #define BWSCON	0x48000000
 /* BWSCON */
 #define DW8			(0x0)
 #define DW16			(0x1)
 #define DW32			(0x2)
 #define WAIT			(0x1<<2)
 #define UBLB			(0x1<<3)
 #define B1_BWSCON		(DW32)
 #define B2_BWSCON		(DW16)
 #define B3_BWSCON		(DW16 + WAIT + UBLB)
 #define B4_BWSCON		(DW16)
 #define B5_BWSCON		(DW16)
 #define B6_BWSCON		(DW32)
 #define B7_BWSCON		(DW32)
 /* BANK0CON */
 #define B0_Tacs			0x0	/*  0clk */
 #define B0_Tcos			0x0	/*  0clk */
 #define B0_Tacc			0x7	/* 14clk */
 #define B0_Tcoh			0x0	/*  0clk */
 #define B0_Tah			0x0	/*  0clk */
 #define B0_Tacp			0x0
 #define B0_PMC			0x0	/* normal */
 /* BANK1CON */
 #define B1_Tacs			0x0	/*  0clk */
 #define B1_Tcos			0x0	/*  0clk */
 #define B1_Tacc			0x7	/* 14clk */
 #define B1_Tcoh			0x0	/*  0clk */
 #define B1_Tah			0x0	/*  0clk */
 #define B1_Tacp			0x0
 #define B1_PMC			0x0
 #define B2_Tacs			0x0
 #define B2_Tcos			0x0
 #define B2_Tacc			0x7
 #define B2_Tcoh			0x0
 #define B2_Tah			0x0
 #define B2_Tacp			0x0
 #define B2_PMC			0x0
 #define B3_Tacs			0x0	/*  0clk */
 #define B3_Tcos			0x3	/*  4clk */
 #define B3_Tacc			0x7	/* 14clk */
 #define B3_Tcoh			0x1	/*  1clk */
 #define B3_Tah			0x0	/*  0clk */
 #define B3_Tacp			0x3     /*  6clk */
 #define B3_PMC			0x0	/* normal */
 #define B4_Tacs			0x0	/*  0clk */
 #define B4_Tcos			0x0	/*  0clk */
 #define B4_Tacc			0x7	/* 14clk */
 #define B4_Tcoh			0x0	/*  0clk */
 #define B4_Tah			0x0	/*  0clk */
 #define B4_Tacp			0x0
 #define B4_PMC			0x0	/* normal */
 #define B5_Tacs			0x0	/*  0clk */
 #define B5_Tcos			0x0	/*  0clk */
 #define B5_Tacc			0x7	/* 14clk */
 #define B5_Tcoh			0x0	/*  0clk */
 #define B5_Tah			0x0	/*  0clk */
 #define B5_Tacp			0x0
 #define B5_PMC			0x0	/* normal */
 #define B6_MT			0x3	/* SDRAM */
 #define B6_Trcd			0x1
 #define B6_SCAN			0x1	/* 9bit */
 #define B7_MT			0x3	/* SDRAM */
 #define B7_Trcd			0x1	/* 3clk */
 #define B7_SCAN			0x1	/* 9bit */
 /* REFRESH parameter */
 #define REFEN			0x1	/* Refresh enable */
 #define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
 #define Trp			0x0	/* 2clk */
 #define Trc			0x3	/* 7clk */
 #define Tchr			0x2	/* 3clk */
 #define REFCNT			1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
 /**************************************/
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
 .globl lowlevel_init
 lowlevel_init:
 	/* memory control configuration */
 	/* make r0 relative the current location so that it */
 	/* reads SMRDATA out of FLASH rather than memory ! */
 	ldr     r0, =SMRDATA
-	ldr	r1, _TEXT_BASE
+	ldr	r1, =CONFIG_SYS_TEXT_BASE
 	sub	r0, r0, r1
 	ldr	r1, =BWSCON	/* Bus Width Status Controller */
 	add     r2, r0, #13*4
 0:
 	ldr     r3, [r0], #4
 	str     r3, [r1], #4
 	cmp     r2, r0
 	bne     0b
 	/* everything is fine now */
 	mov	pc, lr
 	.ltorg
 /* the literal pools origin */
 SMRDATA:
     .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
     .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
     .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
     .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
     .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
     .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
     .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
     .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
     .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
     .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
     .word 0x32
     .word 0x30
     .word 0x30

board/samsung/smdkc100/lowlevel_init.S

Diff comments View file @ b60eff3

 /*
  * Copyright (C) 2009 Samsung Electronics
  * Kyungmin Park <kyungmin.park@samsung.com>
  * Minkyu Kang <mk7.kang@samsung.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
 #include <version.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/power.h>
 /*
  * Register usages:
  *
  * r5 has zero always
  */
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
 	.globl lowlevel_init
 lowlevel_init:
 	mov	r9, lr
 	/* r5 has always zero */
 	mov	r5, #0
 	ldr	r8, =S5PC100_GPIO_BASE
 	/* Disable Watchdog */
 	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
 	orr	r0, r0, #0x0
 	str	r5, [r0]
 	/* setting SRAM */
 	ldr	r0, =S5PC100_SROMC_BASE
 	ldr	r1, =0x9
 	str	r1, [r0]
 	/* S5PC100 has 3 groups of interrupt sources */
 	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
 	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
 	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
 	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
 	mvn	r3, #0x0
 	str	r3, [r0, #0x14]				@INTENCLEAR
 	str	r3, [r1, #0x14]				@INTENCLEAR
 	str	r3, [r2, #0x14]				@INTENCLEAR
 	/* Set all interrupts as IRQ */
 	str	r5, [r0, #0xc]				@INTSELECT
 	str	r5, [r1, #0xc]				@INTSELECT
 	str	r5, [r2, #0xc]				@INTSELECT
 	/* Pending Interrupt Clear */
 	str	r5, [r0, #0xf00]			@INTADDRESS
 	str	r5, [r1, #0xf00]			@INTADDRESS
 	str	r5, [r2, #0xf00]			@INTADDRESS
 	/* for UART */
 	bl uart_asm_init
 	/* for TZPC */
 	bl tzpc_asm_init
 1:
 	mov	lr, r9
 	mov	pc, lr
 /*
  * system_clock_init: Initialize core clock and bus clock.
  * void system_clock_init(void)
  */
 system_clock_init:
 	ldr	r8, =S5PC100_CLOCK_BASE		@ 0xE0100000
 	/* Set Clock divider */
 	ldr	r1, =0x00011110
 	str	r1, [r8, #0x304]
 	ldr	r1, =0x1
 	str	r1, [r8, #0x308]
 	ldr	r1, =0x00011301
 	str	r1, [r8, #0x300]
 	/* Set Lock Time */
 	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
 	str	r1, [r8, #0x000]		@ APLL_LOCK
 	str	r1, [r8, #0x004]		@ MPLL_LOCK
 	str	r1, [r8, #0x008]		@ EPLL_LOCK
 	str	r1, [r8, #0x00C]		@ HPLL_LOCK
 	/* APLL_CON */
 	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
 	str	r1, [r8, #0x100]
 	/* MPLL_CON */
 	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
 	str	r1, [r8, #0x104]
 	/* EPLL_CON */
 	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
 	str	r1, [r8, #0x108]
 	/* HPLL_CON */
 	ldr	r1, =0x80600603
 	str	r1, [r8, #0x10C]
 	/* Set Source Clock */
 	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
 	str	r1, [r8, #0x200]		@ CLK_SRC0
 	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
 	str	r1, [r8, #0x204]		@ CLK_SRC1
 	ldr	r1, =0x9000			@ ARMCLK/4
 	str	r1, [r8, #0x400]		@ CLK_OUT
 	/* wait at least 200us to stablize all clock */
 	mov	r2, #0x10000
 1:	subs	r2, r2, #1
 	bne	1b
 	mov	pc, lr
 /*
  * uart_asm_init: Initialize UART's pins
  */
 uart_asm_init:
 	mov	r0, r8
 	ldr	r1, =0x22222222
 	str	r1, [r0, #0x0]			@ GPA0_CON
 	ldr	r1, =0x00022222
 	str	r1, [r0, #0x20]			@ GPA1_CON
 	mov	pc, lr
 /*
  * tzpc_asm_init: Initialize TZPC
  */
 tzpc_asm_init:
 	ldr	r0, =0xE3800000
 	mov	r1, #0x0
 	str	r1, [r0]
 	mov	r1, #0xff
 	str	r1, [r0, #0x804]
 	str	r1, [r0, #0x810]
 	ldr	r0, =0xE2800000
 	str	r1, [r0, #0x804]
 	str	r1, [r0, #0x810]
 	str	r1, [r0, #0x81C]
 	ldr	r0, =0xE2900000
 	str	r1, [r0, #0x804]
 	str	r1, [r0, #0x810]
 	mov	pc, lr

board/ti/omap5912osk/lowlevel_init.S

Diff comments View file @ b60eff3

 /*
  * Board specific setup info
  *
  * (C) Copyright 2003
  * Texas Instruments, <www.ti.com>
  * Kshitij Gupta <Kshitij@ti.com>
  *
  * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
  *
  * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
 #include <version.h>
 #if defined(CONFIG_OMAP1610)
 #include <./configs/omap1510.h>
 #endif
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
 .globl lowlevel_init
 lowlevel_init:
 	/*------------------------------------------------------*
 	 * Ensure i-cache is enabled                            *
 	 * To configure TC regs without fetching instruction    *
 	 *------------------------------------------------------*/
 	mrc	p15, 0, r0, c1, c0
 	orr	r0, r0, #0x1000
 	mcr	p15, 0, r0, c1, c0
 	/*------------------------------------------------------*
 	 *mask all IRQs by setting all bits in the INTMR default*
 	 *------------------------------------------------------*/
 	mov	r1, #0xffffffff
 	ldr	r0, =REG_IHL1_MIR
 	str	r1, [r0]
 	ldr	r0, =REG_IHL2_MIR
 	str	r1, [r0]
 	/*------------------------------------------------------*
 	 * Set up ARM CLM registers (IDLECT1)                   *
 	 *------------------------------------------------------*/
 	ldr	r0,	REG_ARM_IDLECT1
 	ldr	r1,	VAL_ARM_IDLECT1
 	str	r1,	[r0]
 	/*------------------------------------------------------*
 	 * Set up ARM CLM registers (IDLECT2)                   *
 	 *------------------------------------------------------*/
 	ldr	r0,	REG_ARM_IDLECT2
 	ldr	r1,	VAL_ARM_IDLECT2
 	str	r1,	[r0]
 	/*------------------------------------------------------*
 	 * Set up ARM CLM registers (IDLECT3)                   *
 	 *------------------------------------------------------*/
 	ldr	r0,	REG_ARM_IDLECT3
 	ldr	r1,	VAL_ARM_IDLECT3
 	str	r1,	[r0]
 	mov	r1,	#0x01               /* PER_EN bit */
 	ldr	r0,	REG_ARM_RSTCT2
 	strh	r1,	[r0]            /* CLKM; Peripheral reset. */
 	/* Set CLKM to Sync-Scalable */
 	mov	r1,	#0x1000
 	ldr	r0,	REG_ARM_SYSST
 	mov	r2,	#0
 1:	cmp	r2,	#1
 	streqh	r1,	[r0]
 	add	r2,	r2,	#1
 	cmp	r2,	#0x100              /* wait for any bubbles to finish */
 	bne	1b
 	ldr	r1,	VAL_ARM_CKCTL
 	ldr	r0,	REG_ARM_CKCTL
 	strh	r1,	[r0]
 	/* a few nops to let settle */
 	nop
 	nop
 	nop
 	nop
 	nop
 	nop
 	nop
 	nop
 	nop
 	nop
 	/* setup DPLL 1 */
 	/* Ramp up the clock to 96Mhz */
 	ldr	r1,	VAL_DPLL1_CTL
 	ldr	r0,	REG_DPLL1_CTL
 	strh	r1,	[r0]
 	ands	r1,	r1,	#0x10       /* Check if PLL is enabled. */
 	beq	lock_end                /* Do not look for lock if BYPASS selected */
 2:
 	ldrh	r1,	[r0]
 	ands	r1,	r1,	#0x01       /* Check the LOCK bit.*/
 	beq 2b                      /* loop until bit goes hi. */
 lock_end:
 	/*------------------------------------------------------*
 	 * Turn off the watchdog during init...                 *
 	 *------------------------------------------------------*/
 	ldr	r0,	REG_WATCHDOG
 	ldr	r1,	WATCHDOG_VAL1
 	str	r1,	[r0]
 	ldr	r1,	WATCHDOG_VAL2
 	str	r1,	[r0]
 	ldr	r0,	REG_WSPRDOG
 	ldr	r1,	WSPRDOG_VAL1
 	str	r1,	[r0]
 	ldr	r0,	REG_WWPSDOG
 watch1Wait:
 	ldr	r1,	[r0]
 	tst	r1,	#0x10
 	bne	watch1Wait
 	ldr	r0,	REG_WSPRDOG
 	ldr	r1,	WSPRDOG_VAL2
 	str	r1,	[r0]
 	ldr	r0,	REG_WWPSDOG
 watch2Wait:
 	ldr	r1,	[r0]
 	tst	r1,	#0x10
 	bne	watch2Wait
 	/* Set memory timings corresponding to the new clock speed */
 	ldr	r3, VAL_SDRAM_CONFIG_SDF0
 	/* Check execution location to determine current execution location
 	 * and branch to appropriate initialization code.
 	 */
 	mov	r0,	#0x10000000         /* Load physical SDRAM base. */
 	mov	r1,	pc                  /* Get current execution location. */
 	cmp	r1,	r0                  /* Compare. */
 	bge	skip_sdram              /* Skip over EMIF-fast initialization if running from SDRAM. */
 	/* identify the device revision, -- TMX or TMP(TMS) */
 	ldr	r0, REG_DEVICE_ID
 	ldr	r1, [r0]
 	ldr	r0, VAL_DEVICE_ID_TMP
 	mov	r1, r1, lsl #15
 	mov	r1, r1, lsr #16
 	cmp	r0, r1
 	bne	skip_TMP_Patch
 	/* Enable TMP/TMS device new features */
 	mov	r0, #1
 	ldr	r1, REG_TC_EMIFF_DOUBLER
 	str	r0, [r1]
 	/* Enable new ac parameters */
 	mov	r0, #0x0b
 	ldr	r1, REG_SDRAM_CONFIG2
 	str	r0, [r1]
 	ldr	r3, VAL_SDRAM_CONFIG_SDF1
 skip_TMP_Patch:
 	/*
 	* Delay for SDRAM initialization.
 	*/
 	mov	r0,	#0x1800		/* value should be checked */
 3:
 	subs	r0,	r0,	#0x1	/* Decrement count */
 	bne	3b
 	/*
 	 * Set SDRAM control values. Disable refresh before MRS command.
 	 */
 	/* mobile ddr operation */
 	ldr	r0,	REG_SDRAM_OPERATION
 	mov	r2,	#07
 	str	r2,	[r0]
 	/* config register */
 	ldr	r0,	REG_SDRAM_CONFIG
 	str	r3,	[r0]
 	/* manual command register */
 	ldr	r0,	REG_SDRAM_MANUAL_CMD
 	/* issue set cke high */
 	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
 	str	r1,	[r0]
 	/* issue nop */
 	mov	r1,	#CMD_SDRAM_NOP
 	str	r1,	[r0]
 	mov	r2,	#0x0100
 waitMDDR1:
 	subs	r2,	r2,	 #1
 	bne	waitMDDR1	/* delay loop */
 	/* issue precharge */
 	mov	r1,	#CMD_SDRAM_PRECHARGE
 	str	r1,	[r0]
 	/* issue autorefresh x 2 */
 	mov	r1,	#CMD_SDRAM_AUTOREFRESH
 	str	r1,	[r0]
 	str	r1,	[r0]
 	/* mrs register ddr mobile */
 	ldr	r0,	REG_SDRAM_MRS
 	mov	r1,	#0x33
 	str	r1,	[r0]
 	/* emrs1 low-power register */
 	ldr	r0,	REG_SDRAM_EMRS1
 	/* self refresh on all banks */
 	mov	r1,	#0
 	str	r1,	[r0]
 	ldr	r0,	REG_DLL_URD_CONTROL
 	ldr	r1,	DLL_URD_CONTROL_VAL
 	str	r1,	[r0]
 	ldr	r0,	REG_DLL_LRD_CONTROL
 	ldr	r1,	DLL_LRD_CONTROL_VAL
 	str	r1,	[r0]
 	ldr	r0,	REG_DLL_WRT_CONTROL
 	ldr	r1,	DLL_WRT_CONTROL_VAL
 	str	r1,	[r0]
 	/* delay loop */
 	mov	r0,	#0x0100
 waitMDDR2:
 	subs	r0,	r0,	#1
 	bne	waitMDDR2
 	/*
 	 * Delay for SDRAM initialization.
 	 */
 	mov	r0,	#0x1800
 4:
 	subs	r0,	r0,	#1	/* Decrement count. */
 	bne	4b
 	b	common_tc
 skip_sdram:
 	ldr	r0,	REG_SDRAM_CONFIG
 	str	r3,	[r0]
 common_tc:
 	/* slow interface */
 	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
 	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
 	str	r1,	[r0] /* Chip Select 0 */
 	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
 	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
 	str	r1,	[r0] /* Chip Select 1 */
 	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
 	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
 	str	r1,	[r0] /* Chip Select 3 */
 	ldr	r1,	VAL_TC_EMIFS_DWS
 	ldr	r0,	REG_TC_EMIFS_DWS
 	str	r1,	[r0] /* Enable EMIFS.RDY for CS1 (ether) */
 #ifdef CONFIG_H2_OMAP1610
 	/* inserting additional 2 clock cycle hold time for LAN */
 	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
 	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
 	str     r1,     [r0]
 #endif
 	/* Start MPU Timer 1 */
 	ldr	r0,	REG_MPU_LOAD_TIMER
 	ldr	r1,	VAL_MPU_LOAD_TIMER
 	str	r1,	[r0]
 	ldr	r0,	REG_MPU_CNTL_TIMER
 	ldr	r1,	VAL_MPU_CNTL_TIMER
 	str	r1,	[r0]
 	/*
 	 * Setup a temporary stack
 	 */
 	ldr	sp,	SRAM_STACK
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 	/*
 	 * Save the old lr(passed in ip) and the current lr to stack
 	 */
 	push	{ip, lr}
 	/*
 	 * go setup pll, mux, memory
 	 */
 	bl	s_init
 	pop	{ip, pc}
 	/* back to arch calling code */
 	mov	pc,	lr
 	/* the literal pools origin */
 	.ltorg
 REG_DEVICE_ID:			/* 32 bits */
 	.word 0xfffe2004
 REG_TC_EMIFS_CONFIG:
 	.word 0xfffecc0c
 REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
 	.word 0xfffecc10
 REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
 	.word 0xfffecc14
 REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
 	.word 0xfffecc18
 REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
 	.word 0xfffecc1c
 REG_TC_EMIFS_DWS:		/* 32 bits */
 	.word 0xfffecc40
 #ifdef CONFIG_H2_OMAP1610
 REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
 	.word 0xfffecc54
 #endif
 /* MPU clock/reset/power mode control registers */
 REG_ARM_CKCTL:			/* 16 bits */
 	.word 0xfffece00
 REG_ARM_IDLECT3:		/* 16 bits */
 	.word 0xfffece24
 REG_ARM_IDLECT2:		/* 16 bits */
 	.word 0xfffece08
 REG_ARM_IDLECT1:		/* 16 bits */
 	.word 0xfffece04
 REG_ARM_RSTCT2:			/* 16 bits */
 	.word 0xfffece14
 REG_ARM_SYSST:			/* 16 bits */
 	.word 0xfffece18
 /* DPLL control registers */
 REG_DPLL1_CTL:			/* 16 bits */
 	.word 0xfffecf00
 /* Watch Dog register */
 /* secure watchdog stop */
 REG_WSPRDOG:
 	.word 0xfffeb048
 /* watchdog write pending */
 REG_WWPSDOG:
 	.word 0xfffeb034
 WSPRDOG_VAL1:
 	.word 0x0000aaaa
 WSPRDOG_VAL2:
 	.word 0x00005555
 /* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
  counter @8192 rows, 10 ns, 8 burst */
 REG_SDRAM_CONFIG:
 	.word 0xfffecc20
 REG_SDRAM_CONFIG2:
 	.word 0xfffecc3c
 REG_TC_EMIFF_DOUBLER:		/* 32 bits */
 	.word 0xfffecc60
 /* Operation register */
 REG_SDRAM_OPERATION:
 	.word 0xfffecc80
 /* Manual command register */
 REG_SDRAM_MANUAL_CMD:
 	.word 0xfffecc84
 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
 REG_SDRAM_MRS:
 	.word 0xfffecc70
 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
 REG_SDRAM_EMRS1:
 	.word 0xfffecc78
 /* WRT DLL register */
 REG_DLL_WRT_CONTROL:
 	.word 0xfffecc68
 DLL_WRT_CONTROL_VAL:
 	.word 0x03f00002    /* Phase of 72deg, write offset +31  */
 /* URD DLL register */
 REG_DLL_URD_CONTROL:
 	.word 0xfffeccc0
 DLL_URD_CONTROL_VAL:
 	.word 0x00800002    /* Phase of 72deg, read offset +31  */
 /* LRD DLL register */
 REG_DLL_LRD_CONTROL:
 	.word 0xfffecccc
 DLL_LRD_CONTROL_VAL:
 	.word 0x00800002    /* read offset +31  */
 REG_WATCHDOG:
 	.word 0xfffec808
 WATCHDOG_VAL1:
 	.word 0x000000f5
 WATCHDOG_VAL2:
 	.word 0x000000a0
 REG_MPU_LOAD_TIMER:
 	.word 0xfffec504
 REG_MPU_CNTL_TIMER:
 	.word 0xfffec500
 VAL_MPU_LOAD_TIMER:
 	.word 0xffffffff
 VAL_MPU_CNTL_TIMER:
 	.word 0xffffffa1
 /* 96 MHz Samsung Mobile DDR */
 /* Original setting for TMX device */
 VAL_SDRAM_CONFIG_SDF0:
     .word 0x0014e6fe
 /* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
 VAL_SDRAM_CONFIG_SDF1:
     .word 0x0114e6fe
 VAL_ARM_CKCTL:
 	.word 0x2000		/* was:	0x3000, now use CLK_REF for timer input */
 VAL_DPLL1_CTL:
 	.word 0x2830
 #ifdef CONFIG_OSK_OMAP5912
 VAL_TC_EMIFS_CS0_CONFIG:
 	.word 0x002130b0
 VAL_TC_EMIFS_CS1_CONFIG:
 	.word 0x00001133
 VAL_TC_EMIFS_CS2_CONFIG:
 	.word 0x000055f0
 VAL_TC_EMIFS_CS3_CONFIG:
 	.word 0x88013141
 VAL_TC_EMIFS_DWS:	/* Enable EMIFS.RDY for CS1 access (ether) */
 	.word 0x000000c0
 VAL_DEVICE_ID_TMP:	/* TMP/TMS=0xb65f, TMX=0xb58c */
 	.word 0xb65f
 #endif
 #ifdef CONFIG_H2_OMAP1610
 VAL_TC_EMIFS_CS0_CONFIG:
 	.word 0x00203331
 VAL_TC_EMIFS_CS1_CONFIG:
 	.word 0x8180fff3
 VAL_TC_EMIFS_CS2_CONFIG:
 	.word 0xf800f22a
 VAL_TC_EMIFS_CS3_CONFIG:
 	.word 0x88013141
 VAL_TC_EMIFS_CS1_ADVANCED:
 	.word 0x00000022
 #endif
 VAL_ARM_IDLECT1:
 	.word 0x00000400
 VAL_ARM_IDLECT2:
 	.word 0x00000886
 VAL_ARM_IDLECT3:
 	.word 0x00000015
 SRAM_STACK:
 	.word CONFIG_SYS_INIT_SP_ADDR
 /* command values */
 .equ CMD_SDRAM_NOP,             0x00000000
 .equ CMD_SDRAM_PRECHARGE,       0x00000001
 .equ CMD_SDRAM_AUTOREFRESH,     0x00000002
 .equ CMD_SDRAM_CKE_SET_HIGH,    0x00000007

common/board_f.c

Diff comments View file @ b60eff3

1	/*	1	/*
2	* Copyright (c) 2011 The Chromium OS Authors.	2	* Copyright (c) 2011 The Chromium OS Authors.
3	* (C) Copyright 2002-2006	3	* (C) Copyright 2002-2006
4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5	*	5	*
6	* (C) Copyright 2002	6	* (C) Copyright 2002
7	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>	7	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8	* Marius Groeger <mgroeger@sysgo.de>	8	* Marius Groeger <mgroeger@sysgo.de>
9	*	9	*
10	* SPDX-License-Identifier: GPL-2.0+	10	* SPDX-License-Identifier: GPL-2.0+
11	*/	11	*/
12		12
13	#include <common.h>	13	#include <common.h>
14	#include <linux/compiler.h>	14	#include <linux/compiler.h>
15	#include <version.h>	15	#include <version.h>
16	#include <environment.h>	16	#include <environment.h>
17	#include <fdtdec.h>	17	#include <fdtdec.h>
18	#include <fs.h>	18	#include <fs.h>
19	#if defined(CONFIG_CMD_IDE)	19	#if defined(CONFIG_CMD_IDE)
20	#include <ide.h>	20	#include <ide.h>
21	#endif	21	#endif
22	#include <i2c.h>	22	#include <i2c.h>
23	#include <initcall.h>	23	#include <initcall.h>
24	#include <logbuff.h>	24	#include <logbuff.h>
25		25
26	/* TODO: Can we move these into arch/ headers? */	26	/* TODO: Can we move these into arch/ headers? */
27	#ifdef CONFIG_8xx	27	#ifdef CONFIG_8xx
28	#include <mpc8xx.h>	28	#include <mpc8xx.h>
29	#endif	29	#endif
30	#ifdef CONFIG_5xx	30	#ifdef CONFIG_5xx
31	#include <mpc5xx.h>	31	#include <mpc5xx.h>
32	#endif	32	#endif
33	#ifdef CONFIG_MPC5xxx	33	#ifdef CONFIG_MPC5xxx
34	#include <mpc5xxx.h>	34	#include <mpc5xxx.h>
35	#endif	35	#endif
36		36
37	#include <os.h>	37	#include <os.h>
38	#include <post.h>	38	#include <post.h>
39	#include <spi.h>	39	#include <spi.h>
40	#include <trace.h>	40	#include <trace.h>
41	#include <watchdog.h>	41	#include <watchdog.h>
42	#include <asm/errno.h>	42	#include <asm/errno.h>
43	#include <asm/io.h>	43	#include <asm/io.h>
44	#ifdef CONFIG_MP	44	#ifdef CONFIG_MP
45	#include <asm/mp.h>	45	#include <asm/mp.h>
46	#endif	46	#endif
47	#include <asm/sections.h>	47	#include <asm/sections.h>
48	#ifdef CONFIG_X86	48	#ifdef CONFIG_X86
49	#include <asm/init_helpers.h>	49	#include <asm/init_helpers.h>
50	#include <asm/relocate.h>	50	#include <asm/relocate.h>
51	#endif	51	#endif
52	#ifdef CONFIG_SANDBOX	52	#ifdef CONFIG_SANDBOX
53	#include <asm/state.h>	53	#include <asm/state.h>
54	#endif	54	#endif
55	#include <linux/compiler.h>	55	#include <linux/compiler.h>
56		56
57	/*	57	/*
58	* Pointer to initial global data area	58	* Pointer to initial global data area
59	*	59	*
60	* Here we initialize it if needed.	60	* Here we initialize it if needed.
61	*/	61	*/
62	#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR	62	#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
63	#undef XTRN_DECLARE_GLOBAL_DATA_PTR	63	#undef XTRN_DECLARE_GLOBAL_DATA_PTR
64	#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */	64	#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
65	DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);	65	DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
66	#else	66	#else
67	DECLARE_GLOBAL_DATA_PTR;	67	DECLARE_GLOBAL_DATA_PTR;
68	#endif	68	#endif
69		69
70	/*	70	/*
71	* sjg: IMO this code should be	71	* sjg: IMO this code should be
72	* refactored to a single function, something like:	72	* refactored to a single function, something like:
73	*	73	*
74	* void led_set_state(enum led_colour_t colour, int on);	74	* void led_set_state(enum led_colour_t colour, int on);
75	*/	75	*/
76	/************************************************************************	76	/************************************************************************
77	* Coloured LED functionality	77	* Coloured LED functionality
78	************************************************************************	78	************************************************************************
79	* May be supplied by boards if desired	79	* May be supplied by boards if desired
80	*/	80	*/
81	inline void __coloured_LED_init(void) {}	81	inline void __coloured_LED_init(void) {}
82	void coloured_LED_init(void)	82	void coloured_LED_init(void)
83	__attribute__((weak, alias("__coloured_LED_init")));	83	__attribute__((weak, alias("__coloured_LED_init")));
84	inline void __red_led_on(void) {}	84	inline void __red_led_on(void) {}
85	void red_led_on(void) __attribute__((weak, alias("__red_led_on")));	85	void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
86	inline void __red_led_off(void) {}	86	inline void __red_led_off(void) {}
87	void red_led_off(void) __attribute__((weak, alias("__red_led_off")));	87	void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
88	inline void __green_led_on(void) {}	88	inline void __green_led_on(void) {}
89	void green_led_on(void) __attribute__((weak, alias("__green_led_on")));	89	void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
90	inline void __green_led_off(void) {}	90	inline void __green_led_off(void) {}
91	void green_led_off(void) __attribute__((weak, alias("__green_led_off")));	91	void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
92	inline void __yellow_led_on(void) {}	92	inline void __yellow_led_on(void) {}
93	void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));	93	void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
94	inline void __yellow_led_off(void) {}	94	inline void __yellow_led_off(void) {}
95	void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));	95	void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
96	inline void __blue_led_on(void) {}	96	inline void __blue_led_on(void) {}
97	void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));	97	void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
98	inline void __blue_led_off(void) {}	98	inline void __blue_led_off(void) {}
99	void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));	99	void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
100		100
101	/*	101	/*
102	* Why is gd allocated a register? Prior to reloc it might be better to	102	* Why is gd allocated a register? Prior to reloc it might be better to
103	* just pass it around to each function in this file?	103	* just pass it around to each function in this file?
104	*	104	*
105	* After reloc one could argue that it is hardly used and doesn't need	105	* After reloc one could argue that it is hardly used and doesn't need
106	* to be in a register. Or if it is it should perhaps hold pointers to all	106	* to be in a register. Or if it is it should perhaps hold pointers to all
107	* global data for all modules, so that post-reloc we can avoid the massive	107	* global data for all modules, so that post-reloc we can avoid the massive
108	* literal pool we get on ARM. Or perhaps just encourage each module to use	108	* literal pool we get on ARM. Or perhaps just encourage each module to use
109	* a structure...	109	* a structure...
110	*/	110	*/
111		111
112	/*	112	/*
113	* Could the CONFIG_SPL_BUILD infection become a flag in gd?	113	* Could the CONFIG_SPL_BUILD infection become a flag in gd?
114	*/	114	*/
115		115
116	#if defined(CONFIG_WATCHDOG)	116	#if defined(CONFIG_WATCHDOG)
117	static int init_func_watchdog_init(void)	117	static int init_func_watchdog_init(void)
118	{	118	{
119	puts(" Watchdog enabled\n");	119	puts(" Watchdog enabled\n");
120	WATCHDOG_RESET();	120	WATCHDOG_RESET();
121		121
122	return 0;	122	return 0;
123	}	123	}
124		124
125	int init_func_watchdog_reset(void)	125	int init_func_watchdog_reset(void)
126	{	126	{
127	WATCHDOG_RESET();	127	WATCHDOG_RESET();
128		128
129	return 0;	129	return 0;
130	}	130	}
131	#endif /* CONFIG_WATCHDOG */	131	#endif /* CONFIG_WATCHDOG */
132		132
133	void __board_add_ram_info(int use_default)	133	void __board_add_ram_info(int use_default)
134	{	134	{
135	/* please define platform specific board_add_ram_info() */	135	/* please define platform specific board_add_ram_info() */
136	}	136	}
137		137
138	void board_add_ram_info(int)	138	void board_add_ram_info(int)
139	__attribute__ ((weak, alias("__board_add_ram_info")));	139	__attribute__ ((weak, alias("__board_add_ram_info")));
140		140
141	static int init_baud_rate(void)	141	static int init_baud_rate(void)
142	{	142	{
143	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);	143	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
144	return 0;	144	return 0;
145	}	145	}
146		146
147	static int display_text_info(void)	147	static int display_text_info(void)
148	{	148	{
149	#ifndef CONFIG_SANDBOX	149	#ifndef CONFIG_SANDBOX
150	ulong bss_start, bss_end;	150	ulong bss_start, bss_end;
151		151
152	#ifdef CONFIG_SYS_SYM_OFFSETS
153	bss_start = _bss_start_ofs + _TEXT_BASE;
154	bss_end = _bss_end_ofs + _TEXT_BASE;
155	#else
156	bss_start = (ulong)&__bss_start;	152	bss_start = (ulong)&__bss_start;
157	bss_end = (ulong)&__bss_end;	153	bss_end = (ulong)&__bss_end;
158	#endif	154
159	debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n",	155	debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n",
160	CONFIG_SYS_TEXT_BASE, bss_start, bss_end);	156	CONFIG_SYS_TEXT_BASE, bss_start, bss_end);
161	#endif	157	#endif
162		158
163	#ifdef CONFIG_MODEM_SUPPORT	159	#ifdef CONFIG_MODEM_SUPPORT
164	debug("Modem Support enabled\n");	160	debug("Modem Support enabled\n");
165	#endif	161	#endif
166	#ifdef CONFIG_USE_IRQ	162	#ifdef CONFIG_USE_IRQ
167	debug("IRQ Stack: %08lx\n", IRQ_STACK_START);	163	debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
168	debug("FIQ Stack: %08lx\n", FIQ_STACK_START);	164	debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
169	#endif	165	#endif
170		166
171	return 0;	167	return 0;
172	}	168	}
173		169
174	static int announce_dram_init(void)	170	static int announce_dram_init(void)
175	{	171	{
176	puts("DRAM: ");	172	puts("DRAM: ");
177	return 0;	173	return 0;
178	}	174	}
179		175
180	#ifdef CONFIG_PPC	176	#ifdef CONFIG_PPC
181	static int init_func_ram(void)	177	static int init_func_ram(void)
182	{	178	{
183	#ifdef CONFIG_BOARD_TYPES	179	#ifdef CONFIG_BOARD_TYPES
184	int board_type = gd->board_type;	180	int board_type = gd->board_type;
185	#else	181	#else
186	int board_type = 0; /* use dummy arg */	182	int board_type = 0; /* use dummy arg */
187	#endif	183	#endif
188		184
189	gd->ram_size = initdram(board_type);	185	gd->ram_size = initdram(board_type);
190		186
191	if (gd->ram_size > 0)	187	if (gd->ram_size > 0)
192	return 0;	188	return 0;
193		189
194	puts("* failed *\n");	190	puts("* failed *\n");
195	return 1;	191	return 1;
196	}	192	}
197	#endif	193	#endif
198		194
199	static int show_dram_config(void)	195	static int show_dram_config(void)
200	{	196	{
201	ulong size;	197	ulong size;
202		198
203	#ifdef CONFIG_NR_DRAM_BANKS	199	#ifdef CONFIG_NR_DRAM_BANKS
204	int i;	200	int i;
205		201
206	debug("\nRAM Configuration:\n");	202	debug("\nRAM Configuration:\n");
207	for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {	203	for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
208	size += gd->bd->bi_dram[i].size;	204	size += gd->bd->bi_dram[i].size;
209	debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);	205	debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
210	#ifdef DEBUG	206	#ifdef DEBUG
211	print_size(gd->bd->bi_dram[i].size, "\n");	207	print_size(gd->bd->bi_dram[i].size, "\n");
212	#endif	208	#endif
213	}	209	}
214	debug("\nDRAM: ");	210	debug("\nDRAM: ");
215	#else	211	#else
216	size = gd->ram_size;	212	size = gd->ram_size;
217	#endif	213	#endif
218		214
219	print_size(size, "");	215	print_size(size, "");
220	board_add_ram_info(0);	216	board_add_ram_info(0);
221	putc('\n');	217	putc('\n');
222		218
223	return 0;	219	return 0;
224	}	220	}
225		221
226	ulong get_effective_memsize(void)	222	ulong get_effective_memsize(void)
227	{	223	{
228	#ifndef CONFIG_VERY_BIG_RAM	224	#ifndef CONFIG_VERY_BIG_RAM
229	return gd->ram_size;	225	return gd->ram_size;
230	#else	226	#else
231	/* limit stack to what we can reasonable map */	227	/* limit stack to what we can reasonable map */
232	return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?	228	return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
233	CONFIG_MAX_MEM_MAPPED : gd->ram_size);	229	CONFIG_MAX_MEM_MAPPED : gd->ram_size);
234	#endif	230	#endif
235	}	231	}
236		232
237	void __dram_init_banksize(void)	233	void __dram_init_banksize(void)
238	{	234	{
239	#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)	235	#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
240	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;	236	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
241	gd->bd->bi_dram[0].size = get_effective_memsize();	237	gd->bd->bi_dram[0].size = get_effective_memsize();
242	#endif	238	#endif
243	}	239	}
244		240
245	void dram_init_banksize(void)	241	void dram_init_banksize(void)
246	__attribute__((weak, alias("__dram_init_banksize")));	242	__attribute__((weak, alias("__dram_init_banksize")));
247		243
248	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SYS_I2C)	244	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SYS_I2C)
249	static int init_func_i2c(void)	245	static int init_func_i2c(void)
250	{	246	{
251	puts("I2C: ");	247	puts("I2C: ");
252	#ifdef CONFIG_SYS_I2C	248	#ifdef CONFIG_SYS_I2C
253	i2c_init_all();	249	i2c_init_all();
254	#else	250	#else
255	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);	251	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
256	#endif	252	#endif
257	puts("ready\n");	253	puts("ready\n");
258	return 0;	254	return 0;
259	}	255	}
260	#endif	256	#endif
261		257
262	#if defined(CONFIG_HARD_SPI)	258	#if defined(CONFIG_HARD_SPI)
263	static int init_func_spi(void)	259	static int init_func_spi(void)
264	{	260	{
265	puts("SPI: ");	261	puts("SPI: ");
266	spi_init();	262	spi_init();
267	puts("ready\n");	263	puts("ready\n");
268	return 0;	264	return 0;
269	}	265	}
270	#endif	266	#endif
271		267
272	__maybe_unused	268	__maybe_unused
273	static int zero_global_data(void)	269	static int zero_global_data(void)
274	{	270	{
275	memset((void *)gd, '\0', sizeof(gd_t));	271	memset((void *)gd, '\0', sizeof(gd_t));
276		272
277	return 0;	273	return 0;
278	}	274	}
279		275
280	static int setup_mon_len(void)	276	static int setup_mon_len(void)
281	{	277	{
282	#ifdef CONFIG_SYS_SYM_OFFSETS	278	#ifdef __ARM__
283	gd->mon_len = _bss_end_ofs;	279	gd->mon_len = (ulong)&__bss_end - (ulong)_start;
284	#elif defined(CONFIG_SANDBOX)	280	#elif defined(CONFIG_SANDBOX)
285	gd->mon_len = (ulong)&_end - (ulong)_init;	281	gd->mon_len = (ulong)&_end - (ulong)_init;
286	#else	282	#else
287	/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */	283	/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
288	gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;	284	gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
289	#endif	285	#endif
290	return 0;	286	return 0;
291	}	287	}
292		288
293	__weak int arch_cpu_init(void)	289	__weak int arch_cpu_init(void)
294	{	290	{
295	return 0;	291	return 0;
296	}	292	}
297		293
298	#ifdef CONFIG_OF_HOSTFILE	294	#ifdef CONFIG_OF_HOSTFILE
299		295
300	#define CHECK(x) err = (x); if (err) goto failed;	296	#define CHECK(x) err = (x); if (err) goto failed;
301		297
302	/* Create an empty device tree blob */	298	/* Create an empty device tree blob */
303	static int make_empty_fdt(void *fdt)	299	static int make_empty_fdt(void *fdt)
304	{	300	{
305	int err;	301	int err;
306		302
307	CHECK(fdt_create(fdt, 256));	303	CHECK(fdt_create(fdt, 256));
308	CHECK(fdt_finish_reservemap(fdt));	304	CHECK(fdt_finish_reservemap(fdt));
309	CHECK(fdt_begin_node(fdt, ""));	305	CHECK(fdt_begin_node(fdt, ""));
310	CHECK(fdt_end_node(fdt));	306	CHECK(fdt_end_node(fdt));
311	CHECK(fdt_finish(fdt));	307	CHECK(fdt_finish(fdt));
312		308
313	return 0;	309	return 0;
314	failed:	310	failed:
315	printf("Unable to create empty FDT: %s\n", fdt_strerror(err));	311	printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
316	return -EACCES;	312	return -EACCES;
317	}	313	}
318		314
319	static int read_fdt_from_file(void)	315	static int read_fdt_from_file(void)
320	{	316	{
321	struct sandbox_state *state = state_get_current();	317	struct sandbox_state *state = state_get_current();
322	void *blob;	318	void *blob;
323	int size;	319	int size;
324	int err;	320	int err;
325		321
326	blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);	322	blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
327	if (!state->fdt_fname) {	323	if (!state->fdt_fname) {
328	err = make_empty_fdt(blob);	324	err = make_empty_fdt(blob);
329	if (!err)	325	if (!err)
330	goto done;	326	goto done;
331	return err;	327	return err;
332	}	328	}
333	err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX);	329	err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX);
334	if (err)	330	if (err)
335	return err;	331	return err;
336	size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0);	332	size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0);
337	if (size < 0)	333	if (size < 0)
338	return -EIO;	334	return -EIO;
339		335
340	done:	336	done:
341	gd->fdt_blob = blob;	337	gd->fdt_blob = blob;
342		338
343	return 0;	339	return 0;
344	}	340	}
345	#endif	341	#endif
346		342
347	#ifdef CONFIG_SANDBOX	343	#ifdef CONFIG_SANDBOX
348	static int setup_ram_buf(void)	344	static int setup_ram_buf(void)
349	{	345	{
350	struct sandbox_state *state = state_get_current();	346	struct sandbox_state *state = state_get_current();
351		347
352	gd->arch.ram_buf = state->ram_buf;	348	gd->arch.ram_buf = state->ram_buf;
353	gd->ram_size = state->ram_size;	349	gd->ram_size = state->ram_size;
354		350
355	return 0;	351	return 0;
356	}	352	}
357	#endif	353	#endif
358		354
359	static int setup_fdt(void)	355	static int setup_fdt(void)
360	{	356	{
361	#ifdef CONFIG_OF_EMBED	357	#ifdef CONFIG_OF_EMBED
362	/* Get a pointer to the FDT */	358	/* Get a pointer to the FDT */
363	gd->fdt_blob = __dtb_dt_begin;	359	gd->fdt_blob = __dtb_dt_begin;
364	#elif defined CONFIG_OF_SEPARATE	360	#elif defined CONFIG_OF_SEPARATE
365	/* FDT is at end of image */	361	/* FDT is at end of image */
366	# ifdef CONFIG_SYS_SYM_OFFSETS
367	gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE);
368	# else
369	gd->fdt_blob = (ulong *)&_end;	362	gd->fdt_blob = (ulong *)&_end;
370	# endif
371	#elif defined(CONFIG_OF_HOSTFILE)	363	#elif defined(CONFIG_OF_HOSTFILE)
372	if (read_fdt_from_file()) {	364	if (read_fdt_from_file()) {
373	puts("Failed to read control FDT\n");	365	puts("Failed to read control FDT\n");
374	return -1;	366	return -1;
375	}	367	}
376	#endif	368	#endif
377	/* Allow the early environment to override the fdt address */	369	/* Allow the early environment to override the fdt address */
378	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,	370	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
379	(uintptr_t)gd->fdt_blob);	371	(uintptr_t)gd->fdt_blob);
380	return 0;	372	return 0;
381	}	373	}
382		374
383	/* Get the top of usable RAM */	375	/* Get the top of usable RAM */
384	__weak ulong board_get_usable_ram_top(ulong total_size)	376	__weak ulong board_get_usable_ram_top(ulong total_size)
385	{	377	{
386	return gd->ram_top;	378	return gd->ram_top;
387	}	379	}
388		380
389	static int setup_dest_addr(void)	381	static int setup_dest_addr(void)
390	{	382	{
391	debug("Monitor len: %08lX\n", gd->mon_len);	383	debug("Monitor len: %08lX\n", gd->mon_len);
392	/*	384	/*
393	* Ram is setup, size stored in gd !!	385	* Ram is setup, size stored in gd !!
394	*/	386	*/
395	debug("Ram size: %08lX\n", (ulong)gd->ram_size);	387	debug("Ram size: %08lX\n", (ulong)gd->ram_size);
396	#if defined(CONFIG_SYS_MEM_TOP_HIDE)	388	#if defined(CONFIG_SYS_MEM_TOP_HIDE)
397	/*	389	/*
398	* Subtract specified amount of memory to hide so that it won't	390	* Subtract specified amount of memory to hide so that it won't
399	* get "touched" at all by U-Boot. By fixing up gd->ram_size	391	* get "touched" at all by U-Boot. By fixing up gd->ram_size
400	* the Linux kernel should now get passed the now "corrected"	392	* the Linux kernel should now get passed the now "corrected"
401	* memory size and won't touch it either. This should work	393	* memory size and won't touch it either. This should work
402	* for arch/ppc and arch/powerpc. Only Linux board ports in	394	* for arch/ppc and arch/powerpc. Only Linux board ports in
403	* arch/powerpc with bootwrapper support, that recalculate the	395	* arch/powerpc with bootwrapper support, that recalculate the
404	* memory size from the SDRAM controller setup will have to	396	* memory size from the SDRAM controller setup will have to
405	* get fixed.	397	* get fixed.
406	*/	398	*/
407	gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;	399	gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
408	#endif	400	#endif
409	#ifdef CONFIG_SYS_SDRAM_BASE	401	#ifdef CONFIG_SYS_SDRAM_BASE
410	gd->ram_top = CONFIG_SYS_SDRAM_BASE;	402	gd->ram_top = CONFIG_SYS_SDRAM_BASE;
411	#endif	403	#endif
412	gd->ram_top += get_effective_memsize();	404	gd->ram_top += get_effective_memsize();
413	gd->ram_top = board_get_usable_ram_top(gd->mon_len);	405	gd->ram_top = board_get_usable_ram_top(gd->mon_len);
414	gd->relocaddr = gd->ram_top;	406	gd->relocaddr = gd->ram_top;
415	debug("Ram top: %08lX\n", (ulong)gd->ram_top);	407	debug("Ram top: %08lX\n", (ulong)gd->ram_top);
416	#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) \|\| defined(CONFIG_E500))	408	#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) \|\| defined(CONFIG_E500))
417	/*	409	/*
418	* We need to make sure the location we intend to put secondary core	410	* We need to make sure the location we intend to put secondary core
419	* boot code is reserved and not used by any part of u-boot	411	* boot code is reserved and not used by any part of u-boot
420	*/	412	*/
421	if (gd->relocaddr > determine_mp_bootpg(NULL)) {	413	if (gd->relocaddr > determine_mp_bootpg(NULL)) {
422	gd->relocaddr = determine_mp_bootpg(NULL);	414	gd->relocaddr = determine_mp_bootpg(NULL);
423	debug("Reserving MP boot page to %08lx\n", gd->relocaddr);	415	debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
424	}	416	}
425	#endif	417	#endif
426	return 0;	418	return 0;
427	}	419	}
428		420
429	#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)	421	#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
430	static int reserve_logbuffer(void)	422	static int reserve_logbuffer(void)
431	{	423	{
432	/* reserve kernel log buffer */	424	/* reserve kernel log buffer */
433	gd->relocaddr -= LOGBUFF_RESERVE;	425	gd->relocaddr -= LOGBUFF_RESERVE;
434	debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,	426	debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
435	gd->relocaddr);	427	gd->relocaddr);
436	return 0;	428	return 0;
437	}	429	}
438	#endif	430	#endif
439		431
440	#ifdef CONFIG_PRAM	432	#ifdef CONFIG_PRAM
441	/* reserve protected RAM */	433	/* reserve protected RAM */
442	static int reserve_pram(void)	434	static int reserve_pram(void)
443	{	435	{
444	ulong reg;	436	ulong reg;
445		437
446	reg = getenv_ulong("pram", 10, CONFIG_PRAM);	438	reg = getenv_ulong("pram", 10, CONFIG_PRAM);
447	gd->relocaddr -= (reg << 10); /* size is in kB */	439	gd->relocaddr -= (reg << 10); /* size is in kB */
448	debug("Reserving %ldk for protected RAM at %08lx\n", reg,	440	debug("Reserving %ldk for protected RAM at %08lx\n", reg,
449	gd->relocaddr);	441	gd->relocaddr);
450	return 0;	442	return 0;
451	}	443	}
452	#endif /* CONFIG_PRAM */	444	#endif /* CONFIG_PRAM */
453		445
454	/* Round memory pointer down to next 4 kB limit */	446	/* Round memory pointer down to next 4 kB limit */
455	static int reserve_round_4k(void)	447	static int reserve_round_4k(void)
456	{	448	{
457	gd->relocaddr &= ~(4096 - 1);	449	gd->relocaddr &= ~(4096 - 1);
458	return 0;	450	return 0;
459	}	451	}
460		452
461	#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \	453	#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
462	defined(CONFIG_ARM)	454	defined(CONFIG_ARM)
463	static int reserve_mmu(void)	455	static int reserve_mmu(void)
464	{	456	{
465	/* reserve TLB table */	457	/* reserve TLB table */
466	gd->arch.tlb_size = PGTABLE_SIZE;	458	gd->arch.tlb_size = PGTABLE_SIZE;
467	gd->relocaddr -= gd->arch.tlb_size;	459	gd->relocaddr -= gd->arch.tlb_size;
468		460
469	/* round down to next 64 kB limit */	461	/* round down to next 64 kB limit */
470	gd->relocaddr &= ~(0x10000 - 1);	462	gd->relocaddr &= ~(0x10000 - 1);
471		463
472	gd->arch.tlb_addr = gd->relocaddr;	464	gd->arch.tlb_addr = gd->relocaddr;
473	debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,	465	debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
474	gd->arch.tlb_addr + gd->arch.tlb_size);	466	gd->arch.tlb_addr + gd->arch.tlb_size);
475	return 0;	467	return 0;
476	}	468	}
477	#endif	469	#endif
478		470
479	#ifdef CONFIG_LCD	471	#ifdef CONFIG_LCD
480	static int reserve_lcd(void)	472	static int reserve_lcd(void)
481	{	473	{
482	#ifdef CONFIG_FB_ADDR	474	#ifdef CONFIG_FB_ADDR
483	gd->fb_base = CONFIG_FB_ADDR;	475	gd->fb_base = CONFIG_FB_ADDR;
484	#else	476	#else
485	/* reserve memory for LCD display (always full pages) */	477	/* reserve memory for LCD display (always full pages) */
486	gd->relocaddr = lcd_setmem(gd->relocaddr);	478	gd->relocaddr = lcd_setmem(gd->relocaddr);
487	gd->fb_base = gd->relocaddr;	479	gd->fb_base = gd->relocaddr;
488	#endif /* CONFIG_FB_ADDR */	480	#endif /* CONFIG_FB_ADDR */
489	return 0;	481	return 0;
490	}	482	}
491	#endif /* CONFIG_LCD */	483	#endif /* CONFIG_LCD */
492		484
493	static int reserve_trace(void)	485	static int reserve_trace(void)
494	{	486	{
495	#ifdef CONFIG_TRACE	487	#ifdef CONFIG_TRACE
496	gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;	488	gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
497	gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);	489	gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
498	debug("Reserving %dk for trace data at: %08lx\n",	490	debug("Reserving %dk for trace data at: %08lx\n",
499	CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);	491	CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
500	#endif	492	#endif
501		493
502	return 0;	494	return 0;
503	}	495	}
504		496
505	#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) \|\| defined(CONFIG_8xx)) \	497	#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) \|\| defined(CONFIG_8xx)) \
506	&& !defined(CONFIG_ARM) && !defined(CONFIG_X86)	498	&& !defined(CONFIG_ARM) && !defined(CONFIG_X86)
507	static int reserve_video(void)	499	static int reserve_video(void)
508	{	500	{
509	/* reserve memory for video display (always full pages) */	501	/* reserve memory for video display (always full pages) */
510	gd->relocaddr = video_setmem(gd->relocaddr);	502	gd->relocaddr = video_setmem(gd->relocaddr);
511	gd->fb_base = gd->relocaddr;	503	gd->fb_base = gd->relocaddr;
512		504
513	return 0;	505	return 0;
514	}	506	}
515	#endif	507	#endif
516		508
517	static int reserve_uboot(void)	509	static int reserve_uboot(void)
518	{	510	{
519	/*	511	/*
520	* reserve memory for U-Boot code, data & bss	512	* reserve memory for U-Boot code, data & bss
521	* round down to next 4 kB limit	513	* round down to next 4 kB limit
522	*/	514	*/
523	gd->relocaddr -= gd->mon_len;	515	gd->relocaddr -= gd->mon_len;
524	gd->relocaddr &= ~(4096 - 1);	516	gd->relocaddr &= ~(4096 - 1);
525	#ifdef CONFIG_E500	517	#ifdef CONFIG_E500
526	/* round down to next 64 kB limit so that IVPR stays aligned */	518	/* round down to next 64 kB limit so that IVPR stays aligned */
527	gd->relocaddr &= ~(65536 - 1);	519	gd->relocaddr &= ~(65536 - 1);
528	#endif	520	#endif
529		521
530	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,	522	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,
531	gd->relocaddr);	523	gd->relocaddr);
532		524
533	gd->start_addr_sp = gd->relocaddr;	525	gd->start_addr_sp = gd->relocaddr;
534		526
535	return 0;	527	return 0;
536	}	528	}
537		529
538	#ifndef CONFIG_SPL_BUILD	530	#ifndef CONFIG_SPL_BUILD
539	/* reserve memory for malloc() area */	531	/* reserve memory for malloc() area */
540	static int reserve_malloc(void)	532	static int reserve_malloc(void)
541	{	533	{
542	gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;	534	gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
543	debug("Reserving %dk for malloc() at: %08lx\n",	535	debug("Reserving %dk for malloc() at: %08lx\n",
544	TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);	536	TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
545	return 0;	537	return 0;
546	}	538	}
547		539
548	/* (permanently) allocate a Board Info struct */	540	/* (permanently) allocate a Board Info struct */
549	static int reserve_board(void)	541	static int reserve_board(void)
550	{	542	{
551	gd->start_addr_sp -= sizeof(bd_t);	543	gd->start_addr_sp -= sizeof(bd_t);
552	gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));	544	gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
553	memset(gd->bd, '\0', sizeof(bd_t));	545	memset(gd->bd, '\0', sizeof(bd_t));
554	debug("Reserving %zu Bytes for Board Info at: %08lx\n",	546	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
555	sizeof(bd_t), gd->start_addr_sp);	547	sizeof(bd_t), gd->start_addr_sp);
556	return 0;	548	return 0;
557	}	549	}
558	#endif	550	#endif
559		551
560	static int setup_machine(void)	552	static int setup_machine(void)
561	{	553	{
562	#ifdef CONFIG_MACH_TYPE	554	#ifdef CONFIG_MACH_TYPE
563	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */	555	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
564	#endif	556	#endif
565	return 0;	557	return 0;
566	}	558	}
567		559
568	static int reserve_global_data(void)	560	static int reserve_global_data(void)
569	{	561	{
570	gd->start_addr_sp -= sizeof(gd_t);	562	gd->start_addr_sp -= sizeof(gd_t);
571	gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));	563	gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
572	debug("Reserving %zu Bytes for Global Data at: %08lx\n",	564	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
573	sizeof(gd_t), gd->start_addr_sp);	565	sizeof(gd_t), gd->start_addr_sp);
574	return 0;	566	return 0;
575	}	567	}
576		568
577	static int reserve_fdt(void)	569	static int reserve_fdt(void)
578	{	570	{
579	/*	571	/*
580	* If the device tree is sitting immediate above our image then we	572	* If the device tree is sitting immediate above our image then we
581	* must relocate it. If it is embedded in the data section, then it	573	* must relocate it. If it is embedded in the data section, then it
582	* will be relocated with other data.	574	* will be relocated with other data.
583	*/	575	*/
584	if (gd->fdt_blob) {	576	if (gd->fdt_blob) {
585	gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);	577	gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
586		578
587	gd->start_addr_sp -= gd->fdt_size;	579	gd->start_addr_sp -= gd->fdt_size;
588	gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);	580	gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
589	debug("Reserving %lu Bytes for FDT at: %08lx\n",	581	debug("Reserving %lu Bytes for FDT at: %08lx\n",
590	gd->fdt_size, gd->start_addr_sp);	582	gd->fdt_size, gd->start_addr_sp);
591	}	583	}
592		584
593	return 0;	585	return 0;
594	}	586	}
595		587
596	static int reserve_stacks(void)	588	static int reserve_stacks(void)
597	{	589	{
598	#ifdef CONFIG_SPL_BUILD	590	#ifdef CONFIG_SPL_BUILD
599	# ifdef CONFIG_ARM	591	# ifdef CONFIG_ARM
600	gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */	592	gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */
601	gd->irq_sp = gd->start_addr_sp;	593	gd->irq_sp = gd->start_addr_sp;
602	# endif	594	# endif
603	#else	595	#else
604	# ifdef CONFIG_PPC	596	# ifdef CONFIG_PPC
605	ulong *s;	597	ulong *s;
606	# endif	598	# endif
607		599
608	/* setup stack pointer for exceptions */	600	/* setup stack pointer for exceptions */
609	gd->start_addr_sp -= 16;	601	gd->start_addr_sp -= 16;
610	gd->start_addr_sp &= ~0xf;	602	gd->start_addr_sp &= ~0xf;
611	gd->irq_sp = gd->start_addr_sp;	603	gd->irq_sp = gd->start_addr_sp;
612		604
613	/*	605	/*
614	* Handle architecture-specific things here	606	* Handle architecture-specific things here
615	* TODO(sjg@chromium.org): Perhaps create arch_reserve_stack()	607	* TODO(sjg@chromium.org): Perhaps create arch_reserve_stack()
616	* to handle this and put in arch/xxx/lib/stack.c	608	* to handle this and put in arch/xxx/lib/stack.c
617	*/	609	*/
618	# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)	610	# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
619	# ifdef CONFIG_USE_IRQ	611	# ifdef CONFIG_USE_IRQ
620	gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);	612	gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
621	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",	613	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
622	CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);	614	CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);
623		615
624	/* 8-byte alignment for ARM ABI compliance */	616	/* 8-byte alignment for ARM ABI compliance */
625	gd->start_addr_sp &= ~0x07;	617	gd->start_addr_sp &= ~0x07;
626	# endif	618	# endif
627	/* leave 3 words for abort-stack, plus 1 for alignment */	619	/* leave 3 words for abort-stack, plus 1 for alignment */
628	gd->start_addr_sp -= 16;	620	gd->start_addr_sp -= 16;
629	# elif defined(CONFIG_PPC)	621	# elif defined(CONFIG_PPC)
630	/* Clear initial stack frame */	622	/* Clear initial stack frame */
631	s = (ulong *) gd->start_addr_sp;	623	s = (ulong *) gd->start_addr_sp;
632	s = 0; / Terminate back chain */	624	s = 0; / Terminate back chain */
633	++s = 0; / NULL return address */	625	++s = 0; / NULL return address */
634	# endif /* Architecture specific code */	626	# endif /* Architecture specific code */
635		627
636	return 0;	628	return 0;
637	#endif	629	#endif
638	}	630	}
639		631
640	static int display_new_sp(void)	632	static int display_new_sp(void)
641	{	633	{
642	debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);	634	debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
643		635
644	return 0;	636	return 0;
645	}	637	}
646		638
647	#ifdef CONFIG_PPC	639	#ifdef CONFIG_PPC
648	static int setup_board_part1(void)	640	static int setup_board_part1(void)
649	{	641	{
650	bd_t *bd = gd->bd;	642	bd_t *bd = gd->bd;
651		643
652	/*	644	/*
653	* Save local variables to board info struct	645	* Save local variables to board info struct
654	*/	646	*/
655		647
656	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */	648	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
657	bd->bi_memsize = gd->ram_size; /* size in bytes */	649	bd->bi_memsize = gd->ram_size; /* size in bytes */
658		650
659	#ifdef CONFIG_SYS_SRAM_BASE	651	#ifdef CONFIG_SYS_SRAM_BASE
660	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */	652	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
661	bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */	653	bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
662	#endif	654	#endif
663		655
664	#if defined(CONFIG_8xx) \|\| defined(CONFIG_8260) \|\| defined(CONFIG_5xx) \|\| \	656	#if defined(CONFIG_8xx) \|\| defined(CONFIG_8260) \|\| defined(CONFIG_5xx) \|\| \
665	defined(CONFIG_E500) \|\| defined(CONFIG_MPC86xx)	657	defined(CONFIG_E500) \|\| defined(CONFIG_MPC86xx)
666	bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */	658	bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
667	#endif	659	#endif
668	#if defined(CONFIG_MPC5xxx)	660	#if defined(CONFIG_MPC5xxx)
669	bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */	661	bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
670	#endif	662	#endif
671	#if defined(CONFIG_MPC83xx)	663	#if defined(CONFIG_MPC83xx)
672	bd->bi_immrbar = CONFIG_SYS_IMMR;	664	bd->bi_immrbar = CONFIG_SYS_IMMR;
673	#endif	665	#endif
674		666
675	return 0;	667	return 0;
676	}	668	}
677		669
678	static int setup_board_part2(void)	670	static int setup_board_part2(void)
679	{	671	{
680	bd_t *bd = gd->bd;	672	bd_t *bd = gd->bd;
681		673
682	bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */	674	bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
683	bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */	675	bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
684	#if defined(CONFIG_CPM2)	676	#if defined(CONFIG_CPM2)
685	bd->bi_cpmfreq = gd->arch.cpm_clk;	677	bd->bi_cpmfreq = gd->arch.cpm_clk;
686	bd->bi_brgfreq = gd->arch.brg_clk;	678	bd->bi_brgfreq = gd->arch.brg_clk;
687	bd->bi_sccfreq = gd->arch.scc_clk;	679	bd->bi_sccfreq = gd->arch.scc_clk;
688	bd->bi_vco = gd->arch.vco_out;	680	bd->bi_vco = gd->arch.vco_out;
689	#endif /* CONFIG_CPM2 */	681	#endif /* CONFIG_CPM2 */
690	#if defined(CONFIG_MPC512X)	682	#if defined(CONFIG_MPC512X)
691	bd->bi_ipsfreq = gd->arch.ips_clk;	683	bd->bi_ipsfreq = gd->arch.ips_clk;
692	#endif /* CONFIG_MPC512X */	684	#endif /* CONFIG_MPC512X */
693	#if defined(CONFIG_MPC5xxx)	685	#if defined(CONFIG_MPC5xxx)
694	bd->bi_ipbfreq = gd->arch.ipb_clk;	686	bd->bi_ipbfreq = gd->arch.ipb_clk;
695	bd->bi_pcifreq = gd->pci_clk;	687	bd->bi_pcifreq = gd->pci_clk;
696	#endif /* CONFIG_MPC5xxx */	688	#endif /* CONFIG_MPC5xxx */
697		689
698	return 0;	690	return 0;
699	}	691	}
700	#endif	692	#endif
701		693
702	#ifdef CONFIG_SYS_EXTBDINFO	694	#ifdef CONFIG_SYS_EXTBDINFO
703	static int setup_board_extra(void)	695	static int setup_board_extra(void)
704	{	696	{
705	bd_t *bd = gd->bd;	697	bd_t *bd = gd->bd;
706		698
707	strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));	699	strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
708	strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,	700	strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
709	sizeof(bd->bi_r_version));	701	sizeof(bd->bi_r_version));
710		702
711	bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */	703	bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
712	bd->bi_plb_busfreq = gd->bus_clk;	704	bd->bi_plb_busfreq = gd->bus_clk;
713	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP) \|\| \	705	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP) \|\| \
714	defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \	706	defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
715	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)	707	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
716	bd->bi_pci_busfreq = get_PCI_freq();	708	bd->bi_pci_busfreq = get_PCI_freq();
717	bd->bi_opbfreq = get_OPB_freq();	709	bd->bi_opbfreq = get_OPB_freq();
718	#elif defined(CONFIG_XILINX_405)	710	#elif defined(CONFIG_XILINX_405)
719	bd->bi_pci_busfreq = get_PCI_freq();	711	bd->bi_pci_busfreq = get_PCI_freq();
720	#endif	712	#endif
721		713
722	return 0;	714	return 0;
723	}	715	}
724	#endif	716	#endif
725		717
726	#ifdef CONFIG_POST	718	#ifdef CONFIG_POST
727	static int init_post(void)	719	static int init_post(void)
728	{	720	{
729	post_bootmode_init();	721	post_bootmode_init();
730	post_run(NULL, POST_ROM \| post_bootmode_get(0));	722	post_run(NULL, POST_ROM \| post_bootmode_get(0));
731		723
732	return 0;	724	return 0;
733	}	725	}
734	#endif	726	#endif
735		727
736	static int setup_baud_rate(void)	728	static int setup_baud_rate(void)
737	{	729	{
738	/* Ick, can we get rid of this line? */	730	/* Ick, can we get rid of this line? */
739	gd->bd->bi_baudrate = gd->baudrate;	731	gd->bd->bi_baudrate = gd->baudrate;
740		732
741	return 0;	733	return 0;
742	}	734	}
743		735
744	static int setup_dram_config(void)	736	static int setup_dram_config(void)
745	{	737	{
746	/* Ram is board specific, so move it to board code ... */	738	/* Ram is board specific, so move it to board code ... */
747	dram_init_banksize();	739	dram_init_banksize();
748		740
749	return 0;	741	return 0;
750	}	742	}
751		743
752	static int reloc_fdt(void)	744	static int reloc_fdt(void)
753	{	745	{
754	if (gd->new_fdt) {	746	if (gd->new_fdt) {
755	memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);	747	memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
756	gd->fdt_blob = gd->new_fdt;	748	gd->fdt_blob = gd->new_fdt;
757	}	749	}
758		750
759	return 0;	751	return 0;
760	}	752	}
761		753
762	static int setup_reloc(void)	754	static int setup_reloc(void)
763	{	755	{
764	gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;	756	gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
765	memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));	757	memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
766		758
767	debug("Relocation Offset is: %08lx\n", gd->reloc_off);	759	debug("Relocation Offset is: %08lx\n", gd->reloc_off);
768	debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",	760	debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
769	gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),	761	gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
770	gd->start_addr_sp);	762	gd->start_addr_sp);
771		763
772	return 0;	764	return 0;
773	}	765	}
774		766
775	/* ARM calls relocate_code from its crt0.S */	767	/* ARM calls relocate_code from its crt0.S */
776	#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)	768	#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
777		769
778	static int jump_to_copy(void)	770	static int jump_to_copy(void)
779	{	771	{
780	/*	772	/*
781	* x86 is special, but in a nice way. It uses a trampoline which	773	* x86 is special, but in a nice way. It uses a trampoline which
782	* enables the dcache if possible.	774	* enables the dcache if possible.
783	*	775	*
784	* For now, other archs use relocate_code(), which is implemented	776	* For now, other archs use relocate_code(), which is implemented
785	* similarly for all archs. When we do generic relocation, hopefully	777	* similarly for all archs. When we do generic relocation, hopefully
786	* we can make all archs enable the dcache prior to relocation.	778	* we can make all archs enable the dcache prior to relocation.
787	*/	779	*/
788	#ifdef CONFIG_X86	780	#ifdef CONFIG_X86
789	/*	781	/*
790	* SDRAM and console are now initialised. The final stack can now	782	* SDRAM and console are now initialised. The final stack can now
791	* be setup in SDRAM. Code execution will continue in Flash, but	783	* be setup in SDRAM. Code execution will continue in Flash, but
792	* with the stack in SDRAM and Global Data in temporary memory	784	* with the stack in SDRAM and Global Data in temporary memory
793	* (CPU cache)	785	* (CPU cache)
794	*/	786	*/
795	board_init_f_r_trampoline(gd->start_addr_sp);	787	board_init_f_r_trampoline(gd->start_addr_sp);
796	#else	788	#else
797	relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);	789	relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
798	#endif	790	#endif
799		791
800	return 0;	792	return 0;
801	}	793	}
802	#endif	794	#endif
803		795
804	/* Record the board_init_f() bootstage (after arch_cpu_init()) */	796	/* Record the board_init_f() bootstage (after arch_cpu_init()) */
805	static int mark_bootstage(void)	797	static int mark_bootstage(void)
806	{	798	{
807	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");	799	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
808		800
809	return 0;	801	return 0;
810	}	802	}
811		803
812	static init_fnc_t init_sequence_f[] = {	804	static init_fnc_t init_sequence_f[] = {
813	#ifdef CONFIG_SANDBOX	805	#ifdef CONFIG_SANDBOX
814	setup_ram_buf,	806	setup_ram_buf,
815	#endif	807	#endif
816	setup_mon_len,	808	setup_mon_len,
817	setup_fdt,	809	setup_fdt,
818	trace_early_init,	810	trace_early_init,
819	#if defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)	811	#if defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)
820	/* TODO: can this go into arch_cpu_init()? */	812	/* TODO: can this go into arch_cpu_init()? */
821	probecpu,	813	probecpu,
822	#endif	814	#endif
823	arch_cpu_init, /* basic arch cpu dependent setup */	815	arch_cpu_init, /* basic arch cpu dependent setup */
824	#ifdef CONFIG_X86	816	#ifdef CONFIG_X86
825	cpu_init_f, /* TODO(sjg@chromium.org): remove */	817	cpu_init_f, /* TODO(sjg@chromium.org): remove */
826	# ifdef CONFIG_OF_CONTROL	818	# ifdef CONFIG_OF_CONTROL
827	find_fdt, /* TODO(sjg@chromium.org): remove */	819	find_fdt, /* TODO(sjg@chromium.org): remove */
828	# endif	820	# endif
829	#endif	821	#endif
830	mark_bootstage,	822	mark_bootstage,
831	#ifdef CONFIG_OF_CONTROL	823	#ifdef CONFIG_OF_CONTROL
832	fdtdec_check_fdt,	824	fdtdec_check_fdt,
833	#endif	825	#endif
834	#if defined(CONFIG_BOARD_EARLY_INIT_F)	826	#if defined(CONFIG_BOARD_EARLY_INIT_F)
835	board_early_init_f,	827	board_early_init_f,
836	#endif	828	#endif
837	/* TODO: can any of this go into arch_cpu_init()? */	829	/* TODO: can any of this go into arch_cpu_init()? */
838	#if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT)	830	#if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT)
839	get_clocks, /* get CPU and bus clocks (etc.) */	831	get_clocks, /* get CPU and bus clocks (etc.) */
840	#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \	832	#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
841	&& !defined(CONFIG_TQM885D)	833	&& !defined(CONFIG_TQM885D)
842	adjust_sdram_tbs_8xx,	834	adjust_sdram_tbs_8xx,
843	#endif	835	#endif
844	/* TODO: can we rename this to timer_init()? */	836	/* TODO: can we rename this to timer_init()? */
845	init_timebase,	837	init_timebase,
846	#endif	838	#endif
847	#ifdef CONFIG_ARM	839	#ifdef CONFIG_ARM
848	timer_init, /* initialize timer */	840	timer_init, /* initialize timer */
849	#endif	841	#endif
850	#ifdef CONFIG_SYS_ALLOC_DPRAM	842	#ifdef CONFIG_SYS_ALLOC_DPRAM
851	#if !defined(CONFIG_CPM2)	843	#if !defined(CONFIG_CPM2)
852	dpram_init,	844	dpram_init,
853	#endif	845	#endif
854	#endif	846	#endif
855	#if defined(CONFIG_BOARD_POSTCLK_INIT)	847	#if defined(CONFIG_BOARD_POSTCLK_INIT)
856	board_postclk_init,	848	board_postclk_init,
857	#endif	849	#endif
858	#ifdef CONFIG_FSL_ESDHC	850	#ifdef CONFIG_FSL_ESDHC
859	get_clocks,	851	get_clocks,
860	#endif	852	#endif
861	env_init, /* initialize environment */	853	env_init, /* initialize environment */
862	#if defined(CONFIG_8xx_CPUCLK_DEFAULT)	854	#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
863	/* get CPU and bus clocks according to the environment variable */	855	/* get CPU and bus clocks according to the environment variable */
864	get_clocks_866,	856	get_clocks_866,
865	/* adjust sdram refresh rate according to the new clock */	857	/* adjust sdram refresh rate according to the new clock */
866	sdram_adjust_866,	858	sdram_adjust_866,
867	init_timebase,	859	init_timebase,
868	#endif	860	#endif
869	init_baud_rate, /* initialze baudrate settings */	861	init_baud_rate, /* initialze baudrate settings */
870	serial_init, /* serial communications setup */	862	serial_init, /* serial communications setup */
871	console_init_f, /* stage 1 init of console */	863	console_init_f, /* stage 1 init of console */
872	#ifdef CONFIG_SANDBOX	864	#ifdef CONFIG_SANDBOX
873	sandbox_early_getopt_check,	865	sandbox_early_getopt_check,
874	#endif	866	#endif
875	#ifdef CONFIG_OF_CONTROL	867	#ifdef CONFIG_OF_CONTROL
876	fdtdec_prepare_fdt,	868	fdtdec_prepare_fdt,
877	#endif	869	#endif
878	display_options, /* say that we are here */	870	display_options, /* say that we are here */
879	display_text_info, /* show debugging info if required */	871	display_text_info, /* show debugging info if required */
880	#if defined(CONFIG_8260)	872	#if defined(CONFIG_8260)
881	prt_8260_rsr,	873	prt_8260_rsr,
882	prt_8260_clks,	874	prt_8260_clks,
883	#endif /* CONFIG_8260 */	875	#endif /* CONFIG_8260 */
884	#if defined(CONFIG_MPC83xx)	876	#if defined(CONFIG_MPC83xx)
885	prt_83xx_rsr,	877	prt_83xx_rsr,
886	#endif	878	#endif
887	#ifdef CONFIG_PPC	879	#ifdef CONFIG_PPC
888	checkcpu,	880	checkcpu,
889	#endif	881	#endif
890	print_cpuinfo, /* display cpu info (and speed) */	882	print_cpuinfo, /* display cpu info (and speed) */
891	#if defined(CONFIG_MPC5xxx)	883	#if defined(CONFIG_MPC5xxx)
892	prt_mpc5xxx_clks,	884	prt_mpc5xxx_clks,
893	#endif /* CONFIG_MPC5xxx */	885	#endif /* CONFIG_MPC5xxx */
894	#if defined(CONFIG_DISPLAY_BOARDINFO)	886	#if defined(CONFIG_DISPLAY_BOARDINFO)
895	checkboard, /* display board info */	887	checkboard, /* display board info */
896	#endif	888	#endif
897	INIT_FUNC_WATCHDOG_INIT	889	INIT_FUNC_WATCHDOG_INIT
898	#if defined(CONFIG_MISC_INIT_F)	890	#if defined(CONFIG_MISC_INIT_F)
899	misc_init_f,	891	misc_init_f,
900	#endif	892	#endif
901	INIT_FUNC_WATCHDOG_RESET	893	INIT_FUNC_WATCHDOG_RESET
902	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SYS_I2C)	894	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SYS_I2C)
903	init_func_i2c,	895	init_func_i2c,
904	#endif	896	#endif
905	#if defined(CONFIG_HARD_SPI)	897	#if defined(CONFIG_HARD_SPI)
906	init_func_spi,	898	init_func_spi,
907	#endif	899	#endif
908	#ifdef CONFIG_X86	900	#ifdef CONFIG_X86
909	dram_init_f, /* configure available RAM banks */	901	dram_init_f, /* configure available RAM banks */
910	calculate_relocation_address,	902	calculate_relocation_address,
911	#endif	903	#endif
912	announce_dram_init,	904	announce_dram_init,
913	/* TODO: unify all these dram functions? */	905	/* TODO: unify all these dram functions? */
914	#ifdef CONFIG_ARM	906	#ifdef CONFIG_ARM
915	dram_init, /* configure available RAM banks */	907	dram_init, /* configure available RAM banks */
916	#endif	908	#endif
917	#ifdef CONFIG_PPC	909	#ifdef CONFIG_PPC
918	init_func_ram,	910	init_func_ram,
919	#endif	911	#endif
920	#ifdef CONFIG_POST	912	#ifdef CONFIG_POST
921	post_init_f,	913	post_init_f,
922	#endif	914	#endif
923	INIT_FUNC_WATCHDOG_RESET	915	INIT_FUNC_WATCHDOG_RESET
924	#if defined(CONFIG_SYS_DRAM_TEST)	916	#if defined(CONFIG_SYS_DRAM_TEST)
925	testdram,	917	testdram,
926	#endif /* CONFIG_SYS_DRAM_TEST */	918	#endif /* CONFIG_SYS_DRAM_TEST */
927	INIT_FUNC_WATCHDOG_RESET	919	INIT_FUNC_WATCHDOG_RESET
928		920
929	#ifdef CONFIG_POST	921	#ifdef CONFIG_POST
930	init_post,	922	init_post,
931	#endif	923	#endif
932	INIT_FUNC_WATCHDOG_RESET	924	INIT_FUNC_WATCHDOG_RESET
933	/*	925	/*
934	* Now that we have DRAM mapped and working, we can	926	* Now that we have DRAM mapped and working, we can
935	* relocate the code and continue running from DRAM.	927	* relocate the code and continue running from DRAM.
936	*	928	*
937	* Reserve memory at end of RAM for (top down in that order):	929	* Reserve memory at end of RAM for (top down in that order):
938	* - area that won't get touched by U-Boot and Linux (optional)	930	* - area that won't get touched by U-Boot and Linux (optional)
939	* - kernel log buffer	931	* - kernel log buffer
940	* - protected RAM	932	* - protected RAM
941	* - LCD framebuffer	933	* - LCD framebuffer
942	* - monitor code	934	* - monitor code
943	* - board info struct	935	* - board info struct
944	*/	936	*/
945	setup_dest_addr,	937	setup_dest_addr,
946	#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)	938	#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
947	reserve_logbuffer,	939	reserve_logbuffer,
948	#endif	940	#endif
949	#ifdef CONFIG_PRAM	941	#ifdef CONFIG_PRAM
950	reserve_pram,	942	reserve_pram,
951	#endif	943	#endif
952	reserve_round_4k,	944	reserve_round_4k,
953	#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \	945	#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
954	defined(CONFIG_ARM)	946	defined(CONFIG_ARM)
955	reserve_mmu,	947	reserve_mmu,
956	#endif	948	#endif
957	#ifdef CONFIG_LCD	949	#ifdef CONFIG_LCD
958	reserve_lcd,	950	reserve_lcd,
959	#endif	951	#endif
960	reserve_trace,	952	reserve_trace,
961	/* TODO: Why the dependency on CONFIG_8xx? */	953	/* TODO: Why the dependency on CONFIG_8xx? */
962	#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) \|\| defined(CONFIG_8xx)) \	954	#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) \|\| defined(CONFIG_8xx)) \
963	&& !defined(CONFIG_ARM) && !defined(CONFIG_X86)	955	&& !defined(CONFIG_ARM) && !defined(CONFIG_X86)
964	reserve_video,	956	reserve_video,
965	#endif	957	#endif
966	reserve_uboot,	958	reserve_uboot,
967	#ifndef CONFIG_SPL_BUILD	959	#ifndef CONFIG_SPL_BUILD
968	reserve_malloc,	960	reserve_malloc,
969	reserve_board,	961	reserve_board,
970	#endif	962	#endif
971	setup_machine,	963	setup_machine,
972	reserve_global_data,	964	reserve_global_data,
973	reserve_fdt,	965	reserve_fdt,
974	reserve_stacks,	966	reserve_stacks,
975	setup_dram_config,	967	setup_dram_config,
976	show_dram_config,	968	show_dram_config,
977	#ifdef CONFIG_PPC	969	#ifdef CONFIG_PPC
978	setup_board_part1,	970	setup_board_part1,
979	INIT_FUNC_WATCHDOG_RESET	971	INIT_FUNC_WATCHDOG_RESET
980	setup_board_part2,	972	setup_board_part2,
981	#endif	973	#endif
982	setup_baud_rate,	974	setup_baud_rate,
983	display_new_sp,	975	display_new_sp,
984	#ifdef CONFIG_SYS_EXTBDINFO	976	#ifdef CONFIG_SYS_EXTBDINFO
985	setup_board_extra,	977	setup_board_extra,
986	#endif	978	#endif
987	INIT_FUNC_WATCHDOG_RESET	979	INIT_FUNC_WATCHDOG_RESET
988	reloc_fdt,	980	reloc_fdt,
989	setup_reloc,	981	setup_reloc,
990	#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)	982	#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
991	jump_to_copy,	983	jump_to_copy,
992	#endif	984	#endif
993	NULL,	985	NULL,
994	};	986	};
995		987
996	void board_init_f(ulong boot_flags)	988	void board_init_f(ulong boot_flags)
997	{	989	{
998	#ifndef CONFIG_X86	990	#ifndef CONFIG_X86
999	gd_t data;	991	gd_t data;
1000		992
1001	gd = &data;	993	gd = &data;
1002	#endif	994	#endif
1003		995
1004	/*	996	/*
1005	* Clear global data before it is accessed at debug print	997	* Clear global data before it is accessed at debug print
1006	* in initcall_run_list. Otherwise the debug print probably	998	* in initcall_run_list. Otherwise the debug print probably
1007	* get the wrong vaule of gd->have_console.	999	* get the wrong vaule of gd->have_console.
1008	*/	1000	*/
1009	#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \	1001	#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
1010	!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \	1002	!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
1011	!defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)	1003	!defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
1012	zero_global_data();	1004	zero_global_data();
1013	#endif	1005	#endif
1014		1006
1015	gd->flags = boot_flags;	1007	gd->flags = boot_flags;
1016	gd->have_console = 0;	1008	gd->have_console = 0;
1017		1009
1018	if (initcall_run_list(init_sequence_f))	1010	if (initcall_run_list(init_sequence_f))
1019	hang();	1011	hang();
1020		1012
1021	#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)	1013	#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
1022	/* NOTREACHED - jump_to_copy() does not return */	1014	/* NOTREACHED - jump_to_copy() does not return */
1023	hang();	1015	hang();
1024	#endif	1016	#endif
1025	}	1017	}
1026		1018
1027	#ifdef CONFIG_X86	1019	#ifdef CONFIG_X86
1028	/*	1020	/*
1029	* For now this code is only used on x86.	1021	* For now this code is only used on x86.
1030	*	1022	*
1031	* init_sequence_f_r is the list of init functions which are run when	1023	* init_sequence_f_r is the list of init functions which are run when
1032	* U-Boot is executing from Flash with a semi-limited 'C' environment.	1024	* U-Boot is executing from Flash with a semi-limited 'C' environment.
1033	* The following limitations must be considered when implementing an	1025	* The following limitations must be considered when implementing an
1034	* '_f_r' function:	1026	* '_f_r' function:
1035	* - 'static' variables are read-only	1027	* - 'static' variables are read-only
1036	* - Global Data (gd->xxx) is read/write	1028	* - Global Data (gd->xxx) is read/write
1037	*	1029	*
1038	* The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if	1030	* The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1039	* supported). It _should_, if possible, copy global data to RAM and	1031	* supported). It _should_, if possible, copy global data to RAM and
1040	* initialise the CPU caches (to speed up the relocation process)	1032	* initialise the CPU caches (to speed up the relocation process)
1041	*	1033	*
1042	* NOTE: At present only x86 uses this route, but it is intended that	1034	* NOTE: At present only x86 uses this route, but it is intended that
1043	* all archs will move to this when generic relocation is implemented.	1035	* all archs will move to this when generic relocation is implemented.
1044	*/	1036	*/
1045	static init_fnc_t init_sequence_f_r[] = {	1037	static init_fnc_t init_sequence_f_r[] = {
1046	init_cache_f_r,	1038	init_cache_f_r,
1047	copy_uboot_to_ram,	1039	copy_uboot_to_ram,
1048	clear_bss,	1040	clear_bss,
1049	do_elf_reloc_fixups,	1041	do_elf_reloc_fixups,
1050		1042
1051	NULL,	1043	NULL,
1052	};	1044	};
1053		1045
1054	void board_init_f_r(void)	1046	void board_init_f_r(void)
1055	{	1047	{
1056	if (initcall_run_list(init_sequence_f_r))	1048	if (initcall_run_list(init_sequence_f_r))
1057	hang();	1049	hang();
1058		1050
1059	/*	1051	/*
1060	* U-Boot has been copied into SDRAM, the BSS has been cleared etc.	1052	* U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1061	* Transfer execution from Flash to RAM by calculating the address	1053	* Transfer execution from Flash to RAM by calculating the address
1062	* of the in-RAM copy of board_init_r() and calling it	1054	* of the in-RAM copy of board_init_r() and calling it
1063	*/	1055	*/
1064	(board_init_r + gd->reloc_off)(gd, gd->relocaddr);	1056	(board_init_r + gd->reloc_off)(gd, gd->relocaddr);
1065		1057
1066	/* NOTREACHED - board_init_r() does not return */	1058	/* NOTREACHED - board_init_r() does not return */
1067	hang();	1059	hang();
1068	}	1060	}
1069	#endif /* CONFIG_X86 */	1061	#endif /* CONFIG_X86 */
1070		1062

common/board_r.c

Diff comments View file @ b60eff3

1	/*	1	/*
2	* Copyright (c) 2011 The Chromium OS Authors.	2	* Copyright (c) 2011 The Chromium OS Authors.
3	* (C) Copyright 2002-2006	3	* (C) Copyright 2002-2006
4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5	*	5	*
6	* (C) Copyright 2002	6	* (C) Copyright 2002
7	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>	7	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8	* Marius Groeger <mgroeger@sysgo.de>	8	* Marius Groeger <mgroeger@sysgo.de>
9	*	9	*
10	* SPDX-License-Identifier: GPL-2.0+	10	* SPDX-License-Identifier: GPL-2.0+
11	*/	11	*/
12		12
13	#include <common.h>	13	#include <common.h>
14	/* TODO: can we just include all these headers whether needed or not? */	14	/* TODO: can we just include all these headers whether needed or not? */
15	#if defined(CONFIG_CMD_BEDBUG)	15	#if defined(CONFIG_CMD_BEDBUG)
16	#include <bedbug/type.h>	16	#include <bedbug/type.h>
17	#endif	17	#endif
18	#ifdef CONFIG_HAS_DATAFLASH	18	#ifdef CONFIG_HAS_DATAFLASH
19	#include <dataflash.h>	19	#include <dataflash.h>
20	#endif	20	#endif
21	#include <environment.h>	21	#include <environment.h>
22	#include <fdtdec.h>	22	#include <fdtdec.h>
23	#if defined(CONFIG_CMD_IDE)	23	#if defined(CONFIG_CMD_IDE)
24	#include <ide.h>	24	#include <ide.h>
25	#endif	25	#endif
26	#include <initcall.h>	26	#include <initcall.h>
27	#ifdef CONFIG_PS2KBD	27	#ifdef CONFIG_PS2KBD
28	#include <keyboard.h>	28	#include <keyboard.h>
29	#endif	29	#endif
30	#if defined(CONFIG_CMD_KGDB)	30	#if defined(CONFIG_CMD_KGDB)
31	#include <kgdb.h>	31	#include <kgdb.h>
32	#endif	32	#endif
33	#include <logbuff.h>	33	#include <logbuff.h>
34	#include <malloc.h>	34	#include <malloc.h>
35	#ifdef CONFIG_BITBANGMII	35	#ifdef CONFIG_BITBANGMII
36	#include <miiphy.h>	36	#include <miiphy.h>
37	#endif	37	#endif
38	#include <mmc.h>	38	#include <mmc.h>
39	#include <nand.h>	39	#include <nand.h>
40	#include <onenand_uboot.h>	40	#include <onenand_uboot.h>
41	#include <scsi.h>	41	#include <scsi.h>
42	#include <serial.h>	42	#include <serial.h>
43	#include <spi.h>	43	#include <spi.h>
44	#include <stdio_dev.h>	44	#include <stdio_dev.h>
45	#include <trace.h>	45	#include <trace.h>
46	#include <watchdog.h>	46	#include <watchdog.h>
47	#ifdef CONFIG_ADDR_MAP	47	#ifdef CONFIG_ADDR_MAP
48	#include <asm/mmu.h>	48	#include <asm/mmu.h>
49	#endif	49	#endif
50	#include <asm/sections.h>	50	#include <asm/sections.h>
51	#ifdef CONFIG_X86	51	#ifdef CONFIG_X86
52	#include <asm/init_helpers.h>	52	#include <asm/init_helpers.h>
53	#endif	53	#endif
54	#include <linux/compiler.h>	54	#include <linux/compiler.h>
55		55
56	DECLARE_GLOBAL_DATA_PTR;	56	DECLARE_GLOBAL_DATA_PTR;
57		57
58	ulong monitor_flash_len;	58	ulong monitor_flash_len;
59		59
60	int __board_flash_wp_on(void)	60	int __board_flash_wp_on(void)
61	{	61	{
62	/*	62	/*
63	* Most flashes can't be detected when write protection is enabled,	63	* Most flashes can't be detected when write protection is enabled,
64	* so provide a way to let U-Boot gracefully ignore write protected	64	* so provide a way to let U-Boot gracefully ignore write protected
65	* devices.	65	* devices.
66	*/	66	*/
67	return 0;	67	return 0;
68	}	68	}
69		69
70	int board_flash_wp_on(void)	70	int board_flash_wp_on(void)
71	__attribute__ ((weak, alias("__board_flash_wp_on")));	71	__attribute__ ((weak, alias("__board_flash_wp_on")));
72		72
73	void __cpu_secondary_init_r(void)	73	void __cpu_secondary_init_r(void)
74	{	74	{
75	}	75	}
76		76
77	void cpu_secondary_init_r(void)	77	void cpu_secondary_init_r(void)
78	__attribute__ ((weak, alias("__cpu_secondary_init_r")));	78	__attribute__ ((weak, alias("__cpu_secondary_init_r")));
79		79
80	static int initr_secondary_cpu(void)	80	static int initr_secondary_cpu(void)
81	{	81	{
82	/*	82	/*
83	* after non-volatile devices & environment is setup and cpu code have	83	* after non-volatile devices & environment is setup and cpu code have
84	* another round to deal with any initialization that might require	84	* another round to deal with any initialization that might require
85	* full access to the environment or loading of some image (firmware)	85	* full access to the environment or loading of some image (firmware)
86	* from a non-volatile device	86	* from a non-volatile device
87	*/	87	*/
88	/* TODO: maybe define this for all archs? */	88	/* TODO: maybe define this for all archs? */
89	cpu_secondary_init_r();	89	cpu_secondary_init_r();
90		90
91	return 0;	91	return 0;
92	}	92	}
93		93
94	static int initr_trace(void)	94	static int initr_trace(void)
95	{	95	{
96	#ifdef CONFIG_TRACE	96	#ifdef CONFIG_TRACE
97	trace_init(gd->trace_buff, CONFIG_TRACE_BUFFER_SIZE);	97	trace_init(gd->trace_buff, CONFIG_TRACE_BUFFER_SIZE);
98	#endif	98	#endif
99		99
100	return 0;	100	return 0;
101	}	101	}
102		102
103	static int initr_reloc(void)	103	static int initr_reloc(void)
104	{	104	{
105	gd->flags \|= GD_FLG_RELOC; /* tell others: relocation done */	105	gd->flags \|= GD_FLG_RELOC; /* tell others: relocation done */
106	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");	106	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
107		107
108	return 0;	108	return 0;
109	}	109	}
110		110
111	#ifdef CONFIG_ARM	111	#ifdef CONFIG_ARM
112	/*	112	/*
113	* Some of these functions are needed purely because the functions they	113	* Some of these functions are needed purely because the functions they
114	* call return void. If we change them to return 0, these stubs can go away.	114	* call return void. If we change them to return 0, these stubs can go away.
115	*/	115	*/
116	static int initr_caches(void)	116	static int initr_caches(void)
117	{	117	{
118	/* Enable caches */	118	/* Enable caches */
119	enable_caches();	119	enable_caches();
120	return 0;	120	return 0;
121	}	121	}
122	#endif	122	#endif
123		123
124	__weak int fixup_cpu(void)	124	__weak int fixup_cpu(void)
125	{	125	{
126	return 0;	126	return 0;
127	}	127	}
128		128
129	static int initr_reloc_global_data(void)	129	static int initr_reloc_global_data(void)
130	{	130	{
131	#ifdef CONFIG_SYS_SYM_OFFSETS	131	#ifdef __ARM__
132	monitor_flash_len = _end_ofs;	132	monitor_flash_len = _end - __image_copy_start;
133	#elif !defined(CONFIG_SANDBOX)	133	#elif !defined(CONFIG_SANDBOX)
134	monitor_flash_len = (ulong)&__init_end - gd->relocaddr;	134	monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
135	#endif	135	#endif
136	#if defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)	136	#if defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)
137	/*	137	/*
138	* The gd->cpu pointer is set to an address in flash before relocation.	138	* The gd->cpu pointer is set to an address in flash before relocation.
139	* We need to update it to point to the same CPU entry in RAM.	139	* We need to update it to point to the same CPU entry in RAM.
140	* TODO: why not just add gd->reloc_ofs?	140	* TODO: why not just add gd->reloc_ofs?
141	*/	141	*/
142	gd->arch.cpu += gd->relocaddr - CONFIG_SYS_MONITOR_BASE;	142	gd->arch.cpu += gd->relocaddr - CONFIG_SYS_MONITOR_BASE;
143		143
144	/*	144	/*
145	* If we didn't know the cpu mask & # cores, we can save them of	145	* If we didn't know the cpu mask & # cores, we can save them of
146	* now rather than 'computing' them constantly	146	* now rather than 'computing' them constantly
147	*/	147	*/
148	fixup_cpu();	148	fixup_cpu();
149	#endif	149	#endif
150	#ifdef CONFIG_SYS_EXTRA_ENV_RELOC	150	#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
151	/*	151	/*
152	* Some systems need to relocate the env_addr pointer early because the	152	* Some systems need to relocate the env_addr pointer early because the
153	* location it points to will get invalidated before env_relocate is	153	* location it points to will get invalidated before env_relocate is
154	* called. One example is on systems that might use a L2 or L3 cache	154	* called. One example is on systems that might use a L2 or L3 cache
155	* in SRAM mode and initialize that cache from SRAM mode back to being	155	* in SRAM mode and initialize that cache from SRAM mode back to being
156	* a cache in cpu_init_r.	156	* a cache in cpu_init_r.
157	*/	157	*/
158	gd->env_addr += gd->relocaddr - CONFIG_SYS_MONITOR_BASE;	158	gd->env_addr += gd->relocaddr - CONFIG_SYS_MONITOR_BASE;
159	#endif	159	#endif
160	return 0;	160	return 0;
161	}	161	}
162		162
163	static int initr_serial(void)	163	static int initr_serial(void)
164	{	164	{
165	serial_initialize();	165	serial_initialize();
166	return 0;	166	return 0;
167	}	167	}
168		168
169	#ifdef CONFIG_PPC	169	#ifdef CONFIG_PPC
170	static int initr_trap(void)	170	static int initr_trap(void)
171	{	171	{
172	/*	172	/*
173	* Setup trap handlers	173	* Setup trap handlers
174	*/	174	*/
175	trap_init(gd->relocaddr);	175	trap_init(gd->relocaddr);
176		176
177	return 0;	177	return 0;
178	}	178	}
179	#endif	179	#endif
180		180
181	#ifdef CONFIG_ADDR_MAP	181	#ifdef CONFIG_ADDR_MAP
182	static int initr_addr_map(void)	182	static int initr_addr_map(void)
183	{	183	{
184	init_addr_map();	184	init_addr_map();
185		185
186	return 0;	186	return 0;
187	}	187	}
188	#endif	188	#endif
189		189
190	#ifdef CONFIG_LOGBUFFER	190	#ifdef CONFIG_LOGBUFFER
191	unsigned long logbuffer_base(void)	191	unsigned long logbuffer_base(void)
192	{	192	{
193	return gd->ram_top - LOGBUFF_LEN;	193	return gd->ram_top - LOGBUFF_LEN;
194	}	194	}
195		195
196	static int initr_logbuffer(void)	196	static int initr_logbuffer(void)
197	{	197	{
198	logbuff_init_ptrs();	198	logbuff_init_ptrs();
199	return 0;	199	return 0;
200	}	200	}
201	#endif	201	#endif
202		202
203	#ifdef CONFIG_POST	203	#ifdef CONFIG_POST
204	static int initr_post_backlog(void)	204	static int initr_post_backlog(void)
205	{	205	{
206	post_output_backlog();	206	post_output_backlog();
207	return 0;	207	return 0;
208	}	208	}
209	#endif	209	#endif
210		210
211	#ifdef CONFIG_SYS_DELAYED_ICACHE	211	#ifdef CONFIG_SYS_DELAYED_ICACHE
212	static int initr_icache_enable(void)	212	static int initr_icache_enable(void)
213	{	213	{
214	return 0;	214	return 0;
215	}	215	}
216	#endif	216	#endif
217		217
218	#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)	218	#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
219	static int initr_unlock_ram_in_cache(void)	219	static int initr_unlock_ram_in_cache(void)
220	{	220	{
221	unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */	221	unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
222	return 0;	222	return 0;
223	}	223	}
224	#endif	224	#endif
225		225
226	#ifdef CONFIG_PCI	226	#ifdef CONFIG_PCI
227	static int initr_pci(void)	227	static int initr_pci(void)
228	{	228	{
229	pci_init();	229	pci_init();
230		230
231	return 0;	231	return 0;
232	}	232	}
233	#endif	233	#endif
234		234
235	#ifdef CONFIG_WINBOND_83C553	235	#ifdef CONFIG_WINBOND_83C553
236	static int initr_w83c553f(void)	236	static int initr_w83c553f(void)
237	{	237	{
238	/*	238	/*
239	* Initialise the ISA bridge	239	* Initialise the ISA bridge
240	*/	240	*/
241	initialise_w83c553f();	241	initialise_w83c553f();
242	return 0;	242	return 0;
243	}	243	}
244	#endif	244	#endif
245		245
246	static int initr_barrier(void)	246	static int initr_barrier(void)
247	{	247	{
248	#ifdef CONFIG_PPC	248	#ifdef CONFIG_PPC
249	/* TODO: Can we not use dmb() macros for this? */	249	/* TODO: Can we not use dmb() macros for this? */
250	asm("sync ; isync");	250	asm("sync ; isync");
251	#endif	251	#endif
252	return 0;	252	return 0;
253	}	253	}
254		254
255	static int initr_malloc(void)	255	static int initr_malloc(void)
256	{	256	{
257	ulong malloc_start;	257	ulong malloc_start;
258		258
259	/* The malloc area is immediately below the monitor copy in DRAM */	259	/* The malloc area is immediately below the monitor copy in DRAM */
260	malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN;	260	malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN;
261	mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),	261	mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),
262	TOTAL_MALLOC_LEN);	262	TOTAL_MALLOC_LEN);
263	return 0;	263	return 0;
264	}	264	}
265		265
266	__weak int power_init_board(void)	266	__weak int power_init_board(void)
267	{	267	{
268	return 0;	268	return 0;
269	}	269	}
270		270
271	static int initr_announce(void)	271	static int initr_announce(void)
272	{	272	{
273	debug("Now running in RAM - U-Boot at: %08lx\n", gd->relocaddr);	273	debug("Now running in RAM - U-Boot at: %08lx\n", gd->relocaddr);
274	return 0;	274	return 0;
275	}	275	}
276		276
277	#if !defined(CONFIG_SYS_NO_FLASH)	277	#if !defined(CONFIG_SYS_NO_FLASH)
278	static int initr_flash(void)	278	static int initr_flash(void)
279	{	279	{
280	ulong flash_size = 0;	280	ulong flash_size = 0;
281	bd_t *bd = gd->bd;	281	bd_t *bd = gd->bd;
282	int ok;	282	int ok;
283		283
284	puts("Flash: ");	284	puts("Flash: ");
285		285
286	if (board_flash_wp_on()) {	286	if (board_flash_wp_on()) {
287	printf("Uninitialized - Write Protect On\n");	287	printf("Uninitialized - Write Protect On\n");
288	/* Since WP is on, we can't find real size. Set to 0 */	288	/* Since WP is on, we can't find real size. Set to 0 */
289	ok = 1;	289	ok = 1;
290	} else {	290	} else {
291	flash_size = flash_init();	291	flash_size = flash_init();
292	ok = flash_size > 0;	292	ok = flash_size > 0;
293	}	293	}
294	if (!ok) {	294	if (!ok) {
295	puts("* failed *\n");	295	puts("* failed *\n");
296	#ifdef CONFIG_PPC	296	#ifdef CONFIG_PPC
297	/* Why does PPC do this? */	297	/* Why does PPC do this? */
298	hang();	298	hang();
299	#endif	299	#endif
300	return -1;	300	return -1;
301	}	301	}
302	print_size(flash_size, "");	302	print_size(flash_size, "");
303	#ifdef CONFIG_SYS_FLASH_CHECKSUM	303	#ifdef CONFIG_SYS_FLASH_CHECKSUM
304	/*	304	/*
305	* Compute and print flash CRC if flashchecksum is set to 'y'	305	* Compute and print flash CRC if flashchecksum is set to 'y'
306	*	306	*
307	* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX	307	* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
308	*/	308	*/
309	if (getenv_yesno("flashchecksum") == 1) {	309	if (getenv_yesno("flashchecksum") == 1) {
310	printf(" CRC: %08X", crc32(0,	310	printf(" CRC: %08X", crc32(0,
311	(const unsigned char *) CONFIG_SYS_FLASH_BASE,	311	(const unsigned char *) CONFIG_SYS_FLASH_BASE,
312	flash_size));	312	flash_size));
313	}	313	}
314	#endif /* CONFIG_SYS_FLASH_CHECKSUM */	314	#endif /* CONFIG_SYS_FLASH_CHECKSUM */
315	putc('\n');	315	putc('\n');
316		316
317	/* update start of FLASH memory */	317	/* update start of FLASH memory */
318	#ifdef CONFIG_SYS_FLASH_BASE	318	#ifdef CONFIG_SYS_FLASH_BASE
319	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;	319	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
320	#endif	320	#endif
321	/* size of FLASH memory (final value) */	321	/* size of FLASH memory (final value) */
322	bd->bi_flashsize = flash_size;	322	bd->bi_flashsize = flash_size;
323		323
324	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)	324	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
325	/* Make a update of the Memctrl. */	325	/* Make a update of the Memctrl. */
326	update_flash_size(flash_size);	326	update_flash_size(flash_size);
327	#endif	327	#endif
328		328
329		329
330	#if defined(CONFIG_OXC) \|\| defined(CONFIG_RMU)	330	#if defined(CONFIG_OXC) \|\| defined(CONFIG_RMU)
331	/* flash mapped at end of memory map */	331	/* flash mapped at end of memory map */
332	bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;	332	bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
333	#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE	333	#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
334	bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */	334	bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */
335	#endif	335	#endif
336	return 0;	336	return 0;
337	}	337	}
338	#endif	338	#endif
339		339
340	#ifdef CONFIG_PPC	340	#ifdef CONFIG_PPC
341	static int initr_spi(void)	341	static int initr_spi(void)
342	{	342	{
343	/* PPC does this here */	343	/* PPC does this here */
344	#ifdef CONFIG_SPI	344	#ifdef CONFIG_SPI
345	#if !defined(CONFIG_ENV_IS_IN_EEPROM)	345	#if !defined(CONFIG_ENV_IS_IN_EEPROM)
346	spi_init_f();	346	spi_init_f();
347	#endif	347	#endif
348	spi_init_r();	348	spi_init_r();
349	#endif	349	#endif
350	return 0;	350	return 0;
351	}	351	}
352	#endif	352	#endif
353		353
354	#ifdef CONFIG_CMD_NAND	354	#ifdef CONFIG_CMD_NAND
355	/* go init the NAND */	355	/* go init the NAND */
356	int initr_nand(void)	356	int initr_nand(void)
357	{	357	{
358	puts("NAND: ");	358	puts("NAND: ");
359	nand_init();	359	nand_init();
360	return 0;	360	return 0;
361	}	361	}
362	#endif	362	#endif
363		363
364	#if defined(CONFIG_CMD_ONENAND)	364	#if defined(CONFIG_CMD_ONENAND)
365	/* go init the NAND */	365	/* go init the NAND */
366	int initr_onenand(void)	366	int initr_onenand(void)
367	{	367	{
368	puts("NAND: ");	368	puts("NAND: ");
369	onenand_init();	369	onenand_init();
370	return 0;	370	return 0;
371	}	371	}
372	#endif	372	#endif
373		373
374	#ifdef CONFIG_GENERIC_MMC	374	#ifdef CONFIG_GENERIC_MMC
375	int initr_mmc(void)	375	int initr_mmc(void)
376	{	376	{
377	puts("MMC: ");	377	puts("MMC: ");
378	mmc_initialize(gd->bd);	378	mmc_initialize(gd->bd);
379	return 0;	379	return 0;
380	}	380	}
381	#endif	381	#endif
382		382
383	#ifdef CONFIG_HAS_DATAFLASH	383	#ifdef CONFIG_HAS_DATAFLASH
384	int initr_dataflash(void)	384	int initr_dataflash(void)
385	{	385	{
386	AT91F_DataflashInit();	386	AT91F_DataflashInit();
387	dataflash_print_info();	387	dataflash_print_info();
388	return 0;	388	return 0;
389	}	389	}
390	#endif	390	#endif
391		391
392	/*	392	/*
393	* Tell if it's OK to load the environment early in boot.	393	* Tell if it's OK to load the environment early in boot.
394	*	394	*
395	* If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see	395	* If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
396	* if this is OK (defaulting to saying it's OK).	396	* if this is OK (defaulting to saying it's OK).
397	*	397	*
398	* NOTE: Loading the environment early can be a bad idea if security is	398	* NOTE: Loading the environment early can be a bad idea if security is
399	* important, since no verification is done on the environment.	399	* important, since no verification is done on the environment.
400	*	400	*
401	* @return 0 if environment should not be loaded, !=0 if it is ok to load	401	* @return 0 if environment should not be loaded, !=0 if it is ok to load
402	*/	402	*/
403	static int should_load_env(void)	403	static int should_load_env(void)
404	{	404	{
405	#ifdef CONFIG_OF_CONTROL	405	#ifdef CONFIG_OF_CONTROL
406	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);	406	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
407	#elif defined CONFIG_DELAY_ENVIRONMENT	407	#elif defined CONFIG_DELAY_ENVIRONMENT
408	return 0;	408	return 0;
409	#else	409	#else
410	return 1;	410	return 1;
411	#endif	411	#endif
412	}	412	}
413		413
414	static int initr_env(void)	414	static int initr_env(void)
415	{	415	{
416	/* initialize environment */	416	/* initialize environment */
417	if (should_load_env())	417	if (should_load_env())
418	env_relocate();	418	env_relocate();
419	else	419	else
420	set_default_env(NULL);	420	set_default_env(NULL);
421		421
422	/* Initialize from environment */	422	/* Initialize from environment */
423	load_addr = getenv_ulong("loadaddr", 16, load_addr);	423	load_addr = getenv_ulong("loadaddr", 16, load_addr);
424	#if defined(CONFIG_SYS_EXTBDINFO)	424	#if defined(CONFIG_SYS_EXTBDINFO)
425	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)	425	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)
426	#if defined(CONFIG_I2CFAST)	426	#if defined(CONFIG_I2CFAST)
427	/*	427	/*
428	* set bi_iic_fast for linux taking environment variable	428	* set bi_iic_fast for linux taking environment variable
429	* "i2cfast" into account	429	* "i2cfast" into account
430	*/	430	*/
431	{	431	{
432	char *s = getenv("i2cfast");	432	char *s = getenv("i2cfast");
433		433
434	if (s && ((s == 'y') \|\| (s == 'Y'))) {	434	if (s && ((s == 'y') \|\| (s == 'Y'))) {
435	gd->bd->bi_iic_fast[0] = 1;	435	gd->bd->bi_iic_fast[0] = 1;
436	gd->bd->bi_iic_fast[1] = 1;	436	gd->bd->bi_iic_fast[1] = 1;
437	}	437	}
438	}	438	}
439	#endif /* CONFIG_I2CFAST */	439	#endif /* CONFIG_I2CFAST */
440	#endif /* CONFIG_405GP, CONFIG_405EP */	440	#endif /* CONFIG_405GP, CONFIG_405EP */
441	#endif /* CONFIG_SYS_EXTBDINFO */	441	#endif /* CONFIG_SYS_EXTBDINFO */
442	return 0;	442	return 0;
443	}	443	}
444		444
445	#ifdef CONFIG_HERMES	445	#ifdef CONFIG_HERMES
446	static int initr_hermes(void)	446	static int initr_hermes(void)
447	{	447	{
448	if ((gd->board_type >> 16) == 2)	448	if ((gd->board_type >> 16) == 2)
449	gd->bd->bi_ethspeed = gd->board_type & 0xFFFF;	449	gd->bd->bi_ethspeed = gd->board_type & 0xFFFF;
450	else	450	else
451	gd->bd->bi_ethspeed = 0xFFFF;	451	gd->bd->bi_ethspeed = 0xFFFF;
452	return 0;	452	return 0;
453	}	453	}
454		454
455	static int initr_hermes_start(void)	455	static int initr_hermes_start(void)
456	{	456	{
457	if (gd->bd->bi_ethspeed != 0xFFFF)	457	if (gd->bd->bi_ethspeed != 0xFFFF)
458	hermes_start_lxt980((int) gd->bd->bi_ethspeed);	458	hermes_start_lxt980((int) gd->bd->bi_ethspeed);
459	return 0;	459	return 0;
460	}	460	}
461	#endif	461	#endif
462		462
463	#ifdef CONFIG_SC3	463	#ifdef CONFIG_SC3
464	/* TODO: with new initcalls, move this into the driver */	464	/* TODO: with new initcalls, move this into the driver */
465	extern void sc3_read_eeprom(void);	465	extern void sc3_read_eeprom(void);
466		466
467	static int initr_sc3_read_eeprom(void)	467	static int initr_sc3_read_eeprom(void)
468	{	468	{
469	sc3_read_eeprom();	469	sc3_read_eeprom();
470	return 0;	470	return 0;
471	}	471	}
472	#endif	472	#endif
473		473
474	static int initr_jumptable(void)	474	static int initr_jumptable(void)
475	{	475	{
476	jumptable_init();	476	jumptable_init();
477	return 0;	477	return 0;
478	}	478	}
479		479
480	#if defined(CONFIG_API)	480	#if defined(CONFIG_API)
481	static int initr_api(void)	481	static int initr_api(void)
482	{	482	{
483	/* Initialize API */	483	/* Initialize API */
484	api_init();	484	api_init();
485	return 0;	485	return 0;
486	}	486	}
487	#endif	487	#endif
488		488
489	#ifdef CONFIG_DISPLAY_BOARDINFO_LATE	489	#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
490	static int show_model_r(void)	490	static int show_model_r(void)
491	{	491	{
492	/* Put this here so it appears on the LCD, now it is ready */	492	/* Put this here so it appears on the LCD, now it is ready */
493	# ifdef CONFIG_OF_CONTROL	493	# ifdef CONFIG_OF_CONTROL
494	const char *model;	494	const char *model;
495		495
496	model = (char *)fdt_getprop(gd->fdt_blob, 0, "model", NULL);	496	model = (char *)fdt_getprop(gd->fdt_blob, 0, "model", NULL);
497	printf("Model: %s\n", model ? model : "<unknown>");	497	printf("Model: %s\n", model ? model : "<unknown>");
498	# else	498	# else
499	checkboard();	499	checkboard();
500	# endif	500	# endif
501	}	501	}
502	#endif	502	#endif
503		503
504	/* enable exceptions */	504	/* enable exceptions */
505	#ifdef CONFIG_ARM	505	#ifdef CONFIG_ARM
506	static int initr_enable_interrupts(void)	506	static int initr_enable_interrupts(void)
507	{	507	{
508	enable_interrupts();	508	enable_interrupts();
509	return 0;	509	return 0;
510	}	510	}
511	#endif	511	#endif
512		512
513	#ifdef CONFIG_CMD_NET	513	#ifdef CONFIG_CMD_NET
514	static int initr_ethaddr(void)	514	static int initr_ethaddr(void)
515	{	515	{
516	bd_t *bd = gd->bd;	516	bd_t *bd = gd->bd;
517		517
518	/* kept around for legacy kernels only ... ignore the next section */	518	/* kept around for legacy kernels only ... ignore the next section */
519	eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);	519	eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
520	#ifdef CONFIG_HAS_ETH1	520	#ifdef CONFIG_HAS_ETH1
521	eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);	521	eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
522	#endif	522	#endif
523	#ifdef CONFIG_HAS_ETH2	523	#ifdef CONFIG_HAS_ETH2
524	eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);	524	eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
525	#endif	525	#endif
526	#ifdef CONFIG_HAS_ETH3	526	#ifdef CONFIG_HAS_ETH3
527	eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);	527	eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
528	#endif	528	#endif
529	#ifdef CONFIG_HAS_ETH4	529	#ifdef CONFIG_HAS_ETH4
530	eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);	530	eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
531	#endif	531	#endif
532	#ifdef CONFIG_HAS_ETH5	532	#ifdef CONFIG_HAS_ETH5
533	eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);	533	eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
534	#endif	534	#endif
535	return 0;	535	return 0;
536	}	536	}
537	#endif /* CONFIG_CMD_NET */	537	#endif /* CONFIG_CMD_NET */
538		538
539	#ifdef CONFIG_CMD_KGDB	539	#ifdef CONFIG_CMD_KGDB
540	static int initr_kgdb(void)	540	static int initr_kgdb(void)
541	{	541	{
542	puts("KGDB: ");	542	puts("KGDB: ");
543	kgdb_init();	543	kgdb_init();
544	return 0;	544	return 0;
545	}	545	}
546	#endif	546	#endif
547		547
548	#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)	548	#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
549	static int initr_status_led(void)	549	static int initr_status_led(void)
550	{	550	{
551	status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);	551	status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
552		552
553	return 0;	553	return 0;
554	}	554	}
555	#endif	555	#endif
556		556
557	#if defined(CONFIG_CMD_SCSI)	557	#if defined(CONFIG_CMD_SCSI)
558	static int initr_scsi(void)	558	static int initr_scsi(void)
559	{	559	{
560	/* Not supported properly on ARM yet */	560	/* Not supported properly on ARM yet */
561	#ifndef CONFIG_ARM	561	#ifndef CONFIG_ARM
562	puts("SCSI: ");	562	puts("SCSI: ");
563	scsi_init();	563	scsi_init();
564	#endif	564	#endif
565		565
566	return 0;	566	return 0;
567	}	567	}
568	#endif /* CONFIG_CMD_NET */	568	#endif /* CONFIG_CMD_NET */
569		569
570	#if defined(CONFIG_CMD_DOC)	570	#if defined(CONFIG_CMD_DOC)
571	static int initr_doc(void)	571	static int initr_doc(void)
572	{	572	{
573	puts("DOC: ");	573	puts("DOC: ");
574	doc_init();	574	doc_init();
575	}	575	}
576	#endif	576	#endif
577		577
578	#ifdef CONFIG_BITBANGMII	578	#ifdef CONFIG_BITBANGMII
579	static int initr_bbmii(void)	579	static int initr_bbmii(void)
580	{	580	{
581	bb_miiphy_init();	581	bb_miiphy_init();
582	return 0;	582	return 0;
583	}	583	}
584	#endif	584	#endif
585		585
586	#ifdef CONFIG_CMD_NET	586	#ifdef CONFIG_CMD_NET
587	static int initr_net(void)	587	static int initr_net(void)
588	{	588	{
589	puts("Net: ");	589	puts("Net: ");
590	eth_initialize(gd->bd);	590	eth_initialize(gd->bd);
591	#if defined(CONFIG_RESET_PHY_R)	591	#if defined(CONFIG_RESET_PHY_R)
592	debug("Reset Ethernet PHY\n");	592	debug("Reset Ethernet PHY\n");
593	reset_phy();	593	reset_phy();
594	#endif	594	#endif
595	return 0;	595	return 0;
596	}	596	}
597	#endif	597	#endif
598		598
599	#ifdef CONFIG_POST	599	#ifdef CONFIG_POST
600	static int initr_post(void)	600	static int initr_post(void)
601	{	601	{
602	post_run(NULL, POST_RAM \| post_bootmode_get(0));	602	post_run(NULL, POST_RAM \| post_bootmode_get(0));
603	return 0;	603	return 0;
604	}	604	}
605	#endif	605	#endif
606		606
607	#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)	607	#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
608	static int initr_pcmcia(void)	608	static int initr_pcmcia(void)
609	{	609	{
610	puts("PCMCIA:");	610	puts("PCMCIA:");
611	pcmcia_init();	611	pcmcia_init();
612	return 0;	612	return 0;
613	}	613	}
614	#endif	614	#endif
615		615
616	#if defined(CONFIG_CMD_IDE)	616	#if defined(CONFIG_CMD_IDE)
617	static int initr_ide(void)	617	static int initr_ide(void)
618	{	618	{
619	#ifdef CONFIG_IDE_8xx_PCCARD	619	#ifdef CONFIG_IDE_8xx_PCCARD
620	puts("PCMCIA:");	620	puts("PCMCIA:");
621	#else	621	#else
622	puts("IDE: ");	622	puts("IDE: ");
623	#endif	623	#endif
624	#if defined(CONFIG_START_IDE)	624	#if defined(CONFIG_START_IDE)
625	if (board_start_ide())	625	if (board_start_ide())
626	ide_init();	626	ide_init();
627	#else	627	#else
628	ide_init();	628	ide_init();
629	#endif	629	#endif
630	return 0;	630	return 0;
631	}	631	}
632	#endif	632	#endif
633		633
634	#if defined(CONFIG_PRAM) \|\| defined(CONFIG_LOGBUFFER)	634	#if defined(CONFIG_PRAM) \|\| defined(CONFIG_LOGBUFFER)
635	/*	635	/*
636	* Export available size of memory for Linux, taking into account the	636	* Export available size of memory for Linux, taking into account the
637	* protected RAM at top of memory	637	* protected RAM at top of memory
638	*/	638	*/
639	int initr_mem(void)	639	int initr_mem(void)
640	{	640	{
641	ulong pram = 0;	641	ulong pram = 0;
642	char memsz[32];	642	char memsz[32];
643		643
644	# ifdef CONFIG_PRAM	644	# ifdef CONFIG_PRAM
645	pram = getenv_ulong("pram", 10, CONFIG_PRAM);	645	pram = getenv_ulong("pram", 10, CONFIG_PRAM);
646	# endif	646	# endif
647	# if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)	647	# if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
648	/* Also take the logbuffer into account (pram is in kB) */	648	/* Also take the logbuffer into account (pram is in kB) */
649	pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;	649	pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
650	# endif	650	# endif
651	sprintf(memsz, "%ldk", (gd->ram_size / 1024) - pram);	651	sprintf(memsz, "%ldk", (gd->ram_size / 1024) - pram);
652	setenv("mem", memsz);	652	setenv("mem", memsz);
653		653
654	return 0;	654	return 0;
655	}	655	}
656	#endif	656	#endif
657		657
658	#ifdef CONFIG_CMD_BEDBUG	658	#ifdef CONFIG_CMD_BEDBUG
659	static int initr_bedbug(void)	659	static int initr_bedbug(void)
660	{	660	{
661	bedbug_init();	661	bedbug_init();
662		662
663	return 0;	663	return 0;
664	}	664	}
665	#endif	665	#endif
666		666
667	#ifdef CONFIG_PS2KBD	667	#ifdef CONFIG_PS2KBD
668	static int initr_kbd(void)	668	static int initr_kbd(void)
669	{	669	{
670	puts("PS/2: ");	670	puts("PS/2: ");
671	kbd_init();	671	kbd_init();
672	return 0;	672	return 0;
673	}	673	}
674	#endif	674	#endif
675		675
676	#ifdef CONFIG_MODEM_SUPPORT	676	#ifdef CONFIG_MODEM_SUPPORT
677	static int initr_modem(void)	677	static int initr_modem(void)
678	{	678	{
679	/* TODO: with new initcalls, move this into the driver */	679	/* TODO: with new initcalls, move this into the driver */
680	extern int do_mdm_init;	680	extern int do_mdm_init;
681		681
682	do_mdm_init = gd->do_mdm_init;	682	do_mdm_init = gd->do_mdm_init;
683	return 0;	683	return 0;
684	}	684	}
685	#endif	685	#endif
686		686
687	static int run_main_loop(void)	687	static int run_main_loop(void)
688	{	688	{
689	#ifdef CONFIG_SANDBOX	689	#ifdef CONFIG_SANDBOX
690	sandbox_main_loop_init();	690	sandbox_main_loop_init();
691	#endif	691	#endif
692	/* main_loop() can return to retry autoboot, if so just run it again */	692	/* main_loop() can return to retry autoboot, if so just run it again */
693	for (;;)	693	for (;;)
694	main_loop();	694	main_loop();
695	return 0;	695	return 0;
696	}	696	}
697		697
698	/*	698	/*
699	* Over time we hope to remove these functions with code fragments and	699	* Over time we hope to remove these functions with code fragments and
700	* stub funtcions, and instead call the relevant function directly.	700	* stub funtcions, and instead call the relevant function directly.
701	*	701	*
702	* We also hope to remove most of the driver-related init and do it if/when	702	* We also hope to remove most of the driver-related init and do it if/when
703	* the driver is later used.	703	* the driver is later used.
704	*	704	*
705	* TODO: perhaps reset the watchdog in the initcall function after each call?	705	* TODO: perhaps reset the watchdog in the initcall function after each call?
706	*/	706	*/
707	init_fnc_t init_sequence_r[] = {	707	init_fnc_t init_sequence_r[] = {
708	initr_trace,	708	initr_trace,
709	initr_reloc,	709	initr_reloc,
710	/* TODO: could x86/PPC have this also perhaps? */	710	/* TODO: could x86/PPC have this also perhaps? */
711	#ifdef CONFIG_ARM	711	#ifdef CONFIG_ARM
712	initr_caches,	712	initr_caches,
713	board_init, /* Setup chipselects */	713	board_init, /* Setup chipselects */
714	#endif	714	#endif
715	/*	715	/*
716	* TODO: printing of the clock inforamtion of the board is now	716	* TODO: printing of the clock inforamtion of the board is now
717	* implemented as part of bdinfo command. Currently only support for	717	* implemented as part of bdinfo command. Currently only support for
718	* davinci SOC's is added. Remove this check once all the board	718	* davinci SOC's is added. Remove this check once all the board
719	* implement this.	719	* implement this.
720	*/	720	*/
721	#ifdef CONFIG_CLOCKS	721	#ifdef CONFIG_CLOCKS
722	set_cpu_clk_info, /* Setup clock information */	722	set_cpu_clk_info, /* Setup clock information */
723	#endif	723	#endif
724	initr_reloc_global_data,	724	initr_reloc_global_data,
725	initr_serial,	725	initr_serial,
726	initr_announce,	726	initr_announce,
727	INIT_FUNC_WATCHDOG_RESET	727	INIT_FUNC_WATCHDOG_RESET
728	#ifdef CONFIG_PPC	728	#ifdef CONFIG_PPC
729	initr_trap,	729	initr_trap,
730	#endif	730	#endif
731	#ifdef CONFIG_ADDR_MAP	731	#ifdef CONFIG_ADDR_MAP
732	initr_addr_map,	732	initr_addr_map,
733	#endif	733	#endif
734	#if defined(CONFIG_BOARD_EARLY_INIT_R)	734	#if defined(CONFIG_BOARD_EARLY_INIT_R)
735	board_early_init_r,	735	board_early_init_r,
736	#endif	736	#endif
737	INIT_FUNC_WATCHDOG_RESET	737	INIT_FUNC_WATCHDOG_RESET
738	#ifdef CONFIG_LOGBUFFER	738	#ifdef CONFIG_LOGBUFFER
739	initr_logbuffer,	739	initr_logbuffer,
740	#endif	740	#endif
741	#ifdef CONFIG_POST	741	#ifdef CONFIG_POST
742	initr_post_backlog,	742	initr_post_backlog,
743	#endif	743	#endif
744	INIT_FUNC_WATCHDOG_RESET	744	INIT_FUNC_WATCHDOG_RESET
745	#ifdef CONFIG_SYS_DELAYED_ICACHE	745	#ifdef CONFIG_SYS_DELAYED_ICACHE
746	initr_icache_enable,	746	initr_icache_enable,
747	#endif	747	#endif
748	#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)	748	#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
749	initr_unlock_ram_in_cache,	749	initr_unlock_ram_in_cache,
750	#endif	750	#endif
751	#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)	751	#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
752	/*	752	/*
753	* Do early PCI configuration _before_ the flash gets initialised,	753	* Do early PCI configuration _before_ the flash gets initialised,
754	* because PCU ressources are crucial for flash access on some boards.	754	* because PCU ressources are crucial for flash access on some boards.
755	*/	755	*/
756	initr_pci,	756	initr_pci,
757	#endif	757	#endif
758	#ifdef CONFIG_WINBOND_83C553	758	#ifdef CONFIG_WINBOND_83C553
759	initr_w83c553f,	759	initr_w83c553f,
760	#endif	760	#endif
761	initr_barrier,	761	initr_barrier,
762	initr_malloc,	762	initr_malloc,
763	bootstage_relocate,	763	bootstage_relocate,
764	#ifdef CONFIG_ARCH_EARLY_INIT_R	764	#ifdef CONFIG_ARCH_EARLY_INIT_R
765	arch_early_init_r,	765	arch_early_init_r,
766	#endif	766	#endif
767	power_init_board,	767	power_init_board,
768	#ifndef CONFIG_SYS_NO_FLASH	768	#ifndef CONFIG_SYS_NO_FLASH
769	initr_flash,	769	initr_flash,
770	#endif	770	#endif
771	INIT_FUNC_WATCHDOG_RESET	771	INIT_FUNC_WATCHDOG_RESET
772	#if defined(CONFIG_PPC) \|\| defined(CONFIG_X86)	772	#if defined(CONFIG_PPC) \|\| defined(CONFIG_X86)
773	/* initialize higher level parts of CPU like time base and timers */	773	/* initialize higher level parts of CPU like time base and timers */
774	cpu_init_r,	774	cpu_init_r,
775	#endif	775	#endif
776	#ifdef CONFIG_PPC	776	#ifdef CONFIG_PPC
777	initr_spi,	777	initr_spi,
778	#endif	778	#endif
779	#if defined(CONFIG_X86) && defined(CONFIG_SPI)	779	#if defined(CONFIG_X86) && defined(CONFIG_SPI)
780	init_func_spi,	780	init_func_spi,
781	#endif	781	#endif
782	#ifdef CONFIG_CMD_NAND	782	#ifdef CONFIG_CMD_NAND
783	initr_nand,	783	initr_nand,
784	#endif	784	#endif
785	#ifdef CONFIG_CMD_ONENAND	785	#ifdef CONFIG_CMD_ONENAND
786	initr_onenand,	786	initr_onenand,
787	#endif	787	#endif
788	#ifdef CONFIG_GENERIC_MMC	788	#ifdef CONFIG_GENERIC_MMC
789	initr_mmc,	789	initr_mmc,
790	#endif	790	#endif
791	#ifdef CONFIG_HAS_DATAFLASH	791	#ifdef CONFIG_HAS_DATAFLASH
792	initr_dataflash,	792	initr_dataflash,
793	#endif	793	#endif
794	initr_env,	794	initr_env,
795	INIT_FUNC_WATCHDOG_RESET	795	INIT_FUNC_WATCHDOG_RESET
796	initr_secondary_cpu,	796	initr_secondary_cpu,
797	#ifdef CONFIG_SC3	797	#ifdef CONFIG_SC3
798	initr_sc3_read_eeprom,	798	initr_sc3_read_eeprom,
799	#endif	799	#endif
800	#ifdef CONFIG_HERMES	800	#ifdef CONFIG_HERMES
801	initr_hermes,	801	initr_hermes,
802	#endif	802	#endif
803	#if defined(CONFIG_ID_EEPROM) \|\| defined(CONFIG_SYS_I2C_MAC_OFFSET)	803	#if defined(CONFIG_ID_EEPROM) \|\| defined(CONFIG_SYS_I2C_MAC_OFFSET)
804	mac_read_from_eeprom,	804	mac_read_from_eeprom,
805	#endif	805	#endif
806	INIT_FUNC_WATCHDOG_RESET	806	INIT_FUNC_WATCHDOG_RESET
807	#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)	807	#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
808	/*	808	/*
809	* Do pci configuration	809	* Do pci configuration
810	*/	810	*/
811	initr_pci,	811	initr_pci,
812	#endif	812	#endif
813	stdio_init,	813	stdio_init,
814	initr_jumptable,	814	initr_jumptable,
815	#ifdef CONFIG_API	815	#ifdef CONFIG_API
816	initr_api,	816	initr_api,
817	#endif	817	#endif
818	console_init_r, /* fully init console as a device */	818	console_init_r, /* fully init console as a device */
819	#ifdef CONFIG_DISPLAY_BOARDINFO_LATE	819	#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
820	show_model_r,	820	show_model_r,
821	#endif	821	#endif
822	#ifdef CONFIG_ARCH_MISC_INIT	822	#ifdef CONFIG_ARCH_MISC_INIT
823	arch_misc_init, /* miscellaneous arch-dependent init */	823	arch_misc_init, /* miscellaneous arch-dependent init */
824	#endif	824	#endif
825	#ifdef CONFIG_MISC_INIT_R	825	#ifdef CONFIG_MISC_INIT_R
826	misc_init_r, /* miscellaneous platform-dependent init */	826	misc_init_r, /* miscellaneous platform-dependent init */
827	#endif	827	#endif
828	#ifdef CONFIG_HERMES	828	#ifdef CONFIG_HERMES
829	initr_hermes_start,	829	initr_hermes_start,
830	#endif	830	#endif
831	INIT_FUNC_WATCHDOG_RESET	831	INIT_FUNC_WATCHDOG_RESET
832	#ifdef CONFIG_CMD_KGDB	832	#ifdef CONFIG_CMD_KGDB
833	initr_kgdb,	833	initr_kgdb,
834	#endif	834	#endif
835	#ifdef CONFIG_X86	835	#ifdef CONFIG_X86
836	board_early_init_r,	836	board_early_init_r,
837	#endif	837	#endif
838	interrupt_init,	838	interrupt_init,
839	#if defined(CONFIG_ARM) \|\| defined(CONFIG_x86)	839	#if defined(CONFIG_ARM) \|\| defined(CONFIG_x86)
840	initr_enable_interrupts,	840	initr_enable_interrupts,
841	#endif	841	#endif
842	#ifdef CONFIG_X86	842	#ifdef CONFIG_X86
843	timer_init, /* initialize timer */	843	timer_init, /* initialize timer */
844	#endif	844	#endif
845	#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)	845	#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
846	initr_status_led,	846	initr_status_led,
847	#endif	847	#endif
848	/* PPC has a udelay(20) here dating from 2002. Why? */	848	/* PPC has a udelay(20) here dating from 2002. Why? */
849	#ifdef CONFIG_CMD_NET	849	#ifdef CONFIG_CMD_NET
850	initr_ethaddr,	850	initr_ethaddr,
851	#endif	851	#endif
852	#ifdef CONFIG_BOARD_LATE_INIT	852	#ifdef CONFIG_BOARD_LATE_INIT
853	board_late_init,	853	board_late_init,
854	#endif	854	#endif
855	#ifdef CONFIG_CMD_SCSI	855	#ifdef CONFIG_CMD_SCSI
856	INIT_FUNC_WATCHDOG_RESET	856	INIT_FUNC_WATCHDOG_RESET
857	initr_scsi,	857	initr_scsi,
858	#endif	858	#endif
859	#ifdef CONFIG_CMD_DOC	859	#ifdef CONFIG_CMD_DOC
860	INIT_FUNC_WATCHDOG_RESET	860	INIT_FUNC_WATCHDOG_RESET
861	initr_doc,	861	initr_doc,
862	#endif	862	#endif
863	#ifdef CONFIG_BITBANGMII	863	#ifdef CONFIG_BITBANGMII
864	initr_bbmii,	864	initr_bbmii,
865	#endif	865	#endif
866	#ifdef CONFIG_CMD_NET	866	#ifdef CONFIG_CMD_NET
867	INIT_FUNC_WATCHDOG_RESET	867	INIT_FUNC_WATCHDOG_RESET
868	initr_net,	868	initr_net,
869	#endif	869	#endif
870	#ifdef CONFIG_POST	870	#ifdef CONFIG_POST
871	initr_post,	871	initr_post,
872	#endif	872	#endif
873	#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)	873	#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
874	initr_pcmcia,	874	initr_pcmcia,
875	#endif	875	#endif
876	#if defined(CONFIG_CMD_IDE)	876	#if defined(CONFIG_CMD_IDE)
877	initr_ide,	877	initr_ide,
878	#endif	878	#endif
879	#ifdef CONFIG_LAST_STAGE_INIT	879	#ifdef CONFIG_LAST_STAGE_INIT
880	INIT_FUNC_WATCHDOG_RESET	880	INIT_FUNC_WATCHDOG_RESET
881	/*	881	/*
882	* Some parts can be only initialized if all others (like	882	* Some parts can be only initialized if all others (like
883	* Interrupts) are up and running (i.e. the PC-style ISA	883	* Interrupts) are up and running (i.e. the PC-style ISA
884	* keyboard).	884	* keyboard).
885	*/	885	*/
886	last_stage_init,	886	last_stage_init,
887	#endif	887	#endif
888	#ifdef CONFIG_CMD_BEDBUG	888	#ifdef CONFIG_CMD_BEDBUG
889	INIT_FUNC_WATCHDOG_RESET	889	INIT_FUNC_WATCHDOG_RESET
890	initr_bedbug,	890	initr_bedbug,
891	#endif	891	#endif
892	#if defined(CONFIG_PRAM) \|\| defined(CONFIG_LOGBUFFER)	892	#if defined(CONFIG_PRAM) \|\| defined(CONFIG_LOGBUFFER)
893	initr_mem,	893	initr_mem,
894	#endif	894	#endif
895	#ifdef CONFIG_PS2KBD	895	#ifdef CONFIG_PS2KBD
896	initr_kbd,	896	initr_kbd,
897	#endif	897	#endif
898	#ifdef CONFIG_MODEM_SUPPORT	898	#ifdef CONFIG_MODEM_SUPPORT
899	initr_modem,	899	initr_modem,
900	#endif	900	#endif
901	run_main_loop,	901	run_main_loop,
902	};	902	};
903		903
904	void board_init_r(gd_t *new_gd, ulong dest_addr)	904	void board_init_r(gd_t *new_gd, ulong dest_addr)
905	{	905	{
906	#ifdef CONFIG_NEEDS_MANUAL_RELOC	906	#ifdef CONFIG_NEEDS_MANUAL_RELOC
907	int i;	907	int i;
908	#endif	908	#endif
909		909
910	#ifndef CONFIG_X86	910	#ifndef CONFIG_X86
911	gd = new_gd;	911	gd = new_gd;
912	#endif	912	#endif
913		913
914	#ifdef CONFIG_NEEDS_MANUAL_RELOC	914	#ifdef CONFIG_NEEDS_MANUAL_RELOC
915	for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++)	915	for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++)
916	init_sequence_r[i] += gd->reloc_off;	916	init_sequence_r[i] += gd->reloc_off;
917	#endif	917	#endif
918		918
919	if (initcall_run_list(init_sequence_r))	919	if (initcall_run_list(init_sequence_r))
920	hang();	920	hang();
921		921
922	/* NOTREACHED - run_main_loop() does not return */	922	/* NOTREACHED - run_main_loop() does not return */
923	hang();	923	hang();
924	}	924	}
925		925

include/asm-generic/sections.h

Diff comments View file @ b60eff3

1	/*	1	/*
2	* Copyright (c) 2011 The Chromium OS Authors.	2	* Copyright (c) 2011 The Chromium OS Authors.
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6		6
7	/* Taken from Linux kernel, commit f56c3196 */	7	/* Taken from Linux kernel, commit f56c3196 */
8		8
9	#ifndef _ASM_GENERIC_SECTIONS_H_	9	#ifndef _ASM_GENERIC_SECTIONS_H_
10	#define _ASM_GENERIC_SECTIONS_H_	10	#define _ASM_GENERIC_SECTIONS_H_
11		11
12	/* References to section boundaries */	12	/* References to section boundaries */
13		13
14	extern char _text[], _stext[], _etext[];	14	extern char _text[], _stext[], _etext[];
15	extern char _data[], _sdata[], _edata[];	15	extern char _data[], _sdata[], _edata[];
16	extern char __bss_start[], __bss_stop[];	16	extern char __bss_start[], __bss_stop[];
17	extern char __init_begin[], __init_end[];	17	extern char __init_begin[], __init_end[];
18	extern char _sinittext[], _einittext[];	18	extern char _sinittext[], _einittext[];
19	extern char _end[], _init[];	19	extern char _end[], _init[];
20	extern char __per_cpu_load[], __per_cpu_start[], __per_cpu_end[];	20	extern char __per_cpu_load[], __per_cpu_start[], __per_cpu_end[];
21	extern char __kprobes_text_start[], __kprobes_text_end[];	21	extern char __kprobes_text_start[], __kprobes_text_end[];
22	extern char __entry_text_start[], __entry_text_end[];	22	extern char __entry_text_start[], __entry_text_end[];
23	extern char __initdata_begin[], __initdata_end[];	23	extern char __initdata_begin[], __initdata_end[];
24	extern char __start_rodata[], __end_rodata[];	24	extern char __start_rodata[], __end_rodata[];
25		25
26	/* Start and end of .ctors section - used for constructor calls. */	26	/* Start and end of .ctors section - used for constructor calls. */
27	extern char __ctors_start[], __ctors_end[];	27	extern char __ctors_start[], __ctors_end[];
28		28
29	/* function descriptor handling (if any). Override	29	/* function descriptor handling (if any). Override
30	* in asm/sections.h */	30	* in asm/sections.h */
31	#ifndef dereference_function_descriptor	31	#ifndef dereference_function_descriptor
32	#define dereference_function_descriptor(p) (p)	32	#define dereference_function_descriptor(p) (p)
33	#endif	33	#endif
34		34
35	/* random extra sections (if any). Override	35	/* random extra sections (if any). Override
36	* in asm/sections.h */	36	* in asm/sections.h */
37	#ifndef arch_is_kernel_text	37	#ifndef arch_is_kernel_text
38	static inline int arch_is_kernel_text(unsigned long addr)	38	static inline int arch_is_kernel_text(unsigned long addr)
39	{	39	{
40	return 0;	40	return 0;
41	}	41	}
42	#endif	42	#endif
43		43
44	#ifndef arch_is_kernel_data	44	#ifndef arch_is_kernel_data
45	static inline int arch_is_kernel_data(unsigned long addr)	45	static inline int arch_is_kernel_data(unsigned long addr)
46	{	46	{
47	return 0;	47	return 0;
48	}	48	}
49	#endif	49	#endif
50		50
51	/* U-Boot-specific things begin here */	51	/* U-Boot-specific things begin here */
52		52
53	/* Start of U-Boot text region */	53	/* Start of U-Boot text region */
54	extern char __text_start[];	54	extern char __text_start[];
55		55
56	/* This marks the end of the text region which must be relocated */	56	/* This marks the end of the text region which must be relocated */
57	extern char __image_copy_end[];	57	extern char __image_copy_end[];
58		58
59	/*	59	/*
60	* This is the U-Boot entry point - prior to relocation it should be same	60	* This is the U-Boot entry point - prior to relocation it should be same
61	* as __text_start	61	* as __text_start
62	*/	62	*/
63	extern void _start(void);	63	extern void _start(void);
64		64
65	/*	65	/*
66	* ARM needs to use offsets for symbols, since the values of some symbols	66	* ARM defines its symbols as char[]. Other arches define them as ulongs.
67	* are not resolved prior to relocation (and are just 0). Maybe this can be
68	* resolved, or maybe other architectures are similar, iwc this should be
69	* promoted to an architecture option.
70	*/	67	*/
71	#ifdef CONFIG_ARM	68	#ifdef CONFIG_ARM
72	#define CONFIG_SYS_SYM_OFFSETS
73	#endif
74		69
75	#ifdef CONFIG_SYS_SYM_OFFSETS	70	extern char __bss_start[];
76	/* Start/end of the relocation entries, as an offset from _start */	71	extern char __bss_end[];
77	extern ulong _rel_dyn_start_ofs;	72	extern char __image_copy_start[];
78	extern ulong _rel_dyn_end_ofs;	73	extern char __image_copy_end[];
79		74	extern char __rel_dyn_start[];
80	/* End of the region to be relocated, as an offset form _start */	75	extern char __rel_dyn_end[];
81	extern ulong _image_copy_end_ofs;
82
83	extern ulong _bss_start_ofs; /* BSS start relative to _start */
84	extern ulong _bss_end_ofs; /* BSS end relative to _start */
85	extern ulong _end_ofs; /* end of image relative to _start */
86
87	extern ulong _TEXT_BASE; /* code start */
88		76
89	#else /* don't use offsets: */	77	#else /* don't use offsets: */
90		78
91	/* Exports from the Linker Script */	79	/* Exports from the Linker Script */
92	extern ulong __data_end;	80	extern ulong __data_end;
93	extern ulong __rel_dyn_start;	81	extern ulong __rel_dyn_start;
94	extern ulong __rel_dyn_end;	82	extern ulong __rel_dyn_end;
95	extern ulong __bss_end;	83	extern ulong __bss_end;
96		84
97	extern ulong _TEXT_BASE; /* code start */	85	extern ulong _TEXT_BASE; /* code start */
98		86
99	#endif	87	#endif
100		88
101	#endif /* _ASM_GENERIC_SECTIONS_H_ */	89	#endif /* _ASM_GENERIC_SECTIONS_H_ */
102		90