Eric Lee / smarc-uboot | Embedian Git Server

Commit b87ca80b9b1825b44341aa4bcd28c26a7860fd18

Authored by Simon Glass 2016-10-18 10:12:57 +0800

Committed by Tom Rini 2016-10-24 06:33:57 +0800

Exists in v2017.01-smarct4x and in 25 other branches

Convert CONFIG_CONSOLE_SCROLL_LINES to Kconfig

This converts the following to Kconfig:
   CONFIG_CONSOLE_SCROLL_LINES

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

Showing 47 changed files with 37 additions and 30 deletions Inline Diff

README
configs/bayleybay_defconfig
configs/chromebook_jerry_defconfig
configs/chromebook_link_defconfig
configs/chromebook_samus_defconfig
configs/chromebox_panther_defconfig
configs/colibri_t20_defconfig
configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
configs/conga-qeval20-qa3-e3845_defconfig
configs/coreboot-x86_defconfig
configs/crownbay_defconfig
configs/dfi-bt700-q7x-151_defconfig
configs/firefly-rk3288_defconfig
configs/harmony_defconfig
configs/minnowmax_defconfig
configs/paz00_defconfig
configs/qemu-x86_defconfig
configs/qemu-x86_efi_payload32_defconfig
configs/qemu-x86_efi_payload64_defconfig
configs/rock2_defconfig
configs/rpi_2_defconfig
configs/rpi_3_32b_defconfig
configs/rpi_3_defconfig
configs/rpi_defconfig
configs/seaboard_defconfig
configs/som-db5800-som-6867_defconfig
configs/theadorable-x86-dfi-bt700_defconfig
configs/ventana_defconfig
drivers/video/Kconfig
include/configs/chromebook_jerry.h
include/configs/colibri_pxa270.h
include/configs/colibri_t20.h
include/configs/evb_rk3288.h
include/configs/evb_rk3399.h
include/configs/fennec_rk3288.h
include/configs/firefly-rk3288.h
include/configs/harmony.h
include/configs/miniarm_rk3288.h
include/configs/paz00.h
include/configs/popmetal_rk3288.h
include/configs/rock2.h
include/configs/rpi.h
include/configs/seaboard.h
include/configs/ventana.h
include/configs/x86-common.h
include/lcd_console.h
scripts/config_whitelist.txt

README

Diff comments View file @ b87ca80

 #
 # (C) Copyright 2000 - 2013
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 Summary:
 ========
 This directory contains the source code for U-Boot, a boot loader for
 Embedded boards based on PowerPC, ARM, MIPS and several other
 processors, which can be installed in a boot ROM and used to
 initialize and test the hardware or to download and run application
 code.
 The development of U-Boot is closely related to Linux: some parts of
 the source code originate in the Linux source tree, we have some
 header files in common, and special provision has been made to
 support booting of Linux images.
 Some attention has been paid to make this software easily
 configurable and extendable. For instance, all monitor commands are
 implemented with the same call interface, so that it's very easy to
 add new commands. Also, instead of permanently adding rarely used
 code (for instance hardware test utilities) to the monitor, you can
 load and run it dynamically.
 Status:
 =======
 In general, all boards for which a configuration option exists in the
 Makefile have been tested to some extent and can be considered
 "working". In fact, many of them are used in production systems.
 In case of problems see the CHANGELOG file to find out who contributed
 the specific port. In addition, there are various MAINTAINERS files
 scattered throughout the U-Boot source identifying the people or
 companies responsible for various boards and subsystems.
 Note: As of August, 2010, there is no longer a CHANGELOG file in the
 actual U-Boot source tree; however, it can be created dynamically
 from the Git log using:
 	make CHANGELOG
 Where to get help:
 ==================
 In case you have questions about, problems with or contributions for
 U-Boot, you should send a message to the U-Boot mailing list at
 <u-boot@lists.denx.de>. There is also an archive of previous traffic
 on the mailing list - please search the archive before asking FAQ's.
 Please see http://lists.denx.de/pipermail/u-boot and
 http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
 Where to get source code:
 =========================
 The U-Boot source code is maintained in the Git repository at
 git://www.denx.de/git/u-boot.git ; you can browse it online at
 http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
 The "snapshot" links on this page allow you to download tarballs of
 any version you might be interested in. Official releases are also
 available for FTP download from the ftp://ftp.denx.de/pub/u-boot/
 directory.
 Pre-built (and tested) images are available from
 ftp://ftp.denx.de/pub/u-boot/images/
 Where we come from:
 ===================
 - start from 8xxrom sources
 - create PPCBoot project (http://sourceforge.net/projects/ppcboot)
 - clean up code
 - make it easier to add custom boards
 - make it possible to add other [PowerPC] CPUs
 - extend functions, especially:
   * Provide extended interface to Linux boot loader
   * S-Record download
   * network boot
   * PCMCIA / CompactFlash / ATA disk / SCSI ... boot
 - create ARMBoot project (http://sourceforge.net/projects/armboot)
 - add other CPU families (starting with ARM)
 - create U-Boot project (http://sourceforge.net/projects/u-boot)
 - current project page: see http://www.denx.de/wiki/U-Boot
 Names and Spelling:
 ===================
 The "official" name of this project is "Das U-Boot". The spelling
 "U-Boot" shall be used in all written text (documentation, comments
 in source files etc.). Example:
 	This is the README file for the U-Boot project.
 File names etc. shall be based on the string "u-boot". Examples:
 	include/asm-ppc/u-boot.h
 	#include <asm/u-boot.h>
 Variable names, preprocessor constants etc. shall be either based on
 the string "u_boot" or on "U_BOOT". Example:
 	U_BOOT_VERSION		u_boot_logo
 	IH_OS_U_BOOT		u_boot_hush_start
 Versioning:
 ===========
 Starting with the release in October 2008, the names of the releases
 were changed from numerical release numbers without deeper meaning
 into a time stamp based numbering. Regular releases are identified by
 names consisting of the calendar year and month of the release date.
 Additional fields (if present) indicate release candidates or bug fix
 releases in "stable" maintenance trees.
 Examples:
 	U-Boot v2009.11	    - Release November 2009
 	U-Boot v2009.11.1   - Release 1 in version November 2009 stable tree
 	U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
 Directory Hierarchy:
 ====================
 /arch			Architecture specific files
   /arc			Files generic to ARC architecture
   /arm			Files generic to ARM architecture
   /avr32		Files generic to AVR32 architecture
   /blackfin		Files generic to Analog Devices Blackfin architecture
   /m68k			Files generic to m68k architecture
   /microblaze		Files generic to microblaze architecture
   /mips			Files generic to MIPS architecture
   /nds32		Files generic to NDS32 architecture
   /nios2		Files generic to Altera NIOS2 architecture
   /openrisc		Files generic to OpenRISC architecture
   /powerpc		Files generic to PowerPC architecture
   /sandbox		Files generic to HW-independent "sandbox"
   /sh			Files generic to SH architecture
   /sparc		Files generic to SPARC architecture
   /x86			Files generic to x86 architecture
 /api			Machine/arch independent API for external apps
 /board			Board dependent files
 /cmd			U-Boot commands functions
 /common			Misc architecture independent functions
 /configs		Board default configuration files
 /disk			Code for disk drive partition handling
 /doc			Documentation (don't expect too much)
 /drivers		Commonly used device drivers
 /dts			Contains Makefile for building internal U-Boot fdt.
 /examples		Example code for standalone applications, etc.
 /fs			Filesystem code (cramfs, ext2, jffs2, etc.)
 /include		Header Files
 /lib			Library routines generic to all architectures
 /Licenses		Various license files
 /net			Networking code
 /post			Power On Self Test
 /scripts		Various build scripts and Makefiles
 /test			Various unit test files
 /tools			Tools to build S-Record or U-Boot images, etc.
 Software Configuration:
 =======================
 Configuration is usually done using C preprocessor defines; the
 rationale behind that is to avoid dead code whenever possible.
 There are two classes of configuration variables:
 * Configuration _OPTIONS_:
   These are selectable by the user and have names beginning with
   "CONFIG_".
 * Configuration _SETTINGS_:
   These depend on the hardware etc. and should not be meddled with if
   you don't know what you're doing; they have names beginning with
   "CONFIG_SYS_".
 Previously, all configuration was done by hand, which involved creating
 symbolic links and editing configuration files manually. More recently,
 U-Boot has added the Kbuild infrastructure used by the Linux kernel,
 allowing you to use the "make menuconfig" command to configure your
 build.
 Selection of Processor Architecture and Board Type:
 ---------------------------------------------------
 For all supported boards there are ready-to-use default
 configurations available; just type "make <board_name>_defconfig".
 Example: For a TQM823L module type:
 	cd u-boot
 	make TQM823L_defconfig
 Note: If you're looking for the default configuration file for a board
 you're sure used to be there but is now missing, check the file
 doc/README.scrapyard for a list of no longer supported boards.
 Sandbox Environment:
 --------------------
 U-Boot can be built natively to run on a Linux host using the 'sandbox'
 board. This allows feature development which is not board- or architecture-
 specific to be undertaken on a native platform. The sandbox is also used to
 run some of U-Boot's tests.
 See board/sandbox/README.sandbox for more details.
 Board Initialisation Flow:
 --------------------------
 This is the intended start-up flow for boards. This should apply for both
 SPL and U-Boot proper (i.e. they both follow the same rules).
 Note: "SPL" stands for "Secondary Program Loader," which is explained in
 more detail later in this file.
 At present, SPL mostly uses a separate code path, but the function names
 and roles of each function are the same. Some boards or architectures
 may not conform to this.  At least most ARM boards which use
 CONFIG_SPL_FRAMEWORK conform to this.
 Execution typically starts with an architecture-specific (and possibly
 CPU-specific) start.S file, such as:
 	- arch/arm/cpu/armv7/start.S
 	- arch/powerpc/cpu/mpc83xx/start.S
 	- arch/mips/cpu/start.S
 and so on. From there, three functions are called; the purpose and
 limitations of each of these functions are described below.
 lowlevel_init():
 	- purpose: essential init to permit execution to reach board_init_f()
 	- no global_data or BSS
 	- there is no stack (ARMv7 may have one but it will soon be removed)
 	- must not set up SDRAM or use console
 	- must only do the bare minimum to allow execution to continue to
 		board_init_f()
 	- this is almost never needed
 	- return normally from this function
 board_init_f():
 	- purpose: set up the machine ready for running board_init_r():
 		i.e. SDRAM and serial UART
 	- global_data is available
 	- stack is in SRAM
 	- BSS is not available, so you cannot use global/static variables,
 		only stack variables and global_data
 	Non-SPL-specific notes:
 	- dram_init() is called to set up DRAM. If already done in SPL this
 		can do nothing
 	SPL-specific notes:
 	- you can override the entire board_init_f() function with your own
 		version as needed.
 	- preloader_console_init() can be called here in extremis
 	- should set up SDRAM, and anything needed to make the UART work
 	- these is no need to clear BSS, it will be done by crt0.S
 	- must return normally from this function (don't call board_init_r()
 		directly)
 Here the BSS is cleared. For SPL, if CONFIG_SPL_STACK_R is defined, then at
 this point the stack and global_data are relocated to below
 CONFIG_SPL_STACK_R_ADDR. For non-SPL, U-Boot is relocated to run at the top of
 memory.
 board_init_r():
 	- purpose: main execution, common code
 	- global_data is available
 	- SDRAM is available
 	- BSS is available, all static/global variables can be used
 	- execution eventually continues to main_loop()
 	Non-SPL-specific notes:
 	- U-Boot is relocated to the top of memory and is now running from
 		there.
 	SPL-specific notes:
 	- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
 		CONFIG_SPL_STACK_R_ADDR points into SDRAM
 	- preloader_console_init() can be called here - typically this is
 		done by defining CONFIG_SPL_BOARD_INIT and then supplying a
 		spl_board_init() function containing this call
 	- loads U-Boot or (in falcon mode) Linux
 Configuration Options:
 ----------------------
 Configuration depends on the combination of board and CPU type; all
 such information is kept in a configuration file
 "include/configs/<board_name>.h".
 Example: For a TQM823L module, all configuration settings are in
 "include/configs/TQM823L.h".
 Many of the options are named exactly as the corresponding Linux
 kernel configuration options. The intention is to make it easier to
 build a config tool - later.
 The following options need to be configured:
 - CPU Type:	Define exactly one, e.g. CONFIG_MPC85XX.
 - Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
 		Define exactly one, e.g. CONFIG_ATSTK1002
 - Marvell Family Member
 		CONFIG_SYS_MVFS		- define it if you want to enable
 					  multiple fs option at one time
 					  for marvell soc family
 - 8xx CPU Options: (if using an MPC8xx CPU)
 		CONFIG_8xx_GCLK_FREQ	- deprecated: CPU clock if
 					  get_gclk_freq() cannot work
 					  e.g. if there is no 32KHz
 					  reference PIT/RTC clock
 		CONFIG_8xx_OSCLK	- PLL input clock (either EXTCLK
 					  or XTAL/EXTAL)
 - 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
 		CONFIG_SYS_8xx_CPUCLK_MIN
 		CONFIG_SYS_8xx_CPUCLK_MAX
 		CONFIG_8xx_CPUCLK_DEFAULT
 			See doc/README.MPC866
 		CONFIG_SYS_MEASURE_CPUCLK
 		Define this to measure the actual CPU clock instead
 		of relying on the correctness of the configured
 		values. Mostly useful for board bringup to make sure
 		the PLL is locked at the intended frequency. Note
 		that this requires a (stable) reference clock (32 kHz
 		RTC clock or CONFIG_SYS_8XX_XIN)
 		CONFIG_SYS_DELAYED_ICACHE
 		Define this option if you want to enable the
 		ICache only when Code runs from RAM.
 - 85xx CPU Options:
 		CONFIG_SYS_PPC64
 		Specifies that the core is a 64-bit PowerPC implementation (implements
 		the "64" category of the Power ISA). This is necessary for ePAPR
 		compliance, among other possible reasons.
 		CONFIG_SYS_FSL_TBCLK_DIV
 		Defines the core time base clock divider ratio compared to the
 		system clock.  On most PQ3 devices this is 8, on newer QorIQ
 		devices it can be 16 or 32.  The ratio varies from SoC to Soc.
 		CONFIG_SYS_FSL_PCIE_COMPAT
 		Defines the string to utilize when trying to match PCIe device
 		tree nodes for the given platform.
 		CONFIG_SYS_PPC_E500_DEBUG_TLB
 		Enables a temporary TLB entry to be used during boot to work
 		around limitations in e500v1 and e500v2 external debugger
 		support. This reduces the portions of the boot code where
 		breakpoints and single stepping do not work.  The value of this
 		symbol should be set to the TLB1 entry to be used for this
 		purpose.
 		CONFIG_SYS_FSL_ERRATUM_A004510
 		Enables a workaround for erratum A004510.  If set,
 		then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
 		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
 		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
 		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
 		Defines one or two SoC revisions (low 8 bits of SVR)
 		for which the A004510 workaround should be applied.
 		The rest of SVR is either not relevant to the decision
 		of whether the erratum is present (e.g. p2040 versus
 		p2041) or is implied by the build target, which controls
 		whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
 		See Freescale App Note 4493 for more information about
 		this erratum.
 		CONFIG_A003399_NOR_WORKAROUND
 		Enables a workaround for IFC erratum A003399. It is only
 		required during NOR boot.
 		CONFIG_A008044_WORKAROUND
 		Enables a workaround for T1040/T1042 erratum A008044. It is only
 		required during NAND boot and valid for Rev 1.0 SoC revision
 		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 		This is the value to write into CCSR offset 0x18600
 		according to the A004510 workaround.
 		CONFIG_SYS_FSL_DSP_DDR_ADDR
 		This value denotes start offset of DDR memory which is
 		connected exclusively to the DSP cores.
 		CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
 		This value denotes start offset of M2 memory
 		which is directly connected to the DSP core.
 		CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
 		This value denotes start offset of M3 memory which is directly
 		connected to the DSP core.
 		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 		This value denotes start offset of DSP CCSR space.
 		CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 		Single Source Clock is clocking mode present in some of FSL SoC's.
 		In this mode, a single differential clock is used to supply
 		clocks to the sysclock, ddrclock and usbclock.
 		CONFIG_SYS_CPC_REINIT_F
 		This CONFIG is defined when the CPC is configured as SRAM at the
 		time of U-Boot entry and is required to be re-initialized.
 		CONFIG_DEEP_SLEEP
 		Indicates this SoC supports deep sleep feature. If deep sleep is
 		supported, core will start to execute uboot when wakes up.
 - Generic CPU options:
 		CONFIG_SYS_GENERIC_GLOBAL_DATA
 		Defines global data is initialized in generic board board_init_f().
 		If this macro is defined, global data is created and cleared in
 		generic board board_init_f(). Without this macro, architecture/board
 		should initialize global data before calling board_init_f().
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 		Defines the endianess of the CPU. Implementation of those
 		values is arch specific.
 		CONFIG_SYS_FSL_DDR
 		Freescale DDR driver in use. This type of DDR controller is
 		found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
 		SoCs.
 		CONFIG_SYS_FSL_DDR_ADDR
 		Freescale DDR memory-mapped register base.
 		CONFIG_SYS_FSL_DDR_EMU
 		Specify emulator support for DDR. Some DDR features such as
 		deskew training are not available.
 		CONFIG_SYS_FSL_DDRC_GEN1
 		Freescale DDR1 controller.
 		CONFIG_SYS_FSL_DDRC_GEN2
 		Freescale DDR2 controller.
 		CONFIG_SYS_FSL_DDRC_GEN3
 		Freescale DDR3 controller.
 		CONFIG_SYS_FSL_DDRC_GEN4
 		Freescale DDR4 controller.
 		CONFIG_SYS_FSL_DDRC_ARM_GEN3
 		Freescale DDR3 controller for ARM-based SoCs.
 		CONFIG_SYS_FSL_DDR1
 		Board config to use DDR1. It can be enabled for SoCs with
 		Freescale DDR1 or DDR2 controllers, depending on the board
 		implemetation.
 		CONFIG_SYS_FSL_DDR2
 		Board config to use DDR2. It can be enabled for SoCs with
 		Freescale DDR2 or DDR3 controllers, depending on the board
 		implementation.
 		CONFIG_SYS_FSL_DDR3
 		Board config to use DDR3. It can be enabled for SoCs with
 		Freescale DDR3 or DDR3L controllers.
 		CONFIG_SYS_FSL_DDR3L
 		Board config to use DDR3L. It can be enabled for SoCs with
 		DDR3L controllers.
 		CONFIG_SYS_FSL_DDR4
 		Board config to use DDR4. It can be enabled for SoCs with
 		DDR4 controllers.
 		CONFIG_SYS_FSL_IFC_BE
 		Defines the IFC controller register space as Big Endian
 		CONFIG_SYS_FSL_IFC_LE
 		Defines the IFC controller register space as Little Endian
 		CONFIG_SYS_FSL_PBL_PBI
 		It enables addition of RCW (Power on reset configuration) in built image.
 		Please refer doc/README.pblimage for more details
 		CONFIG_SYS_FSL_PBL_RCW
 		It adds PBI(pre-boot instructions) commands in u-boot build image.
 		PBI commands can be used to configure SoC before it starts the execution.
 		Please refer doc/README.pblimage for more details
 		CONFIG_SPL_FSL_PBL
 		It adds a target to create boot binary having SPL binary in PBI format
 		concatenated with u-boot binary.
 		CONFIG_SYS_FSL_DDR_BE
 		Defines the DDR controller register space as Big Endian
 		CONFIG_SYS_FSL_DDR_LE
 		Defines the DDR controller register space as Little Endian
 		CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
 		Physical address from the view of DDR controllers. It is the
 		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
 		it could be different for ARM SoCs.
 		CONFIG_SYS_FSL_DDR_INTLV_256B
 		DDR controller interleaving on 256-byte. This is a special
 		interleaving mode, handled by Dickens for Freescale layerscape
 		SoCs with ARM core.
 		CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
 		Number of controllers used as main memory.
 		CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 		Number of controllers used for other than main memory.
 		CONFIG_SYS_FSL_HAS_DP_DDR
 		Defines the SoC has DP-DDR used for DPAA.
 		CONFIG_SYS_FSL_SEC_BE
 		Defines the SEC controller register space as Big Endian
 		CONFIG_SYS_FSL_SEC_LE
 		Defines the SEC controller register space as Little Endian
 - MIPS CPU options:
 		CONFIG_SYS_INIT_SP_OFFSET
 		Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
 		pointer. This is needed for the temporary stack before
 		relocation.
 		CONFIG_SYS_MIPS_CACHE_MODE
 		Cache operation mode for the MIPS CPU.
 		See also arch/mips/include/asm/mipsregs.h.
 		Possible values are:
 			CONF_CM_CACHABLE_NO_WA
 			CONF_CM_CACHABLE_WA
 			CONF_CM_UNCACHED
 			CONF_CM_CACHABLE_NONCOHERENT
 			CONF_CM_CACHABLE_CE
 			CONF_CM_CACHABLE_COW
 			CONF_CM_CACHABLE_CUW
 			CONF_CM_CACHABLE_ACCELERATED
 		CONFIG_SYS_XWAY_EBU_BOOTCFG
 		Special option for Lantiq XWAY SoCs for booting from NOR flash.
 		See also arch/mips/cpu/mips32/start.S.
 		CONFIG_XWAY_SWAP_BYTES
 		Enable compilation of tools/xway-swap-bytes needed for Lantiq
 		XWAY SoCs for booting from NOR flash. The U-Boot image needs to
 		be swapped if a flash programmer is used.
 - ARM options:
 		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 		Select high exception vectors of the ARM core, e.g., do not
 		clear the V bit of the c1 register of CP15.
 		CONFIG_SYS_THUMB_BUILD
 		Use this flag to build U-Boot using the Thumb instruction
 		set for ARM architectures. Thumb instruction set provides
 		better code density. For ARM architectures that support
 		Thumb2 this flag will result in Thumb2 code generated by
 		GCC.
 		CONFIG_ARM_ERRATA_716044
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_761320
 		CONFIG_ARM_ERRATA_773022
 		CONFIG_ARM_ERRATA_774769
 		CONFIG_ARM_ERRATA_794072
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
 		workarounds to be applied; no CPU-type/version detection
 		exists, unlike the similar options in the Linux kernel. Do not
 		set these options unless they apply!
 		COUNTER_FREQUENCY
 		Generic timer clock source frequency.
 		COUNTER_FREQUENCY_REAL
 		Generic timer clock source frequency if the real clock is
 		different from COUNTER_FREQUENCY, and can only be determined
 		at run time.
 		NOTE: The following can be machine specific errata. These
 		do have ability to provide rudimentary version and machine
 		specific checks, but expect no product checks.
 		CONFIG_ARM_ERRATA_430973
 		CONFIG_ARM_ERRATA_454179
 		CONFIG_ARM_ERRATA_621766
 		CONFIG_ARM_ERRATA_798870
 		CONFIG_ARM_ERRATA_801819
 - Tegra SoC options:
 		CONFIG_TEGRA_SUPPORT_NON_SECURE
 		Support executing U-Boot in non-secure (NS) mode. Certain
 		impossible actions will be skipped if the CPU is in NS mode,
 		such as ARM architectural timer initialization.
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 		U-Boot stores all clock information in Hz
 		internally. For binary compatibility with older Linux
 		kernels (which expect the clocks passed in the
 		bd_info data to be in MHz) the environment variable
 		"clocks_in_mhz" can be defined so that U-Boot
 		converts clock data to MHZ before passing it to the
 		Linux kernel.
 		When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
 		"clocks_in_mhz=1" is automatically included in the
 		default environment.
 		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
 		When transferring memsize parameter to Linux, some versions
 		expect it to be in bytes, others in MB.
 		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
 		CONFIG_OF_LIBFDT
 		New kernel versions are expecting firmware settings to be
 		passed using flattened device trees (based on open firmware
 		concepts).
 		CONFIG_OF_LIBFDT
 		 * New libfdt-based support
 		 * Adds the "fdt" command
 		 * The bootm command automatically updates the fdt
 		OF_CPU - The proper name of the cpus node (only required for
 			MPC512X and MPC5xxx based boards).
 		OF_SOC - The proper name of the soc node (only required for
 			MPC512X and MPC5xxx based boards).
 		OF_TBCLK - The timebase frequency.
 		OF_STDOUT_PATH - The path to the console device
 		boards with QUICC Engines require OF_QE to set UCC MAC
 		addresses
 		CONFIG_OF_BOARD_SETUP
 		Board code has addition modification that it wants to make
 		to the flat device tree before handing it off to the kernel
 		CONFIG_OF_SYSTEM_SETUP
 		Other code has addition modification that it wants to make
 		to the flat device tree before handing it off to the kernel.
 		This causes ft_system_setup() to be called before booting
 		the kernel.
 		CONFIG_OF_IDE_FIXUP
 		U-Boot can detect if an IDE device is present or not.
 		If not, and this new config option is activated, U-Boot
 		removes the ATA node from the DTS before booting Linux,
 		so the Linux IDE driver does not probe the device and
 		crash. This is needed for buggy hardware (uc101) where
 		no pull down resistor is connected to the signal IDE5V_DD7.
 		CONFIG_MACH_TYPE	[relevant for ARM only][mandatory]
 		This setting is mandatory for all boards that have only one
 		machine type and must be used to specify the machine type
 		number as it appears in the ARM machine registry
 		(see http://www.arm.linux.org.uk/developer/machines/).
 		Only boards that have multiple machine types supported
 		in a single configuration file and the machine type is
 		runtime discoverable, do not have to use this setting.
 - vxWorks boot parameters:
 		bootvx constructs a valid bootline using the following
 		environments variables: bootdev, bootfile, ipaddr, netmask,
 		serverip, gatewayip, hostname, othbootargs.
 		It loads the vxWorks image pointed bootfile.
 		Note: If a "bootargs" environment is defined, it will overwride
 		the defaults discussed just above.
 - Cache Configuration:
 		CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
 		CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
 		CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
 - Cache Configuration for ARM:
 		CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
 				      controller
 		CONFIG_SYS_PL310_BASE - Physical base address of PL310
 					controller register space
 - Serial Ports:
 		CONFIG_PL010_SERIAL
 		Define this if you want support for Amba PrimeCell PL010 UARTs.
 		CONFIG_PL011_SERIAL
 		Define this if you want support for Amba PrimeCell PL011 UARTs.
 		CONFIG_PL011_CLOCK
 		If you have Amba PrimeCell PL011 UARTs, set this variable to
 		the clock speed of the UARTs.
 		CONFIG_PL01x_PORTS
 		If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
 		define this to a list of base addresses for each (supported)
 		port. See e.g. include/configs/versatile.h
 		CONFIG_SERIAL_HW_FLOW_CONTROL
 		Define this variable to enable hw flow control in serial driver.
 		Current user of this option is drivers/serial/nsl16550.c driver
 - Console Interface:
 		Depending on board, define exactly one serial port
 		(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
 		CONFIG_8xx_CONS_SCC1, ...), or switch off the serial
 		console by defining CONFIG_8xx_CONS_NONE
 		Note: if CONFIG_8xx_CONS_NONE is defined, the serial
 		port routines must be defined elsewhere
 		(i.e. serial_init(), serial_getc(), ...)
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
 		CONFIG_SYS_BAUDRATE_TABLE, see below.
 		CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
 - Console Rx buffer length
 		With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
 		the maximum receive buffer length for the SMC.
 		This option is actual only for 82xx and 8xx possible.
 		If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
 		must be defined, to setup the maximum idle timeout for
 		the SMC.
 - Autoboot Command:
 		CONFIG_BOOTCOMMAND
 		Only needed when CONFIG_BOOTDELAY is enabled;
 		define a command string that is automatically executed
 		when no character is read on the console interface
 		within "Boot Delay" after reset.
 		CONFIG_BOOTARGS
 		This can be used to pass arguments to the bootm
 		command. The value of CONFIG_BOOTARGS goes into the
 		environment value "bootargs".
 		CONFIG_RAMBOOT and CONFIG_NFSBOOT
 		The value of these goes into the environment as
 		"ramboot" and "nfsboot" respectively, and can be used
 		as a convenience, when switching between booting from
 		RAM and NFS.
 - Bootcount:
 		CONFIG_BOOTCOUNT_LIMIT
 		Implements a mechanism for detecting a repeating reboot
 		cycle, see:
 		http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
 		CONFIG_BOOTCOUNT_ENV
 		If no softreset save registers are found on the hardware
 		"bootcount" is stored in the environment. To prevent a
 		saveenv on all reboots, the environment variable
 		"upgrade_available" is used. If "upgrade_available" is
 		0, "bootcount" is always 0, if "upgrade_available" is
 		1 "bootcount" is incremented in the environment.
 		So the Userspace Applikation must set the "upgrade_available"
 		and "bootcount" variable to 0, if a boot was successfully.
 - Pre-Boot Commands:
 		CONFIG_PREBOOT
 		When this option is #defined, the existence of the
 		environment variable "preboot" will be checked
 		immediately before starting the CONFIG_BOOTDELAY
 		countdown and/or running the auto-boot command resp.
 		entering interactive mode.
 		This feature is especially useful when "preboot" is
 		automatically generated or modified. For an example
 		see the LWMON board specific code: here "preboot" is
 		modified when the user holds down a certain
 		combination of keys on the (special) keyboard when
 		booting the systems
 - Serial Download Echo Mode:
 		CONFIG_LOADS_ECHO
 		If defined to 1, all characters received during a
 		serial download (using the "loads" command) are
 		echoed back. This might be needed by some terminal
 		emulations (like "cu"), but may as well just take
 		time on others. This setting #define's the initial
 		value of the "loads_echo" environment variable.
 - Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
 		CONFIG_KGDB_BAUDRATE
 		Select one of the baudrates listed in
 		CONFIG_SYS_BAUDRATE_TABLE, see below.
 - Monitor Functions:
 		Monitor commands can be included or excluded
 		from the build by using the #include files
 		<config_cmd_all.h> and #undef'ing unwanted
 		commands, or adding #define's for wanted commands.
 		The default command configuration includes all commands
 		except those marked below with a "*".
 		CONFIG_CMD_AES		  AES 128 CBC encrypt/decrypt
 		CONFIG_CMD_ASKENV	* ask for env variable
 		CONFIG_CMD_BDI		  bdinfo
 		CONFIG_CMD_BEDBUG	* Include BedBug Debugger
 		CONFIG_CMD_BMP		* BMP support
 		CONFIG_CMD_BSP		* Board specific commands
 		CONFIG_CMD_BOOTD	  bootd
 		CONFIG_CMD_BOOTI	* ARM64 Linux kernel Image support
 		CONFIG_CMD_CACHE	* icache, dcache
 		CONFIG_CMD_CLK   	* clock command support
 		CONFIG_CMD_CONSOLE	  coninfo
 		CONFIG_CMD_CRC32	* crc32
 		CONFIG_CMD_DATE		* support for RTC, date/time...
 		CONFIG_CMD_DHCP		* DHCP support
 		CONFIG_CMD_DIAG		* Diagnostics
 		CONFIG_CMD_DS4510	* ds4510 I2C gpio commands
 		CONFIG_CMD_DS4510_INFO	* ds4510 I2C info command
 		CONFIG_CMD_DS4510_MEM	* ds4510 I2C eeprom/sram commansd
 		CONFIG_CMD_DS4510_RST	* ds4510 I2C rst command
 		CONFIG_CMD_DTT		* Digital Therm and Thermostat
 		CONFIG_CMD_ECHO		  echo arguments
 		CONFIG_CMD_EDITENV	  edit env variable
 		CONFIG_CMD_EEPROM	* EEPROM read/write support
 		CONFIG_CMD_EEPROM_LAYOUT* EEPROM layout aware commands
 		CONFIG_CMD_ELF		* bootelf, bootvx
 		CONFIG_CMD_ENV_CALLBACK	* display details about env callbacks
 		CONFIG_CMD_ENV_FLAGS	* display details about env flags
 		CONFIG_CMD_ENV_EXISTS	* check existence of env variable
 		CONFIG_CMD_EXPORTENV	* export the environment
 		CONFIG_CMD_EXT2		* ext2 command support
 		CONFIG_CMD_EXT4		* ext4 command support
 		CONFIG_CMD_FS_GENERIC	* filesystem commands (e.g. load, ls)
 					  that work for multiple fs types
 		CONFIG_CMD_FS_UUID	* Look up a filesystem UUID
 		CONFIG_CMD_SAVEENV	  saveenv
 		CONFIG_CMD_FDC		* Floppy Disk Support
 		CONFIG_CMD_FAT		* FAT command support
 		CONFIG_CMD_FLASH	  flinfo, erase, protect
 		CONFIG_CMD_FPGA		  FPGA device initialization support
 		CONFIG_CMD_FUSE		* Device fuse support
 		CONFIG_CMD_GETTIME	* Get time since boot
 		CONFIG_CMD_GO		* the 'go' command (exec code)
 		CONFIG_CMD_GREPENV	* search environment
 		CONFIG_CMD_HASH		* calculate hash / digest
 		CONFIG_CMD_I2C		* I2C serial bus support
 		CONFIG_CMD_IDE		* IDE harddisk support
 		CONFIG_CMD_IMI		  iminfo
 		CONFIG_CMD_IMLS		  List all images found in NOR flash
 		CONFIG_CMD_IMLS_NAND	* List all images found in NAND flash
 		CONFIG_CMD_IMMAP	* IMMR dump support
 		CONFIG_CMD_IOTRACE	* I/O tracing for debugging
 		CONFIG_CMD_IMPORTENV	* import an environment
 		CONFIG_CMD_INI		* import data from an ini file into the env
 		CONFIG_CMD_IRQ		* irqinfo
 		CONFIG_CMD_ITEST	  Integer/string test of 2 values
 		CONFIG_CMD_JFFS2	* JFFS2 Support
 		CONFIG_CMD_KGDB		* kgdb
 		CONFIG_CMD_LDRINFO	* ldrinfo (display Blackfin loader)
 		CONFIG_CMD_LINK_LOCAL	* link-local IP address auto-configuration
 					  (169.254.*.*)
 		CONFIG_CMD_LOADB	  loadb
 		CONFIG_CMD_LOADS	  loads
 		CONFIG_CMD_MD5SUM	* print md5 message digest
 					  (requires CONFIG_CMD_MEMORY and CONFIG_MD5)
 		CONFIG_CMD_MEMINFO	* Display detailed memory information
 		CONFIG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 					  loop, loopw
 		CONFIG_CMD_MEMTEST	* mtest
 		CONFIG_CMD_MISC		  Misc functions like sleep etc
 		CONFIG_CMD_MMC		* MMC memory mapped support
 		CONFIG_CMD_MII		* MII utility commands
 		CONFIG_CMD_MTDPARTS	* MTD partition support
 		CONFIG_CMD_NAND		* NAND support
 		CONFIG_CMD_NET		  bootp, tftpboot, rarpboot
 		CONFIG_CMD_NFS		  NFS support
 		CONFIG_CMD_PCA953X	* PCA953x I2C gpio commands
 		CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
 		CONFIG_CMD_PCI		* pciinfo
 		CONFIG_CMD_PCMCIA		* PCMCIA support
 		CONFIG_CMD_PING		* send ICMP ECHO_REQUEST to network
 					  host
 		CONFIG_CMD_PORTIO	* Port I/O
 		CONFIG_CMD_READ		* Read raw data from partition
 		CONFIG_CMD_REGINFO	* Register dump
 		CONFIG_CMD_RUN		  run command in env variable
 		CONFIG_CMD_SANDBOX	* sb command to access sandbox features
 		CONFIG_CMD_SAVES	* save S record dump
 		CONFIG_SCSI		* SCSI Support
 		CONFIG_CMD_SDRAM	* print SDRAM configuration information
 					  (requires CONFIG_CMD_I2C)
 		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
 					  (4xx only)
 		CONFIG_CMD_SF		* Read/write/erase SPI NOR flash
 		CONFIG_CMD_SHA1SUM	* print sha1 memory digest
 					  (requires CONFIG_CMD_MEMORY)
 		CONFIG_CMD_SOFTSWITCH	* Soft switch setting command for BF60x
 		CONFIG_CMD_SOURCE	  "source" command Support
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_TFTPSRV	* TFTP transfer in server mode
 		CONFIG_CMD_TFTPPUT	* TFTP put command (upload)
 		CONFIG_CMD_TIME		* run command and report execution time (ARM specific)
 		CONFIG_CMD_TIMER	* access to the system tick timer
 		CONFIG_CMD_USB		* USB support
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_MFSL		* Microblaze FSL support
 		CONFIG_CMD_XIMG		  Load part of Multi Image
 		CONFIG_CMD_UUID		* Generate random UUID or GUID string
 		EXAMPLE: If you want all functions except of network
 		support you can write:
 		#include "config_cmd_all.h"
 		#undef CONFIG_CMD_NET
 	Other Commands:
 		fdt (flattened device tree) command: CONFIG_OF_LIBFDT
 	Note:	Don't enable the "icache" and "dcache" commands
 		(configuration option CONFIG_CMD_CACHE) unless you know
 		what you (and your U-Boot users) are doing. Data
 		cache cannot be enabled on systems like the 8xx or
 		8260 (where accesses to the IMMR region must be
 		uncached), and it cannot be disabled on all other
 		systems where we (mis-) use the data cache to hold an
 		initial stack and some data.
 		XXX - this list needs to get updated!
 - Removal of commands
 		If no commands are needed to boot, you can disable
 		CONFIG_CMDLINE to remove them. In this case, the command line
 		will not be available, and when U-Boot wants to execute the
 		boot command (on start-up) it will call board_run_command()
 		instead. This can reduce image size significantly for very
 		simple boot procedures.
 - Regular expression support:
 		CONFIG_REGEX
 		If this variable is defined, U-Boot is linked against
 		the SLRE (Super Light Regular Expression) library,
 		which adds regex support to some commands, as for
 		example "env grep" and "setexpr".
 - Device tree:
 		CONFIG_OF_CONTROL
 		If this variable is defined, U-Boot will use a device tree
 		to configure its devices, instead of relying on statically
 		compiled #defines in the board file. This option is
 		experimental and only available on a few boards. The device
 		tree is available in the global data as gd->fdt_blob.
 		U-Boot needs to get its device tree from somewhere. This can
 		be done using one of the two options below:
 		CONFIG_OF_EMBED
 		If this variable is defined, U-Boot will embed a device tree
 		binary in its image. This device tree file should be in the
 		board directory and called <soc>-<board>.dts. The binary file
 		is then picked up in board_init_f() and made available through
 		the global data structure as gd->blob.
 		CONFIG_OF_SEPARATE
 		If this variable is defined, U-Boot will build a device tree
 		binary. It will be called u-boot.dtb. Architecture-specific
 		code will locate it at run-time. Generally this works by:
 			cat u-boot.bin u-boot.dtb >image.bin
 		and in fact, U-Boot does this for you, creating a file called
 		u-boot-dtb.bin which is useful in the common case. You can
 		still use the individual files if you need something more
 		exotic.
 - Watchdog:
 		CONFIG_WATCHDOG
 		If this variable is defined, it enables watchdog
 		support for the SoC. There must be support in the SoC
 		specific code for a watchdog. For the 8xx and 8260
 		CPUs, the SIU Watchdog feature is enabled in the SYPCR
 		register.  When supported for a specific SoC is
 		available, then no further board specific code should
 		be needed to use it.
 		CONFIG_HW_WATCHDOG
 		When using a watchdog circuitry external to the used
 		SoC, then define this variable and provide board
 		specific code for the "hw_watchdog_reset" function.
 		CONFIG_AT91_HW_WDT_TIMEOUT
 		specify the timeout in seconds. default 2 seconds.
 - U-Boot Version:
 		CONFIG_VERSION_VARIABLE
 		If this variable is defined, an environment variable
 		named "ver" is created by U-Boot showing the U-Boot
 		version as printed by the "version" command.
 		Any change to this variable will be reverted at the
 		next reset.
 - Real-Time Clock:
 		When CONFIG_CMD_DATE is selected, the type of the RTC
 		has to be selected, too. Define exactly one of the
 		following options:
 		CONFIG_RTC_MPC8xx	- use internal RTC of MPC8xx
 		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
 		CONFIG_RTC_MC13XXX	- use MC13783 or MC13892 RTC
 		CONFIG_RTC_MC146818	- use MC146818 RTC
 		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
 		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS1339	- use Maxim, Inc. DS1339 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
 		CONFIG_RTC_ISL1208	- use Intersil ISL1208 RTC
 		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC
 		CONFIG_SYS_RTC_DS1337_NOOSC	- Turn off the OSC output for DS1337
 		CONFIG_SYS_RV3029_TCR	- enable trickle charger on
 					  RV3029 RTC.
 		Note that if the RTC uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 - GPIO Support:
 		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
 		The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
 		chip-ngpio pairs that tell the PCA953X driver the number of
 		pins supported by a particular chip.
 		Note that if the GPIO device uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 - I/O tracing:
 		When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O
 		accesses and can checksum them or write a list of them out
 		to memory. See the 'iotrace' command for details. This is
 		useful for testing device drivers since it can confirm that
 		the driver behaves the same way before and after a code
 		change. Currently this is supported on sandbox and arm. To
 		add support for your architecture, add '#include <iotrace.h>'
 		to the bottom of arch/<arch>/include/asm/io.h and test.
 		Example output from the 'iotrace stats' command is below.
 		Note that if the trace buffer is exhausted, the checksum will
 		still continue to operate.
 			iotrace is enabled
 			Start:  10000000	(buffer start address)
 			Size:   00010000	(buffer size)
 			Offset: 00000120	(current buffer offset)
 			Output: 10000120	(start + offset)
 			Count:  00000018	(number of trace records)
 			CRC32:  9526fb66	(CRC32 of all trace records)
 - Timestamp Support:
 		When CONFIG_TIMESTAMP is selected, the timestamp
 		(date and time) of an image is printed by image
 		commands like bootm or iminfo. This option is
 		automatically enabled when you select CONFIG_CMD_DATE .
 - Partition Labels (disklabels) Supported:
 		Zero or more of the following:
 		CONFIG_MAC_PARTITION   Apple's MacOS partition table.
 		CONFIG_DOS_PARTITION   MS Dos partition table, traditional on the
 				       Intel architecture, USB sticks, etc.
 		CONFIG_ISO_PARTITION   ISO partition table, used on CDROM etc.
 		CONFIG_EFI_PARTITION   GPT partition table, common when EFI is the
 				       bootloader.  Note 2TB partition limit; see
 				       disk/part_efi.c
 		CONFIG_MTD_PARTITIONS  Memory Technology Device partition table.
 		If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
 		CONFIG_SCSI) you must configure support for at
 		least one non-MTD partition type as well.
 - IDE Reset method:
 		CONFIG_IDE_RESET_ROUTINE - this is defined in several
 		board configurations files but used nowhere!
 		CONFIG_IDE_RESET - is this is defined, IDE Reset will
 		be performed by calling the function
 			ide_set_reset(int reset)
 		which has to be defined in a board specific file
 - ATAPI Support:
 		CONFIG_ATAPI
 		Set this to enable ATAPI support.
 - LBA48 Support
 		CONFIG_LBA48
 		Set this to enable support for disks larger than 137GB
 		Also look at CONFIG_SYS_64BIT_LBA.
 		Whithout these , LBA48 support uses 32bit variables and will 'only'
 		support disks up to 2.1TB.
 		CONFIG_SYS_64BIT_LBA:
 			When enabled, makes the IDE subsystem use 64bit sector addresses.
 			Default is 32bit.
 - SCSI Support:
 		At the moment only there is only support for the
 		SYM53C8XX SCSI controller; define
 		CONFIG_SCSI_SYM53C8XX to enable it.
 		CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
 		CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
 		CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
 		maximum numbers of LUNs, SCSI ID's and target
 		devices.
 		CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
 		The environment variable 'scsidevs' is set to the number of
 		SCSI devices found during the last scan.
 - NETWORK Support (PCI):
 		CONFIG_E1000
 		Support for Intel 8254x/8257x gigabit chips.
 		CONFIG_E1000_SPI
 		Utility code for direct access to the SPI bus on Intel 8257x.
 		This does not do anything useful unless you set at least one
 		of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.
 		CONFIG_E1000_SPI_GENERIC
 		Allow generic access to the SPI bus on the Intel 8257x, for
 		example with the "sspi" command.
 		CONFIG_CMD_E1000
 		Management command for E1000 devices.  When used on devices
 		with SPI support you can reprogram the EEPROM from U-Boot.
 		CONFIG_EEPRO100
 		Support for Intel 82557/82559/82559ER chips.
 		Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
 		write routine for first time initialisation.
 		CONFIG_TULIP
 		Support for Digital 2114x chips.
 		Optional CONFIG_TULIP_SELECT_MEDIA for board specific
 		modem chip initialisation (KS8761/QS6611).
 		CONFIG_NATSEMI
 		Support for National dp83815 chips.
 		CONFIG_NS8382X
 		Support for National dp8382[01] gigabit chips.
 - NETWORK Support (other):
 		CONFIG_DRIVER_AT91EMAC
 		Support for AT91RM9200 EMAC.
 			CONFIG_RMII
 			Define this to use reduced MII inteface
 			CONFIG_DRIVER_AT91EMAC_QUIET
 			If this defined, the driver is quiet.
 			The driver doen't show link status messages.
 		CONFIG_CALXEDA_XGMAC
 		Support for the Calxeda XGMAC device
 		CONFIG_LAN91C96
 		Support for SMSC's LAN91C96 chips.
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 		CONFIG_SMC91111
 		Support for SMSC's LAN91C111 chip
 			CONFIG_SMC91111_BASE
 			Define this to hold the physical address
 			of the device (I/O space)
 			CONFIG_SMC_USE_32_BIT
 			Define this if data bus is 32 bits
 			CONFIG_SMC_USE_IOFUNCS
 			Define this to use i/o functions instead of macros
 			(some hardware wont work with macros)
 		CONFIG_DRIVER_TI_EMAC
 		Support for davinci emac
 			CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
 			Define this if you have more then 3 PHYs.
 		CONFIG_FTGMAC100
 		Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
 			CONFIG_FTGMAC100_EGIGA
 			Define this to use GE link update with gigabit PHY.
 			Define this if FTGMAC100 is connected to gigabit PHY.
 			If your system has 10/100 PHY only, it might not occur
 			wrong behavior. Because PHY usually return timeout or
 			useless data when polling gigabit status and gigabit
 			control registers. This behavior won't affect the
 			correctnessof 10/100 link speed update.
 		CONFIG_SMC911X
 		Support for SMSC's LAN911x and LAN921x chips
 			CONFIG_SMC911X_BASE
 			Define this to hold the physical address
 			of the device (I/O space)
 			CONFIG_SMC911X_32_BIT
 			Define this if data bus is 32 bits
 			CONFIG_SMC911X_16_BIT
 			Define this if data bus is 16 bits. If your processor
 			automatically converts one 32 bit word to two 16 bit
 			words you may also try CONFIG_SMC911X_32_BIT.
 		CONFIG_SH_ETHER
 		Support for Renesas on-chip Ethernet controller
 			CONFIG_SH_ETHER_USE_PORT
 			Define the number of ports to be used
 			CONFIG_SH_ETHER_PHY_ADDR
 			Define the ETH PHY's address
 			CONFIG_SH_ETHER_CACHE_WRITEBACK
 			If this option is set, the driver enables cache flush.
 - PWM Support:
 		CONFIG_PWM_IMX
 		Support for PWM module on the imx6.
 - TPM Support:
 		CONFIG_TPM
 		Support TPM devices.
 		CONFIG_TPM_TIS_INFINEON
 		Support for Infineon i2c bus TPM devices. Only one device
 		per system is supported at this time.
 			CONFIG_TPM_TIS_I2C_BURST_LIMITATION
 			Define the burst count bytes upper limit
 		CONFIG_TPM_ST33ZP24
 		Support for STMicroelectronics TPM devices. Requires DM_TPM support.
 			CONFIG_TPM_ST33ZP24_I2C
 			Support for STMicroelectronics ST33ZP24 I2C devices.
 			Requires TPM_ST33ZP24 and I2C.
 			CONFIG_TPM_ST33ZP24_SPI
 			Support for STMicroelectronics ST33ZP24 SPI devices.
 			Requires TPM_ST33ZP24 and SPI.
 		CONFIG_TPM_ATMEL_TWI
 		Support for Atmel TWI TPM device. Requires I2C support.
 		CONFIG_TPM_TIS_LPC
 		Support for generic parallel port TPM devices. Only one device
 		per system is supported at this time.
 			CONFIG_TPM_TIS_BASE_ADDRESS
 			Base address where the generic TPM device is mapped
 			to. Contemporary x86 systems usually map it at
 			0xfed40000.
 		CONFIG_CMD_TPM
 		Add tpm monitor functions.
 		Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also
 		provides monitor access to authorized functions.
 		CONFIG_TPM
 		Define this to enable the TPM support library which provides
 		functional interfaces to some TPM commands.
 		Requires support for a TPM device.
 		CONFIG_TPM_AUTH_SESSIONS
 		Define this to enable authorized functions in the TPM library.
 		Requires CONFIG_TPM and CONFIG_SHA1.
 - USB Support:
 		At the moment only the UHCI host controller is
 		supported (PIP405, MIP405, MPC5200); define
 		CONFIG_USB_UHCI to enable it.
 		define CONFIG_USB_KEYBOARD to enable the USB Keyboard
 		and define CONFIG_USB_STORAGE to enable the USB
 		storage devices.
 		Note:
 		Supported are USB Keyboards and USB Floppy drives
 		(TEAC FD-05PUB).
 		MPC5200 USB requires additional defines:
 			CONFIG_USB_CLOCK
 				for 528 MHz Clock: 0x0001bbbb
 			CONFIG_PSC3_USB
 				for USB on PSC3
 			CONFIG_USB_CONFIG
 				for differential drivers: 0x00001000
 				for single ended drivers: 0x00005000
 				for differential drivers on PSC3: 0x00000100
 				for single ended drivers on PSC3: 0x00004100
 			CONFIG_SYS_USB_EVENT_POLL
 				May be defined to allow interrupt polling
 				instead of using asynchronous interrupts
 		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
 		txfilltuning field in the EHCI controller on reset.
 		CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
 		HW module registers.
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the
 		command "setenv stdin usbtty; setenv stdout usbtty" and
 		attach your USB cable. The Unix command "dmesg" should print
 		it has found a new device. The environment variable usbtty
 		can be set to gserial or cdc_acm to enable your device to
 		appear to a USB host as a Linux gserial device or a
 		Common Device Class Abstract Control Model serial device.
 		If you select usbtty = gserial you should be able to enumerate
 		a Linux host by
 		# modprobe usbserial vendor=0xVendorID product=0xProductID
 		else if using cdc_acm, simply setting the environment
 		variable usbtty to be cdc_acm should suffice. The following
 		might be defined in YourBoardName.h
 			CONFIG_USB_DEVICE
 			Define this to build a UDC device
 			CONFIG_USB_TTY
 			Define this to have a tty type of device available to
 			talk to the UDC device
 			CONFIG_USBD_HS
 			Define this to enable the high speed support for usb
 			device and usbtty. If this feature is enabled, a routine
 			int is_usbd_high_speed(void)
 			also needs to be defined by the driver to dynamically poll
 			whether the enumeration has succeded at high speed or full
 			speed.
 			CONFIG_SYS_CONSOLE_IS_IN_ENV
 			Define this if you want stdin, stdout &/or stderr to
 			be set to usbtty.
 			mpc8xx:
 				CONFIG_SYS_USB_EXTC_CLK 0xBLAH
 				Derive USB clock from external clock "blah"
 				- CONFIG_SYS_USB_EXTC_CLK 0x02
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
 		CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME,
 		CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot
 		should pretend to be a Linux device to it's target host.
 			CONFIG_USBD_MANUFACTURER
 			Define this string as the name of your company for
 			- CONFIG_USBD_MANUFACTURER "my company"
 			CONFIG_USBD_PRODUCT_NAME
 			Define this string as the name of your product
 			- CONFIG_USBD_PRODUCT_NAME "acme usb device"
 			CONFIG_USBD_VENDORID
 			Define this as your assigned Vendor ID from the USB
 			Implementors Forum. This *must* be a genuine Vendor ID
 			to avoid polluting the USB namespace.
 			- CONFIG_USBD_VENDORID 0xFFFF
 			CONFIG_USBD_PRODUCTID
 			Define this as the unique Product ID
 			for your device
 			- CONFIG_USBD_PRODUCTID 0xFFFF
 - ULPI Layer Support:
 		The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
 		the generic ULPI layer. The generic layer accesses the ULPI PHY
 		via the platform viewport, so you need both the genric layer and
 		the viewport enabled. Currently only Chipidea/ARC based
 		viewport is supported.
 		To enable the ULPI layer support, define CONFIG_USB_ULPI and
 		CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
 		If your ULPI phy needs a different reference clock than the
 		standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
 		the appropriate value in Hz.
 - MMC Support:
 		The MMC controller on the Intel PXA is supported. To
 		enable this define CONFIG_MMC. The MMC can be
 		accessed from the boot prompt by mapping the device
 		to physical memory similar to flash. Command line is
 		enabled with CONFIG_CMD_MMC. The MMC driver also works with
 		the FAT fs. This is enabled with CONFIG_CMD_FAT.
 		CONFIG_SH_MMCIF
 		Support for Renesas on-chip MMCIF controller
 			CONFIG_SH_MMCIF_ADDR
 			Define the base address of MMCIF registers
 			CONFIG_SH_MMCIF_CLK
 			Define the clock frequency for MMCIF
 		CONFIG_GENERIC_MMC
 		Enable the generic MMC driver
 		CONFIG_SUPPORT_EMMC_BOOT
 		Enable some additional features of the eMMC boot partitions.
 		CONFIG_SUPPORT_EMMC_RPMB
 		Enable the commands for reading, writing and programming the
 		key for the Replay Protection Memory Block partition in eMMC.
 - USB Device Firmware Update (DFU) class support:
 		CONFIG_USB_FUNCTION_DFU
 		This enables the USB portion of the DFU USB class
 		CONFIG_CMD_DFU
 		This enables the command "dfu" which is used to have
 		U-Boot create a DFU class device via USB.  This command
 		requires that the "dfu_alt_info" environment variable be
 		set and define the alt settings to expose to the host.
 		CONFIG_DFU_MMC
 		This enables support for exposing (e)MMC devices via DFU.
 		CONFIG_DFU_NAND
 		This enables support for exposing NAND devices via DFU.
 		CONFIG_DFU_RAM
 		This enables support for exposing RAM via DFU.
 		Note: DFU spec refer to non-volatile memory usage, but
 		allow usages beyond the scope of spec - here RAM usage,
 		one that would help mostly the developer.
 		CONFIG_SYS_DFU_DATA_BUF_SIZE
 		Dfu transfer uses a buffer before writing data to the
 		raw storage device. Make the size (in bytes) of this buffer
 		configurable. The size of this buffer is also configurable
 		through the "dfu_bufsiz" environment variable.
 		CONFIG_SYS_DFU_MAX_FILE_SIZE
 		When updating files rather than the raw storage device,
 		we use a static buffer to copy the file into and then write
 		the buffer once we've been given the whole file.  Define
 		this to the maximum filesize (in bytes) for the buffer.
 		Default is 4 MiB if undefined.
 		DFU_DEFAULT_POLL_TIMEOUT
 		Poll timeout [ms], is the timeout a device can send to the
 		host. The host must wait for this timeout before sending
 		a subsequent DFU_GET_STATUS request to the device.
 		DFU_MANIFEST_POLL_TIMEOUT
 		Poll timeout [ms], which the device sends to the host when
 		entering dfuMANIFEST state. Host waits this timeout, before
 		sending again an USB request to the device.
 - USB Device Android Fastboot support:
 		CONFIG_USB_FUNCTION_FASTBOOT
 		This enables the USB part of the fastboot gadget
 		CONFIG_CMD_FASTBOOT
 		This enables the command "fastboot" which enables the Android
 		fastboot mode for the platform's USB device. Fastboot is a USB
 		protocol for downloading images, flashing and device control
 		used on Android devices.
 		See doc/README.android-fastboot for more information.
 		CONFIG_ANDROID_BOOT_IMAGE
 		This enables support for booting images which use the Android
 		image format header.
 		CONFIG_FASTBOOT_BUF_ADDR
 		The fastboot protocol requires a large memory buffer for
 		downloads. Define this to the starting RAM address to use for
 		downloaded images.
 		CONFIG_FASTBOOT_BUF_SIZE
 		The fastboot protocol requires a large memory buffer for
 		downloads. This buffer should be as large as possible for a
 		platform. Define this to the size available RAM for fastboot.
 		CONFIG_FASTBOOT_FLASH
 		The fastboot protocol includes a "flash" command for writing
 		the downloaded image to a non-volatile storage device. Define
 		this to enable the "fastboot flash" command.
 		CONFIG_FASTBOOT_FLASH_MMC_DEV
 		The fastboot "flash" command requires additional information
 		regarding the non-volatile storage device. Define this to
 		the eMMC device that fastboot should use to store the image.
 		CONFIG_FASTBOOT_GPT_NAME
 		The fastboot "flash" command supports writing the downloaded
 		image to the Protective MBR and the Primary GUID Partition
 		Table. (Additionally, this downloaded image is post-processed
 		to generate and write the Backup GUID Partition Table.)
 		This occurs when the specified "partition name" on the
 		"fastboot flash" command line matches this value.
 		The default is "gpt" if undefined.
 		CONFIG_FASTBOOT_MBR_NAME
 		The fastboot "flash" command supports writing the downloaded
 		image to DOS MBR.
 		This occurs when the "partition name" specified on the
 		"fastboot flash" command line matches this value.
 		If not defined the default value "mbr" is used.
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND
 		Define these for a default partition on a NAND device
 		CONFIG_SYS_JFFS2_FIRST_SECTOR,
 		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
 		Define these for a default partition on a NOR device
 - FAT(File Allocation Table) filesystem write function support:
 		CONFIG_FAT_WRITE
 		Define this to enable support for saving memory data as a
 		file in FAT formatted partition.
 		This will also enable the command "fatwrite" enabling the
 		user to write files to FAT.
 CBFS (Coreboot Filesystem) support
 		CONFIG_CMD_CBFS
 		Define this to enable support for reading from a Coreboot
 		filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
 		and cbfsload.
 - FAT(File Allocation Table) filesystem cluster size:
 		CONFIG_FS_FAT_MAX_CLUSTSIZE
 		Define the max cluster size for fat operations else
 		a default value of 65536 will be defined.
 - Keyboard Support:
 		See Kconfig help for available keyboard drivers.
 		CONFIG_KEYBOARD
 		Define this to enable a custom keyboard support.
 		This simply calls drv_keyboard_init() which must be
 		defined in your board-specific files. This option is deprecated
 		and is only used by novena. For new boards, use driver model
 		instead.
 - Video support:
 		CONFIG_FSL_DIU_FB
 		Enable the Freescale DIU video driver.	Reference boards for
 		SOCs that have a DIU should define this macro to enable DIU
 		support, and should also define these other macros:
 			CONFIG_SYS_DIU_ADDR
 			CONFIG_VIDEO
 			CONFIG_CMD_BMP
 			CONFIG_CFB_CONSOLE
 			CONFIG_VIDEO_SW_CURSOR
 			CONFIG_VGA_AS_SINGLE_DEVICE
 			CONFIG_VIDEO_LOGO
 			CONFIG_VIDEO_BMP_LOGO
 		The DIU driver will look for the 'video-mode' environment
 		variable, and if defined, enable the DIU as a console during
 		boot.  See the documentation file doc/README.video for a
 		description of this variable.
 - LCD Support:	CONFIG_LCD
 		Define this to enable LCD support (for output to LCD
 		display); also select one of the supported displays
 		by defining one of these:
 		CONFIG_ATMEL_LCD:
 			HITACHI TX09D70VM1CCA, 3.5", 240x320.
 		CONFIG_NEC_NL6448AC33:
 			NEC NL6448AC33-18. Active, color, single scan.
 		CONFIG_NEC_NL6448BC20
 			NEC NL6448BC20-08. 6.5", 640x480.
 			Active, color, single scan.
 		CONFIG_NEC_NL6448BC33_54
 			NEC NL6448BC33-54. 10.4", 640x480.
 			Active, color, single scan.
 		CONFIG_SHARP_16x9
 			Sharp 320x240. Active, color, single scan.
 			It isn't 16x9, and I am not sure what it is.
 		CONFIG_SHARP_LQ64D341
 			Sharp LQ64D341 display, 640x480.
 			Active, color, single scan.
 		CONFIG_HLD1045
 			HLD1045 display, 640x480.
 			Active, color, single scan.
 		CONFIG_OPTREX_BW
 			Optrex	 CBL50840-2 NF-FW 99 22 M5
 			or
 			Hitachi	 LMG6912RPFC-00T
 			or
 			Hitachi	 SP14Q002
 			320x240. Black & white.
 		Normally display is black on white background; define
 		CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
 		CONFIG_LCD_ALIGNMENT
 		Normally the LCD is page-aligned (typically 4KB). If this is
 		defined then the LCD will be aligned to this value instead.
 		For ARM it is sometimes useful to use MMU_SECTION_SIZE
 		here, since it is cheaper to change data cache settings on
 		a per-section basis.
-		CONFIG_CONSOLE_SCROLL_LINES
-		When the console need to be scrolled, this is the number of
-		lines to scroll by. It defaults to 1. Increasing this makes
-		the console jump but can help speed up operation when scrolling
-		is slow.
 		CONFIG_LCD_ROTATION
 		Sometimes, for example if the display is mounted in portrait
 		mode or even if it's mounted landscape but rotated by 180degree,
 		we need to rotate our content of the display relative to the
 		framebuffer, so that user can read the messages which are
 		printed out.
 		Once CONFIG_LCD_ROTATION is defined, the lcd_console will be
 		initialized with a given rotation from "vl_rot" out of
 		"vidinfo_t" which is provided by the board specific code.
 		The value for vl_rot is coded as following (matching to
 		fbcon=rotate:<n> linux-kernel commandline):
 		0 = no rotation respectively 0 degree
 		1 = 90 degree rotation
 		2 = 180 degree rotation
 		3 = 270 degree rotation
 		If CONFIG_LCD_ROTATION is not defined, the console will be
 		initialized with 0degree rotation.
 		CONFIG_LCD_BMP_RLE8
 		Support drawing of RLE8-compressed bitmaps on the LCD.
 		CONFIG_I2C_EDID
 		Enables an 'i2c edid' command which can read EDID
 		information over I2C from an attached LCD display.
 - Splash Screen Support: CONFIG_SPLASH_SCREEN
 		If this option is set, the environment is checked for
 		a variable "splashimage". If found, the usual display
 		of logo, copyright and system information on the LCD
 		is suppressed and the BMP image at the address
 		specified in "splashimage" is loaded instead. The
 		console is redirected to the "nulldev", too. This
 		allows for a "silent" boot where a splash screen is
 		loaded very quickly after power-on.
 		CONFIG_SPLASHIMAGE_GUARD
 		If this option is set, then U-Boot will prevent the environment
 		variable "splashimage" from being set to a problematic address
 		(see doc/README.displaying-bmps).
 		This option is useful for targets where, due to alignment
 		restrictions, an improperly aligned BMP image will cause a data
 		abort. If you think you will not have problems with unaligned
 		accesses (for example because your toolchain prevents them)
 		there is no need to set this option.
 		CONFIG_SPLASH_SCREEN_ALIGN
 		If this option is set the splash image can be freely positioned
 		on the screen. Environment variable "splashpos" specifies the
 		position as "x,y". If a positive number is given it is used as
 		number of pixel from left/top. If a negative number is given it
 		is used as number of pixel from right/bottom. You can also
 		specify 'm' for centering the image.
 		Example:
 		setenv splashpos m,m
 			=> image at center of screen
 		setenv splashpos 30,20
 			=> image at x = 30 and y = 20
 		setenv splashpos -10,m
 			=> vertically centered image
 			   at x = dspWidth - bmpWidth - 9
 - Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
 		If this option is set, additionally to standard BMP
 		images, gzipped BMP images can be displayed via the
 		splashscreen support or the bmp command.
 - Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
 		If this option is set, 8-bit RLE compressed BMP images
 		can be displayed via the splashscreen support or the
 		bmp command.
 - Do compressing for memory range:
 		CONFIG_CMD_ZIP
 		If this option is set, it would use zlib deflate method
 		to compress the specified memory at its best effort.
 - Compression support:
 		CONFIG_GZIP
 		Enabled by default to support gzip compressed images.
 		CONFIG_BZIP2
 		If this option is set, support for bzip2 compressed
 		images is included. If not, only uncompressed and gzip
 		compressed images are supported.
 		NOTE: the bzip2 algorithm requires a lot of RAM, so
 		the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
 		be at least 4MB.
 		CONFIG_LZMA
 		If this option is set, support for lzma compressed
 		images is included.
 		Note: The LZMA algorithm adds between 2 and 4KB of code and it
 		requires an amount of dynamic memory that is given by the
 		formula:
 			(1846 + 768 << (lc + lp)) * sizeof(uint16)
 		Where lc and lp stand for, respectively, Literal context bits
 		and Literal pos bits.
 		This value is upper-bounded by 14MB in the worst case. Anyway,
 		for a ~4MB large kernel image, we have lc=3 and lp=0 for a
 		total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is
 		a very small buffer.
 		Use the lzmainfo tool to determinate the lc and lp values and
 		then calculate the amount of needed dynamic memory (ensuring
 		the appropriate CONFIG_SYS_MALLOC_LEN value).
 		CONFIG_LZO
 		If this option is set, support for LZO compressed images
 		is included.
 - MII/PHY support:
 		CONFIG_PHY_ADDR
 		The address of PHY on MII bus.
 		CONFIG_PHY_CLOCK_FREQ (ppc4xx)
 		The clock frequency of the MII bus
 		CONFIG_PHY_GIGE
 		If this option is set, support for speed/duplex
 		detection of gigabit PHY is included.
 		CONFIG_PHY_RESET_DELAY
 		Some PHY like Intel LXT971A need extra delay after
 		reset before any MII register access is possible.
 		For such PHY, set this option to the usec delay
 		required. (minimum 300usec for LXT971A)
 		CONFIG_PHY_CMD_DELAY (ppc4xx)
 		Some PHY like Intel LXT971A need extra delay after
 		command issued before MII status register can be read
 - IP address:
 		CONFIG_IPADDR
 		Define a default value for the IP address to use for
 		the default Ethernet interface, in case this is not
 		determined through e.g. bootp.
 		(Environment variable "ipaddr")
 - Server IP address:
 		CONFIG_SERVERIP
 		Defines a default value for the IP address of a TFTP
 		server to contact when using the "tftboot" command.
 		(Environment variable "serverip")
 		CONFIG_KEEP_SERVERADDR
 		Keeps the server's MAC address, in the env 'serveraddr'
 		for passing to bootargs (like Linux's netconsole option)
 - Gateway IP address:
 		CONFIG_GATEWAYIP
 		Defines a default value for the IP address of the
 		default router where packets to other networks are
 		sent to.
 		(Environment variable "gatewayip")
 - Subnet mask:
 		CONFIG_NETMASK
 		Defines a default value for the subnet mask (or
 		routing prefix) which is used to determine if an IP
 		address belongs to the local subnet or needs to be
 		forwarded through a router.
 		(Environment variable "netmask")
 - Multicast TFTP Mode:
 		CONFIG_MCAST_TFTP
 		Defines whether you want to support multicast TFTP as per
 		rfc-2090; for example to work with atftp.  Lets lots of targets
 		tftp down the same boot image concurrently.  Note: the Ethernet
 		driver in use must provide a function: mcast() to join/leave a
 		multicast group.
 - BOOTP Recovery Mode:
 		CONFIG_BOOTP_RANDOM_DELAY
 		If you have many targets in a network that try to
 		boot using BOOTP, you may want to avoid that all
 		systems send out BOOTP requests at precisely the same
 		moment (which would happen for instance at recovery
 		from a power failure, when all systems will try to
 		boot, thus flooding the BOOTP server. Defining
 		CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
 		inserted before sending out BOOTP requests. The
 		following delays are inserted then:
 		1st BOOTP request:	delay 0 ... 1 sec
 		2nd BOOTP request:	delay 0 ... 2 sec
 		3rd BOOTP request:	delay 0 ... 4 sec
 		4th and following
 		BOOTP requests:		delay 0 ... 8 sec
 		CONFIG_BOOTP_ID_CACHE_SIZE
 		BOOTP packets are uniquely identified using a 32-bit ID. The
 		server will copy the ID from client requests to responses and
 		U-Boot will use this to determine if it is the destination of
 		an incoming response. Some servers will check that addresses
 		aren't in use before handing them out (usually using an ARP
 		ping) and therefore take up to a few hundred milliseconds to
 		respond. Network congestion may also influence the time it
 		takes for a response to make it back to the client. If that
 		time is too long, U-Boot will retransmit requests. In order
 		to allow earlier responses to still be accepted after these
 		retransmissions, U-Boot's BOOTP client keeps a small cache of
 		IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this
 		cache. The default is to keep IDs for up to four outstanding
 		requests. Increasing this will allow U-Boot to accept offers
 		from a BOOTP client in networks with unusually high latency.
 - DHCP Advanced Options:
 		You can fine tune the DHCP functionality by defining
 		CONFIG_BOOTP_* symbols:
 		CONFIG_BOOTP_SUBNETMASK
 		CONFIG_BOOTP_GATEWAY
 		CONFIG_BOOTP_HOSTNAME
 		CONFIG_BOOTP_NISDOMAIN
 		CONFIG_BOOTP_BOOTPATH
 		CONFIG_BOOTP_BOOTFILESIZE
 		CONFIG_BOOTP_DNS
 		CONFIG_BOOTP_DNS2
 		CONFIG_BOOTP_SEND_HOSTNAME
 		CONFIG_BOOTP_NTPSERVER
 		CONFIG_BOOTP_TIMEOFFSET
 		CONFIG_BOOTP_VENDOREX
 		CONFIG_BOOTP_MAY_FAIL
 		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
 		environment variable, not the BOOTP server.
 		CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
 		after the configured retry count, the call will fail
 		instead of starting over.  This can be used to fail over
 		to Link-local IP address configuration if the DHCP server
 		is not available.
 		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
 		serverip from a DHCP server, it is possible that more
 		than one DNS serverip is offered to the client.
 		If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
 		serverip will be stored in the additional environment
 		variable "dnsip2". The first DNS serverip is always
 		stored in the variable "dnsip", when CONFIG_BOOTP_DNS
 		is defined.
 		CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
 		to do a dynamic update of a DNS server. To do this, they
 		need the hostname of the DHCP requester.
 		If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
 		of the "hostname" environment variable is passed as
 		option 12 to the DHCP server.
 		CONFIG_BOOTP_DHCP_REQUEST_DELAY
 		A 32bit value in microseconds for a delay between
 		receiving a "DHCP Offer" and sending the "DHCP Request".
 		This fixes a problem with certain DHCP servers that don't
 		respond 100% of the time to a "DHCP request". E.g. On an
 		AT91RM9200 processor running at 180MHz, this delay needed
 		to be *at least* 15,000 usec before a Windows Server 2003
 		DHCP server would reply 100% of the time. I recommend at
 		least 50,000 usec to be safe. The alternative is to hope
 		that one of the retries will be successful but note that
 		the DHCP timeout and retry process takes a longer than
 		this delay.
  - Link-local IP address negotiation:
 		Negotiate with other link-local clients on the local network
 		for an address that doesn't require explicit configuration.
 		This is especially useful if a DHCP server cannot be guaranteed
 		to exist in all environments that the device must operate.
 		See doc/README.link-local for more information.
  - CDP Options:
 		CONFIG_CDP_DEVICE_ID
 		The device id used in CDP trigger frames.
 		CONFIG_CDP_DEVICE_ID_PREFIX
 		A two character string which is prefixed to the MAC address
 		of the device.
 		CONFIG_CDP_PORT_ID
 		A printf format string which contains the ascii name of
 		the port. Normally is set to "eth%d" which sets
 		eth0 for the first Ethernet, eth1 for the second etc.
 		CONFIG_CDP_CAPABILITIES
 		A 32bit integer which indicates the device capabilities;
 		0x00000010 for a normal host which does not forwards.
 		CONFIG_CDP_VERSION
 		An ascii string containing the version of the software.
 		CONFIG_CDP_PLATFORM
 		An ascii string containing the name of the platform.
 		CONFIG_CDP_TRIGGER
 		A 32bit integer sent on the trigger.
 		CONFIG_CDP_POWER_CONSUMPTION
 		A 16bit integer containing the power consumption of the
 		device in .1 of milliwatts.
 		CONFIG_CDP_APPLIANCE_VLAN_TYPE
 		A byte containing the id of the VLAN.
 - Status LED:	CONFIG_STATUS_LED
 		Several configurations allow to display the current
 		status using a LED. For instance, the LED will blink
 		fast while running U-Boot code, stop blinking as
 		soon as a reply to a BOOTP request was received, and
 		start blinking slow once the Linux kernel is running
 		(supported by a status LED driver in the Linux
 		kernel). Defining CONFIG_STATUS_LED enables this
 		feature in U-Boot.
 		Additional options:
 		CONFIG_GPIO_LED
 		The status LED can be connected to a GPIO pin.
 		In such cases, the gpio_led driver can be used as a
 		status LED backend implementation. Define CONFIG_GPIO_LED
 		to include the gpio_led driver in the U-Boot binary.
 		CONFIG_GPIO_LED_INVERTED_TABLE
 		Some GPIO connected LEDs may have inverted polarity in which
 		case the GPIO high value corresponds to LED off state and
 		GPIO low value corresponds to LED on state.
 		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
 		with a list of GPIO LEDs that have inverted polarity.
 - CAN Support:	CONFIG_CAN_DRIVER
 		Defining CONFIG_CAN_DRIVER enables CAN driver support
 		on those systems that support this (optional)
 		feature, like the TQM8xxL modules.
 - I2C Support:	CONFIG_SYS_I2C
 		This enable the NEW i2c subsystem, and will allow you to use
 		i2c commands at the u-boot command line (as long as you set
 		CONFIG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c
 		based realtime clock chips or other i2c devices. See
 		common/cmd_i2c.c for a description of the command line
 		interface.
 		ported i2c driver to the new framework:
 		- drivers/i2c/soft_i2c.c:
 		  - activate first bus with CONFIG_SYS_I2C_SOFT define
 		    CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
 		    for defining speed and slave address
 		  - activate second bus with I2C_SOFT_DECLARATIONS2 define
 		    CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
 		    for defining speed and slave address
 		  - activate third bus with I2C_SOFT_DECLARATIONS3 define
 		    CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
 		    for defining speed and slave address
 		  - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
 		    CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
 		    for defining speed and slave address
 		- drivers/i2c/fsl_i2c.c:
 		  - activate i2c driver with CONFIG_SYS_I2C_FSL
 		    define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
 		    offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
 		    CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
 		    bus.
 		  - If your board supports a second fsl i2c bus, define
 		    CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
 		    CONFIG_SYS_FSL_I2C2_SPEED for the speed and
 		    CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
 		    second bus.
 		- drivers/i2c/tegra_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_TEGRA
 		  - This driver adds 4 i2c buses with a fix speed from
 		    100000 and the slave addr 0!
 		- drivers/i2c/ppc4xx_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_PPC4XX
 		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
 		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
 		- drivers/i2c/i2c_mxc.c
 		  - activate this driver with CONFIG_SYS_I2C_MXC
 		  - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
 		  - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
 		  - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
 		  - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
 		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
 		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
 		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
 		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
 		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
 		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
 		  - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
 		  - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
 		If those defines are not set, default value is 100000
 		for speed, and 0 for slave.
 		- drivers/i2c/rcar_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_RCAR
 		  - This driver adds 4 i2c buses
 		  - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
 		  - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
 		  - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
 		  - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
 		  - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
 		  - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
 		  - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
 		  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
 		  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
 		- drivers/i2c/sh_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_SH
 		  - This driver adds from 2 to 5 i2c buses
 		  - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
 		  - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
 		  - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
 		  - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
 		  - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
 		  - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
 		  - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
 		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
 		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
 		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
 		  - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
 		- drivers/i2c/omap24xx_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_OMAP24XX
 		  - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
 		  - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
 		  - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
 		  - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
 		  - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
 		  - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
 		- drivers/i2c/zynq_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_ZYNQ
 		  - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
 		  - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
 		- drivers/i2c/s3c24x0_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_S3C24X0
 		  - This driver adds i2c buses (11 for Exynos5250, Exynos5420
 		    9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
 		    with a fix speed from 100000 and the slave addr 0!
 		- drivers/i2c/ihs_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_IHS
 		  - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
 		  - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
 		  - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
 		  - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
 		  - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
 		  - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
 		  - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
 		  - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
 		  - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
 		  - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
 		  - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
 		  - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
 		  - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
 		  - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
 		  - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
 		  - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
 		  - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
 		  - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
 		  - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
 		  - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
 		  - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
 		additional defines:
 		CONFIG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c buses you want to use.
 		CONFIG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
 		if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
 		omit this define.
 		CONFIG_SYS_I2C_MAX_HOPS
 		define how many muxes are maximal consecutively connected
 		on one i2c bus. If you not use i2c muxes, omit this
 		define.
 		CONFIG_SYS_I2C_BUSES
 		hold a list of buses you want to use, only used if
 		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
 		a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
 		CONFIG_SYS_NUM_I2C_BUSES = 9:
 		 CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 4}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 5}}}, \
 					{1, {I2C_NULL_HOP}}, \
 					{1, {{I2C_MUX_PCA9544, 0x72, 1}}}, \
 					{1, {{I2C_MUX_PCA9544, 0x72, 2}}}, \
 					}
 		which defines
 			bus 0 on adapter 0 without a mux
 			bus 1 on adapter 0 with a PCA9547 on address 0x70 port 1
 			bus 2 on adapter 0 with a PCA9547 on address 0x70 port 2
 			bus 3 on adapter 0 with a PCA9547 on address 0x70 port 3
 			bus 4 on adapter 0 with a PCA9547 on address 0x70 port 4
 			bus 5 on adapter 0 with a PCA9547 on address 0x70 port 5
 			bus 6 on adapter 1 without a mux
 			bus 7 on adapter 1 with a PCA9544 on address 0x72 port 1
 			bus 8 on adapter 1 with a PCA9544 on address 0x72 port 2
 		If you do not have i2c muxes on your board, omit this define.
 - Legacy I2C Support:	CONFIG_HARD_I2C
 		NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
 		provides the following compelling advantages:
 		- more than one i2c adapter is usable
 		- approved multibus support
 		- better i2c mux support
 		** Please consider updating your I2C driver now. **
 		These enable legacy I2C serial bus commands. Defining
 		CONFIG_HARD_I2C will include the appropriate I2C driver
 		for the selected CPU.
 		This will allow you to use i2c commands at the u-boot
 		command line (as long as you set CONFIG_CMD_I2C in
 		CONFIG_COMMANDS) and communicate with i2c based realtime
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 		CONFIG_HARD_I2C selects a hardware I2C controller.
 		There are several other quantities that must also be
 		defined when you define CONFIG_HARD_I2C.
 		In both cases you will need to define CONFIG_SYS_I2C_SPEED
 		to be the frequency (in Hz) at which you wish your i2c bus
 		to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
 		the CPU's i2c node address).
 		Now, the u-boot i2c code for the mpc8xx
 		(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
 		and so its address should therefore be cleared to 0 (See,
 		eg, MPC823e User's Manual p.16-473). So, set
 		CONFIG_SYS_I2C_SLAVE to 0.
 		CONFIG_SYS_I2C_INIT_MPC5XXX
 		When a board is reset during an i2c bus transfer
 		chips might think that the current transfer is still
 		in progress.  Reset the slave devices by sending start
 		commands until the slave device responds.
 		That's all that's required for CONFIG_HARD_I2C.
 		If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
 		then the following macros need to be defined (examples are
 		from include/configs/lwmon.h):
 		I2C_INIT
 		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.
 		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
 		I2C_PORT
 		(Only for MPC8260 CPU). The I/O port to use (the code
 		assumes both bits are on the same port). Valid values
 		are 0..3 for ports A..D.
 		I2C_ACTIVE
 		The code necessary to make the I2C data line active
 		(driven).  If the data line is open collector, this
 		define can be null.
 		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)
 		I2C_TRISTATE
 		The code necessary to make the I2C data line tri-stated
 		(inactive).  If the data line is open collector, this
 		define can be null.
 		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 		I2C_READ
 		Code that returns true if the I2C data line is high,
 		false if it is low.
 		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 		I2C_SDA(bit)
 		If <bit> is true, sets the I2C data line high. If it
 		is false, it clears it (low).
 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
 		I2C_SCL(bit)
 		If <bit> is true, sets the I2C clock line high. If it
 		is false, it clears it (low).
 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 		I2C_DELAY
 		This delay is invoked four times per clock cycle so this
 		controls the rate of data transfer.  The data rate thus
 		is 1 / (I2C_DELAY * 4). Often defined to be something
 		like:
 		#define I2C_DELAY  udelay(2)
 		CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
 		If your arch supports the generic GPIO framework (asm/gpio.h),
 		then you may alternatively define the two GPIOs that are to be
 		used as SCL / SDA.  Any of the previous I2C_xxx macros will
 		have GPIO-based defaults assigned to them as appropriate.
 		You should define these to the GPIO value as given directly to
 		the generic GPIO functions.
 		CONFIG_SYS_I2C_INIT_BOARD
 		When a board is reset during an i2c bus transfer
 		chips might think that the current transfer is still
 		in progress. On some boards it is possible to access
 		the i2c SCLK line directly, either by using the
 		processor pin as a GPIO or by having a second pin
 		connected to the bus. If this option is defined a
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.
 		CONFIG_SYS_I2C_BOARD_LATE_INIT
 		An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
 		defined a custom i2c_board_late_init() routine in
 		boards/xxx/board.c is run AFTER the operations in i2c_init()
 		is completed. This callpoint can be used to unreset i2c bus
 		using CPU i2c controller register accesses for CPUs whose i2c
 		controller provide such a method. It is called at the end of
 		i2c_init() to allow i2c_init operations to setup the i2c bus
 		controller on the CPU (e.g. setting bus speed & slave address).
 		CONFIG_I2CFAST (PPC405GP|PPC405EP only)
 		This option enables configuration of bi_iic_fast[] flags
 		in u-boot bd_info structure based on u-boot environment
 		variable "i2cfast". (see also i2cfast)
 		CONFIG_I2C_MULTI_BUS
 		This option allows the use of multiple I2C buses, each of which
 		must have a controller.	 At any point in time, only one bus is
 		active.	 To switch to a different bus, use the 'i2c dev' command.
 		Note that bus numbering is zero-based.
 		CONFIG_SYS_I2C_NOPROBES
 		This option specifies a list of I2C devices that will be skipped
 		when the 'i2c probe' command is issued.	 If CONFIG_I2C_MULTI_BUS
 		is set, specify a list of bus-device pairs.  Otherwise, specify
 		a 1D array of device addresses
 		e.g.
 			#undef	CONFIG_I2C_MULTI_BUS
 			#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 			#define CONFIG_I2C_MULTI_BUS
 			#define CONFIG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 		CONFIG_SYS_SPD_BUS_NUM
 		If defined, then this indicates the I2C bus number for DDR SPD.
 		If not defined, then U-Boot assumes that SPD is on I2C bus 0.
 		CONFIG_SYS_RTC_BUS_NUM
 		If defined, then this indicates the I2C bus number for the RTC.
 		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
 		CONFIG_SYS_DTT_BUS_NUM
 		If defined, then this indicates the I2C bus number for the DTT.
 		If not defined, then U-Boot assumes that DTT is on I2C bus 0.
 		CONFIG_SYS_I2C_DTT_ADDR:
 		If defined, specifies the I2C address of the DTT device.
 		If not defined, then U-Boot uses predefined value for
 		specified DTT device.
 		CONFIG_SOFT_I2C_READ_REPEATED_START
 		defining this will force the i2c_read() function in
 		the soft_i2c driver to perform an I2C repeated start
 		between writing the address pointer and reading the
 		data.  If this define is omitted the default behaviour
 		of doing a stop-start sequence will be used.  Most I2C
 		devices can use either method, but some require one or
 		the other.
 - SPI Support:	CONFIG_SPI
 		Enables SPI driver (so far only tested with
 		SPI EEPROM, also an instance works with Crystal A/D and
 		D/As on the SACSng board)
 		CONFIG_SH_SPI
 		Enables the driver for SPI controller on SuperH. Currently
 		only SH7757 is supported.
 		CONFIG_SOFT_SPI
 		Enables a software (bit-bang) SPI driver rather than
 		using hardware support. This is a general purpose
 		driver that only requires three general I/O port pins
 		(two outputs, one input) to function. If this is
 		defined, the board configuration must define several
 		SPI configuration items (port pins to use, etc). For
 		an example, see include/configs/sacsng.h.
 		CONFIG_HARD_SPI
 		Enables a hardware SPI driver for general-purpose reads
 		and writes.  As with CONFIG_SOFT_SPI, the board configuration
 		must define a list of chip-select function pointers.
 		Currently supported on some MPC8xxx processors.	 For an
 		example, see include/configs/mpc8349emds.h.
 		CONFIG_MXC_SPI
 		Enables the driver for the SPI controllers on i.MX and MXC
 		SoCs. Currently i.MX31/35/51 are supported.
 		CONFIG_SYS_SPI_MXC_WAIT
 		Timeout for waiting until spi transfer completed.
 		default: (CONFIG_SYS_HZ/100)     /* 10 ms */
 - FPGA Support: CONFIG_FPGA
 		Enables FPGA subsystem.
 		CONFIG_FPGA_<vendor>
 		Enables support for specific chip vendors.
 		(ALTERA, XILINX)
 		CONFIG_FPGA_<family>
 		Enables support for FPGA family.
 		(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
 		CONFIG_FPGA_COUNT
 		Specify the number of FPGA devices to support.
 		CONFIG_CMD_FPGA_LOADMK
 		Enable support for fpga loadmk command
 		CONFIG_CMD_FPGA_LOADP
 		Enable support for fpga loadp command - load partial bitstream
 		CONFIG_CMD_FPGA_LOADBP
 		Enable support for fpga loadbp command - load partial bitstream
 		(Xilinx only)
 		CONFIG_SYS_FPGA_PROG_FEEDBACK
 		Enable printing of hash marks during FPGA configuration.
 		CONFIG_SYS_FPGA_CHECK_BUSY
 		Enable checks on FPGA configuration interface busy
 		status by the configuration function. This option
 		will require a board or device specific function to
 		be written.
 		CONFIG_FPGA_DELAY
 		If defined, a function that provides delays in the FPGA
 		configuration driver.
 		CONFIG_SYS_FPGA_CHECK_CTRLC
 		Allow Control-C to interrupt FPGA configuration
 		CONFIG_SYS_FPGA_CHECK_ERROR
 		Check for configuration errors during FPGA bitfile
 		loading. For example, abort during Virtex II
 		configuration if the INIT_B line goes low (which
 		indicated a CRC error).
 		CONFIG_SYS_FPGA_WAIT_INIT
 		Maximum time to wait for the INIT_B line to de-assert
 		after PROB_B has been de-asserted during a Virtex II
 		FPGA configuration sequence. The default time is 500
 		ms.
 		CONFIG_SYS_FPGA_WAIT_BUSY
 		Maximum time to wait for BUSY to de-assert during
 		Virtex II FPGA configuration. The default is 5 ms.
 		CONFIG_SYS_FPGA_WAIT_CONFIG
 		Time to wait after FPGA configuration. The default is
 		200 ms.
 - Configuration Management:
 		CONFIG_BUILD_TARGET
 		Some SoCs need special image types (e.g. U-Boot binary
 		with a special header) as build targets. By defining
 		CONFIG_BUILD_TARGET in the SoC / board header, this
 		special image will be automatically built upon calling
 		make / buildman.
 		CONFIG_IDENT_STRING
 		If defined, this string will be added to the U-Boot
 		version information (U_BOOT_VERSION)
 - Vendor Parameter Protection:
 		U-Boot considers the values of the environment
 		variables "serial#" (Board Serial Number) and
 		"ethaddr" (Ethernet Address) to be parameters that
 		are set once by the board vendor / manufacturer, and
 		protects these variables from casual modification by
 		the user. Once set, these variables are read-only,
 		and write or delete attempts are rejected. You can
 		change this behaviour:
 		If CONFIG_ENV_OVERWRITE is #defined in your config
 		file, the write protection for vendor parameters is
 		completely disabled. Anybody can change or delete
 		these parameters.
 		Alternatively, if you define _both_ an ethaddr in the
 		default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
 		Ethernet address is installed in the environment,
 		which can be changed exactly ONCE by the user. [The
 		serial# is unaffected by this, i. e. it remains
 		read-only.]
 		The same can be accomplished in a more flexible way
 		for any variable by configuring the type of access
 		to allow for those variables in the ".flags" variable
 		or define CONFIG_ENV_FLAGS_LIST_STATIC.
 - Protected RAM:
 		CONFIG_PRAM
 		Define this variable to enable the reservation of
 		"protected RAM", i. e. RAM which is not overwritten
 		by U-Boot. Define CONFIG_PRAM to hold the number of
 		kB you want to reserve for pRAM. You can overwrite
 		this default value by defining an environment
 		variable "pram" to the number of kB you want to
 		reserve. Note that the board info structure will
 		still show the full amount of RAM. If pRAM is
 		reserved, a new environment variable "mem" will
 		automatically be defined to hold the amount of
 		remaining RAM in a form that can be passed as boot
 		argument to Linux, for instance like that:
 			setenv bootargs ... mem=\${mem}
 			saveenv
 		This way you can tell Linux not to use this memory,
 		either, which results in a memory region that will
 		not be affected by reboots.
 		*WARNING* If your board configuration uses automatic
 		detection of the RAM size, you must make sure that
 		this memory test is non-destructive. So far, the
 		following board configurations are known to be
 		"pRAM-clean":
 			IVMS8, IVML24, SPD8xx, TQM8xxL,
 			HERMES, IP860, RPXlite, LWMON,
 			FLAGADM, TQM8260
 - Access to physical memory region (> 4GB)
 		Some basic support is provided for operations on memory not
 		normally accessible to U-Boot - e.g. some architectures
 		support access to more than 4GB of memory on 32-bit
 		machines using physical address extension or similar.
 		Define CONFIG_PHYSMEM to access this basic support, which
 		currently only supports clearing the memory.
 - Error Recovery:
 		CONFIG_PANIC_HANG
 		Define this variable to stop the system in case of a
 		fatal error, so that you have to reset it manually.
 		This is probably NOT a good idea for an embedded
 		system where you want the system to reboot
 		automatically as fast as possible, but it may be
 		useful during development since you can try to debug
 		the conditions that lead to the situation.
 		CONFIG_NET_RETRY_COUNT
 		This variable defines the number of retries for
 		network operations like ARP, RARP, TFTP, or BOOTP
 		before giving up the operation. If not defined, a
 		default value of 5 is used.
 		CONFIG_ARP_TIMEOUT
 		Timeout waiting for an ARP reply in milliseconds.
 		CONFIG_NFS_TIMEOUT
 		Timeout in milliseconds used in NFS protocol.
 		If you encounter "ERROR: Cannot umount" in nfs command,
 		try longer timeout such as
 		#define CONFIG_NFS_TIMEOUT 10000UL
 - Command Interpreter:
 		CONFIG_AUTO_COMPLETE
 		Enable auto completion of commands using TAB.
 		CONFIG_SYS_PROMPT_HUSH_PS2
 		This defines the secondary prompt string, which is
 		printed when the command interpreter needs more input
 		to complete a command. Usually "> ".
 	Note:
 		In the current implementation, the local variables
 		space and global environment variables space are
 		separated. Local variables are those you define by
 		simply typing `name=value'. To access a local
 		variable later on, you have write `$name' or
 		`${name}'; to execute the contents of a variable
 		directly type `$name' at the command prompt.
 		Global environment variables are those you use
 		setenv/printenv to work with. To run a command stored
 		in such a variable, you need to use the run command,
 		and you must not use the '$' sign to access them.
 		To store commands and special characters in a
 		variable, please use double quotation marks
 		surrounding the whole text of the variable, instead
 		of the backslashes before semicolons and special
 		symbols.
 - Command Line Editing and History:
 		CONFIG_CMDLINE_EDITING
 		Enable editing and History functions for interactive
 		command line input operations
 - Command Line PS1/PS2 support:
 		CONFIG_CMDLINE_PS_SUPPORT
 		Enable support for changing the command prompt string
 		at run-time. Only static string is supported so far.
 		The string is obtained from environment variables PS1
 		and PS2.
 - Default Environment:
 		CONFIG_EXTRA_ENV_SETTINGS
 		Define this to contain any number of null terminated
 		strings (variable = value pairs) that will be part of
 		the default environment compiled into the boot image.
 		For example, place something like this in your
 		board's config file:
 		#define CONFIG_EXTRA_ENV_SETTINGS \
 			"myvar1=value1\0" \
 			"myvar2=value2\0"
 		Warning: This method is based on knowledge about the
 		internal format how the environment is stored by the
 		U-Boot code. This is NOT an official, exported
 		interface! Although it is unlikely that this format
 		will change soon, there is no guarantee either.
 		You better know what you are doing here.
 		Note: overly (ab)use of the default environment is
 		discouraged. Make sure to check other ways to preset
 		the environment like the "source" command or the
 		boot command first.
 		CONFIG_ENV_VARS_UBOOT_CONFIG
 		Define this in order to add variables describing the
 		U-Boot build configuration to the default environment.
 		These will be named arch, cpu, board, vendor, and soc.
 		Enabling this option will cause the following to be defined:
 		- CONFIG_SYS_ARCH
 		- CONFIG_SYS_CPU
 		- CONFIG_SYS_BOARD
 		- CONFIG_SYS_VENDOR
 		- CONFIG_SYS_SOC
 		CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 		Define this in order to add variables describing certain
 		run-time determined information about the hardware to the
 		environment.  These will be named board_name, board_rev.
 		CONFIG_DELAY_ENVIRONMENT
 		Normally the environment is loaded when the board is
 		initialised so that it is available to U-Boot. This inhibits
 		that so that the environment is not available until
 		explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
 		this is instead controlled by the value of
 		/config/load-environment.
 - Parallel Flash support:
 		CONFIG_SYS_NO_FLASH
 		Traditionally U-Boot was run on systems with parallel NOR
 		flash. This option is used to disable support for parallel NOR
 		flash. This option should be defined if the board does not have
 		parallel flash.
 		If this option is not defined one of the generic flash drivers
 		(e.g.  CONFIG_FLASH_CFI_DRIVER or CONFIG_ST_SMI) must be
 		selected or the board must provide an implementation of the
 		flash API (see include/flash.h).
 - DataFlash Support:
 		CONFIG_HAS_DATAFLASH
 		Defining this option enables DataFlash features and
 		allows to read/write in Dataflash via the standard
 		commands cp, md...
 - Serial Flash support
 		CONFIG_CMD_SF
 		Defining this option enables SPI flash commands
 		'sf probe/read/write/erase/update'.
 		Usage requires an initial 'probe' to define the serial
 		flash parameters, followed by read/write/erase/update
 		commands.
 		The following defaults may be provided by the platform
 		to handle the common case when only a single serial
 		flash is present on the system.
 		CONFIG_SF_DEFAULT_BUS		Bus identifier
 		CONFIG_SF_DEFAULT_CS		Chip-select
 		CONFIG_SF_DEFAULT_MODE 		(see include/spi.h)
 		CONFIG_SF_DEFAULT_SPEED		in Hz
 		CONFIG_CMD_SF_TEST
 		Define this option to include a destructive SPI flash
 		test ('sf test').
 		CONFIG_SF_DUAL_FLASH		Dual flash memories
 		Define this option to use dual flash support where two flash
 		memories can be connected with a given cs line.
 		Currently Xilinx Zynq qspi supports these type of connections.
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 		Adding this option adds support for Xilinx SystemACE
 		chips attached via some sort of local bus. The address
 		of the chip must also be defined in the
 		CONFIG_SYS_SYSTEMACE_BASE macro. For example:
 		#define CONFIG_SYSTEMACE
 		#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
 		When SystemACE support is added, the "ace" device type
 		becomes available to the fat commands, i.e. fatls.
 - TFTP Fixed UDP Port:
 		CONFIG_TFTP_PORT
 		If this is defined, the environment variable tftpsrcp
 		is used to supply the TFTP UDP source port value.
 		If tftpsrcp isn't defined, the normal pseudo-random port
 		number generator is used.
 		Also, the environment variable tftpdstp is used to supply
 		the TFTP UDP destination port value.  If tftpdstp isn't
 		defined, the normal port 69 is used.
 		The purpose for tftpsrcp is to allow a TFTP server to
 		blindly start the TFTP transfer using the pre-configured
 		target IP address and UDP port. This has the effect of
 		"punching through" the (Windows XP) firewall, allowing
 		the remainder of the TFTP transfer to proceed normally.
 		A better solution is to properly configure the firewall,
 		but sometimes that is not allowed.
 - Hashing support:
 		CONFIG_CMD_HASH
 		This enables a generic 'hash' command which can produce
 		hashes / digests from a few algorithms (e.g. SHA1, SHA256).
 		CONFIG_HASH_VERIFY
 		Enable the hash verify command (hash -v). This adds to code
 		size a little.
 		CONFIG_SHA1 - This option enables support of hashing using SHA1
 		algorithm. The hash is calculated in software.
 		CONFIG_SHA256 - This option enables support of hashing using
 		SHA256 algorithm. The hash is calculated in software.
 		CONFIG_SHA_HW_ACCEL - This option enables hardware acceleration
 		for SHA1/SHA256 hashing.
 		This affects the 'hash' command and also the
 		hash_lookup_algo() function.
 		CONFIG_SHA_PROG_HW_ACCEL - This option enables
 		hardware-acceleration for SHA1/SHA256 progressive hashing.
 		Data can be streamed in a block at a time and the hashing
 		is performed in hardware.
 		Note: There is also a sha1sum command, which should perhaps
 		be deprecated in favour of 'hash sha1'.
 - Freescale i.MX specific commands:
 		CONFIG_CMD_HDMIDETECT
 		This enables 'hdmidet' command which returns true if an
 		HDMI monitor is detected.  This command is i.MX 6 specific.
 		CONFIG_CMD_BMODE
 		This enables the 'bmode' (bootmode) command for forcing
 		a boot from specific media.
 		This is useful for forcing the ROM's usb downloader to
 		activate upon a watchdog reset which is nice when iterating
 		on U-Boot.  Using the reset button or running bmode normal
 		will set it back to normal.  This command currently
 		supports i.MX53 and i.MX6.
 - bootcount support:
 		CONFIG_BOOTCOUNT_LIMIT
 		This enables the bootcounter support, see:
 		http://www.denx.de/wiki/DULG/UBootBootCountLimit
 		CONFIG_AT91SAM9XE
 		enable special bootcounter support on at91sam9xe based boards.
 		CONFIG_BLACKFIN
 		enable special bootcounter support on blackfin based boards.
 		CONFIG_SOC_DA8XX
 		enable special bootcounter support on da850 based boards.
 		CONFIG_BOOTCOUNT_RAM
 		enable support for the bootcounter in RAM
 		CONFIG_BOOTCOUNT_I2C
 		enable support for the bootcounter on an i2c (like RTC) device.
 			CONFIG_SYS_I2C_RTC_ADDR = i2c chip address
 			CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
 						    the bootcounter.
 			CONFIG_BOOTCOUNT_ALEN = address len
 - Show boot progress:
 		CONFIG_SHOW_BOOT_PROGRESS
 		Defining this option allows to add some board-
 		specific code (calling a user-provided function
 		"show_boot_progress(int)") that enables you to show
 		the system's boot progress on some display (for
 		example, some LED's) on your board. At the moment,
 		the following checkpoints are implemented:
 Legacy uImage format:
   Arg	Where			When
     1	common/cmd_bootm.c	before attempting to boot an image
    -1	common/cmd_bootm.c	Image header has bad	 magic number
     2	common/cmd_bootm.c	Image header has correct magic number
    -2	common/cmd_bootm.c	Image header has bad	 checksum
     3	common/cmd_bootm.c	Image header has correct checksum
    -3	common/cmd_bootm.c	Image data   has bad	 checksum
     4	common/cmd_bootm.c	Image data   has correct checksum
    -4	common/cmd_bootm.c	Image is for unsupported architecture
     5	common/cmd_bootm.c	Architecture check OK
    -5	common/cmd_bootm.c	Wrong Image Type (not kernel, multi)
     6	common/cmd_bootm.c	Image Type check OK
    -6	common/cmd_bootm.c	gunzip uncompression error
    -7	common/cmd_bootm.c	Unimplemented compression type
     7	common/cmd_bootm.c	Uncompression OK
     8	common/cmd_bootm.c	No uncompress/copy overwrite error
    -9	common/cmd_bootm.c	Unsupported OS (not Linux, BSD, VxWorks, QNX)
     9	common/image.c		Start initial ramdisk verification
   -10	common/image.c		Ramdisk header has bad	   magic number
   -11	common/image.c		Ramdisk header has bad	   checksum
    10	common/image.c		Ramdisk header is OK
   -12	common/image.c		Ramdisk data   has bad	   checksum
    11	common/image.c		Ramdisk data   has correct checksum
    12	common/image.c		Ramdisk verification complete, start loading
   -13	common/image.c		Wrong Image Type (not PPC Linux ramdisk)
    13	common/image.c		Start multifile image verification
    14	common/image.c		No initial ramdisk, no multifile, continue.
    15	arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
   -30	arch/powerpc/lib/board.c	Fatal error, hang the system
   -31	post/post.c		POST test failed, detected by post_output_backlog()
   -32	post/post.c		POST test failed, detected by post_run_single()
    34	common/cmd_doc.c	before loading a Image from a DOC device
   -35	common/cmd_doc.c	Bad usage of "doc" command
    35	common/cmd_doc.c	correct usage of "doc" command
   -36	common/cmd_doc.c	No boot device
    36	common/cmd_doc.c	correct boot device
   -37	common/cmd_doc.c	Unknown Chip ID on boot device
    37	common/cmd_doc.c	correct chip ID found, device available
   -38	common/cmd_doc.c	Read Error on boot device
    38	common/cmd_doc.c	reading Image header from DOC device OK
   -39	common/cmd_doc.c	Image header has bad magic number
    39	common/cmd_doc.c	Image header has correct magic number
   -40	common/cmd_doc.c	Error reading Image from DOC device
    40	common/cmd_doc.c	Image header has correct magic number
    41	common/cmd_ide.c	before loading a Image from a IDE device
   -42	common/cmd_ide.c	Bad usage of "ide" command
    42	common/cmd_ide.c	correct usage of "ide" command
   -43	common/cmd_ide.c	No boot device
    43	common/cmd_ide.c	boot device found
   -44	common/cmd_ide.c	Device not available
    44	common/cmd_ide.c	Device available
   -45	common/cmd_ide.c	wrong partition selected
    45	common/cmd_ide.c	partition selected
   -46	common/cmd_ide.c	Unknown partition table
    46	common/cmd_ide.c	valid partition table found
   -47	common/cmd_ide.c	Invalid partition type
    47	common/cmd_ide.c	correct partition type
   -48	common/cmd_ide.c	Error reading Image Header on boot device
    48	common/cmd_ide.c	reading Image Header from IDE device OK
   -49	common/cmd_ide.c	Image header has bad magic number
    49	common/cmd_ide.c	Image header has correct magic number
   -50	common/cmd_ide.c	Image header has bad	 checksum
    50	common/cmd_ide.c	Image header has correct checksum
   -51	common/cmd_ide.c	Error reading Image from IDE device
    51	common/cmd_ide.c	reading Image from IDE device OK
    52	common/cmd_nand.c	before loading a Image from a NAND device
   -53	common/cmd_nand.c	Bad usage of "nand" command
    53	common/cmd_nand.c	correct usage of "nand" command
   -54	common/cmd_nand.c	No boot device
    54	common/cmd_nand.c	boot device found
   -55	common/cmd_nand.c	Unknown Chip ID on boot device
    55	common/cmd_nand.c	correct chip ID found, device available
   -56	common/cmd_nand.c	Error reading Image Header on boot device
    56	common/cmd_nand.c	reading Image Header from NAND device OK
   -57	common/cmd_nand.c	Image header has bad magic number
    57	common/cmd_nand.c	Image header has correct magic number
   -58	common/cmd_nand.c	Error reading Image from NAND device
    58	common/cmd_nand.c	reading Image from NAND device OK
   -60	common/env_common.c	Environment has a bad CRC, using default
    64	net/eth.c		starting with Ethernet configuration.
   -64	net/eth.c		no Ethernet found.
    65	net/eth.c		Ethernet found.
   -80	common/cmd_net.c	usage wrong
    80	common/cmd_net.c	before calling net_loop()
   -81	common/cmd_net.c	some error in net_loop() occurred
    81	common/cmd_net.c	net_loop() back without error
   -82	common/cmd_net.c	size == 0 (File with size 0 loaded)
    82	common/cmd_net.c	trying automatic boot
    83	common/cmd_net.c	running "source" command
   -83	common/cmd_net.c	some error in automatic boot or "source" command
    84	common/cmd_net.c	end without errors
 FIT uImage format:
   Arg	Where			When
   100	common/cmd_bootm.c	Kernel FIT Image has correct format
  -100	common/cmd_bootm.c	Kernel FIT Image has incorrect format
   101	common/cmd_bootm.c	No Kernel subimage unit name, using configuration
  -101	common/cmd_bootm.c	Can't get configuration for kernel subimage
   102	common/cmd_bootm.c	Kernel unit name specified
  -103	common/cmd_bootm.c	Can't get kernel subimage node offset
   103	common/cmd_bootm.c	Found configuration node
   104	common/cmd_bootm.c	Got kernel subimage node offset
  -104	common/cmd_bootm.c	Kernel subimage hash verification failed
   105	common/cmd_bootm.c	Kernel subimage hash verification OK
  -105	common/cmd_bootm.c	Kernel subimage is for unsupported architecture
   106	common/cmd_bootm.c	Architecture check OK
  -106	common/cmd_bootm.c	Kernel subimage has wrong type
   107	common/cmd_bootm.c	Kernel subimage type OK
  -107	common/cmd_bootm.c	Can't get kernel subimage data/size
   108	common/cmd_bootm.c	Got kernel subimage data/size
  -108	common/cmd_bootm.c	Wrong image type (not legacy, FIT)
  -109	common/cmd_bootm.c	Can't get kernel subimage type
  -110	common/cmd_bootm.c	Can't get kernel subimage comp
  -111	common/cmd_bootm.c	Can't get kernel subimage os
  -112	common/cmd_bootm.c	Can't get kernel subimage load address
  -113	common/cmd_bootm.c	Image uncompress/copy overwrite error
   120	common/image.c		Start initial ramdisk verification
  -120	common/image.c		Ramdisk FIT image has incorrect format
   121	common/image.c		Ramdisk FIT image has correct format
   122	common/image.c		No ramdisk subimage unit name, using configuration
  -122	common/image.c		Can't get configuration for ramdisk subimage
   123	common/image.c		Ramdisk unit name specified
  -124	common/image.c		Can't get ramdisk subimage node offset
   125	common/image.c		Got ramdisk subimage node offset
  -125	common/image.c		Ramdisk subimage hash verification failed
   126	common/image.c		Ramdisk subimage hash verification OK
  -126	common/image.c		Ramdisk subimage for unsupported architecture
   127	common/image.c		Architecture check OK
  -127	common/image.c		Can't get ramdisk subimage data/size
   128	common/image.c		Got ramdisk subimage data/size
   129	common/image.c		Can't get ramdisk load address
  -129	common/image.c		Got ramdisk load address
  -130	common/cmd_doc.c	Incorrect FIT image format
   131	common/cmd_doc.c	FIT image format OK
  -140	common/cmd_ide.c	Incorrect FIT image format
   141	common/cmd_ide.c	FIT image format OK
  -150	common/cmd_nand.c	Incorrect FIT image format
   151	common/cmd_nand.c	FIT image format OK
 - legacy image format:
 		CONFIG_IMAGE_FORMAT_LEGACY
 		enables the legacy image format support in U-Boot.
 		Default:
 		enabled if CONFIG_FIT_SIGNATURE is not defined.
 		CONFIG_DISABLE_IMAGE_LEGACY
 		disable the legacy image format
 		This define is introduced, as the legacy image format is
 		enabled per default for backward compatibility.
 - FIT image support:
 		CONFIG_FIT_DISABLE_SHA256
 		Supporting SHA256 hashes has quite an impact on binary size.
 		For constrained systems sha256 hash support can be disabled
 		with this option.
 		TODO(sjg@chromium.org): Adjust this option to be positive,
 		and move it to Kconfig
 - Standalone program support:
 		CONFIG_STANDALONE_LOAD_ADDR
 		This option defines a board specific value for the
 		address where standalone program gets loaded, thus
 		overwriting the architecture dependent default
 		settings.
 - Frame Buffer Address:
 		CONFIG_FB_ADDR
 		Define CONFIG_FB_ADDR if you want to use specific
 		address for frame buffer.  This is typically the case
 		when using a graphics controller has separate video
 		memory.  U-Boot will then place the frame buffer at
 		the given address instead of dynamically reserving it
 		in system RAM by calling lcd_setmem(), which grabs
 		the memory for the frame buffer depending on the
 		configured panel size.
 		Please see board_init_f function.
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
 		CONFIG_UPDATE_TFTP_MSEC_MAX
 		These options enable and control the auto-update feature;
 		for a more detailed description refer to doc/README.update.
 - MTD Support (mtdparts command, UBI support)
 		CONFIG_MTD_DEVICE
 		Adds the MTD device infrastructure from the Linux kernel.
 		Needed for mtdparts command support.
 		CONFIG_MTD_PARTITIONS
 		Adds the MTD partitioning infrastructure from the Linux
 		kernel. Needed for UBI support.
 - UBI support
 		CONFIG_CMD_UBI
 		Adds commands for interacting with MTD partitions formatted
 		with the UBI flash translation layer
 		Requires also defining CONFIG_RBTREE
 		CONFIG_UBI_SILENCE_MSG
 		Make the verbose messages from UBI stop printing.  This leaves
 		warnings and errors enabled.
 		CONFIG_MTD_UBI_WL_THRESHOLD
 		This parameter defines the maximum difference between the highest
 		erase counter value and the lowest erase counter value of eraseblocks
 		of UBI devices. When this threshold is exceeded, UBI starts performing
 		wear leveling by means of moving data from eraseblock with low erase
 		counter to eraseblocks with high erase counter.
 		The default value should be OK for SLC NAND flashes, NOR flashes and
 		other flashes which have eraseblock life-cycle 100000 or more.
 		However, in case of MLC NAND flashes which typically have eraseblock
 		life-cycle less than 10000, the threshold should be lessened (e.g.,
 		to 128 or 256, although it does not have to be power of 2).
 		default: 4096
 		CONFIG_MTD_UBI_BEB_LIMIT
 		This option specifies the maximum bad physical eraseblocks UBI
 		expects on the MTD device (per 1024 eraseblocks). If the
 		underlying flash does not admit of bad eraseblocks (e.g. NOR
 		flash), this value is ignored.
 		NAND datasheets often specify the minimum and maximum NVM
 		(Number of Valid Blocks) for the flashes' endurance lifetime.
 		The maximum expected bad eraseblocks per 1024 eraseblocks
 		then can be calculated as "1024 * (1 - MinNVB / MaxNVB)",
 		which gives 20 for most NANDs (MaxNVB is basically the total
 		count of eraseblocks on the chip).
 		To put it differently, if this value is 20, UBI will try to
 		reserve about 1.9% of physical eraseblocks for bad blocks
 		handling. And that will be 1.9% of eraseblocks on the entire
 		NAND chip, not just the MTD partition UBI attaches. This means
 		that if you have, say, a NAND flash chip admits maximum 40 bad
 		eraseblocks, and it is split on two MTD partitions of the same
 		size, UBI will reserve 40 eraseblocks when attaching a
 		partition.
 		default: 20
 		CONFIG_MTD_UBI_FASTMAP
 		Fastmap is a mechanism which allows attaching an UBI device
 		in nearly constant time. Instead of scanning the whole MTD device it
 		only has to locate a checkpoint (called fastmap) on the device.
 		The on-flash fastmap contains all information needed to attach
 		the device. Using fastmap makes only sense on large devices where
 		attaching by scanning takes long. UBI will not automatically install
 		a fastmap on old images, but you can set the UBI parameter
 		CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT to 1 if you want so. Please note
 		that fastmap-enabled images are still usable with UBI implementations
 		without	fastmap support. On typical flash devices the whole fastmap
 		fits into one PEB. UBI will reserve PEBs to hold two fastmaps.
 		CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT
 		Set this parameter to enable fastmap automatically on images
 		without a fastmap.
 		default: 0
 		CONFIG_MTD_UBI_FM_DEBUG
 		Enable UBI fastmap debug
 		default: 0
 - UBIFS support
 		CONFIG_CMD_UBIFS
 		Adds commands for interacting with UBI volumes formatted as
 		UBIFS.  UBIFS is read-only in u-boot.
 		Requires UBI support as well as CONFIG_LZO
 		CONFIG_UBIFS_SILENCE_MSG
 		Make the verbose messages from UBIFS stop printing.  This leaves
 		warnings and errors enabled.
 - SPL framework
 		CONFIG_SPL
 		Enable building of SPL globally.
 		CONFIG_SPL_LDSCRIPT
 		LDSCRIPT for linking the SPL binary.
 		CONFIG_SPL_MAX_FOOTPRINT
 		Maximum size in memory allocated to the SPL, BSS included.
 		When defined, the linker checks that the actual memory
 		used by SPL from _start to __bss_end does not exceed it.
 		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
 		must not be both defined at the same time.
 		CONFIG_SPL_MAX_SIZE
 		Maximum size of the SPL image (text, data, rodata, and
 		linker lists sections), BSS excluded.
 		When defined, the linker checks that the actual size does
 		not exceed it.
 		CONFIG_SPL_TEXT_BASE
 		TEXT_BASE for linking the SPL binary.
 		CONFIG_SPL_RELOC_TEXT_BASE
 		Address to relocate to.  If unspecified, this is equal to
 		CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
 		CONFIG_SPL_BSS_START_ADDR
 		Link address for the BSS within the SPL binary.
 		CONFIG_SPL_BSS_MAX_SIZE
 		Maximum size in memory allocated to the SPL BSS.
 		When defined, the linker checks that the actual memory used
 		by SPL from __bss_start to __bss_end does not exceed it.
 		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
 		must not be both defined at the same time.
 		CONFIG_SPL_STACK
 		Adress of the start of the stack SPL will use
 		CONFIG_SPL_PANIC_ON_RAW_IMAGE
 		When defined, SPL will panic() if the image it has
 		loaded does not have a signature.
 		Defining this is useful when code which loads images
 		in SPL cannot guarantee that absolutely all read errors
 		will be caught.
 		An example is the LPC32XX MLC NAND driver, which will
 		consider that a completely unreadable NAND block is bad,
 		and thus should be skipped silently.
 		CONFIG_SPL_ABORT_ON_RAW_IMAGE
 		When defined, SPL will proceed to another boot method
 		if the image it has loaded does not have a signature.
 		CONFIG_SPL_RELOC_STACK
 		Adress of the start of the stack SPL will use after
 		relocation.  If unspecified, this is equal to
 		CONFIG_SPL_STACK.
 		CONFIG_SYS_SPL_MALLOC_START
 		Starting address of the malloc pool used in SPL.
 		When this option is set the full malloc is used in SPL and
 		it is set up by spl_init() and before that, the simple malloc()
 		can be used if CONFIG_SYS_MALLOC_F is defined.
 		CONFIG_SYS_SPL_MALLOC_SIZE
 		The size of the malloc pool used in SPL.
 		CONFIG_SPL_FRAMEWORK
 		Enable the SPL framework under common/.  This framework
 		supports MMC, NAND and YMODEM loading of U-Boot and NAND
 		NAND loading of the Linux Kernel.
 		CONFIG_SPL_OS_BOOT
 		Enable booting directly to an OS from SPL.
 		See also: doc/README.falcon
 		CONFIG_SPL_DISPLAY_PRINT
 		For ARM, enable an optional function to print more information
 		about the running system.
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
 		CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
 		Address and partition on the MMC to load U-Boot from
 		when the MMC is being used in raw mode.
 		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 		Partition on the MMC to load U-Boot from when the MMC is being
 		used in raw mode
 		CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
 		Sector to load kernel uImage from when MMC is being
 		used in raw mode (for Falcon mode)
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
 		Sector and number of sectors to load kernel argument
 		parameters from when MMC is being used in raw mode
 		(for falcon mode)
 		CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
 		Partition on the MMC to load U-Boot from when the MMC is being
 		used in fs mode
 		CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
 		Filename to read to load U-Boot when reading from filesystem
 		CONFIG_SPL_FS_LOAD_KERNEL_NAME
 		Filename to read to load kernel uImage when reading
 		from filesystem (for Falcon mode)
 		CONFIG_SPL_FS_LOAD_ARGS_NAME
 		Filename to read to load kernel argument parameters
 		when reading from filesystem (for Falcon mode)
 		CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
 		Set this for NAND SPL on PPC mpc83xx targets, so that
 		start.S waits for the rest of the SPL to load before
 		continuing (the hardware starts execution after just
 		loading the first page rather than the full 4K).
 		CONFIG_SPL_SKIP_RELOCATE
 		Avoid SPL relocation
 		CONFIG_SPL_NAND_BASE
 		Include nand_base.c in the SPL.  Requires
 		CONFIG_SPL_NAND_DRIVERS.
 		CONFIG_SPL_NAND_DRIVERS
 		SPL uses normal NAND drivers, not minimal drivers.
 		CONFIG_SPL_NAND_ECC
 		Include standard software ECC in the SPL
 		CONFIG_SPL_NAND_SIMPLE
 		Support for NAND boot using simple NAND drivers that
 		expose the cmd_ctrl() interface.
 		CONFIG_SPL_UBI
 		Support for a lightweight UBI (fastmap) scanner and
 		loader
 		CONFIG_SPL_NAND_RAW_ONLY
 		Support to boot only raw u-boot.bin images. Use this only
 		if you need to save space.
 		CONFIG_SPL_COMMON_INIT_DDR
 		Set for common ddr init with serial presence detect in
 		SPL binary.
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
 		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
 		CONFIG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 		CONFIG_SPL_NAND_BOOT
 		Add support NAND boot
 		CONFIG_SYS_NAND_U_BOOT_OFFS
 		Location in NAND to read U-Boot from
 		CONFIG_SYS_NAND_U_BOOT_DST
 		Location in memory to load U-Boot to
 		CONFIG_SYS_NAND_U_BOOT_SIZE
 		Size of image to load
 		CONFIG_SYS_NAND_U_BOOT_START
 		Entry point in loaded image to jump to
 		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 		Define this if you need to first read the OOB and then the
 		data. This is used, for example, on davinci platforms.
 		CONFIG_SPL_OMAP3_ID_NAND
 		Support for an OMAP3-specific set of functions to return the
 		ID and MFR of the first attached NAND chip, if present.
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 		CONFIG_SPL_PAD_TO
 		Image offset to which the SPL should be padded before appending
 		the SPL payload. By default, this is defined as
 		CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
 		CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
 		payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
 		CONFIG_SPL_TARGET
 		Final target image containing SPL and payload.  Some SPLs
 		use an arch-specific makefile fragment instead, for
 		example if more than one image needs to be produced.
 		CONFIG_FIT_SPL_PRINT
 		Printing information about a FIT image adds quite a bit of
 		code to SPL. So this is normally disabled in SPL. Use this
 		option to re-enable it. This will affect the output of the
 		bootm command when booting a FIT image.
 - TPL framework
 		CONFIG_TPL
 		Enable building of TPL globally.
 		CONFIG_TPL_PAD_TO
 		Image offset to which the TPL should be padded before appending
 		the TPL payload. By default, this is defined as
 		CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
 		CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
 		payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
 - Interrupt support (PPC):
 		There are common interrupt_init() and timer_interrupt()
 		for all PPC archs. interrupt_init() calls interrupt_init_cpu()
 		for CPU specific initialization. interrupt_init_cpu()
 		should set decrementer_count to appropriate value. If
 		CPU resets decrementer automatically after interrupt
 		(ppc4xx) it should set decrementer_count to zero.
 		timer_interrupt() calls timer_interrupt_cpu() for CPU
 		specific handling. If board has watchdog / status_led
 		/ other_activity_monitor it works automatically from
 		general timer_interrupt().
 Board initialization settings:
 ------------------------------
 During Initialization u-boot calls a number of board specific functions
 to allow the preparation of board specific prerequisites, e.g. pin setup
 before drivers are initialized. To enable these callbacks the
 following configuration macros have to be defined. Currently this is
 architecture specific, so please check arch/your_architecture/lib/board.c
 typically in board_init_f() and board_init_r().
 - CONFIG_BOARD_EARLY_INIT_F: Call board_early_init_f()
 - CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r()
 - CONFIG_BOARD_LATE_INIT: Call board_late_init()
 - CONFIG_BOARD_POSTCLK_INIT: Call board_postclk_init()
 Configuration Settings:
 -----------------------
 - CONFIG_SYS_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit.
 		Optionally it can be defined to support 64-bit memory commands.
 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
 		undefine this when you're short of memory.
 - CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
 		width of the commands listed in the 'help' command output.
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
 		prompt for user input.
 - CONFIG_SYS_CBSIZE:	Buffer size for input from the Console
 - CONFIG_SYS_PBSIZE:	Buffer size for Console output
 - CONFIG_SYS_MAXARGS:	max. Number of arguments accepted for monitor commands
 - CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
 		the application (usually a Linux kernel) when it is
 		booted
 - CONFIG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 - CONFIG_SYS_CONSOLE_INFO_QUIET
 		Suppress display of console information at boot.
 - CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 		Enable the call to overwrite_console().
 - CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 		Enable overwrite of previous console environment settings.
 - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
 		Begin and End addresses of the area used by the
 		simple memory test.
 - CONFIG_SYS_ALT_MEMTEST:
 		Enable an alternate, more extensive memory test.
 - CONFIG_SYS_MEMTEST_SCRATCH:
 		Scratch address used by the alternate memory test
 		You only need to set this if address zero isn't writeable
 - CONFIG_SYS_MEM_RESERVE_SECURE
 		Only implemented for ARMv8 for now.
 		If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
 		is substracted from total RAM and won't be reported to OS.
 		This memory can be used as secure memory. A variable
 		gd->arch.secure_ram is used to track the location. In systems
 		the RAM base is not zero, or RAM is divided into banks,
 		this variable needs to be recalcuated to get the address.
 - CONFIG_SYS_MEM_TOP_HIDE:
 		If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
 		this specified memory area will get subtracted from the top
 		(end) of RAM and won't get "touched" at all by U-Boot. By
 		fixing up gd->ram_size the Linux kernel should gets passed
 		the now "corrected" memory size and won't touch it either.
 		This should work for arch/ppc and arch/powerpc. Only Linux
 		board ports in arch/powerpc with bootwrapper support that
 		recalculate the memory size from the SDRAM controller setup
 		will have to get fixed in Linux additionally.
 		This option can be used as a workaround for the 440EPx/GRx
 		CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
 		be touched.
 		WARNING: Please make sure that this value is a multiple of
 		the Linux page size (normally 4k). If this is not the case,
 		then the end address of the Linux memory will be located at a
 		non page size aligned address and this could cause major
 		problems.
 - CONFIG_SYS_LOADS_BAUD_CHANGE:
 		Enable temporary baudrate change while serial download
 - CONFIG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 - CONFIG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 - CONFIG_SYS_MONITOR_BASE:
 		Physical start address of boot monitor code (set by
 		make config files to be same as the text base address
 		(CONFIG_SYS_TEXT_BASE) used when linking) - same as
 		CONFIG_SYS_FLASH_BASE when booting from flash.
 - CONFIG_SYS_MONITOR_LEN:
 		Size of memory reserved for monitor code, used to
 		determine _at_compile_time_ (!) if the environment is
 		embedded within the U-Boot image, or in a separate
 		flash sector.
 - CONFIG_SYS_MALLOC_LEN:
 		Size of DRAM reserved for malloc() use.
 - CONFIG_SYS_MALLOC_F_LEN
 		Size of the malloc() pool for use before relocation. If
 		this is defined, then a very simple malloc() implementation
 		will become available before relocation. The address is just
 		below the global data, and the stack is moved down to make
 		space.
 		This feature allocates regions with increasing addresses
 		within the region. calloc() is supported, but realloc()
 		is not available. free() is supported but does nothing.
 		The memory will be freed (or in fact just forgotten) when
 		U-Boot relocates itself.
 - CONFIG_SYS_MALLOC_SIMPLE
 		Provides a simple and small malloc() and calloc() for those
 		boards which do not use the full malloc in SPL (which is
 		enabled with CONFIG_SYS_SPL_MALLOC_START).
 - CONFIG_SYS_NONCACHED_MEMORY:
 		Size of non-cached memory area. This area of memory will be
 		typically located right below the malloc() area and mapped
 		uncached in the MMU. This is useful for drivers that would
 		otherwise require a lot of explicit cache maintenance. For
 		some drivers it's also impossible to properly maintain the
 		cache. For example if the regions that need to be flushed
 		are not a multiple of the cache-line size, *and* padding
 		cannot be allocated between the regions to align them (i.e.
 		if the HW requires a contiguous array of regions, and the
 		size of each region is not cache-aligned), then a flush of
 		one region may result in overwriting data that hardware has
 		written to another region in the same cache-line. This can
 		happen for example in network drivers where descriptors for
 		buffers are typically smaller than the CPU cache-line (e.g.
 		16 bytes vs. 32 or 64 bytes).
 		Non-cached memory is only supported on 32-bit ARM at present.
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,
 		you can define CONFIG_SYS_BOOTM_LEN in your board config file
 		to adjust this setting to your needs.
 - CONFIG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
 		the Linux kernel (bd_info, boot arguments, FDT blob if
 		used) must be put below this limit, unless "bootm_low"
 		environment variable is defined and non-zero. In such case
 		all data for the Linux kernel must be between "bootm_low"
 		and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.	 The environment
 		variable "bootm_mapsize" will override the value of
 		CONFIG_SYS_BOOTMAPSZ.  If CONFIG_SYS_BOOTMAPSZ is undefined,
 		then the value in "bootm_size" will be used instead.
 - CONFIG_SYS_BOOT_RAMDISK_HIGH:
 		Enable initrd_high functionality.  If defined then the
 		initrd_high feature is enabled and the bootm ramdisk subcommand
 		is enabled.
 - CONFIG_SYS_BOOT_GET_CMDLINE:
 		Enables allocating and saving kernel cmdline in space between
 		"bootm_low" and "bootm_low" + BOOTMAPSZ.
 - CONFIG_SYS_BOOT_GET_KBD:
 		Enables allocating and saving a kernel copy of the bd_info in
 		space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
 - CONFIG_SYS_MAX_FLASH_BANKS:
 		Max number of Flash memory banks
 - CONFIG_SYS_MAX_FLASH_SECT:
 		Max number of sectors on a Flash chip
 - CONFIG_SYS_FLASH_ERASE_TOUT:
 		Timeout for Flash erase operations (in ms)
 - CONFIG_SYS_FLASH_WRITE_TOUT:
 		Timeout for Flash write operations (in ms)
 - CONFIG_SYS_FLASH_LOCK_TOUT
 		Timeout for Flash set sector lock bit operation (in ms)
 - CONFIG_SYS_FLASH_UNLOCK_TOUT
 		Timeout for Flash clear lock bits operation (in ms)
 - CONFIG_SYS_FLASH_PROTECTION
 		If defined, hardware flash sectors protection is used
 		instead of U-Boot software protection.
 - CONFIG_SYS_DIRECT_FLASH_TFTP:
 		Enable TFTP transfers directly to flash memory;
 		without this option such a download has to be
 		performed in two steps: (1) download to RAM, and (2)
 		copy from RAM to flash.
 		The two-step approach is usually more reliable, since
 		you can check if the download worked before you erase
 		the flash, but in some situations (when system RAM is
 		too limited to allow for a temporary copy of the
 		downloaded image) this option may be very useful.
 - CONFIG_SYS_FLASH_CFI:
 		Define if the flash driver uses extra elements in the
 		common flash structure for storing flash geometry.
 - CONFIG_FLASH_CFI_DRIVER
 		This option also enables the building of the cfi_flash driver
 		in the drivers directory
 - CONFIG_FLASH_CFI_MTD
 		This option enables the building of the cfi_mtd driver
 		in the drivers directory. The driver exports CFI flash
 		to the MTD layer.
 - CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 		Use buffered writes to flash.
 - CONFIG_FLASH_SPANSION_S29WS_N
 		s29ws-n MirrorBit flash has non-standard addresses for buffered
 		write commands.
 - CONFIG_SYS_FLASH_QUIET_TEST
 		If this option is defined, the common CFI flash doesn't
 		print it's warning upon not recognized FLASH banks. This
 		is useful, if some of the configured banks are only
 		optionally available.
 - CONFIG_FLASH_SHOW_PROGRESS
 		If defined (must be an integer), print out countdown
 		digits and dots.  Recommended value: 45 (9..1) for 80
 		column displays, 15 (3..1) for 40 column displays.
 - CONFIG_FLASH_VERIFY
 		If defined, the content of the flash (destination) is compared
 		against the source after the write operation. An error message
 		will be printed when the contents are not identical.
 		Please note that this option is useless in nearly all cases,
 		since such flash programming errors usually are detected earlier
 		while unprotecting/erasing/programming. Please only enable
 		this option if you really know what you are doing.
 - CONFIG_SYS_RX_ETH_BUFFER:
 		Defines the number of Ethernet receive buffers. On some
 		Ethernet controllers it is recommended to set this value
 		to 8 or even higher (EEPRO100 or 405 EMAC), since all
 		buffers can be full shortly after enabling the interface
 		on high Ethernet traffic.
 		Defaults to 4 if not defined.
 - CONFIG_ENV_MAX_ENTRIES
 	Maximum number of entries in the hash table that is used
 	internally to store the environment settings. The default
 	setting is supposed to be generous and should work in most
 	cases. This setting can be used to tune behaviour; see
 	lib/hashtable.c for details.
 - CONFIG_ENV_FLAGS_LIST_DEFAULT
 - CONFIG_ENV_FLAGS_LIST_STATIC
 	Enable validation of the values given to environment variables when
 	calling env set.  Variables can be restricted to only decimal,
 	hexadecimal, or boolean.  If CONFIG_CMD_NET is also defined,
 	the variables can also be restricted to IP address or MAC address.
 	The format of the list is:
 		type_attribute = [s|d|x|b|i|m]
 		access_attribute = [a|r|o|c]
 		attributes = type_attribute[access_attribute]
 		entry = variable_name[:attributes]
 		list = entry[,list]
 	The type attributes are:
 		s - String (default)
 		d - Decimal
 		x - Hexadecimal
 		b - Boolean ([1yYtT|0nNfF])
 		i - IP address
 		m - MAC address
 	The access attributes are:
 		a - Any (default)
 		r - Read-only
 		o - Write-once
 		c - Change-default
 	- CONFIG_ENV_FLAGS_LIST_DEFAULT
 		Define this to a list (string) to define the ".flags"
 		environment variable in the default or embedded environment.
 	- CONFIG_ENV_FLAGS_LIST_STATIC
 		Define this to a list (string) to define validation that
 		should be done if an entry is not found in the ".flags"
 		environment variable.  To override a setting in the static
 		list, simply add an entry for the same variable name to the
 		".flags" variable.
 	If CONFIG_REGEX is defined, the variable_name above is evaluated as a
 	regular expression. This allows multiple variables to define the same
 	flags without explicitly listing them for each variable.
 - CONFIG_ENV_ACCESS_IGNORE_FORCE
 	If defined, don't allow the -f switch to env set override variable
 	access flags.
 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
 	This is set by OMAP boards for the max time that reset should
 	be asserted. See doc/README.omap-reset-time for details on how
 	the value can be calculated on a given board.
 - CONFIG_USE_STDINT
 	If stdint.h is available with your toolchain you can define this
 	option to enable it. You can provide option 'USE_STDINT=1' when
 	building U-Boot to enable this.
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
 - CONFIG_BUILD_ENVCRC:
 	Builds up envcrc with the target environment so that external utils
 	may easily extract it and embed it in final U-Boot images.
 - CONFIG_ENV_IS_IN_FLASH:
 	Define this if the environment is in flash memory.
 	a) The environment occupies one whole flash sector, which is
 	   "embedded" in the text segment with the U-Boot code. This
 	   happens usually with "bottom boot sector" or "top boot
 	   sector" type flash chips, which have several smaller
 	   sectors at the start or the end. For instance, such a
 	   layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
 	   such a case you would place the environment in one of the
 	   4 kB sectors - with U-Boot code before and after it. With
 	   "top boot sector" type flash chips, you would put the
 	   environment in one of the last sectors, leaving a gap
 	   between U-Boot and the environment.
 	- CONFIG_ENV_OFFSET:
 	   Offset of environment data (variable area) to the
 	   beginning of flash memory; for instance, with bottom boot
 	   type flash chips the second sector can be used: the offset
 	   for this sector is given here.
 	   CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
 	- CONFIG_ENV_ADDR:
 	   This is just another way to specify the start address of
 	   the flash sector containing the environment (instead of
 	   CONFIG_ENV_OFFSET).
 	- CONFIG_ENV_SECT_SIZE:
 	   Size of the sector containing the environment.
 	b) Sometimes flash chips have few, equal sized, BIG sectors.
 	   In such a case you don't want to spend a whole sector for
 	   the environment.
 	- CONFIG_ENV_SIZE:
 	   If you use this in combination with CONFIG_ENV_IS_IN_FLASH
 	   and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
 	   of this flash sector for the environment. This saves
 	   memory for the RAM copy of the environment.
 	   It may also save flash memory if you decide to use this
 	   when your environment is "embedded" within U-Boot code,
 	   since then the remainder of the flash sector could be used
 	   for U-Boot code. It should be pointed out that this is
 	   STRONGLY DISCOURAGED from a robustness point of view:
 	   updating the environment in flash makes it always
 	   necessary to erase the WHOLE sector. If something goes
 	   wrong before the contents has been restored from a copy in
 	   RAM, your target system will be dead.
 	- CONFIG_ENV_ADDR_REDUND
 	  CONFIG_ENV_SIZE_REDUND
 	   These settings describe a second storage area used to hold
 	   a redundant copy of the environment data, so that there is
 	   a valid backup copy in case there is a power failure during
 	   a "saveenv" operation.
 BE CAREFUL! Any changes to the flash layout, and some changes to the
 source code will make it necessary to adapt <board>/u-boot.lds*
 accordingly!
 - CONFIG_ENV_IS_IN_NVRAM:
 	Define this if you have some non-volatile memory device
 	(NVRAM, battery buffered SRAM) which you want to use for the
 	environment.
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These two #defines are used to determine the memory area you
 	  want to use for environment. It is assumed that this memory
 	  can just be read and written to, without any special
 	  provision.
 BE CAREFUL! The first access to the environment happens quite early
 in U-Boot initialization (when we try to get the setting of for the
 console baudrate). You *MUST* have mapped your NVRAM area then, or
 U-Boot will hang.
 Please note that even with NVRAM we still use a copy of the
 environment in RAM: we could work on NVRAM directly, but we want to
 keep settings there always unmodified except somebody uses "saveenv"
 to save the current settings.
 - CONFIG_ENV_IS_IN_EEPROM:
 	Use this if you have an EEPROM or similar serial access
 	device and a driver for it.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the
 	  environment area within the total memory of your EEPROM.
 	- CONFIG_SYS_I2C_EEPROM_ADDR:
 	  If defined, specified the chip address of the EEPROM device.
 	  The default address is zero.
 	- CONFIG_SYS_I2C_EEPROM_BUS:
 	  If defined, specified the i2c bus of the EEPROM device.
 	- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
 	  If defined, the number of bits used to address bytes in a
 	  single page in the EEPROM device.  A 64 byte page, for example
 	  would require six bits.
 	- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
 	  If defined, the number of milliseconds to delay between
 	  page writes.	The default is zero milliseconds.
 	- CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
 	  The length in bytes of the EEPROM memory array address.  Note
 	  that this is NOT the chip address length!
 	- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
 	  EEPROM chips that implement "address overflow" are ones
 	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 	  address and the extra bits end up in the "chip address" bit
 	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
 	  byte chips.
 	  Note that we consider the length of the address field to
 	  still be one byte because the extra address bits are hidden
 	  in the chip address.
 	- CONFIG_SYS_EEPROM_SIZE:
 	  The size in bytes of the EEPROM device.
 	- CONFIG_ENV_EEPROM_IS_ON_I2C
 	  define this, if you have I2C and SPI activated, and your
 	  EEPROM, which holds the environment, is on the I2C bus.
 	- CONFIG_I2C_ENV_EEPROM_BUS
 	  if you have an Environment on an EEPROM reached over
 	  I2C muxes, you can define here, how to reach this
 	  EEPROM. For example:
 	  #define CONFIG_I2C_ENV_EEPROM_BUS	  1
 	  EEPROM which holds the environment, is reached over
 	  a pca9547 i2c mux with address 0x70, channel 3.
 - CONFIG_ENV_IS_IN_DATAFLASH:
 	Define this if you have a DataFlash memory device which you
 	want to use for the environment.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These three #defines specify the offset and size of the
 	  environment area within the total memory of your DataFlash placed
 	  at the specified address.
 - CONFIG_ENV_IS_IN_SPI_FLASH:
 	Define this if you have a SPI Flash memory device which you
 	want to use for the environment.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the
 	  environment area within the SPI Flash. CONFIG_ENV_OFFSET must be
 	  aligned to an erase sector boundary.
 	- CONFIG_ENV_SECT_SIZE:
 	  Define the SPI flash's sector size.
 	- CONFIG_ENV_OFFSET_REDUND (optional):
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
 	  during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
 	  aligned to an erase sector boundary.
 	- CONFIG_ENV_SPI_BUS (optional):
 	- CONFIG_ENV_SPI_CS (optional):
 	  Define the SPI bus and chip select. If not defined they will be 0.
 	- CONFIG_ENV_SPI_MAX_HZ (optional):
 	  Define the SPI max work clock. If not defined then use 1MHz.
 	- CONFIG_ENV_SPI_MODE (optional):
 	  Define the SPI work mode. If not defined then use SPI_MODE_3.
 - CONFIG_ENV_IS_IN_REMOTE:
 	Define this if you have a remote memory space which you
 	want to use for the local device's environment.
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the address and size of the
 	  environment area within the remote memory space. The
 	  local device can get the environment from remote memory
 	  space by SRIO or PCIE links.
 BE CAREFUL! For some special cases, the local device can not use
 "saveenv" command. For example, the local device will get the
 environment stored in a remote NOR flash by SRIO or PCIE link,
 but it can not erase, write this NOR flash by SRIO or PCIE interface.
 - CONFIG_ENV_IS_IN_NAND:
 	Define this if you have a NAND device which you want to use
 	for the environment.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the environment
 	  area within the first NAND device.  CONFIG_ENV_OFFSET must be
 	  aligned to an erase block boundary.
 	- CONFIG_ENV_OFFSET_REDUND (optional):
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
 	  during a "saveenv" operation.	 CONFIG_ENV_OFFSET_REDUND must be
 	  aligned to an erase block boundary.
 	- CONFIG_ENV_RANGE (optional):
 	  Specifies the length of the region in which the environment
 	  can be written.  This should be a multiple of the NAND device's
 	  block size.  Specifying a range with more erase blocks than
 	  are needed to hold CONFIG_ENV_SIZE allows bad blocks within
 	  the range to be avoided.
 	- CONFIG_ENV_OFFSET_OOB (optional):
 	  Enables support for dynamically retrieving the offset of the
 	  environment from block zero's out-of-band data.  The
 	  "nand env.oob" command can be used to record this offset.
 	  Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
 	  using CONFIG_ENV_OFFSET_OOB.
 - CONFIG_NAND_ENV_DST
 	Defines address in RAM to which the nand_spl code should copy the
 	environment. If redundant environment is used, it will be copied to
 	CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
 - CONFIG_ENV_IS_IN_UBI:
 	Define this if you have an UBI volume that you want to use for the
 	environment.  This has the benefit of wear-leveling the environment
 	accesses, which is important on NAND.
 	- CONFIG_ENV_UBI_PART:
 	  Define this to a string that is the mtd partition containing the UBI.
 	- CONFIG_ENV_UBI_VOLUME:
 	  Define this to the name of the volume that you want to store the
 	  environment in.
 	- CONFIG_ENV_UBI_VOLUME_REDUND:
 	  Define this to the name of another volume to store a second copy of
 	  the environment in.  This will enable redundant environments in UBI.
 	  It is assumed that both volumes are in the same MTD partition.
 	- CONFIG_UBI_SILENCE_MSG
 	- CONFIG_UBIFS_SILENCE_MSG
 	  You will probably want to define these to avoid a really noisy system
 	  when storing the env in UBI.
 - CONFIG_ENV_IS_IN_FAT:
        Define this if you want to use the FAT file system for the environment.
        - FAT_ENV_INTERFACE:
          Define this to a string that is the name of the block device.
        - FAT_ENV_DEV_AND_PART:
          Define this to a string to specify the partition of the device. It can
          be as following:
            "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
                - "D:P": device D partition P. Error occurs if device D has no
                         partition table.
                - "D:0": device D.
                - "D" or "D:": device D partition 1 if device D has partition
                               table, or the whole device D if has no partition
                               table.
                - "D:auto": first partition in device D with bootable flag set.
                            If none, first valid partition in device D. If no
                            partition table then means device D.
        - FAT_ENV_FILE:
          It's a string of the FAT file name. This file use to store the
          environment.
        - CONFIG_FAT_WRITE:
          This should be defined. Otherwise it cannot save the environment file.
 - CONFIG_ENV_IS_IN_MMC:
 	Define this if you have an MMC device which you want to use for the
 	environment.
 	- CONFIG_SYS_MMC_ENV_DEV:
 	  Specifies which MMC device the environment is stored in.
 	- CONFIG_SYS_MMC_ENV_PART (optional):
 	  Specifies which MMC partition the environment is stored in. If not
 	  set, defaults to partition 0, the user area. Common values might be
 	  1 (first MMC boot partition), 2 (second MMC boot partition).
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the environment
 	  area within the specified MMC device.
 	  If offset is positive (the usual case), it is treated as relative to
 	  the start of the MMC partition. If offset is negative, it is treated
 	  as relative to the end of the MMC partition. This can be useful if
 	  your board may be fitted with different MMC devices, which have
 	  different sizes for the MMC partitions, and you always want the
 	  environment placed at the very end of the partition, to leave the
 	  maximum possible space before it, to store other data.
 	  These two values are in units of bytes, but must be aligned to an
 	  MMC sector boundary.
 	- CONFIG_ENV_OFFSET_REDUND (optional):
 	  Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
 	  hold a redundant copy of the environment data. This provides a
 	  valid backup copy in case the other copy is corrupted, e.g. due
 	  to a power failure during a "saveenv" operation.
 	  This value may also be positive or negative; this is handled in the
 	  same way as CONFIG_ENV_OFFSET.
 	  This value is also in units of bytes, but must also be aligned to
 	  an MMC sector boundary.
 	- CONFIG_ENV_SIZE_REDUND (optional):
 	  This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
 	  set. If this value is set, it must be set to the same value as
 	  CONFIG_ENV_SIZE.
 - CONFIG_SYS_SPI_INIT_OFFSET
 	Defines offset to the initial SPI buffer area in DPRAM. The
 	area is used at an early stage (ROM part) if the environment
 	is configured to reside in the SPI EEPROM: We need a 520 byte
 	scratch DPRAM area. It is used between the two initialization
 	calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
 	to be a good choice since it makes it far enough from the
 	start of the data area as well as from the stack pointer.
 Please note that the environment is read-only until the monitor
 has been relocated to RAM and a RAM copy of the environment has been
 created; also, when using EEPROM you will have to use getenv_f()
 until then to read environment variables.
 The environment is protected by a CRC32 checksum. Before the monitor
 is relocated into RAM, as a result of a bad CRC you will be working
 with the compiled-in default environment - *silently*!!! [This is
 necessary, because the first environment variable we need is the
 "baudrate" setting for the console - if we have a bad CRC, we don't
 have any device yet where we could complain.]
 Note: once the monitor has been relocated, then it will complain if
 the default environment is used; a new CRC is computed as soon as you
 use the "saveenv" command to store a valid environment.
 - CONFIG_SYS_FAULT_ECHO_LINK_DOWN:
 		Echo the inverted Ethernet link state to the fault LED.
 		Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR
 		      also needs to be defined.
 - CONFIG_SYS_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.
 - CONFIG_NS16550_MIN_FUNCTIONS:
 		Define this if you desire to only have use of the NS16550_init
 		and NS16550_putc functions for the serial driver located at
 		drivers/serial/ns16550.c.  This option is useful for saving
 		space for already greatly restricted images, including but not
 		limited to NAND_SPL configurations.
 - CONFIG_DISPLAY_BOARDINFO
 		Display information about the board that U-Boot is running on
 		when U-Boot starts up. The board function checkboard() is called
 		to do this.
 - CONFIG_DISPLAY_BOARDINFO_LATE
 		Similar to the previous option, but display this information
 		later, once stdio is running and output goes to the LCD, if
 		present.
 - CONFIG_BOARD_SIZE_LIMIT:
 		Maximum size of the U-Boot image. When defined, the
 		build system checks that the actual size does not
 		exceed it.
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 - CONFIG_SYS_CACHELINE_SIZE:
 		Cache Line Size of the CPU.
 - CONFIG_SYS_DEFAULT_IMMR:
 		Default address of the IMMR after system reset.
 		Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
 		and RPXsuper) to be able to adjust the position of
 		the IMMR register after a reset.
 - CONFIG_SYS_CCSRBAR_DEFAULT:
 		Default (power-on reset) physical address of CCSR on Freescale
 		PowerPC SOCs.
 - CONFIG_SYS_CCSRBAR:
 		Virtual address of CCSR.  On a 32-bit build, this is typically
 		the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
 		CONFIG_SYS_DEFAULT_IMMR must also be set to this value,
 		for cross-platform code that uses that macro instead.
 - CONFIG_SYS_CCSRBAR_PHYS:
 		Physical address of CCSR.  CCSR can be relocated to a new
 		physical address, if desired.  In this case, this macro should
 		be set to that address.	 Otherwise, it should be set to the
 		same value as CONFIG_SYS_CCSRBAR_DEFAULT.  For example, CCSR
 		is typically relocated on 36-bit builds.  It is recommended
 		that this macro be defined via the _HIGH and _LOW macros:
 		#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
 			* 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
 - CONFIG_SYS_CCSRBAR_PHYS_HIGH:
 		Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS.	This value is typically
 		either 0 (32-bit build) or 0xF (36-bit build).	This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 - CONFIG_SYS_CCSRBAR_PHYS_LOW:
 		Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS.  This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 - CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
 		If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
 		forced to a value that ensures that CCSR is not relocated.
 - Floppy Disk Support:
 		CONFIG_SYS_FDC_DRIVE_NUMBER
 		the default drive number (default value 0)
 		CONFIG_SYS_ISA_IO_STRIDE
 		defines the spacing between FDC chipset registers
 		(default value 1)
 		CONFIG_SYS_ISA_IO_OFFSET
 		defines the offset of register from address. It
 		depends on which part of the data bus is connected to
 		the FDC chipset. (default value 0)
 		If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and
 		CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their
 		default value.
 		if CONFIG_SYS_FDC_HW_INIT is defined, then the function
 		fdc_hw_init() is called at the beginning of the FDC
 		setup. fdc_hw_init() must be provided by the board
 		source code. It is used to make hardware-dependent
 		initializations.
 - CONFIG_IDE_AHB:
 		Most IDE controllers were designed to be connected with PCI
 		interface. Only few of them were designed for AHB interface.
 		When software is doing ATA command and data transfer to
 		IDE devices through IDE-AHB controller, some additional
 		registers accessing to these kind of IDE-AHB controller
 		is required.
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx/82xx systems only]
 - CONFIG_SYS_INIT_RAM_ADDR:
 		Start address of memory area that can be used for
 		initial data and stack; please note that this must be
 		writable memory that is working WITHOUT special
 		initialization, i. e. you CANNOT use normal RAM which
 		will become available only after programming the
 		memory controller and running certain initialization
 		sequences.
 		U-Boot uses the following memory types:
 		- MPC8xx and MPC8260: IMMR (internal memory of the CPU)
 		- MPC824X: data cache
 		- PPC4xx:  data cache
 - CONFIG_SYS_GBL_DATA_OFFSET:
 		Offset of the initial data structure in the memory
 		area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
 		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
 		data is located at the end of the available space
 		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
 		GENERATED_GBL_DATA_SIZE), and the initial stack is just
 		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
 		CONFIG_SYS_GBL_DATA_OFFSET) downward.
 	Note:
 		On the MPC824X (or other systems that use the data
 		cache for initial memory) the address chosen for
 		CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
 		point to an otherwise UNUSED address space between
 		the top of RAM and the start of the PCI space.
 - CONFIG_SYS_SIUMCR:	SIU Module Configuration (11-6)
 - CONFIG_SYS_SYPCR:	System Protection Control (11-9)
 - CONFIG_SYS_TBSCR:	Time Base Status and Control (11-26)
 - CONFIG_SYS_PISCR:	Periodic Interrupt Status and Control (11-31)
 - CONFIG_SYS_PLPRCR:	PLL, Low-Power, and Reset Control Register (15-30)
 - CONFIG_SYS_SCCR:	System Clock and reset Control Register (15-27)
 - CONFIG_SYS_OR_TIMING_SDRAM:
 		SDRAM timing
 - CONFIG_SYS_MAMR_PTA:
 		periodic timer for refresh
 - CONFIG_SYS_DER:	Debug Event Register (37-47)
 - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
   CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
   CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
   CONFIG_SYS_BR1_PRELIM:
 		Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
 - SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
   CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
   CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
 		Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
 - CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
   CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
 		Machine Mode Register and Memory Periodic Timer
 		Prescaler definitions (SDRAM timing)
 - CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]:
 		enable I2C microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [DSP2]
 - CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]:
 		enable SMC microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SMC1]
 - CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]:
 		enable SPI microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SCC4]
 - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
 		Offset of the bootmode word in DPRAM used by post
 		(Power On Self Tests). This definition overrides
 		#define'd default value in commproc.h resp.
 		cpm_8260.h.
 - CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
   CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
   CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
   CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
   CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
   CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
   CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
   CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
 		Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
 - CONFIG_PCI_DISABLE_PCIE:
 		Disable PCI-Express on systems where it is supported but not
 		required.
 - CONFIG_PCI_ENUM_ONLY
 		Only scan through and get the devices on the buses.
 		Don't do any setup work, presumably because someone or
 		something has already done it, and we don't need to do it
 		a second time.	Useful for platforms that are pre-booted
 		by coreboot or similar.
 - CONFIG_PCI_INDIRECT_BRIDGE:
 		Enable support for indirect PCI bridges.
 - CONFIG_SYS_SRIO:
 		Chip has SRIO or not
 - CONFIG_SRIO1:
 		Board has SRIO 1 port available
 - CONFIG_SRIO2:
 		Board has SRIO 2 port available
 - CONFIG_SRIO_PCIE_BOOT_MASTER
 		Board can support master function for Boot from SRIO and PCIE
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region
 - CONFIG_SYS_SRIOn_MEM_PHYS:
 		Physical Address of SRIO port 'n' memory region
 - CONFIG_SYS_SRIOn_MEM_SIZE:
 		Size of SRIO port 'n' memory region
 - CONFIG_SYS_NAND_BUSWIDTH_16BIT
 		Defined to tell the NAND controller that the NAND chip is using
 		a 16 bit bus.
 		Not all NAND drivers use this symbol.
 		Example of drivers that use it:
 		- drivers/mtd/nand/ndfc.c
 		- drivers/mtd/nand/mxc_nand.c
 - CONFIG_SYS_NDFC_EBC0_CFG
 		Sets the EBC0_CFG register for the NDFC. If not defined
 		a default value will be used.
 - CONFIG_SPD_EEPROM
 		Get DDR timing information from an I2C EEPROM. Common
 		with pluggable memory modules such as SODIMMs
   SPD_EEPROM_ADDRESS
 		I2C address of the SPD EEPROM
 - CONFIG_SYS_SPD_BUS_NUM
 		If SPD EEPROM is on an I2C bus other than the first
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 - CONFIG_SYS_DDR_RAW_TIMING
 		Get DDR timing information from other than SPD. Common with
 		soldered DDR chips onboard without SPD. DDR raw timing
 		parameters are extracted from datasheet and hard-coded into
 		header files or board specific files.
 - CONFIG_FSL_DDR_INTERACTIVE
 		Enable interactive DDR debugging. See doc/README.fsl-ddr.
 - CONFIG_FSL_DDR_SYNC_REFRESH
 		Enable sync of refresh for multiple controllers.
 - CONFIG_FSL_DDR_BIST
 		Enable built-in memory test for Freescale DDR controllers.
 - CONFIG_SYS_83XX_DDR_USES_CS0
 		Only for 83xx systems. If specified, then DDR should
 		be configured using CS0 and CS1 instead of CS2 and CS3.
 - CONFIG_ETHER_ON_FEC[12]
 		Define to enable FEC[12] on a 8xx series processor.
 - CONFIG_FEC[12]_PHY
 		Define to the hardcoded PHY address which corresponds
 		to the given FEC; i. e.
 			#define CONFIG_FEC1_PHY 4
 		means that the PHY with address 4 is connected to FEC1
 		When set to -1, means to probe for first available.
 - CONFIG_FEC[12]_PHY_NORXERR
 		The PHY does not have a RXERR line (RMII only).
 		(so program the FEC to ignore it).
 - CONFIG_RMII
 		Enable RMII mode for all FECs.
 		Note that this is a global option, we can't
 		have one FEC in standard MII mode and another in RMII mode.
 - CONFIG_CRC32_VERIFY
 		Add a verify option to the crc32 command.
 		The syntax is:
 		=> crc32 -v <address> <count> <crc32>
 		Where address/count indicate a memory area
 		and crc32 is the correct crc32 which the
 		area should have.
 - CONFIG_LOOPW
 		Add the "loopw" memory command. This only takes effect if
 		the memory commands are activated globally (CONFIG_CMD_MEM).
 - CONFIG_MX_CYCLIC
 		Add the "mdc" and "mwc" memory commands. These are cyclic
 		"md/mw" commands.
 		Examples:
 		=> mdc.b 10 4 500
 		This command will print 4 bytes (10,11,12,13) each 500 ms.
 		=> mwc.l 100 12345678 10
 		This command will write 12345678 to address 100 all 10 ms.
 		This only takes effect if the memory commands are activated
 		globally (CONFIG_CMD_MEM).
 - CONFIG_SKIP_LOWLEVEL_INIT
 		[ARM, NDS32, MIPS only] If this variable is defined, then certain
 		low level initializations (like setting up the memory
 		controller) are omitted and/or U-Boot does not
 		relocate itself into RAM.
 		Normally this variable MUST NOT be defined. The only
 		exception is when U-Boot is loaded (to RAM) by some
 		other boot loader or by a debugger which performs
 		these initializations itself.
 - CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 		[ARM926EJ-S only] This allows just the call to lowlevel_init()
 		to be skipped. The normal CP15 init (such as enabling the
 		instruction cache) is still performed.
 - CONFIG_SPL_BUILD
 		Modifies the behaviour of start.S when compiling a loader
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
 - CONFIG_TPL_BUILD
 		Modifies the behaviour of start.S  when compiling a loader
 		that is executed after the SPL and before the actual U-Boot.
 		It is loaded by the SPL.
 - CONFIG_SYS_MPC85XX_NO_RESETVEC
 		Only for 85xx systems. If this variable is specified, the section
 		.resetvec is not kept and the section .bootpg is placed in the
 		previous 4k of the .text section.
 - CONFIG_ARCH_MAP_SYSMEM
 		Generally U-Boot (and in particular the md command) uses
 		effective address. It is therefore not necessary to regard
 		U-Boot address as virtual addresses that need to be translated
 		to physical addresses. However, sandbox requires this, since
 		it maintains its own little RAM buffer which contains all
 		addressable memory. This option causes some memory accesses
 		to be mapped through map_sysmem() / unmap_sysmem().
 - CONFIG_USE_ARCH_MEMCPY
   CONFIG_USE_ARCH_MEMSET
 		If these options are used a optimized version of memcpy/memset will
 		be used if available. These functions may be faster under some
 		conditions but may increase the binary size.
 - CONFIG_X86_RESET_VECTOR
 		If defined, the x86 reset vector code is included. This is not
 		needed when U-Boot is running from Coreboot.
 - CONFIG_SYS_MPUCLK
 		Defines the MPU clock speed (in MHz).
 		NOTE : currently only supported on AM335x platforms.
 - CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
 		Enables the RTC32K OSC on AM33xx based plattforms
 - CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
 		Option to disable subpage write in NAND driver
 		driver that uses this:
 		drivers/mtd/nand/davinci_nand.c
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
 loading of "firmware", which is encoded in the QE firmware binary format.
 This firmware often needs to be loaded during U-Boot booting, so macros
 are used to identify the storage device (NOR flash, SPI, etc) and the address
 within that device.
 - CONFIG_SYS_FMAN_FW_ADDR
 	The address in the storage device where the FMAN microcode is located.  The
 	meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
 	is also specified.
 - CONFIG_SYS_QE_FW_ADDR
 	The address in the storage device where the QE microcode is located.  The
 	meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
 	is also specified.
 - CONFIG_SYS_QE_FMAN_FW_LENGTH
 	The maximum possible size of the firmware.  The firmware binary format
 	has a field that specifies the actual size of the firmware, but it
 	might not be possible to read any part of the firmware unless some
 	local storage is allocated to hold the entire firmware first.
 - CONFIG_SYS_QE_FMAN_FW_IN_NOR
 	Specifies that QE/FMAN firmware is located in NOR flash, mapped as
 	normal addressable memory via the LBC.  CONFIG_SYS_FMAN_FW_ADDR is the
 	virtual address in NOR flash.
 - CONFIG_SYS_QE_FMAN_FW_IN_NAND
 	Specifies that QE/FMAN firmware is located in NAND flash.
 	CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
 - CONFIG_SYS_QE_FMAN_FW_IN_MMC
 	Specifies that QE/FMAN firmware is located on the primary SD/MMC
 	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 	Specifies that QE/FMAN firmware is located in the remote (master)
 	memory space.	CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
 	can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
 	window->master inbound window->master LAW->the ucode address in
 	master's memory space.
 Freescale Layerscape Management Complex Firmware Support:
 ---------------------------------------------------------
 The Freescale Layerscape Management Complex (MC) supports the loading of
 "firmware".
 This firmware often needs to be loaded during U-Boot booting, so macros
 are used to identify the storage device (NOR flash, SPI, etc) and the address
 within that device.
 - CONFIG_FSL_MC_ENET
 	Enable the MC driver for Layerscape SoCs.
 Freescale Layerscape Debug Server Support:
 -------------------------------------------
 The Freescale Layerscape Debug Server Support supports the loading of
 "Debug Server firmware" and triggering SP boot-rom.
 This firmware often needs to be loaded during U-Boot booting.
 - CONFIG_SYS_MC_RSV_MEM_ALIGN
 	Define alignment of reserved memory MC requires
 Reproducible builds
 -------------------
 In order to achieve reproducible builds, timestamps used in the U-Boot build
 process have to be set to a fixed value.
 This is done using the SOURCE_DATE_EPOCH environment variable.
 SOURCE_DATE_EPOCH is to be set on the build host's shell, not as a configuration
 option for U-Boot or an environment variable in U-Boot.
 SOURCE_DATE_EPOCH should be set to a number of seconds since the epoch, in UTC.
 Building the Software:
 ======================
 Building U-Boot has been tested in several native build environments
 and in many different cross environments. Of course we cannot support
 all possibly existing versions of cross development tools in all
 (potentially obsolete) versions. In case of tool chain problems we
 recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK)
 which is extensively used to build and test U-Boot.
 If you are not using a native environment, it is assumed that you
 have GNU cross compiling tools available in your path. In this case,
 you must set the environment variable CROSS_COMPILE in your shell.
 Note that no changes to the Makefile or any other source files are
 necessary. For example using the ELDK on a 4xx CPU, please enter:
 	$ CROSS_COMPILE=ppc_4xx-
 	$ export CROSS_COMPILE
 Note: If you wish to generate Windows versions of the utilities in
       the tools directory you can use the MinGW toolchain
       (http://www.mingw.org).  Set your HOST tools to the MinGW
       toolchain and execute 'make tools'.  For example:
        $ make HOSTCC=i586-mingw32msvc-gcc HOSTSTRIP=i586-mingw32msvc-strip tools
       Binaries such as tools/mkimage.exe will be created which can
       be executed on computers running Windows.
 U-Boot is intended to be simple to build. After installing the
 sources you must configure U-Boot for one specific board type. This
 is done by typing:
 	make NAME_defconfig
 where "NAME_defconfig" is the name of one of the existing configu-
 rations; see boards.cfg for supported names.
 Note: for some board special configuration names may exist; check if
       additional information is available from the board vendor; for
       instance, the TQM823L systems are available without (standard)
       or with LCD support. You can select such additional "features"
       when choosing the configuration, i. e.
       make TQM823L_defconfig
 	- will configure for a plain TQM823L, i. e. no LCD support
       make TQM823L_LCD_defconfig
 	- will configure for a TQM823L with U-Boot console on LCD
       etc.
 Finally, type "make all", and you should get some working U-Boot
 images ready for download to / installation on your system:
 - "u-boot.bin" is a raw binary image
 - "u-boot" is an image in ELF binary format
 - "u-boot.srec" is in Motorola S-Record format
 By default the build is performed locally and the objects are saved
 in the source directory. One of the two methods can be used to change
 this behavior and build U-Boot to some external directory:
 1. Add O= to the make command line invocations:
 	make O=/tmp/build distclean
 	make O=/tmp/build NAME_defconfig
 	make O=/tmp/build all
 2. Set environment variable KBUILD_OUTPUT to point to the desired location:
 	export KBUILD_OUTPUT=/tmp/build
 	make distclean
 	make NAME_defconfig
 	make all
 Note that the command line "O=" setting overrides the KBUILD_OUTPUT environment
 variable.
 Please be aware that the Makefiles assume you are using GNU make, so
 for instance on NetBSD you might need to use "gmake" instead of
 native "make".
 If the system board that you have is not listed, then you will need
 to port U-Boot to your hardware platform. To do this, follow these
 steps:
 1.  Create a new directory to hold your board specific code. Add any
     files you need. In your board directory, you will need at least
     the "Makefile" and a "<board>.c".
 2.  Create a new configuration file "include/configs/<board>.h" for
     your board.
 3.  If you're porting U-Boot to a new CPU, then also create a new
     directory to hold your CPU specific code. Add any files you need.
 4.  Run "make <board>_defconfig" with your new name.
 5.  Type "make", and you should get a working "u-boot.srec" file
     to be installed on your target system.
 6.  Debug and solve any problems that might arise.
     [Of course, this last step is much harder than it sounds.]
 Testing of U-Boot Modifications, Ports to New Hardware, etc.:
 ==============================================================
 If you have modified U-Boot sources (for instance added a new board
 or support for new devices, a new CPU, etc.) you are expected to
 provide feedback to the other developers. The feedback normally takes
 the form of a "patch", i. e. a context diff against a certain (latest
 official or latest in the git repository) version of U-Boot sources.
 But before you submit such a patch, please verify that your modifi-
 cation did not break existing code. At least make sure that *ALL* of
 the supported boards compile WITHOUT ANY compiler warnings. To do so,
 just run the buildman script (tools/buildman/buildman), which will
 configure and build U-Boot for ALL supported system. Be warned, this
 will take a while. Please see the buildman README, or run 'buildman -H'
 for documentation.
 See also "U-Boot Porting Guide" below.
 Monitor Commands - Overview:
 ============================
 go	- start application at address 'addr'
 run	- run commands in an environment variable
 bootm	- boot application image from memory
 bootp	- boot image via network using BootP/TFTP protocol
 bootz   - boot zImage from memory
 tftpboot- boot image via network using TFTP protocol
 	       and env variables "ipaddr" and "serverip"
 	       (and eventually "gatewayip")
 tftpput - upload a file via network using TFTP protocol
 rarpboot- boot image via network using RARP/TFTP protocol
 diskboot- boot from IDE devicebootd   - boot default, i.e., run 'bootcmd'
 loads	- load S-Record file over serial line
 loadb	- load binary file over serial line (kermit mode)
 md	- memory display
 mm	- memory modify (auto-incrementing)
 nm	- memory modify (constant address)
 mw	- memory write (fill)
 cp	- memory copy
 cmp	- memory compare
 crc32	- checksum calculation
 i2c	- I2C sub-system
 sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
 setenv	- set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection
 erase	- erase FLASH memory
 flinfo	- print FLASH memory information
 nand	- NAND memory operations (see doc/README.nand)
 bdinfo	- print Board Info structure
 iminfo	- print header information for application image
 coninfo - print console devices and informations
 ide	- IDE sub-system
 loop	- infinite loop on address range
 loopw	- infinite write loop on address range
 mtest	- simple RAM test
 icache	- enable or disable instruction cache
 dcache	- enable or disable data cache
 reset	- Perform RESET of the CPU
 echo	- echo args to console
 version - print monitor version
 help	- print online help
 ?	- alias for 'help'
 Monitor Commands - Detailed Description:
 ========================================
 TODO.
 For now: just type "help <command>".
 Environment Variables:
 ======================
 U-Boot supports user configuration using Environment Variables which
 can be made persistent by saving to Flash memory.
 Environment Variables are set using "setenv", printed using
 "printenv", and saved to Flash using "saveenv". Using "setenv"
 without a value can be used to delete a variable from the
 environment. As long as you don't save the environment you are
 working with an in-memory copy. In case the Flash area containing the
 environment is erased by accident, a default environment is provided.
 Some configuration options can be set using Environment Variables.
 List of environment variables (most likely not complete):
   baudrate	- see CONFIG_BAUDRATE
   bootdelay	- see CONFIG_BOOTDELAY
   bootcmd	- see CONFIG_BOOTCOMMAND
   bootargs	- Boot arguments when booting an RTOS image
   bootfile	- Name of the image to load with TFTP
   bootm_low	- Memory range available for image processing in the bootm
 		  command can be restricted. This variable is given as
 		  a hexadecimal number and defines lowest address allowed
 		  for use by the bootm command. See also "bootm_size"
 		  environment variable. Address defined by "bootm_low" is
 		  also the base of the initial memory mapping for the Linux
 		  kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
 		  bootm_mapsize.
   bootm_mapsize - Size of the initial memory mapping for the Linux kernel.
 		  This variable is given as a hexadecimal number and it
 		  defines the size of the memory region starting at base
 		  address bootm_low that is accessible by the Linux kernel
 		  during early boot.  If unset, CONFIG_SYS_BOOTMAPSZ is used
 		  as the default value if it is defined, and bootm_size is
 		  used otherwise.
   bootm_size	- Memory range available for image processing in the bootm
 		  command can be restricted. This variable is given as
 		  a hexadecimal number and defines the size of the region
 		  allowed for use by the bootm command. See also "bootm_low"
 		  environment variable.
   updatefile	- Location of the software update file on a TFTP server, used
 		  by the automatic software update feature. Please refer to
 		  documentation in doc/README.update for more details.
   autoload	- if set to "no" (any string beginning with 'n'),
 		  "bootp" will just load perform a lookup of the
 		  configuration from the BOOTP server, but not try to
 		  load any image using TFTP
   autostart	- if set to "yes", an image loaded using the "bootp",
 		  "rarpboot", "tftpboot" or "diskboot" commands will
 		  be automatically started (by internally calling
 		  "bootm")
 		  If set to "no", a standalone image passed to the
 		  "bootm" command will be copied to the load address
 		  (and eventually uncompressed), but NOT be started.
 		  This can be used to load and uncompress arbitrary
 		  data.
   fdt_high	- if set this restricts the maximum address that the
 		  flattened device tree will be copied into upon boot.
 		  For example, if you have a system with 1 GB memory
 		  at physical address 0x10000000, while Linux kernel
 		  only recognizes the first 704 MB as low memory, you
 		  may need to set fdt_high as 0x3C000000 to have the
 		  device tree blob be copied to the maximum address
 		  of the 704 MB low memory, so that Linux kernel can
 		  access it during the boot procedure.
 		  If this is set to the special value 0xFFFFFFFF then
 		  the fdt will not be copied at all on boot.  For this
 		  to work it must reside in writable memory, have
 		  sufficient padding on the end of it for u-boot to
 		  add the information it needs into it, and the memory
 		  must be accessible by the kernel.
   fdtcontroladdr- if set this is the address of the control flattened
 		  device tree used by U-Boot when CONFIG_OF_CONTROL is
 		  defined.
   i2cfast	- (PPC405GP|PPC405EP only)
 		  if set to 'y' configures Linux I2C driver for fast
 		  mode (400kHZ). This environment variable is used in
 		  initialization code. So, for changes to be effective
 		  it must be saved and board must be reset.
   initrd_high	- restrict positioning of initrd images:
 		  If this variable is not set, initrd images will be
 		  copied to the highest possible address in RAM; this
 		  is usually what you want since it allows for
 		  maximum initrd size. If for some reason you want to
 		  make sure that the initrd image is loaded below the
 		  CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
 		  variable to a value of "no" or "off" or "0".
 		  Alternatively, you can set it to a maximum upper
 		  address to use (U-Boot will still check that it
 		  does not overwrite the U-Boot stack and data).
 		  For instance, when you have a system with 16 MB
 		  RAM, and want to reserve 4 MB from use by Linux,
 		  you can do this by adding "mem=12M" to the value of
 		  the "bootargs" variable. However, now you must make
 		  sure that the initrd image is placed in the first
 		  12 MB as well - this can be done with
 		  setenv initrd_high 00c00000
 		  If you set initrd_high to 0xFFFFFFFF, this is an
 		  indication to U-Boot that all addresses are legal
 		  for the Linux kernel, including addresses in flash
 		  memory. In this case U-Boot will NOT COPY the
 		  ramdisk at all. This may be useful to reduce the
 		  boot time on your system, but requires that this
 		  feature is supported by your Linux kernel.
   ipaddr	- IP address; needed for tftpboot command
   loadaddr	- Default load address for commands like "bootp",
 		  "rarpboot", "tftpboot", "loadb" or "diskboot"
   loads_echo	- see CONFIG_LOADS_ECHO
   serverip	- TFTP server IP address; needed for tftpboot command
   bootretry	- see CONFIG_BOOT_RETRY_TIME
   bootdelaykey	- see CONFIG_AUTOBOOT_DELAY_STR
   bootstopkey	- see CONFIG_AUTOBOOT_STOP_STR
   ethprime	- controls which interface is used first.
   ethact	- controls which interface is currently active.
 		  For example you can do the following
 		  => setenv ethact FEC
 		  => ping 192.168.0.1 # traffic sent on FEC
 		  => setenv ethact SCC
 		  => ping 10.0.0.1 # traffic sent on SCC
   ethrotate	- When set to "no" U-Boot does not go through all
 		  available network interfaces.
 		  It just stays at the currently selected interface.
   netretry	- When set to "no" each network operation will
 		  either succeed or fail without retrying.
 		  When set to "once" the network operation will
 		  fail when all the available network interfaces
 		  are tried once without success.
 		  Useful on scripts which control the retry operation
 		  themselves.
   npe_ucode	- set load address for the NPE microcode
   silent_linux  - If set then Linux will be told to boot silently, by
 		  changing the console to be empty. If "yes" it will be
 		  made silent. If "no" it will not be made silent. If
 		  unset, then it will be made silent if the U-Boot console
 		  is silent.
   tftpsrcp	- If this is set, the value is used for TFTP's
 		  UDP source port.
   tftpdstp	- If this is set, the value is used for TFTP's UDP
 		  destination port instead of the Well Know Port 69.
   tftpblocksize - Block size to use for TFTP transfers; if not set,
 		  we use the TFTP server's default block size
   tftptimeout	- Retransmission timeout for TFTP packets (in milli-
 		  seconds, minimum value is 1000 = 1 second). Defines
 		  when a packet is considered to be lost so it has to
 		  be retransmitted. The default is 5000 = 5 seconds.
 		  Lowering this value may make downloads succeed
 		  faster in networks with high packet loss rates or
 		  with unreliable TFTP servers.
   tftptimeoutcountmax	- maximum count of TFTP timeouts (no
 		  unit, minimum value = 0). Defines how many timeouts
 		  can happen during a single file transfer before that
 		  transfer is aborted. The default is 10, and 0 means
 		  'no timeouts allowed'. Increasing this value may help
 		  downloads succeed with high packet loss rates, or with
 		  unreliable TFTP servers or client hardware.
   vlan		- When set to a value < 4095 the traffic over
 		  Ethernet is encapsulated/received over 802.1q
 		  VLAN tagged frames.
   bootpretryperiod	- Period during which BOOTP/DHCP sends retries.
 		  Unsigned value, in milliseconds. If not set, the period will
 		  be either the default (28000), or a value based on
 		  CONFIG_NET_RETRY_COUNT, if defined. This value has
 		  precedence over the valu based on CONFIG_NET_RETRY_COUNT.
 The following image location variables contain the location of images
 used in booting. The "Image" column gives the role of the image and is
 not an environment variable name. The other columns are environment
 variable names. "File Name" gives the name of the file on a TFTP
 server, "RAM Address" gives the location in RAM the image will be
 loaded to, and "Flash Location" gives the image's address in NOR
 flash or offset in NAND flash.
 *Note* - these variables don't have to be defined for all boards, some
 boards currently use other variables for these purposes, and some
 boards use these variables for other purposes.
 Image		    File Name	     RAM Address       Flash Location
 -----		    ---------	     -----------       --------------
 u-boot		    u-boot	     u-boot_addr_r     u-boot_addr
 Linux kernel	    bootfile	     kernel_addr_r     kernel_addr
 device tree blob    fdtfile	     fdt_addr_r	       fdt_addr
 ramdisk		    ramdiskfile	     ramdisk_addr_r    ramdisk_addr
 The following environment variables may be used and automatically
 updated by the network boot commands ("bootp" and "rarpboot"),
 depending the information provided by your boot server:
   bootfile	- see above
   dnsip		- IP address of your Domain Name Server
   dnsip2	- IP address of your secondary Domain Name Server
   gatewayip	- IP address of the Gateway (Router) to use
   hostname	- Target hostname
   ipaddr	- see above
   netmask	- Subnet Mask
   rootpath	- Pathname of the root filesystem on the NFS server
   serverip	- see above
 There are two special Environment Variables:
   serial#	- contains hardware identification information such
 		  as type string and/or serial number
   ethaddr	- Ethernet address
 These variables can be set only once (usually during manufacturing of
 the board). U-Boot refuses to delete or overwrite these variables
 once they have been set once.
 Further special Environment Variables:
   ver		- Contains the U-Boot version string as printed
 		  with the "version" command. This variable is
 		  readonly (see CONFIG_VERSION_VARIABLE).
 Please note that changes to some configuration parameters may take
 only effect after the next boot (yes, that's just like Windoze :-).
 Callback functions for environment variables:
 ---------------------------------------------
 For some environment variables, the behavior of u-boot needs to change
 when their values are changed.  This functionality allows functions to
 be associated with arbitrary variables.  On creation, overwrite, or
 deletion, the callback will provide the opportunity for some side
 effect to happen or for the change to be rejected.
 The callbacks are named and associated with a function using the
 U_BOOT_ENV_CALLBACK macro in your board or driver code.
 These callbacks are associated with variables in one of two ways.  The
 static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
 in the board configuration to a string that defines a list of
 associations.  The list must be in the following format:
 	entry = variable_name[:callback_name]
 	list = entry[,list]
 If the callback name is not specified, then the callback is deleted.
 Spaces are also allowed anywhere in the list.
 Callbacks can also be associated by defining the ".callbacks" variable
 with the same list format above.  Any association in ".callbacks" will
 override any association in the static list. You can define
 CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
 ".callbacks" environment variable in the default or embedded environment.
 If CONFIG_REGEX is defined, the variable_name above is evaluated as a
 regular expression. This allows multiple variables to be connected to
 the same callback without explicitly listing them all out.
 Command Line Parsing:
 =====================
 There are two different command line parsers available with U-Boot:
 the old "simple" one, and the much more powerful "hush" shell:
 Old, simple command line parser:
 --------------------------------
 - supports environment variables (through setenv / saveenv commands)
 - several commands on one line, separated by ';'
 - variable substitution using "... ${name} ..." syntax
 - special characters ('$', ';') can be escaped by prefixing with '\',
   for example:
 	setenv bootcmd bootm \${address}
 - You can also escape text by enclosing in single apostrophes, for example:
 	setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off'
 Hush shell:
 -----------
 - similar to Bourne shell, with control structures like
   if...then...else...fi, for...do...done; while...do...done,
   until...do...done, ...
 - supports environment ("global") variables (through setenv / saveenv
   commands) and local shell variables (through standard shell syntax
   "name=value"); only environment variables can be used with "run"
   command
 General rules:
 --------------
 (1) If a command line (or an environment variable executed by a "run"
     command) contains several commands separated by semicolon, and
     one of these commands fails, then the remaining commands will be
     executed anyway.
 (2) If you execute several variables with one call to run (i. e.
     calling run with a list of variables as arguments), any failing
     command will cause "run" to terminate, i. e. the remaining
     variables are not executed.
 Note for Redundant Ethernet Interfaces:
 =======================================
 Some boards come with redundant Ethernet interfaces; U-Boot supports
 such configurations and is capable of automatic selection of a
 "working" interface when needed. MAC assignment works as follows:
 Network interfaces are numbered eth0, eth1, eth2, ... Corresponding
 MAC addresses can be stored in the environment as "ethaddr" (=>eth0),
 "eth1addr" (=>eth1), "eth2addr", ...
 If the network interface stores some valid MAC address (for instance
 in SROM), this is used as default address if there is NO correspon-
 ding setting in the environment; if the corresponding environment
 variable is set, this overrides the settings in the card; that means:
 o If the SROM has a valid MAC address, and there is no address in the
   environment, the SROM's address is used.
 o If there is no valid address in the SROM, and a definition in the
   environment exists, then the value from the environment variable is
   used.
 o If both the SROM and the environment contain a MAC address, and
   both addresses are the same, this MAC address is used.
 o If both the SROM and the environment contain a MAC address, and the
   addresses differ, the value from the environment is used and a
   warning is printed.
 o If neither SROM nor the environment contain a MAC address, an error
   is raised. If CONFIG_NET_RANDOM_ETHADDR is defined, then in this case
   a random, locally-assigned MAC is used.
 If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
 will be programmed into hardware as part of the initialization process.	 This
 may be skipped by setting the appropriate 'ethmacskip' environment variable.
 The naming convention is as follows:
 "ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc.
 Image Formats:
 ==============
 U-Boot is capable of booting (and performing other auxiliary operations on)
 images in two formats:
 New uImage format (FIT)
 -----------------------
 Flexible and powerful format based on Flattened Image Tree -- FIT (similar
 to Flattened Device Tree). It allows the use of images with multiple
 components (several kernels, ramdisks, etc.), with contents protected by
 SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
 Old uImage format
 -----------------
 Old image format is based on binary files which can be basically anything,
 preceded by a special header; see the definitions in include/image.h for
 details; basically, the header defines the following image properties:
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
   LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
   IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
 * Image Name
 * Image Timestamp
 The header is marked by a special Magic Number, and both the header
 and the data portions of the image are secured against corruption by
 CRC32 checksums.
 Linux Support:
 ==============
 Although U-Boot should support any OS or standalone application
 easily, the main focus has always been on Linux during the design of
 U-Boot.
 U-Boot includes many features that so far have been part of some
 special "boot loader" code within the Linux kernel. Also, any
 "initrd" images to be used are no longer part of one big Linux image;
 instead, kernel and "initrd" are separate images. This implementation
 serves several purposes:
 - the same features can be used for other OS or standalone
   applications (for instance: using compressed images to reduce the
   Flash memory footprint)
 - it becomes much easier to port new Linux kernel versions because
   lots of low-level, hardware dependent stuff are done by U-Boot
 - the same Linux kernel image can now be used with different "initrd"
   images; of course this also means that different kernel images can
   be run with the same "initrd". This makes testing easier (you don't
   have to build a new "zImage.initrd" Linux image when you just
   change a file in your "initrd"). Also, a field-upgrade of the
   software is easier now.
 Linux HOWTO:
 ============
 Porting Linux to U-Boot based systems:
 ---------------------------------------
 U-Boot cannot save you from doing all the necessary modifications to
 configure the Linux device drivers for use with your target hardware
 (no, we don't intend to provide a full virtual machine interface to
 Linux :-).
 But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot).
 Just make sure your machine specific header file (for instance
 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
 Information structure as we define in include/asm-<arch>/u-boot.h,
 and make sure that your definition of IMAP_ADDR uses the same value
 as your U-Boot configuration in CONFIG_SYS_IMMR.
 Note that U-Boot now has a driver model, a unified model for drivers.
 If you are adding a new driver, plumb it into driver model. If there
 is no uclass available, you are encouraged to create one. See
 doc/driver-model.
 Configuring the Linux kernel:
 -----------------------------
 No specific requirements for U-Boot. Make sure you have some root
 device (initial ramdisk, NFS) for your target system.
 Building a Linux Image:
 -----------------------
 With U-Boot, "normal" build targets like "zImage" or "bzImage" are
 not used. If you use recent kernel source, a new build target
 "uImage" will exist which automatically builds an image usable by
 U-Boot. Most older kernels also have support for a "pImage" target,
 which was introduced for our predecessor project PPCBoot and uses a
 100% compatible format.
 Example:
 	make TQM850L_defconfig
 	make oldconfig
 	make dep
 	make uImage
 The "uImage" build target uses a special tool (in 'tools/mkimage') to
 encapsulate a compressed Linux kernel image with header	 information,
 CRC32 checksum etc. for use with U-Boot. This is what we are doing:
 * build a standard "vmlinux" kernel image (in ELF binary format):
 * convert the kernel into a raw binary image:
 	${CROSS_COMPILE}-objcopy -O binary \
 				 -R .note -R .comment \
 				 -S vmlinux linux.bin
 * compress the binary image:
 	gzip -9 linux.bin
 * package compressed binary image for U-Boot:
 	mkimage -A ppc -O linux -T kernel -C gzip \
 		-a 0 -e 0 -n "Linux Kernel Image" \
 		-d linux.bin.gz uImage
 The "mkimage" tool can also be used to create ramdisk images for use
 with U-Boot, either separated from the Linux kernel image, or
 combined into one file. "mkimage" encapsulates the images with a 64
 byte header containing information about target architecture,
 operating system, image type, compression method, entry points, time
 stamp, CRC32 checksums, etc.
 "mkimage" can be called in two ways: to verify existing images and
 print the header information, or to build new images.
 In the first form (with "-l" option) mkimage lists the information
 contained in the header of an existing U-Boot image; this includes
 checksum verification:
 	tools/mkimage -l image
 	  -l ==> list image header information
 The second form (with "-d" option) is used to build a U-Boot image
 from a "data file" which is used as image payload:
 	tools/mkimage -A arch -O os -T type -C comp -a addr -e ep \
 		      -n name -d data_file image
 	  -A ==> set architecture to 'arch'
 	  -O ==> set operating system to 'os'
 	  -T ==> set image type to 'type'
 	  -C ==> set compression type 'comp'
 	  -a ==> set load address to 'addr' (hex)
 	  -e ==> set entry point to 'ep' (hex)
 	  -n ==> set image name to 'name'
 	  -d ==> use image data from 'datafile'
 Right now, all Linux kernels for PowerPC systems use the same load
 address (0x00000000), but the entry point address depends on the
 kernel version:
 - 2.2.x kernels have the entry point at 0x0000000C,
 - 2.3.x and later kernels have the entry point at 0x00000000.
 So a typical call to build a U-Boot image would read:
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
 	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \
 	> examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (gzip compressed)
 	Data Size:    335725 Bytes = 327.86 kB = 0.32 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 To verify the contents of the image (or check for corruption):
 	-> tools/mkimage -l examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (gzip compressed)
 	Data Size:    335725 Bytes = 327.86 kB = 0.32 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 NOTE: for embedded systems where boot time is critical you can trade
 speed for memory and install an UNCOMPRESSED image instead: this
 needs more space in Flash, but boots much faster since it does not
 need to be uncompressed:
 	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C none -a 0 -e 0 \
 	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \
 	> examples/uImage.TQM850L-uncompressed
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (uncompressed)
 	Data Size:    792160 Bytes = 773.59 kB = 0.76 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 Similar you can build U-Boot images from a 'ramdisk.image.gz' file
 when your kernel is intended to use an initial ramdisk:
 	-> tools/mkimage -n 'Simple Ramdisk Image' \
 	> -A ppc -O linux -T ramdisk -C gzip \
 	> -d /LinuxPPC/images/SIMPLE-ramdisk.image.gz examples/simple-initrd
 	Image Name:   Simple Ramdisk Image
 	Created:      Wed Jan 12 14:01:50 2000
 	Image Type:   PowerPC Linux RAMDisk Image (gzip compressed)
 	Data Size:    566530 Bytes = 553.25 kB = 0.54 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i"
 option performs the converse operation of the mkimage's second form (the "-d"
 option). Given an image built by mkimage, the dumpimage extracts a "data file"
 from the image:
 	tools/dumpimage -i image -T type -p position data_file
 	  -i ==> extract from the 'image' a specific 'data_file'
 	  -T ==> set image type to 'type'
 	  -p ==> 'position' (starting at 0) of the 'data_file' inside the 'image'
 Installing a Linux Image:
 -------------------------
 To downloading a U-Boot image over the serial (console) interface,
 you must convert the image to S-Record format:
 	objcopy -I binary -O srec examples/image examples/image.srec
 The 'objcopy' does not understand the information in the U-Boot
 image header, so the resulting S-Record file will be relative to
 address 0x00000000. To load it to a given address, you need to
 specify the target address as 'offset' parameter with the 'loads'
 command.
 Example: install the image to address 0x40100000 (which on the
 TQM8xxL is in the first Flash bank):
 	=> erase 40100000 401FFFFF
 	.......... done
 	Erased 8 sectors
 	=> loads 40100000
 	## Ready for S-Record download ...
 	~>examples/image.srec
 	1 2 3 4 5 6 7 8 9 10 11 12 13 ...
 	...
 	15989 15990 15991 15992
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00000000
 You can check the success of the download using the 'iminfo' command;
 this includes a checksum verification so you can be sure no data
 corruption happened:
 	=> imi 40100000
 	## Checking Image at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 Boot Linux:
 -----------
 The "bootm" command is used to boot an application that is stored in
 memory (RAM or Flash). In case of a Linux kernel image, the contents
 of the "bootargs" environment variable is passed to the kernel as
 parameters. You can check and modify this variable using the
 "printenv" and "setenv" commands:
 	=> printenv bootargs
 	bootargs=root=/dev/ram
 	=> setenv bootargs root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	=> printenv bootargs
 	bootargs=root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	=> bootm 40020000
 	## Booting Linux kernel at 40020000 ...
 	   Image Name:	 2.2.13 for NFS on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 381681 Bytes = 372 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	   Uncompressing Kernel Image ... OK
 	Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:35:17 MEST 2000
 	Boot arguments: root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	time_init: decrementer frequency = 187500000/60
 	Calibrating delay loop... 49.77 BogoMIPS
 	Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000]
 	...
 If you want to boot a Linux kernel with initial RAM disk, you pass
 the memory addresses of both the kernel and the initrd image (PPBCOOT
 format!) to the "bootm" command:
 	=> imi 40100000 40200000
 	## Checking Image at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	## Checking Image at 40200000 ...
 	   Image Name:	 Simple Ramdisk Image
 	   Image Type:	 PowerPC Linux RAMDisk Image (gzip compressed)
 	   Data Size:	 566530 Bytes = 553 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 00000000
 	   Verifying Checksum ... OK
 	=> bootm 40100000 40200000
 	## Booting Linux kernel at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	   Uncompressing Kernel Image ... OK
 	## Loading RAMDisk Image at 40200000 ...
 	   Image Name:	 Simple Ramdisk Image
 	   Image Type:	 PowerPC Linux RAMDisk Image (gzip compressed)
 	   Data Size:	 566530 Bytes = 553 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 00000000
 	   Verifying Checksum ... OK
 	   Loading Ramdisk ... OK
 	Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:32:08 MEST 2000
 	Boot arguments: root=/dev/ram
 	time_init: decrementer frequency = 187500000/60
 	Calibrating delay loop... 49.77 BogoMIPS
 	...
 	RAMDISK: Compressed image found at block 0
 	VFS: Mounted root (ext2 filesystem).
 	bash#
 Boot Linux and pass a flat device tree:
 -----------
 First, U-Boot must be compiled with the appropriate defines. See the section
 titled "Linux Kernel Interface" above for a more in depth explanation. The
 following is an example of how to start a kernel and pass an updated
 flat device tree:
 => print oftaddr
 oftaddr=0x300000
 => print oft
 oft=oftrees/mpc8540ads.dtb
 => tftp $oftaddr $oft
 Speed: 1000, full duplex
 Using TSEC0 device
 TFTP from server 192.168.1.1; our IP address is 192.168.1.101
 Filename 'oftrees/mpc8540ads.dtb'.
 Load address: 0x300000
 Loading: #
 done
 Bytes transferred = 4106 (100a hex)
 => tftp $loadaddr $bootfile
 Speed: 1000, full duplex
 Using TSEC0 device
 TFTP from server 192.168.1.1; our IP address is 192.168.1.2
 Filename 'uImage'.
 Load address: 0x200000
 Loading:############
 done
 Bytes transferred = 1029407 (fb51f hex)
 => print loadaddr
 loadaddr=200000
 => print oftaddr
 oftaddr=0x300000
 => bootm $loadaddr - $oftaddr
 ## Booting image at 00200000 ...
    Image Name:	 Linux-2.6.17-dirty
    Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
    Data Size:	 1029343 Bytes = 1005.2 kB
    Load Address: 00000000
    Entry Point:	 00000000
    Verifying Checksum ... OK
    Uncompressing Kernel Image ... OK
 Booting using flat device tree at 0x300000
 Using MPC85xx ADS machine description
 Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
 [snip]
 More About U-Boot Image Types:
 ------------------------------
 U-Boot supports the following image types:
    "Standalone Programs" are directly runnable in the environment
 	provided by U-Boot; it is expected that (if they behave
 	well) you can continue to work in U-Boot after return from
 	the Standalone Program.
    "OS Kernel Images" are usually images of some Embedded OS which
 	will take over control completely. Usually these programs
 	will install their own set of exception handlers, device
 	drivers, set up the MMU, etc. - this means, that you cannot
 	expect to re-enter U-Boot except by resetting the CPU.
    "RAMDisk Images" are more or less just data blocks, and their
 	parameters (address, size) are passed to an OS kernel that is
 	being started.
    "Multi-File Images" contain several images, typically an OS
 	(Linux) kernel image and one or more data images like
 	RAMDisks. This construct is useful for instance when you want
 	to boot over the network using BOOTP etc., where the boot
 	server provides just a single image file, but you want to get
 	for instance an OS kernel and a RAMDisk image.
 	"Multi-File Images" start with a list of image sizes, each
 	image size (in bytes) specified by an "uint32_t" in network
 	byte order. This list is terminated by an "(uint32_t)0".
 	Immediately after the terminating 0 follow the images, one by
 	one, all aligned on "uint32_t" boundaries (size rounded up to
 	a multiple of 4 bytes).
    "Firmware Images" are binary images containing firmware (like
 	U-Boot or FPGA images) which usually will be programmed to
 	flash memory.
    "Script files" are command sequences that will be executed by
 	U-Boot's command interpreter; this feature is especially
 	useful when you configure U-Boot to use a real shell (hush)
 	as command interpreter.
 Booting the Linux zImage:
 -------------------------
 On some platforms, it's possible to boot Linux zImage. This is done
 using the "bootz" command. The syntax of "bootz" command is the same
 as the syntax of "bootm" command.
 Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
 kernel with raw initrd images. The syntax is slightly different, the
 address of the initrd must be augmented by it's size, in the following
 format: "<initrd addres>:<initrd size>".
 Standalone HOWTO:
 =================
 One of the features of U-Boot is that you can dynamically load and
 run "standalone" applications, which can use some resources of
 U-Boot like console I/O functions or interrupt services.
 Two simple examples are included with the sources:
 "Hello World" Demo:
 -------------------
 'examples/hello_world.c' contains a small "Hello World" Demo
 application; it is automatically compiled when you build U-Boot.
 It's configured to run at address 0x00040004, so you can play with it
 like that:
 	=> loads
 	## Ready for S-Record download ...
 	~>examples/hello_world.srec
 	1 2 3 4 5 6 7 8 9 10 11 ...
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00040004
 	=> go 40004 Hello World! This is a test.
 	## Starting application at 0x00040004 ...
 	Hello World
 	argc = 7
 	argv[0] = "40004"
 	argv[1] = "Hello"
 	argv[2] = "World!"
 	argv[3] = "This"
 	argv[4] = "is"
 	argv[5] = "a"
 	argv[6] = "test."
 	argv[7] = "<NULL>"
 	Hit any key to exit ...
 	## Application terminated, rc = 0x0
 Another example, which demonstrates how to register a CPM interrupt
 handler with the U-Boot code, can be found in 'examples/timer.c'.
 Here, a CPM timer is set up to generate an interrupt every second.
 The interrupt service routine is trivial, just printing a '.'
 character, but this is just a demo program. The application can be
 controlled by the following keys:
 	? - print current values og the CPM Timer registers
 	b - enable interrupts and start timer
 	e - stop timer and disable interrupts
 	q - quit application
 	=> loads
 	## Ready for S-Record download ...
 	~>examples/timer.srec
 	1 2 3 4 5 6 7 8 9 10 11 ...
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00040004
 	=> go 40004
 	## Starting application at 0x00040004 ...
 	TIMERS=0xfff00980
 	Using timer 1
 	  tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0xfff009b0
 Hit 'b':
 	[q, b, e, ?] Set interval 1000000 us
 	Enabling timer
 Hit '?':
 	[q, b, e, ?] ........
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0
 Hit 'e':
 	[q, b, e, ?] ...Stopping timer
 Hit 'q':
 	[q, b, e, ?] ## Application terminated, rc = 0x0
 Minicom warning:
 ================
 Over time, many people have reported problems when trying to use the
 "minicom" terminal emulation program for serial download. I (wd)
 consider minicom to be broken, and recommend not to use it. Under
 Unix, I recommend to use C-Kermit for general purpose use (and
 especially for kermit binary protocol download ("loadb" command), and
 use "cu" for S-Record download ("loads" command).  See
 http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
 for help with kermit.
 Nevertheless, if you absolutely want to use it try adding this
 configuration to your "File transfer protocols" section:
 	   Name	   Program			Name U/D FullScr IO-Red. Multi
 	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
 	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N
 NetBSD Notes:
 =============
 Starting at version 0.9.2, U-Boot supports NetBSD both as host
 (build U-Boot) and target system (boots NetBSD/mpc8xx).
 Building requires a cross environment; it is known to work on
 NetBSD/i386 with the cross-powerpc-netbsd-1.3 package (you will also
 need gmake since the Makefiles are not compatible with BSD make).
 Note that the cross-powerpc package does not install include files;
 attempting to build U-Boot will fail because <machine/ansi.h> is
 missing.  This file has to be installed and patched manually:
 	# cd /usr/pkg/cross/powerpc-netbsd/include
 	# mkdir powerpc
 	# ln -s powerpc machine
 	# cp /usr/src/sys/arch/powerpc/include/ansi.h powerpc/ansi.h
 	# ${EDIT} powerpc/ansi.h	## must remove __va_list, _BSD_VA_LIST
 Native builds *don't* work due to incompatibilities between native
 and U-Boot include files.
 Booting assumes that (the first part of) the image booted is a
 stage-2 loader which in turn loads and then invokes the kernel
 proper. Loader sources will eventually appear in the NetBSD source
 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the
 meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz
 Implementation Internals:
 =========================
 The following is not intended to be a complete description of every
 implementation detail. However, it should help to understand the
 inner workings of U-Boot and make it easier to port it to custom
 hardware.
 Initial Stack, Global Data:
 ---------------------------
 The implementation of U-Boot is complicated by the fact that U-Boot
 starts running out of ROM (flash memory), usually without access to
 system RAM (because the memory controller is not initialized yet).
 This means that we don't have writable Data or BSS segments, and BSS
 is not initialized as zero. To be able to get a C environment working
 at all, we have to allocate at least a minimal stack. Implementation
 options for this are defined and restricted by the CPU used: Some CPU
 models provide on-chip memory (like the IMMR area on MPC8xx and
 MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.
 	Chris Hallinan posted a good summary of these issues to the
 	U-Boot mailing list:
 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
 	From: "Chris Hallinan" <clh@net1plus.com>
 	Date: Mon, 10 Feb 2003 16:43:46 -0500 (22:43 MET)
 	...
 	Correct me if I'm wrong, folks, but the way I understand it
 	is this: Using DCACHE as initial RAM for Stack, etc, does not
 	require any physical RAM backing up the cache. The cleverness
 	is that the cache is being used as a temporary supply of
 	necessary storage before the SDRAM controller is setup. It's
 	beyond the scope of this list to explain the details, but you
 	can see how this works by studying the cache architecture and
 	operation in the architecture and processor-specific manuals.
 	OCM is On Chip Memory, which I believe the 405GP has 4K. It
 	is another option for the system designer to use as an
 	initial stack/RAM area prior to SDRAM being available. Either
 	option should work for you. Using CS 4 should be fine if your
 	board designers haven't used it for something that would
 	cause you grief during the initial boot! It is frequently not
 	used.
 	CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
 	with your processor/board/system design. The default value
 	you will find in any recent u-boot distribution in
 	walnut.h should work for you. I'd set it to a value larger
 	than your SDRAM module. If you have a 64MB SDRAM module, set
 	it above 400_0000. Just make sure your board has no resources
 	that are supposed to respond to that address! That code in
 	start.S has been around a while and should work as is when
 	you get the config right.
 	-Chris Hallinan
 	DS4.COM, Inc.
 It is essential to remember this, since it has some impact on the C
 code for the initialization procedures:
 * Initialized global data (data segment) is read-only. Do not attempt
   to write it.
 * Do not use any uninitialized global data (or implicitly initialized
   as zero data - BSS segment) at all - this is undefined, initiali-
   zation is performed later (when relocating to RAM).
 * Stack space is very limited. Avoid big data buffers or things like
   that.
 Having only the stack as writable memory limits means we cannot use
 normal global data to share information between the code. But it
 turned out that the implementation of U-Boot can be greatly
 simplified by making a global data structure (gd_t) available to all
 functions. We could pass a pointer to this data as argument to _all_
 functions, but this would bloat the code. Instead we use a feature of
 the GCC compiler (Global Register Variables) to share the data: we
 place a pointer (gd) to the global data into a register which we
 reserve for this purpose.
 When choosing a register for such a purpose we are restricted by the
 relevant  (E)ABI  specifications for the current architecture, and by
 GCC's implementation.
 For PowerPC, the following registers have specific use:
 	R1:	stack pointer
 	R2:	reserved for system use
 	R3-R4:	parameter passing and return values
 	R5-R10: parameter passing
 	R13:	small data area pointer
 	R30:	GOT pointer
 	R31:	frame pointer
 	(U-Boot also uses R12 as internal GOT pointer. r12
 	is a volatile register so r12 needs to be reset when
 	going back and forth between asm and C)
     ==> U-Boot will use R2 to hold a pointer to the global data
     Note: on PPC, we could use a static initializer (since the
     address of the global data structure is known at compile time),
     but it turned out that reserving a register results in somewhat
     smaller code - although the code savings are not that big (on
     average for all boards 752 bytes for the whole U-Boot image,
     624 text + 127 data).
 On Blackfin, the normal C ABI (except for P3) is followed as documented here:
 	http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
     ==> U-Boot will use P3 to hold a pointer to the global data
 On ARM, the following registers are used:
 	R0:	function argument word/integer result
 	R1-R3:	function argument word
 	R9:	platform specific
 	R10:	stack limit (used only if stack checking is enabled)
 	R11:	argument (frame) pointer
 	R12:	temporary workspace
 	R13:	stack pointer
 	R14:	link register
 	R15:	program counter
     ==> U-Boot will use R9 to hold a pointer to the global data
     Note: on ARM, only R_ARM_RELATIVE relocations are supported.
 On Nios II, the ABI is documented here:
 	http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
     ==> U-Boot will use gp to hold a pointer to the global data
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 On NDS32, the following registers are used:
 	R0-R1:	argument/return
 	R2-R5:	argument
 	R15:	temporary register for assembler
 	R16:	trampoline register
 	R28:	frame pointer (FP)
 	R29:	global pointer (GP)
 	R30:	link register (LP)
 	R31:	stack pointer (SP)
 	PC:	program counter (PC)
     ==> U-Boot will use R10 to hold a pointer to the global data
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 Memory Management:
 ------------------
 U-Boot runs in system state and uses physical addresses, i.e. the
 MMU is not used either for address mapping nor for memory protection.
 The available memory is mapped to fixed addresses using the memory
 controller. In this process, a contiguous block is formed for each
 memory type (Flash, SDRAM, SRAM), even when it consists of several
 physical memory banks.
 U-Boot is installed in the first 128 kB of the first Flash bank (on
 TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After
 booting and sizing and initializing DRAM, the code relocates itself
 to the upper end of DRAM. Immediately below the U-Boot code some
 memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN
 configuration setting]. Below that, a structure with global Board
 Info data is placed, followed by the stack (growing downward).
 Additionally, some exception handler code is copied to the low 8 kB
 of DRAM (0x00000000 ... 0x00001FFF).
 So a typical memory configuration with 16 MB of DRAM could look like
 this:
 	0x0000 0000	Exception Vector code
 	      :
 	0x0000 1FFF
 	0x0000 2000	Free for Application Use
 	      :
 	      :
 	      :
 	      :
 	0x00FB FF20	Monitor Stack (Growing downward)
 	0x00FB FFAC	Board Info Data and permanent copy of global data
 	0x00FC 0000	Malloc Arena
 	      :
 	0x00FD FFFF
 	0x00FE 0000	RAM Copy of Monitor Code
 	...		eventually: LCD or video framebuffer
 	...		eventually: pRAM (Protected RAM - unchanged by reset)
 	0x00FF FFFF	[End of RAM]
 System Initialization:
 ----------------------
 In the reset configuration, U-Boot starts at the reset entry point
 (on most PowerPC systems at address 0x00000100). Because of the reset
 configuration for CS0# this is a mirror of the on board Flash memory.
 To be able to re-map memory U-Boot then jumps to its link address.
 To be able to implement the initialization code in C, a (small!)
 initial stack is set up in the internal Dual Ported RAM (in case CPUs
 which provide such a feature like MPC8xx or MPC8260), or in a locked
 part of the data cache. After that, U-Boot initializes the CPU core,
 the caches and the SIU.
 Next, all (potentially) available memory banks are mapped using a
 preliminary mapping. For example, we put them on 512 MB boundaries
 (multiples of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash
 on 0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is
 programmed for SDRAM access. Using the temporary configuration, a
 simple memory test is run that determines the size of the SDRAM
 banks.
 When there is more than one SDRAM bank, and the banks are of
 different size, the largest is mapped first. For equal size, the first
 bank (CS2#) is mapped first. The first mapping is always for address
 0x00000000, with any additional banks following immediately to create
 contiguous memory starting from 0.
 Then, the monitor installs itself at the upper end of the SDRAM area
 and allocates memory for use by malloc() and for the global Board
 Info data; also, the exception vector code is copied to the low RAM
 pages, and the final stack is set up.
 Only after this relocation will you have a "normal" C environment;
 until that you are restricted in several ways, mostly because you are
 running from ROM, and because the code will have to be relocated to a
 new address in RAM.
 U-Boot Porting Guide:
 ----------------------
 [Based on messages by Jerry Van Baren in the U-Boot-Users mailing
 list, October 2002]
 int main(int argc, char *argv[])
 {
 	sighandler_t no_more_time;
 	signal(SIGALRM, no_more_time);
 	alarm(PROJECT_DEADLINE - toSec (3 * WEEK));
 	if (available_money > available_manpower) {
 		Pay consultant to port U-Boot;
 		return 0;
 	}
 	Download latest U-Boot source;
 	Subscribe to u-boot mailing list;
 	if (clueless)
 		email("Hi, I am new to U-Boot, how do I get started?");
 	while (learning) {
 		Read the README file in the top level directory;
 		Read http://www.denx.de/twiki/bin/view/DULG/Manual;
 		Read applicable doc/*.README;
 		Read the source, Luke;
 		/* find . -name "*.[chS]" | xargs grep -i <keyword> */
 	}
 	if (available_money > toLocalCurrency ($2500))
 		Buy a BDI3000;
 	else
 		Add a lot of aggravation and time;
 	if (a similar board exists) {	/* hopefully... */
 		cp -a board/<similar> board/<myboard>
 		cp include/configs/<similar>.h include/configs/<myboard>.h
 	} else {
 		Create your own board support subdirectory;
 		Create your own board include/configs/<myboard>.h file;
 	}
 	Edit new board/<myboard> files
 	Edit new include/configs/<myboard>.h
 	while (!accepted) {
 		while (!running) {
 			do {
 				Add / modify source code;
 			} until (compiles);
 			Debug;
 			if (clueless)
 				email("Hi, I am having problems...");
 		}
 		Send patch file to the U-Boot email list;
 		if (reasonable critiques)
 			Incorporate improvements from email list code review;
 		else
 			Defend code as written;
 	}
 	return 0;
 }
 void no_more_time (int sig)
 {
       hire_a_guru();
 }
 Coding Standards:
 -----------------
 All contributions to U-Boot should conform to the Linux kernel
 coding style; see the file "Documentation/CodingStyle" and the script
 "scripts/Lindent" in your Linux kernel source directory.
 Source files originating from a different project (for example the
 MTD subsystem) are generally exempt from these guidelines and are not
 reformatted to ease subsequent migration to newer versions of those
 sources.
 Please note that U-Boot is implemented in C (and to some small parts in
 Assembler); no C++ is used, so please do not use C++ style comments (//)
 in your code.
 Please also stick to the following formatting rules:
 - remove any trailing white space
 - use TAB characters for indentation and vertical alignment, not spaces
 - make sure NOT to use DOS '\r\n' line feeds
 - do not add more than 2 consecutive empty lines to source files
 - do not add trailing empty lines to source files
 Submissions which do not conform to the standards may be returned
 with a request to reformat the changes.
 Submitting Patches:
 -------------------
 Since the number of patches for U-Boot is growing, we need to
 establish some rules. Submissions which do not conform to these rules
 may be rejected, even when they contain important and valuable stuff.
 Please see http://www.denx.de/wiki/U-Boot/Patches for details.
 Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
 see http://lists.denx.de/mailman/listinfo/u-boot
 When you send a patch, please include the following information with
 it:
 * For bug fixes: a description of the bug and how your patch fixes
   this bug. Please try to include a way of demonstrating that the
   patch actually fixes something.
 * For new features: a description of the feature and your
   implementation.
 * A CHANGELOG entry as plaintext (separate from the patch)
 * For major contributions, add a MAINTAINERS file with your
   information and associated file and directory references.
 * When you add support for a new board, don't forget to add a
   maintainer e-mail address to the boards.cfg file, too.
 * If your patch adds new configuration options, don't forget to
   document these in the README file.
 * The patch itself. If you are using git (which is *strongly*
   recommended) you can easily generate the patch using the
   "git format-patch". If you then use "git send-email" to send it to
   the U-Boot mailing list, you will avoid most of the common problems
   with some other mail clients.
   If you cannot use git, use "diff -purN OLD NEW". If your version of
   diff does not support these options, then get the latest version of
   GNU diff.
   The current directory when running this command shall be the parent
   directory of the U-Boot source tree (i. e. please make sure that
   your patch includes sufficient directory information for the
   affected files).
   We prefer patches as plain text. MIME attachments are discouraged,
   and compressed attachments must not be used.
 * If one logical set of modifications affects or creates several
   files, all these changes shall be submitted in a SINGLE patch file.
 * Changesets that contain different, unrelated modifications shall be
   submitted as SEPARATE patches, one patch per changeset.
 Notes:
 * Before sending the patch, run the buildman script on your patched
   source tree and make sure that no errors or warnings are reported
   for any of the boards.
 * Keep your modifications to the necessary minimum: A patch
   containing several unrelated changes or arbitrary reformats will be
   returned with a request to re-formatting / split it.
 * If you modify existing code, make sure that your new code does not
   add to the memory footprint of the code ;-) Small is beautiful!
   When adding new features, these should compile conditionally only
   (using #ifdef), and the resulting code with the new feature
   disabled must not need more memory than the old code without your
   modification.
 * Remember that there is a size limit of 100 kB per message on the
   u-boot mailing list. Bigger patches will be moderated. If they are
   reasonable and not too big, they will be acknowledged. But patches
   bigger than the size limit should be avoided.

configs/bayleybay_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
 CONFIG_TARGET_BAYLEYBAY=y
 CONFIG_INTERNAL_UART=y
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_VGA_BIOS_ADDR=0xfffa0000
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/chromebook_jerry_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_MMC_SUPPORT is not set
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_CHROMEBOOK_JERRY=y
 CONFIG_ROCKCHIP_FAST_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
 CONFIG_SILENT_CONSOLE=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_I2C_MUX=y
 CONFIG_DM_KEYBOARD=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_RK3288_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK808=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_REGULATOR_RK808=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y

configs/chromebook_link_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_SYS_MALLOC_F_LEN=0x1800
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
 CONFIG_TARGET_CHROMEBOOK_LINK=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_HAVE_MRC=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_TPM_TIS_LPC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_VIDEO_IVYBRIDGE_IGD=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y

configs/chromebook_samus_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_SYS_MALLOC_F_LEN=0x1800
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
 CONFIG_TARGET_CHROMEBOOK_SAMUS=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_HAVE_MRC=y
 CONFIG_HAVE_REFCODE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_INTEL_BROADWELL_GPIO=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_TPM_TIS_LPC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_VIDEO_BROADWELL_IGD=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y

configs/chromebox_panther_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
 CONFIG_TARGET_CHROMEBOX_PANTHER=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_HAVE_MRC=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_RTL8169=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_TPM_TIS_LPC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y

configs/colibri_t20_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_TEGRA=y
 CONFIG_TEGRA20=y
 CONFIG_TARGET_COLIBRI_T20=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri T20 # "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10

configs/conga-qeval20-qa3-e3845-internal-uart_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_VENDOR_CONGATEC=y
 CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
 CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
 CONFIG_INTERNAL_UART=y
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_114=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/conga-qeval20-qa3-e3845_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_VENDOR_CONGATEC=y
 CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
 CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_114=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/coreboot-x86_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_VENDOR_COREBOOT=y
 CONFIG_TARGET_COREBOOT=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_TPM_TIS_LPC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_COREBOOT=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y

configs/crownbay_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_MAX_CPUS=2
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="crownbay"
 CONFIG_TARGET_CROWNBAY=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_PCH_GBE=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/dfi-bt700-q7x-151_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_VENDOR_DFI=y
 CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151"
 CONFIG_TARGET_DFI_BT700=y
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_NUVOTON_NCT6102D=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_114=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/firefly-rk3288_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_FIREFLY_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
 CONFIG_SILENT_CONSOLE=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_OF_PLATDATA=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_RK3288_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_ACT8846=y
 CONFIG_REGULATOR_ACT8846=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_SYSRESET=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
 # CONFIG_SPL_OF_LIBFDT is not set

configs/harmony_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_TEGRA=y
 CONFIG_TEGRA20=y
 CONFIG_TARGET_HARMONY=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 # CONFIG_BLK is not set
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10

configs/minnowmax_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
 CONFIG_TARGET_MINNOWMAX=y
 CONFIG_INTERNAL_UART=y
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_RTL8169=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/paz00_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_TEGRA=y
 CONFIG_TEGRA20=y
 CONFIG_TARGET_PAZ00=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 # CONFIG_BLK is not set
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10

configs/qemu-x86_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_MAX_CPUS=2
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
 CONFIG_SMP=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_111=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/qemu-x86_efi_payload32_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_MAX_CPUS=2
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
 CONFIG_SMP=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_111=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_EFI=y
 CONFIG_EFI_STUB=y

configs/qemu-x86_efi_payload64_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_MAX_CPUS=2
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
 CONFIG_SMP=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_111=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_EFI=y
 CONFIG_EFI_STUB=y
 CONFIG_EFI_STUB_64BIT=y

configs/rock2_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 # CONFIG_SPL_MMC_SUPPORT is not set
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
 CONFIG_TARGET_ROCK2=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
 CONFIG_SILENT_CONSOLE=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_RK3288_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_ACT8846=y
 CONFIG_REGULATOR_ACT8846=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y

configs/rpi_2_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI_2=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_LCD=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y

configs/rpi_3_32b_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI_3_32B=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_LCD=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y

configs/rpi_3_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI_3=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_LCD=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y

configs/rpi_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_LCD=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y

configs/seaboard_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_TEGRA=y
 CONFIG_TEGRA20=y
 CONFIG_TARGET_SEABOARD=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 # CONFIG_BLK is not set
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10

configs/som-db5800-som-6867_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_VENDOR_ADVANTECH=y
 CONFIG_TARGET_SOM_DB5800_SOM_6867=y
 CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867"
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/theadorable-x86-dfi-bt700_defconfig

Diff comments View file @ b87ca80

 CONFIG_X86=y
 CONFIG_VENDOR_DFI=y
 CONFIG_DEFAULT_DEVICE_TREE="theadorable-x86-dfi-bt700"
 CONFIG_TARGET_DFI_BT700=y
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_NUVOTON_NCT6102D=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
 CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_114=y
 CONFIG_CFB_CONSOLE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/ventana_defconfig

Diff comments View file @ b87ca80

 CONFIG_ARM=y
 CONFIG_TEGRA=y
 CONFIG_TEGRA20=y
 CONFIG_TARGET_VENTANA=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 # CONFIG_BLK is not set
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10

drivers/video/Kconfig

Diff comments View file @ b87ca80

 #
 # Video configuration
 #
 menu "Graphics support"
 config DM_VIDEO
 	bool "Enable driver model support for LCD/video"
 	depends on DM
 	help
 	  This enables driver model for LCD and video devices. These support
 	  a bitmap display of various sizes and depths which can be drawn on
 	  to display a command-line console or splash screen. Enabling this
 	  option compiles in the video uclass and routes all LCD/video access
 	  through this.
 config VIDEO_BPP8
 	bool "Support 8-bit-per-pixel displays"
 	depends on DM_VIDEO
 	default y if DM_VIDEO
 	help
 	  Support drawing text and bitmaps onto a 8-bit-per-pixel display.
 	  Enabling this will include code to support this display. Without
 	  this option, such displays will not be supported and console output
 	  will be empty.
 config VIDEO_BPP16
 	bool "Support 16-bit-per-pixel displays"
 	depends on DM_VIDEO
 	default y if DM_VIDEO
 	help
 	  Support drawing text and bitmaps onto a 16-bit-per-pixel display.
 	  Enabling this will include code to support this display. Without
 	  this option, such displays will not be supported and console output
 	  will be empty.
 config VIDEO_BPP32
 	bool "Support 32-bit-per-pixel displays"
 	depends on DM_VIDEO
 	default y if DM_VIDEO
 	help
 	  Support drawing text and bitmaps onto a 32-bit-per-pixel display.
 	  Enabling this will include code to support this display. Without
 	  this option, such displays will not be supported and console output
 	  will be empty.
 config CONSOLE_NORMAL
 	bool "Support a simple text console"
 	depends on DM_VIDEO
 	default y if DM_VIDEO
 	help
 	  Support drawing text on the frame buffer console so that it can be
 	  used as a console. Rotation is not supported by this driver (see
 	  CONFIG_CONSOLE_ROTATION for that). A built-in 8x16 font is used
 	  for the display.
 config CONSOLE_ROTATION
 	bool "Support rotated displays"
 	depends on DM_VIDEO
 	help
 	  Sometimes, for example if the display is mounted in portrait
 	  mode or even if it's mounted landscape but rotated by 180degree,
 	  we need to rotate our content of the display relative to the
 	  framebuffer, so that user can read the messages which are
 	  printed out. Enable this option to include a text driver which can
 	  support this. The rotation is set by the 'rot' parameter in
 	  struct video_priv: 0=unrotated, 1=90 degrees clockwise, 2=180
 	  degrees, 3=270 degrees.
 config CONSOLE_TRUETYPE
 	bool "Support a console that uses TrueType fonts"
 	depends on DM_VIDEO
 	help
 	  TrueTrype fonts can provide outline-drawing capability rather than
 	  needing to provide a bitmap for each font and size that is needed.
 	  With this option you can adjust the text size and use a variety of
 	  fonts. Note that this is noticeably slower than with normal console.
 config CONSOLE_TRUETYPE_SIZE
 	int "TrueType font size"
 	depends on CONSOLE_TRUETYPE
 	default 18
 	help
 	  This sets the font size for the console. The size is measured in
 	  pixels and is the nominal height of a character. Note that fonts
 	  are commonly measured in 'points', being 1/72 inch (about 3.52mm).
 	  However that measurement depends on the size of your display and
 	  there is no standard display density. At present there is not a
 	  method to select the display's physical size, which would allow
 	  U-Boot to calculate the correct font size.
 source "drivers/video/fonts/Kconfig"
 config VIDCONSOLE_AS_LCD
 	bool "Use 'vidconsole' when 'lcd' is seen in stdout"
 	depends on DM_VIDEO
 	help
 	  This is a work-around for boards which have 'lcd' in their stdout
 	  environment variable, but have moved to use driver model for video.
 	  In this case the console will no-longer work. While it is possible
 	  to update the environment, the breakage may be confusing for users.
 	  This option will be removed around the end of 2016.
 config VIDEO_COREBOOT
 	bool "Enable coreboot framebuffer driver support"
 	depends on X86 && SYS_COREBOOT
 	help
 	  Turn on this option to enable a framebuffer driver when U-Boot is
 	  loaded by coreboot where the graphics device is configured by
 	  coreboot already. This can in principle be used with any platform
 	  that coreboot supports.
 config VIDEO_VESA
 	bool "Enable VESA video driver support"
 	default n
 	help
 	  Turn on this option to enable a very simple driver which uses vesa
 	  to discover the video mode and then provides a frame buffer for use
 	  by U-Boot. This can in principle be used with any platform that
 	  supports PCI and video cards that support VESA BIOS Extension (VBE).
 config FRAMEBUFFER_SET_VESA_MODE
 	bool "Set framebuffer graphics resolution"
 	depends on VIDEO_VESA || VIDEO_BROADWELL_IGD
 	help
 	  Set VESA/native framebuffer mode (needed for bootsplash and graphical
 	  framebuffer console)
 choice
 	prompt "framebuffer graphics resolution"
 	default FRAMEBUFFER_VESA_MODE_117
 	depends on FRAMEBUFFER_SET_VESA_MODE
 	help
 	  This option sets the resolution used for the U-Boot framebuffer (and
 	  bootsplash screen).
 config FRAMEBUFFER_VESA_MODE_100
 	bool "640x400 256-color"
 config FRAMEBUFFER_VESA_MODE_101
 	bool "640x480 256-color"
 config FRAMEBUFFER_VESA_MODE_102
 	bool "800x600 16-color"
 config FRAMEBUFFER_VESA_MODE_103
 	bool "800x600 256-color"
 config FRAMEBUFFER_VESA_MODE_104
 	bool "1024x768 16-color"
 config FRAMEBUFFER_VESA_MODE_105
 	bool "1024x768 256-color"
 config FRAMEBUFFER_VESA_MODE_106
 	bool "1280x1024 16-color"
 config FRAMEBUFFER_VESA_MODE_107
 	bool "1280x1024 256-color"
 config FRAMEBUFFER_VESA_MODE_108
 	bool "80x60 text"
 config FRAMEBUFFER_VESA_MODE_109
 	bool "132x25 text"
 config FRAMEBUFFER_VESA_MODE_10A
 	bool "132x43 text"
 config FRAMEBUFFER_VESA_MODE_10B
 	bool "132x50 text"
 config FRAMEBUFFER_VESA_MODE_10C
 	bool "132x60 text"
 config FRAMEBUFFER_VESA_MODE_10D
 	bool "320x200 32k-color (1:5:5:5)"
 config FRAMEBUFFER_VESA_MODE_10E
 	bool "320x200 64k-color (5:6:5)"
 config FRAMEBUFFER_VESA_MODE_10F
 	bool "320x200 16.8M-color (8:8:8)"
 config FRAMEBUFFER_VESA_MODE_110
 	bool "640x480 32k-color (1:5:5:5)"
 config FRAMEBUFFER_VESA_MODE_111
 	bool "640x480 64k-color (5:6:5)"
 config FRAMEBUFFER_VESA_MODE_112
 	bool "640x480 16.8M-color (8:8:8)"
 config FRAMEBUFFER_VESA_MODE_113
 	bool "800x600 32k-color (1:5:5:5)"
 config FRAMEBUFFER_VESA_MODE_114
 	bool "800x600 64k-color (5:6:5)"
 config FRAMEBUFFER_VESA_MODE_115
 	bool "800x600 16.8M-color (8:8:8)"
 config FRAMEBUFFER_VESA_MODE_116
 	bool "1024x768 32k-color (1:5:5:5)"
 config FRAMEBUFFER_VESA_MODE_117
 	bool "1024x768 64k-color (5:6:5)"
 config FRAMEBUFFER_VESA_MODE_118
 	bool "1024x768 16.8M-color (8:8:8)"
 config FRAMEBUFFER_VESA_MODE_119
 	bool "1280x1024 32k-color (1:5:5:5)"
 config FRAMEBUFFER_VESA_MODE_11A
 	bool "1280x1024 64k-color (5:6:5)"
 config FRAMEBUFFER_VESA_MODE_11B
 	bool "1280x1024 16.8M-color (8:8:8)"
 config FRAMEBUFFER_VESA_MODE_USER
 	bool "Manually select VESA mode"
 endchoice
 # Map the config names to an integer (KB).
 config FRAMEBUFFER_VESA_MODE
 	prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
 	hex
 	default 0x100 if FRAMEBUFFER_VESA_MODE_100
 	default 0x101 if FRAMEBUFFER_VESA_MODE_101
 	default 0x102 if FRAMEBUFFER_VESA_MODE_102
 	default 0x103 if FRAMEBUFFER_VESA_MODE_103
 	default 0x104 if FRAMEBUFFER_VESA_MODE_104
 	default 0x105 if FRAMEBUFFER_VESA_MODE_105
 	default 0x106 if FRAMEBUFFER_VESA_MODE_106
 	default 0x107 if FRAMEBUFFER_VESA_MODE_107
 	default 0x108 if FRAMEBUFFER_VESA_MODE_108
 	default 0x109 if FRAMEBUFFER_VESA_MODE_109
 	default 0x10A if FRAMEBUFFER_VESA_MODE_10A
 	default 0x10B if FRAMEBUFFER_VESA_MODE_10B
 	default 0x10C if FRAMEBUFFER_VESA_MODE_10C
 	default 0x10D if FRAMEBUFFER_VESA_MODE_10D
 	default 0x10E if FRAMEBUFFER_VESA_MODE_10E
 	default 0x10F if FRAMEBUFFER_VESA_MODE_10F
 	default 0x110 if FRAMEBUFFER_VESA_MODE_110
 	default 0x111 if FRAMEBUFFER_VESA_MODE_111
 	default 0x112 if FRAMEBUFFER_VESA_MODE_112
 	default 0x113 if FRAMEBUFFER_VESA_MODE_113
 	default 0x114 if FRAMEBUFFER_VESA_MODE_114
 	default 0x115 if FRAMEBUFFER_VESA_MODE_115
 	default 0x116 if FRAMEBUFFER_VESA_MODE_116
 	default 0x117 if FRAMEBUFFER_VESA_MODE_117
 	default 0x118 if FRAMEBUFFER_VESA_MODE_118
 	default 0x119 if FRAMEBUFFER_VESA_MODE_119
 	default 0x11A if FRAMEBUFFER_VESA_MODE_11A
 	default 0x11B if FRAMEBUFFER_VESA_MODE_11B
 	default 0x117 if FRAMEBUFFER_VESA_MODE_USER
 config VIDEO_LCD_ANX9804
 	bool "ANX9804 bridge chip"
 	default n
 	---help---
 	Support for the ANX9804 bridge chip, which can take pixel data coming
 	from a parallel LCD interface and translate it on the fy into a DP
 	interface for driving eDP TFT displays. It uses I2C for configuration.
 config VIDEO_LCD_SSD2828
 	bool "SSD2828 bridge chip"
 	default n
 	---help---
 	Support for the SSD2828 bridge chip, which can take pixel data coming
 	from a parallel LCD interface and translate it on the fly into MIPI DSI
 	interface for driving a MIPI compatible LCD panel. It uses SPI for
 	configuration.
 config VIDEO_LCD_SSD2828_TX_CLK
 	int "SSD2828 TX_CLK frequency (in MHz)"
 	depends on VIDEO_LCD_SSD2828
 	default 0
 	---help---
 	The frequency of the crystal, which is clocking SSD2828. It may be
 	anything in the 8MHz-30MHz range and the exact value should be
 	retrieved from the board schematics. Or in the case of Allwinner
 	hardware, it can be usually found as 'lcd_xtal_freq' variable in
 	FEX files. It can be also set to 0 for selecting PCLK from the
 	parallel LCD interface instead of TX_CLK as the PLL clock source.
 config VIDEO_LCD_SSD2828_RESET
 	string "RESET pin of SSD2828"
 	depends on VIDEO_LCD_SSD2828
 	default ""
 	---help---
 	The reset pin of SSD2828 chip. This takes a string in the format
 	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
 config VIDEO_LCD_HITACHI_TX18D42VM
 	bool "Hitachi tx18d42vm LVDS LCD panel support"
 	depends on VIDEO
 	default n
 	---help---
 	Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
 	lcd controller which needs to be initialized over SPI, once that is
 	done they work like a regular LVDS panel.
 config VIDEO_LCD_SPI_CS
 	string "SPI CS pin for LCD related config job"
 	depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
 	default ""
 	---help---
 	This is one of the SPI communication pins, involved in setting up a
 	working LCD configuration. The exact role of SPI may differ for
 	different hardware setups. The option takes a string in the format
 	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
 config VIDEO_LCD_SPI_SCLK
 	string "SPI SCLK pin for LCD related config job"
 	depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
 	default ""
 	---help---
 	This is one of the SPI communication pins, involved in setting up a
 	working LCD configuration. The exact role of SPI may differ for
 	different hardware setups. The option takes a string in the format
 	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
 config VIDEO_LCD_SPI_MOSI
 	string "SPI MOSI pin for LCD related config job"
 	depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
 	default ""
 	---help---
 	This is one of the SPI communication pins, involved in setting up a
 	working LCD configuration. The exact role of SPI may differ for
 	different hardware setups. The option takes a string in the format
 	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
 config VIDEO_LCD_SPI_MISO
 	string "SPI MISO pin for LCD related config job (optional)"
 	depends on VIDEO_LCD_SSD2828
 	default ""
 	---help---
 	This is one of the SPI communication pins, involved in setting up a
 	working LCD configuration. The exact role of SPI may differ for
 	different hardware setups. If wired up, this pin may provide additional
 	useful functionality. Such as bi-directional communication with the
 	hardware and LCD panel id retrieval (if the panel can report it). The
 	option takes a string in the format understood by 'name_to_gpio'
 	function, e.g. PH1 for pin 1 of port H.
 config VIDEO_MVEBU
 	bool "Armada XP LCD controller"
 	default n
 	---help---
 	Support for the LCD controller integrated in the Marvell
 	Armada XP SoC.
 config I2C_EDID
 	bool "Enable EDID library"
 	depends on DM_I2C
 	default n
 	help
 	   This enables library for accessing EDID data from an LCD panel.
 config DISPLAY
 	bool "Enable Display support"
 	depends on DM
 	default n
 	select I2C_EDID
 	help
 	   This supports drivers that provide a display, such as eDP (Embedded
 	   DisplayPort) and HDMI (High Definition Multimedia Interface).
 	   The devices provide a simple interface to start up the display,
 	   read display information and enable it.
 config VIDEO_BROADWELL_IGD
 	bool "Enable Intel Broadwell integrated graphics device"
 	depends on X86
 	help
 	  This enables support for integrated graphics on Intel broadwell
 	  devices. Initialisation is mostly performed by a VGA boot ROM, with
 	  some setup handled by U-Boot itself. The graphics adaptor works as
 	  a VESA device and supports LCD panels, eDP and LVDS outputs.
 	  Configuration of most aspects of device operation is performed using
 	  a special tool which configures the VGA ROM, but the graphics
 	  resolution can be selected in U-Boot.
 config VIDEO_IVYBRIDGE_IGD
 	bool "Enable Intel Ivybridge integration graphics support"
 	depends on X86
 	help
 	  This enables support for integrated graphics on Intel ivybridge
 	  devices. Initialisation is mostly performed by a VGA boot ROM, with
 	  some setup handled by U-Boot itself. The graphics adaptor works as
 	  a VESA device and supports LCD panels, eDP and LVDS outputs.
 	  Configuration of most aspects of device operation is performed using
 	  a special tool which configures the VGA ROM, but the graphics
 	  resolution can be selected in U-Boot.
 config VIDEO_ROCKCHIP
 	bool "Enable Rockchip video support"
 	depends on DM_VIDEO
 	help
 	   Rockchip SoCs provide video output capabilities for High-Definition
 	   Multimedia Interface (HDMI), Low-voltage Differential Signalling
 	   (LVDS), embedded DisplayPort (eDP) and Display Serial Interface
 	   (DSI). This driver supports the on-chip video output device, and
 	   targets the Rockchip RK3288.
 config VIDEO_SANDBOX_SDL
 	bool "Enable sandbox video console using SDL"
 	depends on SANDBOX
 	help
 	  When using sandbox you can enable an emulated LCD display which
 	  appears as an SDL (Simple DirectMedia Layer) window. This is a
 	  console device and can display stdout output. Within U-Boot is is
 	  a normal bitmap display and can display images as well as text.
 config VIDEO_TEGRA20
 	bool "Enable LCD support on Tegra20"
 	depends on OF_CONTROL
 	help
 	   Tegra20 supports video output to an attached LCD panel as well as
 	   other options such as HDMI. Only the LCD is supported in U-Boot.
 	   This option enables this support which can be used on devices which
 	   have an LCD display connected.
 config VIDEO_TEGRA124
 	bool "Enable video support on Tegra124"
 	depends on DM_VIDEO
 	help
 	   Tegra124 supports many video output options including eDP and
 	   HDMI. At present only eDP is supported by U-Boot. This option
 	   enables this support which can be used on devices which
 	   have an eDP display connected.
 source "drivers/video/bridge/Kconfig"
 config VIDEO
 	bool "Enable legacy video support"
 	depends on !DM_VIDEO
 	help
 	  Define this for video support, without using driver model. Some
 	  drivers use this because they are not yet converted to driver
 	  model. Video drivers typically provide a colour text console and
 	  cursor.
 config CFB_CONSOLE
 	bool "Enable colour frame buffer console"
 	depends on VIDEO
 	default y if VIDEO
 	help
 	  Enables the colour frame buffer driver. This supports colour
 	  output on a bitmap display from an in-memory frame buffer.
 	  Several colour devices are supported along with various options to
 	  adjust the supported features. The driver is implemented in
 	  cfb_console.c
 	  The following defines are needed (cf. smiLynxEM, i8042)
 		VIDEO_FB_LITTLE_ENDIAN	graphic memory organisation
 					(default big endian)
 		VIDEO_HW_RECTFILL	graphic chip supports
 					rectangle fill (cf. smiLynxEM)
 		VIDEO_HW_BITBLT		graphic chip supports
 					bit-blit (cf. smiLynxEM)
 		VIDEO_VISIBLE_COLS	visible pixel columns (cols=pitch)
 		VIDEO_VISIBLE_ROWS	visible pixel rows
 		VIDEO_PIXEL_SIZE	bytes per pixel
 		VIDEO_DATA_FORMAT	graphic data format
 					(0-5, cf. cfb_console.c)
 		VIDEO_FB_ADRS		framebuffer address
 		VIDEO_KBD_INIT_FCT	keyboard int fct (i.e. rx51_kp_init())
 		VIDEO_TSTC_FCT		test char fct (i.e. rx51_kp_tstc)
 		VIDEO_GETC_FCT		get char fct (i.e. rx51_kp_getc)
 		CONFIG_VIDEO_LOGO	display Linux logo in upper left corner
 		CONFIG_VIDEO_BMP_LOGO	use bmp_logo.h instead of linux_logo.h
 					for logo. Requires CONFIG_VIDEO_LOGO
 		CONFIG_CONSOLE_EXTRA_INFO
 					additional board info beside
 					the logo
 		CONFIG_HIDE_LOGO_VERSION
 					do not display bootloader
 					version string
 	  When CONFIG_CFB_CONSOLE is defined, the video console is the
 	  default console. The serial console can be forced by setting the
 	  environment 'console=serial'.
 config CFB_CONSOLE_ANSI
 	bool "Support ANSI escape sequences"
 	depends on CFB_CONSOLE
 	help
 	  This allows the colour buffer frame buffer driver to support
 	  a limited number of ANSI escape sequences (cursor control,
 	  erase functions and limited graphics rendition control). Normal
 	  output from U-Boot will pass through this filter.
 config VGA_AS_SINGLE_DEVICE
 	bool "Set the video as an output-only device"
 	depends on CFB_CONSOLE
 	default y
 	help
 	  If enable the framebuffer device will be initialized as an
 	  output-only device. The Keyboard driver will not be set up. This
 	  may be used if you have no keyboard device, or more than one
 	  (USB Keyboard, AT Keyboard).
 config VIDEO_SW_CURSOR
 	bool "Enable a software cursor"
 	depends on CFB_CONSOLE
 	default y if CFB_CONSOLE
 	help
 	  This draws a cursor after the last character. No blinking is
 	  provided. This makes it possible to see the current cursor
 	  position when entering text on the console. It is recommended to
 	  enable this.
 config CONSOLE_EXTRA_INFO
 	bool "Display additional board information"
 	depends on CFB_CONSOLE
 	help
 	  Display additional board information strings that normally go to
 	  the serial port. When this option is enabled, a board-specific
 	  function video_get_info_str() is called to get the string for
 	  each line of the display. The function should return the string,
 	  which can be empty if there is nothing to display for that line.
+config CONSOLE_SCROLL_LINES
+	int "Number of lines to scroll the console by"
+	depends on CFB_CONSOLE || DM_VIDEO || LCD
+	default 1
+	help
+	  When the console need to be scrolled, this is the number of
+	  lines to scroll by. It defaults to 1. Increasing this makes the
+	  console jump but can help speed up operation when scrolling
+	  is slow.
 config VIDEO_CT69000
 	bool "Enable Chips & Technologies 69000 video driver"
 	depends on VIDEO
 	help
 	  This enables a frame buffer driver for the Chips & Technologies
 	  ct69000, a fairly old graphics device (circa 2000) which is used
 	  on some hardware. It operates over the ISA bus, and supports
 	  some acceleration features.
 	  For the CT69000 and SMI_LYNXEM drivers, videomode is
 		selected via environment 'videomode'. Two different ways
 		are possible:
 		- "videomode=num"   'num' is a standard LiLo mode numbers.
 		Following standard modes are supported	(* is default):
 		      Colors	640x480 800x600 1024x768 1152x864 1280x1024
 		-------------+---------------------------------------------
 		      8 bits |	0x301*	0x303	 0x305	  0x161	    0x307
 		     15 bits |	0x310	0x313	 0x316	  0x162	    0x319
 		     16 bits |	0x311	0x314	 0x317	  0x163	    0x31A
 		     24 bits |	0x312	0x315	 0x318	    ?	    0x31B
 		-------------+---------------------------------------------
 		(i.e. setenv videomode 317; saveenv; reset;)
 		- "videomode=bootargs" all the video parameters are parsed
 		from the bootargs. (See drivers/video/videomodes.c)
 config SYS_CONSOLE_BG_COL
 	hex "Background colour"
 	depends on CFB_CONSOLE || VIDEO_CT69000
 	default 0x00
 	help
 	  Defines the background colour for the console. The value is from
 	  0x00 to 0xff and the meaning depends on the graphics card.
 	  Typically, 0x00 means black and 0xff means white. Do not set
 	  the background and foreground to the same colour or you will see
 	  nothing.
 config SYS_CONSOLE_FG_COL
 	hex "Foreground colour"
 	depends on CFB_CONSOLE || VIDEO_CT69000
 	default 0xa0
 	help
 	  Defines the foreground colour for the console. The value is from
 	  0x00 to 0xff and the meaning depends on the graphics card.
 	  Typically, 0x00 means black and 0xff means white. Do not set
 	  the background and foreground to the same colour or you will see
 	  nothing.
 config LCD
 	bool "Enable legacy LCD support"
 	help
 	  Define this to enable LCD support (for output to LCD display).
 	  You will also need to select an LCD driver using an additional
 	  CONFIG option. See the README for details. Drives which have been
 	  converted to driver model will instead used CONFIG_DM_VIDEO.
 endmenu

include/configs/chromebook_jerry.h

Diff comments View file @ b87ca80

 /*
  * (C) Copyright 2015 Google, Inc
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define ROCKCHIP_DEVICE_SETTINGS \
 		"stdin=serial,cros-ec-keyb\0" \
 		"stdout=serial,vidconsole\0" \
 		"stderr=serial,vidconsole\0"
 #include <configs/rk3288_common.h>
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPI_FLASH_GIGADEVICE
 #define CONFIG_CMD_SF_TEST
 #define CONFIG_KEYBOARD
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES		10
 #endif

include/configs/colibri_pxa270.h

Diff comments View file @ b87ca80

 /*
  * Toradex Colibri PXA270 configuration file
  *
  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	__CONFIG_H
 #define	__CONFIG_H
 /*
  * High Level Board Configuration Options
  */
 #define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_SYS_TEXT_BASE		0x0
 /* Avoid overwriting factory configuration block */
 #define CONFIG_BOARD_SIZE_LIMIT		0x40000
 /* We will never enable dcache because we have to setup MMU first */
 #define CONFIG_SYS_DCACHE_OFF
 /*
  * Environment settings
  */
 #define	CONFIG_ENV_OVERWRITE
 #define	CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 #define	CONFIG_ARCH_CPU_INIT
 #define	CONFIG_BOOTCOMMAND						\
 	"if fatload mmc 0 0xa0000000 uImage; then "			\
 		"bootm 0xa0000000; "					\
 	"fi; "								\
 	"if usb reset && fatload usb 0 0xa0000000 uImage; then "	\
 		"bootm 0xa0000000; "					\
 	"fi; "								\
 	"bootm 0xc0000;"
 #define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,115200"
 #define	CONFIG_TIMESTAMP
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_LZMA			/* LZMA compression support */
 /*
  * Serial Console Configuration
  */
 #define	CONFIG_PXA_SERIAL
 #define	CONFIG_FFUART			1
 #define CONFIG_CONS_INDEX		3
 #define	CONFIG_BAUDRATE			115200
 /*
  * Bootloader Components Configuration
  */
 #define	CONFIG_CMD_ENV
 /* I2C support */
 #ifdef CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_PXA
 #define CONFIG_PXA_STD_I2C
 #define CONFIG_PXA_PWR_I2C
 #define CONFIG_SYS_I2C_SPEED		100000
 #endif
 /* LCD support */
 #ifdef CONFIG_LCD
 #define CONFIG_PXA_LCD
 #define CONFIG_PXA_VGA
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES	10
 #define CONFIG_CMD_BMP
 #define CONFIG_LCD_LOGO
 #endif
 /*
  * Networking Configuration
  */
 #ifdef	CONFIG_CMD_NET
 #define	CONFIG_DRIVER_DM9000		1
 #define CONFIG_DM9000_BASE		0x08000000
 #define DM9000_IO			(CONFIG_DM9000_BASE)
 #define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
 #define	CONFIG_NET_RETRY_COUNT		10
 #define	CONFIG_BOOTP_BOOTFILESIZE
 #define	CONFIG_BOOTP_BOOTPATH
 #define	CONFIG_BOOTP_GATEWAY
 #define	CONFIG_BOOTP_HOSTNAME
 #endif
 #undef	CONFIG_SYS_LONGHELP		/* Saves 10 KB */
 #define	CONFIG_SYS_CBSIZE		256
 #define	CONFIG_SYS_PBSIZE		\
 	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define	CONFIG_SYS_MAXARGS		16
 #define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define	CONFIG_SYS_DEVICE_NULLDEV	1
 #define	CONFIG_CMDLINE_EDITING		1
 #define	CONFIG_AUTO_COMPLETE		1
 /*
  * Clock Configuration
  */
 #define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */
 /*
  * DRAM Map
  */
 #define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
 #define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
 #define	PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
 #define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
 #define	CONFIG_SYS_DRAM_SIZE		0x04000000	/* 64 MB DRAM */
 #define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
 #define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000
 /*
  * NOR FLASH
  */
 #ifdef	CONFIG_CMD_FLASH
 #define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
 #define	PHYS_FLASH_SIZE			0x02000000	/* 32 MB */
 #define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 #define	CONFIG_SYS_FLASH_CFI
 #define	CONFIG_FLASH_CFI_DRIVER		1
 #define	CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
 #define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
 #define	CONFIG_SYS_MAX_FLASH_BANKS	1
 #define	CONFIG_SYS_FLASH_ERASE_TOUT	(25 * CONFIG_SYS_HZ)
 #define	CONFIG_SYS_FLASH_WRITE_TOUT	(25 * CONFIG_SYS_HZ)
 #define	CONFIG_SYS_FLASH_LOCK_TOUT	(25 * CONFIG_SYS_HZ)
 #define	CONFIG_SYS_FLASH_UNLOCK_TOUT	(25 * CONFIG_SYS_HZ)
 #define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 #define	CONFIG_SYS_FLASH_PROTECTION		1
 #define CONFIG_ENV_IS_IN_FLASH		1
 #else	/* No flash */
 #define	CONFIG_SYS_NO_FLASH
 #define	CONFIG_ENV_IS_NOWHERE
 #endif
 #define	CONFIG_SYS_MONITOR_BASE		0x0
 #define	CONFIG_SYS_MONITOR_LEN		0x40000
 /* Skip factory configuration block */
 #define	CONFIG_ENV_ADDR			\
 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
 #define	CONFIG_ENV_SIZE			0x40000
 #define	CONFIG_ENV_SECT_SIZE		0x40000
 /*
  * GPIO settings
  */
 #define	CONFIG_SYS_GPSR0_VAL	0x00000000
 #define	CONFIG_SYS_GPSR1_VAL	0x00020000
 #define	CONFIG_SYS_GPSR2_VAL	0x0002c000
 #define	CONFIG_SYS_GPSR3_VAL	0x00000000
 #define	CONFIG_SYS_GPCR0_VAL	0x00000000
 #define	CONFIG_SYS_GPCR1_VAL	0x00000000
 #define	CONFIG_SYS_GPCR2_VAL	0x00000000
 #define	CONFIG_SYS_GPCR3_VAL	0x00000000
 #define	CONFIG_SYS_GPDR0_VAL	0xc8008000
 #define	CONFIG_SYS_GPDR1_VAL	0xfc02a981
 #define	CONFIG_SYS_GPDR2_VAL	0x92c3ffff
 #define	CONFIG_SYS_GPDR3_VAL	0x0061e804
 #define	CONFIG_SYS_GAFR0_L_VAL	0x80100000
 #define	CONFIG_SYS_GAFR0_U_VAL	0xa5c00010
 #define	CONFIG_SYS_GAFR1_L_VAL	0x6992901a
 #define	CONFIG_SYS_GAFR1_U_VAL	0xaaa50008
 #define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
 #define	CONFIG_SYS_GAFR2_U_VAL	0x4109a002
 #define	CONFIG_SYS_GAFR3_L_VAL	0x54000310
 #define	CONFIG_SYS_GAFR3_U_VAL	0x00005401
 #define	CONFIG_SYS_PSSR_VAL	0x30
 /*
  * Clock settings
  */
 #define	CONFIG_SYS_CKEN		0x00500240
 #define	CONFIG_SYS_CCCR		0x02000290
 /*
  * Memory settings
  */
 #define	CONFIG_SYS_MSC0_VAL	0x9ee1c5f2
 #define	CONFIG_SYS_MSC1_VAL	0x9ee1f994
 #define	CONFIG_SYS_MSC2_VAL	0x9ee19ee1
 #define	CONFIG_SYS_MDCNFG_VAL	0x090009c9
 #define	CONFIG_SYS_MDREFR_VAL	0x2003a031
 #define	CONFIG_SYS_MDMRS_VAL	0x00220022
 #define	CONFIG_SYS_FLYCNFG_VAL	0x00010001
 #define	CONFIG_SYS_SXCNFG_VAL	0x40044004
 /*
  * PCMCIA and CF Interfaces
  */
 #define	CONFIG_SYS_MECR_VAL	0x00000000
 #define	CONFIG_SYS_MCMEM0_VAL	0x00028307
 #define	CONFIG_SYS_MCMEM1_VAL	0x00014307
 #define	CONFIG_SYS_MCATT0_VAL	0x00038787
 #define	CONFIG_SYS_MCATT1_VAL	0x0001c787
 #define	CONFIG_SYS_MCIO0_VAL	0x0002830f
 #define	CONFIG_SYS_MCIO1_VAL	0x0001430f
 #include "pxa-common.h"
 #endif /* __CONFIG_H */

include/configs/colibri_t20.h

Diff comments View file @ b87ca80

 /*
  * Copyright (C) 2012 Lucas Stach
  *
  * Configuration settings for the Toradex Colibri T20 modules.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include "tegra20-common.h"
 #define CONFIG_ARCH_MISC_INIT
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING	"Toradex Colibri T20"
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
 #define CONFIG_TEGRA_UARTA_SDIO1
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 #define CONFIG_MACH_TYPE		MACH_TYPE_COLIBRI_T20
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
 /* SD/MMC support */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 /* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	3
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 /* General networking support */
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE		1536
 #define CONFIG_TFTP_TSIZE
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES	10
 #define CONFIG_CMD_BMP
 #define CONFIG_LCD_LOGO
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 /* Dynamic MTD partition support */
 #define CONFIG_CMD_MTDPARTS	/* Enable 'mtdparts' command line support */
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
 #define MTDIDS_DEFAULT		"nand0=tegra_nand"
 #define MTDPARTS_DEFAULT	"mtdparts=tegra_nand:"		\
 				"2m(u-boot)ro,"			\
 				"1m(u-boot-env),"		\
 				"1m(cfgblock)ro,"		\
 				"-(ubi)"
 /* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET		(SZ_2M)
 #undef CONFIG_ENV_SIZE		/* undef size from tegra20-common.h */
 #define CONFIG_ENV_SIZE			(SZ_64K)
 /* UBI */
 #define CONFIG_CMD_UBIFS	/* increases size by almost 60 KB */
 #define CONFIG_LZO
 #define CONFIG_RBTREE
 /* Debug commands */
 /* Miscellaneous commands */
 #define CONFIG_FAT_WRITE
 #define BOARD_EXTRA_ENV_SETTINGS \
 	"mtdparts=" MTDPARTS_DEFAULT "\0"
 /* Increase console I/O buffer size */
 #undef CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_CBSIZE		1024
 /* Increase arguments buffer size */
 #undef CONFIG_SYS_BARGSIZE
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 /* Increase print buffer size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 /* Increase maximum number of arguments */
 #undef CONFIG_SYS_MAXARGS
 #define CONFIG_SYS_MAXARGS		32
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 #endif /* __CONFIG_H */

include/configs/evb_rk3288.h

Diff comments View file @ b87ca80

 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define ROCKCHIP_DEVICE_SETTINGS
 #include <configs/rk3288_common.h>
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 1
 /* SPL @ 32k for ~36k
  * ENV @ 96k
  * u-boot @ 128K
  */
 #define CONFIG_ENV_OFFSET (96 * 1024)
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES		10
 #endif

include/configs/evb_rk3399.h

Diff comments View file @ b87ca80

 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __EVB_RK3399_H
 #define __EVB_RK3399_H
 #include <configs/rk3399_common.h>
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 /*
  * SPL @ 32k for ~36k
  * ENV @ 96k
  * u-boot @ 128K
  */
 #define CONFIG_ENV_OFFSET (96 * 1024)
 #define SDRAM_BANK_SIZE			(2UL << 30)
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES		10
 #endif

include/configs/fennec_rk3288.h

Diff comments View file @ b87ca80

 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define ROCKCHIP_DEVICE_SETTINGS
 #include <configs/rk3288_common.h>
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 1
 /* SPL @ 32k for ~36k
  * ENV @ 96k
  * u-boot @ 128K
  */
 #define CONFIG_ENV_OFFSET (96 * 1024)
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES		10
 #endif

include/configs/firefly-rk3288.h

Diff comments View file @ b87ca80

 /*
  * (C) Copyright 2015 Google, Inc
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define ROCKCHIP_DEVICE_SETTINGS \
 		"stdin=serial,cros-ec-keyb\0" \
 		"stdout=serial,vidconsole\0" \
 		"stderr=serial,vidconsole\0"
 #include <configs/rk3288_common.h>
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 /* SPL @ 32k for ~36k
  * ENV @ 96k
  * u-boot @ 128K
  */
 #define CONFIG_ENV_OFFSET (96 * 1024)
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES		10
 #endif

include/configs/harmony.h

Diff comments View file @ b87ca80

 /*
  *  (C) Copyright 2010-2012
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Harmony"
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD
 /* UARTD: keyboard satellite board UART, default */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 #ifdef CONFIG_TEGRA_ENABLE_UARTA
 /* UARTA: debug board UART */
 #define CONFIG_SYS_NS16550_COM2		NV_PA_APB_UARTA_BASE
 #endif
 #define CONFIG_MACH_TYPE		MACH_TYPE_HARMONY
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 /* Environment in NAND (which is 512M), aligned to start of last sector */
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET	(SZ_512M - SZ_128K) /* 128K sector size */
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_MCS7830
 #define CONFIG_USB_ETHER_SMSC95XX
 /* General networking support */
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES	10
 #include "tegra-common-post.h"
 #endif /* __CONFIG_H */

include/configs/miniarm_rk3288.h

Diff comments View file @ b87ca80

 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define ROCKCHIP_DEVICE_SETTINGS
 #include <configs/rk3288_common.h>
 #undef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 /* SPL @ 32k for ~36k
  * ENV @ 96k
  * u-boot @ 128K
  */
 #define CONFIG_ENV_OFFSET (96 * 1024)
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES		10
 #endif

include/configs/paz00.h

Diff comments View file @ b87ca80

 /*
  * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING	"Compal Paz00"
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 #define CONFIG_MACH_TYPE		MACH_TYPE_PAZ00
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
 #define CONFIG_SYS_MMC_ENV_DEV 0
 #define CONFIG_SYS_MMC_ENV_PART 2
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 /* General networking support */
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES	10
 #include "tegra-common-post.h"
 #endif /* __CONFIG_H */

include/configs/popmetal_rk3288.h

Diff comments View file @ b87ca80

 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define ROCKCHIP_DEVICE_SETTINGS
 #include <configs/rk3288_common.h>
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 1
 /* SPL @ 32k for ~36k
  * ENV @ 96k
  * u-boot @ 128K
  */
 #define CONFIG_ENV_OFFSET (96 * 1024)
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES		10
 #endif

include/configs/rock2.h

Diff comments View file @ b87ca80

 /*
  * (C) Copyright 2015 Google, Inc
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define ROCKCHIP_DEVICE_SETTINGS \
 		"stdin=serial,cros-ec-keyb\0" \
 		"stdout=serial,vidconsole\0" \
 		"stderr=serial,vidconsole\0"
 #include <configs/rk3288_common.h>
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
 /* SPL @ 32k for 34k
  * u-boot directly after @ 68k for 400k or so
  * ENV @ 992k
  */
 #define CONFIG_ENV_OFFSET ((1024-32) * 1024)
 #else
 /* SPL @ 32k for ~36k
  * ENV @ 96k
  * u-boot @ 128K
  */
 #define CONFIG_ENV_OFFSET (96 * 1024)
 #endif
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES		10
 #endif

include/configs/rpi.h

Diff comments View file @ b87ca80

 /*
  * (C) Copyright 2012-2016 Stephen Warren
  *
  * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <linux/sizes.h>
 #include <asm/arch/timer.h>
 #if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B)
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 /* Architecture, CPU, etc.*/
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 /* Use SoC timer for AArch32, but architected timer for AArch64 */
 #ifndef CONFIG_ARM64
 #define CONFIG_SYS_TIMER_RATE		1000000
 #define CONFIG_SYS_TIMER_COUNTER	\
 	(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
 #endif
 /*
  * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
  * so 2708 has historically been used rather than a dedicated 2835 ID.
  *
  * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
  * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
  * rather than obtaining a valid ID:-/
  *
  * For the bcm2837, hopefully a machine type is not needed, since everything
  * is DT.
  */
 #ifdef CONFIG_BCM2835
 #define CONFIG_MACH_TYPE		MACH_TYPE_BCM2708
 #endif
 /* Memory layout */
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #ifdef CONFIG_ARM64
 #define CONFIG_SYS_TEXT_BASE		0x00080000
 #else
 #define CONFIG_SYS_TEXT_BASE		0x00008000
 #endif
 #define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
 /*
  * The board really has 256M. However, the VC (VideoCore co-processor) shares
  * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
  * smaller amount of RAM is present in order to avoid stomping on the area
  * the VC uses.
  */
 #define CONFIG_SYS_SDRAM_SIZE		SZ_128M
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
 					 CONFIG_SYS_SDRAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_MALLOC_LEN		SZ_4M
 #define CONFIG_SYS_MEMTEST_START	0x00100000
 #define CONFIG_SYS_MEMTEST_END		0x00200000
 #define CONFIG_LOADADDR			0x00200000
 /* Flash */
 #define CONFIG_SYS_NO_FLASH
 /* Devices */
 /* GPIO */
 #define CONFIG_BCM2835_GPIO
 /* LCD */
 #define CONFIG_LCD_DT_SIMPLEFB
 #define LCD_BPP				LCD_COLOR16
 /*
  * Prevent allocation of RAM for FB; the real FB address is queried
  * dynamically from the VideoCore co-processor, and comes from RAM
  * not owned by the ARM CPU.
  */
 #define CONFIG_FB_ADDR			0
 #define CONFIG_VIDEO_BCM2835
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES	10
 /* SD/MMC configuration */
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC
 #define CONFIG_SDHCI
 #define CONFIG_MMC_SDHCI_IO_ACCESSORS
 #define CONFIG_BCM2835_SDHCI
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_DWC2
 #ifndef CONFIG_BCM2835
 #define CONFIG_USB_DWC2_REG_ADDR 0x3f980000
 #else
 #define CONFIG_USB_DWC2_REG_ADDR 0x20980000
 #endif
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_TFTP_TSIZE
 #define CONFIG_MISC_INIT_R
 #define CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL
 #define CONFIG_SYS_STDIO_DEREGISTER
 #endif
 /* Console UART */
 #ifdef CONFIG_BCM2837
 #define CONFIG_BCM283X_MU_SERIAL
 #else
 #define CONFIG_PL01X_SERIAL
 #endif
 #define CONFIG_CONS_INDEX		0
 #define CONFIG_BAUDRATE			115200
 /* Console configuration */
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
 					 sizeof(CONFIG_SYS_PROMPT) + 16)
 /* Environment */
 #define CONFIG_ENV_SIZE			SZ_16K
 #define CONFIG_ENV_IS_IN_FAT
 #define FAT_ENV_INTERFACE		"mmc"
 #define FAT_ENV_DEVICE_AND_PART		"0:1"
 #define FAT_ENV_FILE			"uboot.env"
 #define CONFIG_FAT_WRITE
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_SYS_LOAD_ADDR		0x1000000
 #define CONFIG_PREBOOT			"usb start"
 /* Shell */
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_COMMAND_HISTORY
 /* Commands */
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 /* ATAGs support for bootm/bootz */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_INITRD_TAG
 #include <config_distro_defaults.h>
 /* Environment */
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define ENV_DEVICE_SETTINGS \
 	"stdin=serial,usbkbd\0" \
 	"stdout=serial,lcd\0" \
 	"stderr=serial,lcd\0"
 /*
  * Memory layout for where various images get loaded by boot scripts:
  *
  * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
  *
  * fdt_addr_r simply shouldn't overlap anything else. However, the RPi's
  *   binary firmware loads a DT to address 0x100, so we choose this address to
  *   match it. This allows custom boot scripts to pass this DT on to Linux
  *   simply by not over-writing the data at this address. When using U-Boot,
  *   U-Boot (and scripts it executes) typicaly ignore the DT loaded by the FW
  *   and loads its own DT from disk (triggered by boot.scr or extlinux.conf).
  *
  * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  *   something else. Put it low in memory to avoid conflicts.
  *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  *   should not overlap that area, or the kernel will have to copy itself
  *   somewhere else before decompression. Similarly, the address of any other
  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
  *   this up to 16M allows for a sizable kernel to be decompressed below the
  *   compressed load address.
  *
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Choosing 32M allows for the compressed kernel to be up to 16M.
  *
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  *   for any boot script to be up to 1M, which is hopefully plenty.
  */
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"fdt_high=ffffffff\0" \
 	"initrd_high=ffffffff\0" \
 	"fdt_addr_r=0x00000100\0" \
 	"pxefile_addr_r=0x00100000\0" \
 	"kernel_addr_r=0x01000000\0" \
 	"scriptaddr=0x02000000\0" \
 	"ramdisk_addr_r=0x02100000\0" \
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	func(USB, usb, 0) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \
 	ENV_DEVICE_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	BOOTENV
 #endif

include/configs/seaboard.h

Diff comments View file @ b87ca80

 /*
  *  (C) Copyright 2010,2011
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <linux/sizes.h>
 /* LP0 suspend / resume */
 #define CONFIG_TEGRA_LP0
 #define CONFIG_AES
 #define CONFIG_TEGRA_PMU
 #define CONFIG_TPS6586X_POWER
 #define CONFIG_TEGRA_CLOCK_SCALING
 #include "tegra20-common.h"
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Seaboard"
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 #define CONFIG_MACH_TYPE		MACH_TYPE_SEABOARD
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
 #define CONFIG_SYS_MMC_ENV_DEV 0
 #define CONFIG_SYS_MMC_ENV_PART 2
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 /* General networking support */
 /* Enable keyboard */
 #define CONFIG_TEGRA_KEYBOARD
 #define CONFIG_KEYBOARD
 /* USB keyboard */
 #define CONFIG_USB_KEYBOARD
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES	10
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND
 /* Max number of NAND devices */
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #include "tegra-common-post.h"
 #endif /* __CONFIG_H */

include/configs/ventana.h

Diff comments View file @ b87ca80

 /*
  *  (C) Copyright 2010,2011
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Ventana"
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 #define CONFIG_MACH_TYPE		MACH_TYPE_VENTANA
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
 #define CONFIG_SYS_MMC_ENV_DEV 0
 #define CONFIG_SYS_MMC_ENV_PART 2
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 /* General networking support */
 /* USB keyboard */
 #define CONFIG_USB_KEYBOARD
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES	10
 #include "tegra-common-post.h"
 #endif /* __CONFIG_H */

include/configs/x86-common.h

Diff comments View file @ b87ca80

 /*
  * Copyright (c) 2011 The Chromium OS Authors.
  * (C) Copyright 2008
  * Graeme Russ, graeme.russ@gmail.com.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm/ibmpc.h>
 #ifndef __CONFIG_X86_COMMON_H
 #define __CONFIG_X86_COMMON_H
 /*
  * High Level Configuration Options
  * (easy to change)
  */
 #define CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_ZBOOT_32
 #define CONFIG_PHYSMEM
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_LAST_STAGE_INIT
 #define CONFIG_NR_DRAM_BANKS		8
 #define CONFIG_LMB
 #define CONFIG_LZO
 #undef CONFIG_ZLIB
 #undef CONFIG_GZIP
 #define CONFIG_SYS_BOOTM_LEN		(16 << 20)
 /* SATA AHCI storage */
 #define CONFIG_SCSI_AHCI
 #ifdef CONFIG_SCSI_AHCI
 #define CONFIG_LIBATA
 #define CONFIG_LBA48
 #define CONFIG_SYS_64BIT_LBA
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 					 CONFIG_SYS_SCSI_MAX_LUN)
 #endif
 /* Generic TPM interfaced through LPC bus */
 #define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
 /*-----------------------------------------------------------------------
  * Real Time Clock Configuration
  */
 #define CONFIG_RTC_MC146818
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
 #define CONFIG_SYS_ISA_IO      CONFIG_SYS_ISA_IO_BASE_ADDRESS
 /*-----------------------------------------------------------------------
  * Serial Configuration
  */
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{300, 600, 1200, 2400, 4800, \
 					 9600, 19200, 38400, 115200}
 #define CONFIG_SYS_NS16550_PORT_MAPPED
 #define CONFIG_SYS_STDIO_DEREGISTER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SUPPORT_VFAT
 /************************************************************
  * DISK Partition support
  ************************************************************/
 #define CONFIG_EFI_PARTITION
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 #define CONFIG_ISO_PARTITION		/* Experimental */
 #define CONFIG_CMD_PART
 #ifdef CONFIG_SYS_COREBOOT
 #define CONFIG_CMD_CBFS
 #endif
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 /* x86 GPIOs are accessed through a PCI device */
 #define CONFIG_INTEL_ICH6_GPIO
 /*-----------------------------------------------------------------------
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_FPGA_LOADMK
 #define CONFIG_CMD_IO
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_GETTIME
 #define CONFIG_SCSI
 #define CONFIG_CMD_ZBOOT
 #define CONFIG_BOOTARGS		\
 	"root=/dev/sdb3 init=/sbin/init rootwait ro"
 #define CONFIG_BOOTCOMMAND	\
 	"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE			115200
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_CBSIZE			512
 #define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
 						 sizeof(CONFIG_SYS_PROMPT) + \
 						 16)
 #define CONFIG_SYS_MAXARGS			16
 #define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_MEMTEST_START		0x00100000
 #define CONFIG_SYS_MEMTEST_END			0x01000000
 #define CONFIG_SYS_LOAD_ADDR			0x20000000
 /*-----------------------------------------------------------------------
- * Video Configuration
- */
-#define CONFIG_CONSOLE_SCROLL_LINES 5
-/*-----------------------------------------------------------------------
  * CPU Features
  */
 #define CONFIG_SYS_STACK_SIZE			(32 * 1024)
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MALLOC_LEN			0x200000
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 /*-----------------------------------------------------------------------
  * FLASH configuration
  */
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_CMD_SF_TEST
 #define CONFIG_SPI
 /*-----------------------------------------------------------------------
  * Environment configuration
  */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SIZE			0x01000
 /*-----------------------------------------------------------------------
  * PCI configuration
  */
 #define CONFIG_PCI
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 /*-----------------------------------------------------------------------
  * USB configuration
  */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_PCI
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS     12
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #define CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_TFTP_TSIZE
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /* Default environment */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_HOSTNAME		x86
 #define CONFIG_BOOTFILE		"bzImage"
 #define CONFIG_LOADADDR		0x1000000
 #define CONFIG_RAMDISK_ADDR	0x4000000
 #ifdef CONFIG_GENERATE_ACPI_TABLE
 #define CONFIG_OTHBOOTARGS	"othbootargs=\0"
 #else
 #define CONFIG_OTHBOOTARGS	"othbootargs=acpi=off\0"
 #endif
 #define CONFIG_EXTRA_ENV_SETTINGS			\
 	CONFIG_STD_DEVICES_SETTINGS			\
 	"pciconfighost=1\0"				\
 	"netdev=eth0\0"					\
 	"consoledev=ttyS0\0"				\
 	CONFIG_OTHBOOTARGS				\
 	"ramdiskaddr=0x4000000\0"			\
 	"ramdiskfile=initramfs.gz\0"
 #define CONFIG_RAMBOOTCOMMAND				\
 	"setenv bootargs root=/dev/ram rw "		\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftpboot $loadaddr $bootfile;"			\
 	"tftpboot $ramdiskaddr $ramdiskfile;"		\
 	"zboot $loadaddr 0 $ramdiskaddr $filesize"
 #define CONFIG_NFSBOOTCOMMAND				\
 	"setenv bootargs root=/dev/nfs rw "		\
 	"nfsroot=$serverip:$rootpath "			\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs;"	\
 	"tftpboot $loadaddr $bootfile;"			\
 	"zboot $loadaddr"
 #endif	/* __CONFIG_H */

include/lcd_console.h

Diff comments View file @ b87ca80

 /*
  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /* By default we scroll by a single line */
-#ifndef CONFIG_CONSOLE_SCROLL_LINES
-#define CONFIG_CONSOLE_SCROLL_LINES 1
-#endif
 struct console_t {
 	short curr_col, curr_row;
 	short cols, rows;
 	void *fbbase;
 	u32 lcdsizex, lcdsizey, lcdrot;
 	void (*fp_putc_xy)(struct console_t *pcons, ushort x, ushort y, char c);
 	void (*fp_console_moverow)(struct console_t *pcons,
 				   u32 rowdst, u32 rowsrc);
 	void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr);
 };
 /**
  * console_calc_rowcol() - calculate available rows / columns wihtin a given
  * screen-size based on used VIDEO_FONT.
  *
  * @pcons: Pointer to struct console_t
  * @sizex: size X of the screen in pixel
  * @sizey: size Y of the screen in pixel
  */
 void console_calc_rowcol(struct console_t *pcons, u32 sizex, u32 sizey);
 /**
  * lcd_init_console() - Initialize lcd console parameters
  *
  * Setup the address of console base, and the number of rows and columns the
  * console has.
  *
  * @address: Console base address
  * @vl_rows: Number of rows in the console
  * @vl_cols: Number of columns in the console
  * @vl_rot: Rotation of display in degree (0 - 90 - 180 - 270) counterlockwise
  */
 void lcd_init_console(void *address, int vl_cols, int vl_rows, int vl_rot);
 /**
  * lcd_set_col() - Set the number of the current lcd console column
  *
  * Set the number of the console column where the cursor is.
  *
  * @col: Column number
  */
 void lcd_set_col(short col);
 /**
  * lcd_set_row() - Set the number of the current lcd console row
  *
  * Set the number of the console row where the cursor is.
  *
  * @row: Row number
  */
 void lcd_set_row(short row);
 /**
  * lcd_position_cursor() - Position the cursor on the screen
  *
  * Position the cursor at the given coordinates on the screen.
  *
  * @col: Column number
  * @row: Row number
  */
 void lcd_position_cursor(unsigned col, unsigned row);
 /**
  * lcd_get_screen_rows() - Get the total number of screen rows
  *
  * @return: Number of screen rows
  */
 int lcd_get_screen_rows(void);
 /**
  * lcd_get_screen_columns() - Get the total number of screen columns
  *
  * @return: Number of screen columns
  */
 int lcd_get_screen_columns(void);
 /**
  * lcd_putc() - Print to screen a single character at the location of the cursor
  *
  * @c: The character to print
  */
 void lcd_putc(const char c);
 /**
  * lcd_puts() - Print to screen a string at the location of the cursor
  *
  * @s: The string to print
  */
 void lcd_puts(const char *s);
 /**
  * lcd_printf() - Print to screen a formatted string at location of the cursor
  *
  * @fmt: The formatted string to print
  * @...: The arguments for the formatted string
  */
 void lcd_printf(const char *fmt, ...);

scripts/config_whitelist.txt

Diff comments View file @ b87ca80

 CONFIG_16BIT
 CONFIG_33
 CONFIG_400MHZ_MODE
 CONFIG_405
 CONFIG_405EP
 CONFIG_405EX
 CONFIG_405EX_CHIP21_ECID3_REV_D
 CONFIG_405EX_CHIP21_PVR_REV_C
 CONFIG_405EX_CHIP21_PVR_REV_D
 CONFIG_405EZ
 CONFIG_405GP
 CONFIG_440
 CONFIG_440EP
 CONFIG_440EPX
 CONFIG_440GP
 CONFIG_440GR
 CONFIG_440GRX
 CONFIG_440GX
 CONFIG_440SP
 CONFIG_440SPE
 CONFIG_440SPE_REVA
 CONFIG_440_GX
 CONFIG_4430SDP
 CONFIG_460EX
 CONFIG_460GT
 CONFIG_460SX
 CONFIG_4xx_CONFIG_BLOCKSIZE
 CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR
 CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET
 CONFIG_4xx_DCACHE
 CONFIG_521X
 CONFIG_533MHZ_MODE
 CONFIG_5xx_CONS_SCI1
 CONFIG_5xx_CONS_SCI2
 CONFIG_5xx_GCLK_FREQ
 CONFIG_64BIT_PHYS_ADDR
 CONFIG_66
 CONFIG_8260_CLKIN
 CONFIG_8349_CLKIN
 CONFIG_83XX
 CONFIG_83XX_CLKIN
 CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
 CONFIG_83XX_PCICLK
 CONFIG_83XX_PCI_STREAMING
 CONFIG_88F5182
 CONFIG_8xx_CONS_NONE
 CONFIG_8xx_CONS_SCCx
 CONFIG_8xx_CONS_SMC1
 CONFIG_8xx_CONS_SMC2
 CONFIG_8xx_CONS_SMCx
 CONFIG_8xx_CPUCLK_DEFAULT
 CONFIG_8xx_GCLK_FREQ
 CONFIG_8xx_OSCLK
 CONFIG_A003399_NOR_WORKAROUND
 CONFIG_A008044_WORKAROUND
 CONFIG_A3M071
 CONFIG_A4M072
 CONFIG_A4M2K
 CONFIG_AC14XX
 CONFIG_ACADIA
 CONFIG_ACX517AKN
 CONFIG_ACX544AKN
 CONFIG_ADCIOP
 CONFIG_ADDMISC
 CONFIG_ADDRESS
 CONFIG_ADDR_AUTO_INCR_BIT
 CONFIG_ADDR_MAP
 CONFIG_ADDR_STREAMING
 CONFIG_ADI_GPIO1
 CONFIG_ADI_GPIO2
 CONFIG_ADNPESC1
 CONFIG_ADP_AG101P
 CONFIG_AEABI
 CONFIG_AEMIF_CNTRL_BASE
 CONFIG_AES
 CONFIG_ALTERA_SDRAM
 CONFIG_ALTERA_SPI_IDLE_VAL
 CONFIG_ALTIVEC
 CONFIG_ALT_LB_ADDR
 CONFIG_ALT_LH_ADDR
 CONFIG_ALU
 CONFIG_AM335X_LCD
 CONFIG_AM335X_USB0
 CONFIG_AM335X_USB0_MODE
 CONFIG_AM335X_USB1
 CONFIG_AM335X_USB1_MODE
 CONFIG_AM33XX
 CONFIG_AM437X_USB2PHY2_HOST
 CONFIG_AM57XX
 CONFIG_AMBAPP_IOAREA
 CONFIG_AMCC_DEF_ENV
 CONFIG_AMCC_DEF_ENV_NOR_UPD
 CONFIG_AMCC_DEF_ENV_POWERPC
 CONFIG_AMCC_DEF_ENV_PPC
 CONFIG_AMCC_DEF_ENV_PPC_OLD
 CONFIG_AMCC_DEF_ENV_ROOTPATH
 CONFIG_AMCORE
 CONFIG_AMIGA_PARTITION
 CONFIG_ANDES_PCU
 CONFIG_ANDES_PCU_BASE
 CONFIG_AP325RXA
 CONFIG_APBH_DMA
 CONFIG_APBH_DMA_BURST
 CONFIG_APBH_DMA_BURST8
 CONFIG_APER_0_BASE
 CONFIG_APER_1_BASE
 CONFIG_APER_SIZE
 CONFIG_API
 CONFIG_APUS_FAST_EXCEPT
 CONFIG_AP_SH4A_4A
 CONFIG_ARCH_AAED2000
 CONFIG_ARCH_ADI_COYOTE
 CONFIG_ARCH_ADPAG101P
 CONFIG_ARCH_AT91RM9200DK
 CONFIG_ARCH_AUTCPU12
 CONFIG_ARCH_BAST
 CONFIG_ARCH_CATS
 CONFIG_ARCH_CDB89712
 CONFIG_ARCH_CEIVA
 CONFIG_ARCH_CLEP7212
 CONFIG_ARCH_CPU_INIT
 CONFIG_ARCH_CSB226
 CONFIG_ARCH_DMA_PIO_WORDS
 CONFIG_ARCH_EARLY_INIT_R
 CONFIG_ARCH_EBSA110
 CONFIG_ARCH_EBSA285
 CONFIG_ARCH_EDB7211
 CONFIG_ARCH_ENP2611
 CONFIG_ARCH_FORTUNET
 CONFIG_ARCH_GUMSTIX
 CONFIG_ARCH_H1940
 CONFIG_ARCH_H5400
 CONFIG_ARCH_H7201
 CONFIG_ARCH_H7202
 CONFIG_ARCH_HAS_ILOG2_U32
 CONFIG_ARCH_HAS_ILOG2_U64
 CONFIG_ARCH_INNOKOM
 CONFIG_ARCH_IQ31244
 CONFIG_ARCH_IQ80321
 CONFIG_ARCH_IQ80331
 CONFIG_ARCH_IXCDP1100
 CONFIG_ARCH_IXDP2400
 CONFIG_ARCH_IXDP2401
 CONFIG_ARCH_IXDP2800
 CONFIG_ARCH_IXDP2801
 CONFIG_ARCH_IXDP425
 CONFIG_ARCH_KIRKWOOD
 CONFIG_ARCH_KS8695
 CONFIG_ARCH_L7200
 CONFIG_ARCH_LUBBOCK
 CONFIG_ARCH_MAP_SYSMEM
 CONFIG_ARCH_MISC_INIT
 CONFIG_ARCH_MX1ADS
 CONFIG_ARCH_NETWINDER
 CONFIG_ARCH_OMAP2
 CONFIG_ARCH_OMAP4
 CONFIG_ARCH_ORION5X
 CONFIG_ARCH_P720T
 CONFIG_ARCH_PERSONAL_SERVER
 CONFIG_ARCH_PLEB
 CONFIG_ARCH_PXA_CERF
 CONFIG_ARCH_PXA_IDP
 CONFIG_ARCH_RMOBILE_BOARD_STRING
 CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
 CONFIG_ARCH_RPC
 CONFIG_ARCH_S3C2440
 CONFIG_ARCH_SHARK
 CONFIG_ARCH_SMDK2410
 CONFIG_ARCH_TEGRA
 CONFIG_ARCH_USE_BUILTIN_BSWAP
 CONFIG_ARCH_VERSATILE_PB
 CONFIG_ARCH_VIPER
 CONFIG_ARC_MMU_VER
 CONFIG_ARC_SERIAL
 CONFIG_ARC_UART_BASE
 CONFIG_ARIA
 CONFIG_ARIA_FPGA
 CONFIG_ARM926EJS
 CONFIG_ARMADA100
 CONFIG_ARMADA100_FEC
 CONFIG_ARMADA100_SPI
 CONFIG_ARMADA168
 CONFIG_ARMADA_39X
 CONFIG_ARMCORTEXA9
 CONFIG_ARMV7_PSCI_1_0
 CONFIG_ARMV7_SECURE_BASE
 CONFIG_ARMV7_SECURE_MAX_SIZE
 CONFIG_ARMV7_SECURE_RESERVE_SIZE
 CONFIG_ARMV8_PSCI
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 CONFIG_ARMV8_SWITCH_TO_EL1
 CONFIG_ARM_ARCH_CP15_ERRATA
 CONFIG_ARM_ASM_UNIFIED
 CONFIG_ARM_DCC
 CONFIG_ARM_ERRATA_430973
 CONFIG_ARM_ERRATA_454179
 CONFIG_ARM_ERRATA_621766
 CONFIG_ARM_ERRATA_716044
 CONFIG_ARM_ERRATA_742230
 CONFIG_ARM_ERRATA_743622
 CONFIG_ARM_ERRATA_751472
 CONFIG_ARM_ERRATA_761320
 CONFIG_ARM_ERRATA_773022
 CONFIG_ARM_ERRATA_774769
 CONFIG_ARM_ERRATA_794072
 CONFIG_ARM_ERRATA_798870
 CONFIG_ARM_ERRATA_801819
 CONFIG_ARM_ERRATA_826974
 CONFIG_ARM_ERRATA_828024
 CONFIG_ARM_ERRATA_829520
 CONFIG_ARM_ERRATA_833069
 CONFIG_ARM_ERRATA_833471
 CONFIG_ARM_FREQ
 CONFIG_ARM_GIC_BASE_ADDRESS
 CONFIG_ARM_PL180_MMCI
 CONFIG_ARM_PL180_MMCI_BASE
 CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
 CONFIG_ARM_THUMB
 CONFIG_ARP_TIMEOUT
 CONFIG_AS3722_POWER
 CONFIG_ASTRO5373L
 CONFIG_ASTRO_COFDMDUOS2
 CONFIG_ASTRO_TWIN7S2
 CONFIG_ASTRO_V512
 CONFIG_ASTRO_V532
 CONFIG_ASTRO_V912
 CONFIG_AT32AP
 CONFIG_AT32AP7000
 CONFIG_AT32UC3A0xxx
 CONFIG_AT91C_PQFP_UHPBUG
 CONFIG_AT91FAMILY
 CONFIG_AT91RESET_EXTRST
 CONFIG_AT91RM9200
 CONFIG_AT91RM9200EK
 CONFIG_AT91SAM9260
 CONFIG_AT91SAM9260EK
 CONFIG_AT91SAM9261
 CONFIG_AT91SAM9261EK
 CONFIG_AT91SAM9263
 CONFIG_AT91SAM9263EK
 CONFIG_AT91SAM9G10
 CONFIG_AT91SAM9G10EK
 CONFIG_AT91SAM9G20
 CONFIG_AT91SAM9G20EK
 CONFIG_AT91SAM9G20EK_2MMC
 CONFIG_AT91SAM9G45
 CONFIG_AT91SAM9G45EKES
 CONFIG_AT91SAM9G45_LCD_BASE
 CONFIG_AT91SAM9M10G45
 CONFIG_AT91SAM9M10G45EK
 CONFIG_AT91SAM9N12
 CONFIG_AT91SAM9RL
 CONFIG_AT91SAM9RLEK
 CONFIG_AT91SAM9X5
 CONFIG_AT91SAM9X5EK
 CONFIG_AT91SAM9XE
 CONFIG_AT91SAM9_WATCHDOG
 CONFIG_AT91_CAN
 CONFIG_AT91_EFLASH
 CONFIG_AT91_GPIO
 CONFIG_AT91_GPIO_PULLUP
 CONFIG_AT91_HW_WDT_TIMEOUT
 CONFIG_AT91_LED
 CONFIG_AT91_WANTS_COMMON_PHY
 CONFIG_ATAPI
 CONFIG_ATA_ACPI
 CONFIG_ATI
 CONFIG_ATI_RADEON_FB
 CONFIG_ATM
 CONFIG_ATMEL_DATAFLASH_SPI
 CONFIG_ATMEL_HLCD
 CONFIG_ATMEL_LCD
 CONFIG_ATMEL_LCD_BGR555
 CONFIG_ATMEL_LCD_RGB565
 CONFIG_ATMEL_LEGACY
 CONFIG_ATMEL_MCI_8BIT
 CONFIG_ATMEL_NAND_HWECC
 CONFIG_ATMEL_NAND_HW_PMECC
 CONFIG_ATMEL_SDHCI0
 CONFIG_ATMEL_SDHCI1
 CONFIG_ATMEL_SPI
 CONFIG_ATMEL_SPI0
 CONFIG_ATMEL_USART
 CONFIG_ATNGW100
 CONFIG_ATNGW100MKII
 CONFIG_ATSTK1000
 CONFIG_ATSTK1000_16MB_SDRAM
 CONFIG_ATSTK1002
 CONFIG_AT_TRANS
 CONFIG_AUTOCALIB
 CONFIG_AUTONEG_TIMEOUT
 CONFIG_AUTO_COMPLETE
 CONFIG_AUTO_ZRELADDR
 CONFIG_B4860QDS
 CONFIG_BACKSIDE_L2_CACHE
 CONFIG_BAMBOO
 CONFIG_BAMBOO_NAND
 CONFIG_BARIX_IPAM390
 CONFIG_BAT_CMD
 CONFIG_BAT_PAIR
 CONFIG_BAT_RW
 CONFIG_BAUDRATE
 CONFIG_BCH
 CONFIG_BCH_CONST_M
 CONFIG_BCH_CONST_PARAMS
 CONFIG_BCH_CONST_T
 CONFIG_BCM2835_GPIO
 CONFIG_BCM2835_SDHCI
 CONFIG_BCM283X_MU_SERIAL
 CONFIG_BCM_SF2_ETH
 CONFIG_BCM_SF2_ETH_DEFAULT_PORT
 CONFIG_BCM_SF2_ETH_GMAC
 CONFIG_BD_NUM_CPUS
 CONFIG_BF506_UART0_PORTF
 CONFIG_BF506_UART1_PORTG
 CONFIG_BF50x
 CONFIG_BF51x
 CONFIG_BF527_EZKIT_REV_2_1
 CONFIG_BF52x
 CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
 CONFIG_BF54x
 CONFIG_BF60x
 CONFIG_BFIN_ATAPI_BASE_ADDR
 CONFIG_BFIN_ATA_MODE
 CONFIG_BFIN_BOARD_VERSION_1_0
 CONFIG_BFIN_BOOTROM_USES_EVT1
 CONFIG_BFIN_BOOT_MODE
 CONFIG_BFIN_CF_IDE
 CONFIG_BFIN_CPU
 CONFIG_BFIN_GET_DCLK_M
 CONFIG_BFIN_GPIO_TRACK
 CONFIG_BFIN_HDD_IDE
 CONFIG_BFIN_IDE
 CONFIG_BFIN_INS_LOWOVERHEAD
 CONFIG_BFIN_LINKPORT
 CONFIG_BFIN_MAC
 CONFIG_BFIN_MAC_PINS
 CONFIG_BFIN_NFC
 CONFIG_BFIN_NFC_BOOTROM_ECC
 CONFIG_BFIN_NFC_CTL_VAL
 CONFIG_BFIN_NFC_NO_HW_ECC
 CONFIG_BFIN_SCRATCH_REG
 CONFIG_BFIN_SDH
 CONFIG_BFIN_SERIAL
 CONFIG_BFIN_SOFT_SWITCH
 CONFIG_BFIN_SPI
 CONFIG_BFIN_SPI6XX
 CONFIG_BFIN_SPI_GPIO_CS
 CONFIG_BFIN_SPI_IDLE_VAL
 CONFIG_BFIN_SPI_IMG_SIZE
 CONFIG_BFIN_TRUE_IDE
 CONFIG_BFIN_WATCHDOG
 CONFIG_BIOSEMU
 CONFIG_BITBANGMII
 CONFIG_BITBANGMII_MULTI
 CONFIG_BKUP_FLASH
 CONFIG_BL1_OFFSET
 CONFIG_BL1_SIZE
 CONFIG_BL2_OFFSET
 CONFIG_BL2_SIZE
 CONFIG_BMP_16BPP
 CONFIG_BMP_24BMP
 CONFIG_BMP_24BPP
 CONFIG_BMP_32BPP
 CONFIG_BOARDDIR
 CONFIG_BOARDINFO
 CONFIG_BOARDNAME
 CONFIG_BOARDNAME_LOCAL
 CONFIG_BOARD_AXM
 CONFIG_BOARD_BOOTCMD
 CONFIG_BOARD_COMMON
 CONFIG_BOARD_EARLY_INIT_F
 CONFIG_BOARD_EARLY_INIT_R
 CONFIG_BOARD_ECC_SUPPORT
 CONFIG_BOARD_EMAC_COUNT
 CONFIG_BOARD_H2200
 CONFIG_BOARD_IS_OPENRD_BASE
 CONFIG_BOARD_IS_OPENRD_CLIENT
 CONFIG_BOARD_IS_OPENRD_ULTIMATE
 CONFIG_BOARD_LATE_INIT
 CONFIG_BOARD_MEM_LIMIT
 CONFIG_BOARD_NAME
 CONFIG_BOARD_POSTCLK_INIT
 CONFIG_BOARD_RESET
 CONFIG_BOARD_REVISION_TAG
 CONFIG_BOARD_SIZE_LIMIT
 CONFIG_BOARD_SPECIFIC_LED
 CONFIG_BOARD_TAURUS
 CONFIG_BOARD_TYPES
 CONFIG_BOOGER
 CONFIG_BOOKE
 CONFIG_BOOM
 CONFIG_BOOTARGS
 CONFIG_BOOTARGS_AXM
 CONFIG_BOOTARGS_ROOT
 CONFIG_BOOTARGS_TAURUS
 CONFIG_BOOTARGS_VIDEO
 CONFIG_BOOTBLOCK
 CONFIG_BOOTCOMMAND
 CONFIG_BOOTCOUNT_ALEN
 CONFIG_BOOTCOUNT_AM33XX
 CONFIG_BOOTCOUNT_ENV
 CONFIG_BOOTCOUNT_I2C
 CONFIG_BOOTCOUNT_LIMIT
 CONFIG_BOOTCOUNT_RAM
 CONFIG_BOOTFILE
 CONFIG_BOOTMAPSZ
 CONFIG_BOOTMODE
 CONFIG_BOOTM_LINUX
 CONFIG_BOOTM_NETBSD
 CONFIG_BOOTM_OPENRTOS
 CONFIG_BOOTM_OSE
 CONFIG_BOOTM_PLAN9
 CONFIG_BOOTM_RTEMS
 CONFIG_BOOTM_VXWORKS
 CONFIG_BOOTP_
 CONFIG_BOOTP_BOOTFILE
 CONFIG_BOOTP_BOOTFILESIZE
 CONFIG_BOOTP_BOOTPATH
 CONFIG_BOOTP_DEFAULT
 CONFIG_BOOTP_DHCP_REQUEST_DELAY
 CONFIG_BOOTP_DNS
 CONFIG_BOOTP_DNS2
 CONFIG_BOOTP_GATEWAY
 CONFIG_BOOTP_HOSTNAME
 CONFIG_BOOTP_ID_CACHE_SIZE
 CONFIG_BOOTP_MAY_FAIL
 CONFIG_BOOTP_NISDOMAIN
 CONFIG_BOOTP_NTPSERVER
 CONFIG_BOOTP_PXE
 CONFIG_BOOTP_RANDOM_DELAY
 CONFIG_BOOTP_SEND_HOSTNAME
 CONFIG_BOOTP_SERVERIP
 CONFIG_BOOTP_SUBNETMASK
 CONFIG_BOOTP_TIMEOFFSET
 CONFIG_BOOTP_VENDOREX
 CONFIG_BOOTROM_ERR_REG
 CONFIG_BOOTSCRIPT_ADDR
 CONFIG_BOOTSCRIPT_COPY_RAM
 CONFIG_BOOTSCRIPT_HDR_ADDR
 CONFIG_BOOTSCRIPT_KEY_HASH
 CONFIG_BOOT_DIR
 CONFIG_BOOT_FROM_XMD
 CONFIG_BOOT_MODE_BIT
 CONFIG_BOOT_NAND
 CONFIG_BOOT_ONENAND
 CONFIG_BOOT_OS_NET
 CONFIG_BOOT_PARAMS_ADDR
 CONFIG_BOOT_PCI
 CONFIG_BOOT_RETRY_MIN
 CONFIG_BOOT_RETRY_TIME
 CONFIG_BOUNCE_BUFFER
 CONFIG_BPTR_VIRT_ADDR
 CONFIG_BSC9131
 CONFIG_BSC9131RDB
 CONFIG_BSC9132
 CONFIG_BSC9132QDS
 CONFIG_BSEIP
 CONFIG_BS_ADDR_DEVICE
 CONFIG_BS_ADDR_RAM
 CONFIG_BS_COPY_CMD
 CONFIG_BS_COPY_ENV
 CONFIG_BS_HDR_ADDR_DEVICE
 CONFIG_BS_HDR_ADDR_RAM
 CONFIG_BS_HDR_SIZE
 CONFIG_BS_SIZE
 CONFIG_BTB
 CONFIG_BUBINGA
 CONFIG_BUFNO_AUTO_INCR_BIT
 CONFIG_BUILD_ENVCRC
 CONFIG_BUILD_TARGET
 CONFIG_BUS_WIDTH
 CONFIG_BZIP2
 CONFIG_C29XPCIE
 CONFIG_CACHELINE_ALIGNED_L1
 CONFIG_CADDY2
 CONFIG_CALXEDA_XGMAC
 CONFIG_CAM5200
 CONFIG_CAM5200_NIOSFLASH
 CONFIG_CANMB
 CONFIG_CAN_DRIVER
 CONFIG_CCLK_ACT_DIV
 CONFIG_CCLK_DIV
 CONFIG_CCLK_DIV_not_defined_properly
 CONFIG_CCLK_HZ
 CONFIG_CDP_APPLIANCE_VLAN_TYPE
 CONFIG_CDP_CAPABILITIES
 CONFIG_CDP_DEVICE_ID
 CONFIG_CDP_DEVICE_ID_PREFIX
 CONFIG_CDP_PLATFORM
 CONFIG_CDP_PORT_ID
 CONFIG_CDP_POWER_CONSUMPTION
 CONFIG_CDP_TRIGGER
 CONFIG_CDP_VERSION
 CONFIG_CFG_DATA_SECTOR
 CONFIG_CFG_FAT
 CONFIG_CFG_USB
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 CONFIG_CF_ATASEL_DIS
 CONFIG_CF_ATASEL_ENA
 CONFIG_CF_DSPI
 CONFIG_CF_QSPI
 CONFIG_CF_SBF
 CONFIG_CF_SPI
 CONFIG_CF_V2
 CONFIG_CF_V3
 CONFIG_CF_V4
 CONFIG_CF_V4E
 CONFIG_CGU_CTL_VAL
 CONFIG_CGU_DIV_VAL
 CONFIG_CHAIN_BOOT_CMD
 CONFIG_CHAIN_OF_TRUST
 CONFIG_CHARON
 CONFIG_CHIP_SELECTS_PER_CTRL
 CONFIG_CHIP_SELECT_QUAD_CAPABLE
 CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
 CONFIG_CIS8201_PHY
 CONFIG_CI_UDC_HAS_HOSTPC
 CONFIG_CLK0_DIV
 CONFIG_CLK0_EN
 CONFIG_CLKIN_HALF
 CONFIG_CLKIN_HZ
 CONFIG_CLK_1000_200_200
 CONFIG_CLK_1000_330_165
 CONFIG_CLK_1000_400_200
 CONFIG_CLK_800_330_165
 CONFIG_CLK_DEBUG
 CONFIG_CLOCKS
 CONFIG_CLOCKS_IN_MHZ
 CONFIG_CLOCK_SYNTHESIZER
 CONFIG_CM5200
 CONFIG_CM922T_XA10
 CONFIG_CMDLINE_EDITING
 CONFIG_CMDLINE_PS_SUPPORT
 CONFIG_CMDLINE_TAG
 CONFIG_CMD_AES
 CONFIG_CMD_ASKEN
 CONFIG_CMD_BAT
 CONFIG_CMD_BEDBUG
 CONFIG_CMD_BLOB
 CONFIG_CMD_BMODE
 CONFIG_CMD_BMP
 CONFIG_CMD_BOOTLDR
 CONFIG_CMD_BOOTMENU
 CONFIG_CMD_BSP
 CONFIG_CMD_CBFS
 CONFIG_CMD_CHIP_CONFIG
 CONFIG_CMD_CLEAR
 CONFIG_CMD_CLK
 CONFIG_CMD_CPLBINFO
 CONFIG_CMD_CRAMFS
 CONFIG_CMD_DATE
 CONFIG_CMD_DEFAULTENV_VARS
 CONFIG_CMD_DEKBLOB
 CONFIG_CMD_DFL
 CONFIG_CMD_DIAG
 CONFIG_CMD_DISPLAY
 CONFIG_CMD_DOC
 CONFIG_CMD_DS4510
 CONFIG_CMD_DS4510_INFO
 CONFIG_CMD_DS4510_MEM
 CONFIG_CMD_DS4510_RST
 CONFIG_CMD_DTT
 CONFIG_CMD_ECCTEST
 CONFIG_CMD_EECONFIG
 CONFIG_CMD_EEPROM
 CONFIG_CMD_EEPROM_LAYOUT
 CONFIG_CMD_ENTERRCM
 CONFIG_CMD_ENV
 CONFIG_CMD_ENV_CALLBACK
 CONFIG_CMD_ENV_FLAGS
 CONFIG_CMD_ERRATA
 CONFIG_CMD_ESBC_VALIDATE
 CONFIG_CMD_ETHSW
 CONFIG_CMD_FDC
 CONFIG_CMD_FDT_MAX_DUMP
 CONFIG_CMD_FPGAD
 CONFIG_CMD_FPGA_LOADBP
 CONFIG_CMD_FPGA_LOADFS
 CONFIG_CMD_FPGA_LOADMK
 CONFIG_CMD_FPGA_LOADP
 CONFIG_CMD_FUSE
 CONFIG_CMD_GETTIME
 CONFIG_CMD_GPT
 CONFIG_CMD_GSC
 CONFIG_CMD_HASH
 CONFIG_CMD_HD44760
 CONFIG_CMD_HD44780
 CONFIG_CMD_HDMIDETECT
 CONFIG_CMD_IDE
 CONFIG_CMD_IMMAP
 CONFIG_CMD_IMXOTP
 CONFIG_CMD_IMX_FUSE
 CONFIG_CMD_IO
 CONFIG_CMD_IOLOOP
 CONFIG_CMD_IOTRACE
 CONFIG_CMD_IRQ
 CONFIG_CMD_JFFS2
 CONFIG_CMD_KGDB
 CONFIG_CMD_LDRINFO
 CONFIG_CMD_LED
 CONFIG_CMD_LOADY
 CONFIG_CMD_LZMADEC
 CONFIG_CMD_MAX6957
 CONFIG_CMD_MD5SUM
 CONFIG_CMD_MEM
 CONFIG_CMD_MFSL
 CONFIG_CMD_MMC_SPI
 CONFIG_CMD_MTDPARTS
 CONFIG_CMD_MTDPARTS_SPREAD
 CONFIG_CMD_NAND_LOCK_UNLOCK
 CONFIG_CMD_NAND_TORTURE
 CONFIG_CMD_NAND_TRIMFFS
 CONFIG_CMD_ONENAND
 CONFIG_CMD_OTP
 CONFIG_CMD_PART
 CONFIG_CMD_PCA953X
 CONFIG_CMD_PCA953X_INFO
 CONFIG_CMD_PCI
 CONFIG_CMD_PCI_ENUM
 CONFIG_CMD_PCMCIA
 CONFIG_CMD_PORTIO
 CONFIG_CMD_PXE
 CONFIG_CMD_READ
 CONFIG_CMD_REGINFO
 CONFIG_CMD_REISER
 CONFIG_CMD_SANDBOX
 CONFIG_CMD_SATA
 CONFIG_CMD_SAVES
 CONFIG_CMD_SCSI
 CONFIG_CMD_SDRAM
 CONFIG_CMD_SF_TEST
 CONFIG_CMD_SH_ZIMAGEBOOT
 CONFIG_CMD_SOFTSWITCH
 CONFIG_CMD_SPIBOOTLDR
 CONFIG_CMD_SPL
 CONFIG_CMD_SPL_NAND_OFS
 CONFIG_CMD_SPL_WRITE_SIZE
 CONFIG_CMD_STRINGS
 CONFIG_CMD_SX151X
 CONFIG_CMD_TCA642X
 CONFIG_CMD_TERMINAL
 CONFIG_CMD_TFTP
 CONFIG_CMD_THOR_DOWNLOAD
 CONFIG_CMD_TRACE
 CONFIG_CMD_TSI148
 CONFIG_CMD_UBIFS
 CONFIG_CMD_UNIVERSE
 CONFIG_CMD_UNZIP
 CONFIG_CMD_USB_STORAGE
 CONFIG_CMD_UUID
 CONFIG_CMD_ZBOOT
 CONFIG_CMD_ZFS
 CONFIG_CM_INIT
 CONFIG_CM_MULTIPLE_SSRAM
 CONFIG_CM_REMAP
 CONFIG_CM_SPD_DETECT
 CONFIG_CM_T335
 CONFIG_CM_T3517
 CONFIG_CM_T3X
 CONFIG_CM_T43
 CONFIG_CM_T54
 CONFIG_CM_TCRAM
 CONFIG_CNTL
 CONFIG_COLDFIRE
 CONFIG_COMMANDS
 CONFIG_COMMAND_HISTORY
 CONFIG_COMMON_BOOT
 CONFIG_COMMON_ENV_MISC
 CONFIG_COMMON_ENV_SETTINGS
 CONFIG_COMMON_ENV_UBI
 CONFIG_COMPACT_FLASH
 CONFIG_COMPAT
-CONFIG_CONSOLE_SCROLL_LINES
 CONFIG_CONS_EXTC_PINSEL
 CONFIG_CONS_EXTC_RATE
 CONFIG_CONS_NONE
 CONFIG_CONS_ON_SCC
 CONFIG_CONS_ON_SMC
 CONFIG_CONS_SCIF0
 CONFIG_CONS_SCIF1
 CONFIG_CONS_SCIF2
 CONFIG_CONS_SCIF3
 CONFIG_CONS_SCIF4
 CONFIG_CONS_SCIF5
 CONFIG_CONS_SCIF7
 CONFIG_CONTROL
 CONFIG_CONTROLCENTERD
 CONFIG_CON_ROT
 CONFIG_CORE1_RUN
 CONFIG_CORE_COUNT
 CONFIG_CORTINA_FW_ADDR
 CONFIG_CORTINA_FW_LENGTH
 CONFIG_CPCI405
 CONFIG_CPCI405_6U
 CONFIG_CPCI405_VER2
 CONFIG_CPCI_AX2000
 CONFIG_CPLD_BR_PRELIM
 CONFIG_CPLD_OR_PRELIM
 CONFIG_CPM2
 CONFIG_CPUAT91
 CONFIG_CPU_ARCHS34
 CONFIG_CPU_ARMV8
 CONFIG_CPU_CAVIUM_OCTEON
 CONFIG_CPU_FREQ_HZ
 CONFIG_CPU_HAS_LLSC
 CONFIG_CPU_HAS_PREFETCH
 CONFIG_CPU_HAS_SMARTMIPS
 CONFIG_CPU_HAS_SR_RB
 CONFIG_CPU_HAS_WB
 CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
 CONFIG_CPU_LITTLE_ENDIAN
 CONFIG_CPU_MICROMIPS
 CONFIG_CPU_MIPSR2
 CONFIG_CPU_MONAHANS
 CONFIG_CPU_PXA25X
 CONFIG_CPU_PXA26X
 CONFIG_CPU_PXA27X
 CONFIG_CPU_PXA300
 CONFIG_CPU_R8000
 CONFIG_CPU_SH7203
 CONFIG_CPU_SH7264
 CONFIG_CPU_SH7269
 CONFIG_CPU_SH7706
 CONFIG_CPU_SH7720
 CONFIG_CPU_SH7722
 CONFIG_CPU_SH7723
 CONFIG_CPU_SH7724
 CONFIG_CPU_SH7734
 CONFIG_CPU_SH7750
 CONFIG_CPU_SH7751
 CONFIG_CPU_SH7752
 CONFIG_CPU_SH7753
 CONFIG_CPU_SH7757
 CONFIG_CPU_SH7763
 CONFIG_CPU_SH7780
 CONFIG_CPU_SH7785
 CONFIG_CPU_SH_TYPE_R
 CONFIG_CPU_TYPE_R
 CONFIG_CPU_VR41XX
 CONFIG_CP_CLK_FREQ
 CONFIG_CQSPI_DECODER
 CONFIG_CQSPI_REF_CLK
 CONFIG_CRC32
 CONFIG_CRC32_VERIFY
 CONFIG_CS8900
 CONFIG_CS8900_BASE
 CONFIG_CS8900_BUS16
 CONFIG_CS8900_BUS32
 CONFIG_CSF_SIZE
 CONFIG_CTL_JTAG
 CONFIG_CTL_TBE
 CONFIG_CTRD1_PROBE_T1
 CONFIG_CTRD1_PROBE_T2
 CONFIG_CUSTOMER_BOARD_SUPPORT
 CONFIG_CYRUS
 CONFIG_D2NET_V2
 CONFIG_DA850_AM18X_EVM
 CONFIG_DA850_EVM_MAX_CPU_CLK
 CONFIG_DA850_LOWLEVEL
 CONFIG_DA8XX_GPIO
 CONFIG_DASA_SIM
 CONFIG_DATA
 CONFIG_DAVINCI_MMC
 CONFIG_DAVINCI_MMC_SD1
 CONFIG_DAVINCI_SPI
 CONFIG_DBAU1000
 CONFIG_DBAU1X00
 CONFIG_DBGU
 CONFIG_DBG_MONITOR
 CONFIG_DB_784MP_GP
 CONFIG_DCACHE
 CONFIG_DCACHE_OFF
 CONFIG_DCACHE_WB
 CONFIG_DCFG_ADDR
 CONFIG_DCLK_DIV
 CONFIG_DDR_
 CONFIG_DDR_2HCLK
 CONFIG_DDR_2T_TIMING
 CONFIG_DDR_32BIT
 CONFIG_DDR_64BIT
 CONFIG_DDR_CLK_FREQ
 CONFIG_DDR_DATA_EYE
 CONFIG_DDR_DEFAULT_CL
 CONFIG_DDR_ECC
 CONFIG_DDR_ECC_CMD
 CONFIG_DDR_ECC_ENABLE
 CONFIG_DDR_ECC_INIT_VIA_DMA
 CONFIG_DDR_FIXED_SIZE
 CONFIG_DDR_FREQ
 CONFIG_DDR_HCLK
 CONFIG_DDR_HYB25D512160BF
 CONFIG_DDR_II
 CONFIG_DDR_K4H511638C
 CONFIG_DDR_LOG_LEVEL
 CONFIG_DDR_MB
 CONFIG_DDR_MT46V16M16
 CONFIG_DDR_MT46V32M16
 CONFIG_DDR_MT47H128M8
 CONFIG_DDR_MT47H32M16
 CONFIG_DDR_MT47H64M16
 CONFIG_DDR_PLL2
 CONFIG_DDR_RFDC_FIXED
 CONFIG_DDR_RQDC_FIXED
 CONFIG_DDR_SPD
 CONFIG_DEBUG
 CONFIG_DEBUG_DUMP
 CONFIG_DEBUG_DUMP_SYMS
 CONFIG_DEBUG_EARLY_SERIAL
 CONFIG_DEBUG_FS
 CONFIG_DEBUG_LED
 CONFIG_DEBUG_LOCK_ALLOC
 CONFIG_DEBUG_NULL_PTR
 CONFIG_DEBUG_SECTION_MISMATCH
 CONFIG_DEBUG_SEMIHOSTING
 CONFIG_DEBUG_SERIAL
 CONFIG_DEBUG_UART_LINFLEXUART
 CONFIG_DEBUG_WRITECOUNT
 CONFIG_DEB_DMA_URGENT
 CONFIG_DEEP_SLEEP
 CONFIG_DEFAULT
 CONFIG_DEFAULT_CONSOLE
 CONFIG_DEFAULT_FDT_FILE
 CONFIG_DEFAULT_IMMR
 CONFIG_DEFAULT_KERNEL_COMMAND_LINE
 CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
 CONFIG_DEFAULT_SPI_BUS
 CONFIG_DEFAULT_SPI_CS
 CONFIG_DEFAULT_SPI_MODE
 CONFIG_DEF_HWCONFIG
 CONFIG_DELAY_ENVIRONMENT
 CONFIG_DENX_M28_V10
 CONFIG_DESIGNWARE_ETH
 CONFIG_DESIGNWARE_WATCHDOG
 CONFIG_DEVCONCENTER
 CONFIG_DEVELOP
 CONFIG_DEVICE_TREE_LIST
 CONFIG_DEV_USB_PHY_BASE
 CONFIG_DFU_ALT
 CONFIG_DFU_ALT_BOOT_EMMC
 CONFIG_DFU_ALT_BOOT_SD
 CONFIG_DFU_ALT_SYSTEM
 CONFIG_DFU_ENV_SETTINGS
 CONFIG_DFU_MMC
 CONFIG_DFU_MTD
 CONFIG_DFU_NAND
 CONFIG_DFU_RAM
 CONFIG_DFU_SF
 CONFIG_DHCP_MIN_EXT_LEN
 CONFIG_DIALOG_POWER
 CONFIG_DIGSY_MTC
 CONFIG_DIGSY_REV5
 CONFIG_DIMM_SLOTS_PER_CTLR
 CONFIG_DIRECT_NOR_BOOT
 CONFIG_DISABLE_CONSOLE
 CONFIG_DISABLE_IMAGE_LEGACY
 CONFIG_DISABLE_PISE_TEST
 CONFIG_DISCONTIGMEM
 CONFIG_DISCOVER_PHY
 CONFIG_DISPLAY_AER_xxxx
 CONFIG_DISPLAY_BOARDINFO_LATE
 CONFIG_DISPLAY_CPUINFO
 CONFIG_DLVISION
 CONFIG_DLVISION_10G
 CONFIG_DM9000_BASE
 CONFIG_DM9000_BYTE_SWAPPED
 CONFIG_DM9000_DEBUG
 CONFIG_DM9000_NO_SROM
 CONFIG_DM9000_USE_16BIT
 CONFIG_DMA_COHERENT
 CONFIG_DMA_COHERENT_SIZE
 CONFIG_DMA_LPC32XX
 CONFIG_DMA_NONCOHERENT
 CONFIG_DMA_REQ_BIT
 CONFIG_DMC_DDRCFG
 CONFIG_DMC_DDRCTL
 CONFIG_DMC_DDREMR1
 CONFIG_DMC_DDRMR
 CONFIG_DMC_DDRTR0
 CONFIG_DMC_DDRTR1
 CONFIG_DMC_DDRTR2
 CONFIG_DNET_AUTONEG_TIMEOUT
 CONFIG_DNP5370_EXT_WD_DISABLE
 CONFIG_DOS_PARTITION
 CONFIG_DP_DDR_CTRL
 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
 CONFIG_DP_DDR_NUM_CTRLS
 CONFIG_DRA7XX
 CONFIG_DRAM_2G
 CONFIG_DRAM_TIMINGS_
 CONFIG_DRIVER_AT91EMAC
 CONFIG_DRIVER_AT91EMAC_PHYADDR
 CONFIG_DRIVER_AT91EMAC_QUIET
 CONFIG_DRIVER_AX88180
 CONFIG_DRIVER_AX88796L
 CONFIG_DRIVER_DM9000
 CONFIG_DRIVER_EP93XX_MAC
 CONFIG_DRIVER_ETHER
 CONFIG_DRIVER_NAND_BFIN
 CONFIG_DRIVER_NE2000
 CONFIG_DRIVER_NE2000_BASE
 CONFIG_DRIVER_NE2000_CCR
 CONFIG_DRIVER_NE2000_VAL
 CONFIG_DRIVER_SMC911X_BASE
 CONFIG_DRIVER_TI_CPSW
 CONFIG_DRIVER_TI_EMAC
 CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
 CONFIG_DRIVER_TI_EMAC_USE_RMII
 CONFIG_DRIVER_TI_KEYSTONE_NET
 CONFIG_DRIVE_MMC
 CONFIG_DRIVE_SATA
 CONFIG_DRIVE_TYPES
 CONFIG_DRIVE_USB
 CONFIG_DS4510
 CONFIG_DSP_CLUSTER_START
 CONFIG_DTT
 CONFIG_DTT_AD7414
 CONFIG_DTT_ADM1021
 CONFIG_DTT_DS1621
 CONFIG_DTT_DS1775
 CONFIG_DTT_DS620
 CONFIG_DTT_HYSTERESIS
 CONFIG_DTT_LM63
 CONFIG_DTT_LM75
 CONFIG_DTT_LM81
 CONFIG_DTT_MAX_TEMP
 CONFIG_DTT_MIN_TEMP
 CONFIG_DTT_PWM_LOOKUPTABLE
 CONFIG_DTT_SENSORS
 CONFIG_DTT_TACH_LIMIT
 CONFIG_DUOVERO
 CONFIG_DV_USBPHY_CTL
 CONFIG_DWC2_DFLT_SPEED_FULL
 CONFIG_DWC2_DMA_BURST_SIZE
 CONFIG_DWC2_DMA_ENABLE
 CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE
 CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE
 CONFIG_DWC2_HOST_RX_FIFO_SIZE
 CONFIG_DWC2_I2C_ENABLE
 CONFIG_DWC2_IC_USB_CAP
 CONFIG_DWC2_MAX_CHANNELS
 CONFIG_DWC2_MAX_PACKET_COUNT
 CONFIG_DWC2_MAX_TRANSFER_SIZE
 CONFIG_DWC2_PHY_TYPE
 CONFIG_DWC2_PHY_ULPI_DDR
 CONFIG_DWC2_PHY_ULPI_EXT_VBUS
 CONFIG_DWC2_THR_CTL
 CONFIG_DWC2_TS_DLINE
 CONFIG_DWC2_TX_THR_LENGTH
 CONFIG_DWC2_ULPI_FS_LS
 CONFIG_DWC2_UTMI_WIDTH
 CONFIG_DWCDDR21MCTL
 CONFIG_DWCDDR21MCTL_BASE
 CONFIG_DWC_AHSATA
 CONFIG_DWC_AHSATA_BASE_ADDR
 CONFIG_DWC_AHSATA_PORT_ID
 CONFIG_DWMMC
 CONFIG_DW_ALTDESCRIPTOR
 CONFIG_DW_AXI_BURST_LEN
 CONFIG_DW_GMAC_DEFAULT_DMA_PBL
 CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
 CONFIG_DW_PORTS
 CONFIG_DW_SERIAL
 CONFIG_DW_UDC
 CONFIG_DW_WDT_BASE
 CONFIG_DW_WDT_CLOCK_KHZ
 CONFIG_DYNAMIC_MMC_DEVNO
 CONFIG_E1000_NO_NVM
 CONFIG_E300
 CONFIG_E500
 CONFIG_E500MC
 CONFIG_E5500
 CONFIG_E6500
 CONFIG_EBCAW_VAL
 CONFIG_EBC_PPC4xx_IBM_VER1
 CONFIG_EBIU_AMBCTL0_VAL
 CONFIG_EBIU_AMBCTL1_VAL
 CONFIG_EBIU_AMGCTL_VAL
 CONFIG_EBIU_DDRCTL0_VAL
 CONFIG_EBIU_DDRCTL1_VAL
 CONFIG_EBIU_DDRCTL2_VAL
 CONFIG_EBIU_DDRCTL3_VAL
 CONFIG_EBIU_DDRQUE_VAL
 CONFIG_EBIU_FCTL_VAL
 CONFIG_EBIU_MBSCTL_VAL
 CONFIG_EBIU_MODE_VAL
 CONFIG_EBIU_RSTCTL_VAL
 CONFIG_EBIU_SDBCTL_VAL
 CONFIG_EBIU_SDGCTL_VAL
 CONFIG_EBIU_SDRRC_VAL
 CONFIG_EBSZ_VAL
 CONFIG_ECC
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 CONFIG_ECC_MODE_MASK
 CONFIG_ECC_MODE_SHIFT
 CONFIG_ECC_SRAM_ADDR_MASK
 CONFIG_ECC_SRAM_ADDR_SHIFT
 CONFIG_ECC_SRAM_REQ_BIT
 CONFIG_ECOVEC
 CONFIG_ECOVEC_ROMIMAGE_ADDR
 CONFIG_EDB9301
 CONFIG_EDB9302
 CONFIG_EDB9302A
 CONFIG_EDB9307
 CONFIG_EDB9307A
 CONFIG_EDB9312
 CONFIG_EDB9315
 CONFIG_EDB9315A
 CONFIG_EDB93XX_INDUSTRIAL
 CONFIG_EDB93XX_SDCS0
 CONFIG_EDB93XX_SDCS1
 CONFIG_EDB93XX_SDCS2
 CONFIG_EDB93XX_SDCS3
 CONFIG_EEPRO100
 CONFIG_EEPRO100_SROM_WRITE
 CONFIG_EEPROM_BUS_ADDRESS
 CONFIG_EEPROM_CHIP_ADDRESS
 CONFIG_EEPROM_LAYOUT_HELP_STRING
 CONFIG_EFI_PARTITION
 CONFIG_EFLASH_PROTSECTORS
 CONFIG_EHCI_DESC_BIG_ENDIAN
 CONFIG_EHCI_HCD_INIT_AFTER_RESET
 CONFIG_EHCI_IS_TDI
 CONFIG_EHCI_MMIO_BIG_ENDIAN
 CONFIG_EHCI_MXS_PORT0
 CONFIG_EHCI_MXS_PORT1
 CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 CONFIG_EMAC_MDIO_PHY_NUM
 CONFIG_EMAC_NR_START
 CONFIG_EMAC_PHY_MODE
 CONFIG_EMIF4
 CONFIG_EMMC_BOOT
 CONFIG_EMU
 CONFIG_ENABLE_36BIT_PHYS
 CONFIG_ENABLE_MMU
 CONFIG_ENABLE_MUST_CHECK
 CONFIG_ENABLE_VBOOT
 CONFIG_ENABLE_WARN_DEPRECATED
 CONFIG_ENC_SILENTLINK
 CONFIG_ENV_ACCESS_IGNORE_FORCE
 CONFIG_ENV_ADDR
 CONFIG_ENV_ADDR_FLEX
 CONFIG_ENV_ADDR_REDUND
 CONFIG_ENV_AES
 CONFIG_ENV_BASE
 CONFIG_ENV_CALLBACK_LIST_DEFAULT
 CONFIG_ENV_CALLBACK_LIST_STATIC
 CONFIG_ENV_COMMON_BOOT
 CONFIG_ENV_EEPROM_IS_ON_I2C
 CONFIG_ENV_FIT_UCBOOT
 CONFIG_ENV_FLAGS_LIST_DEFAULT
 CONFIG_ENV_FLAGS_LIST_STATIC
 CONFIG_ENV_FLASHBOOT
 CONFIG_ENV_IS_EMBEDDED
 CONFIG_ENV_IS_EMBEDDED_IN_LDR
 CONFIG_ENV_IS_IN_
 CONFIG_ENV_IS_IN_DATAFLASH
 CONFIG_ENV_IS_IN_EEPROM
 CONFIG_ENV_IS_IN_FAT
 CONFIG_ENV_IS_IN_FLASH
 CONFIG_ENV_IS_IN_MMC
 CONFIG_ENV_IS_IN_MRAM
 CONFIG_ENV_IS_IN_NAND
 CONFIG_ENV_IS_IN_NVRAM
 CONFIG_ENV_IS_IN_ONENAND
 CONFIG_ENV_IS_IN_REMOTE
 CONFIG_ENV_IS_IN_SPI_FLASH
 CONFIG_ENV_IS_IN_UBI
 CONFIG_ENV_IS_NOWHERE
 CONFIG_ENV_MAX_ENTRIES
 CONFIG_ENV_MIN_ENTRIES
 CONFIG_ENV_OFFSET
 CONFIG_ENV_OFFSET_OOB
 CONFIG_ENV_OFFSET_REDUND
 CONFIG_ENV_OVERWRITE
 CONFIG_ENV_RANGE
 CONFIG_ENV_RDADDR
 CONFIG_ENV_REFLASH
 CONFIG_ENV_SECT_SIZE
 CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS
 CONFIG_ENV_SETTINGS_NAND_V1
 CONFIG_ENV_SETTINGS_NAND_V2
 CONFIG_ENV_SETTINGS_V1
 CONFIG_ENV_SETTINGS_V2
 CONFIG_ENV_SIZE
 CONFIG_ENV_SIZE_FLEX
 CONFIG_ENV_SIZE_REDUND
 CONFIG_ENV_SPI_BASE
 CONFIG_ENV_SPI_BUS
 CONFIG_ENV_SPI_CS
 CONFIG_ENV_SPI_MAX_HZ
 CONFIG_ENV_SPI_MODE
 CONFIG_ENV_SROM_BANK
 CONFIG_ENV_TOTAL_SIZE
 CONFIG_ENV_UBIFS_OPTION
 CONFIG_ENV_UBI_MTD
 CONFIG_ENV_UBI_PART
 CONFIG_ENV_UBI_VOLUME
 CONFIG_ENV_UBI_VOLUME_REDUND
 CONFIG_ENV_VARS_UBOOT_CONFIG
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 CONFIG_ENV_VERSION
 CONFIG_ENV_xxx
 CONFIG_EP9301
 CONFIG_EP9302
 CONFIG_EP9307
 CONFIG_EP9312
 CONFIG_EP9315
 CONFIG_EP93XX
 CONFIG_EP93XX_NO_FLASH_CFG
 CONFIG_EP93XX_SPI
 CONFIG_EP93XX_SPI_MMC
 CONFIG_EPH_POWER_EN
 CONFIG_EPOLL
 CONFIG_ESBC_ADDR_64BIT
 CONFIG_ESBC_HDR_LS
 CONFIG_ESDHC_DETECT_8_BIT_QUIRK
 CONFIG_ESDHC_DETECT_QUIRK
 CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1
 CONFIG_ESDHC_HC_BLK_ADDR
 CONFIG_ESPRESSO7420
 CONFIG_ESPT
 CONFIG_ET1100_BASE
 CONFIG_ETH1ADDR
 CONFIG_ETH2ADDR
 CONFIG_ETHADDR
 CONFIG_ETHBASE
 CONFIG_ETHER_INDEX
 CONFIG_ETHER_LOOPBACK_TEST
 CONFIG_ETHER_NONE
 CONFIG_ETHER_ON_FCC
 CONFIG_ETHER_ON_FCC1
 CONFIG_ETHER_ON_FCC2
 CONFIG_ETHER_ON_FCC3
 CONFIG_ETHER_ON_FEC1
 CONFIG_ETHER_ON_FEC2
 CONFIG_ETHER_ON_SCC
 CONFIG_ETHPRIME
 CONFIG_ETH_BUFSIZE
 CONFIG_ETH_RXSIZE
 CONFIG_EXCEPTION_DEFER
 CONFIG_EXT4_WRITE
 CONFIG_EXTRA_BOOTARGS
 CONFIG_EXTRA_CLOCK
 CONFIG_EXTRA_ENV
 CONFIG_EXTRA_ENV_BOARD_SETTINGS
 CONFIG_EXTRA_ENV_ITB
 CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS
 CONFIG_EXTRA_ENV_SETTINGS
 CONFIG_EXTRA_ENV_SETTINGS_BASE
 CONFIG_EXTRA_ENV_SETTINGS_COMMON
 CONFIG_EXTRA_ENV_SETTINGS_DEVEL
 CONFIG_EXTRA_ENV_SETTINGS_SELECT
 CONFIG_EXTRA_ENV_UNLOCK
 CONFIG_EXTRA_ENV_USBTTY
 CONFIG_EXT_AHB2AHB_BASE
 CONFIG_EXT_AHBAPBBRG_BASE
 CONFIG_EXT_AHBPCIBRG_BASE
 CONFIG_EXT_AHBSLAVE01_BASE
 CONFIG_EXT_AHBSLAVE02_BASE
 CONFIG_EXT_PHY
 CONFIG_EXT_USB_HOST_BASE
 CONFIG_EXYNOS4
 CONFIG_EXYNOS4210
 CONFIG_EXYNOS5
 CONFIG_EXYNOS5250
 CONFIG_EXYNOS5420
 CONFIG_EXYNOS5800
 CONFIG_EXYNOS5_DT
 CONFIG_EXYNOS7420
 CONFIG_EXYNOS_ACE_SHA
 CONFIG_EXYNOS_DP
 CONFIG_EXYNOS_DWMMC
 CONFIG_EXYNOS_FB
 CONFIG_EXYNOS_MIPI_DSIM
 CONFIG_EXYNOS_RELOCATE_CODE_BASE
 CONFIG_EXYNOS_SPL
 CONFIG_EXYNOS_TMU
 CONFIG_FACTORYSET
 CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE
 CONFIG_FASTBOOT_FLASH_NAND_DEV
 CONFIG_FASTBOOT_FLASH_NAND_TRIMFFS
 CONFIG_FASTBOOT_GPT_NAME
 CONFIG_FAST_FLASH_BIT
 CONFIG_FAT_WRITE
 CONFIG_FB_ADDR
 CONFIG_FB_BACKLIGHT
 CONFIG_FB_DEFERRED_IO
 CONFIG_FDT1_ENV_ADDR
 CONFIG_FDT2_ENV_ADDR
 CONFIG_FDTADDR
 CONFIG_FDTFILE
 CONFIG_FDT_ENV_ADDR
 CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 CONFIG_FDT_FIXUP_PARTITIONS
 CONFIG_FDT_FIXUP_PCI_IRQ
 CONFIG_FEATURE_CLEAN_UP
 CONFIG_FEATURE_COMMAND_EDITING
 CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN
 CONFIG_FEATURE_SH_EXTRA_QUIET
 CONFIG_FEATURE_SH_FANCY_PROMPT
 CONFIG_FEATURE_SH_STANDALONE_SHELL
 CONFIG_FEC1_PHY
 CONFIG_FEC2_PHY
 CONFIG_FEC_10MBIT
 CONFIG_FEC_AN_TIMEOUT
 CONFIG_FEC_ENET
 CONFIG_FEC_ENET_DEV
 CONFIG_FEC_FIXED_SPEED
 CONFIG_FEC_MXC
 CONFIG_FEC_MXC_25M_REF_CLK
 CONFIG_FEC_MXC_PHYADDR
 CONFIG_FEC_MXC_SWAP_PACKET
 CONFIG_FEC_XCV_TYPE
 CONFIG_FEROCEON
 CONFIG_FEROCEON_88FR131
 CONFIG_FFUART
 CONFIG_FILE
 CONFIG_FIRMWARE_OFFSET
 CONFIG_FIRMWARE_SIZE
 CONFIG_FIT_DISABLE_SHA256
 CONFIG_FIXED_PHY
 CONFIG_FIXED_PHY_ADDR
 CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 CONFIG_FLASHBOOTCOMMAND
 CONFIG_FLASHCARD
 CONFIG_FLASH_16BIT
 CONFIG_FLASH_8BIT
 CONFIG_FLASH_BASE
 CONFIG_FLASH_BR_PRELIM
 CONFIG_FLASH_CFI_DRIVER
 CONFIG_FLASH_CFI_LEGACY
 CONFIG_FLASH_CFI_MTD
 CONFIG_FLASH_END
 CONFIG_FLASH_NOT_MEM_MAPPED
 CONFIG_FLASH_OR_PRELIM
 CONFIG_FLASH_PNOR
 CONFIG_FLASH_SECTOR_SIZE
 CONFIG_FLASH_SHOW_PROGRESS
 CONFIG_FLASH_SPANSION_S29WS_N
 CONFIG_FLASH_VERIFY
 CONFIG_FMAN_ENET
 CONFIG_FM_PLAT_CLK_DIV
 CONFIG_FO300
 CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
 CONFIG_FORMIKE
 CONFIG_FPGA_ALTERA
 CONFIG_FPGA_COUNT
 CONFIG_FPGA_CYCLON2
 CONFIG_FPGA_DELAY
 CONFIG_FPGA_SOCFPGA
 CONFIG_FPGA_SPARTAN2
 CONFIG_FPGA_SPARTAN3
 CONFIG_FPGA_STRATIX_V
 CONFIG_FPGA_ZYNQPL
 CONFIG_FSLDMAFEC
 CONFIG_FSL_CADMUS
 CONFIG_FSL_CORENET
 CONFIG_FSL_CPLD
 CONFIG_FSL_DCU_FB
 CONFIG_FSL_DCU_SII9022A
 CONFIG_FSL_DDR_BIST
 CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 CONFIG_FSL_DDR_INTERACTIVE
 CONFIG_FSL_DDR_SYNC_REFRESH
 CONFIG_FSL_DEBUG_SERVER
 CONFIG_FSL_DEEP_SLEEP
 CONFIG_FSL_DEVICE_DISABLE
 CONFIG_FSL_DIU_CH7301
 CONFIG_FSL_DIU_FB
 CONFIG_FSL_DMA
 CONFIG_FSL_DSPI1
 CONFIG_FSL_ELBC
 CONFIG_FSL_ESDHC
 CONFIG_FSL_ESDHC_ADAPTER_IDENT
 CONFIG_FSL_ESDHC_PIN_MUX
 CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 CONFIG_FSL_FIXED_MMC_LOCATION
 CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
 CONFIG_FSL_I2C_CUSTOM_DFSR
 CONFIG_FSL_I2C_CUSTOM_FDR
 CONFIG_FSL_IFC
 CONFIG_FSL_IIM
 CONFIG_FSL_ISBC_KEY_EXT
 CONFIG_FSL_LAW
 CONFIG_FSL_LAYERSCAPE
 CONFIG_FSL_LBC
 CONFIG_FSL_LINFLEXUART
 CONFIG_FSL_LS_PPA
 CONFIG_FSL_MC9SDZ60
 CONFIG_FSL_MC_ENET
 CONFIG_FSL_MEMAC
 CONFIG_FSL_NFC_CHIPS
 CONFIG_FSL_NFC_SPARE_SIZE
 CONFIG_FSL_NFC_WIDTH
 CONFIG_FSL_NFC_WRITE_SIZE
 CONFIG_FSL_NGPIXIS
 CONFIG_FSL_PCIE_DISABLE_ASPM
 CONFIG_FSL_PCIE_RESET
 CONFIG_FSL_PCI_INIT
 CONFIG_FSL_PIXIS
 CONFIG_FSL_PMIC_BITLEN
 CONFIG_FSL_PMIC_BUS
 CONFIG_FSL_PMIC_CLK
 CONFIG_FSL_PMIC_CS
 CONFIG_FSL_PMIC_MODE
 CONFIG_FSL_QIXIS
 CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 CONFIG_FSL_QIXIS_V2
 CONFIG_FSL_SATA
 CONFIG_FSL_SATA_ERRATUM_A001
 CONFIG_FSL_SATA_V2
 CONFIG_FSL_SDHC_V2_3
 CONFIG_FSL_SDRAM_TYPE
 CONFIG_FSL_SERDES
 CONFIG_FSL_SERDES1
 CONFIG_FSL_SERDES2
 CONFIG_FSL_SGMII_RISER
 CONFIG_FSL_SPI_INTERFACE
 CONFIG_FSL_TBCLK_EXTRA_DIV
 CONFIG_FSL_TRUST_ARCH_v1
 CONFIG_FSL_TZASC_400
 CONFIG_FSL_TZPC_BP147
 CONFIG_FSL_USDHC
 CONFIG_FSL_VIA
 CONFIG_FSMC_NAND_BASE
 CONFIG_FSMTDBLK
 CONFIG_FSNOTIFY
 CONFIG_FS_EXT4
 CONFIG_FS_FAT
 CONFIG_FS_FAT_MAX_CLUSTSIZE
 CONFIG_FS_POSIX_ACL
 CONFIG_FTAHBC020S
 CONFIG_FTAHBC020S_BASE
 CONFIG_FTAPBBRG020S_01_BASE
 CONFIG_FTCFC010_BASE
 CONFIG_FTDMAC020_BASE
 CONFIG_FTGMAC100_BASE
 CONFIG_FTGMAC100_EGIGA
 CONFIG_FTGPIO010_BASE
 CONFIG_FTI2C010_BASE1
 CONFIG_FTI2C010_BASE2
 CONFIG_FTI2C010_BASE3
 CONFIG_FTI2C010_CLOCK
 CONFIG_FTI2C010_TIMEOUT
 CONFIG_FTIDE020S_BASE
 CONFIG_FTIIC010_BASE
 CONFIG_FTINTC010_BASE
 CONFIG_FTLCDC100_BASE
 CONFIG_FTMAC100
 CONFIG_FTMAC100_BASE
 CONFIG_FTMAC110_BASE
 CONFIG_FTPCI100_BASE
 CONFIG_FTPCI100_IO_SIZE
 CONFIG_FTPCI100_MEM_BASE
 CONFIG_FTPCI100_MEM_SIZE
 CONFIG_FTPMU010
 CONFIG_FTPMU010_BASE
 CONFIG_FTPMU010_POWER
 CONFIG_FTPWM010_BASE
 CONFIG_FTRACE_MCOUNT_RECORD
 CONFIG_FTRTC010_BASE
 CONFIG_FTRTC010_EXTCLK
 CONFIG_FTRTC010_PCLK
 CONFIG_FTSDC010
 CONFIG_FTSDC010_BASE
 CONFIG_FTSDC010_BASE_LIST
 CONFIG_FTSDC010_NUMBER
 CONFIG_FTSDC010_SDIO
 CONFIG_FTSDC021_CLOCK
 CONFIG_FTSDMC021
 CONFIG_FTSDMC021_BASE
 CONFIG_FTSMC020
 CONFIG_FTSMC020_BASE
 CONFIG_FTSSP010_01_BASE
 CONFIG_FTSSP010_02_BASE
 CONFIG_FTTMR010_BASE
 CONFIG_FTTMR010_EXT_CLK
 CONFIG_FTUART010_01_BASE
 CONFIG_FTUART010_02_BASE
 CONFIG_FTUART010_03_BASE
 CONFIG_FTWDT010_BASE
 CONFIG_FTWDT010_WATCHDOG
 CONFIG_FUNC_ISRAM_ADDR
 CONFIG_FWUPDATE_DEBUG
 CONFIG_FZOTG266HD0A_BASE
 CONFIG_GATEWAYIP
 CONFIG_GCOV_KERNEL
 CONFIG_GCOV_PROFILE_ALL
 CONFIG_GENERIC_ATMEL_MCI
 CONFIG_GENERIC_MMC
 CONFIG_GICV2
 CONFIG_GICV3
 CONFIG_GLOBAL_DATA_NOT_REG10
 CONFIG_GLOBAL_TIMER
 CONFIG_GMII
 CONFIG_GOOD_SESH4
 CONFIG_GPCNTRL
 CONFIG_GPCS_PHY1_ADDR
 CONFIG_GPCS_PHY2_ADDR
 CONFIG_GPCS_PHY3_ADDR
 CONFIG_GPCS_PHY_ADDR
 CONFIG_GPIO
 CONFIG_GPIO_ENABLE_SPI_FLASH
 CONFIG_GPIO_LED
 CONFIG_GPIO_LED_INVERTED_TABLE
 CONFIG_GPIO_LED_STUBS
 CONFIG_GREEN_LED
 CONFIG_GRETH
 CONFIG_GRETH_10MBIT
 CONFIG_GRSIM
 CONFIG_GRXC3S1500
 CONFIG_GR_EP2S60
 CONFIG_GURNARD_FPGA
 CONFIG_GURNARD_SPLASH
 CONFIG_GZIP
 CONFIG_GZIP_COMPRESSED
 CONFIG_GZIP_COMPRESS_DEF_SZ
 CONFIG_G_DNL_THOR_PRODUCT_NUM
 CONFIG_G_DNL_THOR_VENDOR_NUM
 CONFIG_G_DNL_UMS_PRODUCT_NUM
 CONFIG_G_DNL_UMS_VENDOR_NUM
 CONFIG_H264_FREQ
 CONFIG_H8300
 CONFIG_HALEAKALA
 CONFIG_HARD_I2C
 CONFIG_HARD_SPI
 CONFIG_HASH_VERIFY
 CONFIG_HAS_DATAFLASH
 CONFIG_HAS_ETH0
 CONFIG_HAS_ETH1
 CONFIG_HAS_ETH2
 CONFIG_HAS_ETH3
 CONFIG_HAS_ETH4
 CONFIG_HAS_ETH5
 CONFIG_HAS_ETH7
 CONFIG_HAS_FEC
 CONFIG_HAS_FSL_DR_USB
 CONFIG_HAS_FSL_MPH_USB
 CONFIG_HAS_FSL_XHCI_USB
 CONFIG_HAS_POST
 CONFIG_HAS_VR
 CONFIG_HAVE_ACPI_RESUME
 CONFIG_HAVE_OWN_RESET
 CONFIG_HCLK_FREQ
 CONFIG_HDBOOT
 CONFIG_HDMI_ENCODER_I2C_ADDR
 CONFIG_HETROGENOUS_CLUSTERS
 CONFIG_HIDE_LOGO_VERSION
 CONFIG_HIGH_BATS
 CONFIG_HIKEY_DWMMC
 CONFIG_HIKEY_GPIO
 CONFIG_HIS_DRIVER
 CONFIG_HITACHI_SP19X001_Z1A
 CONFIG_HITACHI_SX14
 CONFIG_HLD1045
 CONFIG_HOSTNAME
 CONFIG_HOST_MAX_DEVICES
 CONFIG_HOTPLUG
 CONFIG_HPS_ALTERAGRP_DBGATCLK
 CONFIG_HPS_ALTERAGRP_MAINCLK
 CONFIG_HPS_ALTERAGRP_MPUCLK
 CONFIG_HPS_CLK_CAN0_HZ
 CONFIG_HPS_CLK_CAN1_HZ
 CONFIG_HPS_CLK_EMAC0_HZ
 CONFIG_HPS_CLK_EMAC1_HZ
 CONFIG_HPS_CLK_F2S_PER_REF_HZ
 CONFIG_HPS_CLK_F2S_SDR_REF_HZ
 CONFIG_HPS_CLK_GPIODB_HZ
 CONFIG_HPS_CLK_L4_MP_HZ
 CONFIG_HPS_CLK_L4_SP_HZ
 CONFIG_HPS_CLK_MAINVCO_HZ
 CONFIG_HPS_CLK_NAND_HZ
 CONFIG_HPS_CLK_OSC1_HZ
 CONFIG_HPS_CLK_OSC2_HZ
 CONFIG_HPS_CLK_PERVCO_HZ
 CONFIG_HPS_CLK_QSPI_HZ
 CONFIG_HPS_CLK_SDMMC_HZ
 CONFIG_HPS_CLK_SDRVCO_HZ
 CONFIG_HPS_CLK_SPIM_HZ
 CONFIG_HPS_CLK_USBCLK_HZ
 CONFIG_HPS_DBCTRL_STAYOSC1
 CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
 CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH
 CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH
 CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT
 CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT
 CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK
 CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK
 CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP
 CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP
 CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT
 CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK
 CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK
 CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK
 CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK
 CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT
 CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
 CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT
 CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK
 CONFIG_HPS_MAINPLLGRP_VCO_DENOM
 CONFIG_HPS_MAINPLLGRP_VCO_NUMER
 CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK
 CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK
 CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK
 CONFIG_HPS_PERPLLGRP_DIV_USBCLK
 CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT
 CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT
 CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK
 CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT
 CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT
 CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT
 CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT
 CONFIG_HPS_PERPLLGRP_SRC_NAND
 CONFIG_HPS_PERPLLGRP_SRC_QSPI
 CONFIG_HPS_PERPLLGRP_SRC_SDMMC
 CONFIG_HPS_PERPLLGRP_VCO_DENOM
 CONFIG_HPS_PERPLLGRP_VCO_NUMER
 CONFIG_HPS_PERPLLGRP_VCO_PSRC
 CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT
 CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE
 CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT
 CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE
 CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT
 CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE
 CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT
 CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE
 CONFIG_HPS_SDRPLLGRP_VCO_DENOM
 CONFIG_HPS_SDRPLLGRP_VCO_NUMER
 CONFIG_HPS_SDRPLLGRP_VCO_SSRC
 CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR
 CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP
 CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH
 CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN
 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT
 CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH
 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS
 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS
 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS
 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS
 CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH
 CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH
 CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN
 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ
 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
 CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
 CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED
 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED
 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED
 CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
 CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES
 CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4
 CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36
 CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0
 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32
 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14
 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46
 CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0
 CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN
 CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP
 CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
 CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
 CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
 CONFIG_HP_CLK_FREQ
 CONFIG_HRCON
 CONFIG_HRCON_DH
 CONFIG_HRCON_FANS
 CONFIG_HSMMC2_8BIT
 CONFIG_HUSH_INIT_VAR
 CONFIG_HVBOOT
 CONFIG_HWCONFIG
 CONFIG_HW_ENV_SETTINGS
 CONFIG_HW_WATCHDOG
 CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
 CONFIG_HW_WATCHDOG_TIMEOUT_MS
 CONFIG_I2C
 CONFIG_I2CFAST
 CONFIG_I2C_CHIPADDRESS
 CONFIG_I2C_CMD_TREE
 CONFIG_I2C_ENV_EEPROM_BUS
 CONFIG_I2C_FPGA
 CONFIG_I2C_GSC
 CONFIG_I2C_MAC_OFFSET
 CONFIG_I2C_MBB_TIMEOUT
 CONFIG_I2C_MULTI_BUS
 CONFIG_I2C_MV
 CONFIG_I2C_MVTWSI
 CONFIG_I2C_MVTWSI_BASE
 CONFIG_I2C_MVTWSI_BASE0
 CONFIG_I2C_MVTWSI_BASE1
 CONFIG_I2C_MVTWSI_BASE2
 CONFIG_I2C_MVTWSI_BASE3
 CONFIG_I2C_MVTWSI_BASE4
 CONFIG_I2C_MVTWSI_BASE5
 CONFIG_I2C_MXC
 CONFIG_I2C_PMIC
 CONFIG_I2C_REPEATED_START
 CONFIG_I2C_RTC_ADDR
 CONFIG_I2C_TIMEOUT
 CONFIG_IBM_EMAC4_V4
 CONFIG_ICACHE
 CONFIG_ICACHE_OFF
 CONFIG_ICON
 CONFIG_ICS307_REFCLK_HZ
 CONFIG_IDE_8xx_DIRECT
 CONFIG_IDE_8xx_PCCARD
 CONFIG_IDE_INIT_POSTRESET
 CONFIG_IDE_LED
 CONFIG_IDE_PCMCIA
 CONFIG_IDE_PREINIT
 CONFIG_IDE_REG_CS
 CONFIG_IDE_RESET
 CONFIG_IDE_RESET_ROUTINE
 CONFIG_IDE_SIL680
 CONFIG_IDE_SWAP_IO
 CONFIG_IDS8313
 CONFIG_IDT8T49N222A
 CONFIG_ID_EEPROM
 CONFIG_IFM_DEFAULT_ENV_NEW
 CONFIG_IFM_DEFAULT_ENV_OLD
 CONFIG_IFM_DEFAULT_ENV_SETTINGS
 CONFIG_IFM_SENSOR_TYPE
 CONFIG_IMA
 CONFIG_IMAGE_FORMAT_LEGACY
 CONFIG_IMX
 CONFIG_IMX31_PHYCORE_EET
 CONFIG_IMX6_PWM_PER_CLK
 CONFIG_IMX_HDMI
 CONFIG_IMX_NAND
 CONFIG_IMX_OTP
 CONFIG_IMX_THERMAL
 CONFIG_IMX_VIDEO_SKIP
 CONFIG_IMX_WATCHDOG
 CONFIG_INETSPACE_V2
 CONFIG_INITRD_TAG
 CONFIG_INIT_CRITICAL
 CONFIG_INIT_IGNORE_ERROR
 CONFIG_INIT_TLB
 CONFIG_INI_ALLOW_MULTILINE
 CONFIG_INI_CASE_INSENSITIVE
 CONFIG_INI_MAX_LINE
 CONFIG_INI_MAX_NAME
 CONFIG_INI_MAX_SECTION
 CONFIG_INKA4X0
 CONFIG_INTEGRITY
 CONFIG_INTEL_ICH6_GPIO
 CONFIG_INTERRUPTS
 CONFIG_INTIB
 CONFIG_IO
 CONFIG_IO64
 CONFIG_IOCON
 CONFIG_IODELAY_RECALIBRATION
 CONFIG_IOMUX_LPSR
 CONFIG_IOMUX_SHARE_CONF_REG
 CONFIG_IOS
 CONFIG_IO_TRACE
 CONFIG_IP86x
 CONFIG_IPADDR
 CONFIG_IPADDR1
 CONFIG_IPADDR2
 CONFIG_IPAM390_GPIO_BOOTMODE
 CONFIG_IPAM390_GPIO_LED_GREEN
 CONFIG_IPAM390_GPIO_LED_RED
 CONFIG_IPEK01
 CONFIG_IPIPE
 CONFIG_IPROC
 CONFIG_IPUV3_CLK
 CONFIG_IP_DEFRAG
 CONFIG_IRAM_BASE
 CONFIG_IRAM_END
 CONFIG_IRAM_SIZE
 CONFIG_IRAM_STACK
 CONFIG_IRAM_TOP
 CONFIG_IRDA_BASE
 CONFIG_ISO_PARTITION
 CONFIG_ISP1362_USB
 CONFIG_IS_BUILTIN
 CONFIG_IS_ENABLED
 CONFIG_IS_INVALID
 CONFIG_IS_MODULE
 CONFIG_IS_VALID
 CONFIG_IVMS8
 CONFIG_JFFS2_CMDLINE
 CONFIG_JFFS2_DEV
 CONFIG_JFFS2_LZO
 CONFIG_JFFS2_NAND
 CONFIG_JFFS2_PART_OFFSET
 CONFIG_JFFS2_PART_SIZE
 CONFIG_JFFS2_SUMMARY
 CONFIG_JRSTARTR_JR0
 CONFIG_JTAG_CONSOLE
 CONFIG_JTAG_CONSOLE_TIMEOUT
 CONFIG_JUPITER
 CONFIG_K2E_EVM
 CONFIG_K2G_EVM
 CONFIG_K2HK_EVM
 CONFIG_K2L_EVM
 CONFIG_KALLSYMS
 CONFIG_KASAN
 CONFIG_KATMAI
 CONFIG_KCLK_DIS
 CONFIG_KEEP_SERVERADDR
 CONFIG_KERNEL_OFFSET
 CONFIG_KEYBOARD
 CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE
 CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE
 CONFIG_KEYSTONE_RBL_NAND
 CONFIG_KEY_REVOCATION
 CONFIG_KGDB_BAUDRATE
 CONFIG_KGDB_EXTC_PINSEL
 CONFIG_KGDB_EXTC_RATE
 CONFIG_KGDB_INDEX
 CONFIG_KGDB_ON_SCC
 CONFIG_KGDB_ON_SMC
 CONFIG_KGDB_SER_INDEX
 CONFIG_KILAUEA
 CONFIG_KIRKWOOD_EGIGA_INIT
 CONFIG_KIRKWOOD_GPIO
 CONFIG_KIRKWOOD_PCIE_INIT
 CONFIG_KIRKWOOD_RGMII_PAD_1V8
 CONFIG_KIRKWOOD_SPI
 CONFIG_KIRQ_EN
 CONFIG_KM8321
 CONFIG_KM8XX
 CONFIG_KMCOGE4
 CONFIG_KMCOGE5NE
 CONFIG_KMETER1
 CONFIG_KMLION1
 CONFIG_KMOPTI2
 CONFIG_KMP204X
 CONFIG_KMSUPX5
 CONFIG_KMTEGR1
 CONFIG_KMTEPR2
 CONFIG_KMVECT1
 CONFIG_KM_82XX
 CONFIG_KM_BOARD_EXTRA_ENV
 CONFIG_KM_BOARD_NAME
 CONFIG_KM_COGE5UN
 CONFIG_KM_COMMON_ETH_INIT
 CONFIG_KM_CONSOLE_TTY
 CONFIG_KM_CRAMFS_ADDR
 CONFIG_KM_DEF_ARCH
 CONFIG_KM_DEF_BOOT_ARGS_CPU
 CONFIG_KM_DEF_ENV
 CONFIG_KM_DEF_ENV_BOOTARGS
 CONFIG_KM_DEF_ENV_BOOTPARAMS
 CONFIG_KM_DEF_ENV_BOOTTARGETS
 CONFIG_KM_DEF_ENV_CONSTANTS
 CONFIG_KM_DEF_ENV_CPU
 CONFIG_KM_DEF_ENV_FLASH_BOOT
 CONFIG_KM_DEF_NETDEV
 CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
 CONFIG_KM_DISABLE_PCI
 CONFIG_KM_DISABLE_PCIE
 CONFIG_KM_ECC_MODE
 CONFIG_KM_ENV_IS_IN_SPI_NOR
 CONFIG_KM_FDT_ADDR
 CONFIG_KM_FPGA_CONFIG
 CONFIG_KM_I2C_ABORT
 CONFIG_KM_IVM_BUS
 CONFIG_KM_KERNEL_ADDR
 CONFIG_KM_KIRKWOOD
 CONFIG_KM_KIRKWOOD_128M16
 CONFIG_KM_KIRKWOOD_PCI
 CONFIG_KM_MGCOGE3UN
 CONFIG_KM_MVEXTSW_ADDR
 CONFIG_KM_NEW_ENV
 CONFIG_KM_NUSA
 CONFIG_KM_PHRAM
 CONFIG_KM_PIGGY4_88E6061
 CONFIG_KM_PIGGY4_88E6352
 CONFIG_KM_PNVRAM
 CONFIG_KM_PORTL2
 CONFIG_KM_RESERVED_PRAM
 CONFIG_KM_ROOTFSSIZE
 CONFIG_KM_SUGP1
 CONFIG_KM_SUV31
 CONFIG_KM_UBI_LINUX_MTD
 CONFIG_KM_UBI_PARTITION_NAME_APP
 CONFIG_KM_UBI_PARTITION_NAME_BOOT
 CONFIG_KM_UBI_PART_BOOT_OPTS
 CONFIG_KM_UIMAGE_NAME
 CONFIG_KM_UPDATE_UBOOT
 CONFIG_KONA
 CONFIG_KONA_GPIO
 CONFIG_KONA_RESET_S
 CONFIG_KONA_SDHCI
 CONFIG_KPROBES
 CONFIG_KS8851_MLL
 CONFIG_KS8851_MLL_BASEADDR
 CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE
 CONFIG_KSNAV_NETCP_PDMA_RX_BASE
 CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM
 CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE
 CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM
 CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE
 CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE
 CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE
 CONFIG_KSNAV_NETCP_PDMA_TX_BASE
 CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM
 CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE
 CONFIG_KSNAV_PKTDMA_NETCP
 CONFIG_KSNAV_QM_BASE_ADDRESS
 CONFIG_KSNAV_QM_CONF_BASE
 CONFIG_KSNAV_QM_DESC_SETUP_BASE
 CONFIG_KSNAV_QM_INTD_CONF_BASE
 CONFIG_KSNAV_QM_LINK_RAM_BASE
 CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE
 CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE
 CONFIG_KSNAV_QM_PDSP1_CMD_BASE
 CONFIG_KSNAV_QM_PDSP1_CTRL_BASE
 CONFIG_KSNAV_QM_PDSP1_IRAM_BASE
 CONFIG_KSNAV_QM_QPOOL_NUM
 CONFIG_KSNAV_QM_QUEUE_STATUS_BASE
 CONFIG_KSNAV_QM_REGION_NUM
 CONFIG_KSNAV_QM_STATUS_RAM_BASE
 CONFIG_KSNET_CPSW_NUM_PORTS
 CONFIG_KSNET_MAC_ID_BASE
 CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
 CONFIG_KSNET_NETCP_BASE
 CONFIG_KSNET_NETCP_V1_0
 CONFIG_KSNET_NETCP_V1_5
 CONFIG_KSNET_SERDES_LANES_PER_SGMII
 CONFIG_KSNET_SERDES_SGMII2_BASE
 CONFIG_KSNET_SERDES_SGMII_BASE
 CONFIG_KVM_GUEST
 CONFIG_KW88F6192
 CONFIG_KW88F6281
 CONFIG_KW88F6702
 CONFIG_KYOCERA_KCS057QV1AJ
 CONFIG_KZM_A9_GT
 CONFIG_L1_INIT_RAM
 CONFIG_L2_CACHE
 CONFIG_LAN91C96_USE_32_BIT
 CONFIG_LAST_STAGE_INIT
 CONFIG_LAYERSCAPE_NS_ACCESS
 CONFIG_LBA48
 CONFIG_LBD
 CONFIG_LBDAF
 CONFIG_LCD_ALIGNMENT
 CONFIG_LCD_BMP_RLE8
 CONFIG_LCD_DT_SIMPLEFB
 CONFIG_LCD_INFO
 CONFIG_LCD_INFO_BELOW_LOGO
 CONFIG_LCD_IN_PSRAM
 CONFIG_LCD_LOGO
 CONFIG_LCD_MENU
 CONFIG_LCD_MENU_BOARD
 CONFIG_LCD_NOSTDOUT
 CONFIG_LCD_ROTATION
 CONFIG_LD9040
 CONFIG_LEGACY
 CONFIG_LEGACY_BOOTCMD_ENV
 CONFIG_LEON_RAM_SDRAM
 CONFIG_LEON_RAM_SDRAM_NOSRAM
 CONFIG_LEON_RAM_SELECT
 CONFIG_LEON_RAM_SRAM
 CONFIG_LG4573
 CONFIG_LG4573_BUS
 CONFIG_LG4573_CS
 CONFIG_LIBATA
 CONFIG_LIB_HW_RAND
 CONFIG_LIB_UUID
 CONFIG_LINUX
 CONFIG_LINUX_CMDLINE_ADDR
 CONFIG_LINUX_CMDLINE_SIZE
 CONFIG_LINUX_RESET_VEC
 CONFIG_LITTLETON_LCD
 CONFIG_LMB
 CONFIG_LMS283GF05
 CONFIG_LOADADDR
 CONFIG_LOADCMD
 CONFIG_LOADS_ECHO
 CONFIG_LOGBUFFER
 CONFIG_LOWBOOT
 CONFIG_LOWPOWER_ADDR
 CONFIG_LOWPOWER_FLAG
 CONFIG_LOW_MCFCLK
 CONFIG_LPC32XX_ETH
 CONFIG_LPC32XX_ETH_BUFS_BASE
 CONFIG_LPC32XX_HSUART
 CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY
 CONFIG_LPC32XX_NAND_MLC_NAND_TA
 CONFIG_LPC32XX_NAND_MLC_RD_HIGH
 CONFIG_LPC32XX_NAND_MLC_RD_LOW
 CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY
 CONFIG_LPC32XX_NAND_MLC_WR_HIGH
 CONFIG_LPC32XX_NAND_MLC_WR_LOW
 CONFIG_LPC32XX_NAND_SLC_RDR_CLKS
 CONFIG_LPC32XX_NAND_SLC_RHOLD
 CONFIG_LPC32XX_NAND_SLC_RSETUP
 CONFIG_LPC32XX_NAND_SLC_RWIDTH
 CONFIG_LPC32XX_NAND_SLC_WDR_CLKS
 CONFIG_LPC32XX_NAND_SLC_WHOLD
 CONFIG_LPC32XX_NAND_SLC_WSETUP
 CONFIG_LPC32XX_NAND_SLC_WWIDTH
 CONFIG_LPC32XX_SDRAM_
 CONFIG_LPC32XX_SPL
 CONFIG_LPC32XX_SSP
 CONFIG_LPC32XX_SSP_TIMEOUT
 CONFIG_LPC_BASE
 CONFIG_LPC_IO_BASE
 CONFIG_LPUART
 CONFIG_LPUART_32B_REG
 CONFIG_LQ035Q1_LCD_MODE
 CONFIG_LQ035Q1_SPI_BUS
 CONFIG_LQ035Q1_SPI_CS
 CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
 CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
 CONFIG_LQ038J7DH53
 CONFIG_LS1012A
 CONFIG_LS102XA
 CONFIG_LS102XA_STREAM_ID
 CONFIG_LS1043A
 CONFIG_LS2080A
 CONFIG_LSCHLV2
 CONFIG_LSXHL
 CONFIG_LUAN
 CONFIG_LWMON5
 CONFIG_LXT971_NO_SLEEP
 CONFIG_LYNXKDI
 CONFIG_LZMA
 CONFIG_LZO
 CONFIG_M41T94_SPI_CS
 CONFIG_M520x
 CONFIG_M52277EVB
 CONFIG_M5253DEMO
 CONFIG_M5253EVBE
 CONFIG_M5275EVB
 CONFIG_M5301x
 CONFIG_M54418TWR
 CONFIG_M54451EVB
 CONFIG_M54455EVB
 CONFIG_M88E1111_DISABLE_FIBER
 CONFIG_M88E1111_PHY
 CONFIG_M88E1112_PHY
 CONFIG_M88E1141_PHY
 CONFIG_MACB
 CONFIG_MACB0_PHY
 CONFIG_MACB1_PHY
 CONFIG_MACB2_PHY
 CONFIG_MACB3_PHY
 CONFIG_MACB_SEARCH_PHY
 CONFIG_MACH_A0
 CONFIG_MACH_A2F
 CONFIG_MACH_ABACUS
 CONFIG_MACH_ABB_GMA_1_1
 CONFIG_MACH_ABILENE
 CONFIG_MACH_ABLE
 CONFIG_MACH_ACER_A5
 CONFIG_MACH_ACER_A8
 CONFIG_MACH_ACER_GAUGUIN
 CONFIG_MACH_ACER_MAYA
 CONFIG_MACH_ACMENETUSFOXG20
 CONFIG_MACH_ACMEROVER1
 CONFIG_MACH_ACRO37XBRD
 CONFIG_MACH_ACS5K
 CONFIG_MACH_ACSX106
 CONFIG_MACH_ADSSPHERE
 CONFIG_MACH_AEBL
 CONFIG_MACH_AF4000
 CONFIG_MACH_AFEB9260
 CONFIG_MACH_AG11005
 CONFIG_MACH_AG5EVM
 CONFIG_MACH_AKITA
 CONFIG_MACH_AMK_A4
 CONFIG_MACH_AML_M5900
 CONFIG_MACH_AMS_DELTA
 CONFIG_MACH_ANCHOVY
 CONFIG_MACH_ANTARES
 CONFIG_MACH_ANTERO
 CONFIG_MACH_ANUBIS
 CONFIG_MACH_ANW6410
 CONFIG_MACH_AP4EVB
 CONFIG_MACH_APALIS_T30
 CONFIG_MACH_APP3K_ROBIN
 CONFIG_MACH_AQUARIUS
 CONFIG_MACH_AQUILA
 CONFIG_MACH_ARCOM_VULCAN
 CONFIG_MACH_ARCOM_ZEUS
 CONFIG_MACH_ARK9431
 CONFIG_MACH_ARMADA_XP_DB
 CONFIG_MACH_ARMADILLO460
 CONFIG_MACH_ARMADILLO5X0
 CONFIG_MACH_ARMADILLO800EVA
 CONFIG_MACH_ARMCORE
 CONFIG_MACH_ARMLEX4210
 CONFIG_MACH_ARMLGUEST
 CONFIG_MACH_AROWANA
 CONFIG_MACH_ARTHUR
 CONFIG_MACH_ARUBA
 CONFIG_MACH_AS1167
 CONFIG_MACH_ASL_PHOENIX
 CONFIG_MACH_ASPEN
 CONFIG_MACH_ASPENITE
 CONFIG_MACH_AST2200
 CONFIG_MACH_AT2440EVB
 CONFIG_MACH_AT572D940HFEB
 CONFIG_MACH_AT91CAP7STK
 CONFIG_MACH_AT91CAP7XDK
 CONFIG_MACH_AT91CAP9ADK
 CONFIG_MACH_AT91EB01
 CONFIG_MACH_AT91RM9200EK
 CONFIG_MACH_AT91SAM9260EK
 CONFIG_MACH_AT91SAM9261EK
 CONFIG_MACH_AT91SAM9263DESK16L
 CONFIG_MACH_AT91SAM9263EK
 CONFIG_MACH_AT91SAM9263OTLITE
 CONFIG_MACH_AT91SAM9G10EK
 CONFIG_MACH_AT91SAM9G20EK
 CONFIG_MACH_AT91SAM9G20EK_2MMC
 CONFIG_MACH_AT91SAM9G45EKES
 CONFIG_MACH_AT91SAM9M10G45EK
 CONFIG_MACH_AT91SAM9RLEK
 CONFIG_MACH_AT91SAM9X5EK
 CONFIG_MACH_ATDGP318
 CONFIG_MACH_ATEB9200
 CONFIG_MACH_ATHENE
 CONFIG_MACH_ATLAS5_C1
 CONFIG_MACH_AUTOBOT
 CONFIG_MACH_AVENGERS_LITE
 CONFIG_MACH_AVILA
 CONFIG_MACH_AWM2
 CONFIG_MACH_AX502
 CONFIG_MACH_AX8008
 CONFIG_MACH_B5500
 CONFIG_MACH_BASI
 CONFIG_MACH_BCM2708
 CONFIG_MACH_BCM589X
 CONFIG_MACH_BCMHANA_SV
 CONFIG_MACH_BCMHANA_TABLET
 CONFIG_MACH_BCMRING
 CONFIG_MACH_BEECT
 CONFIG_MACH_BIGDISK
 CONFIG_MACH_BIO3K
 CONFIG_MACH_BIPNET
 CONFIG_MACH_BLISS
 CONFIG_MACH_BLISSC
 CONFIG_MACH_BLUECHEESE
 CONFIG_MACH_BLUEPOINT
 CONFIG_MACH_BLUESHARK
 CONFIG_MACH_BOCKW
 CONFIG_MACH_BONAIRE
 CONFIG_MACH_BORABORA
 CONFIG_MACH_BORZOI
 CONFIG_MACH_BROWNSTONE
 CONFIG_MACH_BSTBRD
 CONFIG_MACH_BTMAVB101
 CONFIG_MACH_BTMAWB101
 CONFIG_MACH_BUBBA3
 CONFIG_MACH_BUG
 CONFIG_MACH_BUG20
 CONFIG_MACH_BURY_BL7582
 CONFIG_MACH_BURY_BPS5270
 CONFIG_MACH_BV07
 CONFIG_MACH_C2MMI
 CONFIG_MACH_CALLISTO
 CONFIG_MACH_CAM60
 CONFIG_MACH_CAPC7117
 CONFIG_MACH_CARDHU
 CONFIG_MACH_CARMEVA
 CONFIG_MACH_CAYENNE
 CONFIG_MACH_CC9P9360DEV
 CONFIG_MACH_CC9P9360JS
 CONFIG_MACH_CCMX53
 CONFIG_MACH_CCMX53JS
 CONFIG_MACH_CCWMX51MUT
 CONFIG_MACH_CCWMX53
 CONFIG_MACH_CCWMX53JS
 CONFIG_MACH_CENTRO
 CONFIG_MACH_CETUS9263
 CONFIG_MACH_CHACHA
 CONFIG_MACH_CHALTEN_XA1
 CONFIG_MACH_CHARON
 CONFIG_MACH_CLOD
 CONFIG_MACH_CM4745
 CONFIG_MACH_CM_A510
 CONFIG_MACH_CM_T35
 CONFIG_MACH_CM_T3517
 CONFIG_MACH_CM_T3730
 CONFIG_MACH_CM_X300
 CONFIG_MACH_CNS2133EVB
 CONFIG_MACH_CNS21XX
 CONFIG_MACH_CNS3420VB
 CONFIG_MACH_COBRAL138
 CONFIG_MACH_COCONUT
 CONFIG_MACH_COLIBRI
 CONFIG_MACH_COLIBRI300
 CONFIG_MACH_COLIBRI320
 CONFIG_MACH_COLIBRI_T20
 CONFIG_MACH_COLIBRI_T30
 CONFIG_MACH_CONTROLTEK9G20
 CONFIG_MACH_CORETEC_VCX7400
 CONFIG_MACH_CORGI
 CONFIG_MACH_CPUAT9G20
 CONFIG_MACH_CPX2
 CONFIG_MACH_CRANEBOARD
 CONFIG_MACH_CRUX
 CONFIG_MACH_CSB337
 CONFIG_MACH_CSB637
 CONFIG_MACH_CSB726
 CONFIG_MACH_CSC
 CONFIG_MACH_CTBU_GEN2
 CONFIG_MACH_CTERA_PLUG_C2
 CONFIG_MACH_CURACAO
 CONFIG_MACH_CV2201
 CONFIG_MACH_CV2202
 CONFIG_MACH_CV2203
 CONFIG_MACH_CWAM1808
 CONFIG_MACH_CWDM365
 CONFIG_MACH_CWME9210
 CONFIG_MACH_CWME9210JS
 CONFIG_MACH_CWMX233
 CONFIG_MACH_D2NET
 CONFIG_MACH_D2NET_V2
 CONFIG_MACH_D2PLUG
 CONFIG_MACH_DA850_K5
 CONFIG_MACH_DAINTREE_CWAC
 CONFIG_MACH_DATAWAY
 CONFIG_MACH_DAVINCI_CALIMAIN
 CONFIG_MACH_DAVINCI_DA830_EVM
 CONFIG_MACH_DAVINCI_DA850_EVM
 CONFIG_MACH_DAVINCI_DM355_EVM
 CONFIG_MACH_DAVINCI_DM355_MMM
 CONFIG_MACH_DAVINCI_DM365_BV
 CONFIG_MACH_DAVINCI_DM365_DVR
 CONFIG_MACH_DAVINCI_DM365_EVM
 CONFIG_MACH_DAVINCI_DM6467TEVM
 CONFIG_MACH_DAVINCI_DM6467_EVM
 CONFIG_MACH_DAVINCI_EVM
 CONFIG_MACH_DAVINCI_PICTO
 CONFIG_MACH_DAWAD7
 CONFIG_MACH_DB78X00_BP
 CONFIG_MACH_DB88F5281
 CONFIG_MACH_DB88F6281_BP
 CONFIG_MACH_DDNAS
 CONFIG_MACH_DDPLUG
 CONFIG_MACH_DDS
 CONFIG_MACH_DEEP_R_EK_1
 CONFIG_MACH_DEVIXP
 CONFIG_MACH_DEVKIT8000
 CONFIG_MACH_DGM3240
 CONFIG_MACH_DIMMSAM9G20
 CONFIG_MACH_DIMM_IMX28
 CONFIG_MACH_DIMM_MX257
 CONFIG_MACH_DINGO
 CONFIG_MACH_DIR665
 CONFIG_MACH_DM355_LEOPARD
 CONFIG_MACH_DM365_CV100
 CONFIG_MACH_DM368_LEOPARD
 CONFIG_MACH_DM3730_SOM_LV
 CONFIG_MACH_DM3730_TORPEDO
 CONFIG_MACH_DM6441_ESP
 CONFIG_MACH_DM6446_ADBOX
 CONFIG_MACH_DMA6410
 CONFIG_MACH_DMA_THUNDERBUG
 CONFIG_MACH_DMW96
 CONFIG_MACH_DNS323
 CONFIG_MACH_DOCKSTAR
 CONFIG_MACH_DOORBOY
 CONFIG_MACH_DOUBLESHOT
 CONFIG_MACH_DOVE_AVNG_V3
 CONFIG_MACH_DOVE_DB
 CONFIG_MACH_DP6XX
 CONFIG_MACH_DRAGONET
 CONFIG_MACH_DSM320
 CONFIG_MACH_DSMG600
 CONFIG_MACH_DURIAN
 CONFIG_MACH_DYNASTY
 CONFIG_MACH_E10
 CONFIG_MACH_E330
 CONFIG_MACH_E350
 CONFIG_MACH_E400
 CONFIG_MACH_E740
 CONFIG_MACH_E750
 CONFIG_MACH_E800
 CONFIG_MACH_EA20
 CONFIG_MACH_EA2478DEVKIT
 CONFIG_MACH_EAG_CI4000
 CONFIG_MACH_EASYCRRH
 CONFIG_MACH_EC4350SDB
 CONFIG_MACH_EC4350TBM
 CONFIG_MACH_ECBAT91
 CONFIG_MACH_ECO920
 CONFIG_MACH_ECUV5
 CONFIG_MACH_EDB9301
 CONFIG_MACH_EDB9302
 CONFIG_MACH_EDB9302A
 CONFIG_MACH_EDB9307
 CONFIG_MACH_EDB9307A
 CONFIG_MACH_EDB9312
 CONFIG_MACH_EDB9315
 CONFIG_MACH_EDB9315A
 CONFIG_MACH_EDISON
 CONFIG_MACH_EDMINIV2
 CONFIG_MACH_EDMINI_V2
 CONFIG_MACH_EELX2
 CONFIG_MACH_EIGEN_TTR
 CONFIG_MACH_ELEPHANT
 CONFIG_MACH_ELKE
 CONFIG_MACH_ELOG
 CONFIG_MACH_EM1SY
 CONFIG_MACH_EM7210
 CONFIG_MACH_EMERALD
 CONFIG_MACH_EM_X270
 CONFIG_MACH_ENCORE
 CONFIG_MACH_ENDIAN_MINI
 CONFIG_MACH_EP80219
 CONFIG_MACH_EPC10
 CONFIG_MACH_EPIPHAN
 CONFIG_MACH_ES2440
 CONFIG_MACH_ESATA_SHEEVAPLUG
 CONFIG_MACH_ESL_MOBILIS_A
 CONFIG_MACH_ESL_MOBILIS_B
 CONFIG_MACH_ESL_WAVE_A
 CONFIG_MACH_ESL_WAVE_B
 CONFIG_MACH_ESPRESSO
 CONFIG_MACH_ETHERPRO_ISP
 CONFIG_MACH_ETNA
 CONFIG_MACH_EUKREA_CPUIMX25SD
 CONFIG_MACH_EUKREA_CPUIMX35SD
 CONFIG_MACH_EUKREA_CPUIMX51
 CONFIG_MACH_EUKREA_CPUIMX51SD
 CONFIG_MACH_EVA2000
 CONFIG_MACH_EVSY
 CONFIG_MACH_EXEDA
 CONFIG_MACH_EXPRESS
 CONFIG_MACH_EXPRESSCT
 CONFIG_MACH_EXPRESSH
 CONFIG_MACH_EXPRESS_KT
 CONFIG_MACH_EZX_A1200
 CONFIG_MACH_EZX_A780
 CONFIG_MACH_EZX_A910
 CONFIG_MACH_EZX_E2
 CONFIG_MACH_EZX_E6
 CONFIG_MACH_EZX_E680
 CONFIG_MACH_FA9X27
 CONFIG_MACH_FFCORE
 CONFIG_MACH_FLEXIBITY
 CONFIG_MACH_FLINT
 CONFIG_MACH_FLYER
 CONFIG_MACH_FRISMS
 CONFIG_MACH_FRRHWCDMA60W
 CONFIG_MACH_FSG
 CONFIG_MACH_FSM9XXX_FFA
 CONFIG_MACH_FSM9XXX_SURF
 CONFIG_MACH_FS_S5PC100
 CONFIG_MACH_FUJI
 CONFIG_MACH_FWBD_0404
 CONFIG_MACH_G3EVM
 CONFIG_MACH_G4EVM
 CONFIG_MACH_GATEWAY7001
 CONFIG_MACH_GENEVA_B5
 CONFIG_MACH_GESBC9312
 CONFIG_MACH_GFS_SPM
 CONFIG_MACH_GINGER
 CONFIG_MACH_GIRA_KNXIP_ROUTER
 CONFIG_MACH_GLANTANK
 CONFIG_MACH_GNET_SGCE
 CONFIG_MACH_GNET_SGME
 CONFIG_MACH_GNET_SLC
 CONFIG_MACH_GOFLEXHOME
 CONFIG_MACH_GOFLEXNET
 CONFIG_MACH_GOLDENGATE
 CONFIG_MACH_GONI
 CONFIG_MACH_GORAMO_MLR
 CONFIG_MACH_GPSDISPLAY
 CONFIG_MACH_GREECO
 CONFIG_MACH_GSIA18S
 CONFIG_MACH_GSL_DIAMOND
 CONFIG_MACH_GSNCOMM
 CONFIG_MACH_GTA04
 CONFIG_MACH_GTIB
 CONFIG_MACH_GTL_IT5100
 CONFIG_MACH_GTWX5715
 CONFIG_MACH_GT_I5700
 CONFIG_MACH_GUPPY
 CONFIG_MACH_GURNARD
 CONFIG_MACH_GURUPLUG
 CONFIG_MACH_GW2361
 CONFIG_MACH_H1600
 CONFIG_MACH_H4700
 CONFIG_MACH_HABA_KNX_EXPLORER
 CONFIG_MACH_HALIBUT
 CONFIG_MACH_HAMMERHEAD
 CONFIG_MACH_HARMONY
 CONFIG_MACH_HARVEST_DESOTO
 CONFIG_MACH_HAWKS
 CONFIG_MACH_HDGU
 CONFIG_MACH_HDMINI
 CONFIG_MACH_HDNVP
 CONFIG_MACH_HELIOS_V1
 CONFIG_MACH_HELIOS_V2
 CONFIG_MACH_HERALD
 CONFIG_MACH_HERRING
 CONFIG_MACH_HIMALAYA
 CONFIG_MACH_HJSDU
 CONFIG_MACH_HKDKC100
 CONFIG_MACH_HMT
 CONFIG_MACH_HOLIDAY
 CONFIG_MACH_HREFV60
 CONFIG_MACH_HSGX6D
 CONFIG_MACH_HTCMEGA
 CONFIG_MACH_HTCTORNADO
 CONFIG_MACH_HTC_HD_MINI
 CONFIG_MACH_HTC_SPV_M700
 CONFIG_MACH_HUASHAN
 CONFIG_MACH_HUSKY
 CONFIG_MACH_HWGW6410
 CONFIG_MACH_IAM28
 CONFIG_MACH_ICON
 CONFIG_MACH_ICONG
 CONFIG_MACH_ICONNECT
 CONFIG_MACH_ICONTROL
 CONFIG_MACH_ICON_G
 CONFIG_MACH_ICS_IF_VOIP
 CONFIG_MACH_IDEA6410
 CONFIG_MACH_IGEP0020
 CONFIG_MACH_IGEP0030
 CONFIG_MACH_IGEP0032
 CONFIG_MACH_IJ3K_2440
 CONFIG_MACH_IMATE8502
 CONFIG_MACH_IMX27IPCAM
 CONFIG_MACH_IMX27LITE
 CONFIG_MACH_IMX27_VISSTRIM_M10
 CONFIG_MACH_INCOME
 CONFIG_MACH_INETSPACE_V2
 CONFIG_MACH_INHAND_APEIRON
 CONFIG_MACH_INHAND_FURY
 CONFIG_MACH_INHAND_SIREN
 CONFIG_MACH_INTELMOTE2
 CONFIG_MACH_IOMEGA_IX2_200
 CONFIG_MACH_IQ80332
 CONFIG_MACH_IQ81340MC
 CONFIG_MACH_IQ81340SC
 CONFIG_MACH_ISC3
 CONFIG_MACH_IXDP2351
 CONFIG_MACH_IXDP28X5
 CONFIG_MACH_IXDP465
 CONFIG_MACH_IXDPG425
 CONFIG_MACH_JANUS
 CONFIG_MACH_JIGEN
 CONFIG_MACH_JIVE
 CONFIG_MACH_JOCPU550
 CONFIG_MACH_KAEN
 CONFIG_MACH_KAFA
 CONFIG_MACH_KB9200
 CONFIG_MACH_KEV7A400
 CONFIG_MACH_KINGDOM
 CONFIG_MACH_KIXRP435
 CONFIG_MACH_KMM2M01
 CONFIG_MACH_KMP_AM17_01
 CONFIG_MACH_KM_KIRKWOOD
 CONFIG_MACH_KOI
 CONFIG_MACH_KRONOS
 CONFIG_MACH_KT_SBC_SAM9_1
 CONFIG_MACH_KUROBOX_PRO
 CONFIG_MACH_KX33XX
 CONFIG_MACH_KZM9D
 CONFIG_MACH_KZM9G
 CONFIG_MACH_KZM_ARM11_01
 CONFIG_MACH_LANREADYFN511
 CONFIG_MACH_LAUSANNE
 CONFIG_MACH_LB88RC8480
 CONFIG_MACH_LEAD
 CONFIG_MACH_LEGACY
 CONFIG_MACH_LEMON
 CONFIG_MACH_LIBRA
 CONFIG_MACH_LIGHTNING
 CONFIG_MACH_LILLY1131
 CONFIG_MACH_LINKSTATION_CHLV2
 CONFIG_MACH_LINKSTATION_LSCHL
 CONFIG_MACH_LINKSTATION_LS_HGL
 CONFIG_MACH_LINKSTATION_MINI
 CONFIG_MACH_LINKSTATION_PRO
 CONFIG_MACH_LITTLETON
 CONFIG_MACH_LOFT
 CONFIG_MACH_LOGICPD_PXA270
 CONFIG_MACH_LPC24XX
 CONFIG_MACH_LPD7A400
 CONFIG_MACH_LPD7A404
 CONFIG_MACH_LQ2
 CONFIG_MACH_LS9G20
 CONFIG_MACH_LSWXL
 CONFIG_MACH_M502
 CONFIG_MACH_MACH_SDH001
 CONFIG_MACH_MACKEREL
 CONFIG_MACH_MAGICIAN
 CONFIG_MACH_MAGX_ZN5
 CONFIG_MACH_MAHIMAHI
 CONFIG_MACH_MAINSTONE
 CONFIG_MACH_MANUAE
 CONFIG_MACH_MAPLE1
 CONFIG_MACH_MARVEL
 CONFIG_MACH_MARVELC
 CONFIG_MACH_MARVELCT
 CONFIG_MACH_MARVELL_JASPER
 CONFIG_MACH_MATRIX505
 CONFIG_MACH_MATRIX518
 CONFIG_MACH_MAXIMASP
 CONFIG_MACH_MB3
 CONFIG_MACH_MECHA
 CONFIG_MACH_MENO_QNG
 CONFIG_MACH_MESON
 CONFIG_MACH_MESON_6236M
 CONFIG_MACH_MESON_8626M
 CONFIG_MACH_MESSINA
 CONFIG_MACH_MIC256
 CONFIG_MACH_MICCPT
 CONFIG_MACH_MICRO9
 CONFIG_MACH_MICRO9L
 CONFIG_MACH_MICRO9M
 CONFIG_MACH_MICRO9S
 CONFIG_MACH_MIF10P
 CONFIG_MACH_MIMAS
 CONFIG_MACH_MINI210
 CONFIG_MACH_MINI2440
 CONFIG_MACH_MINI6410
 CONFIG_MACH_MINI8168
 CONFIG_MACH_MIOA502
 CONFIG_MACH_MIOA701
 CONFIG_MACH_MIONE
 CONFIG_MACH_MIOS_V1
 CONFIG_MACH_MITYOMAPL138
 CONFIG_MACH_MMM
 CONFIG_MACH_MONCH
 CONFIG_MACH_MONE
 CONFIG_MACH_MOON
 CONFIG_MACH_MORA
 CONFIG_MACH_MR301A
 CONFIG_MACH_MSM7X25_FFA
 CONFIG_MACH_MSM7X25_SURF
 CONFIG_MACH_MSM7X27A_FFA
 CONFIG_MACH_MSM7X27A_RUMI3
 CONFIG_MACH_MSM7X27A_SURF
 CONFIG_MACH_MSM7X27_FFA
 CONFIG_MACH_MSM7X27_SURF
 CONFIG_MACH_MSM7X30_FFA
 CONFIG_MACH_MSM7X30_FLUID
 CONFIG_MACH_MSM7X30_SURF
 CONFIG_MACH_MSM8960_APQ
 CONFIG_MACH_MSM8960_CDP
 CONFIG_MACH_MSM8960_FLUID
 CONFIG_MACH_MSM8960_MDP
 CONFIG_MACH_MSM8960_RUMI3
 CONFIG_MACH_MSM8960_SIM
 CONFIG_MACH_MSM8X55_SVLTE_FFA
 CONFIG_MACH_MSM8X55_SVLTE_SURF
 CONFIG_MACH_MSM8X60_FFA
 CONFIG_MACH_MSM8X60_FLUID
 CONFIG_MACH_MSM8X60_QRDC
 CONFIG_MACH_MSM8X60_QT
 CONFIG_MACH_MSM8X60_RUMI3
 CONFIG_MACH_MSM8X60_SIM
 CONFIG_MACH_MSM8X60_SURF
 CONFIG_MACH_MSS2
 CONFIG_MACH_MULTHSU
 CONFIG_MACH_MV2120
 CONFIG_MACH_MV88F6281GTW_GE
 CONFIG_MACH_MVBLX
 CONFIG_MACH_MX21ADS
 CONFIG_MACH_MX23EVK
 CONFIG_MACH_MX257SOL
 CONFIG_MACH_MX257SX
 CONFIG_MACH_MX25_3DS
 CONFIG_MACH_MX25_E2S_UC
 CONFIG_MACH_MX27ADS
 CONFIG_MACH_MX27SU2
 CONFIG_MACH_MX27_3DS
 CONFIG_MACH_MX27_WMULTRA
 CONFIG_MACH_MX28EVK
 CONFIG_MACH_MX31ADS
 CONFIG_MACH_MX31LITE
 CONFIG_MACH_MX31MOBOARD
 CONFIG_MACH_MX31_3DS
 CONFIG_MACH_MX35_3DS
 CONFIG_MACH_MX50_ARM2
 CONFIG_MACH_MX50_RDP
 CONFIG_MACH_MX51EREBUS
 CONFIG_MACH_MX51_3DS
 CONFIG_MACH_MX51_ASTER7
 CONFIG_MACH_MX51_BABBAGE
 CONFIG_MACH_MX51_BRAVO
 CONFIG_MACH_MX51_EFIKAMX
 CONFIG_MACH_MX51_EFIKASB
 CONFIG_MACH_MX51_GGC
 CONFIG_MACH_MX51_MORAY
 CONFIG_MACH_MX51_TULIP
 CONFIG_MACH_MX53_ARD
 CONFIG_MACH_MX53_EVK
 CONFIG_MACH_MX53_LOCO
 CONFIG_MACH_MX53_SMD
 CONFIG_MACH_MX61_ARD
 CONFIG_MACH_MXC25_TOPAZ
 CONFIG_MACH_MXLADS
 CONFIG_MACH_MXT_TD60
 CONFIG_MACH_MXT_TD61
 CONFIG_MACH_N2100
 CONFIG_MACH_N30
 CONFIG_MACH_N35
 CONFIG_MACH_NAJAY_A9263
 CONFIG_MACH_NANOS
 CONFIG_MACH_NANOZOOM
 CONFIG_MACH_NAS100D
 CONFIG_MACH_NAS4220B
 CONFIG_MACH_NAS6210
 CONFIG_MACH_NAVEFIHID
 CONFIG_MACH_NAXY1200
 CONFIG_MACH_NAXY400
 CONFIG_MACH_NB31
 CONFIG_MACH_NCP
 CONFIG_MACH_NDA_EVM
 CONFIG_MACH_NEC_MP900
 CONFIG_MACH_NEO1973_GTA02
 CONFIG_MACH_NEOCORE926
 CONFIG_MACH_NERY_1000
 CONFIG_MACH_NET2BIG
 CONFIG_MACH_NET2BIG_NAND_V2
 CONFIG_MACH_NET2BIG_V2
 CONFIG_MACH_NET5BIG_NAND_V2
 CONFIG_MACH_NET5BIG_V2
 CONFIG_MACH_NETSPACE_LITE_V2
 CONFIG_MACH_NETSPACE_MAX_V2
 CONFIG_MACH_NETSPACE_V2
 CONFIG_MACH_NETVIZ
 CONFIG_MACH_NETWALKER
 CONFIG_MACH_NEUROS_OSD2
 CONFIG_MACH_NEXCODER_2440
 CONFIG_MACH_NITROGEN_IMX51
 CONFIG_MACH_NITROGEN_IMX53
 CONFIG_MACH_NITROGEN_VM_IMX51
 CONFIG_MACH_NMH
 CONFIG_MACH_NOKIA770
 CONFIG_MACH_NOKIA_N800
 CONFIG_MACH_NOKIA_N810
 CONFIG_MACH_NOKIA_N810_WIMAX
 CONFIG_MACH_NOKIA_RM680
 CONFIG_MACH_NOKIA_RX51
 CONFIG_MACH_NOMADIK
 CONFIG_MACH_NOTLE
 CONFIG_MACH_NS2416
 CONFIG_MACH_NS2816TB
 CONFIG_MACH_NS2816_NTNB
 CONFIG_MACH_NS2816_NTPAD
 CONFIG_MACH_NSB3AST
 CONFIG_MACH_NSK330
 CONFIG_MACH_NSLU2
 CONFIG_MACH_NSSLSBOARD
 CONFIG_MACH_NS_K330
 CONFIG_MACH_NUC700EVB
 CONFIG_MACH_NUC710EVB
 CONFIG_MACH_NUC740EVB
 CONFIG_MACH_NUC745EVB
 CONFIG_MACH_NUC932EVB
 CONFIG_MACH_NUC950TS
 CONFIG_MACH_NURI
 CONFIG_MACH_NV1000
 CONFIG_MACH_NXDB500
 CONFIG_MACH_NXDKN
 CONFIG_MACH_NXEB500HMI
 CONFIG_MACH_OCE_NIGMA
 CONFIG_MACH_OMAP2EVM
 CONFIG_MACH_OMAP3505NOVA8
 CONFIG_MACH_OMAP3517EVM
 CONFIG_MACH_OMAP3530_LV_SOM
 CONFIG_MACH_OMAP3621_EDP1
 CONFIG_MACH_OMAP3EVM
 CONFIG_MACH_OMAP3SMARTDISPLAY
 CONFIG_MACH_OMAP3_BAIA
 CONFIG_MACH_OMAP3_BC10
 CONFIG_MACH_OMAP3_BEAGLE
 CONFIG_MACH_OMAP3_BRAILLO
 CONFIG_MACH_OMAP3_IBIZA
 CONFIG_MACH_OMAP3_PANDORA
 CONFIG_MACH_OMAP3_RFS200
 CONFIG_MACH_OMAP3_TDM3730
 CONFIG_MACH_OMAP3_TORPEDO
 CONFIG_MACH_OMAP3_WALDO1
 CONFIG_MACH_OMAP4_PANDA
 CONFIG_MACH_OMAP5_SEVM
 CONFIG_MACH_OMAPL138_CASE_A3
 CONFIG_MACH_OMAPL138_EUROPALC
 CONFIG_MACH_OMAPL138_HAWKBOARD
 CONFIG_MACH_OMAPL138_LCDK
 CONFIG_MACH_OMAP_2430SDP
 CONFIG_MACH_OMAP_3430SDP
 CONFIG_MACH_OMAP_3630SDP
 CONFIG_MACH_OMAP_4430SDP
 CONFIG_MACH_OMAP_APOLLON
 CONFIG_MACH_OMAP_BENDER
 CONFIG_MACH_OMAP_FSAMPLE
 CONFIG_MACH_OMAP_GENERIC
 CONFIG_MACH_OMAP_H2
 CONFIG_MACH_OMAP_H3
 CONFIG_MACH_OMAP_H4
 CONFIG_MACH_OMAP_INNOVATOR
 CONFIG_MACH_OMAP_LDP
 CONFIG_MACH_OMAP_MCOP
 CONFIG_MACH_OMAP_OSK
 CONFIG_MACH_OMAP_PALMTE
 CONFIG_MACH_OMAP_PALMTT
 CONFIG_MACH_OMAP_PALMZ71
 CONFIG_MACH_OMAP_PERSEUS2
 CONFIG_MACH_OMAP_ZOOM2
 CONFIG_MACH_OMAP_ZOOM3
 CONFIG_MACH_OMN_AT91SAM9G20
 CONFIG_MACH_ONEARM
 CONFIG_MACH_OPENRD_BASE
 CONFIG_MACH_OPENRD_CLIENT
 CONFIG_MACH_OPENRD_ULTIMATE
 CONFIG_MACH_ORATISAES
 CONFIG_MACH_ORATISLINK
 CONFIG_MACH_ORIGEN
 CONFIG_MACH_OSIRIS
 CONFIG_MACH_OSLO_AMUNDSEN
 CONFIG_MACH_OTOM
 CONFIG_MACH_OVERO
 CONFIG_MACH_OVERO_CTU_INERTIAL
 CONFIG_MACH_P87_SMARTSIM
 CONFIG_MACH_PALMLD
 CONFIG_MACH_PALMT5
 CONFIG_MACH_PALMTC
 CONFIG_MACH_PALMTE2
 CONFIG_MACH_PALMTX
 CONFIG_MACH_PALMZ72
 CONFIG_MACH_PAZ00
 CONFIG_MACH_PC7302
 CONFIG_MACH_PC7308
 CONFIG_MACH_PC9260_V2
 CONFIG_MACH_PCA100
 CONFIG_MACH_PCA102
 CONFIG_MACH_PCATS_OVERLAY
 CONFIG_MACH_PCM027
 CONFIG_MACH_PCM037
 CONFIG_MACH_PCM038
 CONFIG_MACH_PCM043
 CONFIG_MACH_PCM048
 CONFIG_MACH_PCM049
 CONFIG_MACH_PCONTROL_G20
 CONFIG_MACH_PEC_HC2
 CONFIG_MACH_PEC_TC
 CONFIG_MACH_PEMP_OMAP3_APOLLO
 CONFIG_MACH_PGS_SITARA
 CONFIG_MACH_PHILHWANI
 CONFIG_MACH_PHY3250
 CONFIG_MACH_PICASSO
 CONFIG_MACH_PICO
 CONFIG_MACH_PICOCOM3
 CONFIG_MACH_PICOCOM4
 CONFIG_MACH_PICOTUX2XX
 CONFIG_MACH_PIVICC
 CONFIG_MACH_PNX4008
 CONFIG_MACH_POLYSAT1
 CONFIG_MACH_POODLE
 CONFIG_MACH_PORTUXG20
 CONFIG_MACH_POV15HD
 CONFIG_MACH_PREMIERWAVE_EN
 CONFIG_MACH_PRIMA2_EVB
 CONFIG_MACH_PTX7510
 CONFIG_MACH_PTX7545
 CONFIG_MACH_PUNICA
 CONFIG_MACH_PUPITRE
 CONFIG_MACH_PVM2030
 CONFIG_MACH_PWB3090
 CONFIG_MACH_PXWNAS_500_1000
 CONFIG_MACH_PYRAMID
 CONFIG_MACH_QBC9263
 CONFIG_MACH_QIL_A9260
 CONFIG_MACH_QONG
 CONFIG_MACH_QSD8X50A_ST1_5
 CONFIG_MACH_QSD8X50_SURF
 CONFIG_MACH_QSD8X72_FFA
 CONFIG_MACH_QSD8X72_SURF
 CONFIG_MACH_QT2410
 CONFIG_MACH_QUAD_SALSA
 CONFIG_MACH_QUICKSTEP
 CONFIG_MACH_R1801E
 CONFIG_MACH_RASCAL
 CONFIG_MACH_RAUMFELD_CONNECTOR
 CONFIG_MACH_RAUMFELD_RC
 CONFIG_MACH_RAUMFELD_SPEAKER
 CONFIG_MACH_RD78X00_MASA
 CONFIG_MACH_RD88F5181L_FXO
 CONFIG_MACH_RD88F5181L_GE
 CONFIG_MACH_RD88F5182
 CONFIG_MACH_RD88F6183AP_GE
 CONFIG_MACH_RD88F6192_NAS
 CONFIG_MACH_RD88F6281
 CONFIG_MACH_RDSTOR
 CONFIG_MACH_RE2REV20
 CONFIG_MACH_RE2REV21
 CONFIG_MACH_REAL6410
 CONFIG_MACH_REALVIEW_EB
 CONFIG_MACH_REALVIEW_PB1176
 CONFIG_MACH_REALVIEW_PB11MP
 CONFIG_MACH_REALVIEW_PBA8
 CONFIG_MACH_REALVIEW_PBX
 CONFIG_MACH_REMUS
 CONFIG_MACH_REXMAS
 CONFIG_MACH_RFL109145_SSRV
 CONFIG_MACH_RHINO
 CONFIG_MACH_RIB
 CONFIG_MACH_RIDER
 CONFIG_MACH_RIOT_BEI2
 CONFIG_MACH_RIOT_X37
 CONFIG_MACH_ROADRUNNER
 CONFIG_MACH_ROCKHOPPER
 CONFIG_MACH_ROVERPCS8
 CONFIG_MACH_ROVERX7
 CONFIG_MACH_ROVER_G8
 CONFIG_MACH_RPC353
 CONFIG_MACH_RUBY
 CONFIG_MACH_RUBYS
 CONFIG_MACH_RUMP
 CONFIG_MACH_RUT100
 CONFIG_MACH_RV082
 CONFIG_MACH_RX1950
 CONFIG_MACH_RX3715
 CONFIG_MACH_S3C2413
 CONFIG_MACH_S5500
 CONFIG_MACH_S5PC110_CRESPO
 CONFIG_MACH_SAAR
 CONFIG_MACH_SAARB
 CONFIG_MACH_SAARB_MG1
 CONFIG_MACH_SAGA
 CONFIG_MACH_SALUDA
 CONFIG_MACH_SAM9REPEATER
 CONFIG_MACH_SAM9_L9260
 CONFIG_MACH_SANTIAGO
 CONFIG_MACH_SAPPHIRE
 CONFIG_MACH_SBC3530
 CONFIG_MACH_SBC6000X
 CONFIG_MACH_SBCA11
 CONFIG_MACH_SC575IPC
 CONFIG_MACH_SC575PLC
 CONFIG_MACH_SCB9328
 CONFIG_MACH_SCIPHONE_G2
 CONFIG_MACH_SDI_ESS_9263
 CONFIG_MACH_SDVR
 CONFIG_MACH_SEABOARD
 CONFIG_MACH_SERRANO
 CONFIG_MACH_SFFSDR
 CONFIG_MACH_SGH_I740
 CONFIG_MACH_SHARESPACE
 CONFIG_MACH_SHEEVAPLUG
 CONFIG_MACH_SHENZHOU
 CONFIG_MACH_SHEPHERD
 CONFIG_MACH_SHOOTER
 CONFIG_MACH_SHOOTER_CT
 CONFIG_MACH_SHOOTER_U
 CONFIG_MACH_SHORTLOIN
 CONFIG_MACH_SIEMENS_L0
 CONFIG_MACH_SIMPLENET
 CONFIG_MACH_SIMTEC_KIRKMOD
 CONFIG_MACH_SIM_ONE
 CONFIG_MACH_SKY25
 CONFIG_MACH_SKY6410
 CONFIG_MACH_SM1K
 CONFIG_MACH_SMARTQ5
 CONFIG_MACH_SMARTQ7
 CONFIG_MACH_SMARTQV3
 CONFIG_MACH_SMARTQV5
 CONFIG_MACH_SMARTQV7
 CONFIG_MACH_SMDK2412
 CONFIG_MACH_SMDK2413
 CONFIG_MACH_SMDK2416
 CONFIG_MACH_SMDK2443
 CONFIG_MACH_SMDK6410
 CONFIG_MACH_SMDK6440
 CONFIG_MACH_SMDK6442
 CONFIG_MACH_SMDK6450
 CONFIG_MACH_SMDKC100
 CONFIG_MACH_SMDKC110
 CONFIG_MACH_SMDKC210
 CONFIG_MACH_SMDKV210
 CONFIG_MACH_SMDKV310
 CONFIG_MACH_SNAPPER_9260
 CONFIG_MACH_SNAPPER_CL15
 CONFIG_MACH_SOFTWINNER
 CONFIG_MACH_SOLI_01
 CONFIG_MACH_SPADE
 CONFIG_MACH_SPADE_LTE
 CONFIG_MACH_SPDM
 CONFIG_MACH_SPEAR1310
 CONFIG_MACH_SPEAR1340
 CONFIG_MACH_SPEAR300
 CONFIG_MACH_SPEAR310
 CONFIG_MACH_SPEAR320
 CONFIG_MACH_SPEAR600
 CONFIG_MACH_SPEAR900
 CONFIG_MACH_SPECIFIC
 CONFIG_MACH_SPICA
 CONFIG_MACH_SPITZ
 CONFIG_MACH_SPLENDOR
 CONFIG_MACH_SPX_SAKURA
 CONFIG_MACH_SPYPLUG
 CONFIG_MACH_SSC
 CONFIG_MACH_STAMP9G20
 CONFIG_MACH_STAMP9G45
 CONFIG_MACH_STARGATE2
 CONFIG_MACH_STEELYARD
 CONFIG_MACH_STELLA
 CONFIG_MACH_STMP378X
 CONFIG_MACH_STMP37XX
 CONFIG_MACH_STRASBOURG
 CONFIG_MACH_STRASBOURG_A2
 CONFIG_MACH_STRETCHS7000
 CONFIG_MACH_SUNFIRE
 CONFIG_MACH_SUNFLOWER
 CONFIG_MACH_SVCID
 CONFIG_MACH_SVP5500
 CONFIG_MACH_SVP8500V1
 CONFIG_MACH_SVP8500V2
 CONFIG_MACH_SWARCOEXTMODEM
 CONFIG_MACH_SWEDA_TMS2
 CONFIG_MACH_SX1
 CONFIG_MACH_SYNERGY
 CONFIG_MACH_SYNOLOGY_6282
 CONFIG_MACH_T20
 CONFIG_MACH_T5325
 CONFIG_MACH_T5388P
 CONFIG_MACH_T55
 CONFIG_MACH_TAG
 CONFIG_MACH_TAGW
 CONFIG_MACH_TANNA
 CONFIG_MACH_TAVOREVB
 CONFIG_MACH_TAVOREVB3
 CONFIG_MACH_TCC8000_SDK
 CONFIG_MACH_TCT_HAMMER
 CONFIG_MACH_TD3_REV1
 CONFIG_MACH_TEENOTE
 CONFIG_MACH_TEGRA_DAYTONA
 CONFIG_MACH_TEGRA_E1165
 CONFIG_MACH_TEGRA_SWORDFISH
 CONFIG_MACH_TEGRA_VOGUE
 CONFIG_MACH_TEM3X30
 CONFIG_MACH_TENDERLOIN
 CONFIG_MACH_TERASTATION_PRO2
 CONFIG_MACH_TERASTATION_WXL
 CONFIG_MACH_TERA_PRO2_RACK
 CONFIG_MACH_TETON_BGA
 CONFIG_MACH_THALES_ADC
 CONFIG_MACH_THALES_CBC
 CONFIG_MACH_THEBE
 CONFIG_MACH_TI8148EVM
 CONFIG_MACH_TI8168EVM
 CONFIG_MACH_TIMU
 CONFIG_MACH_TIN307
 CONFIG_MACH_TIN510
 CONFIG_MACH_TINY_GURNARD
 CONFIG_MACH_TITAN
 CONFIG_MACH_TJINC1000
 CONFIG_MACH_TM_EFDC
 CONFIG_MACH_TN200
 CONFIG_MACH_TNETV107X
 CONFIG_MACH_TNY_T3530
 CONFIG_MACH_TONGA2_TFTTIMER
 CONFIG_MACH_TOP9000
 CONFIG_MACH_TOP9000_BSL
 CONFIG_MACH_TOP9000_EVAL
 CONFIG_MACH_TOP9000_SU
 CONFIG_MACH_TOP9000_TCU
 CONFIG_MACH_TORBRECK
 CONFIG_MACH_TORNADO3240
 CONFIG_MACH_TOSA
 CONFIG_MACH_TOUCHBOOK
 CONFIG_MACH_TPT_2_0
 CONFIG_MACH_TQ6410
 CONFIG_MACH_TQMA35
 CONFIG_MACH_TQMA9263
 CONFIG_MACH_TRANSCEDE
 CONFIG_MACH_TREO680
 CONFIG_MACH_TRICORDER
 CONFIG_MACH_TRIDENT
 CONFIG_MACH_TRIMSLICE
 CONFIG_MACH_TRIPEL
 CONFIG_MACH_TRITIP
 CONFIG_MACH_TRIZEPS4
 CONFIG_MACH_TRIZEPS4WL
 CONFIG_MACH_TROUT
 CONFIG_MACH_TS209
 CONFIG_MACH_TS219
 CONFIG_MACH_TS3
 CONFIG_MACH_TS409
 CONFIG_MACH_TS41X
 CONFIG_MACH_TS42XX
 CONFIG_MACH_TS47XX
 CONFIG_MACH_TS4800
 CONFIG_MACH_TS48XX
 CONFIG_MACH_TS72XX
 CONFIG_MACH_TS75XX
 CONFIG_MACH_TS78XX
 CONFIG_MACH_TSOPLOADER
 CONFIG_MACH_TSUNAGI
 CONFIG_MACH_TTC_DKB
 CONFIG_MACH_TUBE
 CONFIG_MACH_TULIP
 CONFIG_MACH_TUNA
 CONFIG_MACH_TUXRAIL
 CONFIG_MACH_TX28
 CONFIG_MACH_TX53
 CONFIG_MACH_TYPE
 CONFIG_MACH_TYPE_COMPAT_REV
 CONFIG_MACH_U300
 CONFIG_MACH_U5500
 CONFIG_MACH_UBISYS_P9D_EVP
 CONFIG_MACH_UEMD
 CONFIG_MACH_UNINO1
 CONFIG_MACH_UNISDEV
 CONFIG_MACH_UNISENSE_MMM
 CONFIG_MACH_UNIT2S
 CONFIG_MACH_UNIVERSAL_C210
 CONFIG_MACH_USB_A9260
 CONFIG_MACH_USB_A9263
 CONFIG_MACH_USDLOADER
 CONFIG_MACH_UTM300
 CONFIG_MACH_VALDEZ
 CONFIG_MACH_VANGOGH
 CONFIG_MACH_VC0718
 CONFIG_MACH_VENTANA
 CONFIG_MACH_VERDI
 CONFIG_MACH_VERDI_LTE
 CONFIG_MACH_VERIDIS_A300
 CONFIG_MACH_VERSATILE_AB
 CONFIG_MACH_VEXPRESS
 CONFIG_MACH_VIGOR
 CONFIG_MACH_VIPRINET
 CONFIG_MACH_VIT_IBOX
 CONFIG_MACH_VIVO
 CONFIG_MACH_VIVOW_CT
 CONFIG_MACH_VMX25
 CONFIG_MACH_VMX51
 CONFIG_MACH_VMX53
 CONFIG_MACH_VOICEBLUE
 CONFIG_MACH_VPAC270
 CONFIG_MACH_VPR200
 CONFIG_MACH_VR1000
 CONFIG_MACH_VSTMS
 CONFIG_MACH_VVBOX_SDLITE2
 CONFIG_MACH_VVBOX_SDORIG2
 CONFIG_MACH_VVBOX_SDPRO4
 CONFIG_MACH_W21
 CONFIG_MACH_W90N960EVB
 CONFIG_MACH_W90P910EVB
 CONFIG_MACH_W90P950EVB
 CONFIG_MACH_WARIO
 CONFIG_MACH_WASABI
 CONFIG_MACH_WATSON_EFM_PLUGIN
 CONFIG_MACH_WB40N
 CONFIG_MACH_WBD111
 CONFIG_MACH_WBD222
 CONFIG_MACH_WG302V2
 CONFIG_MACH_WHISTLER
 CONFIG_MACH_WLAN_COMPUTER
 CONFIG_MACH_WLF_CRAGG_6410
 CONFIG_MACH_WM8505_7IN_NETBOOK
 CONFIG_MACH_WM8650REFBOARD
 CONFIG_MACH_WN802T
 CONFIG_MACH_WNR854T
 CONFIG_MACH_WRT350N_V2
 CONFIG_MACH_WTPLUG
 CONFIG_MACH_XARINA
 CONFIG_MACH_XCEP
 CONFIG_MACH_XILINX
 CONFIG_MACH_XILINX_EP107
 CONFIG_MACH_XSBASE255
 CONFIG_MACH_YANOMAMI
 CONFIG_MACH_YL9200
 CONFIG_MACH_Z3_814X_MOD
 CONFIG_MACH_Z3_816X_MOD
 CONFIG_MACH_ZIPIT2
 CONFIG_MACH_ZMX25
 CONFIG_MACH_ZYLONITE
 CONFIG_MACH_ZYLONITE2
 CONFIG_MACPWR
 CONFIG_MACRESET_TIMEOUT
 CONFIG_MAC_ADDR_IN_EEPROM
 CONFIG_MAC_ADDR_IN_SPIFLASH
 CONFIG_MAC_OFFSET
 CONFIG_MAC_PARTITION
 CONFIG_MAKALU
 CONFIG_MALLOC_F_ADDR
 CONFIG_MALTA
 CONFIG_MARCO_MEMSET
 CONFIG_MARUBUN_PCCARD
 CONFIG_MARVELL
 CONFIG_MARVELL_GPIO
 CONFIG_MARVELL_MFP
 CONFIG_MASK_AER_AO
 CONFIG_MAX_DSP_CPUS
 CONFIG_MAX_FPGA_DEVICES
 CONFIG_MAX_I2C_NUM
 CONFIG_MAX_MEM_MAPPED
 CONFIG_MAX_PKT
 CONFIG_MAX_RAM_BANK_SIZE
 CONFIG_MCAST_TFTP
 CONFIG_MCF5249
 CONFIG_MCF5253
 CONFIG_MCFFEC
 CONFIG_MCFPIT
 CONFIG_MCFRTC
 CONFIG_MCFTMR
 CONFIG_MCFUART
 CONFIG_MCLK_DIS
 CONFIG_MD5
 CONFIG_MD5SUM_VERIFY
 CONFIG_MDIO_TIMEOUT
 CONFIG_MECP5123
 CONFIG_MEMSIZE
 CONFIG_MEMSIZE_IN_BYTES
 CONFIG_MEMSIZE_MASK
 CONFIG_MEM_ADD_WDTH
 CONFIG_MEM_HOLE_16M
 CONFIG_MEM_INIT_VALUE
 CONFIG_MEM_REMAP
 CONFIG_MEM_SIZE
 CONFIG_MENU
 CONFIG_MENUKEY
 CONFIG_MENUPROMPT
 CONFIG_MENU_SHOW
 CONFIG_MFG_ENV_SETTINGS
 CONFIG_MGCOGE
 CONFIG_MGCOGE3NE
 CONFIG_MIGO_R
 CONFIG_MII
 CONFIG_MIIM_ADDRESS
 CONFIG_MII_DEFAULT_TSEC
 CONFIG_MII_INIT
 CONFIG_MII_SUPPRESS_PREAMBLE
 CONFIG_MINIFAP
 CONFIG_MIPS_HUGE_TLB_SUPPORT
 CONFIG_MIPS_MT_FPAFF
 CONFIG_MIRQ_EN
 CONFIG_MISC_COMMON
 CONFIG_MISC_INIT_F
 CONFIG_MISC_INIT_R
 CONFIG_MIU_1BIT_INTERLEAVED
 CONFIG_MIU_2BIT_21_7_INTERLEAVED
 CONFIG_MIU_2BIT_INTERLEAVED
 CONFIG_MIU_LINEAR
 CONFIG_MK_edb9301
 CONFIG_MK_edb9315a
 CONFIG_MMCBOOTCOMMAND
 CONFIG_MMCROOT
 CONFIG_MMC_DEFAULT_DEV
 CONFIG_MMC_RPMB_TRACE
 CONFIG_MMC_SDHCI_IO_ACCESSORS
 CONFIG_MMC_SDMA
 CONFIG_MMC_SPI
 CONFIG_MMC_SPI_BUS
 CONFIG_MMC_SPI_CRC_ON
 CONFIG_MMC_SPI_CS
 CONFIG_MMC_SPI_CS_EPGIO
 CONFIG_MMC_SPI_MODE
 CONFIG_MMC_SPI_NPOWER_EGPIO
 CONFIG_MMC_SPI_POWER_EGPIO
 CONFIG_MMC_SPI_SPEED
 CONFIG_MMC_SUNXI
 CONFIG_MMC_SUNXI_SLOT
 CONFIG_MMC_TRACE
 CONFIG_MMU
 CONFIG_MODVERSIONS
 CONFIG_MONITOR_IS_IN_RAM
 CONFIG_MOTIONPRO
 CONFIG_MP
 CONFIG_MPC5121ADS
 CONFIG_MPC5121ADS_REV2
 CONFIG_MPC512x_FEC
 CONFIG_MPC5200
 CONFIG_MPC5200_DDR
 CONFIG_MPC52XX_SPI
 CONFIG_MPC555
 CONFIG_MPC5xxx_FEC
 CONFIG_MPC5xxx_FEC_MII10
 CONFIG_MPC5xxx_FEC_MII100
 CONFIG_MPC823
 CONFIG_MPC8247
 CONFIG_MPC8255
 CONFIG_MPC8272_FAMILY
 CONFIG_MPC8308
 CONFIG_MPC8308RDB
 CONFIG_MPC8308_P1M
 CONFIG_MPC8309
 CONFIG_MPC830x
 CONFIG_MPC8313
 CONFIG_MPC8313ERDB
 CONFIG_MPC8315
 CONFIG_MPC8315ERDB
 CONFIG_MPC831x
 CONFIG_MPC832XEMDS
 CONFIG_MPC832x
 CONFIG_MPC8349
 CONFIG_MPC8349EMDS
 CONFIG_MPC8349ITX
 CONFIG_MPC8349ITXGP
 CONFIG_MPC834x
 CONFIG_MPC8360
 CONFIG_MPC837XEMDS
 CONFIG_MPC837XERDB
 CONFIG_MPC837x
 CONFIG_MPC83XX_GPIO
 CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
 CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
 CONFIG_MPC83XX_GPIO_0_INIT_VALUE
 CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION
 CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN
 CONFIG_MPC83XX_GPIO_1_INIT_VALUE
 CONFIG_MPC83XX_PCI2
 CONFIG_MPC850
 CONFIG_MPC8536
 CONFIG_MPC8536DS
 CONFIG_MPC8540
 CONFIG_MPC8540ADS
 CONFIG_MPC8541
 CONFIG_MPC8541CDS
 CONFIG_MPC8544
 CONFIG_MPC8544DS
 CONFIG_MPC8548
 CONFIG_MPC8548CDS
 CONFIG_MPC855
 CONFIG_MPC8555
 CONFIG_MPC8555CDS
 CONFIG_MPC8560
 CONFIG_MPC8560ADS
 CONFIG_MPC8568
 CONFIG_MPC8568MDS
 CONFIG_MPC8569
 CONFIG_MPC8569MDS
 CONFIG_MPC857
 CONFIG_MPC8572
 CONFIG_MPC8572DS
 CONFIG_MPC85XX_FEC
 CONFIG_MPC85XX_FEC_NAME
 CONFIG_MPC85XX_PCI2
 CONFIG_MPC860
 CONFIG_MPC860T
 CONFIG_MPC8610
 CONFIG_MPC8610HPCD
 CONFIG_MPC862
 CONFIG_MPC8641
 CONFIG_MPC8641HPCN
 CONFIG_MPC866
 CONFIG_MPC866_FAMILY
 CONFIG_MPC86x
 CONFIG_MPC885
 CONFIG_MPC885_FAMILY
 CONFIG_MPC8XXX_SPI
 CONFIG_MPC8XX_LCD
 CONFIG_MPC8xxx_DISABLE_BPTR
 CONFIG_MPLL_FREQ
 CONFIG_MPR2
 CONFIG_MPX5200
 CONFIG_MP_CLK_FREQ
 CONFIG_MS7720SE
 CONFIG_MS7722SE
 CONFIG_MS7750SE
 CONFIG_MSHC_FREQ
 CONFIG_MTDMAP
 CONFIG_MTDPARTS
 CONFIG_MTD_CONCAT
 CONFIG_MTD_DEBUG
 CONFIG_MTD_DEBUG_VERBOSE
 CONFIG_MTD_DEVICE
 CONFIG_MTD_ECC_SOFT
 CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
 CONFIG_MTD_NAND_ECC_SMC
 CONFIG_MTD_NAND_MUSEUM_IDS
 CONFIG_MTD_NAND_VERIFY_WRITE
 CONFIG_MTD_ONENAND_VERIFY_WRITE
 CONFIG_MTD_PARTITION
 CONFIG_MTD_PARTITIONS
 CONFIG_MTD_UBI_BEB_RESERVE
 CONFIG_MTD_UBI_BLOCK
 CONFIG_MTD_UBI_DEBUG
 CONFIG_MTD_UBI_DEBUG_MSG
 CONFIG_MTD_UBI_DEBUG_MSG_BLD
 CONFIG_MTD_UBI_DEBUG_MSG_EBA
 CONFIG_MTD_UBI_DEBUG_MSG_IO
 CONFIG_MTD_UBI_DEBUG_MSG_WL
 CONFIG_MTD_UBI_DEBUG_PARANOID
 CONFIG_MTD_UBI_GLUEBI
 CONFIG_MTD_UBI_MODULE
 CONFIG_MULTI_CS
 CONFIG_MUNICES
 CONFIG_MUSB_HOST
 CONFIG_MV88E61XX_CPU_PORT
 CONFIG_MV88E61XX_PHY_PORTS
 CONFIG_MV88E61XX_SWITCH
 CONFIG_MV88E6352_SWITCH
 CONFIG_MVEBU_MMC
 CONFIG_MVGBE
 CONFIG_MVGBE_PORTS
 CONFIG_MVMFP_V2
 CONFIG_MVNETA
 CONFIG_MVS
 CONFIG_MVSATA_IDE
 CONFIG_MVSATA_IDE_USE_PORT0
 CONFIG_MVSATA_IDE_USE_PORT1
 CONFIG_MV_ETH_RXQ
 CONFIG_MV_I2C_NUM
 CONFIG_MV_I2C_REG
 CONFIG_MV_SDHCI
 CONFIG_MX23
 CONFIG_MX25
 CONFIG_MX25_CLK32
 CONFIG_MX25_HCLK_FREQ
 CONFIG_MX27
 CONFIG_MX27_CLK32
 CONFIG_MX27_TIMER_HIGH_PRECISION
 CONFIG_MX28
 CONFIG_MX28_FEC_MAC_IN_OCOTP
 CONFIG_MX31
 CONFIG_MX31_CLK32
 CONFIG_MX31_HCLK_FREQ
 CONFIG_MX35
 CONFIG_MX35_CLK32
 CONFIG_MX35_HCLK_FREQ
 CONFIG_MX6DL_LPDDR2
 CONFIG_MX6DQ_LPDDR2
 CONFIG_MX6SX_SABRESD_REVA
 CONFIG_MX6UL_14X14_EVK_EMMC_REWORK
 CONFIG_MXC_EPDC
 CONFIG_MXC_GPIO
 CONFIG_MXC_GPT_HCLK
 CONFIG_MXC_MCI_REGS_BASE
 CONFIG_MXC_MMC
 CONFIG_MXC_NAND_HWECC
 CONFIG_MXC_NAND_IP_REGS_BASE
 CONFIG_MXC_NAND_REGS_BASE
 CONFIG_MXC_SPI
 CONFIG_MXC_UART
 CONFIG_MXC_UART_BASE
 CONFIG_MXC_USB_FLAGS
 CONFIG_MXC_USB_PORT
 CONFIG_MXC_USB_PORTSC
 CONFIG_MXS
 CONFIG_MXS_AUART
 CONFIG_MXS_AUART_BASE
 CONFIG_MXS_GPIO
 CONFIG_MXS_MMC
 CONFIG_MXS_OCOTP
 CONFIG_MXS_SPI
 CONFIG_MX_CYCLIC
 CONFIG_MY_OPTION
 CONFIG_NAND
 CONFIG_NANDFLASH_SIZE
 CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 CONFIG_NAND_ACTL
 CONFIG_NAND_ATMEL
 CONFIG_NAND_CS_INIT
 CONFIG_NAND_DATA_REG
 CONFIG_NAND_DAVINCI
 CONFIG_NAND_DENALI_ECC_SIZE
 CONFIG_NAND_ECC_BCH
 CONFIG_NAND_ENV_DST
 CONFIG_NAND_FSL_ELBC
 CONFIG_NAND_FSL_IFC
 CONFIG_NAND_FSL_NFC
 CONFIG_NAND_FSMC
 CONFIG_NAND_KIRKWOOD
 CONFIG_NAND_KMETER1
 CONFIG_NAND_LPC32XX_MLC
 CONFIG_NAND_LPC32XX_SLC
 CONFIG_NAND_MODE_REG
 CONFIG_NAND_MPC5121_NFC
 CONFIG_NAND_MXC
 CONFIG_NAND_MXC_V1_1
 CONFIG_NAND_MXS
 CONFIG_NAND_NDFC
 CONFIG_NAND_OMAP_ECCSCHEME
 CONFIG_NAND_OMAP_ELM
 CONFIG_NAND_OMAP_GPMC
 CONFIG_NAND_OMAP_GPMC_PREFETCH
 CONFIG_NAND_OMAP_GPMC_WSCFG
 CONFIG_NAND_PLAT
 CONFIG_NAND_S3C2410
 CONFIG_NAND_SECBOOT
 CONFIG_NAND_SPL
 CONFIG_NAND_U_BOOT
 CONFIG_NATSEMI
 CONFIG_NB
 CONFIG_NCEL2C100_BASE
 CONFIG_NCEMIC100_BASE
 CONFIG_NDS_DLM1_BASE
 CONFIG_NDS_DLM2_BASE
 CONFIG_NEC_NL6448AC33
 CONFIG_NEC_NL6448BC20
 CONFIG_NEC_NL6448BC33_54
 CONFIG_NEEDS_MANUAL_RELOC
 CONFIG_NEO
 CONFIG_NET2BIG_V2
 CONFIG_NETCONSOLE_BUFFER_SIZE
 CONFIG_NETDEV
 CONFIG_NETMASK
 CONFIG_NETSPACE_LITE_V2
 CONFIG_NETSPACE_MAX_V2
 CONFIG_NETSPACE_MINI_V2
 CONFIG_NETSPACE_V2
 CONFIG_NET_MAXDEFRAG
 CONFIG_NET_MULTI
 CONFIG_NET_RETRY_COUNT
 CONFIG_NEVER_ASSERT_ODT_TO_CPU
 CONFIG_NFC_FREQ
 CONFIG_NFSBOOTCOMMAND
 CONFIG_NFS_READ_SIZE
 CONFIG_NFS_TIMEOUT
 CONFIG_NOBQFMAN
 CONFIG_NON_SECURE
 CONFIG_NORBOOT
 CONFIG_NORFLASH_PS32BIT
 CONFIG_NOT_SELECTED
 CONFIG_NO_ETH
 CONFIG_NO_RELOCATION
 CONFIG_NO_SERIAL_EEPROM
 CONFIG_NO_WAIT
 CONFIG_NR_CPUS
 CONFIG_NR_DRAM_BANKS
 CONFIG_NR_DRAM_BANKS_MAX
 CONFIG_NR_DRAM_POPULATED
 CONFIG_NS16550_MIN_FUNCTIONS
 CONFIG_NS8382X
 CONFIG_NS87308
 CONFIG_NUM_DDR_CONTROLLERS
 CONFIG_NUM_DSP_CPUS
 CONFIG_NUM_PAMU
 CONFIG_OCLK_DIV
 CONFIG_ODROID_REV_AIN
 CONFIG_OFF_PADCONF
 CONFIG_OF_
 CONFIG_OF_IDE_FIXUP
 CONFIG_OF_PLATDATA
 CONFIG_OF_SPI
 CONFIG_OF_SPI_FLASH
 CONFIG_OF_STDOUT_PATH
 CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
 CONFIG_OMAP
 CONFIG_OMAP3430
 CONFIG_OMAP3_AM3517CRANE
 CONFIG_OMAP3_DEVKIT8000
 CONFIG_OMAP3_EVM
 CONFIG_OMAP3_GPIO_2
 CONFIG_OMAP3_GPIO_3
 CONFIG_OMAP3_GPIO_4
 CONFIG_OMAP3_GPIO_5
 CONFIG_OMAP3_GPIO_6
 CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID
 CONFIG_OMAP3_MCX
 CONFIG_OMAP3_MICRON_DDR
 CONFIG_OMAP3_RX51
 CONFIG_OMAP3_SPI_D0_D1_SWAPPED
 CONFIG_OMAP3_ZOOM1
 CONFIG_OMAP4430
 CONFIG_OMAP54X
 CONFIG_OMAP_COMMON
 CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
 CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
 CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
 CONFIG_OMAP_GPIO
 CONFIG_OMAP_HSMMC
 CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
 CONFIG_OMAP_USB2PHY2_HOST
 CONFIG_OMAP_USB3PHY1_HOST
 CONFIG_OMAP_USB_PHY
 CONFIG_OMAP_VC_I2C_HS_MCODE
 CONFIG_OMAP_WATCHDOG
 CONFIG_OPTREX_BW
 CONFIG_ORIGEN
 CONFIG_OS1_ENV_ADDR
 CONFIG_OS2_ENV_ADDR
 CONFIG_OS_ENV_ADDR
 CONFIG_OTHBOOTARGS
 CONFIG_OVERWRITE_ETHADDR_ONCE
 CONFIG_P1010
 CONFIG_P1010RDB_PA
 CONFIG_P1010RDB_PB
 CONFIG_P1020
 CONFIG_P1020MBG
 CONFIG_P1020RDB_PC
 CONFIG_P1020RDB_PD
 CONFIG_P1020UTM
 CONFIG_P1021
 CONFIG_P1021RDB
 CONFIG_P1022
 CONFIG_P1022DS
 CONFIG_P1023
 CONFIG_P1024
 CONFIG_P1024RDB
 CONFIG_P1025
 CONFIG_P1025RDB
 CONFIG_P2020
 CONFIG_P2020RDB
 CONFIG_P2041RDB
 CONFIG_P3041DS
 CONFIG_P4080DS
 CONFIG_P5020DS
 CONFIG_P5040DS
 CONFIG_PAGE_CNT_MASK
 CONFIG_PAGE_CNT_SHIFT
 CONFIG_PALMAS_AUDPWR
 CONFIG_PALMAS_POWER
 CONFIG_PALMAS_SMPS7_FPWM
 CONFIG_PALMAS_USB_SS_PWR
 CONFIG_PANIC_HANG
 CONFIG_PARAVIRT
 CONFIG_PARTITIONS
 CONFIG_PARTITION_TYPE_GUID
 CONFIG_PARTITION_UUIDS
 CONFIG_PATA_BFIN
 CONFIG_PATI
 CONFIG_PB1000
 CONFIG_PB1100
 CONFIG_PB1500
 CONFIG_PB1X00
 CONFIG_PCA953X
 CONFIG_PCA9564_BASE
 CONFIG_PCA9564_I2C
 CONFIG_PCA9698
 CONFIG_PCI1
 CONFIG_PCI2
 CONFIG_PCIAUTO_SKIP_HOST_BRIDGE
 CONFIG_PCIE
 CONFIG_PCIE1
 CONFIG_PCIE2
 CONFIG_PCIE3
 CONFIG_PCIE4
 CONFIG_PCIE_IMX
 CONFIG_PCIE_IMX_PERST_GPIO
 CONFIG_PCIE_IMX_POWER_GPIO
 CONFIG_PCIE_LAYERSCAPE
 CONFIG_PCISLAVE
 CONFIG_PCIX_CHECK
 CONFIG_PCI_33M
 CONFIG_PCI_4xx_PTM_OVERWRITE
 CONFIG_PCI_66M
 CONFIG_PCI_BOOTDELAY
 CONFIG_PCI_CLK_FREQ
 CONFIG_PCI_CONFIG_HOST_BRIDGE
 CONFIG_PCI_DISABLE_PCIE
 CONFIG_PCI_EHCI_DEVICE
 CONFIG_PCI_EHCI_DEVNO
 CONFIG_PCI_ENUM_ONLY
 CONFIG_PCI_FIXUP_DEV
 CONFIG_PCI_GT64120
 CONFIG_PCI_HOST
 CONFIG_PCI_INDIRECT_BRIDGE
 CONFIG_PCI_IO_BUS
 CONFIG_PCI_IO_PHYS
 CONFIG_PCI_IO_SIZE
 CONFIG_PCI_MEMORY_BUS
 CONFIG_PCI_MEMORY_PHYS
 CONFIG_PCI_MEMORY_SIZE
 CONFIG_PCI_MEM_BUS
 CONFIG_PCI_MEM_PHYS
 CONFIG_PCI_MEM_SIZE
 CONFIG_PCI_MSC01
 CONFIG_PCI_MVEBU
 CONFIG_PCI_NOSCAN
 CONFIG_PCI_OHCI
 CONFIG_PCI_OHCI_DEVNO
 CONFIG_PCI_PNP
 CONFIG_PCI_PREF_BUS
 CONFIG_PCI_PREF_PHYS
 CONFIG_PCI_PREF_SIZE
 CONFIG_PCI_SCAN_SHOW
 CONFIG_PCI_SKIP_HOST_BRIDGE
 CONFIG_PCI_SYS_BUS
 CONFIG_PCI_SYS_MEM_BUS
 CONFIG_PCI_SYS_MEM_PHYS
 CONFIG_PCI_SYS_MEM_SIZE
 CONFIG_PCI_SYS_PHYS
 CONFIG_PCI_SYS_SIZE
 CONFIG_PCMCIA
 CONFIG_PCMCIA_SLOT_A
 CONFIG_PCMCIA_SLOT_B
 CONFIG_PCNET
 CONFIG_PCNET_79C973
 CONFIG_PCNET_79C975
 CONFIG_PDM360NG
 CONFIG_PDSP188x
 CONFIG_PEN_ADDR_BIG_ENDIAN
 CONFIG_PERIF1_FREQ
 CONFIG_PERIF2_FREQ
 CONFIG_PERIF3_FREQ
 CONFIG_PERIF4_FREQ
 CONFIG_PHY1_ADDR
 CONFIG_PHY2_ADDR
 CONFIG_PHY3_ADDR
 CONFIG_PHYCORE_MPC5200B_TINY
 CONFIG_PHYLIB_10G
 CONFIG_PHYSMEM
 CONFIG_PHY_ADDR
 CONFIG_PHY_AQUANTIA
 CONFIG_PHY_ATHEROS
 CONFIG_PHY_BASE_ADR
 CONFIG_PHY_BCM5421S
 CONFIG_PHY_BROADCOM
 CONFIG_PHY_CLK_FREQ
 CONFIG_PHY_CLOCK_FREQ
 CONFIG_PHY_CMD_DELAY
 CONFIG_PHY_CORTINA
 CONFIG_PHY_DAVICOM
 CONFIG_PHY_DYNAMIC_ANEG
 CONFIG_PHY_ET1011C
 CONFIG_PHY_ET1011C_TX_CLK_FIX
 CONFIG_PHY_GIGE
 CONFIG_PHY_ID
 CONFIG_PHY_INTERFACE_MODE
 CONFIG_PHY_IRAM_BASE
 CONFIG_PHY_KSZ9031
 CONFIG_PHY_LXT
 CONFIG_PHY_M88E1111
 CONFIG_PHY_MARVELL
 CONFIG_PHY_MAX_ADDR
 CONFIG_PHY_MICREL
 CONFIG_PHY_MICREL_KSZ9021
 CONFIG_PHY_MICREL_KSZ9031
 CONFIG_PHY_MODE_NEED_CHANGE
 CONFIG_PHY_NATSEMI
 CONFIG_PHY_REALTEK
 CONFIG_PHY_RESET
 CONFIG_PHY_RESET_DELAY
 CONFIG_PHY_SMSC
 CONFIG_PHY_TERANETICS
 CONFIG_PHY_TI
 CONFIG_PHY_TYPE
 CONFIG_PHY_VITESSE
 CONFIG_PHY_XILINX
 CONFIG_PHYx_ADDR
 CONFIG_PICOSAM
 CONFIG_PIGGY_MAC_ADRESS_OFFSET
 CONFIG_PIP405
 CONFIG_PIXIS_BRDCFG0_SPI
 CONFIG_PIXIS_BRDCFG0_USB2
 CONFIG_PIXIS_BRDCFG1_AUDCLK_11
 CONFIG_PIXIS_BRDCFG1_AUDCLK_12
 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK
 CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK
 CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI
 CONFIG_PIXIS_BRDCFG1_TDM
 CONFIG_PIXIS_SGMII_CMD
 CONFIG_PL010_SERIAL
 CONFIG_PL011_CLOCK
 CONFIG_PL011_SERIAL
 CONFIG_PL011_SERIAL_RLCR
 CONFIG_PL01X_SERIAL
 CONFIG_PL01x_PORTS
 CONFIG_PLATFORM_ENV_SETTINGS
 CONFIG_PLATINUM_BOARD
 CONFIG_PLATINUM_CPU
 CONFIG_PLATINUM_PICON
 CONFIG_PLATINUM_PROJECT
 CONFIG_PLATINUM_TITANIUM
 CONFIG_PLL
 CONFIG_PLL1_CLK_FREQ
 CONFIG_PLL1_DIV2_CLK_FREQ
 CONFIG_PLL_BYPASS
 CONFIG_PLL_CTL_VAL
 CONFIG_PLL_DIV_VAL
 CONFIG_PLL_LOCKCNT_VAL
 CONFIG_PLU405
 CONFIG_PM
 CONFIG_PM9261
 CONFIG_PM9263
 CONFIG_PM9G45
 CONFIG_PMC405DE
 CONFIG_PMC_BR_PRELIM
 CONFIG_PMC_OR_PRELIM
 CONFIG_PMECC_CAP
 CONFIG_PMECC_INDEX_TABLE_OFFSET
 CONFIG_PMECC_SECTOR_SIZE
 CONFIG_PME_PLAT_CLK_DIV
 CONFIG_PMIC
 CONFIG_PMU
 CONFIG_PMW_BASE
 CONFIG_PM_SLEEP
 CONFIG_PORTMUX_PIO
 CONFIG_PORT_ADDR
 CONFIG_PORT_AP
 CONFIG_PORT_BEM
 CONFIG_PORT_BME
 CONFIG_PORT_BS
 CONFIG_PORT_BU
 CONFIG_PORT_BW
 CONFIG_PORT_CR
 CONFIG_PORT_CSN
 CONFIG_PORT_OEN
 CONFIG_PORT_PEN
 CONFIG_PORT_RE
 CONFIG_PORT_SOR
 CONFIG_PORT_TH
 CONFIG_PORT_TWE
 CONFIG_PORT_WBF
 CONFIG_PORT_WBN
 CONFIG_POST
 CONFIG_POSTBOOTMENU
 CONFIG_POST_ALT_LIST
 CONFIG_POST_BSPEC1
 CONFIG_POST_BSPEC1_GPIO_LEDS
 CONFIG_POST_BSPEC2
 CONFIG_POST_BSPEC2_GPIO_BUTTONS
 CONFIG_POST_BSPEC2_GPIO_NAMES
 CONFIG_POST_BSPEC3
 CONFIG_POST_BSPEC4
 CONFIG_POST_BSPEC5
 CONFIG_POST_EXTERNAL_WORD_FUNCS
 CONFIG_POST_KEY_MAGIC
 CONFIG_POST_SKIP_ENV_FLAGS
 CONFIG_POST_STD_LIST
 CONFIG_POST_UART
 CONFIG_POST_WATCHDOG
 CONFIG_POWER
 CONFIG_POWER_BATTERY
 CONFIG_POWER_BATTERY_TRATS
 CONFIG_POWER_BATTERY_TRATS2
 CONFIG_POWER_FG
 CONFIG_POWER_FG_MAX17042
 CONFIG_POWER_FG_MAX77693
 CONFIG_POWER_FSL
 CONFIG_POWER_FSL_MC13892
 CONFIG_POWER_FSL_MC34704
 CONFIG_POWER_HI6553
 CONFIG_POWER_I2C
 CONFIG_POWER_LTC3676
 CONFIG_POWER_LTC3676_I2C_ADDR
 CONFIG_POWER_MAX77686
 CONFIG_POWER_MAX77696
 CONFIG_POWER_MAX77696_I2C_ADDR
 CONFIG_POWER_MAX8997
 CONFIG_POWER_MAX8998
 CONFIG_POWER_MUIC
 CONFIG_POWER_MUIC_MAX77693
 CONFIG_POWER_MUIC_MAX8997
 CONFIG_POWER_PFUZE100
 CONFIG_POWER_PFUZE100_I2C_ADDR
 CONFIG_POWER_PFUZE3000
 CONFIG_POWER_PFUZE3000_I2C_ADDR
 CONFIG_POWER_PMIC_MAX77693
 CONFIG_POWER_SPI
 CONFIG_POWER_TPS62362
 CONFIG_POWER_TPS65090_EC
 CONFIG_POWER_TPS65217
 CONFIG_POWER_TPS65218
 CONFIG_POWER_TPS65910
 CONFIG_PPC4XX_RAPIDIO_DEBUG
 CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
 CONFIG_PPC4XX_RAPIDIO_LOOPBACK
 CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
 CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
 CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 CONFIG_PPC4xx_DDR_METHOD_A
 CONFIG_PPC4xx_EMAC
 CONFIG_PPC64BRIDGE
 CONFIG_PPC_B4420
 CONFIG_PPC_B4860
 CONFIG_PPC_C29X
 CONFIG_PPC_CLUSTER_START
 CONFIG_PPC_P2041
 CONFIG_PPC_P3041
 CONFIG_PPC_P4080
 CONFIG_PPC_P5020
 CONFIG_PPC_P5040
 CONFIG_PPC_SPINTABLE_COMPATIBLE
 CONFIG_PPC_T1023
 CONFIG_PPC_T1024
 CONFIG_PPC_T1040
 CONFIG_PPC_T1042
 CONFIG_PPC_T2080
 CONFIG_PPC_T2081
 CONFIG_PPC_T4160
 CONFIG_PPC_T4240
 CONFIG_PQ_MDS_PIB
 CONFIG_PQ_MDS_PIB_ATM
 CONFIG_PRAM
 CONFIG_PREBOOT
 CONFIG_PRIMEVIEW_V16C6448AC
 CONFIG_PRINTK
 CONFIG_PROC_FS
 CONFIG_PROFILE_ALL_BRANCHES
 CONFIG_PROFILING
 CONFIG_PROG_FDT
 CONFIG_PROG_FDT1
 CONFIG_PROG_FDT2
 CONFIG_PROG_OS
 CONFIG_PROG_OS1
 CONFIG_PROG_OS2
 CONFIG_PROG_SDRAM_TLB
 CONFIG_PROG_UBOOT
 CONFIG_PROG_UBOOT1
 CONFIG_PROG_UBOOT2
 CONFIG_PROOF_POINTS
 CONFIG_PRPMC_PCI_ALIAS
 CONFIG_PS2KBD
 CONFIG_PS2MULT
 CONFIG_PS2MULT_DELAY
 CONFIG_PS2SERIAL
 CONFIG_PSC3_USB
 CONFIG_PSC_CONSOLE
 CONFIG_PSC_CONSOLE2
 CONFIG_PSRAM_SCFG
 CONFIG_PWM
 CONFIG_PWM_IMX
 CONFIG_PXA_LCD
 CONFIG_PXA_MMC_GENERIC
 CONFIG_PXA_PWR_I2C
 CONFIG_PXA_SERIAL
 CONFIG_PXA_STD_I2C
 CONFIG_PXA_VGA
 CONFIG_PXA_VIDEO
 CONFIG_P_CLK_FREQ
 CONFIG_QBMAN_CLK_DIV
 CONFIG_QE
 CONFIG_QEMU_E500
 CONFIG_QEMU_MIPS
 CONFIG_QIXIS_I2C_ACCESS
 CONFIG_QSPI
 CONFIG_QSPI_QUAD_SUPPORT
 CONFIG_QSPI_SEL_GPIO
 CONFIG_QUOTA
 CONFIG_R0P7734
 CONFIG_R2DPLUS
 CONFIG_R7780MP
 CONFIG_R8A66597_BASE_ADDR
 CONFIG_R8A66597_ENDIAN
 CONFIG_R8A66597_LDRV
 CONFIG_R8A66597_XTAL
 CONFIG_R8A7740
 CONFIG_R8A7790
 CONFIG_R8A7791
 CONFIG_R8A7792
 CONFIG_R8A7793
 CONFIG_R8A7794
 CONFIG_RAINIER
 CONFIG_RAMBOOT
 CONFIG_RAMBOOTCOMMAND
 CONFIG_RAMBOOTCOMMAND_TFTP
 CONFIG_RAMBOOT_NAND
 CONFIG_RAMBOOT_PBL
 CONFIG_RAMBOOT_SDCARD
 CONFIG_RAMBOOT_SPIFLASH
 CONFIG_RAMBOOT_TEXT_BASE
 CONFIG_RAMDISKFILE
 CONFIG_RAMDISK_ADDR
 CONFIG_RAMDISK_BOOT
 CONFIG_RAM_BOOT
 CONFIG_RAM_BOOT_PHYS
 CONFIG_RANDOM_UUID
 CONFIG_RAPIDIO
 CONFIG_RBTREE
 CONFIG_RCAR_BOARD_STRING
 CONFIG_RD_LVL
 CONFIG_REALMODE_DEBUG
 CONFIG_RED_LED
 CONFIG_REFCLK_FREQ
 CONFIG_REG
 CONFIG_REG_0
 CONFIG_REG_1_BASE
 CONFIG_REG_2
 CONFIG_REG_3
 CONFIG_REG_8
 CONFIG_REG_APER_SIZE
 CONFIG_RELOC_GOT_SKIP_NULL
 CONFIG_REMAKE_ELF
 CONFIG_REQ
 CONFIG_RESERVED_01_BASE
 CONFIG_RESERVED_02_BASE
 CONFIG_RESERVED_03_BASE
 CONFIG_RESERVED_04_BASE
 CONFIG_RESET
 CONFIG_RESET_PHY_R
 CONFIG_RESET_TO_RETRY
 CONFIG_RESET_VECTOR_ADDRESS
 CONFIG_RESTORE_FLASH
 CONFIG_RES_BLOCK_SIZE
 CONFIG_REV1
 CONFIG_REV3
 CONFIG_REVISION_TAG
 CONFIG_RFSPART
 CONFIG_RGMII
 CONFIG_RIO
 CONFIG_RMII
 CONFIG_RMOBILE_BOARD_STRING
 CONFIG_RMSTP0_ENA
 CONFIG_RMSTP10_ENA
 CONFIG_RMSTP11_ENA
 CONFIG_RMSTP1_ENA
 CONFIG_RMSTP2_ENA
 CONFIG_RMSTP3_ENA
 CONFIG_RMSTP4_ENA
 CONFIG_RMSTP5_ENA
 CONFIG_RMSTP6_ENA
 CONFIG_RMSTP7_ENA
 CONFIG_RMSTP8_ENA
 CONFIG_RMSTP9_ENA
 CONFIG_ROCKCHIP_CHIP_TAG
 CONFIG_ROCKCHIP_MAX_INIT_SIZE
 CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
 CONFIG_ROCKCHIP_USB2_PHY
 CONFIG_ROM_STUBS
 CONFIG_ROOTFS_OFFSET
 CONFIG_ROOTPATH
 CONFIG_RSK7203
 CONFIG_RSK7264
 CONFIG_RSK7269
 CONFIG_RTC_BFIN
 CONFIG_RTC_DS1307
 CONFIG_RTC_DS1337
 CONFIG_RTC_DS1338
 CONFIG_RTC_DS1374
 CONFIG_RTC_DS1388
 CONFIG_RTC_DS1556
 CONFIG_RTC_DS174x
 CONFIG_RTC_DS3231
 CONFIG_RTC_FTRTC010
 CONFIG_RTC_IMXDI
 CONFIG_RTC_INTERNAL
 CONFIG_RTC_M41T11
 CONFIG_RTC_M41T60
 CONFIG_RTC_M41T62
 CONFIG_RTC_M48T35A
 CONFIG_RTC_MC13XXX
 CONFIG_RTC_MC146818
 CONFIG_RTC_MCFRRTC
 CONFIG_RTC_MCP79411
 CONFIG_RTC_MPC5200
 CONFIG_RTC_MPC8xx
 CONFIG_RTC_MV
 CONFIG_RTC_MXS
 CONFIG_RTC_PCF8563
 CONFIG_RTC_PT7C4338
 CONFIG_RTC_RTC4543
 CONFIG_RTC_RV3029
 CONFIG_RTC_RX8025
 CONFIG_RTC_S3C24X0
 CONFIG_RTC_X1205
 CONFIG_RUN_FROM_DDR0
 CONFIG_RUN_FROM_DDR1
 CONFIG_RUN_FROM_IRAM_ONLY
 CONFIG_RX_DESCR_NUM
 CONFIG_S32V234
 CONFIG_S3C2400
 CONFIG_S3C2410
 CONFIG_S3C2410_NAND_BBT
 CONFIG_S3C2410_NAND_HWECC
 CONFIG_S3C2440
 CONFIG_S3C24X0
 CONFIG_S3C24X0_SERIAL
 CONFIG_S3C24XX_CUSTOM_NAND_TIMING
 CONFIG_S3C24XX_TACLS
 CONFIG_S3C24XX_TWRPH0
 CONFIG_S3C24XX_TWRPH1
 CONFIG_S3D2_CLK_FREQ
 CONFIG_S5P
 CONFIG_S5PC100
 CONFIG_S5PC110
 CONFIG_S5P_PA_SYSRAM
 CONFIG_S5P_SDHCI
 CONFIG_S6E63D6
 CONFIG_S6E8AX0
 CONFIG_SA1100_ADSBITSY
 CONFIG_SA1100_ASSABET
 CONFIG_SA1100_BADGE4
 CONFIG_SA1100_BRUTUS
 CONFIG_SA1100_CERF
 CONFIG_SA1100_COLLIE
 CONFIG_SA1100_CONSUS
 CONFIG_SA1100_FLEXANET
 CONFIG_SA1100_GRAPHICSCLIENT
 CONFIG_SA1100_GRAPHICSMASTER
 CONFIG_SA1100_H3100
 CONFIG_SA1100_H3600
 CONFIG_SA1100_HACKKIT
 CONFIG_SA1100_JORNADA720
 CONFIG_SA1100_LART
 CONFIG_SA1100_NANOENGINE
 CONFIG_SA1100_PFS168
 CONFIG_SA1100_PLEB
 CONFIG_SA1100_PT_SYSTEM3
 CONFIG_SA1100_SHANNON
 CONFIG_SA1100_SIMPAD
 CONFIG_SA1100_XP860
 CONFIG_SABRELITE
 CONFIG_SAMA5D2
 CONFIG_SAMA5D3
 CONFIG_SAMA5D3_LCD_BASE
 CONFIG_SAMA5D4
 CONFIG_SAMSUNG
 CONFIG_SAMSUNG_ONENAND
 CONFIG_SANDBOX_ARCH
 CONFIG_SANDBOX_BIG_ENDIAN
 CONFIG_SANDBOX_BITS_PER_LONG
 CONFIG_SANDBOX_SDL
 CONFIG_SANDBOX_SPI_MAX_BUS
 CONFIG_SANDBOX_SPI_MAX_CS
 CONFIG_SAR2_REG
 CONFIG_SAR_REG
 CONFIG_SATA1
 CONFIG_SATA2
 CONFIG_SATAPWR
 CONFIG_SATA_CEVA
 CONFIG_SATA_DWC
 CONFIG_SATA_MV
 CONFIG_SATA_SIL
 CONFIG_SATA_SIL3114
 CONFIG_SATA_ULI5288
 CONFIG_SBC8349
 CONFIG_SBC8548
 CONFIG_SBC8641D
 CONFIG_SCC1_ENET
 CONFIG_SCC2_ENET
 CONFIG_SCF0403_LCD
 CONFIG_SCIF
 CONFIG_SCIF_A
 CONFIG_SCIF_CONSOLE
 CONFIG_SCIF_EXT_CLOCK
 CONFIG_SCIF_USE_EXT_CLK
 CONFIG_SCLK0_DIV
 CONFIG_SCLK1_DIV
 CONFIG_SCLK_DIV
 CONFIG_SCLK_HZ
 CONFIG_SCSI
 CONFIG_SCSI_AHCI
 CONFIG_SCSI_AHCI_PLAT
 CONFIG_SCSI_DEV_ID
 CONFIG_SCSI_DEV_LIST
 CONFIG_SCSI_SYM53C8XX
 CONFIG_SC_TIMER_CLK
 CONFIG_SDCARD
 CONFIG_SDHCI
 CONFIG_SDRAM_BANK0
 CONFIG_SDRAM_BANK1
 CONFIG_SDRAM_ECC
 CONFIG_SDRAM_OFFSET_FOR_RT
 CONFIG_SDRAM_PPC4xx_DENALI_DDR2
 CONFIG_SDRAM_PPC4xx_IBM_DDR
 CONFIG_SDRAM_PPC4xx_IBM_DDR2
 CONFIG_SDRAM_PPC4xx_IBM_SDRAM
 CONFIG_SDRC
 CONFIG_SDR_MT48LC16M16A2
 CONFIG_SD_BOOT_QSPI
 CONFIG_SECBOOT
 CONFIG_SECURE_BL1_ONLY
 CONFIG_SECURE_BOOT
 CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
 CONFIG_SECURITY
 CONFIG_SEC_DEQ_TIMEOUT
 CONFIG_SEC_FW_SIZE
 CONFIG_SELECTED
 CONFIG_SEQUOIA
 CONFIG_SERIAL0
 CONFIG_SERIAL1
 CONFIG_SERIAL2
 CONFIG_SERIAL3
 CONFIG_SERIAL_BOOT
 CONFIG_SERIAL_FLASH
 CONFIG_SERIAL_HW_FLOW_CONTROL
 CONFIG_SERIAL_MULTI
 CONFIG_SERIAL_SOFTWARE_FIFO
 CONFIG_SERIAL_TAG
 CONFIG_SERIRQ_CONTINUOUS_MODE
 CONFIG_SERVERIP
 CONFIG_SETUP_INITRD_TAG
 CONFIG_SETUP_MEMORY_TAGS
 CONFIG_SET_BIST
 CONFIG_SET_BOOTARGS
 CONFIG_SET_DFU_ALT_BUF_LEN
 CONFIG_SET_DFU_ALT_INFO
 CONFIG_SFIO
 CONFIG_SF_DATAFLASH
 CONFIG_SF_DEFAULT_BUS
 CONFIG_SF_DEFAULT_CS
 CONFIG_SF_DEFAULT_HZ
 CONFIG_SF_DEFAULT_MODE
 CONFIG_SF_DEFAULT_SPEED
 CONFIG_SF_DUAL_FLASH
 CONFIG_SGI_IP28
 CONFIG_SH4_PCI
 CONFIG_SH73A0
 CONFIG_SH7751_PCI
 CONFIG_SH7752EVB
 CONFIG_SH7753EVB
 CONFIG_SH7757LCR
 CONFIG_SH7757LCR_DDR_ECC
 CONFIG_SH7763RDP
 CONFIG_SH7780_PCI
 CONFIG_SH7780_PCI_BAR
 CONFIG_SH7780_PCI_LAR
 CONFIG_SH7780_PCI_LSR
 CONFIG_SH7785LCR
 CONFIG_SHA1SUM_VERIFY
 CONFIG_SHARP_16x9
 CONFIG_SHARP_LM8V31
 CONFIG_SHARP_LQ035Q7DH06
 CONFIG_SHARP_LQ057Q3DC02
 CONFIG_SHARP_LQ065T9DR51U
 CONFIG_SHARP_LQ084V1DG21
 CONFIG_SHARP_LQ104V7DS01
 CONFIG_SHARP_LQ64D341
 CONFIG_SHEEVA_88SV131
 CONFIG_SHEEVA_88SV331xV5
 CONFIG_SHELL
 CONFIG_SHMIN
 CONFIG_SHOW_ACTIVITY
 CONFIG_SHOW_BOOT_PROGRESS
 CONFIG_SH_CMT_CLK_FREQ
 CONFIG_SH_DSP
 CONFIG_SH_ETHER
 CONFIG_SH_ETHER_ALIGNE_SIZE
 CONFIG_SH_ETHER_BASE_ADDR
 CONFIG_SH_ETHER_CACHE_INVALIDATE
 CONFIG_SH_ETHER_CACHE_WRITEBACK
 CONFIG_SH_ETHER_PHY_ADDR
 CONFIG_SH_ETHER_PHY_MODE
 CONFIG_SH_ETHER_SH7734_MII
 CONFIG_SH_ETHER_USE_GETHER
 CONFIG_SH_ETHER_USE_PORT
 CONFIG_SH_GPIO_PFC
 CONFIG_SH_I2C_8BIT
 CONFIG_SH_I2C_BASE0
 CONFIG_SH_I2C_BASE1
 CONFIG_SH_I2C_CLOCK
 CONFIG_SH_I2C_DATA_HIGH
 CONFIG_SH_I2C_DATA_LOW
 CONFIG_SH_MMCIF
 CONFIG_SH_MMCIF_ADDR
 CONFIG_SH_MMCIF_CLK
 CONFIG_SH_QSPI
 CONFIG_SH_QSPI_BASE
 CONFIG_SH_SCIF_CLK_FREQ
 CONFIG_SH_SDHI_FREQ
 CONFIG_SH_SDRAM_OFFSET
 CONFIG_SH_SH7734_I2C
 CONFIG_SH_SPI
 CONFIG_SH_SPI_BASE
 CONFIG_SH_TMU_CLK_FREQ
 CONFIG_SIEMENS_DRACO
 CONFIG_SIEMENS_MACH_TYPE
 CONFIG_SIEMENS_PXM2
 CONFIG_SIEMENS_RUT
 CONFIG_SIMU
 CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
 CONFIG_SKIP_LOWLEVEL_INIT
 CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 CONFIG_SKIP_TRUNOFF_WATCHDOG
 CONFIG_SLIC
 CONFIG_SLTTMR
 CONFIG_SMC91111
 CONFIG_SMC91111_BASE
 CONFIG_SMC91111_EXT_PHY
 CONFIG_SMC911X
 CONFIG_SMC911X_16_BIT
 CONFIG_SMC911X_32_BIT
 CONFIG_SMC911X_BASE
 CONFIG_SMC911X_NO_EEPROM
 CONFIG_SMC_91111_EXT_PHY
 CONFIG_SMC_AUTONEG_TIMEOUT
 CONFIG_SMC_B0CTL_VAL
 CONFIG_SMC_B0ETIM_VAL
 CONFIG_SMC_B0TIM_VAL
 CONFIG_SMC_B1CTL_VAL
 CONFIG_SMC_B1ETIM_VAL
 CONFIG_SMC_B1TIM_VAL
 CONFIG_SMC_B2CTL_VAL
 CONFIG_SMC_B2ETIM_VAL
 CONFIG_SMC_B2TIM_VAL
 CONFIG_SMC_B3CTL_VAL
 CONFIG_SMC_B3ETIM_VAL
 CONFIG_SMC_B3TIM_VAL
 CONFIG_SMC_GCTL_VAL
 CONFIG_SMC_USE_32_BIT
 CONFIG_SMC_USE_IOFUNCS
 CONFIG_SMDK2410
 CONFIG_SMDK5420
 CONFIG_SMDKC100
 CONFIG_SMDKV310
 CONFIG_SMP_PEN_ADDR
 CONFIG_SMSC_LPC47M
 CONFIG_SMSC_SIO1007
 CONFIG_SMSTP0_ENA
 CONFIG_SMSTP10_ENA
 CONFIG_SMSTP11_ENA
 CONFIG_SMSTP1_ENA
 CONFIG_SMSTP2_ENA
 CONFIG_SMSTP3_ENA
 CONFIG_SMSTP4_ENA
 CONFIG_SMSTP5_ENA
 CONFIG_SMSTP6_ENA
 CONFIG_SMSTP7_ENA
 CONFIG_SMSTP8_ENA
 CONFIG_SMSTP9_ENA
 CONFIG_SOCFPGA_DWMMC
 CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH
 CONFIG_SOCFPGA_VIRTUAL_TARGET
 CONFIG_SOCRATES
 CONFIG_SOC_AU1000
 CONFIG_SOC_AU1100
 CONFIG_SOC_AU1500
 CONFIG_SOC_AU1550
 CONFIG_SOC_AU1X00
 CONFIG_SOC_DA850
 CONFIG_SOC_DA8XX
 CONFIG_SOC_DM355
 CONFIG_SOC_DM365
 CONFIG_SOC_DM644X
 CONFIG_SOC_DM646X
 CONFIG_SOC_K2E
 CONFIG_SOC_K2G
 CONFIG_SOC_K2HK
 CONFIG_SOC_K2L
 CONFIG_SOC_KEYSTONE
 CONFIG_SOC_OMAP3430
 CONFIG_SOFT_I2C_GPIO_SCL
 CONFIG_SOFT_I2C_GPIO_SDA
 CONFIG_SOFT_I2C_I2C10_SCL
 CONFIG_SOFT_I2C_I2C10_SDA
 CONFIG_SOFT_I2C_I2C5_SCL
 CONFIG_SOFT_I2C_I2C5_SDA
 CONFIG_SOFT_I2C_I2C9_SCL
 CONFIG_SOFT_I2C_I2C9_SDA
 CONFIG_SOFT_I2C_MULTI_BUS
 CONFIG_SOFT_I2C_READ_REPEATED_START
 CONFIG_SOFT_SPI
 CONFIG_SOFT_TWS
 CONFIG_SOURCE
 CONFIG_SPARSE_RCU_POINTER
 CONFIG_SPDDRAM_SILENT
 CONFIG_SPD_EEPROM
 CONFIG_SPEAR300
 CONFIG_SPEAR310
 CONFIG_SPEAR320
 CONFIG_SPEAR3XX
 CONFIG_SPEAR600
 CONFIG_SPEAR_BOOTSTRAPCFG
 CONFIG_SPEAR_BOOTSTRAPMASK
 CONFIG_SPEAR_BOOTSTRAPSHFT
 CONFIG_SPEAR_EMI
 CONFIG_SPEAR_EMIBASE
 CONFIG_SPEAR_ETHBASE
 CONFIG_SPEAR_GPIO
 CONFIG_SPEAR_HZ
 CONFIG_SPEAR_HZ_CLOCK
 CONFIG_SPEAR_MISCBASE
 CONFIG_SPEAR_MPMCBASE
 CONFIG_SPEAR_MPMCREGS
 CONFIG_SPEAR_NORNAND16BOOT
 CONFIG_SPEAR_NORNAND8BOOT
 CONFIG_SPEAR_NORNANDBOOT
 CONFIG_SPEAR_ONLYSNORBOOT
 CONFIG_SPEAR_RASBASE
 CONFIG_SPEAR_SYSCNTLBASE
 CONFIG_SPEAR_TIMERBASE
 CONFIG_SPEAR_UART48M
 CONFIG_SPEAR_UARTCLKMSK
 CONFIG_SPEAR_USBBOOT
 CONFIG_SPEAR_USBTTY
 CONFIG_SPI
 CONFIG_SPI_ADDR
 CONFIG_SPI_BAUD_INITBLOCK
 CONFIG_SPI_BOOTING
 CONFIG_SPI_CS_IS_VALID
 CONFIG_SPI_DATAFLASH_WRITE_VERIFY
 CONFIG_SPI_FLASH_ALL
 CONFIG_SPI_FLASH_ISSI
 CONFIG_SPI_FLASH_QUAD
 CONFIG_SPI_FLASH_SIZE
 CONFIG_SPI_HALF_DUPLEX
 CONFIG_SPI_IDLE_VAL
 CONFIG_SPI_LENGTH
 CONFIG_SPI_N25Q256A_RESET
 CONFIG_SPLASHIMAGE_GUARD
 CONFIG_SPLASH_SCREEN
 CONFIG_SPLASH_SCREEN_ALIGN
 CONFIG_SPLASH_SOURCE
 CONFIG_SPLL_FREQ
 CONFIG_SPL_
 CONFIG_SPL_ABORT_ON_RAW_IMAGE
 CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 CONFIG_SPL_ATMEL_SIZE
 CONFIG_SPL_BOARD_INIT
 CONFIG_SPL_BOARD_LOAD_IMAGE
 CONFIG_SPL_BOOTROM_SAVE
 CONFIG_SPL_BOOT_DEVICE
 CONFIG_SPL_BSS_MAX_SIZE
 CONFIG_SPL_BSS_START_ADDR
 CONFIG_SPL_CMT
 CONFIG_SPL_CMT_DEBUG
 CONFIG_SPL_COMMON_INIT_DDR
 CONFIG_SPL_CONSOLE
 CONFIG_SPL_DISPLAY_PRINT
 CONFIG_SPL_ETH_DEVICE
 CONFIG_SPL_FLUSH_IMAGE
 CONFIG_SPL_FRAMEWORK
 CONFIG_SPL_FSL_PBL
 CONFIG_SPL_FS_LOAD_ARGS_NAME
 CONFIG_SPL_FS_LOAD_KERNEL_NAME
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
 CONFIG_SPL_GD_ADDR
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 CONFIG_SPL_INIT_MINIMAL
 CONFIG_SPL_JR0_LIODN_NS
 CONFIG_SPL_JR0_LIODN_S
 CONFIG_SPL_LDSCRIPT
 CONFIG_SPL_LOAD_FIT_ADDRESS
 CONFIG_SPL_MAX_FOOTPRINT
 CONFIG_SPL_MAX_PEB_SIZE
 CONFIG_SPL_MAX_SIZE
 CONFIG_SPL_MMC_BOOT
 CONFIG_SPL_MMC_LOAD
 CONFIG_SPL_MMC_MINIMAL
 CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
 CONFIG_SPL_MXS_PSWITCH_WAIT
 CONFIG_SPL_NAND_AM33XX_BCH
 CONFIG_SPL_NAND_BASE
 CONFIG_SPL_NAND_BOOT
 CONFIG_SPL_NAND_DRIVERS
 CONFIG_SPL_NAND_ECC
 CONFIG_SPL_NAND_INIT
 CONFIG_SPL_NAND_LOAD
 CONFIG_SPL_NAND_MINIMAL
 CONFIG_SPL_NAND_MXS
 CONFIG_SPL_NAND_RAW_ONLY
 CONFIG_SPL_NAND_SIMPLE
 CONFIG_SPL_NAND_SOFTECC
 CONFIG_SPL_NAND_WORKSPACE
 CONFIG_SPL_NO_CPU_SUPPORT_CODE
 CONFIG_SPL_OMAP3_ID_NAND
 CONFIG_SPL_OS_BOOT
 CONFIG_SPL_PAD_TO
 CONFIG_SPL_PANIC_ON_RAW_IMAGE
 CONFIG_SPL_PBL_PAD
 CONFIG_SPL_PPAACT_ADDR
 CONFIG_SPL_RAM_DEVICE
 CONFIG_SPL_RELOC_MALLOC_ADDR
 CONFIG_SPL_RELOC_MALLOC_SIZE
 CONFIG_SPL_RELOC_STACK
 CONFIG_SPL_RELOC_STACK_SIZE
 CONFIG_SPL_RELOC_TEXT_BASE
 CONFIG_SPL_SATA_BOOT_DEVICE
 CONFIG_SPL_SIZE
 CONFIG_SPL_SKIP_RELOCATE
 CONFIG_SPL_SPAACT_ADDR
 CONFIG_SPL_SPI_BOOT
 CONFIG_SPL_SPI_FLASH_MINIMAL
 CONFIG_SPL_SPI_LOAD
 CONFIG_SPL_STACK
 CONFIG_SPL_STACK_ADDR
 CONFIG_SPL_STACK_SIZE
 CONFIG_SPL_START_S_PATH
 CONFIG_SPL_TARGET
 CONFIG_SPL_TEXT_BASE
 CONFIG_SPL_UBI
 CONFIG_SPL_UBI_INFO_ADDR
 CONFIG_SPL_UBI_LEB_START
 CONFIG_SPL_UBI_LOAD_ARGS_ID
 CONFIG_SPL_UBI_LOAD_KERNEL_ID
 CONFIG_SPL_UBI_LOAD_MONITOR_ID
 CONFIG_SPL_UBI_MAX_PEBS
 CONFIG_SPL_UBI_MAX_PEB_SIZE
 CONFIG_SPL_UBI_MAX_VOL_LEBS
 CONFIG_SPL_UBI_PEB_OFFSET
 CONFIG_SPL_UBI_VID_OFFSET
 CONFIG_SPL_UBI_VOL_IDS
 CONFIG_SPL_UBOOT_KEY_HASH
 CONFIG_SRAM_BASE
 CONFIG_SRAM_SIZE
 CONFIG_SRIO1
 CONFIG_SRIO2
 CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1
 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2
 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
 CONFIG_SRIO_PCIE_BOOT_MASTER
 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK
 CONFIG_SRIO_PCIE_BOOT_SLAVE
 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
 CONFIG_SSD_BR_PRELIM
 CONFIG_SSD_OR_PRELIM
 CONFIG_SSE2
 CONFIG_SSI1_FREQ
 CONFIG_SSI2_FREQ
 CONFIG_SSP1_BASE
 CONFIG_SSP2_BASE
 CONFIG_SSP3_BASE
 CONFIG_STACKBASE
 CONFIG_STACKSIZE
 CONFIG_STACKSIZE_FIQ
 CONFIG_STACKSIZE_IRQ
 CONFIG_STAMP_CF
 CONFIG_STANDALONE_LOAD_ADDR
 CONFIG_STATIC_BOARD_REV
 CONFIG_STATIC_RELA
 CONFIG_STATUSLED
 CONFIG_STATUS_LED
 CONFIG_STD_DEVICES_SETTINGS
 CONFIG_STK52XX
 CONFIG_STK52XX_REV100
 CONFIG_STM32F4DISCOVERY
 CONFIG_STM32X7_SERIAL
 CONFIG_STM32_FLASH
 CONFIG_STM32_GPIO
 CONFIG_STM32_HSE_HZ
 CONFIG_STM32_HZ
 CONFIG_STM32_SERIAL
 CONFIG_STORAGE_EMMC
 CONFIG_STRESS
 CONFIG_STRIDER
 CONFIG_STRIDER_CON
 CONFIG_STRIDER_CON_DP
 CONFIG_STRIDER_CPU
 CONFIG_STRIDER_CPU_DP
 CONFIG_STRIDER_FANS
 CONFIG_STUART
 CONFIG_STV0991
 CONFIG_STV0991_HZ
 CONFIG_STV0991_HZ_CLOCK
 CONFIG_ST_SMI
 CONFIG_SUN4
 CONFIG_SUNXI
 CONFIG_SUNXI_AHCI
 CONFIG_SUNXI_EMAC
 CONFIG_SUNXI_GMAC
 CONFIG_SUNXI_GPIO
 CONFIG_SUNXI_MAX_FB_SIZE
 CONFIG_SUNXI_USB_PHYS
 CONFIG_SUPERH_ON_CHIP_R8A66597
 CONFIG_SUPPORT_EMMC_BOOT
 CONFIG_SUPPORT_EMMC_RPMB
 CONFIG_SUPPORT_RAW_INITRD
 CONFIG_SUPPORT_VFAT
 CONFIG_SUVD3
 CONFIG_SX151X_GPIO_COUNT_8
 CONFIG_SX151X_SPI_BUS
 CONFIG_SXNI855T
 CONFIG_SYSCOUNTER_TIMER
 CONFIG_SYSFLAGS_ADDR
 CONFIG_SYSFS
 CONFIG_SYSMGR_ISWGRP_HANDOFF
 CONFIG_SYSTEMACE
 CONFIG_SYS_33MHZ
 CONFIG_SYS_405_UART_ERRATA_59
 CONFIG_SYS_460GT_SRIO_ERRATA_1
 CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
 CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
 CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
 CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
 CONFIG_SYS_4xx_CHIP_21_ERRATA
 CONFIG_SYS_4xx_GPIO_TABLE
 CONFIG_SYS_4xx_RESET_TYPE
 CONFIG_SYS_64BIT
 CONFIG_SYS_64BIT_LBA
 CONFIG_SYS_64BIT_VSPRINTF
 CONFIG_SYS_66MHZ
 CONFIG_SYS_8313ERDB_BROKEN_PMC
 CONFIG_SYS_83XX_DDR_USES_CS0
 CONFIG_SYS_8XX_XIN
 CONFIG_SYS_8xx_CPUCLK_MAX
 CONFIG_SYS_8xx_CPUCLK_MIN
 CONFIG_SYS_ACE_BASE
 CONFIG_SYS_ACE_BASE_PHYS_H
 CONFIG_SYS_ACE_BASE_PHYS_L
 CONFIG_SYS_ACR_APARK
 CONFIG_SYS_ACR_PARKM
 CONFIG_SYS_ACR_PIPE_DEP
 CONFIG_SYS_ACR_RPTCNT
 CONFIG_SYS_ADDRESS_MAP_A
 CONFIG_SYS_ADV7611_I2C
 CONFIG_SYS_AHB_BASE
 CONFIG_SYS_ALE_MASK
 CONFIG_SYS_ALLOC_DPRAM
 CONFIG_SYS_ALT_BOOT
 CONFIG_SYS_ALT_FLASH
 CONFIG_SYS_ALT_MEMTEST
 CONFIG_SYS_AMASK0
 CONFIG_SYS_AMASK0_FINAL
 CONFIG_SYS_AMASK1
 CONFIG_SYS_AMASK1_FINAL
 CONFIG_SYS_AMASK2
 CONFIG_SYS_AMASK2_FINAL
 CONFIG_SYS_AMASK3
 CONFIG_SYS_AMASK3_FINAL
 CONFIG_SYS_AMASK4
 CONFIG_SYS_AMASK5
 CONFIG_SYS_AMASK6
 CONFIG_SYS_AMASK7
 CONFIG_SYS_APP1_BASE
 CONFIG_SYS_APP1_SIZE
 CONFIG_SYS_APP2_BASE
 CONFIG_SYS_APP2_SIZE
 CONFIG_SYS_ARCH_TIMER
 CONFIG_SYS_ARIA_FPGA_BASE
 CONFIG_SYS_ARIA_FPGA_SIZE
 CONFIG_SYS_ARIA_SRAM_BASE
 CONFIG_SYS_ARIA_SRAM_SIZE
 CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 CONFIG_SYS_AT91_CPU_NAME
 CONFIG_SYS_AT91_MAIN_CLOCK
 CONFIG_SYS_AT91_PLLA
 CONFIG_SYS_AT91_PLLB
 CONFIG_SYS_AT91_SLOW_CLOCK
 CONFIG_SYS_ATA_ALT_OFFSET
 CONFIG_SYS_ATA_BASE_ADDR
 CONFIG_SYS_ATA_CS_ON_I2C2
 CONFIG_SYS_ATA_CS_ON_TIMER01
 CONFIG_SYS_ATA_DATA_OFFSET
 CONFIG_SYS_ATA_IDE0_OFFSET
 CONFIG_SYS_ATA_IDE1_OFFSET
 CONFIG_SYS_ATA_PORT_ADDR
 CONFIG_SYS_ATA_REG_OFFSET
 CONFIG_SYS_ATA_STRIDE
 CONFIG_SYS_ATI_REV_A11
 CONFIG_SYS_ATI_REV_A12
 CONFIG_SYS_ATI_REV_A13
 CONFIG_SYS_ATI_REV_ID_MASK
 CONFIG_SYS_ATMEL_BASE
 CONFIG_SYS_ATMEL_BOOT
 CONFIG_SYS_ATMEL_CPU_NAME
 CONFIG_SYS_ATMEL_REGION
 CONFIG_SYS_ATMEL_SECT
 CONFIG_SYS_ATMEL_SECTSZ
 CONFIG_SYS_ATMEL_TOTALSECT
 CONFIG_SYS_AUTOLOAD
 CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 CONFIG_SYS_AUXCORE_BOOTDATA
 CONFIG_SYS_BARGSIZE
 CONFIG_SYS_BASE_BAUD
 CONFIG_SYS_BAUDRATE_TABLE
 CONFIG_SYS_BCR
 CONFIG_SYS_BCR_60x
 CONFIG_SYS_BCR_SINGLE
 CONFIG_SYS_BCSR
 CONFIG_SYS_BCSR3_PCIE
 CONFIG_SYS_BCSR5_PCI66EN
 CONFIG_SYS_BCSR_ADDR
 CONFIG_SYS_BCSR_BASE
 CONFIG_SYS_BCSR_BASE_PHYS
 CONFIG_SYS_BCSR_SIZE
 CONFIG_SYS_BD_INFO_ADDR
 CONFIG_SYS_BD_REV
 CONFIG_SYS_BFTIC3_BASE
 CONFIG_SYS_BFTIC3_SIZE
 CONFIG_SYS_BITBANG_PHY_PORT
 CONFIG_SYS_BITBANG_PHY_PORTS
 CONFIG_SYS_BLACK_IN_WRITE
 CONFIG_SYS_BMAN_CENA_BASE
 CONFIG_SYS_BMAN_CENA_SIZE
 CONFIG_SYS_BMAN_CINH_BASE
 CONFIG_SYS_BMAN_CINH_SIZE
 CONFIG_SYS_BMAN_MEM_BASE
 CONFIG_SYS_BMAN_MEM_PHYS
 CONFIG_SYS_BMAN_MEM_SIZE
 CONFIG_SYS_BMAN_NUM_PORTALS
 CONFIG_SYS_BMAN_SP_CENA_SIZE
 CONFIG_SYS_BMAN_SP_CINH_SIZE
 CONFIG_SYS_BMAN_SWP_ISDR_REG
 CONFIG_SYS_BOARD_NAME
 CONFIG_SYS_BOARD_OMAP3_HA
 CONFIG_SYS_BOARD_VERSION
 CONFIG_SYS_BOOK3E_HV
 CONFIG_SYS_BOOTCOUNT_ADDR
 CONFIG_SYS_BOOTCOUNT_BE
 CONFIG_SYS_BOOTCOUNT_LE
 CONFIG_SYS_BOOTCOUNT_SINGLEWORD
 CONFIG_SYS_BOOTCS_CFG
 CONFIG_SYS_BOOTCS_SIZE
 CONFIG_SYS_BOOTCS_START
 CONFIG_SYS_BOOTFILE
 CONFIG_SYS_BOOTFILE_PREFIX
 CONFIG_SYS_BOOTMAPSZ
 CONFIG_SYS_BOOTM_LEN
 CONFIG_SYS_BOOTPARAMS_LEN
 CONFIG_SYS_BOOTSZ
 CONFIG_SYS_BOOT_BASE_ADDR
 CONFIG_SYS_BOOT_BLOCK
 CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS
 CONFIG_SYS_BOOT_GET_CMDLINE
 CONFIG_SYS_BOOT_GET_KBD
 CONFIG_SYS_BOOT_RAMDISK_HIGH
 CONFIG_SYS_BOOT_SPINOR
 CONFIG_SYS_BR0_64M
 CONFIG_SYS_BR0_8M
 CONFIG_SYS_BR0_PRELIM
 CONFIG_SYS_BR10_PRELIM
 CONFIG_SYS_BR11_PRELIM
 CONFIG_SYS_BR1_PRELIM
 CONFIG_SYS_BR2_PRELIM
 CONFIG_SYS_BR3_CAN
 CONFIG_SYS_BR3_PRELIM
 CONFIG_SYS_BR4_PRELIM
 CONFIG_SYS_BR5_ISP1362
 CONFIG_SYS_BR5_PRELIM
 CONFIG_SYS_BR6_64M
 CONFIG_SYS_BR6_8M
 CONFIG_SYS_BR6_PRELIM
 CONFIG_SYS_BR7_PRELIM
 CONFIG_SYS_BR8_PRELIM
 CONFIG_SYS_BR9_PRELIM
 CONFIG_SYS_BRGCLK_PRESCALE
 CONFIG_SYS_BRIGHTNESS
 CONFIG_SYS_BUSCLK
 CONFIG_SYS_CACHELINE_SHIFT
 CONFIG_SYS_CACHE_ACR0
 CONFIG_SYS_CACHE_ACR1
 CONFIG_SYS_CACHE_ACR2
 CONFIG_SYS_CACHE_ACR3
 CONFIG_SYS_CACHE_ACR4
 CONFIG_SYS_CACHE_ACR5
 CONFIG_SYS_CACHE_ACR6
 CONFIG_SYS_CACHE_ACR7
 CONFIG_SYS_CACHE_DCACR
 CONFIG_SYS_CACHE_ICACR
 CONFIG_SYS_CACHE_STASHING
 CONFIG_SYS_CADMUS_BASE_REG
 CONFIG_SYS_CAN_BASE
 CONFIG_SYS_CAN_OR_AM
 CONFIG_SYS_CBSIZE
 CONFIG_SYS_CCCR
 CONFIG_SYS_CCI400_ADDR
 CONFIG_SYS_CCSRBAR
 CONFIG_SYS_CCSRBAR_DEFAULT
 CONFIG_SYS_CCSRBAR_PHYS
 CONFIG_SYS_CCSRBAR_PHYS_HIGH
 CONFIG_SYS_CCSRBAR_PHYS_LOW
 CONFIG_SYS_CCSR_DEFAULT_DBATL
 CONFIG_SYS_CCSR_DEFAULT_DBATU
 CONFIG_SYS_CCSR_DEFAULT_IBATL
 CONFIG_SYS_CCSR_DEFAULT_IBATU
 CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 CONFIG_SYS_CFI_FLASH_CONFIG_REGS
 CONFIG_SYS_CFI_FLASH_STATUS_POLL
 CONFIG_SYS_CF_BASE
 CONFIG_SYS_CF_INTC_REG1
 CONFIG_SYS_CF_SIZE
 CONFIG_SYS_CH7301_I2C
 CONFIG_SYS_CKEN
 CONFIG_SYS_CLE_MASK
 CONFIG_SYS_CLK
 CONFIG_SYS_CLKDIV_CPU
 CONFIG_SYS_CLKDIV_HSB
 CONFIG_SYS_CLKDIV_PBA
 CONFIG_SYS_CLKDIV_PBB
 CONFIG_SYS_CLKTL_CBCDR
 CONFIG_SYS_CLK_100
 CONFIG_SYS_CLK_100_DDR_100
 CONFIG_SYS_CLK_100_DDR_133
 CONFIG_SYS_CLK_DIV
 CONFIG_SYS_CLK_FREQ_C100
 CONFIG_SYS_CLK_FREQ_C110
 CONFIG_SYS_CMD_CONFIGURE
 CONFIG_SYS_CMD_EL
 CONFIG_SYS_CMD_IAS
 CONFIG_SYS_CMD_INT
 CONFIG_SYS_CMD_SUSPEND
 CONFIG_SYS_CMXFCR_MASK1
 CONFIG_SYS_CMXFCR_MASK2
 CONFIG_SYS_CMXFCR_MASK3
 CONFIG_SYS_CMXFCR_VALUE1
 CONFIG_SYS_CMXFCR_VALUE2
 CONFIG_SYS_CMXFCR_VALUE3
 CONFIG_SYS_CMXSCR_VALUE
 CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 CONFIG_SYS_CONSOLE_INFO_QUIET
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 CONFIG_SYS_CORE_SRAM
 CONFIG_SYS_CORE_SRAM_SIZE
 CONFIG_SYS_CORTEX_R4
 CONFIG_SYS_CORTINA_FW_IN_MMC
 CONFIG_SYS_CORTINA_FW_IN_NAND
 CONFIG_SYS_CORTINA_FW_IN_NOR
 CONFIG_SYS_CORTINA_FW_IN_REMOTE
 CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 CONFIG_SYS_CPC_REINIT_F
 CONFIG_SYS_CPLD
 CONFIG_SYS_CPLD_ADDR
 CONFIG_SYS_CPLD_AMASK
 CONFIG_SYS_CPLD_BASE
 CONFIG_SYS_CPLD_BASE_PHYS
 CONFIG_SYS_CPLD_CSOR
 CONFIG_SYS_CPLD_CSPR
 CONFIG_SYS_CPLD_CSPR_EXT
 CONFIG_SYS_CPLD_DATA
 CONFIG_SYS_CPLD_FTIM0
 CONFIG_SYS_CPLD_FTIM1
 CONFIG_SYS_CPLD_FTIM2
 CONFIG_SYS_CPLD_FTIM3
 CONFIG_SYS_CPLD_SIZE
 CONFIG_SYS_CPMFCR_RAMTYPE
 CONFIG_SYS_CPM_BOOTCOUNT_ADDR
 CONFIG_SYS_CPM_INTERRUPT
 CONFIG_SYS_CPM_POST_WORD_ADDR
 CONFIG_SYS_CPRI
 CONFIG_SYS_CPRI_CLK
 CONFIG_SYS_CPUSPEED
 CONFIG_SYS_CPU_CLK
 CONFIG_SYS_CPU_PCI_IO_START
 CONFIG_SYS_CPU_PCI_MEMIO_START
 CONFIG_SYS_CPU_PCI_MEM_START
 CONFIG_SYS_CS0_BASE
 CONFIG_SYS_CS0_CFG
 CONFIG_SYS_CS0_CTRL
 CONFIG_SYS_CS0_FTIM0
 CONFIG_SYS_CS0_FTIM1
 CONFIG_SYS_CS0_FTIM2
 CONFIG_SYS_CS0_FTIM3
 CONFIG_SYS_CS0_MASK
 CONFIG_SYS_CS0_SIZE
 CONFIG_SYS_CS0_START
 CONFIG_SYS_CS1_BASE
 CONFIG_SYS_CS1_CFG
 CONFIG_SYS_CS1_CTRL
 CONFIG_SYS_CS1_FLASH_BASE
 CONFIG_SYS_CS1_FTIM0
 CONFIG_SYS_CS1_FTIM1
 CONFIG_SYS_CS1_FTIM2
 CONFIG_SYS_CS1_FTIM3
 CONFIG_SYS_CS1_MASK
 CONFIG_SYS_CS1_SIZE
 CONFIG_SYS_CS1_START
 CONFIG_SYS_CS2_BASE
 CONFIG_SYS_CS2_CFG
 CONFIG_SYS_CS2_CTRL
 CONFIG_SYS_CS2_FLASH_BASE
 CONFIG_SYS_CS2_FTIM0
 CONFIG_SYS_CS2_FTIM1
 CONFIG_SYS_CS2_FTIM2
 CONFIG_SYS_CS2_FTIM3
 CONFIG_SYS_CS2_MASK
 CONFIG_SYS_CS2_SIZE
 CONFIG_SYS_CS2_START
 CONFIG_SYS_CS3_BASE
 CONFIG_SYS_CS3_CFG
 CONFIG_SYS_CS3_CTRL
 CONFIG_SYS_CS3_FLASH_BASE
 CONFIG_SYS_CS3_FTIM0
 CONFIG_SYS_CS3_FTIM1
 CONFIG_SYS_CS3_FTIM2
 CONFIG_SYS_CS3_FTIM3
 CONFIG_SYS_CS3_MASK
 CONFIG_SYS_CS3_SIZE
 CONFIG_SYS_CS3_START
 CONFIG_SYS_CS4_BASE
 CONFIG_SYS_CS4_CFG
 CONFIG_SYS_CS4_CTRL
 CONFIG_SYS_CS4_FLASH_BASE
 CONFIG_SYS_CS4_FTIM0
 CONFIG_SYS_CS4_FTIM1
 CONFIG_SYS_CS4_FTIM2
 CONFIG_SYS_CS4_FTIM3
 CONFIG_SYS_CS4_MASK
 CONFIG_SYS_CS4_SIZE
 CONFIG_SYS_CS4_START
 CONFIG_SYS_CS5_BASE
 CONFIG_SYS_CS5_CFG
 CONFIG_SYS_CS5_CTRL
 CONFIG_SYS_CS5_FLASH_BASE
 CONFIG_SYS_CS5_FTIM0
 CONFIG_SYS_CS5_FTIM1
 CONFIG_SYS_CS5_FTIM2
 CONFIG_SYS_CS5_FTIM3
 CONFIG_SYS_CS5_MASK
 CONFIG_SYS_CS5_SIZE
 CONFIG_SYS_CS5_START
 CONFIG_SYS_CS6_BASE
 CONFIG_SYS_CS6_CFG
 CONFIG_SYS_CS6_CTRL
 CONFIG_SYS_CS6_FTIM0
 CONFIG_SYS_CS6_FTIM1
 CONFIG_SYS_CS6_FTIM2
 CONFIG_SYS_CS6_FTIM3
 CONFIG_SYS_CS6_MASK
 CONFIG_SYS_CS6_SIZE
 CONFIG_SYS_CS6_START
 CONFIG_SYS_CS7_BASE
 CONFIG_SYS_CS7_CFG
 CONFIG_SYS_CS7_CTRL
 CONFIG_SYS_CS7_FTIM0
 CONFIG_SYS_CS7_FTIM1
 CONFIG_SYS_CS7_FTIM2
 CONFIG_SYS_CS7_FTIM3
 CONFIG_SYS_CS7_MASK
 CONFIG_SYS_CS7_SIZE
 CONFIG_SYS_CS7_START
 CONFIG_SYS_CSOR0
 CONFIG_SYS_CSOR0_EXT
 CONFIG_SYS_CSOR1
 CONFIG_SYS_CSOR1_EXT
 CONFIG_SYS_CSOR2
 CONFIG_SYS_CSOR2_EXT
 CONFIG_SYS_CSOR3
 CONFIG_SYS_CSOR3_EXT
 CONFIG_SYS_CSOR4
 CONFIG_SYS_CSOR4_EXT
 CONFIG_SYS_CSOR5
 CONFIG_SYS_CSOR5_EXT
 CONFIG_SYS_CSOR6
 CONFIG_SYS_CSOR6_EXT
 CONFIG_SYS_CSOR7
 CONFIG_SYS_CSOR7_EXT
 CONFIG_SYS_CSPR0
 CONFIG_SYS_CSPR0_EXT
 CONFIG_SYS_CSPR0_FINAL
 CONFIG_SYS_CSPR1
 CONFIG_SYS_CSPR1_EXT
 CONFIG_SYS_CSPR1_FINAL
 CONFIG_SYS_CSPR2
 CONFIG_SYS_CSPR2_EXT
 CONFIG_SYS_CSPR2_FINAL
 CONFIG_SYS_CSPR3
 CONFIG_SYS_CSPR3_EXT
 CONFIG_SYS_CSPR3_FINAL
 CONFIG_SYS_CSPR4
 CONFIG_SYS_CSPR4_EXT
 CONFIG_SYS_CSPR5
 CONFIG_SYS_CSPR5_EXT
 CONFIG_SYS_CSPR6
 CONFIG_SYS_CSPR6_EXT
 CONFIG_SYS_CSPR7
 CONFIG_SYS_CSPR7_EXT
 CONFIG_SYS_CS_ALETIMING
 CONFIG_SYS_CS_BURST
 CONFIG_SYS_CS_DEADCYCLE
 CONFIG_SYS_CS_HOLDCYCLE
 CONFIG_SYS_DA850_CS2CFG
 CONFIG_SYS_DA850_CS3CFG
 CONFIG_SYS_DA850_DDR2_DDRPHYCR
 CONFIG_SYS_DA850_DDR2_PBBPR
 CONFIG_SYS_DA850_DDR2_SDBCR
 CONFIG_SYS_DA850_DDR2_SDBCR2
 CONFIG_SYS_DA850_DDR2_SDRCR
 CONFIG_SYS_DA850_DDR2_SDTIMR
 CONFIG_SYS_DA850_DDR2_SDTIMR2
 CONFIG_SYS_DA850_DDR_INIT
 CONFIG_SYS_DA850_PLL0_PLLDIV1
 CONFIG_SYS_DA850_PLL0_PLLDIV2
 CONFIG_SYS_DA850_PLL0_PLLDIV3
 CONFIG_SYS_DA850_PLL0_PLLDIV4
 CONFIG_SYS_DA850_PLL0_PLLDIV5
 CONFIG_SYS_DA850_PLL0_PLLDIV6
 CONFIG_SYS_DA850_PLL0_PLLDIV7
 CONFIG_SYS_DA850_PLL0_PLLM
 CONFIG_SYS_DA850_PLL0_POSTDIV
 CONFIG_SYS_DA850_PLL0_PREDIV
 CONFIG_SYS_DA850_PLL1_PLLDIV1
 CONFIG_SYS_DA850_PLL1_PLLDIV2
 CONFIG_SYS_DA850_PLL1_PLLDIV3
 CONFIG_SYS_DA850_PLL1_PLLM
 CONFIG_SYS_DA850_PLL1_POSTDIV
 CONFIG_SYS_DA850_PLL_INIT
 CONFIG_SYS_DA850_SYSCFG_SUSPSRC
 CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0
 CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
 CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
 CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
 CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
 CONFIG_SYS_DAVINCI_I2C_SLAVE
 CONFIG_SYS_DAVINCI_I2C_SLAVE1
 CONFIG_SYS_DAVINCI_I2C_SLAVE2
 CONFIG_SYS_DAVINCI_I2C_SPEED
 CONFIG_SYS_DAVINCI_I2C_SPEED1
 CONFIG_SYS_DAVINCI_I2C_SPEED2
 CONFIG_SYS_DBAT
 CONFIG_SYS_DBAT0L
 CONFIG_SYS_DBAT0U
 CONFIG_SYS_DBAT1L
 CONFIG_SYS_DBAT1U
 CONFIG_SYS_DBAT2L
 CONFIG_SYS_DBAT2U
 CONFIG_SYS_DBAT3L
 CONFIG_SYS_DBAT3U
 CONFIG_SYS_DBAT4L
 CONFIG_SYS_DBAT4U
 CONFIG_SYS_DBAT5L
 CONFIG_SYS_DBAT5U
 CONFIG_SYS_DBAT6L
 CONFIG_SYS_DBAT6L_EARLY
 CONFIG_SYS_DBAT6U
 CONFIG_SYS_DBAT6U_EARLY
 CONFIG_SYS_DBAT7L
 CONFIG_SYS_DBAT7U
 CONFIG_SYS_DCACHE_INV
 CONFIG_SYS_DCACHE_LINESZ
 CONFIG_SYS_DCACHE_SACR_VALUE
 CONFIG_SYS_DCSRBAR
 CONFIG_SYS_DCSRBAR_PHYS
 CONFIG_SYS_DCSR_COP_CCP_ADDR
 CONFIG_SYS_DCSR_DCFG_ADDR
 CONFIG_SYS_DCSR_DCFG_OFFSET
 CONFIG_SYS_DCU_ADDR
 CONFIG_SYS_DDR1_CS0_BNDS
 CONFIG_SYS_DDR2_CFG_1A
 CONFIG_SYS_DDR2_CFG_1B
 CONFIG_SYS_DDR2_CFG_2
 CONFIG_SYS_DDR2_CLK_CTRL
 CONFIG_SYS_DDR2_CS0_BNDS
 CONFIG_SYS_DDR2_CS0_CONFIG
 CONFIG_SYS_DDR2_CS1_BNDS
 CONFIG_SYS_DDR2_CS1_CONFIG
 CONFIG_SYS_DDR2_CS2_BNDS
 CONFIG_SYS_DDR2_CS2_CONFIG
 CONFIG_SYS_DDR2_CS3_BNDS
 CONFIG_SYS_DDR2_CS3_CONFIG
 CONFIG_SYS_DDR2_DATA_INIT
 CONFIG_SYS_DDR2_EXT_REFRESH
 CONFIG_SYS_DDR2_INTERVAL
 CONFIG_SYS_DDR2_MODE_1
 CONFIG_SYS_DDR2_MODE_2
 CONFIG_SYS_DDR2_MODE_CTL
 CONFIG_SYS_DDR2_TIMING_0
 CONFIG_SYS_DDR2_TIMING_1
 CONFIG_SYS_DDR2_TIMING_2
 CONFIG_SYS_DDRCDR
 CONFIG_SYS_DDRCDR_VALUE
 CONFIG_SYS_DDRCMD_EM2
 CONFIG_SYS_DDRCMD_EM3
 CONFIG_SYS_DDRCMD_EN_DLL
 CONFIG_SYS_DDRCMD_NOP
 CONFIG_SYS_DDRCMD_OCD_DEFAULT
 CONFIG_SYS_DDRCMD_OCD_EXIT
 CONFIG_SYS_DDRCMD_PCHG_ALL
 CONFIG_SYS_DDRCMD_RES_DLL
 CONFIG_SYS_DDRCMD_RFSH
 CONFIG_SYS_DDRD
 CONFIG_SYS_DDRTC
 CONFIG_SYS_DDRUA
 CONFIG_SYS_DDR_BASE
 CONFIG_SYS_DDR_BLOCK1_SIZE
 CONFIG_SYS_DDR_BLOCK2_BASE
 CONFIG_SYS_DDR_CACHED_ADDR
 CONFIG_SYS_DDR_CDR_1
 CONFIG_SYS_DDR_CDR_2
 CONFIG_SYS_DDR_CFG_1A
 CONFIG_SYS_DDR_CFG_1B
 CONFIG_SYS_DDR_CFG_2
 CONFIG_SYS_DDR_CLKSEL
 CONFIG_SYS_DDR_CLK_CNTL
 CONFIG_SYS_DDR_CLK_CONTROL
 CONFIG_SYS_DDR_CLK_CTRL
 CONFIG_SYS_DDR_CLK_CTRL_1000
 CONFIG_SYS_DDR_CLK_CTRL_1200
 CONFIG_SYS_DDR_CLK_CTRL_1333
 CONFIG_SYS_DDR_CLK_CTRL_667
 CONFIG_SYS_DDR_CLK_CTRL_800
 CONFIG_SYS_DDR_CLK_CTRL_900
 CONFIG_SYS_DDR_CONFIG
 CONFIG_SYS_DDR_CONFIG_2
 CONFIG_SYS_DDR_CONFIG_256
 CONFIG_SYS_DDR_CONTROL
 CONFIG_SYS_DDR_CONTROL2
 CONFIG_SYS_DDR_CONTROL_1333
 CONFIG_SYS_DDR_CONTROL_2
 CONFIG_SYS_DDR_CONTROL_2_1333
 CONFIG_SYS_DDR_CONTROL_2_800
 CONFIG_SYS_DDR_CONTROL_800
 CONFIG_SYS_DDR_CPO
 CONFIG_SYS_DDR_CS0_BNDS
 CONFIG_SYS_DDR_CS0_CONFIG
 CONFIG_SYS_DDR_CS0_CONFIG_1333
 CONFIG_SYS_DDR_CS0_CONFIG_2
 CONFIG_SYS_DDR_CS0_CONFIG_800
 CONFIG_SYS_DDR_CS1_BNDS
 CONFIG_SYS_DDR_CS1_CONFIG
 CONFIG_SYS_DDR_CS1_CONFIG_2
 CONFIG_SYS_DDR_CS2_BNDS
 CONFIG_SYS_DDR_CS2_CONFIG
 CONFIG_SYS_DDR_CS3_BNDS
 CONFIG_SYS_DDR_CS3_CONFIG
 CONFIG_SYS_DDR_DATA_INIT
 CONFIG_SYS_DDR_ERR_DIS
 CONFIG_SYS_DDR_ERR_INT_EN
 CONFIG_SYS_DDR_INIT_ADDR
 CONFIG_SYS_DDR_INIT_EXT_ADDR
 CONFIG_SYS_DDR_INTERVAL
 CONFIG_SYS_DDR_INTERVAL_1000
 CONFIG_SYS_DDR_INTERVAL_1200
 CONFIG_SYS_DDR_INTERVAL_1333
 CONFIG_SYS_DDR_INTERVAL_667
 CONFIG_SYS_DDR_INTERVAL_800
 CONFIG_SYS_DDR_INTERVAL_900
 CONFIG_SYS_DDR_MODE
 CONFIG_SYS_DDR_MODE2
 CONFIG_SYS_DDR_MODE_1
 CONFIG_SYS_DDR_MODE_1_1000
 CONFIG_SYS_DDR_MODE_1_1200
 CONFIG_SYS_DDR_MODE_1_1333
 CONFIG_SYS_DDR_MODE_1_667
 CONFIG_SYS_DDR_MODE_1_800
 CONFIG_SYS_DDR_MODE_1_900
 CONFIG_SYS_DDR_MODE_2
 CONFIG_SYS_DDR_MODE_2_1000
 CONFIG_SYS_DDR_MODE_2_1200
 CONFIG_SYS_DDR_MODE_2_1333
 CONFIG_SYS_DDR_MODE_2_667
 CONFIG_SYS_DDR_MODE_2_800
 CONFIG_SYS_DDR_MODE_2_900
 CONFIG_SYS_DDR_MODE_CONTROL
 CONFIG_SYS_DDR_MODE_CTL
 CONFIG_SYS_DDR_MODE_WEAK
 CONFIG_SYS_DDR_OCD_CTRL
 CONFIG_SYS_DDR_OCD_STATUS
 CONFIG_SYS_DDR_RAW_TIMING
 CONFIG_SYS_DDR_RCW_1
 CONFIG_SYS_DDR_RCW_2
 CONFIG_SYS_DDR_SBE
 CONFIG_SYS_DDR_SDRAM_BASE
 CONFIG_SYS_DDR_SDRAM_BASE2
 CONFIG_SYS_DDR_SDRAM_CFG
 CONFIG_SYS_DDR_SDRAM_CFG2
 CONFIG_SYS_DDR_SDRAM_CFG_2
 CONFIG_SYS_DDR_SDRAM_CLK_CNTL
 CONFIG_SYS_DDR_SDRAM_INTERVAL
 CONFIG_SYS_DDR_SDRAM_MODE
 CONFIG_SYS_DDR_SDRAM_MODE_2
 CONFIG_SYS_DDR_SIZE
 CONFIG_SYS_DDR_SR_CNTR
 CONFIG_SYS_DDR_TIMING_0
 CONFIG_SYS_DDR_TIMING_0_1000
 CONFIG_SYS_DDR_TIMING_0_1200
 CONFIG_SYS_DDR_TIMING_0_1333
 CONFIG_SYS_DDR_TIMING_0_667
 CONFIG_SYS_DDR_TIMING_0_800
 CONFIG_SYS_DDR_TIMING_0_900
 CONFIG_SYS_DDR_TIMING_1
 CONFIG_SYS_DDR_TIMING_1_1000
 CONFIG_SYS_DDR_TIMING_1_1200
 CONFIG_SYS_DDR_TIMING_1_1333
 CONFIG_SYS_DDR_TIMING_1_667
 CONFIG_SYS_DDR_TIMING_1_800
 CONFIG_SYS_DDR_TIMING_1_900
 CONFIG_SYS_DDR_TIMING_2
 CONFIG_SYS_DDR_TIMING_2_1000
 CONFIG_SYS_DDR_TIMING_2_1200
 CONFIG_SYS_DDR_TIMING_2_1333
 CONFIG_SYS_DDR_TIMING_2_667
 CONFIG_SYS_DDR_TIMING_2_800
 CONFIG_SYS_DDR_TIMING_2_900
 CONFIG_SYS_DDR_TIMING_3
 CONFIG_SYS_DDR_TIMING_3_1000
 CONFIG_SYS_DDR_TIMING_3_1200
 CONFIG_SYS_DDR_TIMING_3_1333
 CONFIG_SYS_DDR_TIMING_3_667
 CONFIG_SYS_DDR_TIMING_3_800
 CONFIG_SYS_DDR_TIMING_3_900
 CONFIG_SYS_DDR_TIMING_4
 CONFIG_SYS_DDR_TIMING_4_1333
 CONFIG_SYS_DDR_TIMING_4_800
 CONFIG_SYS_DDR_TIMING_5
 CONFIG_SYS_DDR_TIMING_5_1333
 CONFIG_SYS_DDR_TIMING_5_800
 CONFIG_SYS_DDR_WRITE_DATA_DELAY
 CONFIG_SYS_DDR_WRLVL_CNTL
 CONFIG_SYS_DDR_WRLVL_CONTROL
 CONFIG_SYS_DDR_WRLVL_CONTROL_1333
 CONFIG_SYS_DDR_WRLVL_CONTROL_667
 CONFIG_SYS_DDR_WRLVL_CONTROL_800
 CONFIG_SYS_DDR_ZQ_CNTL
 CONFIG_SYS_DDR_ZQ_CONTROL
 CONFIG_SYS_DEBUG
 CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
 CONFIG_SYS_DEBUG_SERVER_FW_ADDR
 CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 CONFIG_SYS_DEBUG_SERVER_TIMEOUT
 CONFIG_SYS_DECREMENT_PATTERNS
 CONFIG_SYS_DEFAULT_IMMR
 CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 CONFIG_SYS_DEFAULT_MBAR
 CONFIG_SYS_DEFAULT_VIDEO_MODE
 CONFIG_SYS_DEF_EEPROM_ADDR
 CONFIG_SYS_DELAYED_ICACHE
 CONFIG_SYS_DER
 CONFIG_SYS_DEVICE_NULLDEV
 CONFIG_SYS_DFU_DATA_BUF_SIZE
 CONFIG_SYS_DFU_MAX_FILE_SIZE
 CONFIG_SYS_DIAG_ADDR
 CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
 CONFIG_SYS_DIMM_SLOTS_PER_CTLR
 CONFIG_SYS_DIRECT_FLASH_NFS
 CONFIG_SYS_DIRECT_FLASH_TFTP
 CONFIG_SYS_DISCOVER_PHY
 CONFIG_SYS_DISPLAY_BASE
 CONFIG_SYS_DISP_CHR_RAM
 CONFIG_SYS_DIU_ADDR
 CONFIG_SYS_DM36x_PINMUX0
 CONFIG_SYS_DM36x_PINMUX1
 CONFIG_SYS_DM36x_PINMUX2
 CONFIG_SYS_DM36x_PINMUX3
 CONFIG_SYS_DM36x_PINMUX4
 CONFIG_SYS_DM36x_PLL1_PREDIV
 CONFIG_SYS_DM36x_PLL2_PREDIV
 CONFIG_SYS_DMA_USE_INTSRAM
 CONFIG_SYS_DOC_SHORT_TIMEOUT
 CONFIG_SYS_DOC_SUPPORT_2000
 CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 CONFIG_SYS_DP501_BASE
 CONFIG_SYS_DP501_DIFFERENTIAL
 CONFIG_SYS_DP501_I2C
 CONFIG_SYS_DP501_VCAPCTRL0
 CONFIG_SYS_DPAA_DCE
 CONFIG_SYS_DPAA_FMAN
 CONFIG_SYS_DPAA_PME
 CONFIG_SYS_DPAA_QBMAN
 CONFIG_SYS_DPAA_RMAN
 CONFIG_SYS_DP_DDR_BASE
 CONFIG_SYS_DP_DDR_BASE_PHY
 CONFIG_SYS_DRAMSZ
 CONFIG_SYS_DRAMSZ1
 CONFIG_SYS_DRAM_BASE
 CONFIG_SYS_DRAM_SIZE
 CONFIG_SYS_DRAM_TEST
 CONFIG_SYS_DS1339_TCR_VAL
 CONFIG_SYS_DS1388_TCR_VAL
 CONFIG_SYS_DSPIC_TEST_ADDR
 CONFIG_SYS_DSPIC_TEST_MASK
 CONFIG_SYS_DSPI_CS0
 CONFIG_SYS_DSPI_CS2
 CONFIG_SYS_DSPI_CTAR0
 CONFIG_SYS_DSPI_CTAR1
 CONFIG_SYS_DSPI_CTAR2
 CONFIG_SYS_DSPI_CTAR3
 CONFIG_SYS_DSPI_CTAR4
 CONFIG_SYS_DSPI_CTAR5
 CONFIG_SYS_DSPI_CTAR6
 CONFIG_SYS_DSPI_CTAR7
 CONFIG_SYS_DTT_ADM1021
 CONFIG_SYS_DTT_BUS_NUM
 CONFIG_SYS_DTT_HYSTERESIS
 CONFIG_SYS_DTT_LOW_TEMP
 CONFIG_SYS_DTT_MAX_TEMP
 CONFIG_SYS_DTT_MIN_TEMP
 CONFIG_SYS_DUART_RST
 CONFIG_SYS_DV_CLKMODE
 CONFIG_SYS_DV_NOR_BOOT_CFG
 CONFIG_SYS_EBC_CFG
 CONFIG_SYS_EBC_PB0AP
 CONFIG_SYS_EBC_PB0CR
 CONFIG_SYS_EBC_PB1AP
 CONFIG_SYS_EBC_PB1CR
 CONFIG_SYS_EBC_PB2AP
 CONFIG_SYS_EBC_PB2CR
 CONFIG_SYS_EBC_PB3AP
 CONFIG_SYS_EBC_PB3CR
 CONFIG_SYS_EBC_PB4AP
 CONFIG_SYS_EBC_PB4CR
 CONFIG_SYS_EBC_PB5AP
 CONFIG_SYS_EBC_PB5CR
 CONFIG_SYS_EBC_PB6AP
 CONFIG_SYS_EBC_PB6CR
 CONFIG_SYS_EBC_PB7AP
 CONFIG_SYS_EBC_PB7CR
 CONFIG_SYS_EBI_CFGR_VAL
 CONFIG_SYS_EBI_CSA_VAL
 CONFIG_SYS_EEPROM_BASE
 CONFIG_SYS_EEPROM_BUS_NUM
 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
 CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 CONFIG_SYS_EEPROM_SIZE
 CONFIG_SYS_EEPROM_WP
 CONFIG_SYS_EEPROM_WREN
 CONFIG_SYS_EHCI_USB1_ADDR
 CONFIG_SYS_ELBC_BASE
 CONFIG_SYS_ELBC_BASE_PHYS
 CONFIG_SYS_ELO3_DMA3
 CONFIG_SYS_ELPIDA_INIT_DEV_OP
 CONFIG_SYS_ELPIDA_OCD_EXIT
 CONFIG_SYS_ELPIDA_RES_DLL
 CONFIG_SYS_EMAC_TI_CLKDIV
 CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 CONFIG_SYS_ENABLE_PADS_ALL
 CONFIG_SYS_ENET_BD_BASE
 CONFIG_SYS_ENV_ADDR
 CONFIG_SYS_ENV_OFFSET
 CONFIG_SYS_ENV_SECT_SIZE
 CONFIG_SYS_EPLD_BASE
 CONFIG_SYS_ETHOC_BASE
 CONFIG_SYS_ETHOC_BUFFER_ADDR
 CONFIG_SYS_ETH_IOBASE
 CONFIG_SYS_ETVPE_CLK
 CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 CONFIG_SYS_EXTBDINFO
 CONFIG_SYS_EXTRA_ENV_RELOC
 CONFIG_SYS_EXT_SERIAL_CLOCK
 CONFIG_SYS_FAST_CLK
 CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 CONFIG_SYS_FAULT_MII_ADDR
 CONFIG_SYS_FCC_PSMR
 CONFIG_SYS_FCPU133MHZ
 CONFIG_SYS_FCPU266MHZ
 CONFIG_SYS_FCPU333MHZ
 CONFIG_SYS_FDC_DRIVE_NUMBER
 CONFIG_SYS_FDC_HW_INIT
 CONFIG_SYS_FDT_ADDR
 CONFIG_SYS_FDT_BASE
 CONFIG_SYS_FDT_LOAD_ADDR
 CONFIG_SYS_FDT_PAD
 CONFIG_SYS_FDT_SIZE
 CONFIG_SYS_FEC0_IOBASE
 CONFIG_SYS_FEC0_MIIBASE
 CONFIG_SYS_FEC0_PHYADDR
 CONFIG_SYS_FEC0_PINMUX
 CONFIG_SYS_FEC1_IOBASE
 CONFIG_SYS_FEC1_MIIBASE
 CONFIG_SYS_FEC1_PHYADDR
 CONFIG_SYS_FEC1_PINMUX
 CONFIG_SYS_FECI2C
 CONFIG_SYS_FEC_BUF_USE_SRAM
 CONFIG_SYS_FEC_FULL_MII
 CONFIG_SYS_FEC_NO_SHARED_PHY
 CONFIG_SYS_FIFO_BASE
 CONFIG_SYS_FIXED_PHY_ADDR
 CONFIG_SYS_FIXED_PHY_PORT
 CONFIG_SYS_FIXED_PHY_PORTS
 CONFIG_SYS_FLASH
 CONFIG_SYS_FLASH0
 CONFIG_SYS_FLASH0_BASE
 CONFIG_SYS_FLASH1
 CONFIG_SYS_FLASH1_BASE
 CONFIG_SYS_FLASH1_BASE_PHYS
 CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
 CONFIG_SYS_FLASH2_BASE
 CONFIG_SYS_FLASHBOOT
 CONFIG_SYS_FLASH_2ND_16BIT_DEV
 CONFIG_SYS_FLASH_2ND_ADDR
 CONFIG_SYS_FLASH_ADDR0
 CONFIG_SYS_FLASH_ADDR1
 CONFIG_SYS_FLASH_ADDR_BASE
 CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 CONFIG_SYS_FLASH_AUTOPROTECT_LIST
 CONFIG_SYS_FLASH_BANKS_LIST
 CONFIG_SYS_FLASH_BANKS_SIZES
 CONFIG_SYS_FLASH_BANK_SIZE
 CONFIG_SYS_FLASH_BASE
 CONFIG_SYS_FLASH_BASE0
 CONFIG_SYS_FLASH_BASE1
 CONFIG_SYS_FLASH_BASE2
 CONFIG_SYS_FLASH_BASE_1
 CONFIG_SYS_FLASH_BASE_2
 CONFIG_SYS_FLASH_BASE_CS1
 CONFIG_SYS_FLASH_BASE_PHYS
 CONFIG_SYS_FLASH_BASE_PHYS_EARLY
 CONFIG_SYS_FLASH_BASE_PHYS_H
 CONFIG_SYS_FLASH_BASE_PHYS_L
 CONFIG_SYS_FLASH_BASE_PHYS_LOW
 CONFIG_SYS_FLASH_BR_PRELIM
 CONFIG_SYS_FLASH_CFI
 CONFIG_SYS_FLASH_CFI_AMD_RESET
 CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
 CONFIG_SYS_FLASH_CFI_BYPASS_READ
 CONFIG_SYS_FLASH_CFI_NONBLOCK
 CONFIG_SYS_FLASH_CFI_WIDTH
 CONFIG_SYS_FLASH_CHECKSUM
 CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE
 CONFIG_SYS_FLASH_EMPTY_INFO
 CONFIG_SYS_FLASH_ERASE_TOUT
 CONFIG_SYS_FLASH_LEGACY_256Kx8
 CONFIG_SYS_FLASH_LEGACY_512Kx16
 CONFIG_SYS_FLASH_LEGACY_512Kx8
 CONFIG_SYS_FLASH_LOCK_TOUT
 CONFIG_SYS_FLASH_OR_PRELIM
 CONFIG_SYS_FLASH_PARMSECT_SZ
 CONFIG_SYS_FLASH_PROTECTION
 CONFIG_SYS_FLASH_QUIET_TEST
 CONFIG_SYS_FLASH_READ0
 CONFIG_SYS_FLASH_READ1
 CONFIG_SYS_FLASH_READ2
 CONFIG_SYS_FLASH_SECT_SIZE
 CONFIG_SYS_FLASH_SECT_SZ
 CONFIG_SYS_FLASH_SIZE
 CONFIG_SYS_FLASH_SIZE_1
 CONFIG_SYS_FLASH_SIZE_2
 CONFIG_SYS_FLASH_UNLOCK_TOUT
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE
 CONFIG_SYS_FLASH_WORD_SIZE
 CONFIG_SYS_FLASH_WRITE_TOUT
 CONFIG_SYS_FLYCNFG_VAL
 CONFIG_SYS_FM1_10GEC1_PHY_ADDR
 CONFIG_SYS_FM1_10GEC2_PHY_ADDR
 CONFIG_SYS_FM1_CLK
 CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR
 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC2_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC3_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR
 CONFIG_SYS_FM1_DTSEC_MDIO_ADDR
 CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR
 CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR
 CONFIG_SYS_FM1_QSGMII11_PHY_ADDR
 CONFIG_SYS_FM1_QSGMII21_PHY_ADDR
 CONFIG_SYS_FM1_TGEC_MDIO_ADDR
 CONFIG_SYS_FM2_10GEC1_PHY_ADDR
 CONFIG_SYS_FM2_CLK
 CONFIG_SYS_FM2_DTSEC1_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC2_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC3_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC4_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC_MDIO_ADDR
 CONFIG_SYS_FM2_TGEC_MDIO_ADDR
 CONFIG_SYS_FMAN_FW_ADDR
 CONFIG_SYS_FMAN_V3
 CONFIG_SYS_FM_MURAM_SIZE
 CONFIG_SYS_FORM_3U_CPCI
 CONFIG_SYS_FORM_3U_VPX
 CONFIG_SYS_FORM_6U_CPCI
 CONFIG_SYS_FORM_6U_VPX
 CONFIG_SYS_FORM_AMC
 CONFIG_SYS_FORM_ATCA_AMC
 CONFIG_SYS_FORM_ATCA_PMC
 CONFIG_SYS_FORM_CUSTOM
 CONFIG_SYS_FORM_PCI
 CONFIG_SYS_FORM_PCI_EXPRESS
 CONFIG_SYS_FORM_PMC
 CONFIG_SYS_FORM_PMC_XMC
 CONFIG_SYS_FORM_VME
 CONFIG_SYS_FORM_XMC
 CONFIG_SYS_FPGA0_BASE
 CONFIG_SYS_FPGA0_SIZE
 CONFIG_SYS_FPGA1_BASE
 CONFIG_SYS_FPGA2_BASE
 CONFIG_SYS_FPGA3_BASE
 CONFIG_SYS_FPGAREG_DATE
 CONFIG_SYS_FPGAREG_DIPSW
 CONFIG_SYS_FPGAREG_FREQ
 CONFIG_SYS_FPGAREG_RESET
 CONFIG_SYS_FPGAREG_RESET_CODE
 CONFIG_SYS_FPGA_AMASK
 CONFIG_SYS_FPGA_BASE
 CONFIG_SYS_FPGA_BASE0
 CONFIG_SYS_FPGA_BASE1
 CONFIG_SYS_FPGA_BASE_0
 CONFIG_SYS_FPGA_BASE_1
 CONFIG_SYS_FPGA_BASE_ADDR
 CONFIG_SYS_FPGA_BASE_PHYS
 CONFIG_SYS_FPGA_CHECK_BUSY
 CONFIG_SYS_FPGA_CHECK_CTRLC
 CONFIG_SYS_FPGA_CHECK_ERROR
 CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK
 CONFIG_SYS_FPGA_CLK
 CONFIG_SYS_FPGA_COMMON
 CONFIG_SYS_FPGA_COUNT
 CONFIG_SYS_FPGA_CSOR
 CONFIG_SYS_FPGA_CSPR
 CONFIG_SYS_FPGA_CSPR_EXT
 CONFIG_SYS_FPGA_CTRL
 CONFIG_SYS_FPGA_CTRL_CF_RESET
 CONFIG_SYS_FPGA_CTRL_PS2_RESET
 CONFIG_SYS_FPGA_CTRL_WDI
 CONFIG_SYS_FPGA_DATA
 CONFIG_SYS_FPGA_DONE
 CONFIG_SYS_FPGA_DPRAM_RST
 CONFIG_SYS_FPGA_DPRAM_RW_TYPE
 CONFIG_SYS_FPGA_DPRAM_R_INT_LINE
 CONFIG_SYS_FPGA_DPRAM_W_INT_LINE
 CONFIG_SYS_FPGA_FIFO_BASE
 CONFIG_SYS_FPGA_FTIM0
 CONFIG_SYS_FPGA_FTIM1
 CONFIG_SYS_FPGA_FTIM2
 CONFIG_SYS_FPGA_FTIM3
 CONFIG_SYS_FPGA_INIT
 CONFIG_SYS_FPGA_IS_PROTO
 CONFIG_SYS_FPGA_LINESIDE_LOOPBACK
 CONFIG_SYS_FPGA_MAGIC
 CONFIG_SYS_FPGA_MAGIC_MASK
 CONFIG_SYS_FPGA_MAX_SIZE
 CONFIG_SYS_FPGA_MODE
 CONFIG_SYS_FPGA_MODE_CF_RESET
 CONFIG_SYS_FPGA_MODE_DUART_RESET
 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT
 CONFIG_SYS_FPGA_MODE_TS_CLEAR
 CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR
 CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE
 CONFIG_SYS_FPGA_NO_RFL_HI
 CONFIG_SYS_FPGA_PHY0_INT
 CONFIG_SYS_FPGA_PHY1_INT
 CONFIG_SYS_FPGA_PRG
 CONFIG_SYS_FPGA_PROG
 CONFIG_SYS_FPGA_PROG_FEEDBACK
 CONFIG_SYS_FPGA_PROG_TIME
 CONFIG_SYS_FPGA_PTR
 CONFIG_SYS_FPGA_REG_BASE
 CONFIG_SYS_FPGA_REG_BASE_ADDR
 CONFIG_SYS_FPGA_SIZE
 CONFIG_SYS_FPGA_SLIC0_CS
 CONFIG_SYS_FPGA_SLIC0_ENABLE
 CONFIG_SYS_FPGA_SLIC0_INT
 CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT
 CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT
 CONFIG_SYS_FPGA_SLIC1_CS
 CONFIG_SYS_FPGA_SLIC1_ENABLE
 CONFIG_SYS_FPGA_SLIC1_INT
 CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT
 CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT
 CONFIG_SYS_FPGA_SPARTAN2
 CONFIG_SYS_FPGA_STATUS
 CONFIG_SYS_FPGA_STATUS_DIP0
 CONFIG_SYS_FPGA_STATUS_DIP1
 CONFIG_SYS_FPGA_STATUS_DIP2
 CONFIG_SYS_FPGA_STATUS_FLASH
 CONFIG_SYS_FPGA_STATUS_TS_IRQ
 CONFIG_SYS_FPGA_TS
 CONFIG_SYS_FPGA_TS_CAP0
 CONFIG_SYS_FPGA_TS_CAP0_LOW
 CONFIG_SYS_FPGA_TS_CAP1
 CONFIG_SYS_FPGA_TS_CAP1_LOW
 CONFIG_SYS_FPGA_TS_CAP2
 CONFIG_SYS_FPGA_TS_CAP2_LOW
 CONFIG_SYS_FPGA_TS_CAP3
 CONFIG_SYS_FPGA_TS_CAP3_LOW
 CONFIG_SYS_FPGA_TS_LOW
 CONFIG_SYS_FPGA_UART0_FO
 CONFIG_SYS_FPGA_UART1_FO
 CONFIG_SYS_FPGA_USER_LED0
 CONFIG_SYS_FPGA_USER_LED1
 CONFIG_SYS_FPGA_VER_MASK
 CONFIG_SYS_FPGA_WAIT
 CONFIG_SYS_FPGA_WAIT_BUSY
 CONFIG_SYS_FPGA_WAIT_CONFIG
 CONFIG_SYS_FPGA_WAIT_INIT
 CONFIG_SYS_FPGA_xxx
 CONFIG_SYS_FSL_A004447_SVR_REV
 CONFIG_SYS_FSL_AIOP1_BASE
 CONFIG_SYS_FSL_AIOP1_SIZE
 CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 CONFIG_SYS_FSL_BMAN_ADDR
 CONFIG_SYS_FSL_BMAN_OFFSET
 CONFIG_SYS_FSL_BOOTROM_BASE
 CONFIG_SYS_FSL_BOOTROM_SIZE
 CONFIG_SYS_FSL_CCSR_BASE
 CONFIG_SYS_FSL_CCSR_GUR_BE
 CONFIG_SYS_FSL_CCSR_GUR_LE
 CONFIG_SYS_FSL_CCSR_SCFG_BE
 CONFIG_SYS_FSL_CCSR_SCFG_LE
 CONFIG_SYS_FSL_CCSR_SIZE
 CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR
 CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR
 CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR
 CONFIG_SYS_FSL_CLK
 CONFIG_SYS_FSL_CLK_ADDR
 CONFIG_SYS_FSL_CLUSTER_1_L2
 CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET
 CONFIG_SYS_FSL_CLUSTER_CLOCKS
 CONFIG_SYS_FSL_CORENET_CCM_ADDR
 CONFIG_SYS_FSL_CORENET_CCM_OFFSET
 CONFIG_SYS_FSL_CORENET_CLK_ADDR
 CONFIG_SYS_FSL_CORENET_CLK_OFFSET
 CONFIG_SYS_FSL_CORENET_PMAN
 CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET
 CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET
 CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET
 CONFIG_SYS_FSL_CORENET_PME_ADDR
 CONFIG_SYS_FSL_CORENET_PME_OFFSET
 CONFIG_SYS_FSL_CORENET_RCPM_ADDR
 CONFIG_SYS_FSL_CORENET_RCPM_OFFSET
 CONFIG_SYS_FSL_CORENET_RMAN_ADDR
 CONFIG_SYS_FSL_CORENET_RMAN_OFFSET
 CONFIG_SYS_FSL_CORENET_SERDES2_ADDR
 CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET
 CONFIG_SYS_FSL_CORENET_SERDES3_ADDR
 CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET
 CONFIG_SYS_FSL_CORENET_SERDES4_ADDR
 CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET
 CONFIG_SYS_FSL_CORENET_SERDES_ADDR
 CONFIG_SYS_FSL_CORENET_SERDES_OFFSET
 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 CONFIG_SYS_FSL_CORES_PER_CLUSTER
 CONFIG_SYS_FSL_CPC
 CONFIG_SYS_FSL_CPC_ADDR
 CONFIG_SYS_FSL_CPC_OFFSET
 CONFIG_SYS_FSL_CSU_ADDR
 CONFIG_SYS_FSL_DCFG_ADDR
 CONFIG_SYS_FSL_DCSR_BASE
 CONFIG_SYS_FSL_DCSR_DDR2_ADDR
 CONFIG_SYS_FSL_DCSR_DDR3_ADDR
 CONFIG_SYS_FSL_DCSR_DDR4_ADDR
 CONFIG_SYS_FSL_DCSR_DDR_ADDR
 CONFIG_SYS_FSL_DCSR_SIZE
 CONFIG_SYS_FSL_DCU_BE
 CONFIG_SYS_FSL_DCU_LE
 CONFIG_SYS_FSL_DDR
 CONFIG_SYS_FSL_DDR1
 CONFIG_SYS_FSL_DDR2
 CONFIG_SYS_FSL_DDR2_ADDR
 CONFIG_SYS_FSL_DDR3
 CONFIG_SYS_FSL_DDR3L
 CONFIG_SYS_FSL_DDR3_ADDR
 CONFIG_SYS_FSL_DDR4
 CONFIG_SYS_FSL_DDRC_ARM_GEN3
 CONFIG_SYS_FSL_DDRC_GEN1
 CONFIG_SYS_FSL_DDRC_GEN2
 CONFIG_SYS_FSL_DDRC_GEN3
 CONFIG_SYS_FSL_DDRC_GEN4
 CONFIG_SYS_FSL_DDR_86XX
 CONFIG_SYS_FSL_DDR_ADDR
 CONFIG_SYS_FSL_DDR_BE
 CONFIG_SYS_FSL_DDR_EMU
 CONFIG_SYS_FSL_DDR_INTLV_256B
 CONFIG_SYS_FSL_DDR_LE
 CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
 CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
 CONFIG_SYS_FSL_DDR_VER
 CONFIG_SYS_FSL_DRAM_BASE1
 CONFIG_SYS_FSL_DRAM_BASE2
 CONFIG_SYS_FSL_DRAM_BASE3
 CONFIG_SYS_FSL_DRAM_SIZE1
 CONFIG_SYS_FSL_DRAM_SIZE2
 CONFIG_SYS_FSL_DRAM_SIZE3
 CONFIG_SYS_FSL_DSPI_BE
 CONFIG_SYS_FSL_DSP_CCSRBAR
 CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS
 CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
 CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
 CONFIG_SYS_FSL_DSP_DDR_ADDR
 CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
 CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
 CONFIG_SYS_FSL_ERRATUM_A004468
 CONFIG_SYS_FSL_ERRATUM_A004477
 CONFIG_SYS_FSL_ERRATUM_A004508
 CONFIG_SYS_FSL_ERRATUM_A004510
 CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
 CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
 CONFIG_SYS_FSL_ERRATUM_A004580
 CONFIG_SYS_FSL_ERRATUM_A004699
 CONFIG_SYS_FSL_ERRATUM_A004849
 CONFIG_SYS_FSL_ERRATUM_A005125
 CONFIG_SYS_FSL_ERRATUM_A005434
 CONFIG_SYS_FSL_ERRATUM_A005812
 CONFIG_SYS_FSL_ERRATUM_A005871
 CONFIG_SYS_FSL_ERRATUM_A006261
 CONFIG_SYS_FSL_ERRATUM_A006379
 CONFIG_SYS_FSL_ERRATUM_A006384
 CONFIG_SYS_FSL_ERRATUM_A006475
 CONFIG_SYS_FSL_ERRATUM_A006593
 CONFIG_SYS_FSL_ERRATUM_A007075
 CONFIG_SYS_FSL_ERRATUM_A007186
 CONFIG_SYS_FSL_ERRATUM_A007212
 CONFIG_SYS_FSL_ERRATUM_A007798
 CONFIG_SYS_FSL_ERRATUM_A008044
 CONFIG_SYS_FSL_ERRATUM_A008336
 CONFIG_SYS_FSL_ERRATUM_A008378
 CONFIG_SYS_FSL_ERRATUM_A008407
 CONFIG_SYS_FSL_ERRATUM_A008511
 CONFIG_SYS_FSL_ERRATUM_A008514
 CONFIG_SYS_FSL_ERRATUM_A008585
 CONFIG_SYS_FSL_ERRATUM_A008751
 CONFIG_SYS_FSL_ERRATUM_A008850
 CONFIG_SYS_FSL_ERRATUM_A009635
 CONFIG_SYS_FSL_ERRATUM_A009660
 CONFIG_SYS_FSL_ERRATUM_A009663
 CONFIG_SYS_FSL_ERRATUM_A009801
 CONFIG_SYS_FSL_ERRATUM_A009803
 CONFIG_SYS_FSL_ERRATUM_A009929
 CONFIG_SYS_FSL_ERRATUM_A009942
 CONFIG_SYS_FSL_ERRATUM_A010165
 CONFIG_SYS_FSL_ERRATUM_A_004934
 CONFIG_SYS_FSL_ERRATUM_CPC_A002
 CONFIG_SYS_FSL_ERRATUM_CPC_A003
 CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 CONFIG_SYS_FSL_ERRATUM_DDR_115
 CONFIG_SYS_FSL_ERRATUM_DDR_A003
 CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 CONFIG_SYS_FSL_ERRATUM_ESDHC111
 CONFIG_SYS_FSL_ERRATUM_ESDHC13
 CONFIG_SYS_FSL_ERRATUM_ESDHC135
 CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 CONFIG_SYS_FSL_ERRATUM_USB14
 CONFIG_SYS_FSL_ESDHC_ADDR
 CONFIG_SYS_FSL_ESDHC_BE
 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
 CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 CONFIG_SYS_FSL_ESDHC_LE
 CONFIG_SYS_FSL_ESDHC_NUM
 CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
 CONFIG_SYS_FSL_ESDHC_USE_PIO
 CONFIG_SYS_FSL_FM
 CONFIG_SYS_FSL_FM1_ADDR
 CONFIG_SYS_FSL_FM1_DTSEC1_ADDR
 CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
 CONFIG_SYS_FSL_FM1_OFFSET
 CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET
 CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET
 CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
 CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
 CONFIG_SYS_FSL_FM2_ADDR
 CONFIG_SYS_FSL_FM2_OFFSET
 CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET
 CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET
 CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
 CONFIG_SYS_FSL_FMAN_ADDR
 CONFIG_SYS_FSL_GUTS_ADDR
 CONFIG_SYS_FSL_HAS_DP_DDR
 CONFIG_SYS_FSL_I2C
 CONFIG_SYS_FSL_I2C2_OFFSET
 CONFIG_SYS_FSL_I2C2_SLAVE
 CONFIG_SYS_FSL_I2C2_SPEED
 CONFIG_SYS_FSL_I2C3_OFFSET
 CONFIG_SYS_FSL_I2C3_SLAVE
 CONFIG_SYS_FSL_I2C3_SPEED
 CONFIG_SYS_FSL_I2C4_OFFSET
 CONFIG_SYS_FSL_I2C4_SLAVE
 CONFIG_SYS_FSL_I2C4_SPEED
 CONFIG_SYS_FSL_I2C_OFFSET
 CONFIG_SYS_FSL_I2C_SLAVE
 CONFIG_SYS_FSL_I2C_SPEED
 CONFIG_SYS_FSL_IFC_BANK_COUNT
 CONFIG_SYS_FSL_IFC_BASE
 CONFIG_SYS_FSL_IFC_BASE1
 CONFIG_SYS_FSL_IFC_BASE2
 CONFIG_SYS_FSL_IFC_BE
 CONFIG_SYS_FSL_IFC_LE
 CONFIG_SYS_FSL_IFC_SIZE
 CONFIG_SYS_FSL_IFC_SIZE1
 CONFIG_SYS_FSL_IFC_SIZE1_1
 CONFIG_SYS_FSL_IFC_SIZE2
 CONFIG_SYS_FSL_ISBC_VER
 CONFIG_SYS_FSL_JR0_ADDR
 CONFIG_SYS_FSL_JR0_OFFSET
 CONFIG_SYS_FSL_LS1_CLK_ADDR
 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
 CONFIG_SYS_FSL_MAX_NUM_OF_SEC
 CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
 CONFIG_SYS_FSL_MC_BASE
 CONFIG_SYS_FSL_MC_SIZE
 CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 CONFIG_SYS_FSL_NI_BASE
 CONFIG_SYS_FSL_NI_SIZE
 CONFIG_SYS_FSL_NO_SERDES
 CONFIG_SYS_FSL_NUM_CC_PLL
 CONFIG_SYS_FSL_NUM_CC_PLLS
 CONFIG_SYS_FSL_NUM_LAWS
 CONFIG_SYS_FSL_OCRAM_BASE
 CONFIG_SYS_FSL_OCRAM_SIZE
 CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 CONFIG_SYS_FSL_PAMU_OFFSET
 CONFIG_SYS_FSL_PBL_PBI
 CONFIG_SYS_FSL_PBL_RCW
 CONFIG_SYS_FSL_PCIE_COMPAT
 CONFIG_SYS_FSL_PCI_VER_3_X
 CONFIG_SYS_FSL_PEBUF_BASE
 CONFIG_SYS_FSL_PEBUF_SIZE
 CONFIG_SYS_FSL_PEX_LUT_BE
 CONFIG_SYS_FSL_PEX_LUT_LE
 CONFIG_SYS_FSL_PMIC_I2C_ADDR
 CONFIG_SYS_FSL_PMU_ADDR
 CONFIG_SYS_FSL_PMU_CLTBENR
 CONFIG_SYS_FSL_QBMAN_BASE
 CONFIG_SYS_FSL_QBMAN_SIZE
 CONFIG_SYS_FSL_QBMAN_SIZE_1
 CONFIG_SYS_FSL_QMAN_ADDR
 CONFIG_SYS_FSL_QMAN_OFFSET
 CONFIG_SYS_FSL_QMAN_V3
 CONFIG_SYS_FSL_QORIQ_CHASSIS1
 CONFIG_SYS_FSL_QORIQ_CHASSIS2
 CONFIG_SYS_FSL_QSPI_AHB
 CONFIG_SYS_FSL_QSPI_BASE
 CONFIG_SYS_FSL_QSPI_BASE1
 CONFIG_SYS_FSL_QSPI_BASE2
 CONFIG_SYS_FSL_QSPI_BE
 CONFIG_SYS_FSL_QSPI_LE
 CONFIG_SYS_FSL_QSPI_SIZE
 CONFIG_SYS_FSL_QSPI_SIZE1
 CONFIG_SYS_FSL_QSPI_SIZE2
 CONFIG_SYS_FSL_RAID_ENGINE
 CONFIG_SYS_FSL_RAID_ENGINE_ADDR
 CONFIG_SYS_FSL_RAID_ENGINE_OFFSET
 CONFIG_SYS_FSL_RCPM_ADDR
 CONFIG_SYS_FSL_RMU
 CONFIG_SYS_FSL_RST_ADDR
 CONFIG_SYS_FSL_SCFG_ADDR
 CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
 CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET
 CONFIG_SYS_FSL_SCFG_OFFSET
 CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
 CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
 CONFIG_SYS_FSL_SEC_ADDR
 CONFIG_SYS_FSL_SEC_BE
 CONFIG_SYS_FSL_SEC_COMPAT
 CONFIG_SYS_FSL_SEC_IDX_OFFSET
 CONFIG_SYS_FSL_SEC_LE
 CONFIG_SYS_FSL_SEC_MON_BE
 CONFIG_SYS_FSL_SEC_MON_LE
 CONFIG_SYS_FSL_SEC_OFFSET
 CONFIG_SYS_FSL_SERDES
 CONFIG_SYS_FSL_SERDES_ADDR
 CONFIG_SYS_FSL_SFP_BE
 CONFIG_SYS_FSL_SFP_LE
 CONFIG_SYS_FSL_SFP_VER_3_0
 CONFIG_SYS_FSL_SFP_VER_3_2
 CONFIG_SYS_FSL_SFP_VER_3_4
 CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 CONFIG_SYS_FSL_SNVS_LE
 CONFIG_SYS_FSL_SP_ADDR
 CONFIG_SYS_FSL_SP_LOOPBACK_DUART
 CONFIG_SYS_FSL_SP_VSG_GIC_ADDR
 CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1
 CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2
 CONFIG_SYS_FSL_SRDS_1
 CONFIG_SYS_FSL_SRDS_2
 CONFIG_SYS_FSL_SRDS_3
 CONFIG_SYS_FSL_SRDS_4
 CONFIG_SYS_FSL_SRDS_NUM_PLLS
 CONFIG_SYS_FSL_SRIO_ADDR
 CONFIG_SYS_FSL_SRIO_IB_WIN_NUM
 CONFIG_SYS_FSL_SRIO_LIODN
 CONFIG_SYS_FSL_SRIO_MAX_PORTS
 CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM
 CONFIG_SYS_FSL_SRIO_OB_WIN_NUM
 CONFIG_SYS_FSL_SRIO_OFFSET
 CONFIG_SYS_FSL_SRK_LE
 CONFIG_SYS_FSL_TBCLK_DIV
 CONFIG_SYS_FSL_THREADS_PER_CORE
 CONFIG_SYS_FSL_TIMER_ADDR
 CONFIG_SYS_FSL_USB1_ADDR
 CONFIG_SYS_FSL_USB1_PHY_ENABLE
 CONFIG_SYS_FSL_USB2_ADDR
 CONFIG_SYS_FSL_USB2_PHY_ENABLE
 CONFIG_SYS_FSL_USB_CTRL_PHY_EN
 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN
 CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE
 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC
 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN
 CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV
 CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN
 CONFIG_SYS_FSL_USB_PLLPRG2_MFI
 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK
 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN
 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN
 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN
 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV
 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK
 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN
 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0
 CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3
 CONFIG_SYS_FSL_USB_SYS_CLK_VALID
 CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN
 CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK
 CONFIG_SYS_FSL_USDHC_NUM
 CONFIG_SYS_FSL_WDOG_BE
 CONFIG_SYS_FSL_WRIOP1_ADDR
 CONFIG_SYS_FSL_WRIOP1_BASE
 CONFIG_SYS_FSL_WRIOP1_MDIO1
 CONFIG_SYS_FSL_WRIOP1_MDIO2
 CONFIG_SYS_FSL_WRIOP1_SIZE
 CONFIG_SYS_FSL_XHCI_USB1_ADDR
 CONFIG_SYS_FSL_XHCI_USB2_ADDR
 CONFIG_SYS_FSL_XHCI_USB3_ADDR
 CONFIG_SYS_FSMC_BASE
 CONFIG_SYS_FSMC_NAND_16BIT
 CONFIG_SYS_FSMC_NAND_8BIT
 CONFIG_SYS_FSMC_NAND_SP
 CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
 CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS
 CONFIG_SYS_FTPMU010_SDRAMHTC
 CONFIG_SYS_FTSDMC021_BANK0_BASE
 CONFIG_SYS_FTSDMC021_BANK0_BSR
 CONFIG_SYS_FTSDMC021_BANK1_BASE
 CONFIG_SYS_FTSDMC021_BANK1_BSR
 CONFIG_SYS_FTSDMC021_CR1
 CONFIG_SYS_FTSDMC021_CR2
 CONFIG_SYS_FTSDMC021_TP1
 CONFIG_SYS_FTSDMC021_TP2
 CONFIG_SYS_FTSMC020_CONFIGS
 CONFIG_SYS_FULL_VA
 CONFIG_SYS_GAFR0_L_VAL
 CONFIG_SYS_GAFR0_U_VAL
 CONFIG_SYS_GAFR1_L_VAL
 CONFIG_SYS_GAFR1_U_VAL
 CONFIG_SYS_GAFR2_L_VAL
 CONFIG_SYS_GAFR2_U_VAL
 CONFIG_SYS_GAFR3_L_VAL
 CONFIG_SYS_GAFR3_U_VAL
 CONFIG_SYS_GBIT_MII1_BUSNAME
 CONFIG_SYS_GBIT_MII_BUSNAME
 CONFIG_SYS_GBL_DATA_ADDR
 CONFIG_SYS_GBL_DATA_OFFSET
 CONFIG_SYS_GBL_DATA_SIZE
 CONFIG_SYS_GENERIC_BOARD
 CONFIG_SYS_GENERIC_GLOBAL_DATA
 CONFIG_SYS_GIC400_ADDR
 CONFIG_SYS_GLOBAL_SDRAM_LIMIT
 CONFIG_SYS_GP1DIR
 CONFIG_SYS_GP1ODR
 CONFIG_SYS_GP2DIR
 CONFIG_SYS_GP2ODR
 CONFIG_SYS_GPCR0_VAL
 CONFIG_SYS_GPCR1_VAL
 CONFIG_SYS_GPCR2_VAL
 CONFIG_SYS_GPCR3_VAL
 CONFIG_SYS_GPDR0_VAL
 CONFIG_SYS_GPDR1_VAL
 CONFIG_SYS_GPDR2_VAL
 CONFIG_SYS_GPDR3_VAL
 CONFIG_SYS_GPIO0_ISR1H
 CONFIG_SYS_GPIO0_ISR1L
 CONFIG_SYS_GPIO0_ISR2H
 CONFIG_SYS_GPIO0_ISR2L
 CONFIG_SYS_GPIO0_ODR
 CONFIG_SYS_GPIO0_OR
 CONFIG_SYS_GPIO0_OSRH
 CONFIG_SYS_GPIO0_OSRL
 CONFIG_SYS_GPIO0_TCR
 CONFIG_SYS_GPIO0_TSRH
 CONFIG_SYS_GPIO0_TSRL
 CONFIG_SYS_GPIO1_DAT
 CONFIG_SYS_GPIO1_DIR
 CONFIG_SYS_GPIO1_EN
 CONFIG_SYS_GPIO1_FUNC
 CONFIG_SYS_GPIO1_ISR1H
 CONFIG_SYS_GPIO1_ISR1L
 CONFIG_SYS_GPIO1_LED
 CONFIG_SYS_GPIO1_OSRH
 CONFIG_SYS_GPIO1_OSRL
 CONFIG_SYS_GPIO1_OUT
 CONFIG_SYS_GPIO1_PRELIM
 CONFIG_SYS_GPIO1_TCR
 CONFIG_SYS_GPIO1_TSRH
 CONFIG_SYS_GPIO1_TSRL
 CONFIG_SYS_GPIO2_DAT
 CONFIG_SYS_GPIO2_DIR
 CONFIG_SYS_GPIO2_PRELIM
 CONFIG_SYS_GPIO_0_ADDR
 CONFIG_SYS_GPIO_BASE
 CONFIG_SYS_GPIO_BOARD_RESET
 CONFIG_SYS_GPIO_CAN_ENABLE
 CONFIG_SYS_GPIO_CRAM_ADV
 CONFIG_SYS_GPIO_CRAM_CLK
 CONFIG_SYS_GPIO_CRAM_CRE
 CONFIG_SYS_GPIO_CRAM_WAIT
 CONFIG_SYS_GPIO_DATADIR
 CONFIG_SYS_GPIO_DATAVALUE
 CONFIG_SYS_GPIO_DSPIC_READY
 CONFIG_SYS_GPIO_EEPROM_EXT_WP
 CONFIG_SYS_GPIO_EEPROM_INT_WP
 CONFIG_SYS_GPIO_EEPROM_WP
 CONFIG_SYS_GPIO_EN
 CONFIG_SYS_GPIO_ENABLE
 CONFIG_SYS_GPIO_EREADY
 CONFIG_SYS_GPIO_FLASH_WP
 CONFIG_SYS_GPIO_FUNC
 CONFIG_SYS_GPIO_HIGHSIDE
 CONFIG_SYS_GPIO_HWREV_MASK
 CONFIG_SYS_GPIO_HWREV_SHIFT
 CONFIG_SYS_GPIO_I2C_SCL
 CONFIG_SYS_GPIO_I2C_SDA
 CONFIG_SYS_GPIO_LEDA_N
 CONFIG_SYS_GPIO_LEDB_N
 CONFIG_SYS_GPIO_LEDRUN_N
 CONFIG_SYS_GPIO_LIME_RST
 CONFIG_SYS_GPIO_LIME_S
 CONFIG_SYS_GPIO_LSB_ENABLE
 CONFIG_SYS_GPIO_M66EN
 CONFIG_SYS_GPIO_MONARCH_N
 CONFIG_SYS_GPIO_ODR
 CONFIG_SYS_GPIO_OPENDRAIN
 CONFIG_SYS_GPIO_OR
 CONFIG_SYS_GPIO_OUT
 CONFIG_SYS_GPIO_PCIE_CLKREQ
 CONFIG_SYS_GPIO_PCIE_PRESENT0
 CONFIG_SYS_GPIO_PCIE_PRESENT1
 CONFIG_SYS_GPIO_PCIE_PRESENT2
 CONFIG_SYS_GPIO_PCIE_RST
 CONFIG_SYS_GPIO_PCIE_WAKE
 CONFIG_SYS_GPIO_PERM_VOLT_FEED
 CONFIG_SYS_GPIO_PHY0_RST
 CONFIG_SYS_GPIO_PHY1_RST
 CONFIG_SYS_GPIO_PHY_RST
 CONFIG_SYS_GPIO_RS232_FORCEOFF
 CONFIG_SYS_GPIO_SELFRST_N
 CONFIG_SYS_GPIO_STARTUP_FINISHED
 CONFIG_SYS_GPIO_STARTUP_FINISHED_N
 CONFIG_SYS_GPIO_SYSMON_STATUS
 CONFIG_SYS_GPIO_TCR
 CONFIG_SYS_GPIO_WATCHDOG
 CONFIG_SYS_GPIO_WIDTH
 CONFIG_SYS_GPR1
 CONFIG_SYS_GPSR0_VAL
 CONFIG_SYS_GPSR1_VAL
 CONFIG_SYS_GPSR2_VAL
 CONFIG_SYS_GPSR3_VAL
 CONFIG_SYS_GPS_PORT_CONFIG
 CONFIG_SYS_GPS_PORT_CONFIG_1
 CONFIG_SYS_GPS_PORT_CONFIG_2
 CONFIG_SYS_GRLIB_APBUART_INDEX
 CONFIG_SYS_GRLIB_ESA_MCTRL1
 CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1
 CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2
 CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3
 CONFIG_SYS_GRLIB_ESA_MCTRL2
 CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG1
 CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG2
 CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG3
 CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
 CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG1
 CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG3
 CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG4
 CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
 CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG1
 CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG3
 CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG4
 CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
 CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL
 CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
 CONFIG_SYS_GRLIB_GAISLER_DDRSPA2_CTRL
 CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
 CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1
 CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2
 CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3
 CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
 CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG1
 CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG2
 CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG3
 CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
 CONFIG_SYS_GRLIB_GAISLER_SDCTRL1_CTRL
 CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
 CONFIG_SYS_GRLIB_GAISLER_SDCTRL2_CTRL
 CONFIG_SYS_GRLIB_GPTIMER_INDEX
 CONFIG_SYS_GRLIB_GRETH_INDEX
 CONFIG_SYS_GRLIB_GRETH_PHYADDR
 CONFIG_SYS_GRLIB_GRUSB_INDEX
 CONFIG_SYS_GRLIB_MEMCFG1
 CONFIG_SYS_GRLIB_MEMCFG2
 CONFIG_SYS_GRLIB_MEMCFG3
 CONFIG_SYS_GRLIB_SDRAM
 CONFIG_SYS_GRLIB_SINGLE_BUS
 CONFIG_SYS_HALT_BEFOR_RAM_JUMP
 CONFIG_SYS_HAS_NO_CACHE
 CONFIG_SYS_HAS_SERDES
 CONFIG_SYS_HELP_CMD_WIDTH
 CONFIG_SYS_HID0_FINAL
 CONFIG_SYS_HID0_INIT
 CONFIG_SYS_HID2
 CONFIG_SYS_HIGH
 CONFIG_SYS_HMI_BASE
 CONFIG_SYS_HOSTNAME
 CONFIG_SYS_HRCW_HIGH
 CONFIG_SYS_HRCW_HIGH_BASE
 CONFIG_SYS_HRCW_LOW
 CONFIG_SYS_HRCW_MASTER
 CONFIG_SYS_HRCW_SLAVE1
 CONFIG_SYS_HRCW_SLAVE2
 CONFIG_SYS_HRCW_SLAVE3
 CONFIG_SYS_HRCW_SLAVE4
 CONFIG_SYS_HRCW_SLAVE5
 CONFIG_SYS_HRCW_SLAVE6
 CONFIG_SYS_HRCW_SLAVE7
 CONFIG_SYS_HSDRAMC
 CONFIG_SYS_HWINFO_MAGIC
 CONFIG_SYS_HWINFO_OFFSET
 CONFIG_SYS_HWINFO_SIZE
 CONFIG_SYS_HZ_CLOCK
 CONFIG_SYS_I2C
 CONFIG_SYS_I2C2_FSL_OFFSET
 CONFIG_SYS_I2C2_OFFSET
 CONFIG_SYS_I2C2_PINMUX_CLR
 CONFIG_SYS_I2C2_PINMUX_REG
 CONFIG_SYS_I2C2_PINMUX_SET
 CONFIG_SYS_I2C_0
 CONFIG_SYS_I2C_2
 CONFIG_SYS_I2C_5
 CONFIG_SYS_I2C_8574A_ADDR1
 CONFIG_SYS_I2C_8574A_ADDR2
 CONFIG_SYS_I2C_8574_ADDR1
 CONFIG_SYS_I2C_8574_ADDR2
 CONFIG_SYS_I2C_ADI
 CONFIG_SYS_I2C_BASE
 CONFIG_SYS_I2C_BASE0
 CONFIG_SYS_I2C_BASE1
 CONFIG_SYS_I2C_BASE2
 CONFIG_SYS_I2C_BASE3
 CONFIG_SYS_I2C_BASE4
 CONFIG_SYS_I2C_BASE5
 CONFIG_SYS_I2C_BOARD_LATE_INIT
 CONFIG_SYS_I2C_BOOT_EEPROM_ADDR
 CONFIG_SYS_I2C_BUSES
 CONFIG_SYS_I2C_BUS_MAX
 CONFIG_SYS_I2C_CLK_OFFSET
 CONFIG_SYS_I2C_DAVINCI
 CONFIG_SYS_I2C_DIRECT_BUS
 CONFIG_SYS_I2C_DPMEM_OFFSET
 CONFIG_SYS_I2C_DS1621_ADDR
 CONFIG_SYS_I2C_DS4510_ADDR
 CONFIG_SYS_I2C_DSPIC_2_ADDR
 CONFIG_SYS_I2C_DSPIC_ADDR
 CONFIG_SYS_I2C_DSPIC_IO_ADDR
 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR
 CONFIG_SYS_I2C_DTT_ADDR
 CONFIG_SYS_I2C_DVI_ADDR
 CONFIG_SYS_I2C_DVI_BUS_NUM
 CONFIG_SYS_I2C_EARLY_INIT
 CONFIG_SYS_I2C_EEPROM
 CONFIG_SYS_I2C_EEPROM_ADDR
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN
 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 CONFIG_SYS_I2C_EEPROM_BUS
 CONFIG_SYS_I2C_EEPROM_BUS_NUM
 CONFIG_SYS_I2C_EEPROM_CCID
 CONFIG_SYS_I2C_EEPROM_CPU_ADDR
 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET
 CONFIG_SYS_I2C_EEPROM_MB_ADDR
 CONFIG_SYS_I2C_EEPROM_NXID
 CONFIG_SYS_I2C_EEPROM_NXID_MAC
 CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS
 CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS
 CONFIG_SYS_I2C_EXPANDER_ADDR
 CONFIG_SYS_I2C_FACT_ADDR
 CONFIG_SYS_I2C_FPGA_ADDR
 CONFIG_SYS_I2C_FRAM
 CONFIG_SYS_I2C_G762_ADDR
 CONFIG_SYS_I2C_GENERIC_MAC
 CONFIG_SYS_I2C_HWMON_ADDR
 CONFIG_SYS_I2C_IDT6V49205B
 CONFIG_SYS_I2C_IFDR_DIV
 CONFIG_SYS_I2C_IHS
 CONFIG_SYS_I2C_IHS_CH0
 CONFIG_SYS_I2C_IHS_CH0_1
 CONFIG_SYS_I2C_IHS_CH1
 CONFIG_SYS_I2C_IHS_CH1_1
 CONFIG_SYS_I2C_IHS_CH2
 CONFIG_SYS_I2C_IHS_CH2_1
 CONFIG_SYS_I2C_IHS_CH3
 CONFIG_SYS_I2C_IHS_CH3_1
 CONFIG_SYS_I2C_IHS_DUAL
 CONFIG_SYS_I2C_IHS_SLAVE_0
 CONFIG_SYS_I2C_IHS_SLAVE_0_1
 CONFIG_SYS_I2C_IHS_SLAVE_1
 CONFIG_SYS_I2C_IHS_SLAVE_1_1
 CONFIG_SYS_I2C_IHS_SLAVE_2
 CONFIG_SYS_I2C_IHS_SLAVE_2_1
 CONFIG_SYS_I2C_IHS_SLAVE_3
 CONFIG_SYS_I2C_IHS_SLAVE_3_1
 CONFIG_SYS_I2C_IHS_SPEED_0
 CONFIG_SYS_I2C_IHS_SPEED_0_1
 CONFIG_SYS_I2C_IHS_SPEED_1
 CONFIG_SYS_I2C_IHS_SPEED_1_1
 CONFIG_SYS_I2C_IHS_SPEED_2
 CONFIG_SYS_I2C_IHS_SPEED_2_1
 CONFIG_SYS_I2C_IHS_SPEED_3
 CONFIG_SYS_I2C_IHS_SPEED_3_1
 CONFIG_SYS_I2C_INIT_BOARD
 CONFIG_SYS_I2C_IO
 CONFIG_SYS_I2C_KEYBD_ADDR
 CONFIG_SYS_I2C_KONA
 CONFIG_SYS_I2C_LDI_ADDR
 CONFIG_SYS_I2C_LM75_ADDR
 CONFIG_SYS_I2C_LM90_ADDR
 CONFIG_SYS_I2C_LPC32XX
 CONFIG_SYS_I2C_LPC32XX_SLAVE
 CONFIG_SYS_I2C_LPC32XX_SPEED
 CONFIG_SYS_I2C_MAC1_BUS
 CONFIG_SYS_I2C_MAC1_CHIP_ADDR
 CONFIG_SYS_I2C_MAC1_DATA_ADDR
 CONFIG_SYS_I2C_MAC2_BUS
 CONFIG_SYS_I2C_MAC2_CHIP_ADDR
 CONFIG_SYS_I2C_MAC2_DATA_ADDR
 CONFIG_SYS_I2C_MAC_OFFSET
 CONFIG_SYS_I2C_MAX1237_ADDR
 CONFIG_SYS_I2C_MAX_HOPS
 CONFIG_SYS_I2C_MODULE
 CONFIG_SYS_I2C_MXC
 CONFIG_SYS_I2C_MXC_I2C1
 CONFIG_SYS_I2C_MXC_I2C2
 CONFIG_SYS_I2C_MXC_I2C3
 CONFIG_SYS_I2C_MXC_I2C4
 CONFIG_SYS_I2C_MXS
 CONFIG_SYS_I2C_NCT72_ADDR
 CONFIG_SYS_I2C_NOPROBES
 CONFIG_SYS_I2C_OFFSET
 CONFIG_SYS_I2C_OMAP24XX
 CONFIG_SYS_I2C_OMAP34XX
 CONFIG_SYS_I2C_PCA953X_ADDR
 CONFIG_SYS_I2C_PCA953X_ADDR0
 CONFIG_SYS_I2C_PCA953X_ADDR1
 CONFIG_SYS_I2C_PCA953X_ADDR2
 CONFIG_SYS_I2C_PCA953X_ADDR3
 CONFIG_SYS_I2C_PCA953X_WIDTH
 CONFIG_SYS_I2C_PCA9553_ADDR
 CONFIG_SYS_I2C_PCA9555_ADDR
 CONFIG_SYS_I2C_PCA9557_ADDR
 CONFIG_SYS_I2C_PCF8574A_ADDR
 CONFIG_SYS_I2C_PEX8518_ADDR
 CONFIG_SYS_I2C_PINMUX_CLR
 CONFIG_SYS_I2C_PINMUX_REG
 CONFIG_SYS_I2C_PINMUX_SET
 CONFIG_SYS_I2C_POWERIC_ADDR
 CONFIG_SYS_I2C_PPC4XX
 CONFIG_SYS_I2C_PPC4XX_CH0
 CONFIG_SYS_I2C_PPC4XX_CH1
 CONFIG_SYS_I2C_PPC4XX_SLAVE_0
 CONFIG_SYS_I2C_PPC4XX_SLAVE_1
 CONFIG_SYS_I2C_PPC4XX_SPEED_0
 CONFIG_SYS_I2C_PPC4XX_SPEED_1
 CONFIG_SYS_I2C_PXA
 CONFIG_SYS_I2C_QIXIS_ADDR
 CONFIG_SYS_I2C_RCAR
 CONFIG_SYS_I2C_RTC_ADDR
 CONFIG_SYS_I2C_S3C24X0
 CONFIG_SYS_I2C_S3C24X0_SLAVE
 CONFIG_SYS_I2C_S3C24X0_SPEED
 CONFIG_SYS_I2C_SH
 CONFIG_SYS_I2C_SH_BASE0
 CONFIG_SYS_I2C_SH_BASE1
 CONFIG_SYS_I2C_SH_BASE2
 CONFIG_SYS_I2C_SH_BASE3
 CONFIG_SYS_I2C_SH_BASE4
 CONFIG_SYS_I2C_SH_NUM_CONTROLLERS
 CONFIG_SYS_I2C_SH_SPEED0
 CONFIG_SYS_I2C_SH_SPEED1
 CONFIG_SYS_I2C_SH_SPEED2
 CONFIG_SYS_I2C_SH_SPEED3
 CONFIG_SYS_I2C_SH_SPEED4
 CONFIG_SYS_I2C_SLAVE
 CONFIG_SYS_I2C_SLAVE1
 CONFIG_SYS_I2C_SLAVE2
 CONFIG_SYS_I2C_SLAVE3
 CONFIG_SYS_I2C_SOFT
 CONFIG_SYS_I2C_SOFT_SLAVE
 CONFIG_SYS_I2C_SOFT_SLAVE_10
 CONFIG_SYS_I2C_SOFT_SLAVE_11
 CONFIG_SYS_I2C_SOFT_SLAVE_12
 CONFIG_SYS_I2C_SOFT_SLAVE_2
 CONFIG_SYS_I2C_SOFT_SLAVE_3
 CONFIG_SYS_I2C_SOFT_SLAVE_4
 CONFIG_SYS_I2C_SOFT_SLAVE_5
 CONFIG_SYS_I2C_SOFT_SLAVE_6
 CONFIG_SYS_I2C_SOFT_SLAVE_7
 CONFIG_SYS_I2C_SOFT_SLAVE_8
 CONFIG_SYS_I2C_SOFT_SLAVE_9
 CONFIG_SYS_I2C_SOFT_SPEED
 CONFIG_SYS_I2C_SOFT_SPEED_10
 CONFIG_SYS_I2C_SOFT_SPEED_11
 CONFIG_SYS_I2C_SOFT_SPEED_12
 CONFIG_SYS_I2C_SOFT_SPEED_2
 CONFIG_SYS_I2C_SOFT_SPEED_3
 CONFIG_SYS_I2C_SOFT_SPEED_4
 CONFIG_SYS_I2C_SOFT_SPEED_5
 CONFIG_SYS_I2C_SOFT_SPEED_6
 CONFIG_SYS_I2C_SOFT_SPEED_7
 CONFIG_SYS_I2C_SOFT_SPEED_8
 CONFIG_SYS_I2C_SOFT_SPEED_9
 CONFIG_SYS_I2C_SPEED
 CONFIG_SYS_I2C_SPEED1
 CONFIG_SYS_I2C_SPEED2
 CONFIG_SYS_I2C_SPEED3
 CONFIG_SYS_I2C_TCA642X_ADDR
 CONFIG_SYS_I2C_TCA642X_BUS_NUM
 CONFIG_SYS_I2C_TEGRA
 CONFIG_SYS_I2C_UCODE_PATCH
 CONFIG_SYS_I2C_W83782G_ADDR
 CONFIG_SYS_I2C_ZYNQ
 CONFIG_SYS_I2C_ZYNQ_SLAVE
 CONFIG_SYS_I2C_ZYNQ_SPEED
 CONFIG_SYS_I2ODMA_BASE
 CONFIG_SYS_I2ODMA_PHYS_ADDR
 CONFIG_SYS_I2c_INIT_MPC5XXX
 CONFIG_SYS_IBAT
 CONFIG_SYS_IBAT0L
 CONFIG_SYS_IBAT0U
 CONFIG_SYS_IBAT1L
 CONFIG_SYS_IBAT1U
 CONFIG_SYS_IBAT2L
 CONFIG_SYS_IBAT2U
 CONFIG_SYS_IBAT3L
 CONFIG_SYS_IBAT3U
 CONFIG_SYS_IBAT4L
 CONFIG_SYS_IBAT4U
 CONFIG_SYS_IBAT5L
 CONFIG_SYS_IBAT5U
 CONFIG_SYS_IBAT6L
 CONFIG_SYS_IBAT6L_EARLY
 CONFIG_SYS_IBAT6U
 CONFIG_SYS_IBAT6U_EARLY
 CONFIG_SYS_IBAT7L
 CONFIG_SYS_IBAT7U
 CONFIG_SYS_ICACHE_INV
 CONFIG_SYS_ICACHE_LINESZ
 CONFIG_SYS_ICACHE_SACR_VALUE
 CONFIG_SYS_ICS8N3QV01_I2C
 CONFIG_SYS_ICTRL
 CONFIG_SYS_IDE_MAXBUS
 CONFIG_SYS_IDE_MAXDEVICE
 CONFIG_SYS_ID_EEPROM
 CONFIG_SYS_IFC_ADDR
 CONFIG_SYS_IFC_CCR
 CONFIG_SYS_IMMR
 CONFIG_SYS_INIT_DBCR
 CONFIG_SYS_INIT_DCACHE_CS
 CONFIG_SYS_INIT_DCACHE_PBxAR
 CONFIG_SYS_INIT_DCACHE_PBxCR
 CONFIG_SYS_INIT_EXTRA_SIZE
 CONFIG_SYS_INIT_L2CSR0
 CONFIG_SYS_INIT_L2_ADDR
 CONFIG_SYS_INIT_L2_ADDR_PHYS
 CONFIG_SYS_INIT_L2_END
 CONFIG_SYS_INIT_L3_ADDR
 CONFIG_SYS_INIT_L3_ADDR_PHYS
 CONFIG_SYS_INIT_L3_END
 CONFIG_SYS_INIT_L3_VADDR
 CONFIG_SYS_INIT_RAM1_ADDR
 CONFIG_SYS_INIT_RAM1_CTRL
 CONFIG_SYS_INIT_RAM1_END
 CONFIG_SYS_INIT_RAM_ADDR
 CONFIG_SYS_INIT_RAM_ADDR_PHYS
 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW
 CONFIG_SYS_INIT_RAM_CTRL
 CONFIG_SYS_INIT_RAM_DCACHE
 CONFIG_SYS_INIT_RAM_LOCK
 CONFIG_SYS_INIT_RAM_PATTERN
 CONFIG_SYS_INIT_RAM_SIZE
 CONFIG_SYS_INIT_SP_ADDR
 CONFIG_SYS_INIT_SP_OFFSET
 CONFIG_SYS_INPUT_CLKSRC
 CONFIG_SYS_INTA_FAKE
 CONFIG_SYS_INTEL_BOOT
 CONFIG_SYS_INTERLAKEN
 CONFIG_SYS_INTRAM_BASE
 CONFIG_SYS_INTRAM_SIZE
 CONFIG_SYS_INTR_BASE
 CONFIG_SYS_INTSRAM
 CONFIG_SYS_INTSRAMSZ
 CONFIG_SYS_INT_FLASH_BASE
 CONFIG_SYS_INT_FLASH_ENABLE
 CONFIG_SYS_IOCTRL_MUX_DDR
 CONFIG_SYS_IO_BASE
 CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
 CONFIG_SYS_IPBSPEED_133
 CONFIG_SYS_IR_REG_BASE_ADDR
 CONFIG_SYS_ISA_BASE
 CONFIG_SYS_ISA_IO
 CONFIG_SYS_ISA_IO_BASE_ADDRESS
 CONFIG_SYS_ISA_IO_OFFSET
 CONFIG_SYS_ISA_IO_STRIDE
 CONFIG_SYS_ISA_MEM
 CONFIG_SYS_ISB
 CONFIG_SYS_ISRAM_BASE
 CONFIG_SYS_IVM_EEPROM_ADR
 CONFIG_SYS_IVM_EEPROM_MAX_LEN
 CONFIG_SYS_IVM_EEPROM_PAGE_LEN
 CONFIG_SYS_JFFS2_FIRST_BANK
 CONFIG_SYS_JFFS2_FIRST_SECTOR
 CONFIG_SYS_JFFS2_MEM_NAND
 CONFIG_SYS_JFFS2_NUM_BANKS
 CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 CONFIG_SYS_KBYTES_SDRAM
 CONFIG_SYS_KEY_REG_BASE_ADDR
 CONFIG_SYS_KMBEC_FPGA_BASE
 CONFIG_SYS_KMBEC_FPGA_SIZE
 CONFIG_SYS_KWD_CONFIG
 CONFIG_SYS_KW_SPI_MPP
 CONFIG_SYS_L2
 CONFIG_SYS_L2_PL310
 CONFIG_SYS_L2_SIZE
 CONFIG_SYS_L3_SIZE
 CONFIG_SYS_LARGE_FLASH
 CONFIG_SYS_LATCH0_BOOT
 CONFIG_SYS_LATCH0_RESET
 CONFIG_SYS_LATCH1_BOOT
 CONFIG_SYS_LATCH1_RESET
 CONFIG_SYS_LATCH_ADDR
 CONFIG_SYS_LATCH_BASE
 CONFIG_SYS_LBAPP1_BASE
 CONFIG_SYS_LBAPP1_BASE_PHYS
 CONFIG_SYS_LBAPP1_BR_PRELIM
 CONFIG_SYS_LBAPP1_OR_PRELIM
 CONFIG_SYS_LBAPP2_BASE
 CONFIG_SYS_LBAPP2_BASE_PHYS
 CONFIG_SYS_LBAPP2_BR_PRELIM
 CONFIG_SYS_LBAPP2_OR_PRELIM
 CONFIG_SYS_LBC0_BASE
 CONFIG_SYS_LBC0_BASE_PHYS
 CONFIG_SYS_LBC1_BASE
 CONFIG_SYS_LBC1_BASE_PHYS
 CONFIG_SYS_LBCR_ADDR
 CONFIG_SYS_LBC_ADDR
 CONFIG_SYS_LBC_BASE
 CONFIG_SYS_LBC_BASE_PHYS_LOW
 CONFIG_SYS_LBC_CACHE_BASE
 CONFIG_SYS_LBC_FLASH_BASE
 CONFIG_SYS_LBC_LBCR
 CONFIG_SYS_LBC_LCRR
 CONFIG_SYS_LBC_LSDMR_1
 CONFIG_SYS_LBC_LSDMR_2
 CONFIG_SYS_LBC_LSDMR_3
 CONFIG_SYS_LBC_LSDMR_4
 CONFIG_SYS_LBC_LSDMR_5
 CONFIG_SYS_LBC_LSDMR_ARFRSH
 CONFIG_SYS_LBC_LSDMR_COMMON
 CONFIG_SYS_LBC_LSDMR_MRW
 CONFIG_SYS_LBC_LSDMR_PCHALL
 CONFIG_SYS_LBC_LSDMR_RFEN
 CONFIG_SYS_LBC_LSRT
 CONFIG_SYS_LBC_MRTPR
 CONFIG_SYS_LBC_NONCACHE_BASE
 CONFIG_SYS_LBC_SDRAM_BASE
 CONFIG_SYS_LBC_SDRAM_BASE_PHYS
 CONFIG_SYS_LBC_SDRAM_SIZE
 CONFIG_SYS_LBLAWAR0_PRELIM
 CONFIG_SYS_LBLAWAR1_PRELIM
 CONFIG_SYS_LBLAWAR2_PRELIM
 CONFIG_SYS_LBLAWAR3_PRELIM
 CONFIG_SYS_LBLAWAR4_PRELIM
 CONFIG_SYS_LBLAWAR5_PRELIM
 CONFIG_SYS_LBLAWAR6_PRELIM
 CONFIG_SYS_LBLAWAR7_PRELIM
 CONFIG_SYS_LBLAWBAR0_PRELIM
 CONFIG_SYS_LBLAWBAR1_PRELIM
 CONFIG_SYS_LBLAWBAR2_PRELIM
 CONFIG_SYS_LBLAWBAR3_PRELIM
 CONFIG_SYS_LBLAWBAR4_PRELIM
 CONFIG_SYS_LBLAWBAR5_PRELIM
 CONFIG_SYS_LBLAWBAR6_PRELIM
 CONFIG_SYS_LBLAWBAR7_PRELIM
 CONFIG_SYS_LB_SDRAM
 CONFIG_SYS_LCD0_RST
 CONFIG_SYS_LCD1_RST
 CONFIG_SYS_LCD_BASE
 CONFIG_SYS_LCD_ENDIAN
 CONFIG_SYS_LCRR_CLKDIV
 CONFIG_SYS_LCRR_DBYP
 CONFIG_SYS_LCRR_EADC
 CONFIG_SYS_LDB_CLOCK
 CONFIG_SYS_LDSCRIPT
 CONFIG_SYS_LED_ADDR
 CONFIG_SYS_LED_BASE
 CONFIG_SYS_LED_DISP_BASE
 CONFIG_SYS_LIME_BASE
 CONFIG_SYS_LIME_BASE_0
 CONFIG_SYS_LIME_BASE_1
 CONFIG_SYS_LIME_BASE_2
 CONFIG_SYS_LIME_BASE_3
 CONFIG_SYS_LIME_CLOCK_100MHZ
 CONFIG_SYS_LIME_CLOCK_133MHZ
 CONFIG_SYS_LIME_MMR
 CONFIG_SYS_LIME_SDRAM_CLOCK
 CONFIG_SYS_LIME_SIZE
 CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
 CONFIG_SYS_LOADS_BAUD_CHANGE
 CONFIG_SYS_LOAD_ADDR
 CONFIG_SYS_LOAD_ADDR2
 CONFIG_SYS_LOCAL_CONF_REGS
 CONFIG_SYS_LONGHELP
 CONFIG_SYS_LOW
 CONFIG_SYS_LOWBOOT
 CONFIG_SYS_LOWBOOT16
 CONFIG_SYS_LOWBOOT32
 CONFIG_SYS_LOWMEM_BASE
 CONFIG_SYS_LOW_RES_TIMER
 CONFIG_SYS_LPAE_SDRAM_BASE
 CONFIG_SYS_LPC32XX_UART
 CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
 CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
 CONFIG_SYS_LS_MC_DPC_ADDR
 CONFIG_SYS_LS_MC_DPC_IN_DDR
 CONFIG_SYS_LS_MC_DPC_IN_NOR
 CONFIG_SYS_LS_MC_DPC_MAX_LENGTH
 CONFIG_SYS_LS_MC_DPL_ADDR
 CONFIG_SYS_LS_MC_DPL_IN_DDR
 CONFIG_SYS_LS_MC_DPL_IN_NOR
 CONFIG_SYS_LS_MC_DPL_MAX_LENGTH
 CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
 CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
 CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
 CONFIG_SYS_LS_MC_FW_ADDR
 CONFIG_SYS_LS_MC_FW_IN_DDR
 CONFIG_SYS_LS_MC_FW_IN_NOR
 CONFIG_SYS_LS_PPA_FW_ADDR
 CONFIG_SYS_LS_PPA_FW_IN_XIP
 CONFIG_SYS_LS_PPA_FW_IN_xxx
 CONFIG_SYS_M41T11_BASE_YEAR
 CONFIG_SYS_M41T11_EXT_CENTURY_DATA
 CONFIG_SYS_MACB0_BASE
 CONFIG_SYS_MACB1_BASE
 CONFIG_SYS_MACB2_BASE
 CONFIG_SYS_MACB3_BASE
 CONFIG_SYS_MAIN_PWR_ON
 CONFIG_SYS_MALLOC_BASE
 CONFIG_SYS_MALLOC_CLEAR_ON_INIT
 CONFIG_SYS_MALLOC_END
 CONFIG_SYS_MALLOC_LEN
 CONFIG_SYS_MALLOC_SIMPLE
 CONFIG_SYS_MAMR
 CONFIG_SYS_MAMR_10COL
 CONFIG_SYS_MAMR_8COL
 CONFIG_SYS_MAMR_9COL
 CONFIG_SYS_MAMR_PTA
 CONFIG_SYS_MAPLE
 CONFIG_SYS_MAPLE_MEM_PHYS
 CONFIG_SYS_MAPPED_RAM_BASE
 CONFIG_SYS_MARUBUN_IO
 CONFIG_SYS_MARUBUN_MRSHPC
 CONFIG_SYS_MARUBUN_MW1
 CONFIG_SYS_MARUBUN_MW2
 CONFIG_SYS_MASK
 CONFIG_SYS_MASTER_CLOCK
 CONFIG_SYS_MATRIX_EBI0CSA_VAL
 CONFIG_SYS_MATRIX_EBICSA_VAL
 CONFIG_SYS_MATRIX_MCFG_REMAP
 CONFIG_SYS_MAXARGS
 CONFIG_SYS_MAXIDLE
 CONFIG_SYS_MAX_DATAFLASH_BANKS
 CONFIG_SYS_MAX_DDR_BAT_SIZE
 CONFIG_SYS_MAX_DOC_DEVICE
 CONFIG_SYS_MAX_FLASH_BANKS
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 CONFIG_SYS_MAX_FLASH_SECT
 CONFIG_SYS_MAX_I2C_BUS
 CONFIG_SYS_MAX_MTD_BANKS
 CONFIG_SYS_MAX_NAND_CHIPS
 CONFIG_SYS_MAX_NAND_DEVICE
 CONFIG_SYS_MAX_PCI_EPS
 CONFIG_SYS_MAX_RAM_SIZE
 CONFIG_SYS_MB862xx_CCF
 CONFIG_SYS_MB862xx_MMR
 CONFIG_SYS_MBAR
 CONFIG_SYS_MBAR2
 CONFIG_SYS_MBYTES_RAM
 CONFIG_SYS_MBYTES_SDRAM
 CONFIG_SYS_MCATT0_VAL
 CONFIG_SYS_MCATT1_VAL
 CONFIG_SYS_MCFRRTC_BASE
 CONFIG_SYS_MCFRTC_BASE
 CONFIG_SYS_MCF_SYNCR
 CONFIG_SYS_MCIO0_VAL
 CONFIG_SYS_MCIO1_VAL
 CONFIG_SYS_MCKR
 CONFIG_SYS_MCKR1_VAL
 CONFIG_SYS_MCKR2_VAL
 CONFIG_SYS_MCKR_CSS
 CONFIG_SYS_MCKR_VAL
 CONFIG_SYS_MCLINK_MAX
 CONFIG_SYS_MCMEM0_VAL
 CONFIG_SYS_MCMEM1_VAL
 CONFIG_SYS_MC_RSV_MEM_ALIGN
 CONFIG_SYS_MDC1_PIN
 CONFIG_SYS_MDCNFG_VAL
 CONFIG_SYS_MDC_PIN
 CONFIG_SYS_MDDRCGRP_HIPRIO_CFG
 CONFIG_SYS_MDDRCGRP_LUT0_AL
 CONFIG_SYS_MDDRCGRP_LUT0_AU
 CONFIG_SYS_MDDRCGRP_LUT0_ML
 CONFIG_SYS_MDDRCGRP_LUT0_MU
 CONFIG_SYS_MDDRCGRP_LUT1_AL
 CONFIG_SYS_MDDRCGRP_LUT1_AU
 CONFIG_SYS_MDDRCGRP_LUT1_ML
 CONFIG_SYS_MDDRCGRP_LUT1_MU
 CONFIG_SYS_MDDRCGRP_LUT2_AL
 CONFIG_SYS_MDDRCGRP_LUT2_AU
 CONFIG_SYS_MDDRCGRP_LUT2_ML
 CONFIG_SYS_MDDRCGRP_LUT2_MU
 CONFIG_SYS_MDDRCGRP_LUT3_AL
 CONFIG_SYS_MDDRCGRP_LUT3_AU
 CONFIG_SYS_MDDRCGRP_LUT3_ML
 CONFIG_SYS_MDDRCGRP_LUT3_MU
 CONFIG_SYS_MDDRCGRP_LUT4_AL
 CONFIG_SYS_MDDRCGRP_LUT4_AU
 CONFIG_SYS_MDDRCGRP_LUT4_ML
 CONFIG_SYS_MDDRCGRP_LUT4_MU
 CONFIG_SYS_MDDRCGRP_PM_CFG1
 CONFIG_SYS_MDDRCGRP_PM_CFG2
 CONFIG_SYS_MDDRC_SYS_CFG
 CONFIG_SYS_MDDRC_SYS_CFG_ALT1
 CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA
 CONFIG_SYS_MDDRC_SYS_CFG_EN
 CONFIG_SYS_MDDRC_TIME_CFG0
 CONFIG_SYS_MDDRC_TIME_CFG0_ALT1
 CONFIG_SYS_MDDRC_TIME_CFG1
 CONFIG_SYS_MDDRC_TIME_CFG1_ALT1
 CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA
 CONFIG_SYS_MDDRC_TIME_CFG2
 CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
 CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA
 CONFIG_SYS_MDIO1_OFFSET
 CONFIG_SYS_MDIO1_PIN
 CONFIG_SYS_MDIO_BASE_ADDR
 CONFIG_SYS_MDIO_PIN
 CONFIG_SYS_MDMRS_VAL
 CONFIG_SYS_MDREFR_VAL
 CONFIG_SYS_MEASURE_CPUCLK
 CONFIG_SYS_MECR_VAL
 CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 CONFIG_SYS_MEMORY_BASE
 CONFIG_SYS_MEMORY_SIZE
 CONFIG_SYS_MEMORY_TOP
 CONFIG_SYS_MEMTEST_END
 CONFIG_SYS_MEMTEST_SCRATCH
 CONFIG_SYS_MEMTEST_START
 CONFIG_SYS_MEM_MAP
 CONFIG_SYS_MEM_RESERVE_SECURE
 CONFIG_SYS_MEM_SIZE
 CONFIG_SYS_MEM_TOP_HIDE
 CONFIG_SYS_MFD
 CONFIG_SYS_MHZ
 CONFIG_SYS_MICRON_BMODE
 CONFIG_SYS_MICRON_BMODE_PARAM
 CONFIG_SYS_MICRON_BMODE_RSTDLL
 CONFIG_SYS_MICRON_EMODE
 CONFIG_SYS_MICRON_EMODE2
 CONFIG_SYS_MICRON_EMODE3
 CONFIG_SYS_MICRON_EMODE_PARAM
 CONFIG_SYS_MICRON_EMR
 CONFIG_SYS_MICRON_EMR2
 CONFIG_SYS_MICRON_EMR3
 CONFIG_SYS_MICRON_EMR_OCD
 CONFIG_SYS_MICRON_INIT_DEV_OP
 CONFIG_SYS_MII_MODE
 CONFIG_SYS_MIPS_CACHE_MODE
 CONFIG_SYS_MIPS_TIMER_FREQ
 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 CONFIG_SYS_MMC_BASE
 CONFIG_SYS_MMC_CD_PIN
 CONFIG_SYS_MMC_CLK_OD
 CONFIG_SYS_MMC_ENV_DEV
 CONFIG_SYS_MMC_ENV_PART
 CONFIG_SYS_MMC_IMG_LOAD_PART
 CONFIG_SYS_MMC_MAX_BLK_COUNT
 CONFIG_SYS_MMC_MAX_DEVICE
 CONFIG_SYS_MMC_U_BOOT_DST
 CONFIG_SYS_MMC_U_BOOT_OFFS
 CONFIG_SYS_MMC_U_BOOT_SIZE
 CONFIG_SYS_MMC_U_BOOT_START
 CONFIG_SYS_MMDC_CORE_ADDR_PARTITION
 CONFIG_SYS_MMDC_CORE_CONTROL_1
 CONFIG_SYS_MMDC_CORE_CONTROL_2
 CONFIG_SYS_MMDC_CORE_MISC
 CONFIG_SYS_MMDC_CORE_ODT_TIMING
 CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY
 CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL
 CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT
 CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY
 CONFIG_SYS_MMDC_CORE_REFRESH_CTL
 CONFIG_SYS_MMDC_CORE_TIMING_CFG_0
 CONFIG_SYS_MMDC_CORE_TIMING_CFG_1
 CONFIG_SYS_MMDC_CORE_TIMING_CFG_2
 CONFIG_SYS_MMDC_PHY_MEASURE_UNIT
 CONFIG_SYS_MMDC_PHY_ODT_CTRL
 CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG
 CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL
 CONFIG_SYS_MM_TOP_HIDE
 CONFIG_SYS_MONITOR_
 CONFIG_SYS_MONITOR_BASE
 CONFIG_SYS_MONITOR_BASE_EARLY
 CONFIG_SYS_MONITOR_LEN
 CONFIG_SYS_MONITOR_SEC
 CONFIG_SYS_MOR_VAL
 CONFIG_SYS_MPC512X_CLKIN
 CONFIG_SYS_MPC512x_USB1_ADDR
 CONFIG_SYS_MPC512x_USB1_OFFSET
 CONFIG_SYS_MPC5XXX_CLKIN
 CONFIG_SYS_MPC83xx_DMA_ADDR
 CONFIG_SYS_MPC83xx_DMA_OFFSET
 CONFIG_SYS_MPC83xx_ESDHC_ADDR
 CONFIG_SYS_MPC83xx_ESDHC_OFFSET
 CONFIG_SYS_MPC83xx_USB1_ADDR
 CONFIG_SYS_MPC83xx_USB1_OFFSET
 CONFIG_SYS_MPC83xx_USB2_ADDR
 CONFIG_SYS_MPC83xx_USB2_OFFSET
 CONFIG_SYS_MPC85XX_NO_RESETVEC
 CONFIG_SYS_MPC85xx_CPM_ADDR
 CONFIG_SYS_MPC85xx_CPM_OFFSET
 CONFIG_SYS_MPC85xx_DMA
 CONFIG_SYS_MPC85xx_DMA1_OFFSET
 CONFIG_SYS_MPC85xx_DMA2_OFFSET
 CONFIG_SYS_MPC85xx_DMA3_OFFSET
 CONFIG_SYS_MPC85xx_DMA_ADDR
 CONFIG_SYS_MPC85xx_DMA_OFFSET
 CONFIG_SYS_MPC85xx_ECM_ADDR
 CONFIG_SYS_MPC85xx_ECM_OFFSET
 CONFIG_SYS_MPC85xx_ESDHC_ADDR
 CONFIG_SYS_MPC85xx_ESDHC_OFFSET
 CONFIG_SYS_MPC85xx_ESPI_ADDR
 CONFIG_SYS_MPC85xx_ESPI_OFFSET
 CONFIG_SYS_MPC85xx_GPIO3_ADDR
 CONFIG_SYS_MPC85xx_GPIO_ADDR
 CONFIG_SYS_MPC85xx_GPIO_OFFSET
 CONFIG_SYS_MPC85xx_GUTS_ADDR
 CONFIG_SYS_MPC85xx_GUTS_OFFSET
 CONFIG_SYS_MPC85xx_IFC_OFFSET
 CONFIG_SYS_MPC85xx_L2_ADDR
 CONFIG_SYS_MPC85xx_L2_OFFSET
 CONFIG_SYS_MPC85xx_LBC_OFFSET
 CONFIG_SYS_MPC85xx_PCI1_OFFSET
 CONFIG_SYS_MPC85xx_PCI2_OFFSET
 CONFIG_SYS_MPC85xx_PCIE
 CONFIG_SYS_MPC85xx_PCIE1_OFFSET
 CONFIG_SYS_MPC85xx_PCIE2_OFFSET
 CONFIG_SYS_MPC85xx_PCIE3_OFFSET
 CONFIG_SYS_MPC85xx_PCIE4_OFFSET
 CONFIG_SYS_MPC85xx_PCIX2_ADDR
 CONFIG_SYS_MPC85xx_PCIX2_OFFSET
 CONFIG_SYS_MPC85xx_PCIX_ADDR
 CONFIG_SYS_MPC85xx_PCIX_OFFSET
 CONFIG_SYS_MPC85xx_PIC_OFFSET
 CONFIG_SYS_MPC85xx_QE_OFFSET
 CONFIG_SYS_MPC85xx_SATA
 CONFIG_SYS_MPC85xx_SATA1_ADDR
 CONFIG_SYS_MPC85xx_SATA1_OFFSET
 CONFIG_SYS_MPC85xx_SATA2_ADDR
 CONFIG_SYS_MPC85xx_SATA2_OFFSET
 CONFIG_SYS_MPC85xx_SCFG
 CONFIG_SYS_MPC85xx_SCFG_OFFSET
 CONFIG_SYS_MPC85xx_SERDES1_ADDR
 CONFIG_SYS_MPC85xx_SERDES1_OFFSET
 CONFIG_SYS_MPC85xx_SERDES2_ADDR
 CONFIG_SYS_MPC85xx_SERDES2_OFFSET
 CONFIG_SYS_MPC85xx_TDM_OFFSET
 CONFIG_SYS_MPC85xx_USB
 CONFIG_SYS_MPC85xx_USB1_ADDR
 CONFIG_SYS_MPC85xx_USB1_OFFSET
 CONFIG_SYS_MPC85xx_USB1_PHY_ADDR
 CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET
 CONFIG_SYS_MPC85xx_USB2_ADDR
 CONFIG_SYS_MPC85xx_USB2_OFFSET
 CONFIG_SYS_MPC85xx_USB2_PHY_ADDR
 CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET
 CONFIG_SYS_MPC86xx_DMA_ADDR
 CONFIG_SYS_MPC86xx_DMA_OFFSET
 CONFIG_SYS_MPC86xx_PCI1_OFFSET
 CONFIG_SYS_MPC86xx_PCI2_OFFSET
 CONFIG_SYS_MPC86xx_PCIE1_OFFSET
 CONFIG_SYS_MPC86xx_PCIE2_OFFSET
 CONFIG_SYS_MPC86xx_PIC_OFFSET
 CONFIG_SYS_MPC8xxx_DDR2_OFFSET
 CONFIG_SYS_MPC8xxx_DDR3_OFFSET
 CONFIG_SYS_MPC8xxx_DDR_OFFSET
 CONFIG_SYS_MPC8xxx_GUTS_ADDR
 CONFIG_SYS_MPC8xxx_PIC_ADDR
 CONFIG_SYS_MPC92469AC
 CONFIG_SYS_MPEG_BASE
 CONFIG_SYS_MPEG_SIZE
 CONFIG_SYS_MPTPR
 CONFIG_SYS_MPTPR_1BK_2K
 CONFIG_SYS_MPTPR_1BK_4K
 CONFIG_SYS_MPTPR_1BK_8K
 CONFIG_SYS_MPTPR_2BK_2K
 CONFIG_SYS_MPTPR_2BK_4K
 CONFIG_SYS_MPTPR_2BK_8K
 CONFIG_SYS_MPUCLK
 CONFIG_SYS_MRAM_BASE
 CONFIG_SYS_MRAM_SIZE
 CONFIG_SYS_MRS_OFFS
 CONFIG_SYS_MSC0_VAL
 CONFIG_SYS_MSC1_VAL
 CONFIG_SYS_MSC2_VAL
 CONFIG_SYS_MTDPARTS_RUNTIME
 CONFIG_SYS_MVEBU_PLL_CLOCK
 CONFIG_SYS_MVFS
 CONFIG_SYS_MX5_CLK32
 CONFIG_SYS_MX5_HCLK
 CONFIG_SYS_MX6_CLK32
 CONFIG_SYS_MX6_HCLK
 CONFIG_SYS_MX7_CLK32
 CONFIG_SYS_MX7_HCLK
 CONFIG_SYS_MXC_I2C1_SLAVE
 CONFIG_SYS_MXC_I2C1_SPEED
 CONFIG_SYS_MXC_I2C2_SLAVE
 CONFIG_SYS_MXC_I2C2_SPEED
 CONFIG_SYS_MXC_I2C3_SLAVE
 CONFIG_SYS_MXC_I2C3_SPEED
 CONFIG_SYS_MXC_I2C4_SLAVE
 CONFIG_SYS_MXC_I2C4_SPEED
 CONFIG_SYS_MXS_VDD5V_ONLY
 CONFIG_SYS_NAND2_ADDR
 CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 CONFIG_SYS_NAND_4_ADDR_CYCLE
 CONFIG_SYS_NAND_5_ADDR_CYCLE
 CONFIG_SYS_NAND_ACTL_ALE
 CONFIG_SYS_NAND_ACTL_CLE
 CONFIG_SYS_NAND_ACTL_DELAY
 CONFIG_SYS_NAND_ACTL_NCE
 CONFIG_SYS_NAND_ADDR
 CONFIG_SYS_NAND_ALE
 CONFIG_SYS_NAND_AMASK
 CONFIG_SYS_NAND_BAD_BLOCK_POS
 CONFIG_SYS_NAND_BASE
 CONFIG_SYS_NAND_BASE2
 CONFIG_SYS_NAND_BASE_LIST
 CONFIG_SYS_NAND_BASE_PHYS
 CONFIG_SYS_NAND_BCR
 CONFIG_SYS_NAND_BLOCK_SIZE
 CONFIG_SYS_NAND_BOOT
 CONFIG_SYS_NAND_BR_PRELIM
 CONFIG_SYS_NAND_BUSWIDTH_16
 CONFIG_SYS_NAND_BUSWIDTH_16_BIT
 CONFIG_SYS_NAND_CE
 CONFIG_SYS_NAND_CLE
 CONFIG_SYS_NAND_CS
 CONFIG_SYS_NAND_CSOR
 CONFIG_SYS_NAND_CSPR
 CONFIG_SYS_NAND_CSPR_EXT
 CONFIG_SYS_NAND_DATA_BASE
 CONFIG_SYS_NAND_DBW_16
 CONFIG_SYS_NAND_DBW_8
 CONFIG_SYS_NAND_DDR_LAW
 CONFIG_SYS_NAND_ECCBYTES
 CONFIG_SYS_NAND_ECCPOS
 CONFIG_SYS_NAND_ECCSIZE
 CONFIG_SYS_NAND_ECCSTEPS
 CONFIG_SYS_NAND_ECCTOTAL
 CONFIG_SYS_NAND_ECC_BASE
 CONFIG_SYS_NAND_ENABLE_PIN
 CONFIG_SYS_NAND_ENABLE_PIN_SPL
 CONFIG_SYS_NAND_FTIM0
 CONFIG_SYS_NAND_FTIM1
 CONFIG_SYS_NAND_FTIM2
 CONFIG_SYS_NAND_FTIM3
 CONFIG_SYS_NAND_HW_ECC
 CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 CONFIG_SYS_NAND_LARGEPAGE
 CONFIG_SYS_NAND_LBLAWAR_PRELIM
 CONFIG_SYS_NAND_LBLAWBAR_PRELIM
 CONFIG_SYS_NAND_MASK_ALE
 CONFIG_SYS_NAND_MASK_CLE
 CONFIG_SYS_NAND_MAX_CHIPS
 CONFIG_SYS_NAND_MAX_ECCPOS
 CONFIG_SYS_NAND_MAX_OOBFREE
 CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
 CONFIG_SYS_NAND_NO_SUBPAGE
 CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
 CONFIG_SYS_NAND_ONFI_DETECTION
 CONFIG_SYS_NAND_OOBSIZE
 CONFIG_SYS_NAND_OR_PRELIM
 CONFIG_SYS_NAND_PAGE_2K
 CONFIG_SYS_NAND_PAGE_4K
 CONFIG_SYS_NAND_PAGE_COUNT
 CONFIG_SYS_NAND_PAGE_SIZE
 CONFIG_SYS_NAND_QUIET
 CONFIG_SYS_NAND_RDY
 CONFIG_SYS_NAND_READY_PIN
 CONFIG_SYS_NAND_REGS_BASE
 CONFIG_SYS_NAND_SELECT_DEVICE
 CONFIG_SYS_NAND_SIZE
 CONFIG_SYS_NAND_SKIP_BAD_DOT_I
 CONFIG_SYS_NAND_SPL_KERNEL_OFFS
 CONFIG_SYS_NAND_SPL_SIZE
 CONFIG_SYS_NAND_USE_FLASH_BBT
 CONFIG_SYS_NAND_U_BOOT_DST
 CONFIG_SYS_NAND_U_BOOT_RELOC
 CONFIG_SYS_NAND_U_BOOT_RELOC_SP
 CONFIG_SYS_NAND_U_BOOT_SIZE
 CONFIG_SYS_NAND_U_BOOT_START
 CONFIG_SYS_NAND_WINDOW_SIZE
 CONFIG_SYS_NDFC_EBC0_CFG
 CONFIG_SYS_NETA_INTERFACE_TYPE
 CONFIG_SYS_NONCACHED_MEMORY
 CONFIG_SYS_NOR0_CSPR
 CONFIG_SYS_NOR0_CSPR_EARLY
 CONFIG_SYS_NOR0_CSPR_EXT
 CONFIG_SYS_NOR1SZ
 CONFIG_SYS_NOR1_CSPR
 CONFIG_SYS_NOR1_CSPR_EARLY
 CONFIG_SYS_NOR1_CSPR_EXT
 CONFIG_SYS_NOR_AMASK
 CONFIG_SYS_NOR_AMASK_EARLY
 CONFIG_SYS_NOR_BR_PRELIM
 CONFIG_SYS_NOR_CS
 CONFIG_SYS_NOR_CSOR
 CONFIG_SYS_NOR_CSPR
 CONFIG_SYS_NOR_CSPR_EXT
 CONFIG_SYS_NOR_FTIM0
 CONFIG_SYS_NOR_FTIM1
 CONFIG_SYS_NOR_FTIM2
 CONFIG_SYS_NOR_FTIM3
 CONFIG_SYS_NOR_OR_PRELIM
 CONFIG_SYS_NO_DCACHE
 CONFIG_SYS_NR_PIOS
 CONFIG_SYS_NR_VM_REGIONS
 CONFIG_SYS_NS16550_CLK
 CONFIG_SYS_NS16550_CLK_DIV
 CONFIG_SYS_NS16550_COM1
 CONFIG_SYS_NS16550_COM2
 CONFIG_SYS_NS16550_COM3
 CONFIG_SYS_NS16550_COM4
 CONFIG_SYS_NS16550_COM5
 CONFIG_SYS_NS16550_COM6
 CONFIG_SYS_NS16550_IER
 CONFIG_SYS_NS16550_MEM32
 CONFIG_SYS_NS16550_PORT_MAPPED
 CONFIG_SYS_NS16550_REG_SIZE
 CONFIG_SYS_NS16550_SERIAL
 CONFIG_SYS_NS87308_CS0_BASE
 CONFIG_SYS_NS87308_CS0_CONF
 CONFIG_SYS_NS87308_CS1_BASE
 CONFIG_SYS_NS87308_CS1_CONF
 CONFIG_SYS_NS87308_CS2_BASE
 CONFIG_SYS_NS87308_CS2_CONF
 CONFIG_SYS_NS87308_FDC
 CONFIG_SYS_NS87308_FDC_BASE
 CONFIG_SYS_NS87308_GPIO
 CONFIG_SYS_NS87308_GPIO_BASE
 CONFIG_SYS_NS87308_KBC1
 CONFIG_SYS_NS87308_KBC1_BASE
 CONFIG_SYS_NS87308_KBC2
 CONFIG_SYS_NS87308_LPT_BASE
 CONFIG_SYS_NS87308_MOUSE
 CONFIG_SYS_NS87308_PARP
 CONFIG_SYS_NS87308_PMC1
 CONFIG_SYS_NS87308_PMC2
 CONFIG_SYS_NS87308_PMC3
 CONFIG_SYS_NS87308_POWRMAN
 CONFIG_SYS_NS87308_PS2MOD
 CONFIG_SYS_NS87308_PWMAN_BASE
 CONFIG_SYS_NS87308_RARP
 CONFIG_SYS_NS87308_RTC_APC
 CONFIG_SYS_NS87308_RTC_BASE
 CONFIG_SYS_NS87308_UART1
 CONFIG_SYS_NS87308_UART1_BASE
 CONFIG_SYS_NS87308_UART2
 CONFIG_SYS_NS87308_UART2_BASE
 CONFIG_SYS_NUM_ADDR_MAP
 CONFIG_SYS_NUM_CPC
 CONFIG_SYS_NUM_DDR_CTLRS
 CONFIG_SYS_NUM_FM1_10GEC
 CONFIG_SYS_NUM_FM1_DTSEC
 CONFIG_SYS_NUM_FM2_10GEC
 CONFIG_SYS_NUM_FM2_DTSEC
 CONFIG_SYS_NUM_FMAN
 CONFIG_SYS_NUM_I2C_BUSES
 CONFIG_SYS_NUM_IRQS
 CONFIG_SYS_NUM_TLBCAMS
 CONFIG_SYS_NVRAM_ACCESS_ROUTINE
 CONFIG_SYS_NVRAM_BASE
 CONFIG_SYS_NVRAM_BASE_ADDR
 CONFIG_SYS_NVRAM_SIZE
 CONFIG_SYS_OBIR
 CONFIG_SYS_OCM_BASE
 CONFIG_SYS_OCM_DATA_ADDR
 CONFIG_SYS_OCM_DATA_SIZE
 CONFIG_SYS_OCM_SIZE
 CONFIG_SYS_OCM_STATUS_ADDR
 CONFIG_SYS_OCM_STATUS_FAIL
 CONFIG_SYS_OCM_STATUS_MASK
 CONFIG_SYS_OCM_STATUS_OK
 CONFIG_SYS_OHCI_BE_CONTROLLER
 CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 CONFIG_SYS_OHCI_USE_NPS
 CONFIG_SYS_OMAP24_I2C_SLAVE
 CONFIG_SYS_OMAP24_I2C_SLAVE1
 CONFIG_SYS_OMAP24_I2C_SLAVE2
 CONFIG_SYS_OMAP24_I2C_SLAVE3
 CONFIG_SYS_OMAP24_I2C_SLAVE4
 CONFIG_SYS_OMAP24_I2C_SPEED
 CONFIG_SYS_OMAP24_I2C_SPEED1
 CONFIG_SYS_OMAP24_I2C_SPEED2
 CONFIG_SYS_OMAP24_I2C_SPEED3
 CONFIG_SYS_OMAP24_I2C_SPEED4
 CONFIG_SYS_OMAP24_I2C_SPEED_PSOC
 CONFIG_SYS_OMAP_ABE_SYSCK
 CONFIG_SYS_ONENAND_BASE
 CONFIG_SYS_ONENAND_BLOCK_SIZE
 CONFIG_SYS_ONENAND_PAGE_SIZE
 CONFIG_SYS_OPENRISC_TMR_HZ
 CONFIG_SYS_OPER_FLASH
 CONFIG_SYS_OR0_64M
 CONFIG_SYS_OR0_8M
 CONFIG_SYS_OR0_PRELIM
 CONFIG_SYS_OR0_REMAP
 CONFIG_SYS_OR1
 CONFIG_SYS_OR10_PRELIM
 CONFIG_SYS_OR11_PRELIM
 CONFIG_SYS_OR1_PRELIM
 CONFIG_SYS_OR1_REMAP
 CONFIG_SYS_OR2_PRELIM
 CONFIG_SYS_OR3_CAN
 CONFIG_SYS_OR3_PRELIM
 CONFIG_SYS_OR4_PRELIM
 CONFIG_SYS_OR5_ISP1362
 CONFIG_SYS_OR5_PRELIM
 CONFIG_SYS_OR5_REMAP
 CONFIG_SYS_OR6_64M
 CONFIG_SYS_OR6_8M
 CONFIG_SYS_OR6_PRELIM
 CONFIG_SYS_OR7_PRELIM
 CONFIG_SYS_OR8_PRELIM
 CONFIG_SYS_OR9_PRELIM
 CONFIG_SYS_OR_TIMING_FLASH
 CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
 CONFIG_SYS_OR_TIMING_MRAM
 CONFIG_SYS_OR_TIMING_SDRAM
 CONFIG_SYS_OSC0_HZ
 CONFIG_SYS_OSC1_HZ
 CONFIG_SYS_OSCIN_FREQ
 CONFIG_SYS_OSC_CLK
 CONFIG_SYS_OSD_DH
 CONFIG_SYS_OSD_SCREENS
 CONFIG_SYS_OSPR_OFFSET
 CONFIG_SYS_OS_BASE
 CONFIG_SYS_P4080_ERRATUM_CPU22
 CONFIG_SYS_P4080_ERRATUM_PCIE_A003
 CONFIG_SYS_P4080_ERRATUM_SERDES8
 CONFIG_SYS_P4080_ERRATUM_SERDES9
 CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 CONFIG_SYS_PACNT
 CONFIG_SYS_PADAT
 CONFIG_SYS_PADDR
 CONFIG_SYS_PAGE_SIZE
 CONFIG_SYS_PAMU_ADDR
 CONFIG_SYS_PASPAR
 CONFIG_SYS_PAXE_BASE
 CONFIG_SYS_PAXE_SIZE
 CONFIG_SYS_PBCNT
 CONFIG_SYS_PBDAT
 CONFIG_SYS_PBDDR
 CONFIG_SYS_PBI_FLASH_BASE
 CONFIG_SYS_PBI_FLASH_WINDOW
 CONFIG_SYS_PBSIZE
 CONFIG_SYS_PB_LED
 CONFIG_SYS_PCA953X_BRD_CFG0
 CONFIG_SYS_PCA953X_BRD_CFG1
 CONFIG_SYS_PCA953X_BRD_CFG2
 CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS
 CONFIG_SYS_PCA953X_C0_SER0_EN
 CONFIG_SYS_PCA953X_C0_SER0_MODE
 CONFIG_SYS_PCA953X_C0_SER1_EN
 CONFIG_SYS_PCA953X_C0_SER1_MODE
 CONFIG_SYS_PCA953X_C0_VCORE_VID2
 CONFIG_SYS_PCA953X_C0_VCORE_VID3
 CONFIG_SYS_PCA953X_EREADY
 CONFIG_SYS_PCA953X_FLASH_PASS_CS
 CONFIG_SYS_PCA953X_GPIO_VPX0
 CONFIG_SYS_PCA953X_GPIO_VPX1
 CONFIG_SYS_PCA953X_GPIO_VPX2
 CONFIG_SYS_PCA953X_GPIO_VPX3
 CONFIG_SYS_PCA953X_MC_GPIO0
 CONFIG_SYS_PCA953X_MC_GPIO1
 CONFIG_SYS_PCA953X_MC_GPIO2
 CONFIG_SYS_PCA953X_MC_GPIO3
 CONFIG_SYS_PCA953X_MC_GPIO4
 CONFIG_SYS_PCA953X_MC_GPIO5
 CONFIG_SYS_PCA953X_MC_GPIO6
 CONFIG_SYS_PCA953X_MC_GPIO7
 CONFIG_SYS_PCA953X_MONARCH
 CONFIG_SYS_PCA953X_NVM_WP
 CONFIG_SYS_PCA953X_P0_GA0
 CONFIG_SYS_PCA953X_P0_GA1
 CONFIG_SYS_PCA953X_P0_GA2
 CONFIG_SYS_PCA953X_P0_GA3
 CONFIG_SYS_PCA953X_P0_GA4
 CONFIG_SYS_PCA953X_P0_GAP
 CONFIG_SYS_PCA953X_P14_IO0
 CONFIG_SYS_PCA953X_P14_IO1
 CONFIG_SYS_PCA953X_P14_IO2
 CONFIG_SYS_PCA953X_P14_IO3
 CONFIG_SYS_PCA953X_P14_IO4
 CONFIG_SYS_PCA953X_P14_IO5
 CONFIG_SYS_PCA953X_P14_IO6
 CONFIG_SYS_PCA953X_P14_IO7
 CONFIG_SYS_PCA953X_P1_SYSEN
 CONFIG_SYS_PCA953X_PLUG_GPIO0
 CONFIG_SYS_PCA953X_PMC0_EREADY
 CONFIG_SYS_PCA953X_PMC0_MONARCH
 CONFIG_SYS_PCA953X_PMC_EREADY
 CONFIG_SYS_PCA953X_PMC_MONARCH
 CONFIG_SYS_PCA953X_PMC_PRESENT
 CONFIG_SYS_PCA953X_VPX_FRU_WRCTL
 CONFIG_SYS_PCA953X_VPX_GPIO0
 CONFIG_SYS_PCA953X_VPX_GPIO1
 CONFIG_SYS_PCA953X_VPX_GPIO2
 CONFIG_SYS_PCA953X_VPX_GPIO3
 CONFIG_SYS_PCA953X_XMC0_BIST
 CONFIG_SYS_PCA953X_XMC0_MVMR0
 CONFIG_SYS_PCA953X_XMC0_ROOT0
 CONFIG_SYS_PCA953X_XMC0_WAKE
 CONFIG_SYS_PCA953X_XMC_BIST
 CONFIG_SYS_PCA953X_XMC_GA0
 CONFIG_SYS_PCA953X_XMC_GA1
 CONFIG_SYS_PCA953X_XMC_GA2
 CONFIG_SYS_PCA953X_XMC_PRESENT
 CONFIG_SYS_PCA953X_XMC_ROOT0
 CONFIG_SYS_PCA953X_XMC_WAKE
 CONFIG_SYS_PCCNT
 CONFIG_SYS_PCDAT
 CONFIG_SYS_PCDDR
 CONFIG_SYS_PCI
 CONFIG_SYS_PCI0_IO_SPACE
 CONFIG_SYS_PCI1_ADDR
 CONFIG_SYS_PCI1_IO_BASE
 CONFIG_SYS_PCI1_IO_BUS
 CONFIG_SYS_PCI1_IO_PHYS
 CONFIG_SYS_PCI1_IO_SIZE
 CONFIG_SYS_PCI1_IO_VIRT
 CONFIG_SYS_PCI1_MEM_BASE
 CONFIG_SYS_PCI1_MEM_BUS
 CONFIG_SYS_PCI1_MEM_PHYS
 CONFIG_SYS_PCI1_MEM_SIZE
 CONFIG_SYS_PCI1_MEM_VIRT
 CONFIG_SYS_PCI1_MMIO_BASE
 CONFIG_SYS_PCI1_MMIO_PHYS
 CONFIG_SYS_PCI1_MMIO_SIZE
 CONFIG_SYS_PCI2_ADDR
 CONFIG_SYS_PCI2_IO_BASE
 CONFIG_SYS_PCI2_IO_BUS
 CONFIG_SYS_PCI2_IO_PHYS
 CONFIG_SYS_PCI2_IO_SIZE
 CONFIG_SYS_PCI2_IO_VIRT
 CONFIG_SYS_PCI2_MEM_BASE
 CONFIG_SYS_PCI2_MEM_BUS
 CONFIG_SYS_PCI2_MEM_PHYS
 CONFIG_SYS_PCI2_MEM_SIZE
 CONFIG_SYS_PCI2_MEM_VIRT
 CONFIG_SYS_PCI2_MMIO_BASE
 CONFIG_SYS_PCI2_MMIO_PHYS
 CONFIG_SYS_PCI2_MMIO_SIZE
 CONFIG_SYS_PCI64_MEMORY_BUS
 CONFIG_SYS_PCI9054_IOBASE
 CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 CONFIG_SYS_PCIE
 CONFIG_SYS_PCIE0_CFGBASE
 CONFIG_SYS_PCIE0_CFGMASK
 CONFIG_SYS_PCIE0_MEMBASE
 CONFIG_SYS_PCIE0_REGBASE
 CONFIG_SYS_PCIE0_UTLBASE
 CONFIG_SYS_PCIE0_XCFGBASE
 CONFIG_SYS_PCIE1_ADDR
 CONFIG_SYS_PCIE1_BASE
 CONFIG_SYS_PCIE1_CFGBASE
 CONFIG_SYS_PCIE1_CFGMASK
 CONFIG_SYS_PCIE1_CFG_BASE
 CONFIG_SYS_PCIE1_CFG_SIZE
 CONFIG_SYS_PCIE1_IO_BASE
 CONFIG_SYS_PCIE1_IO_BUS
 CONFIG_SYS_PCIE1_IO_PHYS
 CONFIG_SYS_PCIE1_IO_PHYS_LOW
 CONFIG_SYS_PCIE1_IO_SIZE
 CONFIG_SYS_PCIE1_IO_VIRT
 CONFIG_SYS_PCIE1_MEMBASE
 CONFIG_SYS_PCIE1_MEM_BASE
 CONFIG_SYS_PCIE1_MEM_BUS
 CONFIG_SYS_PCIE1_MEM_PHYS
 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 CONFIG_SYS_PCIE1_MEM_PHYS_LOW
 CONFIG_SYS_PCIE1_MEM_SIZE
 CONFIG_SYS_PCIE1_MEM_VIRT
 CONFIG_SYS_PCIE1_NAME
 CONFIG_SYS_PCIE1_PHYS_ADDR
 CONFIG_SYS_PCIE1_PHYS_BASE
 CONFIG_SYS_PCIE1_PHYS_SIZE
 CONFIG_SYS_PCIE1_REGBASE
 CONFIG_SYS_PCIE1_UTLBASE
 CONFIG_SYS_PCIE1_VIRT_ADDR
 CONFIG_SYS_PCIE1_XCFGBASE
 CONFIG_SYS_PCIE2_ADDR
 CONFIG_SYS_PCIE2_BASE
 CONFIG_SYS_PCIE2_CFGBASE
 CONFIG_SYS_PCIE2_CFG_BASE
 CONFIG_SYS_PCIE2_CFG_SIZE
 CONFIG_SYS_PCIE2_IO_BASE
 CONFIG_SYS_PCIE2_IO_BUS
 CONFIG_SYS_PCIE2_IO_PHYS
 CONFIG_SYS_PCIE2_IO_PHYS_LOW
 CONFIG_SYS_PCIE2_IO_SIZE
 CONFIG_SYS_PCIE2_IO_VIRT
 CONFIG_SYS_PCIE2_MEM_BASE
 CONFIG_SYS_PCIE2_MEM_BUS
 CONFIG_SYS_PCIE2_MEM_PHYS
 CONFIG_SYS_PCIE2_MEM_PHYS_HIGH
 CONFIG_SYS_PCIE2_MEM_PHYS_LOW
 CONFIG_SYS_PCIE2_MEM_SIZE
 CONFIG_SYS_PCIE2_MEM_VIRT
 CONFIG_SYS_PCIE2_NAME
 CONFIG_SYS_PCIE2_PHYS_ADDR
 CONFIG_SYS_PCIE2_PHYS_BASE
 CONFIG_SYS_PCIE2_PHYS_SIZE
 CONFIG_SYS_PCIE2_REGBASE
 CONFIG_SYS_PCIE2_VIRT_ADDR
 CONFIG_SYS_PCIE2_XCFGBASE
 CONFIG_SYS_PCIE3_ADDR
 CONFIG_SYS_PCIE3_IO_BUS
 CONFIG_SYS_PCIE3_IO_PHYS
 CONFIG_SYS_PCIE3_IO_SIZE
 CONFIG_SYS_PCIE3_IO_VIRT
 CONFIG_SYS_PCIE3_MEM_BUS
 CONFIG_SYS_PCIE3_MEM_BUS2
 CONFIG_SYS_PCIE3_MEM_PHYS
 CONFIG_SYS_PCIE3_MEM_PHYS2
 CONFIG_SYS_PCIE3_MEM_SIZE
 CONFIG_SYS_PCIE3_MEM_SIZE2
 CONFIG_SYS_PCIE3_MEM_VIRT
 CONFIG_SYS_PCIE3_MEM_VIRT2
 CONFIG_SYS_PCIE3_NAME
 CONFIG_SYS_PCIE3_PHYS_ADDR
 CONFIG_SYS_PCIE3_PHYS_SIZE
 CONFIG_SYS_PCIE4_ADDR
 CONFIG_SYS_PCIE4_IO_BUS
 CONFIG_SYS_PCIE4_IO_PHYS
 CONFIG_SYS_PCIE4_IO_SIZE
 CONFIG_SYS_PCIE4_IO_VIRT
 CONFIG_SYS_PCIE4_MEM_BUS
 CONFIG_SYS_PCIE4_MEM_PHYS
 CONFIG_SYS_PCIE4_MEM_SIZE
 CONFIG_SYS_PCIE4_MEM_VIRT
 CONFIG_SYS_PCIE4_NAME
 CONFIG_SYS_PCIE4_PHYS_ADDR
 CONFIG_SYS_PCIE4_PHYS_SIZE
 CONFIG_SYS_PCIE_ADDR_HIGH
 CONFIG_SYS_PCIE_BASE
 CONFIG_SYS_PCIE_CFG0_PHYS_OFF
 CONFIG_SYS_PCIE_CFG0_SIZE
 CONFIG_SYS_PCIE_CFG1_PHYS_OFF
 CONFIG_SYS_PCIE_CFG1_SIZE
 CONFIG_SYS_PCIE_INBOUND_BASE
 CONFIG_SYS_PCIE_IO_BUS
 CONFIG_SYS_PCIE_IO_PHYS_OFF
 CONFIG_SYS_PCIE_IO_SIZE
 CONFIG_SYS_PCIE_MEMBASE
 CONFIG_SYS_PCIE_MEMSIZE
 CONFIG_SYS_PCIE_MEM_BUS
 CONFIG_SYS_PCIE_MEM_PHYS_OFF
 CONFIG_SYS_PCIE_MEM_SIZE
 CONFIG_SYS_PCIE_MMAP_SIZE
 CONFIG_SYS_PCIE_NR_PORTS
 CONFIG_SYS_PCIE_PHYS
 CONFIG_SYS_PCIE_VIRT
 CONFIG_SYS_PCIMSK0_MASK
 CONFIG_SYS_PCIMSK1_MASK
 CONFIG_SYS_PCISPEED_66
 CONFIG_SYS_PCI_64BIT
 CONFIG_SYS_PCI_BAR0
 CONFIG_SYS_PCI_BAR1
 CONFIG_SYS_PCI_BAR2
 CONFIG_SYS_PCI_BAR3
 CONFIG_SYS_PCI_BAR4
 CONFIG_SYS_PCI_BAR5
 CONFIG_SYS_PCI_BASE
 CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 CONFIG_SYS_PCI_CACHE_LINE_SIZE
 CONFIG_SYS_PCI_CFG_BASE
 CONFIG_SYS_PCI_CFG_BUS
 CONFIG_SYS_PCI_CFG_PHYS
 CONFIG_SYS_PCI_CFG_SIZE
 CONFIG_SYS_PCI_CLASSCODE
 CONFIG_SYS_PCI_CLASSCODE_MONARCH
 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH
 CONFIG_SYS_PCI_CON_DEVICE
 CONFIG_SYS_PCI_EP_MEMORY_BASE
 CONFIG_SYS_PCI_FORCE_PCI_CONV
 CONFIG_SYS_PCI_IO_BASE
 CONFIG_SYS_PCI_IO_BUS
 CONFIG_SYS_PCI_IO_PHYS
 CONFIG_SYS_PCI_IO_SIZE
 CONFIG_SYS_PCI_MAP_END
 CONFIG_SYS_PCI_MAP_START
 CONFIG_SYS_PCI_MASTER_INIT
 CONFIG_SYS_PCI_MEMBASE
 CONFIG_SYS_PCI_MEMBASE1
 CONFIG_SYS_PCI_MEMBASE2
 CONFIG_SYS_PCI_MEMBASE3
 CONFIG_SYS_PCI_MEMORY_BUS
 CONFIG_SYS_PCI_MEMORY_PHYS
 CONFIG_SYS_PCI_MEMORY_SIZE
 CONFIG_SYS_PCI_MEMSIZE
 CONFIG_SYS_PCI_MEM_BASE
 CONFIG_SYS_PCI_MEM_BUS
 CONFIG_SYS_PCI_MEM_PHYS
 CONFIG_SYS_PCI_MEM_SIZE
 CONFIG_SYS_PCI_MMIO_BASE
 CONFIG_SYS_PCI_MMIO_PHYS
 CONFIG_SYS_PCI_MMIO_SIZE
 CONFIG_SYS_PCI_MSTR0_LOCAL
 CONFIG_SYS_PCI_MSTR1_LOCAL
 CONFIG_SYS_PCI_MSTR_IO_BUS
 CONFIG_SYS_PCI_MSTR_IO_LOCAL
 CONFIG_SYS_PCI_MSTR_IO_SIZE
 CONFIG_SYS_PCI_MSTR_MEMIO_BUS
 CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
 CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
 CONFIG_SYS_PCI_MSTR_MEM_BUS
 CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 CONFIG_SYS_PCI_MSTR_MEM_SIZE
 CONFIG_SYS_PCI_NR_INBOUND_WIN
 CONFIG_SYS_PCI_PHYS
 CONFIG_SYS_PCI_PTM1LA
 CONFIG_SYS_PCI_PTM1MS
 CONFIG_SYS_PCI_PTM1PCI
 CONFIG_SYS_PCI_PTM2LA
 CONFIG_SYS_PCI_PTM2MS
 CONFIG_SYS_PCI_PTM2PCI
 CONFIG_SYS_PCI_SLV_MEM_BUS
 CONFIG_SYS_PCI_SLV_MEM_LOCAL
 CONFIG_SYS_PCI_SLV_MEM_SIZE
 CONFIG_SYS_PCI_SUBSYS_DEVICEID
 CONFIG_SYS_PCI_SUBSYS_DEVICEID2
 CONFIG_SYS_PCI_SUBSYS_ID
 CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH
 CONFIG_SYS_PCI_SUBSYS_VENDORID
 CONFIG_SYS_PCI_SYS_MEM_BUS
 CONFIG_SYS_PCI_SYS_MEM_PHYS
 CONFIG_SYS_PCI_SYS_MEM_SIZE
 CONFIG_SYS_PCI_TARGBASE
 CONFIG_SYS_PCI_TARGET_INIT
 CONFIG_SYS_PCI_TBATR0
 CONFIG_SYS_PCI_TBATR1
 CONFIG_SYS_PCI_TBATR2
 CONFIG_SYS_PCI_TBATR3
 CONFIG_SYS_PCI_TBATR4
 CONFIG_SYS_PCI_TBATR5
 CONFIG_SYS_PCI_VIRT
 CONFIG_SYS_PCMCIA_ATTRB_ADDR
 CONFIG_SYS_PCMCIA_ATTRB_SIZE
 CONFIG_SYS_PCMCIA_ATTR_BASE
 CONFIG_SYS_PCMCIA_CIS_WIN
 CONFIG_SYS_PCMCIA_CIS_WIN_SIZE
 CONFIG_SYS_PCMCIA_DMA_ADDR
 CONFIG_SYS_PCMCIA_DMA_SIZE
 CONFIG_SYS_PCMCIA_IO_ADDR
 CONFIG_SYS_PCMCIA_IO_BASE
 CONFIG_SYS_PCMCIA_IO_SIZE
 CONFIG_SYS_PCMCIA_IO_WIN
 CONFIG_SYS_PCMCIA_IO_WIN_SIZE
 CONFIG_SYS_PCMCIA_MEM_ADDR
 CONFIG_SYS_PCMCIA_MEM_SIZE
 CONFIG_SYS_PCMCIA_PBR0
 CONFIG_SYS_PCMCIA_PBR1
 CONFIG_SYS_PCMCIA_PBR2
 CONFIG_SYS_PCMCIA_PBR3
 CONFIG_SYS_PCMCIA_PBR4
 CONFIG_SYS_PCMCIA_PBR5
 CONFIG_SYS_PCMCIA_PBR6
 CONFIG_SYS_PCMCIA_PBR7
 CONFIG_SYS_PCMCIA_POR0
 CONFIG_SYS_PCMCIA_POR1
 CONFIG_SYS_PCMCIA_POR2
 CONFIG_SYS_PCMCIA_POR3
 CONFIG_SYS_PCMCIA_POR4
 CONFIG_SYS_PCMCIA_POR5
 CONFIG_SYS_PCMCIA_POR6
 CONFIG_SYS_PCMCIA_POR7
 CONFIG_SYS_PCMCIA_TIMING
 CONFIG_SYS_PDCNT
 CONFIG_SYS_PDM360NG_COPROC_BAUDRATE
 CONFIG_SYS_PDM360NG_COPROC_READ_DELAY
 CONFIG_SYS_PEHLPAR
 CONFIG_SYS_PEPAR
 CONFIG_SYS_PERIPHERAL_BASE
 CONFIG_SYS_PFC0
 CONFIG_SYS_PFPAR
 CONFIG_SYS_PHYS_ADDR_HIGH
 CONFIG_SYS_PHY_UBOOT_BASE
 CONFIG_SYS_PIB_BASE
 CONFIG_SYS_PIB_WINDOW_SIZE
 CONFIG_SYS_PICMR0_MASK_ATTRIB
 CONFIG_SYS_PIOC_ASR_VAL
 CONFIG_SYS_PIOC_BSR_VAL
 CONFIG_SYS_PIOC_PDR_VAL
 CONFIG_SYS_PIOC_PDR_VAL1
 CONFIG_SYS_PIOC_PPUDR_VAL
 CONFIG_SYS_PIOD_PDR_VAL1
 CONFIG_SYS_PIOD_PPUDR_VAL
 CONFIG_SYS_PIO_MODE
 CONFIG_SYS_PISCR
 CONFIG_SYS_PIT_BASE
 CONFIG_SYS_PIT_PRESCALE
 CONFIG_SYS_PIXIS_VBOOT_ENABLE
 CONFIG_SYS_PIXIS_VBOOT_MASK
 CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
 CONFIG_SYS_PJPAR
 CONFIG_SYS_PL310_BASE
 CONFIG_SYS_PLATFORM_SRAM_BASE
 CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS
 CONFIG_SYS_PLATFORM_SRAM_SIZE
 CONFIG_SYS_PLL0_DIV
 CONFIG_SYS_PLL0_MUL
 CONFIG_SYS_PLL0_OPT
 CONFIG_SYS_PLL0_SUPPRESS_CYCLES
 CONFIG_SYS_PLLAR_VAL
 CONFIG_SYS_PLLBR_VAL
 CONFIG_SYS_PLLCR
 CONFIG_SYS_PLL_BYPASS
 CONFIG_SYS_PLL_FDR
 CONFIG_SYS_PLL_ODR
 CONFIG_SYS_PLL_RECONFIG
 CONFIG_SYS_PLL_SETTLING_TIME
 CONFIG_SYS_PLPRCR
 CONFIG_SYS_PLUG_BASE
 CONFIG_SYS_PMAN
 CONFIG_SYS_PMC_BASE
 CONFIG_SYS_PMC_BASE_PHYS
 CONFIG_SYS_PME_CLK
 CONFIG_SYS_POCMR0_MASK_ATTRIB
 CONFIG_SYS_POCMR1_MASK_ATTRIB
 CONFIG_SYS_POCMR2_MASK_ATTRIB
 CONFIG_SYS_PORTTC
 CONFIG_SYS_POST_BSPEC1
 CONFIG_SYS_POST_BSPEC2
 CONFIG_SYS_POST_BSPEC3
 CONFIG_SYS_POST_BSPEC4
 CONFIG_SYS_POST_BSPEC5
 CONFIG_SYS_POST_CACHE
 CONFIG_SYS_POST_CACHE_ADDR
 CONFIG_SYS_POST_CODEC
 CONFIG_SYS_POST_COPROC
 CONFIG_SYS_POST_CPU
 CONFIG_SYS_POST_DSP
 CONFIG_SYS_POST_ECC
 CONFIG_SYS_POST_ETHER
 CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
 CONFIG_SYS_POST_ETH_LOOPS
 CONFIG_SYS_POST_FLASH
 CONFIG_SYS_POST_FLASH_END
 CONFIG_SYS_POST_FLASH_NUM
 CONFIG_SYS_POST_FLASH_START
 CONFIG_SYS_POST_FPU
 CONFIG_SYS_POST_FPU_ON
 CONFIG_SYS_POST_HOTKEYS_GPIO
 CONFIG_SYS_POST_I2C
 CONFIG_SYS_POST_I2C_ADDRS
 CONFIG_SYS_POST_I2C_IGNORES
 CONFIG_SYS_POST_MEMORY
 CONFIG_SYS_POST_MEMORY_ON
 CONFIG_SYS_POST_MEM_REGIONS
 CONFIG_SYS_POST_OCM
 CONFIG_SYS_POST_PREREL
 CONFIG_SYS_POST_RTC
 CONFIG_SYS_POST_SPI
 CONFIG_SYS_POST_SPR
 CONFIG_SYS_POST_SYSMON
 CONFIG_SYS_POST_UART
 CONFIG_SYS_POST_UART_TABLE
 CONFIG_SYS_POST_USB
 CONFIG_SYS_POST_WATCHDOG
 CONFIG_SYS_POST_WORD_ADDR
 CONFIG_SYS_POWER_MANAGER
 CONFIG_SYS_PPC4XX_USB_ADDR
 CONFIG_SYS_PPC64
 CONFIG_SYS_PPC_DDR_WIMGE
 CONFIG_SYS_PPC_E500_DEBUG_TLB
 CONFIG_SYS_PQSPAR
 CONFIG_SYS_PRELIM_OR_AM
 CONFIG_SYS_PROMPT_HUSH_PS2
 CONFIG_SYS_PROM_OFFSET
 CONFIG_SYS_PROM_SIZE
 CONFIG_SYS_PSC1
 CONFIG_SYS_PSC3
 CONFIG_SYS_PSC4
 CONFIG_SYS_PSC6
 CONFIG_SYS_PSDMR
 CONFIG_SYS_PSDPAR
 CONFIG_SYS_PSRT
 CONFIG_SYS_PSSR_VAL
 CONFIG_SYS_PTA_PER_CLK
 CONFIG_SYS_PTCPAR
 CONFIG_SYS_PTDPAR
 CONFIG_SYS_PTL2_BITS
 CONFIG_SYS_PTV
 CONFIG_SYS_PUAPAR
 CONFIG_SYS_QE_FMAN_FW_IN_MMC
 CONFIG_SYS_QE_FMAN_FW_IN_NAND
 CONFIG_SYS_QE_FMAN_FW_IN_NOR
 CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 CONFIG_SYS_QE_FMAN_FW_LENGTH
 CONFIG_SYS_QE_FW_ADDR
 CONFIG_SYS_QE_FW_IN_SPIFLASH
 CONFIG_SYS_QMAN_CENA_BASE
 CONFIG_SYS_QMAN_CENA_SIZE
 CONFIG_SYS_QMAN_CINH_BASE
 CONFIG_SYS_QMAN_CINH_SIZE
 CONFIG_SYS_QMAN_MEM_BASE
 CONFIG_SYS_QMAN_MEM_PHYS
 CONFIG_SYS_QMAN_MEM_SIZE
 CONFIG_SYS_QMAN_NUM_PORTALS
 CONFIG_SYS_QMAN_SP_CENA_SIZE
 CONFIG_SYS_QMAN_SP_CINH_SIZE
 CONFIG_SYS_QMAN_SWP_ISDR_REG
 CONFIG_SYS_QRIO_BASE
 CONFIG_SYS_QRIO_BASE_PHYS
 CONFIG_SYS_QRIO_BR_PRELIM
 CONFIG_SYS_QRIO_OR_PRELIM
 CONFIG_SYS_R7780MP_OLD_FLASH
 CONFIG_SYS_RAMBOOT
 CONFIG_SYS_RAM_BASE
 CONFIG_SYS_RAM_CS
 CONFIG_SYS_RAM_END
 CONFIG_SYS_RAM_FREQ_DIV
 CONFIG_SYS_RAM_SIZE
 CONFIG_SYS_RCAR_I2C0_BASE
 CONFIG_SYS_RCAR_I2C0_SPEED
 CONFIG_SYS_RCAR_I2C1_BASE
 CONFIG_SYS_RCAR_I2C1_SPEED
 CONFIG_SYS_RCAR_I2C2_BASE
 CONFIG_SYS_RCAR_I2C2_SPEED
 CONFIG_SYS_RCAR_I2C3_BASE
 CONFIG_SYS_RCAR_I2C3_SPEED
 CONFIG_SYS_RCCR
 CONFIG_SYS_RCWH_PCIHOST
 CONFIG_SYS_READ_SPD
 CONFIG_SYS_REDUNDAND_ENVIRONMENT
 CONFIG_SYS_RELOC_MONITOR_BASE
 CONFIG_SYS_RELOC_MONITOR_MAX_END
 CONFIG_SYS_REMAP_OR_AM
 CONFIG_SYS_RESET_ADDR
 CONFIG_SYS_RESET_ADDRESS
 CONFIG_SYS_RESET_BASE
 CONFIG_SYS_RESET_SCTRL
 CONFIG_SYS_RFD
 CONFIG_SYS_RGMII1_PHY_ADDR
 CONFIG_SYS_RGMII2_PHY_ADDR
 CONFIG_SYS_RIO_MEM_BASE
 CONFIG_SYS_RIO_MEM_BUS
 CONFIG_SYS_RIO_MEM_PHYS
 CONFIG_SYS_RIO_MEM_SIZE
 CONFIG_SYS_RIO_MEM_VIRT
 CONFIG_SYS_RMDS
 CONFIG_SYS_RMR
 CONFIG_SYS_ROM_BASE
 CONFIG_SYS_ROOTPATH
 CONFIG_SYS_RSTC_RMR_VAL
 CONFIG_SYS_RTCSC
 CONFIG_SYS_RTC_BUS_NUM
 CONFIG_SYS_RTC_CNT
 CONFIG_SYS_RTC_DS1337
 CONFIG_SYS_RTC_DS1337_NOOSC
 CONFIG_SYS_RTC_DS1388
 CONFIG_SYS_RTC_OSCILLATOR
 CONFIG_SYS_RTC_PL031_BASE
 CONFIG_SYS_RTC_REG_BASE_ADDR
 CONFIG_SYS_RTC_SETUP
 CONFIG_SYS_RV3029_TCR
 CONFIG_SYS_RX_ETH_BUFFER
 CONFIG_SYS_S3C2410_NAND_HWECC
 CONFIG_SYS_SATA
 CONFIG_SYS_SATA1
 CONFIG_SYS_SATA1_FLAGS
 CONFIG_SYS_SATA1_OFFSET
 CONFIG_SYS_SATA2
 CONFIG_SYS_SATA2_FLAGS
 CONFIG_SYS_SATA2_OFFSET
 CONFIG_SYS_SATA_ENV_DEV
 CONFIG_SYS_SATA_FAT_BOOT_PARTITION
 CONFIG_SYS_SATA_MAX_DEVICE
 CONFIG_SYS_SBFHDR_DATA_OFFSET
 CONFIG_SYS_SBFHDR_SIZE
 CONFIG_SYS_SCCR
 CONFIG_SYS_SCCR_ENCCM
 CONFIG_SYS_SCCR_PCICM
 CONFIG_SYS_SCCR_PCIEXP1CM
 CONFIG_SYS_SCCR_PCIEXP2CM
 CONFIG_SYS_SCCR_SATACM
 CONFIG_SYS_SCCR_TSEC1CM
 CONFIG_SYS_SCCR_TSEC1ON
 CONFIG_SYS_SCCR_TSEC2CM
 CONFIG_SYS_SCCR_TSEC2ON
 CONFIG_SYS_SCCR_TSECCM
 CONFIG_SYS_SCCR_USBDRCM
 CONFIG_SYS_SCCR_USBMPHCM
 CONFIG_SYS_SCC_TOUT_LOOP
 CONFIG_SYS_SCR
 CONFIG_SYS_SCRATCH_VA
 CONFIG_SYS_SCSI_MAXDEVICE
 CONFIG_SYS_SCSI_MAX_DEVICE
 CONFIG_SYS_SCSI_MAX_LUN
 CONFIG_SYS_SCSI_MAX_SCSI_ID
 CONFIG_SYS_SCSI_SPIN_UP_TIME
 CONFIG_SYS_SCSI_SYM53C8XX_CCF
 CONFIG_SYS_SDHC_CLK
 CONFIG_SYS_SDHC_CLK_2_PLL
 CONFIG_SYS_SDIO0
 CONFIG_SYS_SDIO0_MAX_CLK
 CONFIG_SYS_SDIO1
 CONFIG_SYS_SDIO1_MAX_CLK
 CONFIG_SYS_SDIO2
 CONFIG_SYS_SDIO2_MAX_CLK
 CONFIG_SYS_SDIO3
 CONFIG_SYS_SDIO3_MAX_CLK
 CONFIG_SYS_SDIO_BASE0
 CONFIG_SYS_SDIO_BASE1
 CONFIG_SYS_SDIO_BASE2
 CONFIG_SYS_SDIO_BASE3
 CONFIG_SYS_SDMR
 CONFIG_SYS_SDRAM
 CONFIG_SYS_SDRAM0_CFG0
 CONFIG_SYS_SDRAM0_CLKTR
 CONFIG_SYS_SDRAM0_CODT
 CONFIG_SYS_SDRAM0_DLCR
 CONFIG_SYS_SDRAM0_INITPLR0
 CONFIG_SYS_SDRAM0_INITPLR1
 CONFIG_SYS_SDRAM0_INITPLR10
 CONFIG_SYS_SDRAM0_INITPLR11
 CONFIG_SYS_SDRAM0_INITPLR12
 CONFIG_SYS_SDRAM0_INITPLR13
 CONFIG_SYS_SDRAM0_INITPLR14
 CONFIG_SYS_SDRAM0_INITPLR15
 CONFIG_SYS_SDRAM0_INITPLR2
 CONFIG_SYS_SDRAM0_INITPLR3
 CONFIG_SYS_SDRAM0_INITPLR4
 CONFIG_SYS_SDRAM0_INITPLR5
 CONFIG_SYS_SDRAM0_INITPLR6
 CONFIG_SYS_SDRAM0_INITPLR7
 CONFIG_SYS_SDRAM0_INITPLR8
 CONFIG_SYS_SDRAM0_INITPLR9
 CONFIG_SYS_SDRAM0_MB0CF
 CONFIG_SYS_SDRAM0_MB0CF_BASE
 CONFIG_SYS_SDRAM0_MB1CF
 CONFIG_SYS_SDRAM0_MB1CF_BASE
 CONFIG_SYS_SDRAM0_MB2CF
 CONFIG_SYS_SDRAM0_MB3CF
 CONFIG_SYS_SDRAM0_MCOPT1
 CONFIG_SYS_SDRAM0_MCOPT2
 CONFIG_SYS_SDRAM0_MEMODE
 CONFIG_SYS_SDRAM0_MMODE
 CONFIG_SYS_SDRAM0_MODT0
 CONFIG_SYS_SDRAM0_MODT1
 CONFIG_SYS_SDRAM0_MODT2
 CONFIG_SYS_SDRAM0_MODT3
 CONFIG_SYS_SDRAM0_RDCC
 CONFIG_SYS_SDRAM0_RFDC
 CONFIG_SYS_SDRAM0_RQDC
 CONFIG_SYS_SDRAM0_RTR
 CONFIG_SYS_SDRAM0_SDTR1
 CONFIG_SYS_SDRAM0_SDTR2
 CONFIG_SYS_SDRAM0_SDTR3
 CONFIG_SYS_SDRAM0_TR0
 CONFIG_SYS_SDRAM0_WDDCTR
 CONFIG_SYS_SDRAM0_WRDTR
 CONFIG_SYS_SDRAM1
 CONFIG_SYS_SDRAM_BANKS
 CONFIG_SYS_SDRAM_BASE
 CONFIG_SYS_SDRAM_BASE0
 CONFIG_SYS_SDRAM_BASE1
 CONFIG_SYS_SDRAM_BASE1xx
 CONFIG_SYS_SDRAM_BASE2
 CONFIG_SYS_SDRAM_CASL
 CONFIG_SYS_SDRAM_CFG
 CONFIG_SYS_SDRAM_CFG1
 CONFIG_SYS_SDRAM_CFG2
 CONFIG_SYS_SDRAM_CL
 CONFIG_SYS_SDRAM_CONF1HB
 CONFIG_SYS_SDRAM_CONF1LL
 CONFIG_SYS_SDRAM_CONFPATHB
 CONFIG_SYS_SDRAM_CS1
 CONFIG_SYS_SDRAM_CTP
 CONFIG_SYS_SDRAM_CTRL
 CONFIG_SYS_SDRAM_DRVSTRENGTH
 CONFIG_SYS_SDRAM_DRV_STRENGTH
 CONFIG_SYS_SDRAM_EMOD
 CONFIG_SYS_SDRAM_END
 CONFIG_SYS_SDRAM_LDF
 CONFIG_SYS_SDRAM_LIST
 CONFIG_SYS_SDRAM_LOWER
 CONFIG_SYS_SDRAM_MODE
 CONFIG_SYS_SDRAM_PLBADDUHB
 CONFIG_SYS_SDRAM_PLBADDULL
 CONFIG_SYS_SDRAM_PTA
 CONFIG_SYS_SDRAM_R0BAS
 CONFIG_SYS_SDRAM_R1BAS
 CONFIG_SYS_SDRAM_R2BAS
 CONFIG_SYS_SDRAM_R3BAS
 CONFIG_SYS_SDRAM_RCD
 CONFIG_SYS_SDRAM_RFTA
 CONFIG_SYS_SDRAM_SIZE
 CONFIG_SYS_SDRAM_SIZE0
 CONFIG_SYS_SDRAM_SIZE1
 CONFIG_SYS_SDRAM_SIZE_LAW
 CONFIG_SYS_SDRAM_SIZE_MB
 CONFIG_SYS_SDRAM_TABLE
 CONFIG_SYS_SDRAM_UPPER
 CONFIG_SYS_SDRAM_VAL
 CONFIG_SYS_SDRAM_VAL1
 CONFIG_SYS_SDRAM_VAL10
 CONFIG_SYS_SDRAM_VAL11
 CONFIG_SYS_SDRAM_VAL12
 CONFIG_SYS_SDRAM_VAL2
 CONFIG_SYS_SDRAM_VAL3
 CONFIG_SYS_SDRAM_VAL4
 CONFIG_SYS_SDRAM_VAL5
 CONFIG_SYS_SDRAM_VAL6
 CONFIG_SYS_SDRAM_VAL7
 CONFIG_SYS_SDRAM_VAL8
 CONFIG_SYS_SDRAM_VAL9
 CONFIG_SYS_SDRAM_tRC
 CONFIG_SYS_SDRAM_tRCD
 CONFIG_SYS_SDRAM_tRFC
 CONFIG_SYS_SDRAM_tRP
 CONFIG_SYS_SDRC_CR_VAL
 CONFIG_SYS_SDRC_MDR_VAL
 CONFIG_SYS_SDRC_MR_VAL
 CONFIG_SYS_SDRC_MR_VAL1
 CONFIG_SYS_SDRC_MR_VAL2
 CONFIG_SYS_SDRC_MR_VAL3
 CONFIG_SYS_SDRC_MR_VAL4
 CONFIG_SYS_SDRC_MR_VAL5
 CONFIG_SYS_SDRC_TR_VAL
 CONFIG_SYS_SDRC_TR_VAL1
 CONFIG_SYS_SDRC_TR_VAL2
 CONFIG_SYS_SDSR
 CONFIG_SYS_SD_VOLTAGE
 CONFIG_SYS_SEC_MON_ADDR
 CONFIG_SYS_SEC_MON_OFFSET
 CONFIG_SYS_SELF_RST
 CONFIG_SYS_SERIAL0
 CONFIG_SYS_SERIAL1
 CONFIG_SYS_SERIAL2
 CONFIG_SYS_SERIAL3
 CONFIG_SYS_SERIAL4
 CONFIG_SYS_SERIAL5
 CONFIG_SYS_SERIAL_BOOT
 CONFIG_SYS_SFP_ADDR
 CONFIG_SYS_SFP_OFFSET
 CONFIG_SYS_SGMII1_PHY_ADDR
 CONFIG_SYS_SGMII2_PHY_ADDR
 CONFIG_SYS_SGMII3_PHY_ADDR
 CONFIG_SYS_SGMII_LINERATE_MHZ
 CONFIG_SYS_SGMII_RATESCALE
 CONFIG_SYS_SGMII_REFCLK_MHZ
 CONFIG_SYS_SH_SDHI0_BASE
 CONFIG_SYS_SH_SDHI1_BASE
 CONFIG_SYS_SH_SDHI2_BASE
 CONFIG_SYS_SH_SDHI3_BASE
 CONFIG_SYS_SH_SDHI_NR_CHANNEL
 CONFIG_SYS_SICRH
 CONFIG_SYS_SICRL
 CONFIG_SYS_SIL1178_I2C
 CONFIG_SYS_SIMULATE_SPD_EEPROM
 CONFIG_SYS_SIUMCR
 CONFIG_SYS_SIUMCR_HIGH
 CONFIG_SYS_SIUMCR_LOW
 CONFIG_SYS_SJA1000_BASE
 CONFIG_SYS_SMALL_FLASH
 CONFIG_SYS_SMC0_CYCLE0_VAL
 CONFIG_SYS_SMC0_MODE0_VAL
 CONFIG_SYS_SMC0_PULSE0_VAL
 CONFIG_SYS_SMC0_SETUP0_VAL
 CONFIG_SYS_SMC_CSR0_VAL
 CONFIG_SYS_SMC_DPMEM_OFFSET
 CONFIG_SYS_SMC_RXBUFLEN
 CONFIG_SYS_SMC_UCODE_PATCH
 CONFIG_SYS_SMI_BASE
 CONFIG_SYS_SPANSION_BASE
 CONFIG_SYS_SPANSION_BOOT
 CONFIG_SYS_SPC1920_PLD_BASE
 CONFIG_SYS_SPC1920_SMC1_CLK4
 CONFIG_SYS_SPCR_OPT
 CONFIG_SYS_SPCR_TSEC1EP
 CONFIG_SYS_SPCR_TSEC2EP
 CONFIG_SYS_SPCR_TSECEP
 CONFIG_SYS_SPD_BUS_NUM
 CONFIG_SYS_SPD_MAX_DIMMS
 CONFIG_SYS_SPI0
 CONFIG_SYS_SPI0_NUM_CS
 CONFIG_SYS_SPI1
 CONFIG_SYS_SPI1_BASE
 CONFIG_SYS_SPI1_NUM_CS
 CONFIG_SYS_SPI2
 CONFIG_SYS_SPI2_BASE
 CONFIG_SYS_SPI2_NUM_CS
 CONFIG_SYS_SPI_ARGS_OFFS
 CONFIG_SYS_SPI_ARGS_SIZE
 CONFIG_SYS_SPI_BASE
 CONFIG_SYS_SPI_CLK
 CONFIG_SYS_SPI_CS_ACT
 CONFIG_SYS_SPI_CS_BASE
 CONFIG_SYS_SPI_CS_USED
 CONFIG_SYS_SPI_DPMEM_OFFSET
 CONFIG_SYS_SPI_FLASH_U_BOOT_DST
 CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS
 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE
 CONFIG_SYS_SPI_FLASH_U_BOOT_START
 CONFIG_SYS_SPI_INIT_OFFSET
 CONFIG_SYS_SPI_KERNEL_OFFS
 CONFIG_SYS_SPI_MXC_WAIT
 CONFIG_SYS_SPI_RTC_DEVID
 CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
 CONFIG_SYS_SPI_UCODE_PATCH
 CONFIG_SYS_SPI_U_BOOT_OFFS
 CONFIG_SYS_SPI_U_BOOT_SIZE
 CONFIG_SYS_SPI_WRITE_TOUT
 CONFIG_SYS_SPL_ARGS_ADDR
 CONFIG_SYS_SPL_LEN
 CONFIG_SYS_SPL_MALLOC_SIZE
 CONFIG_SYS_SPL_MALLOC_START
 CONFIG_SYS_SPL_MAX_LEN
 CONFIG_SYS_SPR
 CONFIG_SYS_SRAM_BASE
 CONFIG_SYS_SRAM_END
 CONFIG_SYS_SRAM_SIZE
 CONFIG_SYS_SRAM_START
 CONFIG_SYS_SRGPL0_CFG_BAR
 CONFIG_SYS_SRGPL0_MNT_BAR
 CONFIG_SYS_SRGPL0_MSG_BAR
 CONFIG_SYS_SRGPL0_REG_BAR
 CONFIG_SYS_SRIO
 CONFIG_SYS_SRIO1_MEM_BASE
 CONFIG_SYS_SRIO1_MEM_BUS
 CONFIG_SYS_SRIO1_MEM_PHYS
 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH
 CONFIG_SYS_SRIO1_MEM_PHYS_LOW
 CONFIG_SYS_SRIO1_MEM_SIZE
 CONFIG_SYS_SRIO1_MEM_VIRT
 CONFIG_SYS_SRIO2_MEM_PHYS
 CONFIG_SYS_SRIO2_MEM_SIZE
 CONFIG_SYS_SRIO2_MEM_VIRT
 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS
 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR
 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS
 CONFIG_SYS_SSD_BASE
 CONFIG_SYS_SSD_BASE_PHYS
 CONFIG_SYS_SSP_PORT
 CONFIG_SYS_SST_SECT
 CONFIG_SYS_SST_SECTSZ
 CONFIG_SYS_STACKSIZE
 CONFIG_SYS_STACK_LENGTH
 CONFIG_SYS_STACK_SIZE
 CONFIG_SYS_STATUS_C
 CONFIG_SYS_STATUS_OK
 CONFIG_SYS_STDIO_DEREGISTER
 CONFIG_SYS_STMICRO_BOOT
 CONFIG_SYS_SUPPORT_64BIT_DATA
 CONFIG_SYS_SXCNFG_VAL
 CONFIG_SYS_SYPCR
 CONFIG_SYS_SYSTEMACE_BASE
 CONFIG_SYS_SYSTEMACE_WIDTH
 CONFIG_SYS_TBIPA_VALUE
 CONFIG_SYS_TBSCR
 CONFIG_SYS_TCLK
 CONFIG_SYS_TEMP_STACK_OCM
 CONFIG_SYS_TEXT_ADDR
 CONFIG_SYS_TEXT_BASE_NOR
 CONFIG_SYS_TEXT_BASE_SPL
 CONFIG_SYS_TFP410_ADDR
 CONFIG_SYS_TFP410_BUS
 CONFIG_SYS_THUMB_BUILD
 CONFIG_SYS_TIMERBASE
 CONFIG_SYS_TIMER_BASE
 CONFIG_SYS_TIMER_COUNTER
 CONFIG_SYS_TIMER_COUNTS_DOWN
 CONFIG_SYS_TIMER_PRESCALER
 CONFIG_SYS_TIMER_RATE
 CONFIG_SYS_TLB_FOR_BOOT_FLASH
 CONFIG_SYS_TMCNTSC
 CONFIG_SYS_TMPVIRT
 CONFIG_SYS_TMRINTR_MASK
 CONFIG_SYS_TMRINTR_NO
 CONFIG_SYS_TMRINTR_PEND
 CONFIG_SYS_TMRINTR_PRI
 CONFIG_SYS_TMRPND_REG
 CONFIG_SYS_TMR_BASE
 CONFIG_SYS_TMU_CLK_DIV
 CONFIG_SYS_TSEC1
 CONFIG_SYS_TSEC1_OFFSET
 CONFIG_SYS_TSEC2
 CONFIG_SYS_TSEC2_OFFSET
 CONFIG_SYS_TSEC3_OFFSET
 CONFIG_SYS_TX_ETH_BUFFER
 CONFIG_SYS_UART1_ALT1_GPIO
 CONFIG_SYS_UART1_PRI_GPIO
 CONFIG_SYS_UART2_ALT1_GPIO
 CONFIG_SYS_UART2_ALT3_GPIO
 CONFIG_SYS_UART2_PRI_GPIO
 CONFIG_SYS_UART_BASE
 CONFIG_SYS_UART_BAUD
 CONFIG_SYS_UART_FREQ
 CONFIG_SYS_UART_PORT
 CONFIG_SYS_UBOOT_BASE
 CONFIG_SYS_UBOOT_END
 CONFIG_SYS_UBOOT_START
 CONFIG_SYS_UCC_RGMII_MODE
 CONFIG_SYS_UCC_RMII_MODE
 CONFIG_SYS_UDELAY_BASE
 CONFIG_SYS_UEC
 CONFIG_SYS_UEC1_ETH_TYPE
 CONFIG_SYS_UEC1_INTERFACE_SPEED
 CONFIG_SYS_UEC1_INTERFACE_TYPE
 CONFIG_SYS_UEC1_PHY_ADDR
 CONFIG_SYS_UEC1_RX_CLK
 CONFIG_SYS_UEC1_TX_CLK
 CONFIG_SYS_UEC1_UCC_NUM
 CONFIG_SYS_UEC2_ETH_TYPE
 CONFIG_SYS_UEC2_INTERFACE_SPEED
 CONFIG_SYS_UEC2_INTERFACE_TYPE
 CONFIG_SYS_UEC2_PHY_ADDR
 CONFIG_SYS_UEC2_RX_CLK
 CONFIG_SYS_UEC2_TX_CLK
 CONFIG_SYS_UEC2_UCC_NUM
 CONFIG_SYS_UEC3_ETH_TYPE
 CONFIG_SYS_UEC3_INTERFACE_SPEED
 CONFIG_SYS_UEC3_INTERFACE_TYPE
 CONFIG_SYS_UEC3_PHY_ADDR
 CONFIG_SYS_UEC3_RX_CLK
 CONFIG_SYS_UEC3_TX_CLK
 CONFIG_SYS_UEC3_UCC_NUM
 CONFIG_SYS_UEC4_ETH_TYPE
 CONFIG_SYS_UEC4_INTERFACE_SPEED
 CONFIG_SYS_UEC4_INTERFACE_TYPE
 CONFIG_SYS_UEC4_PHY_ADDR
 CONFIG_SYS_UEC4_RX_CLK
 CONFIG_SYS_UEC4_TX_CLK
 CONFIG_SYS_UEC4_UCC_NUM
 CONFIG_SYS_UEC5_ETH_TYPE
 CONFIG_SYS_UEC5_INTERFACE_SPEED
 CONFIG_SYS_UEC5_INTERFACE_TYPE
 CONFIG_SYS_UEC5_PHY_ADDR
 CONFIG_SYS_UEC5_RX_CLK
 CONFIG_SYS_UEC5_TX_CLK
 CONFIG_SYS_UEC5_UCC_NUM
 CONFIG_SYS_UEC6_ETH_TYPE
 CONFIG_SYS_UEC6_INTERFACE_SPEED
 CONFIG_SYS_UEC6_INTERFACE_TYPE
 CONFIG_SYS_UEC6_PHY_ADDR
 CONFIG_SYS_UEC6_RX_CLK
 CONFIG_SYS_UEC6_TX_CLK
 CONFIG_SYS_UEC6_UCC_NUM
 CONFIG_SYS_UEC8_ETH_TYPE
 CONFIG_SYS_UEC8_INTERFACE_SPEED
 CONFIG_SYS_UEC8_INTERFACE_TYPE
 CONFIG_SYS_UEC8_PHY_ADDR
 CONFIG_SYS_UEC8_RX_CLK
 CONFIG_SYS_UEC8_TX_CLK
 CONFIG_SYS_UEC8_UCC_NUM
 CONFIG_SYS_UECx_PHY_ADDR
 CONFIG_SYS_UHC0_EHCI_BASE
 CONFIG_SYS_UHC1_EHCI_BASE
 CONFIG_SYS_ULB_CLK
 CONFIG_SYS_UMCR
 CONFIG_SYS_UNIFY_CACHE
 CONFIG_SYS_UNSPEC_PHYID
 CONFIG_SYS_UNSPEC_STRID
 CONFIG_SYS_UPDATE_FLASH_SIZE
 CONFIG_SYS_USB2D0_BASE
 CONFIG_SYS_USBCTRL
 CONFIG_SYS_USBD_BASE
 CONFIG_SYS_USB_BRGCLK
 CONFIG_SYS_USB_DEVICE
 CONFIG_SYS_USB_EHCI_CPU_INIT
 CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
 CONFIG_SYS_USB_EHCI_REGS_BASE
 CONFIG_SYS_USB_EVENT_POLL
 CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
 CONFIG_SYS_USB_FAT_BOOT_PARTITION
 CONFIG_SYS_USB_HOST
 CONFIG_SYS_USB_OHCI_BOARD_INIT
 CONFIG_SYS_USB_OHCI_CPU_INIT
 CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
 CONFIG_SYS_USB_OHCI_REGS_BASE
 CONFIG_SYS_USB_OHCI_SLOT_NAME
 CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS
 CONFIG_SYS_USER_SWITCHES_BASE
 CONFIG_SYS_USE_BOOT_NORFLASH
 CONFIG_SYS_USE_DATAFLASH
 CONFIG_SYS_USE_DATAFLASH_CS0
 CONFIG_SYS_USE_DATAFLASH_CS1
 CONFIG_SYS_USE_DATAFLASH_CS3
 CONFIG_SYS_USE_DSPLINK
 CONFIG_SYS_USE_FLASH
 CONFIG_SYS_USE_MAIN_OSCILLATOR
 CONFIG_SYS_USE_MMC
 CONFIG_SYS_USE_MPC834XSYS_USB_PHY
 CONFIG_SYS_USE_NAND
 CONFIG_SYS_USE_NANDFLASH
 CONFIG_SYS_USE_NOR
 CONFIG_SYS_USE_NORFLASH
 CONFIG_SYS_USE_PPCENV
 CONFIG_SYS_USE_SERIALFLASH
 CONFIG_SYS_USE_SPIFLASH
 CONFIG_SYS_USE_UBI
 CONFIG_SYS_USR_EXCEP
 CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS
 CONFIG_SYS_U_BOOT_OFFS
 CONFIG_SYS_VA_BITS
 CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
 CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
 CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
 CONFIG_SYS_VCXK_AUTODETECT
 CONFIG_SYS_VCXK_BASE
 CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
 CONFIG_SYS_VCXK_DOUBLEBUFFERED
 CONFIG_SYS_VCXK_ENABLE_DDR
 CONFIG_SYS_VCXK_ENABLE_PIN
 CONFIG_SYS_VCXK_ENABLE_PORT
 CONFIG_SYS_VCXK_INVERT_DDR
 CONFIG_SYS_VCXK_INVERT_PIN
 CONFIG_SYS_VCXK_INVERT_PORT
 CONFIG_SYS_VCXK_REQUEST_DDR
 CONFIG_SYS_VCXK_REQUEST_PIN
 CONFIG_SYS_VCXK_REQUEST_PORT
 CONFIG_SYS_VCXK_RESET_DDR
 CONFIG_SYS_VCXK_RESET_PIN
 CONFIG_SYS_VCXK_RESET_PORT
 CONFIG_SYS_VGA_RAM_EN
 CONFIG_SYS_VIDEO
 CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
 CONFIG_SYS_VPC3_BASE
 CONFIG_SYS_VPC3_SIZE
 CONFIG_SYS_VSC7385_BASE
 CONFIG_SYS_VSC7385_BASE_PHYS
 CONFIG_SYS_VSC7385_BR_PRELIM
 CONFIG_SYS_VSC7385_OR_PRELIM
 CONFIG_SYS_VSC7385_SIZE
 CONFIG_SYS_VSC8601_SKEWFIX
 CONFIG_SYS_VXWORKS_MAC_PTR
 CONFIG_SYS_WATCHDOG_FLAGS_ADDR
 CONFIG_SYS_WATCHDOG_FREQ
 CONFIG_SYS_WATCHDOG_MAGIC
 CONFIG_SYS_WATCHDOG_MAGIC_MASK
 CONFIG_SYS_WATCHDOG_TIME_ADDR
 CONFIG_SYS_WATCHDOG_VALUE
 CONFIG_SYS_WDTC_WDMR_VAL
 CONFIG_SYS_WDTTIMERBASE
 CONFIG_SYS_WDT_PERIOD_HIGH
 CONFIG_SYS_WDT_PERIOD_LOW
 CONFIG_SYS_WHITE_ON_BLACK
 CONFIG_SYS_WINDOW1_BASE
 CONFIG_SYS_WRITE_SWAPPED_DATA
 CONFIG_SYS_XHCI_USB1_ADDR
 CONFIG_SYS_XHCI_USB2_ADDR
 CONFIG_SYS_XHCI_USB3_ADDR
 CONFIG_SYS_XILINX_SPI_LIST
 CONFIG_SYS_XIMG_LEN
 CONFIG_SYS_XLB_PIPELINING
 CONFIG_SYS_XSVF_DEFAULT_ADDR
 CONFIG_SYS_XWAY_EBU_BOOTCFG
 CONFIG_SYS_ZYNQ_QSPI_WAIT
 CONFIG_SYS_ZYNQ_SPI_WAIT
 CONFIG_SYS_i2C_FSL
 CONFIG_T1023RDB
 CONFIG_T1024RDB
 CONFIG_T1040D4RDB
 CONFIG_T1040QDS
 CONFIG_T1040RDB
 CONFIG_T1042D4RDB
 CONFIG_T1042RDB
 CONFIG_T1042RDB_PI
 CONFIG_T104XD4RDB
 CONFIG_T104xRDB
 CONFIG_T2080QDS
 CONFIG_T2080RDB
 CONFIG_T2081QDS
 CONFIG_T4240QDS
 CONFIG_T4240RDB
 CONFIG_TAM3517_SETTINGS
 CONFIG_TAM3517_SW3_SETTINGS
 CONFIG_TCA642X
 CONFIG_TEGRA_BOARD_STRING
 CONFIG_TEGRA_CLOCK_SCALING
 CONFIG_TEGRA_ENABLE_UARTA
 CONFIG_TEGRA_ENABLE_UARTB
 CONFIG_TEGRA_ENABLE_UARTC
 CONFIG_TEGRA_ENABLE_UARTD
 CONFIG_TEGRA_ENABLE_UARTE
 CONFIG_TEGRA_GPU
 CONFIG_TEGRA_KEYBOARD
 CONFIG_TEGRA_LP0
 CONFIG_TEGRA_MMC
 CONFIG_TEGRA_NAND
 CONFIG_TEGRA_PMU
 CONFIG_TEGRA_SLINK_CTRLS
 CONFIG_TEGRA_SPI
 CONFIG_TEGRA_UARTA_GPU
 CONFIG_TEGRA_UARTA_SDIO1
 CONFIG_TEGRA_UARTA_UAA_UAB
 CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
 CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
 CONFIG_TESTPIN_MASK
 CONFIG_TESTPIN_REG
 CONFIG_TEST_LIST_SORT
 CONFIG_TFP410_I2C_ADDR
 CONFIG_TFTP_BLOCKSIZE
 CONFIG_TFTP_FILE_NAME_MAX_LEN
 CONFIG_TFTP_PORT
 CONFIG_TFTP_TSIZE
 CONFIG_THOR_RESET_OFF
 CONFIG_THUMB2_KERNEL
 CONFIG_THUNDERX
 CONFIG_TI814X
 CONFIG_TI816X
 CONFIG_TI816X_DDR_PLL_796
 CONFIG_TI816X_EVM_DDR2
 CONFIG_TI816X_EVM_DDR3
 CONFIG_TI816X_USE_EMIF0
 CONFIG_TI816X_USE_EMIF1
 CONFIG_TI81XX
 CONFIG_TIMER_CLK_FREQ
 CONFIG_TIMESTAMP
 CONFIG_TIZEN
 CONFIG_TI_KEYSTONE_SERDES
 CONFIG_TI_KSNAV
 CONFIG_TI_SPI_MMAP
 CONFIG_TMU_CMD_DTT
 CONFIG_TMU_TIMER
 CONFIG_TOTAL5200
 CONFIG_TPL_DRIVERS_MISC_SUPPORT
 CONFIG_TPL_PAD_TO
 CONFIG_TPM_TIS_BASE_ADDRESS
 CONFIG_TPS6586X_POWER
 CONFIG_TQM5200
 CONFIG_TQM5200S
 CONFIG_TQM5200_B
 CONFIG_TQM5200_REV100
 CONFIG_TQM823L
 CONFIG_TQM823M
 CONFIG_TQM834X
 CONFIG_TQM850L
 CONFIG_TQM850M
 CONFIG_TQM855L
 CONFIG_TQM855M
 CONFIG_TQM860L
 CONFIG_TQM860M
 CONFIG_TQM862L
 CONFIG_TQM862M
 CONFIG_TQM866M
 CONFIG_TQM885D
 CONFIG_TQM8xxL
 CONFIG_TQM8xxM
 CONFIG_TRACE
 CONFIG_TRACE_BUFFER_SIZE
 CONFIG_TRACE_EARLY
 CONFIG_TRACE_EARLY_ADDR
 CONFIG_TRACE_EARLY_SIZE
 CONFIG_TRAILBLAZER
 CONFIG_TRATS
 CONFIG_TRDX_PID_COLIBRI_VF50
 CONFIG_TRDX_PID_COLIBRI_VF50IT
 CONFIG_TRDX_PID_COLIBRI_VF61
 CONFIG_TRDX_PID_COLIBRI_VF61IT
 CONFIG_TRDX_VID
 CONFIG_TSEC
 CONFIG_TSEC1
 CONFIG_TSEC1_NAME
 CONFIG_TSEC2
 CONFIG_TSEC2_NAME
 CONFIG_TSEC3
 CONFIG_TSEC3_NAME
 CONFIG_TSEC4
 CONFIG_TSEC4_NAME
 CONFIG_TSECV2
 CONFIG_TSECV2_1
 CONFIG_TSEC_ENET
 CONFIG_TSEC_TBI
 CONFIG_TSEC_TBICR_SETTINGS
 CONFIG_TSI108_ETH_NUM_PORTS
 CONFIG_TSIM
 CONFIG_TUGE1
 CONFIG_TULIP
 CONFIG_TULIP_FIX_DAVICOM
 CONFIG_TULIP_SELECT_MEDIA
 CONFIG_TULIP_USE_IO
 CONFIG_TUXX1
 CONFIG_TWL4030_INPUT
 CONFIG_TWL4030_KEYPAD
 CONFIG_TWL4030_LED
 CONFIG_TWL4030_POWER
 CONFIG_TWL4030_PWM
 CONFIG_TWL4030_USB
 CONFIG_TWL6030_INPUT
 CONFIG_TWL6030_POWER
 CONFIG_TWR
 CONFIG_TWR_P1025
 CONFIG_TX_DESCR_NUM
 CONFIG_TZSW_RESERVED_DRAM_SIZE
 CONFIG_T_SH7706LSR
 CONFIG_UART_BASE
 CONFIG_UART_BR_PRELIM
 CONFIG_UART_CONSOLE
 CONFIG_UART_CONSOLE_IS_JTAG
 CONFIG_UART_MEM
 CONFIG_UART_OR_PRELIM
 CONFIG_UBIBLOCK
 CONFIG_UBIFS_SILENCE_MSG
 CONFIG_UBIFS_VOLUME
 CONFIG_UBI_PART
 CONFIG_UBI_SILENCE_MSG
 CONFIG_UBI_SIZE
 CONFIG_UBOOT1_ENV_ADDR
 CONFIG_UBOOT2_ENV_ADDR
 CONFIG_UBOOTPATH
 CONFIG_UBOOT_ENABLE_PADS_ALL
 CONFIG_UBOOT_ENV_ADDR
 CONFIG_UBOOT_SECTOR_COUNT
 CONFIG_UBOOT_SECTOR_START
 CONFIG_UCP1020
 CONFIG_UCP1020_REV_1_3
 CONFIG_UDP_CHECKSUM
 CONFIG_UEC_ETH
 CONFIG_UEC_ETH1
 CONFIG_UEC_ETH2
 CONFIG_UEC_ETH3
 CONFIG_UEC_ETH4
 CONFIG_UEC_ETH5
 CONFIG_UEC_ETH6
 CONFIG_UEC_ETH7
 CONFIG_UEC_ETH8
 CONFIG_UID16
 CONFIG_ULI526X
 CONFIG_ULPI_REF_CLK
 CONFIG_UMSDEVS
 CONFIG_UNIPHIER_ETH
 CONFIG_UPDATEB
 CONFIG_UPDATE_LOAD_ADDR
 CONFIG_UPDATE_TFTP
 CONFIG_UPDATE_TFTP_CNT_MAX
 CONFIG_UPDATE_TFTP_MSEC_MAX
 CONFIG_USART1
 CONFIG_USART3
 CONFIG_USART_BASE
 CONFIG_USART_ID
 CONFIG_USBBOOTCOMMAND
 CONFIG_USBDEBUG
 CONFIG_USBD_CONFIGURATION_STR
 CONFIG_USBD_CTRL_INTERFACE_STR
 CONFIG_USBD_DATA_INTERFACE_STR
 CONFIG_USBD_HS
 CONFIG_USBD_MANUFACTURER
 CONFIG_USBD_PRODUCTID
 CONFIG_USBD_PRODUCTID_CDCACM
 CONFIG_USBD_PRODUCTID_GSERIAL
 CONFIG_USBD_PRODUCT_NAME
 CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE
 CONFIG_USBD_SERIAL_BULK_PKTSIZE
 CONFIG_USBD_SERIAL_INT_ENDPOINT
 CONFIG_USBD_SERIAL_INT_PKTSIZE
 CONFIG_USBD_SERIAL_IN_ENDPOINT
 CONFIG_USBD_SERIAL_IN_PKTSIZE
 CONFIG_USBD_SERIAL_OUT_ENDPOINT
 CONFIG_USBD_SERIAL_OUT_PKTSIZE
 CONFIG_USBD_VENDORID
 CONFIG_USBID_ADDR
 CONFIG_USBNET_DEV_ADDR
 CONFIG_USBNET_HOST_ADDR
 CONFIG_USBNET_MANUFACTURER
 CONFIG_USBTTY
 CONFIG_USB_AM35X
 CONFIG_USB_ATMEL
 CONFIG_USB_ATMEL_CLK_SEL_PLLB
 CONFIG_USB_ATMEL_CLK_SEL_UPLL
 CONFIG_USB_BIN_FIXUP
 CONFIG_USB_BLACKFIN
 CONFIG_USB_BLACKFIN_CLKIN
 CONFIG_USB_BOOTING
 CONFIG_USB_CABLE_CHECK
 CONFIG_USB_CLOCK
 CONFIG_USB_CONFIG
 CONFIG_USB_DEVICE
 CONFIG_USB_DEV_BASE
 CONFIG_USB_DEV_PULLUP_GPIO
 CONFIG_USB_DWC2
 CONFIG_USB_DWC2_REG_ADDR
 CONFIG_USB_EHCI_ARMADA100
 CONFIG_USB_EHCI_BASE
 CONFIG_USB_EHCI_BASE_LIST
 CONFIG_USB_EHCI_EXYNOS
 CONFIG_USB_EHCI_FARADAY
 CONFIG_USB_EHCI_FSL
 CONFIG_USB_EHCI_KIRKWOOD
 CONFIG_USB_EHCI_MX5
 CONFIG_USB_EHCI_MXC
 CONFIG_USB_EHCI_MXS
 CONFIG_USB_EHCI_OMAP
 CONFIG_USB_EHCI_PCI
 CONFIG_USB_EHCI_PPC4XX
 CONFIG_USB_EHCI_RMOBILE
 CONFIG_USB_EHCI_SPEAR
 CONFIG_USB_EHCI_SUNXI
 CONFIG_USB_EHCI_TEGRA
 CONFIG_USB_EHCI_TXFIFO_THRESH
 CONFIG_USB_EHCI_VCT
 CONFIG_USB_EHCI_VF
 CONFIG_USB_ETHER
 CONFIG_USB_ETHER_ASIX
 CONFIG_USB_ETHER_ASIX88179
 CONFIG_USB_ETHER_DM9601
 CONFIG_USB_ETHER_MCS7830
 CONFIG_USB_ETHER_RNDIS
 CONFIG_USB_ETHER_RTL8152
 CONFIG_USB_ETHER_SMSC95XX
 CONFIG_USB_ETHER_xxx
 CONFIG_USB_ETH_CDC
 CONFIG_USB_ETH_QMULT
 CONFIG_USB_ETH_RNDIS
 CONFIG_USB_ETH_SUBSET
 CONFIG_USB_EXT2_BOOT
 CONFIG_USB_FAT_BOOT
 CONFIG_USB_FREQ
 CONFIG_USB_FUNCTION_DFU
 CONFIG_USB_FUNCTION_MASS_STORAGE
 CONFIG_USB_FUNCTION_THOR
 CONFIG_USB_GADGET_AMD5536UDC
 CONFIG_USB_GADGET_AT91
 CONFIG_USB_GADGET_AU1X00
 CONFIG_USB_GADGET_DUMMY_HCD
 CONFIG_USB_GADGET_DWC2_OTG_PHY
 CONFIG_USB_GADGET_FOTG210
 CONFIG_USB_GADGET_FSL_USB2
 CONFIG_USB_GADGET_GOKU
 CONFIG_USB_GADGET_IMX
 CONFIG_USB_GADGET_M66592
 CONFIG_USB_GADGET_MASS_STORAGE
 CONFIG_USB_GADGET_MPC8272
 CONFIG_USB_GADGET_MQ11XX
 CONFIG_USB_GADGET_MUSBHSFC
 CONFIG_USB_GADGET_N9604
 CONFIG_USB_GADGET_NET2280
 CONFIG_USB_GADGET_OMAP
 CONFIG_USB_GADGET_PXA27X
 CONFIG_USB_GADGET_PXA2XX
 CONFIG_USB_GADGET_S3C2410
 CONFIG_USB_GADGET_SA1100
 CONFIG_USB_GADGET_SUPERH
 CONFIG_USB_GADGET_SX2
 CONFIG_USB_HOST_ETHER
 CONFIG_USB_HOST_XHCI_BASE
 CONFIG_USB_INVENTRA_DMA
 CONFIG_USB_ISP1301_I2C_ADDR
 CONFIG_USB_MAX_CONTROLLER_COUNT
 CONFIG_USB_MUSB_AM35X
 CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 CONFIG_USB_MUSB_DSPS
 CONFIG_USB_MUSB_HCD
 CONFIG_USB_MUSB_OMAP2PLUS
 CONFIG_USB_MUSB_PIO_ONLY
 CONFIG_USB_MUSB_TIMEOUT
 CONFIG_USB_MUSB_TUSB6010
 CONFIG_USB_MUSB_UDC
 CONFIG_USB_MUSB_UDD
 CONFIG_USB_OHCI
 CONFIG_USB_OHCI_EP93XX
 CONFIG_USB_OHCI_LPC32XX
 CONFIG_USB_OHCI_NEW
 CONFIG_USB_OHCI_S3C24XX
 CONFIG_USB_OHCI_SUNXI
 CONFIG_USB_OMAP3
 CONFIG_USB_OTG
 CONFIG_USB_OTG_BLACKLIST_HUB
 CONFIG_USB_PHY_CFG_BASE
 CONFIG_USB_PHY_TYPE
 CONFIG_USB_PXA25X_SMALL
 CONFIG_USB_R8A66597_HCD
 CONFIG_USB_SERIALNO
 CONFIG_USB_SS_BASE
 CONFIG_USB_TI_CPPI_DMA
 CONFIG_USB_TTY
 CONFIG_USB_TUSB_OMAP_DMA
 CONFIG_USB_UHCI
 CONFIG_USB_ULPI_TIMEOUT
 CONFIG_USB_XHCI_EXYNOS
 CONFIG_USB_XHCI_FSL
 CONFIG_USB_XHCI_KEYSTONE
 CONFIG_USB_XHCI_OMAP
 CONFIG_USB_XHCI_PCI
 CONFIG_USB_XHCI_ZYNQMP
 CONFIG_USER_LOWLEVEL_INIT
 CONFIG_USE_ARCH_MEMCPY
 CONFIG_USE_ARCH_MEMSET
 CONFIG_USE_FDT
 CONFIG_USE_INTERRUPT
 CONFIG_USE_IRQ
 CONFIG_USE_NAND
 CONFIG_USE_NETDEV
 CONFIG_USE_NOR
 CONFIG_USE_ONENAND_BOARD_INIT
 CONFIG_USE_SPIFLASH
 CONFIG_USE_STDINT
 CONFIG_USE_TTY
 CONFIG_UTBIPAR_INIT_TBIPA
 CONFIG_U_BOOT_HDR_ADDR
 CONFIG_U_BOOT_HDR_SIZE
 CONFIG_U_QE
 CONFIG_V38B
 CONFIG_VAL
 CONFIG_VAR_SIZE_SPL
 CONFIG_VCMA9
 CONFIG_VCO_HZ
 CONFIG_VCO_MULT
 CONFIG_VCT_NOR
 CONFIG_VE8313
 CONFIG_VERY_BIG_RAM
 CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
 CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
 CONFIG_VF610
 CONFIG_VID
 CONFIG_VIDEO_BCM2835
 CONFIG_VIDEO_BMP_GZIP
 CONFIG_VIDEO_BMP_LOGO
 CONFIG_VIDEO_BMP_RLE8
 CONFIG_VIDEO_CORALP
 CONFIG_VIDEO_DA8XX
 CONFIG_VIDEO_DT_SIMPLEFB
 CONFIG_VIDEO_FONT_4X6
 CONFIG_VIDEO_IPUV3
 CONFIG_VIDEO_LCD_I2C_BUS
 CONFIG_VIDEO_LOGO
 CONFIG_VIDEO_MB862xx
 CONFIG_VIDEO_MB862xx_ACCEL
 CONFIG_VIDEO_MX3
 CONFIG_VIDEO_MXS
 CONFIG_VIDEO_MXS_MODE_SYSTEM
 CONFIG_VIDEO_OMAP3
 CONFIG_VIDEO_ONBOARD
 CONFIG_VIDEO_SM501
 CONFIG_VIDEO_SM501_16BPP
 CONFIG_VIDEO_SM501_32BPP
 CONFIG_VIDEO_SM501_8BPP
 CONFIG_VIDEO_SM501_PCI
 CONFIG_VIDEO_STD_TIMINGS
 CONFIG_VIDEO_SUNXI
 CONFIG_VIDEO_VCXK
 CONFIG_VID_FLS_ENV
 CONFIG_VM86
 CONFIG_VME8349
 CONFIG_VOIPAC_LCD
 CONFIG_VOL_MONITOR_INA220
 CONFIG_VOL_MONITOR_IR36021_READ
 CONFIG_VOL_MONITOR_IR36021_SET
 CONFIG_VOM405
 CONFIG_VR_CTL_CLKBUF
 CONFIG_VR_CTL_FREQ
 CONFIG_VR_CTL_VAL
 CONFIG_VR_CTL_VLEV
 CONFIG_VSC7385_ENET
 CONFIG_VSC7385_IMAGE
 CONFIG_VSC7385_IMAGE_SIZE
 CONFIG_VSC9953
 CONFIG_VSC_CROSSBAR
 CONFIG_WALNUT
 CONFIG_WATCHDOG
 CONFIG_WATCHDOG_BASEADDR
 CONFIG_WATCHDOG_IRQ
 CONFIG_WATCHDOG_NOWAYOUT
 CONFIG_WATCHDOG_PRESC
 CONFIG_WATCHDOG_RC
 CONFIG_WATCHDOG_TIMEOUT
 CONFIG_WATCHDOG_TIMEOUT_MSECS
 CONFIG_WDOG_GPIO_PIN
 CONFIG_WD_MAX_RATE
 CONFIG_WD_PERIOD
 CONFIG_WINBOND_83C553
 CONFIG_X600
 CONFIG_X86EMU_DEBUG
 CONFIG_X86EMU_RAW_IO
 CONFIG_X86_64
 CONFIG_X86_BSWAP
 CONFIG_X86_MRC_ADDR
 CONFIG_X86_REFCODE_ADDR
 CONFIG_X86_REFCODE_RUN_ADDR
 CONFIG_XGI_XG22_BASE
 CONFIG_XILINX_405
 CONFIG_XILINX_440
 CONFIG_XILINX_GPIO
 CONFIG_XILINX_LL_TEMAC
 CONFIG_XILINX_LL_TEMAC_CLK
 CONFIG_XILINX_PPC440_GENERIC
 CONFIG_XILINX_SPI_IDLE_VAL
 CONFIG_XILINX_TB_WATCHDOG
 CONFIG_XPEDITE1000
 CONFIG_XPEDITE5140
 CONFIG_XPEDITE5200
 CONFIG_XPEDITE5370
 CONFIG_XPEDITE550X
 CONFIG_XR16L2751
 CONFIG_XSENGINE
 CONFIG_XTFPGA
 CONFIG_YAFFS2
 CONFIG_YAFFSFS_PROVIDE_VALUES
 CONFIG_YAFFS_AUTO_UNICODE
 CONFIG_YAFFS_CASE_INSENSITIVE
 CONFIG_YAFFS_DEFINES_TYPES
 CONFIG_YAFFS_DIRECT
 CONFIG_YAFFS_PROVIDE_DEFS
 CONFIG_YAFFS_UNICODE
 CONFIG_YAFFS_UTIL
 CONFIG_YAFFS_WINCE
 CONFIG_YELLOWSTONE
 CONFIG_YELLOW_LED
 CONFIG_YOSEMITE
 CONFIG_ZBOOT_32
 CONFIG_ZC770_XM010
 CONFIG_ZC770_XM011
 CONFIG_ZC770_XM012
 CONFIG_ZC770_XM013
 CONFIG_ZLIB
 CONFIG_ZLT
 CONFIG_ZM7300
 CONFIG_ZYNQMP_EEPROM
 CONFIG_ZYNQMP_XHCI_LIST
 CONFIG_ZYNQ_EEPROM
 CONFIG_ZYNQ_EEPROM_BUS
 CONFIG_ZYNQ_GEM_EEPROM_ADDR
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
 CONFIG_ZYNQ_HISPD_BROKEN
 CONFIG_ZYNQ_I2C0
 CONFIG_ZYNQ_I2C1
 CONFIG_ZYNQ_PS_CLK_FREQ
 CONFIG_ZYNQ_SDHCI0
 CONFIG_ZYNQ_SDHCI1
 CONFIG_ZYNQ_SDHCI_MAX_FREQ
 CONFIG_ZYNQ_SDHCI_MIN_FREQ
 CONFIG_ZYNQ_SERIAL
 CONFIG_eTSEC_MDIO_BUS