Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit b97476965bf292c13074e01de4bd39253de0ef66

Authored by Vikas Manocha
Committed by Tom Rini
1 parent ea744fca0e
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

stm32: stm32f7: add spl build support 

This commit supports booting from stm32 internal nor flash. spl U-Boot
initializes the sdram memory, copies next image (e.g. standard U-Boot)
to sdram & then jumps to entry point.

Here are the flash memory addresses for U-Boot-spl & standard U-Boot:
	- spl U-Boot		: 0x0800_0000
	- standard U-Boot	: 0x0800_8000

To compile u-boot without spl: Remove SUPPORT_SPL configuration
(arch/arm/mach-stm32/Kconfig)

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Rework Kconfig logic a bit]
Signed-off-by: Tom Rini <trini@konsulko.com>

Showing 5 changed files with 65 additions and 3 deletions Inline Diff

arch/arm/mach-stm32/Kconfig
Diff comments   View file @ b974769
1 if STM32 1 if STM32
2 2
3 config STM32F4 3 config STM32F4
4 bool "stm32f4 family" 4 bool "stm32f4 family"
5 5
6 config STM32F1 6 config STM32F1
7 bool "stm32f1 family" 7 bool "stm32f1 family"
8 8
9 config STM32F7 9 config STM32F7
10 bool "stm32f7 family" 10 bool "stm32f7 family"
11 select SUPPORT_SPL
12 select SPL
13 select SPL_CLK
14 select SPL_DM
15 select SPL_DM_SEQ_ALIAS
16 select SPL_DRIVERS_MISC_SUPPORT
17 select SPL_GPIO_SUPPORT
18 select SPL_LIBCOMMON_SUPPORT
19 select SPL_LIBGENERIC_SUPPORT
20 select SPL_MTD_SUPPORT
21 select SPL_OF_CONTROL
22 select SPL_OF_LIBFDT
23 select SPL_OF_TRANSLATE
24 select SPL_PINCTRL
25 select SPL_RAM
26 select SPL_SERIAL_SUPPORT
27 select SPL_SYS_MALLOC_SIMPLE
11 28
12 source "arch/arm/mach-stm32/stm32f4/Kconfig" 29 source "arch/arm/mach-stm32/stm32f4/Kconfig"
13 source "arch/arm/mach-stm32/stm32f1/Kconfig" 30 source "arch/arm/mach-stm32/stm32f1/Kconfig"
14 source "arch/arm/mach-stm32/stm32f7/Kconfig" 31 source "arch/arm/mach-stm32/stm32f7/Kconfig"
15 32
16 endif 33 endif
17 34
board/st/stm32f746-disco/stm32f746-disco.c
Diff comments   View file @ b974769
1 /* 1 /*
2 * (C) Copyright 2016 2 * (C) Copyright 2016
3 * Vikas Manocha, <vikas.manocha@st.com> 3 * Vikas Manocha, <vikas.manocha@st.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <dm.h> 9 #include <dm.h>
10 #include <ram.h> 10 #include <ram.h>
11 #include <spl.h>
11 #include <asm/io.h> 12 #include <asm/io.h>
12 #include <asm/armv7m.h> 13 #include <asm/armv7m.h>
13 #include <asm/arch/stm32.h> 14 #include <asm/arch/stm32.h>
14 #include <asm/arch/gpio.h> 15 #include <asm/arch/gpio.h>
15 #include <asm/arch/fmc.h> 16 #include <asm/arch/fmc.h>
16 #include <dm/platform_data/serial_stm32x7.h> 17 #include <dm/platform_data/serial_stm32x7.h>
17 #include <asm/arch/stm32_periph.h> 18 #include <asm/arch/stm32_periph.h>
18 #include <asm/arch/stm32_defs.h> 19 #include <asm/arch/stm32_defs.h>
19 #include <asm/arch/syscfg.h> 20 #include <asm/arch/syscfg.h>
20 #include <asm/gpio.h> 21 #include <asm/gpio.h>
21 22
22 DECLARE_GLOBAL_DATA_PTR; 23 DECLARE_GLOBAL_DATA_PTR;
23 24
24 int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size) 25 int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size)
25 { 26 {
26 int mr_node; 27 int mr_node;
27 28
28 mr_node = fdt_path_offset(gd->fdt_blob, "/memory"); 29 mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
29 if (mr_node < 0) 30 if (mr_node < 0)
30 return mr_node; 31 return mr_node;
31 *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node, 32 *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
32 "reg", 0, mr_size, false); 33 "reg", 0, mr_size, false);
33 debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size); 34 debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size);
34 35
35 return 0; 36 return 0;
36 } 37 }
37 int dram_init(void) 38 int dram_init(void)
38 { 39 {
39 struct udevice *dev;
40 int rv; 40 int rv;
41 fdt_addr_t mr_base, mr_size; 41 fdt_addr_t mr_base, mr_size;
42 42
43 #ifndef CONFIG_SUPPORT_SPL
44 struct udevice *dev;
43 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 45 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
44 if (rv) { 46 if (rv) {
45 debug("DRAM init failed: %d\n", rv); 47 debug("DRAM init failed: %d\n", rv);
46 return rv; 48 return rv;
47 } 49 }
48 50
51 #endif
49 rv = get_memory_base_size(&mr_base, &mr_size); 52 rv = get_memory_base_size(&mr_base, &mr_size);
50 if (rv) 53 if (rv)
51 return rv; 54 return rv;
52 gd->ram_size = mr_size; 55 gd->ram_size = mr_size;
53 gd->ram_top = mr_base; 56 gd->ram_top = mr_base;
54 57
55 return rv; 58 return rv;
56 } 59 }
57 60
58 int dram_init_banksize(void) 61 int dram_init_banksize(void)
59 { 62 {
60 fdt_addr_t mr_base, mr_size; 63 fdt_addr_t mr_base, mr_size;
61 get_memory_base_size(&mr_base, &mr_size); 64 get_memory_base_size(&mr_base, &mr_size);
62 /* 65 /*
63 * Fill in global info with description of SRAM configuration 66 * Fill in global info with description of SRAM configuration
64 */ 67 */
65 gd->bd->bi_dram[0].start = mr_base; 68 gd->bd->bi_dram[0].start = mr_base;
66 gd->bd->bi_dram[0].size = mr_size; 69 gd->bd->bi_dram[0].size = mr_size;
67 70
68 return 0; 71 return 0;
69 } 72 }
70 73
71 #ifdef CONFIG_ETH_DESIGNWARE 74 #ifdef CONFIG_ETH_DESIGNWARE
72 static int stmmac_setup(void) 75 static int stmmac_setup(void)
73 { 76 {
74 clock_setup(SYSCFG_CLOCK_CFG); 77 clock_setup(SYSCFG_CLOCK_CFG);
75 /* Set >RMII mode */ 78 /* Set >RMII mode */
76 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; 79 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
77 clock_setup(STMMAC_CLOCK_CFG); 80 clock_setup(STMMAC_CLOCK_CFG);
78 81
79 return 0; 82 return 0;
80 } 83 }
81 84
82 int board_early_init_f(void) 85 int board_early_init_f(void)
83 { 86 {
84 stmmac_setup(); 87 stmmac_setup();
85 88
86 return 0; 89 return 0;
87 } 90 }
88 #endif 91 #endif
89 92
93 #ifdef CONFIG_SPL_BUILD
94 int spl_dram_init(void)
95 {
96 struct udevice *dev;
97 int rv;
98 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
99 if (rv)
100 debug("DRAM init failed: %d\n", rv);
101 return rv;
102 }
103 void spl_board_init(void)
104 {
105 spl_dram_init();
106 preloader_console_init();
107 arch_cpu_init(); /* to configure mpu for sdram rw permissions */
108 }
109 u32 spl_boot_device(void)
110 {
111 return BOOT_DEVICE_NOR;
112 }
113
114 #endif
90 u32 get_board_rev(void) 115 u32 get_board_rev(void)
91 { 116 {
92 return 0; 117 return 0;
93 } 118 }
94 119
95 int board_late_init(void) 120 int board_late_init(void)
96 { 121 {
97 struct gpio_desc gpio = {}; 122 struct gpio_desc gpio = {};
98 int node; 123 int node;
99 124
100 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1"); 125 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
101 if (node < 0) 126 if (node < 0)
102 return -1; 127 return -1;
103 128
104 gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio, 129 gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
105 GPIOD_IS_OUT); 130 GPIOD_IS_OUT);
106 131
107 if (dm_gpio_is_valid(&gpio)) { 132 if (dm_gpio_is_valid(&gpio)) {
108 dm_gpio_set_value(&gpio, 0); 133 dm_gpio_set_value(&gpio, 0);
109 mdelay(10); 134 mdelay(10);
110 dm_gpio_set_value(&gpio, 1); 135 dm_gpio_set_value(&gpio, 1);
111 } 136 }
112 137
113 /* read button 1*/ 138 /* read button 1*/
114 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1"); 139 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
115 if (node < 0) 140 if (node < 0)
116 return -1; 141 return -1;
117 142
118 gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0, 143 gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
119 &gpio, GPIOD_IS_IN); 144 &gpio, GPIOD_IS_IN);
120 145
121 if (dm_gpio_is_valid(&gpio)) { 146 if (dm_gpio_is_valid(&gpio)) {
122 if (dm_gpio_get_value(&gpio)) 147 if (dm_gpio_get_value(&gpio))
123 puts("usr button is at HIGH LEVEL\n"); 148 puts("usr button is at HIGH LEVEL\n");
124 else 149 else
125 puts("usr button is at LOW LEVEL\n"); 150 puts("usr button is at LOW LEVEL\n");
126 } 151 }
127 152
128 return 0; 153 return 0;
129 } 154 }
130 155
131 int board_init(void) 156 int board_init(void)
132 { 157 {
133 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; 158 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
134 return 0; 159 return 0;
135 } 160 }
configs/stm32f746-disco_defconfig
Diff comments   View file @ b974769
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_STM32=y 2 CONFIG_STM32=y
3 CONFIG_STM32F7=y 3 CONFIG_STM32F7=y
4 CONFIG_TARGET_STM32F746_DISCO=y 4 CONFIG_TARGET_STM32F746_DISCO=y
5 CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" 5 CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
6 CONFIG_BOOTDELAY=3 6 CONFIG_BOOTDELAY=3
7 # CONFIG_DISPLAY_CPUINFO is not set 7 # CONFIG_DISPLAY_CPUINFO is not set
8 # CONFIG_DISPLAY_BOARDINFO is not set 8 # CONFIG_DISPLAY_BOARDINFO is not set
9 CONFIG_BOARD_EARLY_INIT_F=y 9 CONFIG_BOARD_EARLY_INIT_F=y
10 CONFIG_HUSH_PARSER=y 10 CONFIG_HUSH_PARSER=y
11 CONFIG_SYS_PROMPT="U-Boot > " 11 CONFIG_SYS_PROMPT="U-Boot > "
12 CONFIG_AUTOBOOT_KEYED=y 12 CONFIG_AUTOBOOT_KEYED=y
13 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" 13 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
14 CONFIG_AUTOBOOT_STOP_STR=" " 14 CONFIG_AUTOBOOT_STOP_STR=" "
15 # CONFIG_CMD_IMLS is not set 15 # CONFIG_CMD_IMLS is not set
16 CONFIG_CMD_SF=y 16 CONFIG_CMD_SF=y
17 # CONFIG_CMD_FPGA is not set 17 # CONFIG_CMD_FPGA is not set
18 # CONFIG_CMD_SETEXPR is not set 18 # CONFIG_CMD_SETEXPR is not set
19 CONFIG_CMD_DHCP=y 19 CONFIG_CMD_DHCP=y
20 CONFIG_CMD_MII=y 20 CONFIG_CMD_MII=y
21 CONFIG_CMD_PING=y 21 CONFIG_CMD_PING=y
22 CONFIG_CMD_SNTP=y 22 CONFIG_CMD_SNTP=y
23 CONFIG_CMD_DNS=y 23 CONFIG_CMD_DNS=y
24 CONFIG_CMD_LINK_LOCAL=y 24 CONFIG_CMD_LINK_LOCAL=y
25 CONFIG_CMD_TIMER=y 25 CONFIG_CMD_TIMER=y
26 CONFIG_OF_CONTROL=y 26 CONFIG_OF_CONTROL=y
27 CONFIG_DM_SEQ_ALIAS=y 27 CONFIG_DM_SEQ_ALIAS=y
28 CONFIG_NET_RANDOM_ETHADDR=y 28 CONFIG_NET_RANDOM_ETHADDR=y
29 CONFIG_NETCONSOLE=y 29 CONFIG_NETCONSOLE=y
30 CONFIG_CLK=y 30 CONFIG_CLK=y
31 # CONFIG_MMC is not set 31 # CONFIG_MMC is not set
32 CONFIG_MTD=y 32 CONFIG_MTD=y
33 CONFIG_MTD_NOR_FLASH=y 33 CONFIG_MTD_NOR_FLASH=y
34 CONFIG_DM_SPI_FLASH=y 34 CONFIG_DM_SPI_FLASH=y
35 CONFIG_SPI_FLASH=y 35 CONFIG_SPI_FLASH=y
36 CONFIG_SPI_FLASH_STMICRO=y 36 CONFIG_SPI_FLASH_STMICRO=y
37 CONFIG_DM_ETH=y 37 CONFIG_DM_ETH=y
38 CONFIG_ETH_DESIGNWARE=y 38 CONFIG_ETH_DESIGNWARE=y
39 CONFIG_PINCTRL=y 39 CONFIG_PINCTRL=y
40 # CONFIG_PINCTRL_FULL is not set 40 # CONFIG_PINCTRL_FULL is not set
41 CONFIG_PINCTRL_STM32=y 41 CONFIG_PINCTRL_STM32=y
42 # CONFIG_SPL_SERIAL_PRESENT is not set
43 CONFIG_DM_SPI=y 42 CONFIG_DM_SPI=y
44 CONFIG_STM32_QSPI=y 43 CONFIG_STM32_QSPI=y
45 CONFIG_OF_LIBFDT_OVERLAY=y 44 CONFIG_OF_LIBFDT_OVERLAY=y
46 # CONFIG_EFI_LOADER is not set 45 # CONFIG_EFI_LOADER is not set
47 CONFIG_RAM=y 46 CONFIG_RAM=y
48 CONFIG_STM32_SDRAM=y 47 CONFIG_STM32_SDRAM=y
49 CONFIG_DM_GPIO=y 48 CONFIG_DM_GPIO=y
50 CONFIG_STM32F7_GPIO=y 49 CONFIG_STM32F7_GPIO=y
51 CONFIG_SYS_MALLOC_F_LEN=0xC00 50 CONFIG_SYS_MALLOC_F_LEN=0xC00
52 51
drivers/pinctrl/Kconfig
Diff comments   View file @ b974769
1 # 1 #
2 # PINCTRL infrastructure and drivers 2 # PINCTRL infrastructure and drivers
3 # 3 #
4 4
5 menu "Pin controllers" 5 menu "Pin controllers"
6 6
7 config PINCTRL 7 config PINCTRL
8 bool "Support pin controllers" 8 bool "Support pin controllers"
9 depends on DM 9 depends on DM
10 help 10 help
11 This enables the basic support for pinctrl framework. You may want 11 This enables the basic support for pinctrl framework. You may want
12 to enable some more options depending on what you want to do. 12 to enable some more options depending on what you want to do.
13 13
14 config PINCTRL_FULL 14 config PINCTRL_FULL
15 bool "Support full pin controllers" 15 bool "Support full pin controllers"
16 depends on PINCTRL && OF_CONTROL 16 depends on PINCTRL && OF_CONTROL
17 default y 17 default y
18 help 18 help
19 This provides Linux-compatible device tree interface for the pinctrl 19 This provides Linux-compatible device tree interface for the pinctrl
20 subsystem. This feature depends on device tree configuration because 20 subsystem. This feature depends on device tree configuration because
21 it parses a device tree to look for the pinctrl device which the 21 it parses a device tree to look for the pinctrl device which the
22 peripheral device is associated with. 22 peripheral device is associated with.
23 23
24 If this option is disabled (it is the only possible choice for non-DT 24 If this option is disabled (it is the only possible choice for non-DT
25 boards), the pinctrl core provides no systematic mechanism for 25 boards), the pinctrl core provides no systematic mechanism for
26 identifying peripheral devices, applying needed pinctrl settings. 26 identifying peripheral devices, applying needed pinctrl settings.
27 It is totally up to the implementation of each low-level driver. 27 It is totally up to the implementation of each low-level driver.
28 You can save memory footprint in return for some limitations. 28 You can save memory footprint in return for some limitations.
29 29
30 config PINCTRL_GENERIC 30 config PINCTRL_GENERIC
31 bool "Support generic pin controllers" 31 bool "Support generic pin controllers"
32 depends on PINCTRL_FULL 32 depends on PINCTRL_FULL
33 default y 33 default y
34 help 34 help
35 Say Y here if you want to use the pinctrl subsystem through the 35 Say Y here if you want to use the pinctrl subsystem through the
36 generic DT interface. If enabled, some functions become available 36 generic DT interface. If enabled, some functions become available
37 to parse common properties such as "pins", "groups", "functions" and 37 to parse common properties such as "pins", "groups", "functions" and
38 some pin configuration parameters. It would be easier if you only 38 some pin configuration parameters. It would be easier if you only
39 need the generic DT interface for pin muxing and pin configuration. 39 need the generic DT interface for pin muxing and pin configuration.
40 If you need to handle vendor-specific DT properties, you can disable 40 If you need to handle vendor-specific DT properties, you can disable
41 this option and implement your own set_state callback in the pinctrl 41 this option and implement your own set_state callback in the pinctrl
42 operations. 42 operations.
43 43
44 config PINMUX 44 config PINMUX
45 bool "Support pin multiplexing controllers" 45 bool "Support pin multiplexing controllers"
46 depends on PINCTRL_GENERIC 46 depends on PINCTRL_GENERIC
47 default y 47 default y
48 help 48 help
49 This option enables pin multiplexing through the generic pinctrl 49 This option enables pin multiplexing through the generic pinctrl
50 framework. Most SoCs have their own own multiplexing arrangement 50 framework. Most SoCs have their own own multiplexing arrangement
51 where a single pin can be used for several functions. An SoC pinctrl 51 where a single pin can be used for several functions. An SoC pinctrl
52 driver allows the required function to be selected for each pin. 52 driver allows the required function to be selected for each pin.
53 The driver is typically controlled by the device tree. 53 The driver is typically controlled by the device tree.
54 54
55 config PINCONF 55 config PINCONF
56 bool "Support pin configuration controllers" 56 bool "Support pin configuration controllers"
57 depends on PINCTRL_GENERIC 57 depends on PINCTRL_GENERIC
58 help 58 help
59 This option enables pin configuration through the generic pinctrl 59 This option enables pin configuration through the generic pinctrl
60 framework. 60 framework.
61 61
62 config SPL_PINCTRL 62 config SPL_PINCTRL
63 bool "Support pin controlloers in SPL" 63 bool "Support pin controlloers in SPL"
64 depends on SPL && SPL_DM 64 depends on SPL && SPL_DM
65 help 65 help
66 This option is an SPL-variant of the PINCTRL option. 66 This option is an SPL-variant of the PINCTRL option.
67 See the help of PINCTRL for details. 67 See the help of PINCTRL for details.
68 68
69 config SPL_PINCTRL_FULL 69 config SPL_PINCTRL_FULL
70 bool "Support full pin controllers in SPL" 70 bool "Support full pin controllers in SPL"
71 depends on SPL_PINCTRL && SPL_OF_CONTROL 71 depends on SPL_PINCTRL && SPL_OF_CONTROL
72 default n if TARGET_STM32F746_DISCO
72 default y 73 default y
73 help 74 help
74 This option is an SPL-variant of the PINCTRL_FULL option. 75 This option is an SPL-variant of the PINCTRL_FULL option.
75 See the help of PINCTRL_FULL for details. 76 See the help of PINCTRL_FULL for details.
76 77
77 config SPL_PINCTRL_GENERIC 78 config SPL_PINCTRL_GENERIC
78 bool "Support generic pin controllers in SPL" 79 bool "Support generic pin controllers in SPL"
79 depends on SPL_PINCTRL_FULL 80 depends on SPL_PINCTRL_FULL
80 default y 81 default y
81 help 82 help
82 This option is an SPL-variant of the PINCTRL_GENERIC option. 83 This option is an SPL-variant of the PINCTRL_GENERIC option.
83 See the help of PINCTRL_GENERIC for details. 84 See the help of PINCTRL_GENERIC for details.
84 85
85 config SPL_PINMUX 86 config SPL_PINMUX
86 bool "Support pin multiplexing controllers in SPL" 87 bool "Support pin multiplexing controllers in SPL"
87 depends on SPL_PINCTRL_GENERIC 88 depends on SPL_PINCTRL_GENERIC
88 default y 89 default y
89 help 90 help
90 This option is an SPL-variant of the PINMUX option. 91 This option is an SPL-variant of the PINMUX option.
91 See the help of PINMUX for details. 92 See the help of PINMUX for details.
92 The pinctrl subsystem can add a substantial overhead to the SPL 93 The pinctrl subsystem can add a substantial overhead to the SPL
93 image since it typically requires quite a few tables either in the 94 image since it typically requires quite a few tables either in the
94 driver or in the device tree. If this is acceptable and you need 95 driver or in the device tree. If this is acceptable and you need
95 to adjust pin multiplexing in SPL in order to boot into U-Boot, 96 to adjust pin multiplexing in SPL in order to boot into U-Boot,
96 enable this option. You will need to enable device tree in SPL 97 enable this option. You will need to enable device tree in SPL
97 for this to work. 98 for this to work.
98 99
99 config SPL_PINCONF 100 config SPL_PINCONF
100 bool "Support pin configuration controllers in SPL" 101 bool "Support pin configuration controllers in SPL"
101 depends on SPL_PINCTRL_GENERIC 102 depends on SPL_PINCTRL_GENERIC
102 help 103 help
103 This option is an SPL-variant of the PINCONF option. 104 This option is an SPL-variant of the PINCONF option.
104 See the help of PINCONF for details. 105 See the help of PINCONF for details.
105 106
106 if PINCTRL || SPL_PINCTRL 107 if PINCTRL || SPL_PINCTRL
107 108
108 config PINCTRL_AR933X 109 config PINCTRL_AR933X
109 bool "QCA/Athores ar933x pin control driver" 110 bool "QCA/Athores ar933x pin control driver"
110 depends on DM && SOC_AR933X 111 depends on DM && SOC_AR933X
111 help 112 help
112 Support pin multiplexing control on QCA/Athores ar933x SoCs. 113 Support pin multiplexing control on QCA/Athores ar933x SoCs.
113 The driver is controlled by a device tree node which contains 114 The driver is controlled by a device tree node which contains
114 both the GPIO definitions and pin control functions for each 115 both the GPIO definitions and pin control functions for each
115 available multiplex function. 116 available multiplex function.
116 117
117 config PINCTRL_AT91 118 config PINCTRL_AT91
118 bool "AT91 pinctrl driver" 119 bool "AT91 pinctrl driver"
119 depends on DM 120 depends on DM
120 help 121 help
121 This option is to enable the AT91 pinctrl driver for AT91 PIO 122 This option is to enable the AT91 pinctrl driver for AT91 PIO
122 controller. 123 controller.
123 124
124 AT91 PIO controller is a combined gpio-controller, pin-mux and 125 AT91 PIO controller is a combined gpio-controller, pin-mux and
125 pin-config module. Each I/O pin may be dedicated as a general-purpose 126 pin-config module. Each I/O pin may be dedicated as a general-purpose
126 I/O or be assigned to a function of an embedded peripheral. Each I/O 127 I/O or be assigned to a function of an embedded peripheral. Each I/O
127 pin has a glitch filter providing rejection of glitches lower than 128 pin has a glitch filter providing rejection of glitches lower than
128 one-half of peripheral clock cycle and a debouncing filter providing 129 one-half of peripheral clock cycle and a debouncing filter providing
129 rejection of unwanted pulses from key or push button operations. You 130 rejection of unwanted pulses from key or push button operations. You
130 can also control the multi-driver capability, pull-up and pull-down 131 can also control the multi-driver capability, pull-up and pull-down
131 feature on each I/O pin. 132 feature on each I/O pin.
132 133
133 config PINCTRL_AT91PIO4 134 config PINCTRL_AT91PIO4
134 bool "AT91 PIO4 pinctrl driver" 135 bool "AT91 PIO4 pinctrl driver"
135 depends on DM 136 depends on DM
136 help 137 help
137 This option is to enable the AT91 pinctrl driver for AT91 PIO4 138 This option is to enable the AT91 pinctrl driver for AT91 PIO4
138 controller which is available on SAMA5D2 SoC. 139 controller which is available on SAMA5D2 SoC.
139 140
140 config PINCTRL_PIC32 141 config PINCTRL_PIC32
141 bool "Microchip PIC32 pin-control and pin-mux driver" 142 bool "Microchip PIC32 pin-control and pin-mux driver"
142 depends on DM && MACH_PIC32 143 depends on DM && MACH_PIC32
143 default y 144 default y
144 help 145 help
145 Supports individual pin selection and configuration for each 146 Supports individual pin selection and configuration for each
146 remappable peripheral available on Microchip PIC32 147 remappable peripheral available on Microchip PIC32
147 SoCs. This driver is controlled by a device tree node which 148 SoCs. This driver is controlled by a device tree node which
148 contains both GPIO defintion and pin control functions. 149 contains both GPIO defintion and pin control functions.
149 150
150 config PINCTRL_QCA953X 151 config PINCTRL_QCA953X
151 bool "QCA/Athores qca953x pin control driver" 152 bool "QCA/Athores qca953x pin control driver"
152 depends on DM && SOC_QCA953X 153 depends on DM && SOC_QCA953X
153 help 154 help
154 Support pin multiplexing control on QCA/Athores qca953x SoCs. 155 Support pin multiplexing control on QCA/Athores qca953x SoCs.
155 156
156 The driver is controlled by a device tree node which contains both 157 The driver is controlled by a device tree node which contains both
157 the GPIO definitions and pin control functions for each available 158 the GPIO definitions and pin control functions for each available
158 multiplex function. 159 multiplex function.
159 160
160 config PINCTRL_ROCKCHIP_RK3036 161 config PINCTRL_ROCKCHIP_RK3036
161 bool "Rockchip rk3036 pin control driver" 162 bool "Rockchip rk3036 pin control driver"
162 depends on DM 163 depends on DM
163 help 164 help
164 Support pin multiplexing control on Rockchip rk3036 SoCs. 165 Support pin multiplexing control on Rockchip rk3036 SoCs.
165 166
166 The driver is controlled by a device tree node which contains both 167 The driver is controlled by a device tree node which contains both
167 the GPIO definitions and pin control functions for each available 168 the GPIO definitions and pin control functions for each available
168 multiplex function. 169 multiplex function.
169 170
170 config PINCTRL_ROCKCHIP_RK3188 171 config PINCTRL_ROCKCHIP_RK3188
171 bool "Rockchip rk3188 pin control driver" 172 bool "Rockchip rk3188 pin control driver"
172 depends on DM 173 depends on DM
173 help 174 help
174 Support pin multiplexing control on Rockchip rk3188 SoCs. 175 Support pin multiplexing control on Rockchip rk3188 SoCs.
175 176
176 The driver is controlled by a device tree node which contains both 177 The driver is controlled by a device tree node which contains both
177 the GPIO definitions and pin control functions for each available 178 the GPIO definitions and pin control functions for each available
178 multiplex function. 179 multiplex function.
179 180
180 config PINCTRL_ROCKCHIP_RK3288 181 config PINCTRL_ROCKCHIP_RK3288
181 bool "Rockchip rk3288 pin control driver" 182 bool "Rockchip rk3288 pin control driver"
182 depends on DM 183 depends on DM
183 help 184 help
184 Support pin multiplexing control on Rockchip rk3288 SoCs. 185 Support pin multiplexing control on Rockchip rk3288 SoCs.
185 186
186 The driver is controlled by a device tree node which contains both 187 The driver is controlled by a device tree node which contains both
187 the GPIO definitions and pin control functions for each available 188 the GPIO definitions and pin control functions for each available
188 multiplex function. 189 multiplex function.
189 190
190 config PINCTRL_ROCKCHIP_RK3328 191 config PINCTRL_ROCKCHIP_RK3328
191 bool "Rockchip rk3328 pin control driver" 192 bool "Rockchip rk3328 pin control driver"
192 depends on DM 193 depends on DM
193 help 194 help
194 Support pin multiplexing control on Rockchip rk3328 SoCs. 195 Support pin multiplexing control on Rockchip rk3328 SoCs.
195 196
196 The driver is controlled by a device tree node which contains both 197 The driver is controlled by a device tree node which contains both
197 the GPIO definitions and pin control functions for each available 198 the GPIO definitions and pin control functions for each available
198 multiplex function. 199 multiplex function.
199 200
200 config PINCTRL_ROCKCHIP_RK3368 201 config PINCTRL_ROCKCHIP_RK3368
201 bool "Rockchip RK3368 pin control driver" 202 bool "Rockchip RK3368 pin control driver"
202 depends on DM 203 depends on DM
203 help 204 help
204 Support pin multiplexing control on Rockchip rk3368 SoCs. 205 Support pin multiplexing control on Rockchip rk3368 SoCs.
205 206
206 The driver is controlled by a device tree node which contains both 207 The driver is controlled by a device tree node which contains both
207 the GPIO definitions and pin control functions for each available 208 the GPIO definitions and pin control functions for each available
208 multiplex function. 209 multiplex function.
209 210
210 config PINCTRL_ROCKCHIP_RK3399 211 config PINCTRL_ROCKCHIP_RK3399
211 bool "Rockchip rk3399 pin control driver" 212 bool "Rockchip rk3399 pin control driver"
212 depends on DM 213 depends on DM
213 help 214 help
214 Support pin multiplexing control on Rockchip rk3399 SoCs. 215 Support pin multiplexing control on Rockchip rk3399 SoCs.
215 216
216 The driver is controlled by a device tree node which contains both 217 The driver is controlled by a device tree node which contains both
217 the GPIO definitions and pin control functions for each available 218 the GPIO definitions and pin control functions for each available
218 multiplex function. 219 multiplex function.
219 220
220 config PINCTRL_ROCKCHIP_RV1108 221 config PINCTRL_ROCKCHIP_RV1108
221 bool "Rockchip rv1108 pin control driver" 222 bool "Rockchip rv1108 pin control driver"
222 depends on DM 223 depends on DM
223 help 224 help
224 Support pin multiplexing control on Rockchip rv1108 SoC. 225 Support pin multiplexing control on Rockchip rv1108 SoC.
225 226
226 The driver is controlled by a device tree node which contains 227 The driver is controlled by a device tree node which contains
227 both the GPIO definitions and pin control functions for each 228 both the GPIO definitions and pin control functions for each
228 available multiplex function. 229 available multiplex function.
229 230
230 config PINCTRL_SANDBOX 231 config PINCTRL_SANDBOX
231 bool "Sandbox pinctrl driver" 232 bool "Sandbox pinctrl driver"
232 depends on SANDBOX 233 depends on SANDBOX
233 help 234 help
234 This enables pinctrl driver for sandbox. 235 This enables pinctrl driver for sandbox.
235 236
236 Currently, this driver actually does nothing but print debug 237 Currently, this driver actually does nothing but print debug
237 messages when pinctrl operations are invoked. 238 messages when pinctrl operations are invoked.
238 239
239 config PINCTRL_SINGLE 240 config PINCTRL_SINGLE
240 bool "Single register pin-control and pin-multiplex driver" 241 bool "Single register pin-control and pin-multiplex driver"
241 depends on DM 242 depends on DM
242 help 243 help
243 This enables pinctrl driver for systems using a single register for 244 This enables pinctrl driver for systems using a single register for
244 pin configuration and multiplexing. TI's AM335X SoCs are examples of 245 pin configuration and multiplexing. TI's AM335X SoCs are examples of
245 such systems. 246 such systems.
246 247
247 Depending on the platform make sure to also enable OF_TRANSLATE and 248 Depending on the platform make sure to also enable OF_TRANSLATE and
248 eventually SPL_OF_TRANSLATE to get correct address translations. 249 eventually SPL_OF_TRANSLATE to get correct address translations.
249 250
250 config PINCTRL_STI 251 config PINCTRL_STI
251 bool "STMicroelectronics STi pin-control and pin-mux driver" 252 bool "STMicroelectronics STi pin-control and pin-mux driver"
252 depends on DM && ARCH_STI 253 depends on DM && ARCH_STI
253 default y 254 default y
254 help 255 help
255 Support pin multiplexing control on STMicrolectronics STi SoCs. 256 Support pin multiplexing control on STMicrolectronics STi SoCs.
256 257
257 The driver is controlled by a device tree node which contains both 258 The driver is controlled by a device tree node which contains both
258 the GPIO definitions and pin control functions for each available 259 the GPIO definitions and pin control functions for each available
259 multiplex function. 260 multiplex function.
260 261
261 config PINCTRL_STM32 262 config PINCTRL_STM32
262 bool "ST STM32 pin control driver" 263 bool "ST STM32 pin control driver"
263 depends on DM 264 depends on DM
264 help 265 help
265 Supports pin multiplexing control on stm32 SoCs. 266 Supports pin multiplexing control on stm32 SoCs.
266 267
267 The driver is controlled by a device tree node which contains both 268 The driver is controlled by a device tree node which contains both
268 the GPIO definitions and pin control functions for each available 269 the GPIO definitions and pin control functions for each available
269 multiplex function. 270 multiplex function.
270 271
271 config ASPEED_AST2500_PINCTRL 272 config ASPEED_AST2500_PINCTRL
272 bool "Aspeed AST2500 pin control driver" 273 bool "Aspeed AST2500 pin control driver"
273 depends on DM && PINCTRL_GENERIC && ASPEED_AST2500 274 depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
274 default y 275 default y
275 help 276 help
276 Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses 277 Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses
277 Generic Pinctrl framework and is compatible with the Linux driver, 278 Generic Pinctrl framework and is compatible with the Linux driver,
278 i.e. it uses the same device tree configuration. 279 i.e. it uses the same device tree configuration.
279 280
280 endif 281 endif
281 282
282 source "drivers/pinctrl/meson/Kconfig" 283 source "drivers/pinctrl/meson/Kconfig"
283 source "drivers/pinctrl/nxp/Kconfig" 284 source "drivers/pinctrl/nxp/Kconfig"
284 source "drivers/pinctrl/uniphier/Kconfig" 285 source "drivers/pinctrl/uniphier/Kconfig"
285 source "drivers/pinctrl/exynos/Kconfig" 286 source "drivers/pinctrl/exynos/Kconfig"
286 source "drivers/pinctrl/mvebu/Kconfig" 287 source "drivers/pinctrl/mvebu/Kconfig"
287 288
288 endmenu 289 endmenu
289 290
include/configs/stm32f746-disco.h
Diff comments   View file @ b974769
1 /* 1 /*
2 * (C) Copyright 2016 2 * (C) Copyright 2016
3 * Vikas Manocha, <vikas.manocha@st.com> 3 * Vikas Manocha, <vikas.manocha@st.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef __CONFIG_H 8 #ifndef __CONFIG_H
9 #define __CONFIG_H 9 #define __CONFIG_H
10 10
11 #define CONFIG_SYS_FLASH_BASE 0x08000000 11 #define CONFIG_SYS_FLASH_BASE 0x08000000
12 #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 12 #define CONFIG_SYS_INIT_SP_ADDR 0x20050000
13 #define CONFIG_SYS_TEXT_BASE 0x08000000
14 13
14 #ifdef CONFIG_SUPPORT_SPL
15 #define CONFIG_SYS_TEXT_BASE 0xC0000000
16 #else
17 #define CONFIG_SYS_TEXT_BASE CONFIG_SYS_FLASH_BASE
18 #endif
19
15 /* 20 /*
16 * Configuration of the external SDRAM memory 21 * Configuration of the external SDRAM memory
17 */ 22 */
18 #define CONFIG_NR_DRAM_BANKS 1 23 #define CONFIG_NR_DRAM_BANKS 1
19 #define CONFIG_SYS_LOAD_ADDR 0xC0400000 24 #define CONFIG_SYS_LOAD_ADDR 0xC0400000
20 #define CONFIG_LOADADDR 0xC0400000 25 #define CONFIG_LOADADDR 0xC0400000
21 26
22 #define CONFIG_SYS_MAX_FLASH_SECT 8 27 #define CONFIG_SYS_MAX_FLASH_SECT 8
23 #define CONFIG_SYS_MAX_FLASH_BANKS 1 28 #define CONFIG_SYS_MAX_FLASH_BANKS 1
24 29
25 #define CONFIG_ENV_IS_NOWHERE 30 #define CONFIG_ENV_IS_NOWHERE
26 #define CONFIG_ENV_SIZE (8 << 10) 31 #define CONFIG_ENV_SIZE (8 << 10)
27 32
28 #define CONFIG_STM32_FLASH 33 #define CONFIG_STM32_FLASH
29 #define CONFIG_STM32X7_SERIAL 34 #define CONFIG_STM32X7_SERIAL
30 35
31 #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) 36 #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
32 #define CONFIG_DW_ALTDESCRIPTOR 37 #define CONFIG_DW_ALTDESCRIPTOR
33 #define CONFIG_MII 38 #define CONFIG_MII
34 #define CONFIG_PHY_SMSC 39 #define CONFIG_PHY_SMSC
35 40
36 #define CONFIG_STM32_HSE_HZ 25000000 41 #define CONFIG_STM32_HSE_HZ 25000000
37 #define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */ 42 #define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */
38 #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ 43 #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
39 44
40 #define CONFIG_CMDLINE_TAG 45 #define CONFIG_CMDLINE_TAG
41 #define CONFIG_SETUP_MEMORY_TAGS 46 #define CONFIG_SETUP_MEMORY_TAGS
42 #define CONFIG_INITRD_TAG 47 #define CONFIG_INITRD_TAG
43 #define CONFIG_REVISION_TAG 48 #define CONFIG_REVISION_TAG
44 49
45 #define CONFIG_SYS_CBSIZE 1024 50 #define CONFIG_SYS_CBSIZE 1024
46 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 51 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
47 + sizeof(CONFIG_SYS_PROMPT) + 16) 52 + sizeof(CONFIG_SYS_PROMPT) + 16)
48 53
49 #define CONFIG_SYS_MAXARGS 16 54 #define CONFIG_SYS_MAXARGS 16
50 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 55 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
51 56
52 #define CONFIG_BOOTARGS \ 57 #define CONFIG_BOOTARGS \
53 "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" 58 "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
54 #define CONFIG_BOOTCOMMAND \ 59 #define CONFIG_BOOTCOMMAND \
55 "run bootcmd_romfs" 60 "run bootcmd_romfs"
56 61
57 #define CONFIG_EXTRA_ENV_SETTINGS \ 62 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ 63 "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
59 "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ 64 "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
60 "bootm 0x08044000 - 0x08042000\0" 65 "bootm 0x08044000 - 0x08042000\0"
61 66
62 67
63 /* 68 /*
64 * Command line configuration. 69 * Command line configuration.
65 */ 70 */
66 #define CONFIG_SYS_LONGHELP 71 #define CONFIG_SYS_LONGHELP
67 #define CONFIG_AUTO_COMPLETE 72 #define CONFIG_AUTO_COMPLETE
68 #define CONFIG_CMDLINE_EDITING 73 #define CONFIG_CMDLINE_EDITING
69 #define CONFIG_CMD_CACHE 74 #define CONFIG_CMD_CACHE
70 #define CONFIG_BOARD_LATE_INIT 75 #define CONFIG_BOARD_LATE_INIT
71 #define CONFIG_DISPLAY_BOARDINFO 76 #define CONFIG_DISPLAY_BOARDINFO
77
78 /* For SPL */
79 #ifdef CONFIG_SUPPORT_SPL
80 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
81 #define CONFIG_SPL_FRAMEWORK
82 #define CONFIG_SPL_BOARD_INIT
83 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE
84 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
85 #define CONFIG_SYS_SPL_LEN 0x00008000
86 #define CONFIG_SYS_UBOOT_START 0XC00003FD
87 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
88 CONFIG_SYS_SPL_LEN)
89 #endif
90 /* For SPL ends */
91
72 #endif /* __CONFIG_H */ 92 #endif /* __CONFIG_H */