Eric Lee / smarc-uboot

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/*

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/*

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* Steven J. Hill <sjhill@realitydiluted.com>

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* Steven J. Hill <sjhill@realitydiluted.com>

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* Thomas Gleixner <tglx@linutronix.de>

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* Thomas Gleixner <tglx@linutronix.de>

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*

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*

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* SPDX-License-Identifier: GPL-2.0+

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* SPDX-License-Identifier: GPL-2.0+

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*

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*

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* Info:

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* Info:

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* Contains standard defines and IDs for NAND flash devices

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* Contains standard defines and IDs for NAND flash devices

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*

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*

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* Changelog:

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* Changelog:

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* See git changelog.

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* See git changelog.

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*/

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*/

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#ifndef __LINUX_MTD_RAWNAND_H

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#ifndef __LINUX_MTD_RAWNAND_H

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#define __LINUX_MTD_RAWNAND_H

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#define __LINUX_MTD_RAWNAND_H

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#include <config.h>

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#include <config.h>

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#include <linux/compat.h>

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#include <linux/compat.h>

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#include <linux/mtd/mtd.h>

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#include <linux/mtd/mtd.h>

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#include <linux/mtd/flashchip.h>

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#include <linux/mtd/flashchip.h>

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#include <linux/mtd/bbm.h>

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#include <linux/mtd/bbm.h>

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#include <asm/cache.h>

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struct mtd_info;

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struct mtd_info;

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struct nand_flash_dev;

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struct nand_flash_dev;

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struct device_node;

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struct device_node;

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/* Scan and identify a NAND device */

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/* Scan and identify a NAND device */

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int nand_scan(struct mtd_info *mtd, int max_chips);

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int nand_scan(struct mtd_info *mtd, int max_chips);

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/*

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/*

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* Separate phases of nand_scan(), allowing board driver to intervene

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* Separate phases of nand_scan(), allowing board driver to intervene

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* and override command or ECC setup according to flash type.

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* and override command or ECC setup according to flash type.

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*/

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*/

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int nand_scan_ident(struct mtd_info *mtd, int max_chips,

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int nand_scan_ident(struct mtd_info *mtd, int max_chips,

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struct nand_flash_dev *table);

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struct nand_flash_dev *table);

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int nand_scan_tail(struct mtd_info *mtd);

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int nand_scan_tail(struct mtd_info *mtd);

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/* Free resources held by the NAND device */

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/* Free resources held by the NAND device */

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void nand_release(struct mtd_info *mtd);

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void nand_release(struct mtd_info *mtd);

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/* Internal helper for board drivers which need to override command function */

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/* Internal helper for board drivers which need to override command function */

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void nand_wait_ready(struct mtd_info *mtd);

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void nand_wait_ready(struct mtd_info *mtd);

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/*

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/*

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* This constant declares the max. oobsize / page, which

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* This constant declares the max. oobsize / page, which

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* is supported now. If you add a chip with bigger oobsize/page

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* is supported now. If you add a chip with bigger oobsize/page

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* adjust this accordingly.

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* adjust this accordingly.

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*/

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*/

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#define NAND_MAX_OOBSIZE 1664

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#define NAND_MAX_OOBSIZE 1664

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#define NAND_MAX_PAGESIZE 16384

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#define NAND_MAX_PAGESIZE 16384

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/*

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/*

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* Constants for hardware specific CLE/ALE/NCE function

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* Constants for hardware specific CLE/ALE/NCE function

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*

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*

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* These are bits which can be or'ed to set/clear multiple

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* These are bits which can be or'ed to set/clear multiple

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* bits in one go.

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* bits in one go.

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*/

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*/

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/* Select the chip by setting nCE to low */

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/* Select the chip by setting nCE to low */

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#define NAND_NCE 0x01

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#define NAND_NCE 0x01

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/* Select the command latch by setting CLE to high */

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/* Select the command latch by setting CLE to high */

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#define NAND_CLE 0x02

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#define NAND_CLE 0x02

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/* Select the address latch by setting ALE to high */

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/* Select the address latch by setting ALE to high */

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#define NAND_ALE 0x04

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#define NAND_ALE 0x04

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#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)

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#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)

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#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)

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#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)

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#define NAND_CTRL_CHANGE 0x80

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#define NAND_CTRL_CHANGE 0x80

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/*

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/*

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* Standard NAND flash commands

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* Standard NAND flash commands

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*/

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*/

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#define NAND_CMD_READ0 0

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#define NAND_CMD_READ0 0

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#define NAND_CMD_READ1 1

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#define NAND_CMD_READ1 1

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#define NAND_CMD_RNDOUT 5

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#define NAND_CMD_RNDOUT 5

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#define NAND_CMD_PAGEPROG 0x10

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#define NAND_CMD_PAGEPROG 0x10

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#define NAND_CMD_READOOB 0x50

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#define NAND_CMD_READOOB 0x50

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#define NAND_CMD_ERASE1 0x60

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#define NAND_CMD_ERASE1 0x60

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#define NAND_CMD_STATUS 0x70

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#define NAND_CMD_STATUS 0x70

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#define NAND_CMD_SEQIN 0x80

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#define NAND_CMD_SEQIN 0x80

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#define NAND_CMD_RNDIN 0x85

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#define NAND_CMD_RNDIN 0x85

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#define NAND_CMD_READID 0x90

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#define NAND_CMD_READID 0x90

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#define NAND_CMD_ERASE2 0xd0

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#define NAND_CMD_ERASE2 0xd0

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#define NAND_CMD_PARAM 0xec

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#define NAND_CMD_PARAM 0xec

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#define NAND_CMD_GET_FEATURES 0xee

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#define NAND_CMD_GET_FEATURES 0xee

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#define NAND_CMD_SET_FEATURES 0xef

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#define NAND_CMD_SET_FEATURES 0xef

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#define NAND_CMD_RESET 0xff

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#define NAND_CMD_RESET 0xff

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#define NAND_CMD_LOCK 0x2a

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#define NAND_CMD_LOCK 0x2a

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#define NAND_CMD_UNLOCK1 0x23

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#define NAND_CMD_UNLOCK1 0x23

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#define NAND_CMD_UNLOCK2 0x24

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#define NAND_CMD_UNLOCK2 0x24

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/* Extended commands for large page devices */

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/* Extended commands for large page devices */

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#define NAND_CMD_READSTART 0x30

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#define NAND_CMD_READSTART 0x30

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#define NAND_CMD_RNDOUTSTART 0xE0

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#define NAND_CMD_RNDOUTSTART 0xE0

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#define NAND_CMD_CACHEDPROG 0x15

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#define NAND_CMD_CACHEDPROG 0x15

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/* Extended commands for AG-AND device */

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/* Extended commands for AG-AND device */

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/*

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/*

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* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but

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* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but

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* there is no way to distinguish that from NAND_CMD_READ0

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* there is no way to distinguish that from NAND_CMD_READ0

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* until the remaining sequence of commands has been completed

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* until the remaining sequence of commands has been completed

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* so add a high order bit and mask it off in the command.

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* so add a high order bit and mask it off in the command.

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*/

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*/

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#define NAND_CMD_DEPLETE1 0x100

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#define NAND_CMD_DEPLETE1 0x100

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#define NAND_CMD_DEPLETE2 0x38

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#define NAND_CMD_DEPLETE2 0x38

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#define NAND_CMD_STATUS_MULTI 0x71

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#define NAND_CMD_STATUS_MULTI 0x71

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#define NAND_CMD_STATUS_ERROR 0x72

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#define NAND_CMD_STATUS_ERROR 0x72

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/* multi-bank error status (banks 0-3) */

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/* multi-bank error status (banks 0-3) */

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#define NAND_CMD_STATUS_ERROR0 0x73

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#define NAND_CMD_STATUS_ERROR0 0x73

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#define NAND_CMD_STATUS_ERROR1 0x74

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#define NAND_CMD_STATUS_ERROR1 0x74

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#define NAND_CMD_STATUS_ERROR2 0x75

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#define NAND_CMD_STATUS_ERROR2 0x75

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#define NAND_CMD_STATUS_ERROR3 0x76

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#define NAND_CMD_STATUS_ERROR3 0x76

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#define NAND_CMD_STATUS_RESET 0x7f

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#define NAND_CMD_STATUS_RESET 0x7f

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#define NAND_CMD_STATUS_CLEAR 0xff

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#define NAND_CMD_STATUS_CLEAR 0xff

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#define NAND_CMD_NONE -1

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#define NAND_CMD_NONE -1

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/* Status bits */

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/* Status bits */

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#define NAND_STATUS_FAIL 0x01

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#define NAND_STATUS_FAIL 0x01

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#define NAND_STATUS_FAIL_N1 0x02

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#define NAND_STATUS_FAIL_N1 0x02

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#define NAND_STATUS_TRUE_READY 0x20

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#define NAND_STATUS_TRUE_READY 0x20

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#define NAND_STATUS_READY 0x40

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#define NAND_STATUS_READY 0x40

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#define NAND_STATUS_WP 0x80

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#define NAND_STATUS_WP 0x80

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#define NAND_DATA_IFACE_CHECK_ONLY -1

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#define NAND_DATA_IFACE_CHECK_ONLY -1

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/*

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/*

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* Constants for ECC_MODES

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* Constants for ECC_MODES

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*/

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*/

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typedef enum {

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typedef enum {

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NAND_ECC_NONE,

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NAND_ECC_NONE,

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NAND_ECC_SOFT,

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NAND_ECC_SOFT,

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NAND_ECC_HW,

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NAND_ECC_HW,

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NAND_ECC_HW_SYNDROME,

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NAND_ECC_HW_SYNDROME,

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NAND_ECC_HW_OOB_FIRST,

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NAND_ECC_HW_OOB_FIRST,

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NAND_ECC_SOFT_BCH,

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NAND_ECC_SOFT_BCH,

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} nand_ecc_modes_t;

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} nand_ecc_modes_t;

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/*

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/*

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* Constants for Hardware ECC

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* Constants for Hardware ECC

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*/

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*/

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/* Reset Hardware ECC for read */

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/* Reset Hardware ECC for read */

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#define NAND_ECC_READ 0

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#define NAND_ECC_READ 0

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/* Reset Hardware ECC for write */

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/* Reset Hardware ECC for write */

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#define NAND_ECC_WRITE 1

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#define NAND_ECC_WRITE 1

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/* Enable Hardware ECC before syndrome is read back from flash */

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/* Enable Hardware ECC before syndrome is read back from flash */

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#define NAND_ECC_READSYN 2

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#define NAND_ECC_READSYN 2

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/*

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/*

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* Enable generic NAND 'page erased' check. This check is only done when

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* Enable generic NAND 'page erased' check. This check is only done when

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* ecc.correct() returns -EBADMSG.

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* ecc.correct() returns -EBADMSG.

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* Set this flag if your implementation does not fix bitflips in erased

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* Set this flag if your implementation does not fix bitflips in erased

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* pages and you want to rely on the default implementation.

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* pages and you want to rely on the default implementation.

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*/

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*/

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#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)

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#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)

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#define NAND_ECC_MAXIMIZE BIT(1)

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#define NAND_ECC_MAXIMIZE BIT(1)

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/*

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/*

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* If your controller already sends the required NAND commands when

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* If your controller already sends the required NAND commands when

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* reading or writing a page, then the framework is not supposed to

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* reading or writing a page, then the framework is not supposed to

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* send READ0 and SEQIN/PAGEPROG respectively.

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* send READ0 and SEQIN/PAGEPROG respectively.

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*/

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*/

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#define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)

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#define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)

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/* Bit mask for flags passed to do_nand_read_ecc */

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/* Bit mask for flags passed to do_nand_read_ecc */

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#define NAND_GET_DEVICE 0x80

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#define NAND_GET_DEVICE 0x80

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/*

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/*

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* Option constants for bizarre disfunctionality and real

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* Option constants for bizarre disfunctionality and real

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* features.

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* features.

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*/

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*/

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/* Buswidth is 16 bit */

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/* Buswidth is 16 bit */

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#define NAND_BUSWIDTH_16 0x00000002

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#define NAND_BUSWIDTH_16 0x00000002

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/* Device supports partial programming without padding */

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/* Device supports partial programming without padding */

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#define NAND_NO_PADDING 0x00000004

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#define NAND_NO_PADDING 0x00000004

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/* Chip has cache program function */

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/* Chip has cache program function */

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#define NAND_CACHEPRG 0x00000008

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#define NAND_CACHEPRG 0x00000008

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/* Chip has copy back function */

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/* Chip has copy back function */

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#define NAND_COPYBACK 0x00000010

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#define NAND_COPYBACK 0x00000010

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/*

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/*

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* Chip requires ready check on read (for auto-incremented sequential read).

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* Chip requires ready check on read (for auto-incremented sequential read).

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* True only for small page devices; large page devices do not support

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* True only for small page devices; large page devices do not support

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* autoincrement.

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* autoincrement.

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*/

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*/

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#define NAND_NEED_READRDY 0x00000100

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#define NAND_NEED_READRDY 0x00000100

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/* Chip does not allow subpage writes */

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/* Chip does not allow subpage writes */

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#define NAND_NO_SUBPAGE_WRITE 0x00000200

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#define NAND_NO_SUBPAGE_WRITE 0x00000200

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/* Device is one of 'new' xD cards that expose fake nand command set */

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/* Device is one of 'new' xD cards that expose fake nand command set */

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#define NAND_BROKEN_XD 0x00000400

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#define NAND_BROKEN_XD 0x00000400

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/* Device behaves just like nand, but is readonly */

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/* Device behaves just like nand, but is readonly */

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#define NAND_ROM 0x00000800

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#define NAND_ROM 0x00000800

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/* Device supports subpage reads */

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/* Device supports subpage reads */

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#define NAND_SUBPAGE_READ 0x00001000

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#define NAND_SUBPAGE_READ 0x00001000

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/*

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/*

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* Some MLC NANDs need data scrambling to limit bitflips caused by repeated

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* Some MLC NANDs need data scrambling to limit bitflips caused by repeated

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* patterns.

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* patterns.

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*/

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*/

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#define NAND_NEED_SCRAMBLING 0x00002000

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#define NAND_NEED_SCRAMBLING 0x00002000

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/* Device needs 3rd row address cycle */

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/* Device needs 3rd row address cycle */

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#define NAND_ROW_ADDR_3 0x00004000

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#define NAND_ROW_ADDR_3 0x00004000

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/* Options valid for Samsung large page devices */

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/* Options valid for Samsung large page devices */

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#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG

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#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG

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/* Macros to identify the above */

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/* Macros to identify the above */

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#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))

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#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))

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#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))

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#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))

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#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)

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#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)

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/* Non chip related options */

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/* Non chip related options */

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/* This option skips the bbt scan during initialization. */

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/* This option skips the bbt scan during initialization. */

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#define NAND_SKIP_BBTSCAN 0x00010000

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#define NAND_SKIP_BBTSCAN 0x00010000

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/*

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/*

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* This option is defined if the board driver allocates its own buffers

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* This option is defined if the board driver allocates its own buffers

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* (e.g. because it needs them DMA-coherent).

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* (e.g. because it needs them DMA-coherent).

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*/

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*/

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#define NAND_OWN_BUFFERS 0x00020000

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#define NAND_OWN_BUFFERS 0x00020000

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/* Chip may not exist, so silence any errors in scan */

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/* Chip may not exist, so silence any errors in scan */

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#define NAND_SCAN_SILENT_NODEV 0x00040000

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#define NAND_SCAN_SILENT_NODEV 0x00040000

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/*

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/*

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* Autodetect nand buswidth with readid/onfi.

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* Autodetect nand buswidth with readid/onfi.

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* This suppose the driver will configure the hardware in 8 bits mode

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* This suppose the driver will configure the hardware in 8 bits mode

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* when calling nand_scan_ident, and update its configuration

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* when calling nand_scan_ident, and update its configuration

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* before calling nand_scan_tail.

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* before calling nand_scan_tail.

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*/

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*/

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#define NAND_BUSWIDTH_AUTO 0x00080000

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#define NAND_BUSWIDTH_AUTO 0x00080000

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/*

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/*

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* This option could be defined by controller drivers to protect against

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* This option could be defined by controller drivers to protect against

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* kmap'ed, vmalloc'ed highmem buffers being passed from upper layers

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* kmap'ed, vmalloc'ed highmem buffers being passed from upper layers

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*/

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*/

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#define NAND_USE_BOUNCE_BUFFER 0x00100000

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#define NAND_USE_BOUNCE_BUFFER 0x00100000

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/* Options set by nand scan */

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/* Options set by nand scan */

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/* bbt has already been read */

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/* bbt has already been read */

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#define NAND_BBT_SCANNED 0x40000000

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#define NAND_BBT_SCANNED 0x40000000

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/* Nand scan has allocated controller struct */

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/* Nand scan has allocated controller struct */

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#define NAND_CONTROLLER_ALLOC 0x80000000

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#define NAND_CONTROLLER_ALLOC 0x80000000

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/* Cell info constants */

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/* Cell info constants */

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#define NAND_CI_CHIPNR_MSK 0x03

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#define NAND_CI_CHIPNR_MSK 0x03

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#define NAND_CI_CELLTYPE_MSK 0x0C

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#define NAND_CI_CELLTYPE_MSK 0x0C

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#define NAND_CI_CELLTYPE_SHIFT 2

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#define NAND_CI_CELLTYPE_SHIFT 2

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/* Keep gcc happy */

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/* Keep gcc happy */

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struct nand_chip;

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struct nand_chip;

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/* ONFI features */

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/* ONFI features */

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#define ONFI_FEATURE_16_BIT_BUS (1 << 0)

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#define ONFI_FEATURE_16_BIT_BUS (1 << 0)

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#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)

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#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)

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/* ONFI timing mode, used in both asynchronous and synchronous mode */

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/* ONFI timing mode, used in both asynchronous and synchronous mode */

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#define ONFI_TIMING_MODE_0 (1 << 0)

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#define ONFI_TIMING_MODE_0 (1 << 0)

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#define ONFI_TIMING_MODE_1 (1 << 1)

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#define ONFI_TIMING_MODE_1 (1 << 1)

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#define ONFI_TIMING_MODE_2 (1 << 2)

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#define ONFI_TIMING_MODE_2 (1 << 2)

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#define ONFI_TIMING_MODE_3 (1 << 3)

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#define ONFI_TIMING_MODE_3 (1 << 3)

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#define ONFI_TIMING_MODE_4 (1 << 4)

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#define ONFI_TIMING_MODE_4 (1 << 4)

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#define ONFI_TIMING_MODE_5 (1 << 5)

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#define ONFI_TIMING_MODE_5 (1 << 5)

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#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)

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#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)

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/* ONFI feature address */

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/* ONFI feature address */

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#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1

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#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1

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/* Vendor-specific feature address (Micron) */

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/* Vendor-specific feature address (Micron) */

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#define ONFI_FEATURE_ADDR_READ_RETRY 0x89

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#define ONFI_FEATURE_ADDR_READ_RETRY 0x89

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/* ONFI subfeature parameters length */

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/* ONFI subfeature parameters length */

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#define ONFI_SUBFEATURE_PARAM_LEN 4

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#define ONFI_SUBFEATURE_PARAM_LEN 4

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/* ONFI optional commands SET/GET FEATURES supported? */

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/* ONFI optional commands SET/GET FEATURES supported? */

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#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)

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#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)

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struct nand_onfi_params {

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struct nand_onfi_params {

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/* rev info and features block */

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/* rev info and features block */

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/* 'O' 'N' 'F' 'I' */

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/* 'O' 'N' 'F' 'I' */

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u8 sig[4];

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u8 sig[4];

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__le16 revision;

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__le16 revision;

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__le16 features;

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__le16 features;

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__le16 opt_cmd;

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__le16 opt_cmd;

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u8 reserved0[2];

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u8 reserved0[2];

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__le16 ext_param_page_length; /* since ONFI 2.1 */

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__le16 ext_param_page_length; /* since ONFI 2.1 */

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u8 num_of_param_pages; /* since ONFI 2.1 */

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u8 num_of_param_pages; /* since ONFI 2.1 */

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u8 reserved1[17];

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u8 reserved1[17];

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/* manufacturer information block */

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/* manufacturer information block */

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char manufacturer[12];

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char manufacturer[12];

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char model[20];

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char model[20];

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u8 jedec_id;

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u8 jedec_id;

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__le16 date_code;

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__le16 date_code;

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u8 reserved2[13];

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u8 reserved2[13];

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/* memory organization block */

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/* memory organization block */

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__le32 byte_per_page;

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__le32 byte_per_page;

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__le16 spare_bytes_per_page;

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__le16 spare_bytes_per_page;

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__le32 data_bytes_per_ppage;

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__le32 data_bytes_per_ppage;

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__le16 spare_bytes_per_ppage;

302

__le16 spare_bytes_per_ppage;

302

__le32 pages_per_block;

303

__le32 pages_per_block;

303

__le32 blocks_per_lun;

304

__le32 blocks_per_lun;

304

u8 lun_count;

305

u8 lun_count;

305

u8 addr_cycles;

306

u8 addr_cycles;

306

u8 bits_per_cell;

307

u8 bits_per_cell;

307

__le16 bb_per_lun;

308

__le16 bb_per_lun;

308

__le16 block_endurance;

309

__le16 block_endurance;

309

u8 guaranteed_good_blocks;

310

u8 guaranteed_good_blocks;

310

__le16 guaranteed_block_endurance;

311

__le16 guaranteed_block_endurance;

311

u8 programs_per_page;

312

u8 programs_per_page;

312

u8 ppage_attr;

313

u8 ppage_attr;

313

u8 ecc_bits;

314

u8 ecc_bits;

314

u8 interleaved_bits;

315

u8 interleaved_bits;

315

u8 interleaved_ops;

316

u8 interleaved_ops;

316

u8 reserved3[13];

317

u8 reserved3[13];

317

318

/* electrical parameter block */

319

/* electrical parameter block */

319

u8 io_pin_capacitance_max;

320

u8 io_pin_capacitance_max;

320

__le16 async_timing_mode;

321

__le16 async_timing_mode;

321

__le16 program_cache_timing_mode;

322

__le16 program_cache_timing_mode;

322

__le16 t_prog;

323

__le16 t_prog;

323

__le16 t_bers;

324

__le16 t_bers;

324

__le16 t_r;

325

__le16 t_r;

325

__le16 t_ccs;

326

__le16 t_ccs;

326

__le16 src_sync_timing_mode;

327

__le16 src_sync_timing_mode;

327

u8 src_ssync_features;

328

u8 src_ssync_features;

328

__le16 clk_pin_capacitance_typ;

329

__le16 clk_pin_capacitance_typ;

329

__le16 io_pin_capacitance_typ;

330

__le16 io_pin_capacitance_typ;

330

__le16 input_pin_capacitance_typ;

331

__le16 input_pin_capacitance_typ;

331

u8 input_pin_capacitance_max;

332

u8 input_pin_capacitance_max;

332

u8 driver_strength_support;

333

u8 driver_strength_support;

333

__le16 t_int_r;

334

__le16 t_int_r;

334

__le16 t_adl;

335

__le16 t_adl;

335

u8 reserved4[8];

336

u8 reserved4[8];

336

337

/* vendor */

338

/* vendor */

338

__le16 vendor_revision;

339

__le16 vendor_revision;

339

u8 vendor[88];

340

u8 vendor[88];

340

341

__le16 crc;

342

__le16 crc;

342

} __packed;

343

} __packed;

343

344

#define ONFI_CRC_BASE 0x4F4E

345

#define ONFI_CRC_BASE 0x4F4E

345

346

/* Extended ECC information Block Definition (since ONFI 2.1) */

347

/* Extended ECC information Block Definition (since ONFI 2.1) */

347

struct onfi_ext_ecc_info {

348

struct onfi_ext_ecc_info {

348

u8 ecc_bits;

349

u8 ecc_bits;

349

u8 codeword_size;

350

u8 codeword_size;

350

__le16 bb_per_lun;

351

__le16 bb_per_lun;

351

__le16 block_endurance;

352

__le16 block_endurance;

352

u8 reserved[2];

353

u8 reserved[2];

353

} __packed;

354

} __packed;

354

355

#define ONFI_SECTION_TYPE_0 0 /* Unused section. */

356

#define ONFI_SECTION_TYPE_0 0 /* Unused section. */

356

#define ONFI_SECTION_TYPE_1 1 /* for additional sections. */

357

#define ONFI_SECTION_TYPE_1 1 /* for additional sections. */

357

#define ONFI_SECTION_TYPE_2 2 /* for ECC information. */

358

#define ONFI_SECTION_TYPE_2 2 /* for ECC information. */

358

struct onfi_ext_section {

359

struct onfi_ext_section {

359

u8 type;

360

u8 type;

360

u8 length;

361

u8 length;

361

} __packed;

362

} __packed;

362

363

#define ONFI_EXT_SECTION_MAX 8

364

#define ONFI_EXT_SECTION_MAX 8

364

365

/* Extended Parameter Page Definition (since ONFI 2.1) */

366

/* Extended Parameter Page Definition (since ONFI 2.1) */

366

struct onfi_ext_param_page {

367

struct onfi_ext_param_page {

367

__le16 crc;

368

__le16 crc;

368

u8 sig[4]; /* 'E' 'P' 'P' 'S' */

369

u8 sig[4]; /* 'E' 'P' 'P' 'S' */

369

u8 reserved0[10];

370

u8 reserved0[10];

370

struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];

371

struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];

371

372

/*

373

/*

373

* The actual size of the Extended Parameter Page is in

374

* The actual size of the Extended Parameter Page is in

374

* @ext_param_page_length of nand_onfi_params{}.

375

* @ext_param_page_length of nand_onfi_params{}.

375

* The following are the variable length sections.

376

* The following are the variable length sections.

376

* So we do not add any fields below. Please see the ONFI spec.

377

* So we do not add any fields below. Please see the ONFI spec.

377

*/

378

*/

378

} __packed;

379

} __packed;

379

380

struct nand_onfi_vendor_micron {

381

struct nand_onfi_vendor_micron {

381

u8 two_plane_read;

382

u8 two_plane_read;

382

u8 read_cache;

383

u8 read_cache;

383

u8 read_unique_id;

384

u8 read_unique_id;

384

u8 dq_imped;

385

u8 dq_imped;

385

u8 dq_imped_num_settings;

386

u8 dq_imped_num_settings;

386

u8 dq_imped_feat_addr;

387

u8 dq_imped_feat_addr;

387

u8 rb_pulldown_strength;

388

u8 rb_pulldown_strength;

388

u8 rb_pulldown_strength_feat_addr;

389

u8 rb_pulldown_strength_feat_addr;

389

u8 rb_pulldown_strength_num_settings;

390

u8 rb_pulldown_strength_num_settings;

390

u8 otp_mode;

391

u8 otp_mode;

391

u8 otp_page_start;

392

u8 otp_page_start;

392

u8 otp_data_prot_addr;

393

u8 otp_data_prot_addr;

393

u8 otp_num_pages;

394

u8 otp_num_pages;

394

u8 otp_feat_addr;

395

u8 otp_feat_addr;

395

u8 read_retry_options;

396

u8 read_retry_options;

396

u8 reserved[72];

397

u8 reserved[72];

397

u8 param_revision;

398

u8 param_revision;

398

} __packed;

399

} __packed;

399

400

struct jedec_ecc_info {

401

struct jedec_ecc_info {

401

u8 ecc_bits;

402

u8 ecc_bits;

402

u8 codeword_size;

403

u8 codeword_size;

403

__le16 bb_per_lun;

404

__le16 bb_per_lun;

404

__le16 block_endurance;

405

__le16 block_endurance;

405

u8 reserved[2];

406

u8 reserved[2];

406

} __packed;

407

} __packed;

407

408

/* JEDEC features */

409

/* JEDEC features */

409

#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)

410

#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)

410

411

struct nand_jedec_params {

412

struct nand_jedec_params {

412

/* rev info and features block */

413

/* rev info and features block */

413

/* 'J' 'E' 'S' 'D' */

414

/* 'J' 'E' 'S' 'D' */

414

u8 sig[4];

415

u8 sig[4];

415

__le16 revision;

416

__le16 revision;

416

__le16 features;

417

__le16 features;

417

u8 opt_cmd[3];

418

u8 opt_cmd[3];

418

__le16 sec_cmd;

419

__le16 sec_cmd;

419

u8 num_of_param_pages;

420

u8 num_of_param_pages;

420

u8 reserved0[18];

421

u8 reserved0[18];

421

422

/* manufacturer information block */

423

/* manufacturer information block */

423

char manufacturer[12];

424

char manufacturer[12];

424

char model[20];

425

char model[20];

425

u8 jedec_id[6];

426

u8 jedec_id[6];

426

u8 reserved1[10];

427

u8 reserved1[10];

427

428

/* memory organization block */

429

/* memory organization block */

429

__le32 byte_per_page;

430

__le32 byte_per_page;

430

__le16 spare_bytes_per_page;

431

__le16 spare_bytes_per_page;

431

u8 reserved2[6];

432

u8 reserved2[6];

432

__le32 pages_per_block;

433

__le32 pages_per_block;

433

__le32 blocks_per_lun;

434

__le32 blocks_per_lun;

434

u8 lun_count;

435

u8 lun_count;

435

u8 addr_cycles;

436

u8 addr_cycles;

436

u8 bits_per_cell;

437

u8 bits_per_cell;

437

u8 programs_per_page;

438

u8 programs_per_page;

438

u8 multi_plane_addr;

439

u8 multi_plane_addr;

439

u8 multi_plane_op_attr;

440

u8 multi_plane_op_attr;

440

u8 reserved3[38];

441

u8 reserved3[38];

441

442

/* electrical parameter block */

443

/* electrical parameter block */

443

__le16 async_sdr_speed_grade;

444

__le16 async_sdr_speed_grade;

444

__le16 toggle_ddr_speed_grade;

445

__le16 toggle_ddr_speed_grade;

445

__le16 sync_ddr_speed_grade;

446

__le16 sync_ddr_speed_grade;

446

u8 async_sdr_features;

447

u8 async_sdr_features;

447

u8 toggle_ddr_features;

448

u8 toggle_ddr_features;

448

u8 sync_ddr_features;

449

u8 sync_ddr_features;

449

__le16 t_prog;

450

__le16 t_prog;

450

__le16 t_bers;

451

__le16 t_bers;

451

__le16 t_r;

452

__le16 t_r;

452

__le16 t_r_multi_plane;

453

__le16 t_r_multi_plane;

453

__le16 t_ccs;

454

__le16 t_ccs;

454

__le16 io_pin_capacitance_typ;

455

__le16 io_pin_capacitance_typ;

455

__le16 input_pin_capacitance_typ;

456

__le16 input_pin_capacitance_typ;

456

__le16 clk_pin_capacitance_typ;

457

__le16 clk_pin_capacitance_typ;

457

u8 driver_strength_support;

458

u8 driver_strength_support;

458

__le16 t_adl;

459

__le16 t_adl;

459

u8 reserved4[36];

460

u8 reserved4[36];

460

461

/* ECC and endurance block */

462

/* ECC and endurance block */

462

u8 guaranteed_good_blocks;

463

u8 guaranteed_good_blocks;

463

__le16 guaranteed_block_endurance;

464

__le16 guaranteed_block_endurance;

464

struct jedec_ecc_info ecc_info[4];

465

struct jedec_ecc_info ecc_info[4];

465

u8 reserved5[29];

466

u8 reserved5[29];

466

467

/* reserved */

468

/* reserved */

468

u8 reserved6[148];

469

u8 reserved6[148];

469

470

/* vendor */

471

/* vendor */

471

__le16 vendor_rev_num;

472

__le16 vendor_rev_num;

472

u8 reserved7[88];

473

u8 reserved7[88];

473

474

/* CRC for Parameter Page */

475

/* CRC for Parameter Page */

475

__le16 crc;

476

__le16 crc;

476

} __packed;

477

} __packed;

477

478

/**

479

/**

479

* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices

480

* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices

480

* @lock: protection lock

481

* @lock: protection lock

481

* @active: the mtd device which holds the controller currently

482

* @active: the mtd device which holds the controller currently

482

* @wq: wait queue to sleep on if a NAND operation is in

483

* @wq: wait queue to sleep on if a NAND operation is in

483

* progress used instead of the per chip wait queue

484

* progress used instead of the per chip wait queue

484

* when a hw controller is available.

485

* when a hw controller is available.

485

*/

486

*/

486

struct nand_hw_control {

487

struct nand_hw_control {

487

spinlock_t lock;

488

spinlock_t lock;

488

struct nand_chip *active;

489

struct nand_chip *active;

489

};

490

};

490

491

/**

492

/**

492

* struct nand_ecc_step_info - ECC step information of ECC engine

493

* struct nand_ecc_step_info - ECC step information of ECC engine

493

* @stepsize: data bytes per ECC step

494

* @stepsize: data bytes per ECC step

494

* @strengths: array of supported strengths

495

* @strengths: array of supported strengths

495

* @nstrengths: number of supported strengths

496

* @nstrengths: number of supported strengths

496

*/

497

*/

497

struct nand_ecc_step_info {

498

struct nand_ecc_step_info {

498

int stepsize;

499

int stepsize;

499

const int *strengths;

500

const int *strengths;

500

int nstrengths;

501

int nstrengths;

501

};

502

};

502

503

/**

504

/**

504

* struct nand_ecc_caps - capability of ECC engine

505

* struct nand_ecc_caps - capability of ECC engine

505

* @stepinfos: array of ECC step information

506

* @stepinfos: array of ECC step information

506

* @nstepinfos: number of ECC step information

507

* @nstepinfos: number of ECC step information

507

* @calc_ecc_bytes: driver's hook to calculate ECC bytes per step

508

* @calc_ecc_bytes: driver's hook to calculate ECC bytes per step

508

*/

509

*/

509

struct nand_ecc_caps {

510

struct nand_ecc_caps {

510

const struct nand_ecc_step_info *stepinfos;

511

const struct nand_ecc_step_info *stepinfos;

511

int nstepinfos;

512

int nstepinfos;

512

int (*calc_ecc_bytes)(int step_size, int strength);

513

int (*calc_ecc_bytes)(int step_size, int strength);

513

};

514

};

514

515

/* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */

516

/* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */

516

#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \

517

#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \

517

static const int __name##_strengths[] = { __VA_ARGS__ }; \

518

static const int __name##_strengths[] = { __VA_ARGS__ }; \

518

static const struct nand_ecc_step_info __name##_stepinfo = { \

519

static const struct nand_ecc_step_info __name##_stepinfo = { \

519

.stepsize = __step, \

520

.stepsize = __step, \

520

.strengths = __name##_strengths, \

521

.strengths = __name##_strengths, \

521

.nstrengths = ARRAY_SIZE(__name##_strengths), \

522

.nstrengths = ARRAY_SIZE(__name##_strengths), \

522

}; \

523

}; \

523

static const struct nand_ecc_caps __name = { \

524

static const struct nand_ecc_caps __name = { \

524

.stepinfos = &__name##_stepinfo, \

525

.stepinfos = &__name##_stepinfo, \

525

.nstepinfos = 1, \

526

.nstepinfos = 1, \

526

.calc_ecc_bytes = __calc, \

527

.calc_ecc_bytes = __calc, \

527

}

528

}

528

529

/**

530

/**

530

* struct nand_ecc_ctrl - Control structure for ECC

531

* struct nand_ecc_ctrl - Control structure for ECC

531

* @mode: ECC mode

532

* @mode: ECC mode

532

* @steps: number of ECC steps per page

533

* @steps: number of ECC steps per page

533

* @size: data bytes per ECC step

534

* @size: data bytes per ECC step

534

* @bytes: ECC bytes per step

535

* @bytes: ECC bytes per step

535

* @strength: max number of correctible bits per ECC step

536

* @strength: max number of correctible bits per ECC step

536

* @total: total number of ECC bytes per page

537

* @total: total number of ECC bytes per page

537

* @prepad: padding information for syndrome based ECC generators

538

* @prepad: padding information for syndrome based ECC generators

538

* @postpad: padding information for syndrome based ECC generators

539

* @postpad: padding information for syndrome based ECC generators

539

* @options: ECC specific options (see NAND_ECC_XXX flags defined above)

540

* @options: ECC specific options (see NAND_ECC_XXX flags defined above)

540

* @layout: ECC layout control struct pointer

541

* @layout: ECC layout control struct pointer

541

* @priv: pointer to private ECC control data

542

* @priv: pointer to private ECC control data

542

* @hwctl: function to control hardware ECC generator. Must only

543

* @hwctl: function to control hardware ECC generator. Must only

543

* be provided if an hardware ECC is available

544

* be provided if an hardware ECC is available

544

* @calculate: function for ECC calculation or readback from ECC hardware

545

* @calculate: function for ECC calculation or readback from ECC hardware

545

* @correct: function for ECC correction, matching to ECC generator (sw/hw).

546

* @correct: function for ECC correction, matching to ECC generator (sw/hw).

546

* Should return a positive number representing the number of

547

* Should return a positive number representing the number of

547

* corrected bitflips, -EBADMSG if the number of bitflips exceed

548

* corrected bitflips, -EBADMSG if the number of bitflips exceed

548

* ECC strength, or any other error code if the error is not

549

* ECC strength, or any other error code if the error is not

549

* directly related to correction.

550

* directly related to correction.

550

* If -EBADMSG is returned the input buffers should be left

551

* If -EBADMSG is returned the input buffers should be left

551

* untouched.

552

* untouched.

552

* @read_page_raw: function to read a raw page without ECC. This function

553

* @read_page_raw: function to read a raw page without ECC. This function

553

* should hide the specific layout used by the ECC

554

* should hide the specific layout used by the ECC

554

* controller and always return contiguous in-band and

555

* controller and always return contiguous in-band and

555

* out-of-band data even if they're not stored

556

* out-of-band data even if they're not stored

556

* contiguously on the NAND chip (e.g.

557

* contiguously on the NAND chip (e.g.

557

* NAND_ECC_HW_SYNDROME interleaves in-band and

558

* NAND_ECC_HW_SYNDROME interleaves in-band and

558

* out-of-band data).

559

* out-of-band data).

559

* @write_page_raw: function to write a raw page without ECC. This function

560

* @write_page_raw: function to write a raw page without ECC. This function

560

* should hide the specific layout used by the ECC

561

* should hide the specific layout used by the ECC

561

* controller and consider the passed data as contiguous

562

* controller and consider the passed data as contiguous

562

* in-band and out-of-band data. ECC controller is

563

* in-band and out-of-band data. ECC controller is

563

* responsible for doing the appropriate transformations

564

* responsible for doing the appropriate transformations

564

* to adapt to its specific layout (e.g.

565

* to adapt to its specific layout (e.g.

565

* NAND_ECC_HW_SYNDROME interleaves in-band and

566

* NAND_ECC_HW_SYNDROME interleaves in-band and

566

* out-of-band data).

567

* out-of-band data).

567

* @read_page: function to read a page according to the ECC generator

568

* @read_page: function to read a page according to the ECC generator

568

* requirements; returns maximum number of bitflips corrected in

569

* requirements; returns maximum number of bitflips corrected in

569

* any single ECC step, 0 if bitflips uncorrectable, -EIO hw error

570

* any single ECC step, 0 if bitflips uncorrectable, -EIO hw error

570

* @read_subpage: function to read parts of the page covered by ECC;

571

* @read_subpage: function to read parts of the page covered by ECC;

571

* returns same as read_page()

572

* returns same as read_page()

572

* @write_subpage: function to write parts of the page covered by ECC.

573

* @write_subpage: function to write parts of the page covered by ECC.

573

* @write_page: function to write a page according to the ECC generator

574

* @write_page: function to write a page according to the ECC generator

574

* requirements.

575

* requirements.

575

* @write_oob_raw: function to write chip OOB data without ECC

576

* @write_oob_raw: function to write chip OOB data without ECC

576

* @read_oob_raw: function to read chip OOB data without ECC

577

* @read_oob_raw: function to read chip OOB data without ECC

577

* @read_oob: function to read chip OOB data

578

* @read_oob: function to read chip OOB data

578

* @write_oob: function to write chip OOB data

579

* @write_oob: function to write chip OOB data

579

*/

580

*/

580

struct nand_ecc_ctrl {

581

struct nand_ecc_ctrl {

581

nand_ecc_modes_t mode;

582

nand_ecc_modes_t mode;

582

int steps;

583

int steps;

583

int size;

584

int size;

584

int bytes;

585

int bytes;

585

int total;

586

int total;

586

int strength;

587

int strength;

587

int prepad;

588

int prepad;

588

int postpad;

589

int postpad;

589

unsigned int options;

590

unsigned int options;

590

struct nand_ecclayout *layout;

591

struct nand_ecclayout *layout;

591

void *priv;

592

void *priv;

592

void (*hwctl)(struct mtd_info *mtd, int mode);

593

void (*hwctl)(struct mtd_info *mtd, int mode);

593

int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,

594

int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,

594

uint8_t *ecc_code);

595

uint8_t *ecc_code);

595

int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,

596

int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,

596

uint8_t *calc_ecc);

597

uint8_t *calc_ecc);

597

int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,

598

int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,

598

uint8_t *buf, int oob_required, int page);

599

uint8_t *buf, int oob_required, int page);

599

int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,

600

int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,

600

const uint8_t *buf, int oob_required, int page);

601

const uint8_t *buf, int oob_required, int page);

601

int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,

602

int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,

602

uint8_t *buf, int oob_required, int page);

603

uint8_t *buf, int oob_required, int page);

603

int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,

604

int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,

604

uint32_t offs, uint32_t len, uint8_t *buf, int page);

605

uint32_t offs, uint32_t len, uint8_t *buf, int page);

605

int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,

606

int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,

606

uint32_t offset, uint32_t data_len,

607

uint32_t offset, uint32_t data_len,

607

const uint8_t *data_buf, int oob_required, int page);

608

const uint8_t *data_buf, int oob_required, int page);

608

int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,

609

int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,

609

const uint8_t *buf, int oob_required, int page);

610

const uint8_t *buf, int oob_required, int page);

610

int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,

611

int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,

611

int page);

612

int page);

612

int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,

613

int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,

613

int page);

614

int page);

614

int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);

615

int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);

615

int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,

616

int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,

616

int page);

617

int page);

617

};

618

};

618

619

static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)

620

static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)

620

{

621

{

621

return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);

622

return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);

622

}

623

}

623

624

/**

625

/**

625

* struct nand_buffers - buffer structure for read/write

626

* struct nand_buffers - buffer structure for read/write

626

* @ecccalc: buffer pointer for calculated ECC, size is oobsize.

627

* @ecccalc: buffer pointer for calculated ECC, size is oobsize.

627

* @ecccode: buffer pointer for ECC read from flash, size is oobsize.

628

* @ecccode: buffer pointer for ECC read from flash, size is oobsize.

628

* @databuf: buffer pointer for data, size is (page size + oobsize).

629

* @databuf: buffer pointer for data, size is (page size + oobsize).

629

*

630

*

630

* Do not change the order of buffers. databuf and oobrbuf must be in

631

* Do not change the order of buffers. databuf and oobrbuf must be in

631

* consecutive order.

632

* consecutive order.

632

*/

633

*/

633

struct nand_buffers {

634

struct nand_buffers {

634

uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];

635

uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];

635

uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];

636

uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];

636

uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,

637

uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,

637

ARCH_DMA_MINALIGN)];

638

ARCH_DMA_MINALIGN)];

638

};

639

};

639

640

/**

641

/**

641

* struct nand_sdr_timings - SDR NAND chip timings

642

* struct nand_sdr_timings - SDR NAND chip timings

642

*

643

*

643

* This struct defines the timing requirements of a SDR NAND chip.

644

* This struct defines the timing requirements of a SDR NAND chip.

644

* These information can be found in every NAND datasheets and the timings

645

* These information can be found in every NAND datasheets and the timings

645

* meaning are described in the ONFI specifications:

646

* meaning are described in the ONFI specifications:

646

* www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing

647

* www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing

647

* Parameters)

648

* Parameters)

648

*

649

*

649

* All these timings are expressed in picoseconds.

650

* All these timings are expressed in picoseconds.

650

*

651

*

651

* @tBERS_max: Block erase time

652

* @tBERS_max: Block erase time

652

* @tCCS_min: Change column setup time

653

* @tCCS_min: Change column setup time

653

* @tPROG_max: Page program time

654

* @tPROG_max: Page program time

654

* @tR_max: Page read time

655

* @tR_max: Page read time

655

* @tALH_min: ALE hold time

656

* @tALH_min: ALE hold time

656

* @tADL_min: ALE to data loading time

657

* @tADL_min: ALE to data loading time

657

* @tALS_min: ALE setup time

658

* @tALS_min: ALE setup time

658

* @tAR_min: ALE to RE# delay

659

* @tAR_min: ALE to RE# delay

659

* @tCEA_max: CE# access time

660

* @tCEA_max: CE# access time

660

* @tCEH_min: CE# high hold time

661

* @tCEH_min: CE# high hold time

661

* @tCH_min: CE# hold time

662

* @tCH_min: CE# hold time

662

* @tCHZ_max: CE# high to output hi-Z

663

* @tCHZ_max: CE# high to output hi-Z

663

* @tCLH_min: CLE hold time

664

* @tCLH_min: CLE hold time

664

* @tCLR_min: CLE to RE# delay

665

* @tCLR_min: CLE to RE# delay

665

* @tCLS_min: CLE setup time

666

* @tCLS_min: CLE setup time

666

* @tCOH_min: CE# high to output hold

667

* @tCOH_min: CE# high to output hold

667

* @tCS_min: CE# setup time

668

* @tCS_min: CE# setup time

668

* @tDH_min: Data hold time

669

* @tDH_min: Data hold time

669

* @tDS_min: Data setup time

670

* @tDS_min: Data setup time

670

* @tFEAT_max: Busy time for Set Features and Get Features

671

* @tFEAT_max: Busy time for Set Features and Get Features

671

* @tIR_min: Output hi-Z to RE# low

672

* @tIR_min: Output hi-Z to RE# low

672

* @tITC_max: Interface and Timing Mode Change time

673

* @tITC_max: Interface and Timing Mode Change time

673

* @tRC_min: RE# cycle time

674

* @tRC_min: RE# cycle time

674

* @tREA_max: RE# access time

675

* @tREA_max: RE# access time

675

* @tREH_min: RE# high hold time

676

* @tREH_min: RE# high hold time

676

* @tRHOH_min: RE# high to output hold

677

* @tRHOH_min: RE# high to output hold

677

* @tRHW_min: RE# high to WE# low

678

* @tRHW_min: RE# high to WE# low

678

* @tRHZ_max: RE# high to output hi-Z

679

* @tRHZ_max: RE# high to output hi-Z

679

* @tRLOH_min: RE# low to output hold

680

* @tRLOH_min: RE# low to output hold

680

* @tRP_min: RE# pulse width

681

* @tRP_min: RE# pulse width

681

* @tRR_min: Ready to RE# low (data only)

682

* @tRR_min: Ready to RE# low (data only)

682

* @tRST_max: Device reset time, measured from the falling edge of R/B# to the

683

* @tRST_max: Device reset time, measured from the falling edge of R/B# to the

683

* rising edge of R/B#.

684

* rising edge of R/B#.

684

* @tWB_max: WE# high to SR[6] low

685

* @tWB_max: WE# high to SR[6] low

685

* @tWC_min: WE# cycle time

686

* @tWC_min: WE# cycle time

686

* @tWH_min: WE# high hold time

687

* @tWH_min: WE# high hold time

687

* @tWHR_min: WE# high to RE# low

688

* @tWHR_min: WE# high to RE# low

688

* @tWP_min: WE# pulse width

689

* @tWP_min: WE# pulse width

689

* @tWW_min: WP# transition to WE# low

690

* @tWW_min: WP# transition to WE# low

690

*/

691

*/

691

struct nand_sdr_timings {

692

struct nand_sdr_timings {

692

u64 tBERS_max;

693

u64 tBERS_max;

693

u32 tCCS_min;

694

u32 tCCS_min;

694

u64 tPROG_max;

695

u64 tPROG_max;

695

u64 tR_max;

696

u64 tR_max;

696

u32 tALH_min;

697

u32 tALH_min;

697

u32 tADL_min;

698

u32 tADL_min;

698

u32 tALS_min;

699

u32 tALS_min;

699

u32 tAR_min;

700

u32 tAR_min;

700

u32 tCEA_max;

701

u32 tCEA_max;

701

u32 tCEH_min;

702

u32 tCEH_min;

702

u32 tCH_min;

703

u32 tCH_min;

703

u32 tCHZ_max;

704

u32 tCHZ_max;

704

u32 tCLH_min;

705

u32 tCLH_min;

705

u32 tCLR_min;

706

u32 tCLR_min;

706

u32 tCLS_min;

707

u32 tCLS_min;

707

u32 tCOH_min;

708

u32 tCOH_min;

708

u32 tCS_min;

709

u32 tCS_min;

709

u32 tDH_min;

710

u32 tDH_min;

710

u32 tDS_min;

711

u32 tDS_min;

711

u32 tFEAT_max;

712

u32 tFEAT_max;

712

u32 tIR_min;

713

u32 tIR_min;

713

u32 tITC_max;

714

u32 tITC_max;

714

u32 tRC_min;

715

u32 tRC_min;

715

u32 tREA_max;

716

u32 tREA_max;

716

u32 tREH_min;

717

u32 tREH_min;

717

u32 tRHOH_min;

718

u32 tRHOH_min;

718

u32 tRHW_min;

719

u32 tRHW_min;

719

u32 tRHZ_max;

720

u32 tRHZ_max;

720

u32 tRLOH_min;

721

u32 tRLOH_min;

721

u32 tRP_min;

722

u32 tRP_min;

722

u32 tRR_min;

723

u32 tRR_min;

723

u64 tRST_max;

724

u64 tRST_max;

724

u32 tWB_max;

725

u32 tWB_max;

725

u32 tWC_min;

726

u32 tWC_min;

726

u32 tWH_min;

727

u32 tWH_min;

727

u32 tWHR_min;

728

u32 tWHR_min;

728

u32 tWP_min;

729

u32 tWP_min;

729

u32 tWW_min;

730

u32 tWW_min;

730

};

731

};

731

732

/**

733

/**

733

* enum nand_data_interface_type - NAND interface timing type

734

* enum nand_data_interface_type - NAND interface timing type

734

* @NAND_SDR_IFACE: Single Data Rate interface

735

* @NAND_SDR_IFACE: Single Data Rate interface

735

*/

736

*/

736

enum nand_data_interface_type {

737

enum nand_data_interface_type {

737

NAND_SDR_IFACE,

738

NAND_SDR_IFACE,

738

};

739

};

739

740

/**

741

/**

741

* struct nand_data_interface - NAND interface timing

742

* struct nand_data_interface - NAND interface timing

742

* @type: type of the timing

743

* @type: type of the timing

743

* @timings: The timing, type according to @type

744

* @timings: The timing, type according to @type

744

*/

745

*/

745

struct nand_data_interface {

746

struct nand_data_interface {

746

enum nand_data_interface_type type;

747

enum nand_data_interface_type type;

747

union {

748

union {

748

struct nand_sdr_timings sdr;

749

struct nand_sdr_timings sdr;

749

} timings;

750

} timings;

750

};

751

};

751

752

/**

753

/**

753

* nand_get_sdr_timings - get SDR timing from data interface

754

* nand_get_sdr_timings - get SDR timing from data interface

754

* @conf: The data interface

755

* @conf: The data interface

755

*/

756

*/

756

static inline const struct nand_sdr_timings *

757

static inline const struct nand_sdr_timings *

757

nand_get_sdr_timings(const struct nand_data_interface *conf)

758

nand_get_sdr_timings(const struct nand_data_interface *conf)

758

{

759

{

759

if (conf->type != NAND_SDR_IFACE)

760

if (conf->type != NAND_SDR_IFACE)

760

return ERR_PTR(-EINVAL);

761

return ERR_PTR(-EINVAL);

761

762

return &conf->timings.sdr;

763

return &conf->timings.sdr;

763

}

764

}

764

765

/**

766

/**

766

* struct nand_chip - NAND Private Flash Chip Data

767

* struct nand_chip - NAND Private Flash Chip Data

767

* @mtd: MTD device registered to the MTD framework

768

* @mtd: MTD device registered to the MTD framework

768

* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the

769

* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the

769

* flash device

770

* flash device

770

* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the

771

* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the

771

* flash device.

772

* flash device.

772

* @flash_node: [BOARDSPECIFIC] device node describing this instance

773

* @flash_node: [BOARDSPECIFIC] device node describing this instance

773

* @read_byte: [REPLACEABLE] read one byte from the chip

774

* @read_byte: [REPLACEABLE] read one byte from the chip

774

* @read_word: [REPLACEABLE] read one word from the chip

775

* @read_word: [REPLACEABLE] read one word from the chip

775

* @write_byte: [REPLACEABLE] write a single byte to the chip on the

776

* @write_byte: [REPLACEABLE] write a single byte to the chip on the

776

* low 8 I/O lines

777

* low 8 I/O lines

777

* @write_buf: [REPLACEABLE] write data from the buffer to the chip

778

* @write_buf: [REPLACEABLE] write data from the buffer to the chip

778

* @read_buf: [REPLACEABLE] read data from the chip into the buffer

779

* @read_buf: [REPLACEABLE] read data from the chip into the buffer

779

* @select_chip: [REPLACEABLE] select chip nr

780

* @select_chip: [REPLACEABLE] select chip nr

780

* @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers

781

* @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers

781

* @block_markbad: [REPLACEABLE] mark a block bad

782

* @block_markbad: [REPLACEABLE] mark a block bad

782

* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling

783

* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling

783

* ALE/CLE/nCE. Also used to write command and address

784

* ALE/CLE/nCE. Also used to write command and address

784

* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing

785

* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing

785

* device ready/busy line. If set to NULL no access to

786

* device ready/busy line. If set to NULL no access to

786

* ready/busy is available and the ready/busy information

787

* ready/busy is available and the ready/busy information

787

* is read from the chip status register.

788

* is read from the chip status register.

788

* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing

789

* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing

789

* commands to the chip.

790

* commands to the chip.

790

* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on

791

* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on

791

* ready.

792

* ready.

792

* @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for

793

* @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for

793

* setting the read-retry mode. Mostly needed for MLC NAND.

794

* setting the read-retry mode. Mostly needed for MLC NAND.

794

* @ecc: [BOARDSPECIFIC] ECC control structure

795

* @ecc: [BOARDSPECIFIC] ECC control structure

795

* @buffers: buffer structure for read/write

796

* @buffers: buffer structure for read/write

796

* @buf_align: minimum buffer alignment required by a platform

797

* @buf_align: minimum buffer alignment required by a platform

797

* @hwcontrol: platform-specific hardware control structure

798

* @hwcontrol: platform-specific hardware control structure

798

* @erase: [REPLACEABLE] erase function

799

* @erase: [REPLACEABLE] erase function

799

* @scan_bbt: [REPLACEABLE] function to scan bad block table

800

* @scan_bbt: [REPLACEABLE] function to scan bad block table

800

* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring

801

* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring

801

* data from array to read regs (tR).

802

* data from array to read regs (tR).

802

* @state: [INTERN] the current state of the NAND device

803

* @state: [INTERN] the current state of the NAND device

803

* @oob_poi: "poison value buffer," used for laying out OOB data

804

* @oob_poi: "poison value buffer," used for laying out OOB data

804

* before writing

805

* before writing

805

* @page_shift: [INTERN] number of address bits in a page (column

806

* @page_shift: [INTERN] number of address bits in a page (column

806

* address bits).

807

* address bits).

807

* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock

808

* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock

808

* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry

809

* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry

809

* @chip_shift: [INTERN] number of address bits in one chip

810

* @chip_shift: [INTERN] number of address bits in one chip

810

* @options: [BOARDSPECIFIC] various chip options. They can partly

811

* @options: [BOARDSPECIFIC] various chip options. They can partly

811

* be set to inform nand_scan about special functionality.

812

* be set to inform nand_scan about special functionality.

812

* See the defines for further explanation.

813

* See the defines for further explanation.

813

* @bbt_options: [INTERN] bad block specific options. All options used

814

* @bbt_options: [INTERN] bad block specific options. All options used

814

* here must come from bbm.h. By default, these options

815

* here must come from bbm.h. By default, these options

815

* will be copied to the appropriate nand_bbt_descr's.

816

* will be copied to the appropriate nand_bbt_descr's.

816

* @badblockpos: [INTERN] position of the bad block marker in the oob

817

* @badblockpos: [INTERN] position of the bad block marker in the oob

817

* area.

818

* area.

818

* @badblockbits: [INTERN] minimum number of set bits in a good block's

819

* @badblockbits: [INTERN] minimum number of set bits in a good block's

819

* bad block marker position; i.e., BBM == 11110111b is

820

* bad block marker position; i.e., BBM == 11110111b is

820

* not bad when badblockbits == 7

821

* not bad when badblockbits == 7

821

* @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.

822

* @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.

822

* @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.

823

* @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.

823

* Minimum amount of bit errors per @ecc_step_ds guaranteed

824

* Minimum amount of bit errors per @ecc_step_ds guaranteed

824

* to be correctable. If unknown, set to zero.

825

* to be correctable. If unknown, set to zero.

825

* @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,

826

* @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,

826

* also from the datasheet. It is the recommended ECC step

827

* also from the datasheet. It is the recommended ECC step

827

* size, if known; if unknown, set to zero.

828

* size, if known; if unknown, set to zero.

828

* @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is

829

* @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is

829

* set to the actually used ONFI mode if the chip is

830

* set to the actually used ONFI mode if the chip is

830

* ONFI compliant or deduced from the datasheet if

831

* ONFI compliant or deduced from the datasheet if

831

* the NAND chip is not ONFI compliant.

832

* the NAND chip is not ONFI compliant.

832

* @numchips: [INTERN] number of physical chips

833

* @numchips: [INTERN] number of physical chips

833

* @chipsize: [INTERN] the size of one chip for multichip arrays

834

* @chipsize: [INTERN] the size of one chip for multichip arrays

834

* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1

835

* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1

835

* @pagebuf: [INTERN] holds the pagenumber which is currently in

836

* @pagebuf: [INTERN] holds the pagenumber which is currently in

836

* data_buf.

837

* data_buf.

837

* @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is

838

* @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is

838

* currently in data_buf.

839

* currently in data_buf.

839

* @subpagesize: [INTERN] holds the subpagesize

840

* @subpagesize: [INTERN] holds the subpagesize

840

* @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),

841

* @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),

841

* non 0 if ONFI supported.

842

* non 0 if ONFI supported.

842

* @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),

843

* @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),

843

* non 0 if JEDEC supported.

844

* non 0 if JEDEC supported.

844

* @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is

845

* @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is

845

* supported, 0 otherwise.

846

* supported, 0 otherwise.

846

* @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is

847

* @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is

847

* supported, 0 otherwise.

848

* supported, 0 otherwise.

848

* @read_retries: [INTERN] the number of read retry modes supported

849

* @read_retries: [INTERN] the number of read retry modes supported

849

* @onfi_set_features: [REPLACEABLE] set the features for ONFI nand

850

* @onfi_set_features: [REPLACEABLE] set the features for ONFI nand

850

* @onfi_get_features: [REPLACEABLE] get the features for ONFI nand

851

* @onfi_get_features: [REPLACEABLE] get the features for ONFI nand

851

* @setup_data_interface: [OPTIONAL] setup the data interface and timing. If

852

* @setup_data_interface: [OPTIONAL] setup the data interface and timing. If

852

* chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this

853

* chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this

853

* means the configuration should not be applied but

854

* means the configuration should not be applied but

854

* only checked.

855

* only checked.

855

* @bbt: [INTERN] bad block table pointer

856

* @bbt: [INTERN] bad block table pointer

856

* @bbt_td: [REPLACEABLE] bad block table descriptor for flash

857

* @bbt_td: [REPLACEABLE] bad block table descriptor for flash

857

* lookup.

858

* lookup.

858

* @bbt_md: [REPLACEABLE] bad block table mirror descriptor

859

* @bbt_md: [REPLACEABLE] bad block table mirror descriptor

859

* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial

860

* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial

860

* bad block scan.

861

* bad block scan.

861

* @controller: [REPLACEABLE] a pointer to a hardware controller

862

* @controller: [REPLACEABLE] a pointer to a hardware controller

862

* structure which is shared among multiple independent

863

* structure which is shared among multiple independent

863

* devices.

864

* devices.

864

* @priv: [OPTIONAL] pointer to private chip data

865

* @priv: [OPTIONAL] pointer to private chip data

865

* @write_page: [REPLACEABLE] High-level page write function

866

* @write_page: [REPLACEABLE] High-level page write function

866

*/

867

*/

867

868

struct nand_chip {

869

struct nand_chip {

869

struct mtd_info mtd;

870

struct mtd_info mtd;

870

void __iomem *IO_ADDR_R;

871

void __iomem *IO_ADDR_R;

871

void __iomem *IO_ADDR_W;

872

void __iomem *IO_ADDR_W;

872

873

int flash_node;

874

int flash_node;

874

875

uint8_t (*read_byte)(struct mtd_info *mtd);

876

uint8_t (*read_byte)(struct mtd_info *mtd);

876

u16 (*read_word)(struct mtd_info *mtd);

877

u16 (*read_word)(struct mtd_info *mtd);

877

void (*write_byte)(struct mtd_info *mtd, uint8_t byte);

878

void (*write_byte)(struct mtd_info *mtd, uint8_t byte);

878

void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);

879

void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);

879

void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);

880

void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);

880

void (*select_chip)(struct mtd_info *mtd, int chip);

881

void (*select_chip)(struct mtd_info *mtd, int chip);

881

int (*block_bad)(struct mtd_info *mtd, loff_t ofs);

882

int (*block_bad)(struct mtd_info *mtd, loff_t ofs);

882

int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);

883

int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);

883

void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);

884

void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);

884

int (*dev_ready)(struct mtd_info *mtd);

885

int (*dev_ready)(struct mtd_info *mtd);

885

void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,

886

void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,

886

int page_addr);

887

int page_addr);

887

int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);

888

int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);

888

int (*erase)(struct mtd_info *mtd, int page);

889

int (*erase)(struct mtd_info *mtd, int page);

889

int (*scan_bbt)(struct mtd_info *mtd);

890

int (*scan_bbt)(struct mtd_info *mtd);

890

int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,

891

int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,

891

uint32_t offset, int data_len, const uint8_t *buf,

892

uint32_t offset, int data_len, const uint8_t *buf,

892

int oob_required, int page, int raw);

893

int oob_required, int page, int raw);

893

int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,

894

int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,

894

int feature_addr, uint8_t *subfeature_para);

895

int feature_addr, uint8_t *subfeature_para);

895

int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,

896

int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,

896

int feature_addr, uint8_t *subfeature_para);

897

int feature_addr, uint8_t *subfeature_para);

897

int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);

898

int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);

898

int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,

899

int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,

899

const struct nand_data_interface *conf);

900

const struct nand_data_interface *conf);

900

901

902

int chip_delay;

903

int chip_delay;

903

unsigned int options;

904

unsigned int options;

904

unsigned int bbt_options;

905

unsigned int bbt_options;

905

906

int page_shift;

907

int page_shift;

907

int phys_erase_shift;

908

int phys_erase_shift;

908

int bbt_erase_shift;

909

int bbt_erase_shift;

909

int chip_shift;

910

int chip_shift;

910

int numchips;

911

int numchips;

911

uint64_t chipsize;

912

uint64_t chipsize;

912

int pagemask;

913

int pagemask;

913

int pagebuf;

914

int pagebuf;

914

unsigned int pagebuf_bitflips;

915

unsigned int pagebuf_bitflips;

915

int subpagesize;

916

int subpagesize;

916

uint8_t bits_per_cell;

917

uint8_t bits_per_cell;

917

uint16_t ecc_strength_ds;

918

uint16_t ecc_strength_ds;

918

uint16_t ecc_step_ds;

919

uint16_t ecc_step_ds;

919

int onfi_timing_mode_default;

920

int onfi_timing_mode_default;

920

int badblockpos;

921

int badblockpos;

921

int badblockbits;

922

int badblockbits;

922

923

int onfi_version;

924

int onfi_version;

924

int jedec_version;

925

int jedec_version;

925

struct nand_onfi_params onfi_params;

926

struct nand_onfi_params onfi_params;

926

struct nand_jedec_params jedec_params;

927

struct nand_jedec_params jedec_params;

927

928

struct nand_data_interface *data_interface;

929

struct nand_data_interface *data_interface;

929

930

int read_retries;

931

int read_retries;

931

932

flstate_t state;

933

flstate_t state;

933

934

uint8_t *oob_poi;

935

uint8_t *oob_poi;

935

struct nand_hw_control *controller;

936

struct nand_hw_control *controller;

936

struct nand_ecclayout *ecclayout;

937

struct nand_ecclayout *ecclayout;

937

938

struct nand_ecc_ctrl ecc;

939

struct nand_ecc_ctrl ecc;

939

struct nand_buffers *buffers;

940

struct nand_buffers *buffers;

940

unsigned long buf_align;

941

unsigned long buf_align;

941

struct nand_hw_control hwcontrol;

942

struct nand_hw_control hwcontrol;

942

943

uint8_t *bbt;

944

uint8_t *bbt;

944

struct nand_bbt_descr *bbt_td;

945

struct nand_bbt_descr *bbt_td;

945

struct nand_bbt_descr *bbt_md;

946

struct nand_bbt_descr *bbt_md;

946

947

struct nand_bbt_descr *badblock_pattern;

948

struct nand_bbt_descr *badblock_pattern;

948

949

void *priv;

950

void *priv;

950

};

951

};

951

952

static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)

953

static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)

953

{

954

{

954

return container_of(mtd, struct nand_chip, mtd);

955

return container_of(mtd, struct nand_chip, mtd);

955

}

956

}

956

957

static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)

958

static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)

958

{

959

{

959

return &chip->mtd;

960

return &chip->mtd;

960

}

961

}

961

962

static inline void *nand_get_controller_data(struct nand_chip *chip)

963

static inline void *nand_get_controller_data(struct nand_chip *chip)

963

{

964

{

964

return chip->priv;

965

return chip->priv;

965

}

966

}

966

967

static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)

968

static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)

968

{

969

{

969

chip->priv = priv;

970

chip->priv = priv;

970

}

971

}

971

972

/*

973

/*

973

* NAND Flash Manufacturer ID Codes

974

* NAND Flash Manufacturer ID Codes

974

*/

975

*/

975

#define NAND_MFR_TOSHIBA 0x98

976

#define NAND_MFR_TOSHIBA 0x98

976

#define NAND_MFR_SAMSUNG 0xec

977

#define NAND_MFR_SAMSUNG 0xec

977

#define NAND_MFR_FUJITSU 0x04

978

#define NAND_MFR_FUJITSU 0x04

978

#define NAND_MFR_NATIONAL 0x8f

979

#define NAND_MFR_NATIONAL 0x8f

979

#define NAND_MFR_RENESAS 0x07

980

#define NAND_MFR_RENESAS 0x07

980

#define NAND_MFR_STMICRO 0x20

981

#define NAND_MFR_STMICRO 0x20

981

#define NAND_MFR_HYNIX 0xad

982

#define NAND_MFR_HYNIX 0xad

982

#define NAND_MFR_MICRON 0x2c

983

#define NAND_MFR_MICRON 0x2c

983

#define NAND_MFR_AMD 0x01

984

#define NAND_MFR_AMD 0x01

984

#define NAND_MFR_MACRONIX 0xc2

985

#define NAND_MFR_MACRONIX 0xc2

985

#define NAND_MFR_EON 0x92

986

#define NAND_MFR_EON 0x92

986

#define NAND_MFR_SANDISK 0x45

987

#define NAND_MFR_SANDISK 0x45

987

#define NAND_MFR_INTEL 0x89

988

#define NAND_MFR_INTEL 0x89

988

#define NAND_MFR_ATO 0x9b

989

#define NAND_MFR_ATO 0x9b

989

990

/* The maximum expected count of bytes in the NAND ID sequence */

991

/* The maximum expected count of bytes in the NAND ID sequence */

991

#define NAND_MAX_ID_LEN 8

992

#define NAND_MAX_ID_LEN 8

992

993

/*

994

/*

994

* A helper for defining older NAND chips where the second ID byte fully

995

* A helper for defining older NAND chips where the second ID byte fully

995

* defined the chip, including the geometry (chip size, eraseblock size, page

996

* defined the chip, including the geometry (chip size, eraseblock size, page

996

* size). All these chips have 512 bytes NAND page size.

997

* size). All these chips have 512 bytes NAND page size.

997

*/

998

*/

998

#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \

999

#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \

999

{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \

1000

{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \

1000

.chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }

1001

.chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }

1001

1002

/*

1003

/*

1003

* A helper for defining newer chips which report their page size and

1004

* A helper for defining newer chips which report their page size and

1004

* eraseblock size via the extended ID bytes.

1005

* eraseblock size via the extended ID bytes.

1005

*

1006

*

1006

* The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with

1007

* The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with

1007

* EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the

1008

* EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the

1008

* device ID now only represented a particular total chip size (and voltage,

1009

* device ID now only represented a particular total chip size (and voltage,

1009

* buswidth), and the page size, eraseblock size, and OOB size could vary while

1010

* buswidth), and the page size, eraseblock size, and OOB size could vary while

1010

* using the same device ID.

1011

* using the same device ID.

1011

*/

1012

*/

1012

#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \

1013

#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \

1013

{ .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \

1014

{ .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \

1014

.options = (opts) }

1015

.options = (opts) }

1015

1016

#define NAND_ECC_INFO(_strength, _step) \

1017

#define NAND_ECC_INFO(_strength, _step) \

1017

{ .strength_ds = (_strength), .step_ds = (_step) }

1018

{ .strength_ds = (_strength), .step_ds = (_step) }

1018

#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)

1019

#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)

1019

#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)

1020

#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)

1020

1021

/**

1022

/**

1022

* struct nand_flash_dev - NAND Flash Device ID Structure

1023

* struct nand_flash_dev - NAND Flash Device ID Structure

1023

* @name: a human-readable name of the NAND chip

1024

* @name: a human-readable name of the NAND chip

1024

* @dev_id: the device ID (the second byte of the full chip ID array)

1025

* @dev_id: the device ID (the second byte of the full chip ID array)

1025

* @mfr_id: manufecturer ID part of the full chip ID array (refers the same

1026

* @mfr_id: manufecturer ID part of the full chip ID array (refers the same

1026

* memory address as @id[0])

1027

* memory address as @id[0])

1027

* @dev_id: device ID part of the full chip ID array (refers the same memory

1028

* @dev_id: device ID part of the full chip ID array (refers the same memory

1028

* address as @id[1])

1029

* address as @id[1])

1029

* @id: full device ID array

1030

* @id: full device ID array

1030

* @pagesize: size of the NAND page in bytes; if 0, then the real page size (as

1031

* @pagesize: size of the NAND page in bytes; if 0, then the real page size (as

1031

* well as the eraseblock size) is determined from the extended NAND

1032

* well as the eraseblock size) is determined from the extended NAND

1032

* chip ID array)

1033

* chip ID array)

1033

* @chipsize: total chip size in MiB

1034

* @chipsize: total chip size in MiB

1034

* @erasesize: eraseblock size in bytes (determined from the extended ID if 0)

1035

* @erasesize: eraseblock size in bytes (determined from the extended ID if 0)

1035

* @options: stores various chip bit options

1036

* @options: stores various chip bit options

1036

* @id_len: The valid length of the @id.

1037

* @id_len: The valid length of the @id.

1037

* @oobsize: OOB size

1038

* @oobsize: OOB size

1038

* @ecc: ECC correctability and step information from the datasheet.

1039

* @ecc: ECC correctability and step information from the datasheet.

1039

* @ecc.strength_ds: The ECC correctability from the datasheet, same as the

1040

* @ecc.strength_ds: The ECC correctability from the datasheet, same as the

1040

* @ecc_strength_ds in nand_chip{}.

1041

* @ecc_strength_ds in nand_chip{}.

1041

* @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the

1042

* @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the

1042

* @ecc_step_ds in nand_chip{}, also from the datasheet.

1043

* @ecc_step_ds in nand_chip{}, also from the datasheet.

1043

* For example, the "4bit ECC for each 512Byte" can be set with

1044

* For example, the "4bit ECC for each 512Byte" can be set with

1044

* NAND_ECC_INFO(4, 512).

1045

* NAND_ECC_INFO(4, 512).

1045

* @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND

1046

* @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND

1046

* reset. Should be deduced from timings described

1047

* reset. Should be deduced from timings described

1047

* in the datasheet.

1048

* in the datasheet.

1048

*

1049

*

1049

*/

1050

*/

1050

struct nand_flash_dev {

1051

struct nand_flash_dev {

1051

char *name;

1052

char *name;

1052

union {

1053

union {

1053

struct {

1054

struct {

1054

uint8_t mfr_id;

1055

uint8_t mfr_id;

1055

uint8_t dev_id;

1056

uint8_t dev_id;

1056

};

1057

};

1057

uint8_t id[NAND_MAX_ID_LEN];

1058

uint8_t id[NAND_MAX_ID_LEN];

1058

};

1059

};

1059

unsigned int pagesize;

1060

unsigned int pagesize;

1060

unsigned int chipsize;

1061

unsigned int chipsize;

1061

unsigned int erasesize;

1062

unsigned int erasesize;

1062

unsigned int options;

1063

unsigned int options;

1063

uint16_t id_len;

1064

uint16_t id_len;

1064

uint16_t oobsize;

1065

uint16_t oobsize;

1065

struct {

1066

struct {

1066

uint16_t strength_ds;

1067

uint16_t strength_ds;

1067

uint16_t step_ds;

1068

uint16_t step_ds;

1068

} ecc;

1069

} ecc;

1069

int onfi_timing_mode_default;

1070

int onfi_timing_mode_default;

1070

};

1071

};

1071

1072

/**

1073

/**

1073

* struct nand_manufacturers - NAND Flash Manufacturer ID Structure

1074

* struct nand_manufacturers - NAND Flash Manufacturer ID Structure

1074

* @name: Manufacturer name

1075

* @name: Manufacturer name

1075

* @id: manufacturer ID code of device.

1076

* @id: manufacturer ID code of device.

1076

*/

1077

*/

1077

struct nand_manufacturers {

1078

struct nand_manufacturers {

1078

int id;

1079

int id;

1079

char *name;

1080

char *name;

1080

};

1081

};

1081

1082

extern struct nand_flash_dev nand_flash_ids[];

1083

extern struct nand_flash_dev nand_flash_ids[];

1083

extern struct nand_manufacturers nand_manuf_ids[];

1084

extern struct nand_manufacturers nand_manuf_ids[];

1084

1085

int nand_default_bbt(struct mtd_info *mtd);

1086

int nand_default_bbt(struct mtd_info *mtd);

1086

int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);

1087

int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);

1087

int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);

1088

int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);

1088

int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);

1089

int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);

1089

int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,

1090

int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,

1090

int allowbbt);

1091

int allowbbt);

1091

int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,

1092

int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,

1092

size_t *retlen, uint8_t *buf);

1093

size_t *retlen, uint8_t *buf);

1093

1094

/*

1095

/*

1095

* Constants for oob configuration

1096

* Constants for oob configuration

1096

*/

1097

*/

1097

#define NAND_SMALL_BADBLOCK_POS 5

1098

#define NAND_SMALL_BADBLOCK_POS 5

1098

#define NAND_LARGE_BADBLOCK_POS 0

1099

#define NAND_LARGE_BADBLOCK_POS 0

1099

1100

/**

1101

/**

1101

* struct platform_nand_chip - chip level device structure

1102

* struct platform_nand_chip - chip level device structure

1102

* @nr_chips: max. number of chips to scan for

1103

* @nr_chips: max. number of chips to scan for

1103

* @chip_offset: chip number offset

1104

* @chip_offset: chip number offset

1104

* @nr_partitions: number of partitions pointed to by partitions (or zero)

1105

* @nr_partitions: number of partitions pointed to by partitions (or zero)

1105

* @partitions: mtd partition list

1106

* @partitions: mtd partition list

1106

* @chip_delay: R/B delay value in us

1107

* @chip_delay: R/B delay value in us

1107

* @options: Option flags, e.g. 16bit buswidth

1108

* @options: Option flags, e.g. 16bit buswidth

1108

* @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH

1109

* @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH

1109

* @part_probe_types: NULL-terminated array of probe types

1110

* @part_probe_types: NULL-terminated array of probe types

1110

*/

1111

*/

1111

struct platform_nand_chip {

1112

struct platform_nand_chip {

1112

int nr_chips;

1113

int nr_chips;

1113

int chip_offset;

1114

int chip_offset;

1114

int nr_partitions;

1115

int nr_partitions;

1115

struct mtd_partition *partitions;

1116

struct mtd_partition *partitions;

1116

int chip_delay;

1117

int chip_delay;

1117

unsigned int options;

1118

unsigned int options;

1118

unsigned int bbt_options;

1119

unsigned int bbt_options;

1119

const char **part_probe_types;

1120

const char **part_probe_types;

1120

};

1121

};

1121

1122

/* Keep gcc happy */

1123

/* Keep gcc happy */

1123

struct platform_device;

1124

struct platform_device;

1124

1125

/**

1126

/**

1126

* struct platform_nand_ctrl - controller level device structure

1127

* struct platform_nand_ctrl - controller level device structure

1127

* @probe: platform specific function to probe/setup hardware

1128

* @probe: platform specific function to probe/setup hardware

1128

* @remove: platform specific function to remove/teardown hardware

1129

* @remove: platform specific function to remove/teardown hardware

1129

* @hwcontrol: platform specific hardware control structure

1130

* @hwcontrol: platform specific hardware control structure

1130

* @dev_ready: platform specific function to read ready/busy pin

1131

* @dev_ready: platform specific function to read ready/busy pin

1131

* @select_chip: platform specific chip select function

1132

* @select_chip: platform specific chip select function

1132

* @cmd_ctrl: platform specific function for controlling

1133

* @cmd_ctrl: platform specific function for controlling

1133

* ALE/CLE/nCE. Also used to write command and address

1134

* ALE/CLE/nCE. Also used to write command and address

1134

* @write_buf: platform specific function for write buffer

1135

* @write_buf: platform specific function for write buffer

1135

* @read_buf: platform specific function for read buffer

1136

* @read_buf: platform specific function for read buffer

1136

* @read_byte: platform specific function to read one byte from chip

1137

* @read_byte: platform specific function to read one byte from chip

1137

* @priv: private data to transport driver specific settings

1138

* @priv: private data to transport driver specific settings

1138

*

1139

*

1139

* All fields are optional and depend on the hardware driver requirements

1140

* All fields are optional and depend on the hardware driver requirements

1140

*/

1141

*/

1141

struct platform_nand_ctrl {

1142

struct platform_nand_ctrl {

1142

int (*probe)(struct platform_device *pdev);

1143

int (*probe)(struct platform_device *pdev);

1143

void (*remove)(struct platform_device *pdev);

1144

void (*remove)(struct platform_device *pdev);

1144

void (*hwcontrol)(struct mtd_info *mtd, int cmd);

1145

void (*hwcontrol)(struct mtd_info *mtd, int cmd);

1145

int (*dev_ready)(struct mtd_info *mtd);

1146

int (*dev_ready)(struct mtd_info *mtd);

1146

void (*select_chip)(struct mtd_info *mtd, int chip);

1147

void (*select_chip)(struct mtd_info *mtd, int chip);

1147

void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);

1148

void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);

1148

void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);

1149

void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);

1149

void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);

1150

void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);

1150

unsigned char (*read_byte)(struct mtd_info *mtd);

1151

unsigned char (*read_byte)(struct mtd_info *mtd);

1151

void *priv;

1152

void *priv;

1152

};

1153

};

1153

1154

/**

1155

/**

1155

* struct platform_nand_data - container structure for platform-specific data

1156

* struct platform_nand_data - container structure for platform-specific data

1156

* @chip: chip level chip structure

1157

* @chip: chip level chip structure

1157

* @ctrl: controller level device structure

1158

* @ctrl: controller level device structure

1158

*/

1159

*/

1159

struct platform_nand_data {

1160

struct platform_nand_data {

1160

struct platform_nand_chip chip;

1161

struct platform_nand_chip chip;

1161

struct platform_nand_ctrl ctrl;

1162

struct platform_nand_ctrl ctrl;

1162

};

1163

};

1163

1164

#ifdef CONFIG_SYS_NAND_ONFI_DETECTION

1165

#ifdef CONFIG_SYS_NAND_ONFI_DETECTION

1165

/* return the supported features. */

1166

/* return the supported features. */

1166

static inline int onfi_feature(struct nand_chip *chip)

1167

static inline int onfi_feature(struct nand_chip *chip)

1167

{

1168

{

1168

return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;

1169

return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;

1169

}

1170

}

1170

1171

/* return the supported asynchronous timing mode. */

1172

/* return the supported asynchronous timing mode. */

1172

static inline int onfi_get_async_timing_mode(struct nand_chip *chip)

1173

static inline int onfi_get_async_timing_mode(struct nand_chip *chip)

1173

{

1174

{

1174

if (!chip->onfi_version)

1175

if (!chip->onfi_version)

1175

return ONFI_TIMING_MODE_UNKNOWN;

1176

return ONFI_TIMING_MODE_UNKNOWN;

1176

return le16_to_cpu(chip->onfi_params.async_timing_mode);

1177

return le16_to_cpu(chip->onfi_params.async_timing_mode);

1177

}

1178

}

1178

1179

/* return the supported synchronous timing mode. */

1180

/* return the supported synchronous timing mode. */

1180

static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)

1181

static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)

1181

{

1182

{

1182

if (!chip->onfi_version)

1183

if (!chip->onfi_version)

1183

return ONFI_TIMING_MODE_UNKNOWN;

1184

return ONFI_TIMING_MODE_UNKNOWN;

1184

return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);

1185

return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);

1185

}

1186

}

1186

#else

1187

#else

1187

static inline int onfi_feature(struct nand_chip *chip)

1188

static inline int onfi_feature(struct nand_chip *chip)

1188

{

1189

{

1189

return 0;

1190

return 0;

1190

}

1191

}

1191

1192

static inline int onfi_get_async_timing_mode(struct nand_chip *chip)

1193

static inline int onfi_get_async_timing_mode(struct nand_chip *chip)

1193

{

1194

{

1194

return ONFI_TIMING_MODE_UNKNOWN;

1195

return ONFI_TIMING_MODE_UNKNOWN;

1195

}

1196

}

1196

1197

static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)

1198

static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)

1198

{

1199

{

1199

return ONFI_TIMING_MODE_UNKNOWN;

1200

return ONFI_TIMING_MODE_UNKNOWN;

1200

}

1201

}

1201

#endif

1202

#endif

1202

1203

int onfi_init_data_interface(struct nand_chip *chip,

1204

int onfi_init_data_interface(struct nand_chip *chip,

1204

struct nand_data_interface *iface,

1205

struct nand_data_interface *iface,

1205

enum nand_data_interface_type type,

1206

enum nand_data_interface_type type,

1206

int timing_mode);

1207

int timing_mode);

1207

1208

/*

1209

/*

1209

* Check if it is a SLC nand.

1210

* Check if it is a SLC nand.

1210

* The !nand_is_slc() can be used to check the MLC/TLC nand chips.

1211

* The !nand_is_slc() can be used to check the MLC/TLC nand chips.

1211

* We do not distinguish the MLC and TLC now.

1212

* We do not distinguish the MLC and TLC now.

1212

*/

1213

*/

1213

static inline bool nand_is_slc(struct nand_chip *chip)

1214

static inline bool nand_is_slc(struct nand_chip *chip)

1214

{

1215

{

1215

return chip->bits_per_cell == 1;

1216

return chip->bits_per_cell == 1;

1216

}

1217

}

1217

1218

/**

1219

/**

1219

* Check if the opcode's address should be sent only on the lower 8 bits

1220

* Check if the opcode's address should be sent only on the lower 8 bits

1220

* @command: opcode to check

1221

* @command: opcode to check

1221

*/

1222

*/

1222

static inline int nand_opcode_8bits(unsigned int command)

1223

static inline int nand_opcode_8bits(unsigned int command)

1223

{

1224

{

1224

switch (command) {

1225

switch (command) {

1225

case NAND_CMD_READID:

1226

case NAND_CMD_READID:

1226

case NAND_CMD_PARAM:

1227

case NAND_CMD_PARAM:

1227

case NAND_CMD_GET_FEATURES:

1228

case NAND_CMD_GET_FEATURES:

1228

case NAND_CMD_SET_FEATURES:

1229

case NAND_CMD_SET_FEATURES:

1229

return 1;

1230

return 1;

1230

default:

1231

default:

1231

break;

1232

break;

1232

}

1233

}

1233

return 0;

1234

return 0;

1234

}

1235

}

1235

1236

/* return the supported JEDEC features. */

1237

/* return the supported JEDEC features. */

1237

static inline int jedec_feature(struct nand_chip *chip)

1238

static inline int jedec_feature(struct nand_chip *chip)

1238

{

1239

{

1239

return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)

1240

return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)

1240

: 0;

1241

: 0;

1241

}

1242

}

1242

1243

/* Standard NAND functions from nand_base.c */

1244

/* Standard NAND functions from nand_base.c */

1244

void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);

1245

void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);

1245

void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);

1246

void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);

1246

void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);

1247

void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);

1247

void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);

1248

void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);

1248

uint8_t nand_read_byte(struct mtd_info *mtd);

1249

uint8_t nand_read_byte(struct mtd_info *mtd);

1249

1250

/* get timing characteristics from ONFI timing mode. */

1251

/* get timing characteristics from ONFI timing mode. */

1251

const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);

1252

const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);

1252

/* get data interface from ONFI timing mode 0, used after reset. */

1253

/* get data interface from ONFI timing mode 0, used after reset. */

1253

const struct nand_data_interface *nand_get_default_data_interface(void);

1254

const struct nand_data_interface *nand_get_default_data_interface(void);

1254

1255

int nand_check_erased_ecc_chunk(void *data, int datalen,

1256

int nand_check_erased_ecc_chunk(void *data, int datalen,

1256

void *ecc, int ecclen,

1257

void *ecc, int ecclen,

1257

void *extraoob, int extraooblen,

1258

void *extraoob, int extraooblen,

1258

int threshold);

1259

int threshold);

1259

1260

int nand_check_ecc_caps(struct nand_chip *chip,

1261

int nand_check_ecc_caps(struct nand_chip *chip,

1261

const struct nand_ecc_caps *caps, int oobavail);

1262

const struct nand_ecc_caps *caps, int oobavail);

1262

1263

int nand_match_ecc_req(struct nand_chip *chip,

1264

int nand_match_ecc_req(struct nand_chip *chip,

1264

const struct nand_ecc_caps *caps, int oobavail);

1265

const struct nand_ecc_caps *caps, int oobavail);

1265

1266

int nand_maximize_ecc(struct nand_chip *chip,

1267

int nand_maximize_ecc(struct nand_chip *chip,

1267

const struct nand_ecc_caps *caps, int oobavail);

1268

const struct nand_ecc_caps *caps, int oobavail);

1268

1269

/* Reset and initialize a NAND device */

1270

/* Reset and initialize a NAND device */

1270

int nand_reset(struct nand_chip *chip, int chipnr);

1271

int nand_reset(struct nand_chip *chip, int chipnr);

1271

#endif /* __LINUX_MTD_RAWNAND_H */

1272

#endif /* __LINUX_MTD_RAWNAND_H */

1272

1273

GITLAB

mtd: nand: include <asm/cache.h> from include/linux/mtd/rawnand.h

 /*
  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
  *                        Steven J. Hill <sjhill@realitydiluted.com>
  *		          Thomas Gleixner <tglx@linutronix.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
  * Info:
  *	Contains standard defines and IDs for NAND flash devices
  *
  * Changelog:
  *	See git changelog.
  */
 #ifndef __LINUX_MTD_RAWNAND_H
 #define __LINUX_MTD_RAWNAND_H
 #include <config.h>
 #include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/flashchip.h>
 #include <linux/mtd/bbm.h>
+#include <asm/cache.h>
 struct mtd_info;
 struct nand_flash_dev;
 struct device_node;
 /* Scan and identify a NAND device */
 int nand_scan(struct mtd_info *mtd, int max_chips);
 /*
  * Separate phases of nand_scan(), allowing board driver to intervene
  * and override command or ECC setup according to flash type.
  */
 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
 			   struct nand_flash_dev *table);
 int nand_scan_tail(struct mtd_info *mtd);
 /* Free resources held by the NAND device */
 void nand_release(struct mtd_info *mtd);
 /* Internal helper for board drivers which need to override command function */
 void nand_wait_ready(struct mtd_info *mtd);
 /*
  * This constant declares the max. oobsize / page, which
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
 #define NAND_MAX_OOBSIZE       1664
 #define NAND_MAX_PAGESIZE      16384
 /*
  * Constants for hardware specific CLE/ALE/NCE function
  *
  * These are bits which can be or'ed to set/clear multiple
  * bits in one go.
  */
 /* Select the chip by setting nCE to low */
 #define NAND_NCE		0x01
 /* Select the command latch by setting CLE to high */
 #define NAND_CLE		0x02
 /* Select the address latch by setting ALE to high */
 #define NAND_ALE		0x04
 #define NAND_CTRL_CLE		(NAND_NCE | NAND_CLE)
 #define NAND_CTRL_ALE		(NAND_NCE | NAND_ALE)
 #define NAND_CTRL_CHANGE	0x80
 /*
  * Standard NAND flash commands
  */
 #define NAND_CMD_READ0		0
 #define NAND_CMD_READ1		1
 #define NAND_CMD_RNDOUT		5
 #define NAND_CMD_PAGEPROG	0x10
 #define NAND_CMD_READOOB	0x50
 #define NAND_CMD_ERASE1		0x60
 #define NAND_CMD_STATUS		0x70
 #define NAND_CMD_SEQIN		0x80
 #define NAND_CMD_RNDIN		0x85
 #define NAND_CMD_READID		0x90
 #define NAND_CMD_ERASE2		0xd0
 #define NAND_CMD_PARAM		0xec
 #define NAND_CMD_GET_FEATURES	0xee
 #define NAND_CMD_SET_FEATURES	0xef
 #define NAND_CMD_RESET		0xff
 #define NAND_CMD_LOCK		0x2a
 #define NAND_CMD_UNLOCK1	0x23
 #define NAND_CMD_UNLOCK2	0x24
 /* Extended commands for large page devices */
 #define NAND_CMD_READSTART	0x30
 #define NAND_CMD_RNDOUTSTART	0xE0
 #define NAND_CMD_CACHEDPROG	0x15
 /* Extended commands for AG-AND device */
 /*
  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  *       there is no way to distinguish that from NAND_CMD_READ0
  *       until the remaining sequence of commands has been completed
  *       so add a high order bit and mask it off in the command.
  */
 #define NAND_CMD_DEPLETE1	0x100
 #define NAND_CMD_DEPLETE2	0x38
 #define NAND_CMD_STATUS_MULTI	0x71
 #define NAND_CMD_STATUS_ERROR	0x72
 /* multi-bank error status (banks 0-3) */
 #define NAND_CMD_STATUS_ERROR0	0x73
 #define NAND_CMD_STATUS_ERROR1	0x74
 #define NAND_CMD_STATUS_ERROR2	0x75
 #define NAND_CMD_STATUS_ERROR3	0x76
 #define NAND_CMD_STATUS_RESET	0x7f
 #define NAND_CMD_STATUS_CLEAR	0xff
 #define NAND_CMD_NONE		-1
 /* Status bits */
 #define NAND_STATUS_FAIL	0x01
 #define NAND_STATUS_FAIL_N1	0x02
 #define NAND_STATUS_TRUE_READY	0x20
 #define NAND_STATUS_READY	0x40
 #define NAND_STATUS_WP		0x80
 #define NAND_DATA_IFACE_CHECK_ONLY	-1
 /*
  * Constants for ECC_MODES
  */
 typedef enum {
 	NAND_ECC_NONE,
 	NAND_ECC_SOFT,
 	NAND_ECC_HW,
 	NAND_ECC_HW_SYNDROME,
 	NAND_ECC_HW_OOB_FIRST,
 	NAND_ECC_SOFT_BCH,
 } nand_ecc_modes_t;
 /*
  * Constants for Hardware ECC
  */
 /* Reset Hardware ECC for read */
 #define NAND_ECC_READ		0
 /* Reset Hardware ECC for write */
 #define NAND_ECC_WRITE		1
 /* Enable Hardware ECC before syndrome is read back from flash */
 #define NAND_ECC_READSYN	2
 /*
  * Enable generic NAND 'page erased' check. This check is only done when
  * ecc.correct() returns -EBADMSG.
  * Set this flag if your implementation does not fix bitflips in erased
  * pages and you want to rely on the default implementation.
  */
 #define NAND_ECC_GENERIC_ERASED_CHECK	BIT(0)
 #define NAND_ECC_MAXIMIZE		BIT(1)
 /*
  * If your controller already sends the required NAND commands when
  * reading or writing a page, then the framework is not supposed to
  * send READ0 and SEQIN/PAGEPROG respectively.
  */
 #define NAND_ECC_CUSTOM_PAGE_ACCESS	BIT(2)
 /* Bit mask for flags passed to do_nand_read_ecc */
 #define NAND_GET_DEVICE		0x80
 /*
  * Option constants for bizarre disfunctionality and real
  * features.
  */
 /* Buswidth is 16 bit */
 #define NAND_BUSWIDTH_16	0x00000002
 /* Device supports partial programming without padding */
 #define NAND_NO_PADDING		0x00000004
 /* Chip has cache program function */
 #define NAND_CACHEPRG		0x00000008
 /* Chip has copy back function */
 #define NAND_COPYBACK		0x00000010
 /*
  * Chip requires ready check on read (for auto-incremented sequential read).
  * True only for small page devices; large page devices do not support
  * autoincrement.
  */
 #define NAND_NEED_READRDY	0x00000100
 /* Chip does not allow subpage writes */
 #define NAND_NO_SUBPAGE_WRITE	0x00000200
 /* Device is one of 'new' xD cards that expose fake nand command set */
 #define NAND_BROKEN_XD		0x00000400
 /* Device behaves just like nand, but is readonly */
 #define NAND_ROM		0x00000800
 /* Device supports subpage reads */
 #define NAND_SUBPAGE_READ	0x00001000
 /*
  * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
  * patterns.
  */
 #define NAND_NEED_SCRAMBLING	0x00002000
 /* Device needs 3rd row address cycle */
 #define NAND_ROW_ADDR_3		0x00004000
 /* Options valid for Samsung large page devices */
 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
 /* Macros to identify the above */
 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
 /* Non chip related options */
 /* This option skips the bbt scan during initialization. */
 #define NAND_SKIP_BBTSCAN	0x00010000
 /*
  * This option is defined if the board driver allocates its own buffers
  * (e.g. because it needs them DMA-coherent).
  */
 #define NAND_OWN_BUFFERS	0x00020000
 /* Chip may not exist, so silence any errors in scan */
 #define NAND_SCAN_SILENT_NODEV	0x00040000
 /*
  * Autodetect nand buswidth with readid/onfi.
  * This suppose the driver will configure the hardware in 8 bits mode
  * when calling nand_scan_ident, and update its configuration
  * before calling nand_scan_tail.
  */
 #define NAND_BUSWIDTH_AUTO      0x00080000
 /*
  * This option could be defined by controller drivers to protect against
  * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
  */
 #define NAND_USE_BOUNCE_BUFFER	0x00100000
 /* Options set by nand scan */
 /* bbt has already been read */
 #define NAND_BBT_SCANNED	0x40000000
 /* Nand scan has allocated controller struct */
 #define NAND_CONTROLLER_ALLOC	0x80000000
 /* Cell info constants */
 #define NAND_CI_CHIPNR_MSK	0x03
 #define NAND_CI_CELLTYPE_MSK	0x0C
 #define NAND_CI_CELLTYPE_SHIFT	2
 /* Keep gcc happy */
 struct nand_chip;
 /* ONFI features */
 #define ONFI_FEATURE_16_BIT_BUS		(1 << 0)
 #define ONFI_FEATURE_EXT_PARAM_PAGE	(1 << 7)
 /* ONFI timing mode, used in both asynchronous and synchronous mode */
 #define ONFI_TIMING_MODE_0		(1 << 0)
 #define ONFI_TIMING_MODE_1		(1 << 1)
 #define ONFI_TIMING_MODE_2		(1 << 2)
 #define ONFI_TIMING_MODE_3		(1 << 3)
 #define ONFI_TIMING_MODE_4		(1 << 4)
 #define ONFI_TIMING_MODE_5		(1 << 5)
 #define ONFI_TIMING_MODE_UNKNOWN	(1 << 6)
 /* ONFI feature address */
 #define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
 /* Vendor-specific feature address (Micron) */
 #define ONFI_FEATURE_ADDR_READ_RETRY	0x89
 /* ONFI subfeature parameters length */
 #define ONFI_SUBFEATURE_PARAM_LEN	4
 /* ONFI optional commands SET/GET FEATURES supported? */
 #define ONFI_OPT_CMD_SET_GET_FEATURES	(1 << 2)
 struct nand_onfi_params {
 	/* rev info and features block */
 	/* 'O' 'N' 'F' 'I'  */
 	u8 sig[4];
 	__le16 revision;
 	__le16 features;
 	__le16 opt_cmd;
 	u8 reserved0[2];
 	__le16 ext_param_page_length; /* since ONFI 2.1 */
 	u8 num_of_param_pages;        /* since ONFI 2.1 */
 	u8 reserved1[17];
 	/* manufacturer information block */
 	char manufacturer[12];
 	char model[20];
 	u8 jedec_id;
 	__le16 date_code;
 	u8 reserved2[13];
 	/* memory organization block */
 	__le32 byte_per_page;
 	__le16 spare_bytes_per_page;
 	__le32 data_bytes_per_ppage;
 	__le16 spare_bytes_per_ppage;
 	__le32 pages_per_block;
 	__le32 blocks_per_lun;
 	u8 lun_count;
 	u8 addr_cycles;
 	u8 bits_per_cell;
 	__le16 bb_per_lun;
 	__le16 block_endurance;
 	u8 guaranteed_good_blocks;
 	__le16 guaranteed_block_endurance;
 	u8 programs_per_page;
 	u8 ppage_attr;
 	u8 ecc_bits;
 	u8 interleaved_bits;
 	u8 interleaved_ops;
 	u8 reserved3[13];
 	/* electrical parameter block */
 	u8 io_pin_capacitance_max;
 	__le16 async_timing_mode;
 	__le16 program_cache_timing_mode;
 	__le16 t_prog;
 	__le16 t_bers;
 	__le16 t_r;
 	__le16 t_ccs;
 	__le16 src_sync_timing_mode;
 	u8 src_ssync_features;
 	__le16 clk_pin_capacitance_typ;
 	__le16 io_pin_capacitance_typ;
 	__le16 input_pin_capacitance_typ;
 	u8 input_pin_capacitance_max;
 	u8 driver_strength_support;
 	__le16 t_int_r;
 	__le16 t_adl;
 	u8 reserved4[8];
 	/* vendor */
 	__le16 vendor_revision;
 	u8 vendor[88];
 	__le16 crc;
 } __packed;
 #define ONFI_CRC_BASE	0x4F4E
 /* Extended ECC information Block Definition (since ONFI 2.1) */
 struct onfi_ext_ecc_info {
 	u8 ecc_bits;
 	u8 codeword_size;
 	__le16 bb_per_lun;
 	__le16 block_endurance;
 	u8 reserved[2];
 } __packed;
 #define ONFI_SECTION_TYPE_0	0	/* Unused section. */
 #define ONFI_SECTION_TYPE_1	1	/* for additional sections. */
 #define ONFI_SECTION_TYPE_2	2	/* for ECC information. */
 struct onfi_ext_section {
 	u8 type;
 	u8 length;
 } __packed;
 #define ONFI_EXT_SECTION_MAX 8
 /* Extended Parameter Page Definition (since ONFI 2.1) */
 struct onfi_ext_param_page {
 	__le16 crc;
 	u8 sig[4];             /* 'E' 'P' 'P' 'S' */
 	u8 reserved0[10];
 	struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
 	/*
 	 * The actual size of the Extended Parameter Page is in
 	 * @ext_param_page_length of nand_onfi_params{}.
 	 * The following are the variable length sections.
 	 * So we do not add any fields below. Please see the ONFI spec.
 	 */
 } __packed;
 struct nand_onfi_vendor_micron {
 	u8 two_plane_read;
 	u8 read_cache;
 	u8 read_unique_id;
 	u8 dq_imped;
 	u8 dq_imped_num_settings;
 	u8 dq_imped_feat_addr;
 	u8 rb_pulldown_strength;
 	u8 rb_pulldown_strength_feat_addr;
 	u8 rb_pulldown_strength_num_settings;
 	u8 otp_mode;
 	u8 otp_page_start;
 	u8 otp_data_prot_addr;
 	u8 otp_num_pages;
 	u8 otp_feat_addr;
 	u8 read_retry_options;
 	u8 reserved[72];
 	u8 param_revision;
 } __packed;
 struct jedec_ecc_info {
 	u8 ecc_bits;
 	u8 codeword_size;
 	__le16 bb_per_lun;
 	__le16 block_endurance;
 	u8 reserved[2];
 } __packed;
 /* JEDEC features */
 #define JEDEC_FEATURE_16_BIT_BUS	(1 << 0)
 struct nand_jedec_params {
 	/* rev info and features block */
 	/* 'J' 'E' 'S' 'D'  */
 	u8 sig[4];
 	__le16 revision;
 	__le16 features;
 	u8 opt_cmd[3];
 	__le16 sec_cmd;
 	u8 num_of_param_pages;
 	u8 reserved0[18];
 	/* manufacturer information block */
 	char manufacturer[12];
 	char model[20];
 	u8 jedec_id[6];
 	u8 reserved1[10];
 	/* memory organization block */
 	__le32 byte_per_page;
 	__le16 spare_bytes_per_page;
 	u8 reserved2[6];
 	__le32 pages_per_block;
 	__le32 blocks_per_lun;
 	u8 lun_count;
 	u8 addr_cycles;
 	u8 bits_per_cell;
 	u8 programs_per_page;
 	u8 multi_plane_addr;
 	u8 multi_plane_op_attr;
 	u8 reserved3[38];
 	/* electrical parameter block */
 	__le16 async_sdr_speed_grade;
 	__le16 toggle_ddr_speed_grade;
 	__le16 sync_ddr_speed_grade;
 	u8 async_sdr_features;
 	u8 toggle_ddr_features;
 	u8 sync_ddr_features;
 	__le16 t_prog;
 	__le16 t_bers;
 	__le16 t_r;
 	__le16 t_r_multi_plane;
 	__le16 t_ccs;
 	__le16 io_pin_capacitance_typ;
 	__le16 input_pin_capacitance_typ;
 	__le16 clk_pin_capacitance_typ;
 	u8 driver_strength_support;
 	__le16 t_adl;
 	u8 reserved4[36];
 	/* ECC and endurance block */
 	u8 guaranteed_good_blocks;
 	__le16 guaranteed_block_endurance;
 	struct jedec_ecc_info ecc_info[4];
 	u8 reserved5[29];
 	/* reserved */
 	u8 reserved6[148];
 	/* vendor */
 	__le16 vendor_rev_num;
 	u8 reserved7[88];
 	/* CRC for Parameter Page */
 	__le16 crc;
 } __packed;
 /**
  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
  * @lock:               protection lock
  * @active:		the mtd device which holds the controller currently
  * @wq:			wait queue to sleep on if a NAND operation is in
  *			progress used instead of the per chip wait queue
  *			when a hw controller is available.
  */
 struct nand_hw_control {
 	spinlock_t lock;
 	struct nand_chip *active;
 };
 /**
  * struct nand_ecc_step_info - ECC step information of ECC engine
  * @stepsize: data bytes per ECC step
  * @strengths: array of supported strengths
  * @nstrengths: number of supported strengths
  */
 struct nand_ecc_step_info {
 	int stepsize;
 	const int *strengths;
 	int nstrengths;
 };
 /**
  * struct nand_ecc_caps - capability of ECC engine
  * @stepinfos: array of ECC step information
  * @nstepinfos: number of ECC step information
  * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
  */
 struct nand_ecc_caps {
 	const struct nand_ecc_step_info *stepinfos;
 	int nstepinfos;
 	int (*calc_ecc_bytes)(int step_size, int strength);
 };
 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...)	\
 static const int __name##_strengths[] = { __VA_ARGS__ };	\
 static const struct nand_ecc_step_info __name##_stepinfo = {	\
 	.stepsize = __step,					\
 	.strengths = __name##_strengths,			\
 	.nstrengths = ARRAY_SIZE(__name##_strengths),		\
 };								\
 static const struct nand_ecc_caps __name = {			\
 	.stepinfos = &__name##_stepinfo,			\
 	.nstepinfos = 1,					\
 	.calc_ecc_bytes = __calc,				\
 }
 /**
  * struct nand_ecc_ctrl - Control structure for ECC
  * @mode:	ECC mode
  * @steps:	number of ECC steps per page
  * @size:	data bytes per ECC step
  * @bytes:	ECC bytes per step
  * @strength:	max number of correctible bits per ECC step
  * @total:	total number of ECC bytes per page
  * @prepad:	padding information for syndrome based ECC generators
  * @postpad:	padding information for syndrome based ECC generators
  * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
  * @layout:	ECC layout control struct pointer
  * @priv:	pointer to private ECC control data
  * @hwctl:	function to control hardware ECC generator. Must only
  *		be provided if an hardware ECC is available
  * @calculate:	function for ECC calculation or readback from ECC hardware
  * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
  *		Should return a positive number representing the number of
  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
  *		ECC strength, or any other error code if the error is not
  *		directly related to correction.
  *		If -EBADMSG is returned the input buffers should be left
  *		untouched.
  * @read_page_raw:	function to read a raw page without ECC. This function
  *			should hide the specific layout used by the ECC
  *			controller and always return contiguous in-band and
  *			out-of-band data even if they're not stored
  *			contiguously on the NAND chip (e.g.
  *			NAND_ECC_HW_SYNDROME interleaves in-band and
  *			out-of-band data).
  * @write_page_raw:	function to write a raw page without ECC. This function
  *			should hide the specific layout used by the ECC
  *			controller and consider the passed data as contiguous
  *			in-band and out-of-band data. ECC controller is
  *			responsible for doing the appropriate transformations
  *			to adapt to its specific layout (e.g.
  *			NAND_ECC_HW_SYNDROME interleaves in-band and
  *			out-of-band data).
  * @read_page:	function to read a page according to the ECC generator
  *		requirements; returns maximum number of bitflips corrected in
  *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
  * @read_subpage:	function to read parts of the page covered by ECC;
  *			returns same as read_page()
  * @write_subpage:	function to write parts of the page covered by ECC.
  * @write_page:	function to write a page according to the ECC generator
  *		requirements.
  * @write_oob_raw:	function to write chip OOB data without ECC
  * @read_oob_raw:	function to read chip OOB data without ECC
  * @read_oob:	function to read chip OOB data
  * @write_oob:	function to write chip OOB data
  */
 struct nand_ecc_ctrl {
 	nand_ecc_modes_t mode;
 	int steps;
 	int size;
 	int bytes;
 	int total;
 	int strength;
 	int prepad;
 	int postpad;
 	unsigned int options;
 	struct nand_ecclayout	*layout;
 	void *priv;
 	void (*hwctl)(struct mtd_info *mtd, int mode);
 	int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 			uint8_t *ecc_code);
 	int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 			uint8_t *calc_ecc);
 	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint8_t *buf, int oob_required, int page);
 	int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 			const uint8_t *buf, int oob_required, int page);
 	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint8_t *buf, int oob_required, int page);
 	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint32_t offs, uint32_t len, uint8_t *buf, int page);
 	int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint32_t offset, uint32_t data_len,
 			const uint8_t *data_buf, int oob_required, int page);
 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 			const uint8_t *buf, int oob_required, int page);
 	int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 			int page);
 	int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 			int page);
 	int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
 	int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 			int page);
 };
 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
 {
 	return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
 }
 /**
  * struct nand_buffers - buffer structure for read/write
  * @ecccalc:	buffer pointer for calculated ECC, size is oobsize.
  * @ecccode:	buffer pointer for ECC read from flash, size is oobsize.
  * @databuf:	buffer pointer for data, size is (page size + oobsize).
  *
  * Do not change the order of buffers. databuf and oobrbuf must be in
  * consecutive order.
  */
 struct nand_buffers {
 	uint8_t	ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
 	uint8_t	ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
 	uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
 			      ARCH_DMA_MINALIGN)];
 };
 /**
  * struct nand_sdr_timings - SDR NAND chip timings
  *
  * This struct defines the timing requirements of a SDR NAND chip.
  * These information can be found in every NAND datasheets and the timings
  * meaning are described in the ONFI specifications:
  * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
  * Parameters)
  *
  * All these timings are expressed in picoseconds.
  *
  * @tBERS_max: Block erase time
  * @tCCS_min: Change column setup time
  * @tPROG_max: Page program time
  * @tR_max: Page read time
  * @tALH_min: ALE hold time
  * @tADL_min: ALE to data loading time
  * @tALS_min: ALE setup time
  * @tAR_min: ALE to RE# delay
  * @tCEA_max: CE# access time
  * @tCEH_min: CE# high hold time
  * @tCH_min:  CE# hold time
  * @tCHZ_max: CE# high to output hi-Z
  * @tCLH_min: CLE hold time
  * @tCLR_min: CLE to RE# delay
  * @tCLS_min: CLE setup time
  * @tCOH_min: CE# high to output hold
  * @tCS_min: CE# setup time
  * @tDH_min: Data hold time
  * @tDS_min: Data setup time
  * @tFEAT_max: Busy time for Set Features and Get Features
  * @tIR_min: Output hi-Z to RE# low
  * @tITC_max: Interface and Timing Mode Change time
  * @tRC_min: RE# cycle time
  * @tREA_max: RE# access time
  * @tREH_min: RE# high hold time
  * @tRHOH_min: RE# high to output hold
  * @tRHW_min: RE# high to WE# low
  * @tRHZ_max: RE# high to output hi-Z
  * @tRLOH_min: RE# low to output hold
  * @tRP_min: RE# pulse width
  * @tRR_min: Ready to RE# low (data only)
  * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
  *	      rising edge of R/B#.
  * @tWB_max: WE# high to SR[6] low
  * @tWC_min: WE# cycle time
  * @tWH_min: WE# high hold time
  * @tWHR_min: WE# high to RE# low
  * @tWP_min: WE# pulse width
  * @tWW_min: WP# transition to WE# low
  */
 struct nand_sdr_timings {
 	u64 tBERS_max;
 	u32 tCCS_min;
 	u64 tPROG_max;
 	u64 tR_max;
 	u32 tALH_min;
 	u32 tADL_min;
 	u32 tALS_min;
 	u32 tAR_min;
 	u32 tCEA_max;
 	u32 tCEH_min;
 	u32 tCH_min;
 	u32 tCHZ_max;
 	u32 tCLH_min;
 	u32 tCLR_min;
 	u32 tCLS_min;
 	u32 tCOH_min;
 	u32 tCS_min;
 	u32 tDH_min;
 	u32 tDS_min;
 	u32 tFEAT_max;
 	u32 tIR_min;
 	u32 tITC_max;
 	u32 tRC_min;
 	u32 tREA_max;
 	u32 tREH_min;
 	u32 tRHOH_min;
 	u32 tRHW_min;
 	u32 tRHZ_max;
 	u32 tRLOH_min;
 	u32 tRP_min;
 	u32 tRR_min;
 	u64 tRST_max;
 	u32 tWB_max;
 	u32 tWC_min;
 	u32 tWH_min;
 	u32 tWHR_min;
 	u32 tWP_min;
 	u32 tWW_min;
 };
 /**
  * enum nand_data_interface_type - NAND interface timing type
  * @NAND_SDR_IFACE:	Single Data Rate interface
  */
 enum nand_data_interface_type {
 	NAND_SDR_IFACE,
 };
 /**
  * struct nand_data_interface - NAND interface timing
  * @type:	type of the timing
  * @timings:	The timing, type according to @type
  */
 struct nand_data_interface {
 	enum nand_data_interface_type type;
 	union {
 		struct nand_sdr_timings sdr;
 	} timings;
 };
 /**
  * nand_get_sdr_timings - get SDR timing from data interface
  * @conf:	The data interface
  */
 static inline const struct nand_sdr_timings *
 nand_get_sdr_timings(const struct nand_data_interface *conf)
 {
 	if (conf->type != NAND_SDR_IFACE)
 		return ERR_PTR(-EINVAL);
 	return &conf->timings.sdr;
 }
 /**
  * struct nand_chip - NAND Private Flash Chip Data
  * @mtd:		MTD device registered to the MTD framework
  * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
  *			flash device
  * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
  *			flash device.
  * @flash_node:		[BOARDSPECIFIC] device node describing this instance
  * @read_byte:		[REPLACEABLE] read one byte from the chip
  * @read_word:		[REPLACEABLE] read one word from the chip
  * @write_byte:		[REPLACEABLE] write a single byte to the chip on the
  *			low 8 I/O lines
  * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
  * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
  * @select_chip:	[REPLACEABLE] select chip nr
  * @block_bad:		[REPLACEABLE] check if a block is bad, using OOB markers
  * @block_markbad:	[REPLACEABLE] mark a block bad
  * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific function for controlling
  *			ALE/CLE/nCE. Also used to write command and address
  * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accessing
  *			device ready/busy line. If set to NULL no access to
  *			ready/busy is available and the ready/busy information
  *			is read from the chip status register.
  * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing
  *			commands to the chip.
  * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on
  *			ready.
  * @setup_read_retry:	[FLASHSPECIFIC] flash (vendor) specific function for
  *			setting the read-retry mode. Mostly needed for MLC NAND.
  * @ecc:		[BOARDSPECIFIC] ECC control structure
  * @buffers:		buffer structure for read/write
  * @buf_align:		minimum buffer alignment required by a platform
  * @hwcontrol:		platform-specific hardware control structure
  * @erase:		[REPLACEABLE] erase function
  * @scan_bbt:		[REPLACEABLE] function to scan bad block table
  * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transferring
  *			data from array to read regs (tR).
  * @state:		[INTERN] the current state of the NAND device
  * @oob_poi:		"poison value buffer," used for laying out OOB data
  *			before writing
  * @page_shift:		[INTERN] number of address bits in a page (column
  *			address bits).
  * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
  * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
  * @chip_shift:		[INTERN] number of address bits in one chip
  * @options:		[BOARDSPECIFIC] various chip options. They can partly
  *			be set to inform nand_scan about special functionality.
  *			See the defines for further explanation.
  * @bbt_options:	[INTERN] bad block specific options. All options used
  *			here must come from bbm.h. By default, these options
  *			will be copied to the appropriate nand_bbt_descr's.
  * @badblockpos:	[INTERN] position of the bad block marker in the oob
  *			area.
  * @badblockbits:	[INTERN] minimum number of set bits in a good block's
  *			bad block marker position; i.e., BBM == 11110111b is
  *			not bad when badblockbits == 7
  * @bits_per_cell:	[INTERN] number of bits per cell. i.e., 1 means SLC.
  * @ecc_strength_ds:	[INTERN] ECC correctability from the datasheet.
  *			Minimum amount of bit errors per @ecc_step_ds guaranteed
  *			to be correctable. If unknown, set to zero.
  * @ecc_step_ds:	[INTERN] ECC step required by the @ecc_strength_ds,
  *                      also from the datasheet. It is the recommended ECC step
  *			size, if known; if unknown, set to zero.
  * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
  *			      set to the actually used ONFI mode if the chip is
  *			      ONFI compliant or deduced from the datasheet if
  *			      the NAND chip is not ONFI compliant.
  * @numchips:		[INTERN] number of physical chips
  * @chipsize:		[INTERN] the size of one chip for multichip arrays
  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
  * @pagebuf:		[INTERN] holds the pagenumber which is currently in
  *			data_buf.
  * @pagebuf_bitflips:	[INTERN] holds the bitflip count for the page which is
  *			currently in data_buf.
  * @subpagesize:	[INTERN] holds the subpagesize
  * @onfi_version:	[INTERN] holds the chip ONFI version (BCD encoded),
  *			non 0 if ONFI supported.
  * @jedec_version:	[INTERN] holds the chip JEDEC version (BCD encoded),
  *			non 0 if JEDEC supported.
  * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
  *			supported, 0 otherwise.
  * @jedec_params:	[INTERN] holds the JEDEC parameter page when JEDEC is
  *			supported, 0 otherwise.
  * @read_retries:	[INTERN] the number of read retry modes supported
  * @onfi_set_features:	[REPLACEABLE] set the features for ONFI nand
  * @onfi_get_features:	[REPLACEABLE] get the features for ONFI nand
  * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
  *			  chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
  *			  means the configuration should not be applied but
  *			  only checked.
  * @bbt:		[INTERN] bad block table pointer
  * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
  *			lookup.
  * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
  * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial
  *			bad block scan.
  * @controller:		[REPLACEABLE] a pointer to a hardware controller
  *			structure which is shared among multiple independent
  *			devices.
  * @priv:		[OPTIONAL] pointer to private chip data
  * @write_page:		[REPLACEABLE] High-level page write function
  */
 struct nand_chip {
 	struct mtd_info mtd;
 	void __iomem *IO_ADDR_R;
 	void __iomem *IO_ADDR_W;
 	int flash_node;
 	uint8_t (*read_byte)(struct mtd_info *mtd);
 	u16 (*read_word)(struct mtd_info *mtd);
 	void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
 	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 	void (*select_chip)(struct mtd_info *mtd, int chip);
 	int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
 	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 	int (*dev_ready)(struct mtd_info *mtd);
 	void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 			int page_addr);
 	int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 	int (*erase)(struct mtd_info *mtd, int page);
 	int (*scan_bbt)(struct mtd_info *mtd);
 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint32_t offset, int data_len, const uint8_t *buf,
 			int oob_required, int page, int raw);
 	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
 			int feature_addr, uint8_t *subfeature_para);
 	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
 			int feature_addr, uint8_t *subfeature_para);
 	int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
 	int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
 				    const struct nand_data_interface *conf);
 	int chip_delay;
 	unsigned int options;
 	unsigned int bbt_options;
 	int page_shift;
 	int phys_erase_shift;
 	int bbt_erase_shift;
 	int chip_shift;
 	int numchips;
 	uint64_t chipsize;
 	int pagemask;
 	int pagebuf;
 	unsigned int pagebuf_bitflips;
 	int subpagesize;
 	uint8_t bits_per_cell;
 	uint16_t ecc_strength_ds;
 	uint16_t ecc_step_ds;
 	int onfi_timing_mode_default;
 	int badblockpos;
 	int badblockbits;
 	int onfi_version;
 	int jedec_version;
 	struct nand_onfi_params	onfi_params;
 	struct nand_jedec_params jedec_params;
 	struct nand_data_interface *data_interface;
 	int read_retries;
 	flstate_t state;
 	uint8_t *oob_poi;
 	struct nand_hw_control *controller;
 	struct nand_ecclayout *ecclayout;
 	struct nand_ecc_ctrl ecc;
 	struct nand_buffers *buffers;
 	unsigned long buf_align;
 	struct nand_hw_control hwcontrol;
 	uint8_t *bbt;
 	struct nand_bbt_descr *bbt_td;
 	struct nand_bbt_descr *bbt_md;
 	struct nand_bbt_descr *badblock_pattern;
 	void *priv;
 };
 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
 {
 	return container_of(mtd, struct nand_chip, mtd);
 }
 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
 {
 	return &chip->mtd;
 }
 static inline void *nand_get_controller_data(struct nand_chip *chip)
 {
 	return chip->priv;
 }
 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
 {
 	chip->priv = priv;
 }
 /*
  * NAND Flash Manufacturer ID Codes
  */
 #define NAND_MFR_TOSHIBA	0x98
 #define NAND_MFR_SAMSUNG	0xec
 #define NAND_MFR_FUJITSU	0x04
 #define NAND_MFR_NATIONAL	0x8f
 #define NAND_MFR_RENESAS	0x07
 #define NAND_MFR_STMICRO	0x20
 #define NAND_MFR_HYNIX		0xad
 #define NAND_MFR_MICRON		0x2c
 #define NAND_MFR_AMD		0x01
 #define NAND_MFR_MACRONIX	0xc2
 #define NAND_MFR_EON		0x92
 #define NAND_MFR_SANDISK	0x45
 #define NAND_MFR_INTEL		0x89
 #define NAND_MFR_ATO		0x9b
 /* The maximum expected count of bytes in the NAND ID sequence */
 #define NAND_MAX_ID_LEN 8
 /*
  * A helper for defining older NAND chips where the second ID byte fully
  * defined the chip, including the geometry (chip size, eraseblock size, page
  * size). All these chips have 512 bytes NAND page size.
  */
 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
 	{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
 	  .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
 /*
  * A helper for defining newer chips which report their page size and
  * eraseblock size via the extended ID bytes.
  *
  * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
  * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
  * device ID now only represented a particular total chip size (and voltage,
  * buswidth), and the page size, eraseblock size, and OOB size could vary while
  * using the same device ID.
  */
 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
 	{ .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
 	  .options = (opts) }
 #define NAND_ECC_INFO(_strength, _step)	\
 			{ .strength_ds = (_strength), .step_ds = (_step) }
 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
  * @name: a human-readable name of the NAND chip
  * @dev_id: the device ID (the second byte of the full chip ID array)
  * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
  *          memory address as @id[0])
  * @dev_id: device ID part of the full chip ID array (refers the same memory
  *          address as @id[1])
  * @id: full device ID array
  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
  *            well as the eraseblock size) is determined from the extended NAND
  *            chip ID array)
  * @chipsize: total chip size in MiB
  * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
  * @options: stores various chip bit options
  * @id_len: The valid length of the @id.
  * @oobsize: OOB size
  * @ecc: ECC correctability and step information from the datasheet.
  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
  *                   @ecc_strength_ds in nand_chip{}.
  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
  *               @ecc_step_ds in nand_chip{}, also from the datasheet.
  *               For example, the "4bit ECC for each 512Byte" can be set with
  *               NAND_ECC_INFO(4, 512).
  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
  *			      reset. Should be deduced from timings described
  *			      in the datasheet.
  *
  */
 struct nand_flash_dev {
 	char *name;
 	union {
 		struct {
 			uint8_t mfr_id;
 			uint8_t dev_id;
 		};
 		uint8_t id[NAND_MAX_ID_LEN];
 	};
 	unsigned int pagesize;
 	unsigned int chipsize;
 	unsigned int erasesize;
 	unsigned int options;
 	uint16_t id_len;
 	uint16_t oobsize;
 	struct {
 		uint16_t strength_ds;
 		uint16_t step_ds;
 	} ecc;
 	int onfi_timing_mode_default;
 };
 /**
  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
  * @name:	Manufacturer name
  * @id:		manufacturer ID code of device.
 */
 struct nand_manufacturers {
 	int id;
 	char *name;
 };
 extern struct nand_flash_dev nand_flash_ids[];
 extern struct nand_manufacturers nand_manuf_ids[];
 int nand_default_bbt(struct mtd_info *mtd);
 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 			   int allowbbt);
 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 			size_t *retlen, uint8_t *buf);
 /*
 * Constants for oob configuration
 */
 #define NAND_SMALL_BADBLOCK_POS		5
 #define NAND_LARGE_BADBLOCK_POS		0
 /**
  * struct platform_nand_chip - chip level device structure
  * @nr_chips:		max. number of chips to scan for
  * @chip_offset:	chip number offset
  * @nr_partitions:	number of partitions pointed to by partitions (or zero)
  * @partitions:		mtd partition list
  * @chip_delay:		R/B delay value in us
  * @options:		Option flags, e.g. 16bit buswidth
  * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
  * @part_probe_types:	NULL-terminated array of probe types
  */
 struct platform_nand_chip {
 	int nr_chips;
 	int chip_offset;
 	int nr_partitions;
 	struct mtd_partition *partitions;
 	int chip_delay;
 	unsigned int options;
 	unsigned int bbt_options;
 	const char **part_probe_types;
 };
 /* Keep gcc happy */
 struct platform_device;
 /**
  * struct platform_nand_ctrl - controller level device structure
  * @probe:		platform specific function to probe/setup hardware
  * @remove:		platform specific function to remove/teardown hardware
  * @hwcontrol:		platform specific hardware control structure
  * @dev_ready:		platform specific function to read ready/busy pin
  * @select_chip:	platform specific chip select function
  * @cmd_ctrl:		platform specific function for controlling
  *			ALE/CLE/nCE. Also used to write command and address
  * @write_buf:		platform specific function for write buffer
  * @read_buf:		platform specific function for read buffer
  * @read_byte:		platform specific function to read one byte from chip
  * @priv:		private data to transport driver specific settings
  *
  * All fields are optional and depend on the hardware driver requirements
  */
 struct platform_nand_ctrl {
 	int (*probe)(struct platform_device *pdev);
 	void (*remove)(struct platform_device *pdev);
 	void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 	int (*dev_ready)(struct mtd_info *mtd);
 	void (*select_chip)(struct mtd_info *mtd, int chip);
 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 	unsigned char (*read_byte)(struct mtd_info *mtd);
 	void *priv;
 };
 /**
  * struct platform_nand_data - container structure for platform-specific data
  * @chip:		chip level chip structure
  * @ctrl:		controller level device structure
  */
 struct platform_nand_data {
 	struct platform_nand_chip chip;
 	struct platform_nand_ctrl ctrl;
 };
 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 /* return the supported features. */
 static inline int onfi_feature(struct nand_chip *chip)
 {
 	return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
 }
 /* return the supported asynchronous timing mode. */
 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
 {
 	if (!chip->onfi_version)
 		return ONFI_TIMING_MODE_UNKNOWN;
 	return le16_to_cpu(chip->onfi_params.async_timing_mode);
 }
 /* return the supported synchronous timing mode. */
 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
 {
 	if (!chip->onfi_version)
 		return ONFI_TIMING_MODE_UNKNOWN;
 	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
 }
 #else
 static inline int onfi_feature(struct nand_chip *chip)
 {
 	return 0;
 }
 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
 {
 	return ONFI_TIMING_MODE_UNKNOWN;
 }
 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
 {
 	return ONFI_TIMING_MODE_UNKNOWN;
 }
 #endif
 int onfi_init_data_interface(struct nand_chip *chip,
 			     struct nand_data_interface *iface,
 			     enum nand_data_interface_type type,
 			     int timing_mode);
 /*
  * Check if it is a SLC nand.
  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
  * We do not distinguish the MLC and TLC now.
  */
 static inline bool nand_is_slc(struct nand_chip *chip)
 {
 	return chip->bits_per_cell == 1;
 }
 /**
  * Check if the opcode's address should be sent only on the lower 8 bits
  * @command: opcode to check
  */
 static inline int nand_opcode_8bits(unsigned int command)
 {
 	switch (command) {
 	case NAND_CMD_READID:
 	case NAND_CMD_PARAM:
 	case NAND_CMD_GET_FEATURES:
 	case NAND_CMD_SET_FEATURES:
 		return 1;
 	default:
 		break;
 	}
 	return 0;
 }
 /* return the supported JEDEC features. */
 static inline int jedec_feature(struct nand_chip *chip)
 {
 	return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
 		: 0;
 }
 /* Standard NAND functions from nand_base.c */
 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
 uint8_t nand_read_byte(struct mtd_info *mtd);
 /* get timing characteristics from ONFI timing mode. */
 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
 /* get data interface from ONFI timing mode 0, used after reset. */
 const struct nand_data_interface *nand_get_default_data_interface(void);
 int nand_check_erased_ecc_chunk(void *data, int datalen,
 				void *ecc, int ecclen,
 				void *extraoob, int extraooblen,
 				int threshold);
 int nand_check_ecc_caps(struct nand_chip *chip,
 			const struct nand_ecc_caps *caps, int oobavail);
 int nand_match_ecc_req(struct nand_chip *chip,
 		       const struct nand_ecc_caps *caps,  int oobavail);
 int nand_maximize_ecc(struct nand_chip *chip,
 		      const struct nand_ecc_caps *caps, int oobavail);
 /* Reset and initialize a NAND device */
 int nand_reset(struct nand_chip *chip, int chipnr);
 #endif /* __LINUX_MTD_RAWNAND_H */