Eric Lee / smarc-uboot

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Commit bb1e7cde624d44edf75c1b607fd6c60e038f98dd

Authored by Tom Warren
1 parent 083bbbbe77
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Tegra30: I2C: Enable I2C driver on Cardhu 

Tested all 5 'buses', i2c probe enumerates device addresses on all
but dev 4 (I2C4) [no devices on that bus on my Cardhu].

Note that this uses the extant tegra_i2c.c driver w/o modification.

Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 2 changed files with 57 additions and 0 deletions Inline Diff

include/configs/cardhu.h
Diff comments   View file @ bb1e7cd
File was created 1 /*
2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #ifndef __CONFIG_H
18 #define __CONFIG_H
19
20 #include <asm/sizes.h>
21
22 #include "tegra30-common.h"
23
24 /* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
25 #define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu
26 #define CONFIG_OF_CONTROL
27 #define CONFIG_OF_SEPARATE
28
29 /* High-level configuration options */
30 #define V_PROMPT "Tegra30 (Cardhu) # "
31 #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
32
33 /* Board-specific serial config */
34 #define CONFIG_SERIAL_MULTI
35 #define CONFIG_TEGRA_ENABLE_UARTA
36 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
37
38 #define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
39
40 #define CONFIG_BOARD_EARLY_INIT_F
41
42 /* I2C */
43 #define CONFIG_TEGRA_I2C
44 #define CONFIG_SYS_I2C_INIT_BOARD
45 #define CONFIG_I2C_MULTI_BUS
46 #define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
47 #define CONFIG_SYS_I2C_SPEED 100000
48 #define CONFIG_CMD_I2C
49
50 #define CONFIG_ENV_IS_NOWHERE
51
52 #include "tegra-common-post.h"
53
54 #endif /* __CONFIG_H */
55
include/configs/tegra30-common.h
Diff comments   View file @ bb1e7cd
1 /* 1 /*
2 * (C) Copyright 2010-2012 2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com> 3 * NVIDIA Corporation <www.nvidia.com>
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 #ifndef _TEGRA30_COMMON_H_ 24 #ifndef _TEGRA30_COMMON_H_
25 #define _TEGRA30_COMMON_H_ 25 #define _TEGRA30_COMMON_H_
26 #include "tegra-common.h" 26 #include "tegra-common.h"
27 27
28 /* 28 /*
29 * NS16550 Configuration 29 * NS16550 Configuration
30 */ 30 */
31 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 31 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
32 32
33 /* 33 /*
34 * High Level Configuration Options 34 * High Level Configuration Options
35 */ 35 */
36 #define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */ 36 #define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
37 37
38 /* Environment information, boards can override if required */ 38 /* Environment information, boards can override if required */
39 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ 39 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
40 40
41 /* 41 /*
42 * Miscellaneous configurable options 42 * Miscellaneous configurable options
43 */ 43 */
44 #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ 44 #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
45 #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 45 #define CONFIG_STACKBASE 0x82800000 /* 40MB */
46 46
47 /*----------------------------------------------------------------------- 47 /*-----------------------------------------------------------------------
48 * Physical Memory Map 48 * Physical Memory Map
49 */ 49 */
50 #define CONFIG_SYS_TEXT_BASE 0x8010E000 50 #define CONFIG_SYS_TEXT_BASE 0x8010E000
51 51
52 /* 52 /*
53 * Memory layout for where various images get loaded by boot scripts: 53 * Memory layout for where various images get loaded by boot scripts:
54 * 54 *
55 * scriptaddr can be pretty much anywhere that doesn't conflict with something 55 * scriptaddr can be pretty much anywhere that doesn't conflict with something
56 * else. Put it above BOOTMAPSZ to eliminate conflicts. 56 * else. Put it above BOOTMAPSZ to eliminate conflicts.
57 * 57 *
58 * kernel_addr_r must be within the first 128M of RAM in order for the 58 * kernel_addr_r must be within the first 128M of RAM in order for the
59 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 59 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
60 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 60 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
61 * should not overlap that area, or the kernel will have to copy itself 61 * should not overlap that area, or the kernel will have to copy itself
62 * somewhere else before decompression. Similarly, the address of any other 62 * somewhere else before decompression. Similarly, the address of any other
63 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 63 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
64 * this up to 16M allows for a sizable kernel to be decompressed below the 64 * this up to 16M allows for a sizable kernel to be decompressed below the
65 * compressed load address. 65 * compressed load address.
66 * 66 *
67 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 67 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
68 * the compressed kernel to be up to 16M too. 68 * the compressed kernel to be up to 16M too.
69 * 69 *
70 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 70 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
71 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 71 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
72 */ 72 */
73 #define MEM_LAYOUT_ENV_SETTINGS \ 73 #define MEM_LAYOUT_ENV_SETTINGS \
74 "scriptaddr=0x90000000\0" \ 74 "scriptaddr=0x90000000\0" \
75 "kernel_addr_r=0x81000000\0" \ 75 "kernel_addr_r=0x81000000\0" \
76 "fdt_addr_r=0x82000000\0" \ 76 "fdt_addr_r=0x82000000\0" \
77 "ramdisk_addr_r=0x82100000\0" 77 "ramdisk_addr_r=0x82100000\0"
78 78
79 /* Defines for SPL */ 79 /* Defines for SPL */
80 #define CONFIG_SPL_TEXT_BASE 0x80108000 80 #define CONFIG_SPL_TEXT_BASE 0x80108000
81 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 81 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
82 #define CONFIG_SPL_STACK 0x800ffffc 82 #define CONFIG_SPL_STACK 0x800ffffc
83 83
84 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds" 84 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds"
85 85
86 /* Total I2C ports on Tegra30 */
87 #define TEGRA_I2C_NUM_CONTROLLERS 5
88
86 #endif /* _TEGRA30_COMMON_H_ */ 89 #endif /* _TEGRA30_COMMON_H_ */
87 90