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Commit c155ab74f78794979944e5a49d87776cc460c6c9

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent bdde659516
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

m68k: mcf532x: move CPU type to Kconfig and refactor config.mk 

This commit intends to stop grepping CPU type in
arch/m68k/cpu/mcf532x/config.mk.

Move the CPU type config options from include/configs/*.h
to arch/m68k/Kconfig and refactor the CPU flags select in
arch/m68k/cpu/mcf532x/config.mk.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>

Showing 6 changed files with 29 additions and 25 deletions Inline Diff

1 menu "M68000 architecture" 1 menu "M68000 architecture"
2 depends on M68K 2 depends on M68K
3 3
4 config SYS_ARCH 4 config SYS_ARCH
5 default "m68k" 5 default "m68k"
6 6
7 # processor family 7 # processor family
8 config MCF520x 8 config MCF520x
9 bool 9 bool
10 10
11 config MCF52x2 11 config MCF52x2
12 bool 12 bool
13 13
14 config MCF530x 14 config MCF530x
15 bool 15 bool
16 16
17 config MCF5301x
18 bool
19
20 config MCF532x
21 bool
22
23 config MCF537x
24 bool
25
17 # processor type 26 # processor type
18 config M5208 27 config M5208
19 bool 28 bool
20 select MCF520x 29 select MCF520x
21 30
22 config M5249 31 config M5249
23 bool 32 bool
24 select MCF52x2 33 select MCF52x2
25 34
26 config M5253 35 config M5253
27 bool 36 bool
28 select MCF52x2 37 select MCF52x2
29 38
30 config M5271 39 config M5271
31 bool 40 bool
32 select MCF52x2 41 select MCF52x2
33 42
34 config M5272 43 config M5272
35 bool 44 bool
36 select MCF52x2 45 select MCF52x2
37 46
38 config M5275 47 config M5275
39 bool 48 bool
40 select MCF52x2 49 select MCF52x2
41 50
42 config M5282 51 config M5282
43 bool 52 bool
44 select MCF52x2 53 select MCF52x2
45 54
46 config M5307 55 config M5307
47 bool 56 bool
48 select MCF530x 57 select MCF530x
49 58
59 config M53015
60 bool
61 select MCF5301x
62
63 config M5329
64 bool
65 select MCF532x
66
67 config M5373
68 bool
69 select MCF532x
70 select MCF537x
71
50 choice 72 choice
51 prompt "Target select" 73 prompt "Target select"
52 74
53 config TARGET_M52277EVB 75 config TARGET_M52277EVB
54 bool "Support M52277EVB" 76 bool "Support M52277EVB"
55 77
56 config TARGET_M5235EVB 78 config TARGET_M5235EVB
57 bool "Support M5235EVB" 79 bool "Support M5235EVB"
58 80
59 config TARGET_COBRA5272 81 config TARGET_COBRA5272
60 bool "Support cobra5272" 82 bool "Support cobra5272"
61 select M5272 83 select M5272
62 84
63 config TARGET_EB_CPU5282 85 config TARGET_EB_CPU5282
64 bool "Support eb_cpu5282" 86 bool "Support eb_cpu5282"
65 select M5282 87 select M5282
66 88
67 config TARGET_M5208EVBE 89 config TARGET_M5208EVBE
68 bool "Support M5208EVBE" 90 bool "Support M5208EVBE"
69 select M5208 91 select M5208
70 92
71 config TARGET_M5249EVB 93 config TARGET_M5249EVB
72 bool "Support M5249EVB" 94 bool "Support M5249EVB"
73 select M5249 95 select M5249
74 96
75 config TARGET_M5253DEMO 97 config TARGET_M5253DEMO
76 bool "Support M5253DEMO" 98 bool "Support M5253DEMO"
77 select M5253 99 select M5253
78 100
79 config TARGET_M5253EVBE 101 config TARGET_M5253EVBE
80 bool "Support M5253EVBE" 102 bool "Support M5253EVBE"
81 select M5253 103 select M5253
82 104
83 config TARGET_M5272C3 105 config TARGET_M5272C3
84 bool "Support M5272C3" 106 bool "Support M5272C3"
85 select M5272 107 select M5272
86 108
87 config TARGET_M5275EVB 109 config TARGET_M5275EVB
88 bool "Support M5275EVB" 110 bool "Support M5275EVB"
89 select M5275 111 select M5275
90 112
91 config TARGET_M5282EVB 113 config TARGET_M5282EVB
92 bool "Support M5282EVB" 114 bool "Support M5282EVB"
93 select M5282 115 select M5282
94 116
95 config TARGET_ASTRO_MCF5373L 117 config TARGET_ASTRO_MCF5373L
96 bool "Support astro_mcf5373l" 118 bool "Support astro_mcf5373l"
119 select M5373
97 120
98 config TARGET_M53017EVB 121 config TARGET_M53017EVB
99 bool "Support M53017EVB" 122 bool "Support M53017EVB"
123 select M53015
100 124
101 config TARGET_M5329EVB 125 config TARGET_M5329EVB
102 bool "Support M5329EVB" 126 bool "Support M5329EVB"
127 select M5329
103 128
104 config TARGET_M5373EVB 129 config TARGET_M5373EVB
105 bool "Support M5373EVB" 130 bool "Support M5373EVB"
131 select M5373
106 132
107 config TARGET_M54418TWR 133 config TARGET_M54418TWR
108 bool "Support M54418TWR" 134 bool "Support M54418TWR"
109 135
110 config TARGET_M54451EVB 136 config TARGET_M54451EVB
111 bool "Support M54451EVB" 137 bool "Support M54451EVB"
112 138
113 config TARGET_M54455EVB 139 config TARGET_M54455EVB
114 bool "Support M54455EVB" 140 bool "Support M54455EVB"
115 141
116 config TARGET_M5475EVB 142 config TARGET_M5475EVB
117 bool "Support M5475EVB" 143 bool "Support M5475EVB"
118 144
119 config TARGET_M5485EVB 145 config TARGET_M5485EVB
120 bool "Support M5485EVB" 146 bool "Support M5485EVB"
121 147
122 config TARGET_AMCORE 148 config TARGET_AMCORE
123 bool "Support AMCORE" 149 bool "Support AMCORE"
124 select M5307 150 select M5307
125 151
126 endchoice 152 endchoice
127 153
128 source "board/BuS/eb_cpu5282/Kconfig" 154 source "board/BuS/eb_cpu5282/Kconfig"
129 source "board/astro/mcf5373l/Kconfig" 155 source "board/astro/mcf5373l/Kconfig"
130 source "board/cobra5272/Kconfig" 156 source "board/cobra5272/Kconfig"
131 source "board/freescale/m5208evbe/Kconfig" 157 source "board/freescale/m5208evbe/Kconfig"
132 source "board/freescale/m52277evb/Kconfig" 158 source "board/freescale/m52277evb/Kconfig"
133 source "board/freescale/m5235evb/Kconfig" 159 source "board/freescale/m5235evb/Kconfig"
134 source "board/freescale/m5249evb/Kconfig" 160 source "board/freescale/m5249evb/Kconfig"
135 source "board/freescale/m5253demo/Kconfig" 161 source "board/freescale/m5253demo/Kconfig"
136 source "board/freescale/m5253evbe/Kconfig" 162 source "board/freescale/m5253evbe/Kconfig"
137 source "board/freescale/m5272c3/Kconfig" 163 source "board/freescale/m5272c3/Kconfig"
138 source "board/freescale/m5275evb/Kconfig" 164 source "board/freescale/m5275evb/Kconfig"
139 source "board/freescale/m5282evb/Kconfig" 165 source "board/freescale/m5282evb/Kconfig"
140 source "board/freescale/m53017evb/Kconfig" 166 source "board/freescale/m53017evb/Kconfig"
141 source "board/freescale/m5329evb/Kconfig" 167 source "board/freescale/m5329evb/Kconfig"
142 source "board/freescale/m5373evb/Kconfig" 168 source "board/freescale/m5373evb/Kconfig"
143 source "board/freescale/m54418twr/Kconfig" 169 source "board/freescale/m54418twr/Kconfig"
144 source "board/freescale/m54451evb/Kconfig" 170 source "board/freescale/m54451evb/Kconfig"
145 source "board/freescale/m54455evb/Kconfig" 171 source "board/freescale/m54455evb/Kconfig"
146 source "board/freescale/m547xevb/Kconfig" 172 source "board/freescale/m547xevb/Kconfig"
147 source "board/freescale/m548xevb/Kconfig" 173 source "board/freescale/m548xevb/Kconfig"
148 source "board/sysam/amcore/Kconfig" 174 source "board/sysam/amcore/Kconfig"
149 175
150 endmenu 176 endmenu
151 177
arch/m68k/cpu/mcf532x/config.mk
Diff comments   View file @ c155ab7
1 # 1 #
2 # (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 2 # (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 # 3 #
4 # (C) Copyright 2000-2004 4 # (C) Copyright 2000-2004
5 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 # 6 #
7 # SPDX-License-Identifier: GPL-2.0+ 7 # SPDX-License-Identifier: GPL-2.0+
8 # 8 #
9 9
10 cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h 10 cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC
11 is5301x:=$(shell grep CONFIG_MCF5301x $(cfg)) 11 cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC
12 is532x:=$(shell grep CONFIG_MCF532x $(cfg))
13 12
14 ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x))) 13 PLATFORM_CPPFLAGS += $(cpuflags-y)
15 PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC
16 endif
17 ifneq (,$(findstring CONFIG_MCF532x,$(is532x)))
18 PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
19 endif
20 14
include/configs/M53017EVB.h
Diff comments   View file @ c155ab7
1 /* 1 /*
2 * Configuation settings for the Freescale MCF53017EVB. 2 * Configuation settings for the Freescale MCF53017EVB.
3 * 3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 /* 10 /*
11 * board/config.h - configuration options, board specific 11 * board/config.h - configuration options, board specific
12 */ 12 */
13 13
14 #ifndef _M53017EVB_H 14 #ifndef _M53017EVB_H
15 #define _M53017EVB_H 15 #define _M53017EVB_H
16 16
17 /* 17 /*
18 * High Level Configuration Options 18 * High Level Configuration Options
19 * (easy to change) 19 * (easy to change)
20 */ 20 */
21 #define CONFIG_MCF5301x /* define processor family */
22 #define CONFIG_M53015 /* define processor type */
23 21
24 #define CONFIG_MCFUART 22 #define CONFIG_MCFUART
25 #define CONFIG_SYS_UART_PORT (0) 23 #define CONFIG_SYS_UART_PORT (0)
26 #define CONFIG_BAUDRATE 115200 24 #define CONFIG_BAUDRATE 115200
27 25
28 #undef CONFIG_WATCHDOG 26 #undef CONFIG_WATCHDOG
29 #define CONFIG_WATCHDOG_TIMEOUT 5000 27 #define CONFIG_WATCHDOG_TIMEOUT 5000
30 28
31 /* Command line configuration */ 29 /* Command line configuration */
32 #include <config_cmd_default.h> 30 #include <config_cmd_default.h>
33 31
34 #define CONFIG_CMD_CACHE 32 #define CONFIG_CMD_CACHE
35 #define CONFIG_CMD_DATE 33 #define CONFIG_CMD_DATE
36 #define CONFIG_CMD_ELF 34 #define CONFIG_CMD_ELF
37 #define CONFIG_CMD_FLASH 35 #define CONFIG_CMD_FLASH
38 #undef CONFIG_CMD_I2C 36 #undef CONFIG_CMD_I2C
39 #define CONFIG_CMD_MEMORY 37 #define CONFIG_CMD_MEMORY
40 #define CONFIG_CMD_MISC 38 #define CONFIG_CMD_MISC
41 #define CONFIG_CMD_MII 39 #define CONFIG_CMD_MII
42 #define CONFIG_CMD_NET 40 #define CONFIG_CMD_NET
43 #define CONFIG_CMD_PING 41 #define CONFIG_CMD_PING
44 #define CONFIG_CMD_REGINFO 42 #define CONFIG_CMD_REGINFO
45 43
46 #define CONFIG_SYS_UNIFY_CACHE 44 #define CONFIG_SYS_UNIFY_CACHE
47 45
48 #define CONFIG_MCFFEC 46 #define CONFIG_MCFFEC
49 #ifdef CONFIG_MCFFEC 47 #ifdef CONFIG_MCFFEC
50 # define CONFIG_MII 1 48 # define CONFIG_MII 1
51 # define CONFIG_MII_INIT 1 49 # define CONFIG_MII_INIT 1
52 # define CONFIG_SYS_DISCOVER_PHY 50 # define CONFIG_SYS_DISCOVER_PHY
53 # define CONFIG_SYS_RX_ETH_BUFFER 8 51 # define CONFIG_SYS_RX_ETH_BUFFER 8
54 # define CONFIG_SYS_TX_ETH_BUFFER 8 52 # define CONFIG_SYS_TX_ETH_BUFFER 8
55 # define CONFIG_SYS_FEC_BUF_USE_SRAM 53 # define CONFIG_SYS_FEC_BUF_USE_SRAM
56 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57 # define CONFIG_HAS_ETH1 55 # define CONFIG_HAS_ETH1
58 56
59 # define CONFIG_SYS_FEC0_PINMUX 0 57 # define CONFIG_SYS_FEC0_PINMUX 0
60 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 58 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
61 # define CONFIG_SYS_FEC1_PINMUX 0 59 # define CONFIG_SYS_FEC1_PINMUX 0
62 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 60 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
63 # define MCFFEC_TOUT_LOOP 50000 61 # define MCFFEC_TOUT_LOOP 50000
64 62
65 # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2" 63 # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2"
66 64
67 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 65 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
68 # ifndef CONFIG_SYS_DISCOVER_PHY 66 # ifndef CONFIG_SYS_DISCOVER_PHY
69 # define FECDUPLEX FULL 67 # define FECDUPLEX FULL
70 # define FECSPEED _100BASET 68 # define FECSPEED _100BASET
71 # else 69 # else
72 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 70 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
73 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 71 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
74 # endif 72 # endif
75 # endif /* CONFIG_SYS_DISCOVER_PHY */ 73 # endif /* CONFIG_SYS_DISCOVER_PHY */
76 #endif 74 #endif
77 75
78 #define CONFIG_MCFRTC 76 #define CONFIG_MCFRTC
79 #undef RTC_DEBUG 77 #undef RTC_DEBUG
80 #define CONFIG_SYS_RTC_CNT (0x8000) 78 #define CONFIG_SYS_RTC_CNT (0x8000)
81 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) 79 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
82 80
83 /* Timer */ 81 /* Timer */
84 #define CONFIG_MCFTMR 82 #define CONFIG_MCFTMR
85 #undef CONFIG_MCFPIT 83 #undef CONFIG_MCFPIT
86 84
87 /* I2C */ 85 /* I2C */
88 #define CONFIG_SYS_I2C 86 #define CONFIG_SYS_I2C
89 #define CONFIG_SYS_I2C_FSL 87 #define CONFIG_SYS_I2C_FSL
90 #define CONFIG_SYS_FSL_I2C_SPEED 80000 88 #define CONFIG_SYS_FSL_I2C_SPEED 80000
91 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 89 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
92 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 90 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
93 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 91 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
94 92
95 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 93 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
96 #define CONFIG_UDP_CHECKSUM 94 #define CONFIG_UDP_CHECKSUM
97 95
98 #ifdef CONFIG_MCFFEC 96 #ifdef CONFIG_MCFFEC
99 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 97 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
100 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 98 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
101 # define CONFIG_IPADDR 192.162.1.2 99 # define CONFIG_IPADDR 192.162.1.2
102 # define CONFIG_NETMASK 255.255.255.0 100 # define CONFIG_NETMASK 255.255.255.0
103 # define CONFIG_SERVERIP 192.162.1.1 101 # define CONFIG_SERVERIP 192.162.1.1
104 # define CONFIG_GATEWAYIP 192.162.1.1 102 # define CONFIG_GATEWAYIP 192.162.1.1
105 # define CONFIG_OVERWRITE_ETHADDR_ONCE 103 # define CONFIG_OVERWRITE_ETHADDR_ONCE
106 #endif /* FEC_ENET */ 104 #endif /* FEC_ENET */
107 105
108 #define CONFIG_HOSTNAME M53017 106 #define CONFIG_HOSTNAME M53017
109 #define CONFIG_EXTRA_ENV_SETTINGS \ 107 #define CONFIG_EXTRA_ENV_SETTINGS \
110 "netdev=eth0\0" \ 108 "netdev=eth0\0" \
111 "loadaddr=40010000\0" \ 109 "loadaddr=40010000\0" \
112 "u-boot=u-boot.bin\0" \ 110 "u-boot=u-boot.bin\0" \
113 "load=tftp ${loadaddr) ${u-boot}\0" \ 111 "load=tftp ${loadaddr) ${u-boot}\0" \
114 "upd=run load; run prog\0" \ 112 "upd=run load; run prog\0" \
115 "prog=prot off 0 3ffff;" \ 113 "prog=prot off 0 3ffff;" \
116 "era 0 3ffff;" \ 114 "era 0 3ffff;" \
117 "cp.b ${loadaddr} 0 ${filesize};" \ 115 "cp.b ${loadaddr} 0 ${filesize};" \
118 "save\0" \ 116 "save\0" \
119 "" 117 ""
120 118
121 #define CONFIG_PRAM 512 /* 512 KB */ 119 #define CONFIG_PRAM 512 /* 512 KB */
122 #define CONFIG_SYS_PROMPT "-> " 120 #define CONFIG_SYS_PROMPT "-> "
123 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 121 #define CONFIG_SYS_LONGHELP /* undef to save memory */
124 122
125 #ifdef CONFIG_CMD_KGDB 123 #ifdef CONFIG_CMD_KGDB
126 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 124 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
127 #else 125 #else
128 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 126 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
129 #endif 127 #endif
130 128
131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
132 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 130 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
134 #define CONFIG_SYS_LOAD_ADDR 0x40010000 132 #define CONFIG_SYS_LOAD_ADDR 0x40010000
135 133
136 #define CONFIG_SYS_CLK 80000000 134 #define CONFIG_SYS_CLK 80000000
137 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 135 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
138 136
139 #define CONFIG_SYS_MBAR 0xFC000000 137 #define CONFIG_SYS_MBAR 0xFC000000
140 138
141 /* 139 /*
142 * Low Level Configuration Settings 140 * Low Level Configuration Settings
143 * (address mappings, register initial values, etc.) 141 * (address mappings, register initial values, etc.)
144 * You should know what you are doing if you make changes here. 142 * You should know what you are doing if you make changes here.
145 */ 143 */
146 /* 144 /*
147 * Definitions for initial stack pointer and data area (in DPRAM) 145 * Definitions for initial stack pointer and data area (in DPRAM)
148 */ 146 */
149 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 147 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
150 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ 148 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
151 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 149 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
152 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 150 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
153 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 151 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
154 152
155 /* 153 /*
156 * Start addresses for the final memory configuration 154 * Start addresses for the final memory configuration
157 * (Set up by the startup code) 155 * (Set up by the startup code)
158 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 156 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
159 */ 157 */
160 #define CONFIG_SYS_SDRAM_BASE 0x40000000 158 #define CONFIG_SYS_SDRAM_BASE 0x40000000
161 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 159 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
162 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 160 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
163 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 161 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
164 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 162 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
165 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 163 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
166 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 164 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
167 165
168 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 166 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
169 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 167 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
170 168
171 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 169 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
172 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 170 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
173 171
174 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 172 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
175 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 173 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
176 174
177 /* 175 /*
178 * For booting Linux, the board info and command line data 176 * For booting Linux, the board info and command line data
179 * have to be in the first 8 MB of memory, since this is 177 * have to be in the first 8 MB of memory, since this is
180 * the maximum mapped by the Linux kernel during initialization ?? 178 * the maximum mapped by the Linux kernel during initialization ??
181 */ 179 */
182 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 180 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
183 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 181 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
184 182
185 /*----------------------------------------------------------------------- 183 /*-----------------------------------------------------------------------
186 * FLASH organization 184 * FLASH organization
187 */ 185 */
188 #define CONFIG_SYS_FLASH_CFI 186 #define CONFIG_SYS_FLASH_CFI
189 #ifdef CONFIG_SYS_FLASH_CFI 187 #ifdef CONFIG_SYS_FLASH_CFI
190 # define CONFIG_FLASH_CFI_DRIVER 1 188 # define CONFIG_FLASH_CFI_DRIVER 1
191 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 189 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
192 # define CONFIG_FLASH_SPANSION_S29WS_N 1 190 # define CONFIG_FLASH_SPANSION_S29WS_N 1
193 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 191 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
194 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 192 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
195 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 193 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
196 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 194 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
197 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 195 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
198 #endif 196 #endif
199 197
200 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 198 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
201 199
202 /* Configuration for environment 200 /* Configuration for environment
203 * Environment is embedded in u-boot in the second sector of the flash 201 * Environment is embedded in u-boot in the second sector of the flash
204 */ 202 */
205 #define CONFIG_ENV_OFFSET 0x8000 203 #define CONFIG_ENV_OFFSET 0x8000
206 #define CONFIG_ENV_SIZE 0x1000 204 #define CONFIG_ENV_SIZE 0x1000
207 #define CONFIG_ENV_SECT_SIZE 0x8000 205 #define CONFIG_ENV_SECT_SIZE 0x8000
208 #define CONFIG_ENV_IS_IN_FLASH 1 206 #define CONFIG_ENV_IS_IN_FLASH 1
209 207
210 /*----------------------------------------------------------------------- 208 /*-----------------------------------------------------------------------
211 * Cache Configuration 209 * Cache Configuration
212 */ 210 */
213 #define CONFIG_SYS_CACHELINE_SIZE 16 211 #define CONFIG_SYS_CACHELINE_SIZE 16
214 212
215 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 213 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
216 CONFIG_SYS_INIT_RAM_SIZE - 8) 214 CONFIG_SYS_INIT_RAM_SIZE - 8)
217 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 215 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
218 CONFIG_SYS_INIT_RAM_SIZE - 4) 216 CONFIG_SYS_INIT_RAM_SIZE - 4)
219 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 217 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
220 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 218 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
221 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 219 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
222 CF_ACR_EN | CF_ACR_SM_ALL) 220 CF_ACR_EN | CF_ACR_SM_ALL)
223 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 221 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
224 CF_CACR_DCM_P) 222 CF_CACR_DCM_P)
225 223
226 /*----------------------------------------------------------------------- 224 /*-----------------------------------------------------------------------
227 * Chipselect bank definitions 225 * Chipselect bank definitions
228 */ 226 */
229 /* 227 /*
230 * CS0 - NOR Flash 228 * CS0 - NOR Flash
231 * CS1 - Ext SRAM 229 * CS1 - Ext SRAM
232 * CS2 - Available 230 * CS2 - Available
233 * CS3 - Available 231 * CS3 - Available
234 * CS4 - Available 232 * CS4 - Available
235 * CS5 - Available 233 * CS5 - Available
236 */ 234 */
237 #define CONFIG_SYS_CS0_BASE 0 235 #define CONFIG_SYS_CS0_BASE 0
238 #define CONFIG_SYS_CS0_MASK 0x00FF0001 236 #define CONFIG_SYS_CS0_MASK 0x00FF0001
239 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 237 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
240 238
241 #define CONFIG_SYS_CS1_BASE 0xC0000000 239 #define CONFIG_SYS_CS1_BASE 0xC0000000
242 #define CONFIG_SYS_CS1_MASK 0x00070001 240 #define CONFIG_SYS_CS1_MASK 0x00070001
243 #define CONFIG_SYS_CS1_CTRL 0x00001FA0 241 #define CONFIG_SYS_CS1_CTRL 0x00001FA0
244 242
245 #endif /* _M53017EVB_H */ 243 #endif /* _M53017EVB_H */
246 244
include/configs/M5329EVB.h
Diff comments   View file @ c155ab7
1 /* 1 /*
2 * Configuation settings for the Freescale MCF5329 FireEngine board. 2 * Configuation settings for the Freescale MCF5329 FireEngine board.
3 * 3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 /* 10 /*
11 * board/config.h - configuration options, board specific 11 * board/config.h - configuration options, board specific
12 */ 12 */
13 13
14 #ifndef _M5329EVB_H 14 #ifndef _M5329EVB_H
15 #define _M5329EVB_H 15 #define _M5329EVB_H
16 16
17 /* 17 /*
18 * High Level Configuration Options 18 * High Level Configuration Options
19 * (easy to change) 19 * (easy to change)
20 */ 20 */
21 #define CONFIG_MCF532x /* define processor family */
22 #define CONFIG_M5329 /* define processor type */
23 21
24 #define CONFIG_MCFUART 22 #define CONFIG_MCFUART
25 #define CONFIG_SYS_UART_PORT (0) 23 #define CONFIG_SYS_UART_PORT (0)
26 #define CONFIG_BAUDRATE 115200 24 #define CONFIG_BAUDRATE 115200
27 25
28 #undef CONFIG_WATCHDOG 26 #undef CONFIG_WATCHDOG
29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
30 28
31 /* Command line configuration */ 29 /* Command line configuration */
32 #include <config_cmd_default.h> 30 #include <config_cmd_default.h>
33 31
34 #define CONFIG_CMD_CACHE 32 #define CONFIG_CMD_CACHE
35 #define CONFIG_CMD_DATE 33 #define CONFIG_CMD_DATE
36 #define CONFIG_CMD_ELF 34 #define CONFIG_CMD_ELF
37 #define CONFIG_CMD_FLASH 35 #define CONFIG_CMD_FLASH
38 #define CONFIG_CMD_I2C 36 #define CONFIG_CMD_I2C
39 #define CONFIG_CMD_MEMORY 37 #define CONFIG_CMD_MEMORY
40 #define CONFIG_CMD_MISC 38 #define CONFIG_CMD_MISC
41 #define CONFIG_CMD_MII 39 #define CONFIG_CMD_MII
42 #define CONFIG_CMD_NET 40 #define CONFIG_CMD_NET
43 #define CONFIG_CMD_PING 41 #define CONFIG_CMD_PING
44 #define CONFIG_CMD_REGINFO 42 #define CONFIG_CMD_REGINFO
45 43
46 #ifdef CONFIG_NANDFLASH_SIZE 44 #ifdef CONFIG_NANDFLASH_SIZE
47 # define CONFIG_CMD_NAND 45 # define CONFIG_CMD_NAND
48 #endif 46 #endif
49 47
50 #define CONFIG_SYS_UNIFY_CACHE 48 #define CONFIG_SYS_UNIFY_CACHE
51 49
52 #define CONFIG_MCFFEC 50 #define CONFIG_MCFFEC
53 #ifdef CONFIG_MCFFEC 51 #ifdef CONFIG_MCFFEC
54 # define CONFIG_MII 1 52 # define CONFIG_MII 1
55 # define CONFIG_MII_INIT 1 53 # define CONFIG_MII_INIT 1
56 # define CONFIG_SYS_DISCOVER_PHY 54 # define CONFIG_SYS_DISCOVER_PHY
57 # define CONFIG_SYS_RX_ETH_BUFFER 8 55 # define CONFIG_SYS_RX_ETH_BUFFER 8
58 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
59 57
60 # define CONFIG_SYS_FEC0_PINMUX 0 58 # define CONFIG_SYS_FEC0_PINMUX 0
61 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 59 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
62 # define MCFFEC_TOUT_LOOP 50000 60 # define MCFFEC_TOUT_LOOP 50000
63 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 61 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
64 # ifndef CONFIG_SYS_DISCOVER_PHY 62 # ifndef CONFIG_SYS_DISCOVER_PHY
65 # define FECDUPLEX FULL 63 # define FECDUPLEX FULL
66 # define FECSPEED _100BASET 64 # define FECSPEED _100BASET
67 # else 65 # else
68 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
69 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 67 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
70 # endif 68 # endif
71 # endif /* CONFIG_SYS_DISCOVER_PHY */ 69 # endif /* CONFIG_SYS_DISCOVER_PHY */
72 #endif 70 #endif
73 71
74 #define CONFIG_MCFRTC 72 #define CONFIG_MCFRTC
75 #undef RTC_DEBUG 73 #undef RTC_DEBUG
76 74
77 /* Timer */ 75 /* Timer */
78 #define CONFIG_MCFTMR 76 #define CONFIG_MCFTMR
79 #undef CONFIG_MCFPIT 77 #undef CONFIG_MCFPIT
80 78
81 /* I2C */ 79 /* I2C */
82 #define CONFIG_SYS_I2C 80 #define CONFIG_SYS_I2C
83 #define CONFIG_SYS_I2C_FSL 81 #define CONFIG_SYS_I2C_FSL
84 #define CONFIG_SYS_FSL_I2C_SPEED 80000 82 #define CONFIG_SYS_FSL_I2C_SPEED 80000
85 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 83 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
86 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 84 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
87 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 85 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
88 86
89 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 87 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
90 #define CONFIG_UDP_CHECKSUM 88 #define CONFIG_UDP_CHECKSUM
91 89
92 #ifdef CONFIG_MCFFEC 90 #ifdef CONFIG_MCFFEC
93 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 91 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
94 # define CONFIG_IPADDR 192.162.1.2 92 # define CONFIG_IPADDR 192.162.1.2
95 # define CONFIG_NETMASK 255.255.255.0 93 # define CONFIG_NETMASK 255.255.255.0
96 # define CONFIG_SERVERIP 192.162.1.1 94 # define CONFIG_SERVERIP 192.162.1.1
97 # define CONFIG_GATEWAYIP 192.162.1.1 95 # define CONFIG_GATEWAYIP 192.162.1.1
98 # define CONFIG_OVERWRITE_ETHADDR_ONCE 96 # define CONFIG_OVERWRITE_ETHADDR_ONCE
99 #endif /* FEC_ENET */ 97 #endif /* FEC_ENET */
100 98
101 #define CONFIG_HOSTNAME M5329EVB 99 #define CONFIG_HOSTNAME M5329EVB
102 #define CONFIG_EXTRA_ENV_SETTINGS \ 100 #define CONFIG_EXTRA_ENV_SETTINGS \
103 "netdev=eth0\0" \ 101 "netdev=eth0\0" \
104 "loadaddr=40010000\0" \ 102 "loadaddr=40010000\0" \
105 "u-boot=u-boot.bin\0" \ 103 "u-boot=u-boot.bin\0" \
106 "load=tftp ${loadaddr) ${u-boot}\0" \ 104 "load=tftp ${loadaddr) ${u-boot}\0" \
107 "upd=run load; run prog\0" \ 105 "upd=run load; run prog\0" \
108 "prog=prot off 0 3ffff;" \ 106 "prog=prot off 0 3ffff;" \
109 "era 0 3ffff;" \ 107 "era 0 3ffff;" \
110 "cp.b ${loadaddr} 0 ${filesize};" \ 108 "cp.b ${loadaddr} 0 ${filesize};" \
111 "save\0" \ 109 "save\0" \
112 "" 110 ""
113 111
114 #define CONFIG_PRAM 512 /* 512 KB */ 112 #define CONFIG_PRAM 512 /* 512 KB */
115 #define CONFIG_SYS_PROMPT "-> " 113 #define CONFIG_SYS_PROMPT "-> "
116 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 114 #define CONFIG_SYS_LONGHELP /* undef to save memory */
117 115
118 #ifdef CONFIG_CMD_KGDB 116 #ifdef CONFIG_CMD_KGDB
119 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 117 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
120 #else 118 #else
121 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 119 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
122 #endif 120 #endif
123 121
124 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 122 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 123 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 124 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
127 #define CONFIG_SYS_LOAD_ADDR 0x40010000 125 #define CONFIG_SYS_LOAD_ADDR 0x40010000
128 126
129 #define CONFIG_SYS_CLK 80000000 127 #define CONFIG_SYS_CLK 80000000
130 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 128 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
131 129
132 #define CONFIG_SYS_MBAR 0xFC000000 130 #define CONFIG_SYS_MBAR 0xFC000000
133 131
134 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 132 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
135 133
136 /* 134 /*
137 * Low Level Configuration Settings 135 * Low Level Configuration Settings
138 * (address mappings, register initial values, etc.) 136 * (address mappings, register initial values, etc.)
139 * You should know what you are doing if you make changes here. 137 * You should know what you are doing if you make changes here.
140 */ 138 */
141 /*----------------------------------------------------------------------- 139 /*-----------------------------------------------------------------------
142 * Definitions for initial stack pointer and data area (in DPRAM) 140 * Definitions for initial stack pointer and data area (in DPRAM)
143 */ 141 */
144 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 142 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
145 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 143 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
146 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 144 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
147 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 145 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
148 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 146 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
149 147
150 /*----------------------------------------------------------------------- 148 /*-----------------------------------------------------------------------
151 * Start addresses for the final memory configuration 149 * Start addresses for the final memory configuration
152 * (Set up by the startup code) 150 * (Set up by the startup code)
153 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
154 */ 152 */
155 #define CONFIG_SYS_SDRAM_BASE 0x40000000 153 #define CONFIG_SYS_SDRAM_BASE 0x40000000
156 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 154 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
157 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 155 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
158 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 156 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
159 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 157 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
160 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 158 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
161 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 159 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
162 160
163 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 161 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
164 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 162 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
165 163
166 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 164 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
167 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 165 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
168 166
169 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 167 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
170 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 168 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
171 169
172 /* 170 /*
173 * For booting Linux, the board info and command line data 171 * For booting Linux, the board info and command line data
174 * have to be in the first 8 MB of memory, since this is 172 * have to be in the first 8 MB of memory, since this is
175 * the maximum mapped by the Linux kernel during initialization ?? 173 * the maximum mapped by the Linux kernel during initialization ??
176 */ 174 */
177 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 175 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
178 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 176 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
179 177
180 /*----------------------------------------------------------------------- 178 /*-----------------------------------------------------------------------
181 * FLASH organization 179 * FLASH organization
182 */ 180 */
183 #define CONFIG_SYS_FLASH_CFI 181 #define CONFIG_SYS_FLASH_CFI
184 #ifdef CONFIG_SYS_FLASH_CFI 182 #ifdef CONFIG_SYS_FLASH_CFI
185 # define CONFIG_FLASH_CFI_DRIVER 1 183 # define CONFIG_FLASH_CFI_DRIVER 1
186 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 184 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
187 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 185 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
188 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 186 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
189 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 187 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
190 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 188 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
191 #endif 189 #endif
192 190
193 #ifdef CONFIG_NANDFLASH_SIZE 191 #ifdef CONFIG_NANDFLASH_SIZE
194 # define CONFIG_SYS_MAX_NAND_DEVICE 1 192 # define CONFIG_SYS_MAX_NAND_DEVICE 1
195 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 193 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
196 # define CONFIG_SYS_NAND_SIZE 1 194 # define CONFIG_SYS_NAND_SIZE 1
197 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 195 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
198 # define NAND_ALLOW_ERASE_ALL 1 196 # define NAND_ALLOW_ERASE_ALL 1
199 # define CONFIG_JFFS2_NAND 1 197 # define CONFIG_JFFS2_NAND 1
200 # define CONFIG_JFFS2_DEV "nand0" 198 # define CONFIG_JFFS2_DEV "nand0"
201 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 199 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
202 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 200 # define CONFIG_JFFS2_PART_OFFSET 0x00000000
203 #endif 201 #endif
204 202
205 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 203 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
206 204
207 /* Configuration for environment 205 /* Configuration for environment
208 * Environment is embedded in u-boot in the second sector of the flash 206 * Environment is embedded in u-boot in the second sector of the flash
209 */ 207 */
210 #define CONFIG_ENV_OFFSET 0x4000 208 #define CONFIG_ENV_OFFSET 0x4000
211 #define CONFIG_ENV_SECT_SIZE 0x2000 209 #define CONFIG_ENV_SECT_SIZE 0x2000
212 #define CONFIG_ENV_IS_IN_FLASH 1 210 #define CONFIG_ENV_IS_IN_FLASH 1
213 211
214 /*----------------------------------------------------------------------- 212 /*-----------------------------------------------------------------------
215 * Cache Configuration 213 * Cache Configuration
216 */ 214 */
217 #define CONFIG_SYS_CACHELINE_SIZE 16 215 #define CONFIG_SYS_CACHELINE_SIZE 16
218 216
219 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 217 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
220 CONFIG_SYS_INIT_RAM_SIZE - 8) 218 CONFIG_SYS_INIT_RAM_SIZE - 8)
221 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 219 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
222 CONFIG_SYS_INIT_RAM_SIZE - 4) 220 CONFIG_SYS_INIT_RAM_SIZE - 4)
223 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 221 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
224 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 222 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
225 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 223 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
226 CF_ACR_EN | CF_ACR_SM_ALL) 224 CF_ACR_EN | CF_ACR_SM_ALL)
227 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 225 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
228 CF_CACR_DCM_P) 226 CF_CACR_DCM_P)
229 227
230 /*----------------------------------------------------------------------- 228 /*-----------------------------------------------------------------------
231 * Chipselect bank definitions 229 * Chipselect bank definitions
232 */ 230 */
233 /* 231 /*
234 * CS0 - NOR Flash 1, 2, 4, or 8MB 232 * CS0 - NOR Flash 1, 2, 4, or 8MB
235 * CS1 - CompactFlash and registers 233 * CS1 - CompactFlash and registers
236 * CS2 - NAND Flash 16, 32, or 64MB 234 * CS2 - NAND Flash 16, 32, or 64MB
237 * CS3 - Available 235 * CS3 - Available
238 * CS4 - Available 236 * CS4 - Available
239 * CS5 - Available 237 * CS5 - Available
240 */ 238 */
241 #define CONFIG_SYS_CS0_BASE 0 239 #define CONFIG_SYS_CS0_BASE 0
242 #define CONFIG_SYS_CS0_MASK 0x007f0001 240 #define CONFIG_SYS_CS0_MASK 0x007f0001
243 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 241 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
244 242
245 #define CONFIG_SYS_CS1_BASE 0x10000000 243 #define CONFIG_SYS_CS1_BASE 0x10000000
246 #define CONFIG_SYS_CS1_MASK 0x001f0001 244 #define CONFIG_SYS_CS1_MASK 0x001f0001
247 #define CONFIG_SYS_CS1_CTRL 0x002A3780 245 #define CONFIG_SYS_CS1_CTRL 0x002A3780
248 246
249 #ifdef CONFIG_NANDFLASH_SIZE 247 #ifdef CONFIG_NANDFLASH_SIZE
250 #define CONFIG_SYS_CS2_BASE 0x20000000 248 #define CONFIG_SYS_CS2_BASE 0x20000000
251 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 249 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
252 #define CONFIG_SYS_CS2_CTRL 0x00001f60 250 #define CONFIG_SYS_CS2_CTRL 0x00001f60
253 #endif 251 #endif
254 252
255 #endif /* _M5329EVB_H */ 253 #endif /* _M5329EVB_H */
256 254
include/configs/M5373EVB.h
Diff comments   View file @ c155ab7
1 /* 1 /*
2 * Configuation settings for the Freescale MCF5373 FireEngine board. 2 * Configuation settings for the Freescale MCF5373 FireEngine board.
3 * 3 *
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 /* 10 /*
11 * board/config.h - configuration options, board specific 11 * board/config.h - configuration options, board specific
12 */ 12 */
13 13
14 #ifndef _M5373EVB_H 14 #ifndef _M5373EVB_H
15 #define _M5373EVB_H 15 #define _M5373EVB_H
16 16
17 /* 17 /*
18 * High Level Configuration Options 18 * High Level Configuration Options
19 * (easy to change) 19 * (easy to change)
20 */ 20 */
21 #define CONFIG_MCF532x /* define processor family */
22 #define CONFIG_M5373 /* define processor type */
23 21
24 #define CONFIG_MCFUART 22 #define CONFIG_MCFUART
25 #define CONFIG_SYS_UART_PORT (0) 23 #define CONFIG_SYS_UART_PORT (0)
26 #define CONFIG_BAUDRATE 115200 24 #define CONFIG_BAUDRATE 115200
27 25
28 #undef CONFIG_WATCHDOG 26 #undef CONFIG_WATCHDOG
29 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 27 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
30 28
31 /* Command line configuration */ 29 /* Command line configuration */
32 #include <config_cmd_default.h> 30 #include <config_cmd_default.h>
33 31
34 #define CONFIG_CMD_CACHE 32 #define CONFIG_CMD_CACHE
35 #define CONFIG_CMD_DATE 33 #define CONFIG_CMD_DATE
36 #define CONFIG_CMD_ELF 34 #define CONFIG_CMD_ELF
37 #define CONFIG_CMD_FLASH 35 #define CONFIG_CMD_FLASH
38 #define CONFIG_CMD_I2C 36 #define CONFIG_CMD_I2C
39 #define CONFIG_CMD_MEMORY 37 #define CONFIG_CMD_MEMORY
40 #define CONFIG_CMD_MISC 38 #define CONFIG_CMD_MISC
41 #define CONFIG_CMD_MII 39 #define CONFIG_CMD_MII
42 #define CONFIG_CMD_NET 40 #define CONFIG_CMD_NET
43 #define CONFIG_CMD_PING 41 #define CONFIG_CMD_PING
44 #define CONFIG_CMD_REGINFO 42 #define CONFIG_CMD_REGINFO
45 43
46 #ifdef CONFIG_NANDFLASH_SIZE 44 #ifdef CONFIG_NANDFLASH_SIZE
47 # define CONFIG_CMD_NAND 45 # define CONFIG_CMD_NAND
48 #endif 46 #endif
49 47
50 #define CONFIG_SYS_UNIFY_CACHE 48 #define CONFIG_SYS_UNIFY_CACHE
51 49
52 #define CONFIG_MCFFEC 50 #define CONFIG_MCFFEC
53 #ifdef CONFIG_MCFFEC 51 #ifdef CONFIG_MCFFEC
54 # define CONFIG_MII 1 52 # define CONFIG_MII 1
55 # define CONFIG_MII_INIT 1 53 # define CONFIG_MII_INIT 1
56 # define CONFIG_SYS_DISCOVER_PHY 54 # define CONFIG_SYS_DISCOVER_PHY
57 # define CONFIG_SYS_RX_ETH_BUFFER 8 55 # define CONFIG_SYS_RX_ETH_BUFFER 8
58 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
59 57
60 # define CONFIG_SYS_FEC0_PINMUX 0 58 # define CONFIG_SYS_FEC0_PINMUX 0
61 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 59 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
62 # define MCFFEC_TOUT_LOOP 50000 60 # define MCFFEC_TOUT_LOOP 50000
63 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 61 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
64 # ifndef CONFIG_SYS_DISCOVER_PHY 62 # ifndef CONFIG_SYS_DISCOVER_PHY
65 # define FECDUPLEX FULL 63 # define FECDUPLEX FULL
66 # define FECSPEED _100BASET 64 # define FECSPEED _100BASET
67 # else 65 # else
68 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
69 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 67 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
70 # endif 68 # endif
71 # endif /* CONFIG_SYS_DISCOVER_PHY */ 69 # endif /* CONFIG_SYS_DISCOVER_PHY */
72 #endif 70 #endif
73 71
74 #define CONFIG_MCFRTC 72 #define CONFIG_MCFRTC
75 #undef RTC_DEBUG 73 #undef RTC_DEBUG
76 74
77 /* Timer */ 75 /* Timer */
78 #define CONFIG_MCFTMR 76 #define CONFIG_MCFTMR
79 #undef CONFIG_MCFPIT 77 #undef CONFIG_MCFPIT
80 78
81 /* I2C */ 79 /* I2C */
82 #define CONFIG_SYS_I2C 80 #define CONFIG_SYS_I2C
83 #define CONFIG_SYS_I2C_FSL 81 #define CONFIG_SYS_I2C_FSL
84 #define CONFIG_SYS_FSL_I2C_SPEED 80000 82 #define CONFIG_SYS_FSL_I2C_SPEED 80000
85 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 83 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
86 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 84 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
87 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 85 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
88 86
89 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 87 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
90 #define CONFIG_UDP_CHECKSUM 88 #define CONFIG_UDP_CHECKSUM
91 89
92 #ifdef CONFIG_MCFFEC 90 #ifdef CONFIG_MCFFEC
93 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 91 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
94 # define CONFIG_IPADDR 192.162.1.2 92 # define CONFIG_IPADDR 192.162.1.2
95 # define CONFIG_NETMASK 255.255.255.0 93 # define CONFIG_NETMASK 255.255.255.0
96 # define CONFIG_SERVERIP 192.162.1.1 94 # define CONFIG_SERVERIP 192.162.1.1
97 # define CONFIG_GATEWAYIP 192.162.1.1 95 # define CONFIG_GATEWAYIP 192.162.1.1
98 # define CONFIG_OVERWRITE_ETHADDR_ONCE 96 # define CONFIG_OVERWRITE_ETHADDR_ONCE
99 #endif /* FEC_ENET */ 97 #endif /* FEC_ENET */
100 98
101 #define CONFIG_HOSTNAME M5373EVB 99 #define CONFIG_HOSTNAME M5373EVB
102 #define CONFIG_EXTRA_ENV_SETTINGS \ 100 #define CONFIG_EXTRA_ENV_SETTINGS \
103 "netdev=eth0\0" \ 101 "netdev=eth0\0" \
104 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 102 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
105 "u-boot=u-boot.bin\0" \ 103 "u-boot=u-boot.bin\0" \
106 "load=tftp ${loadaddr) ${u-boot}\0" \ 104 "load=tftp ${loadaddr) ${u-boot}\0" \
107 "upd=run load; run prog\0" \ 105 "upd=run load; run prog\0" \
108 "prog=prot off 0 3ffff;" \ 106 "prog=prot off 0 3ffff;" \
109 "era 0 3ffff;" \ 107 "era 0 3ffff;" \
110 "cp.b ${loadaddr} 0 ${filesize};" \ 108 "cp.b ${loadaddr} 0 ${filesize};" \
111 "save\0" \ 109 "save\0" \
112 "" 110 ""
113 111
114 #define CONFIG_PRAM 512 /* 512 KB */ 112 #define CONFIG_PRAM 512 /* 512 KB */
115 #define CONFIG_SYS_PROMPT "-> " 113 #define CONFIG_SYS_PROMPT "-> "
116 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 114 #define CONFIG_SYS_LONGHELP /* undef to save memory */
117 115
118 #ifdef CONFIG_CMD_KGDB 116 #ifdef CONFIG_CMD_KGDB
119 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 117 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
120 #else 118 #else
121 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 119 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
122 #endif 120 #endif
123 121
124 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 122 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 123 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 124 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
127 #define CONFIG_SYS_LOAD_ADDR 0x40010000 125 #define CONFIG_SYS_LOAD_ADDR 0x40010000
128 126
129 #define CONFIG_SYS_CLK 80000000 127 #define CONFIG_SYS_CLK 80000000
130 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 128 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
131 129
132 #define CONFIG_SYS_MBAR 0xFC000000 130 #define CONFIG_SYS_MBAR 0xFC000000
133 131
134 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 132 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
135 133
136 /* 134 /*
137 * Low Level Configuration Settings 135 * Low Level Configuration Settings
138 * (address mappings, register initial values, etc.) 136 * (address mappings, register initial values, etc.)
139 * You should know what you are doing if you make changes here. 137 * You should know what you are doing if you make changes here.
140 */ 138 */
141 /*----------------------------------------------------------------------- 139 /*-----------------------------------------------------------------------
142 * Definitions for initial stack pointer and data area (in DPRAM) 140 * Definitions for initial stack pointer and data area (in DPRAM)
143 */ 141 */
144 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 142 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
145 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 143 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
146 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 144 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
147 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 145 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
148 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 146 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
149 147
150 /*----------------------------------------------------------------------- 148 /*-----------------------------------------------------------------------
151 * Start addresses for the final memory configuration 149 * Start addresses for the final memory configuration
152 * (Set up by the startup code) 150 * (Set up by the startup code)
153 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
154 */ 152 */
155 #define CONFIG_SYS_SDRAM_BASE 0x40000000 153 #define CONFIG_SYS_SDRAM_BASE 0x40000000
156 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 154 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
157 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 155 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
158 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 156 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
159 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 157 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
160 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 158 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
161 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 159 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
162 160
163 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 161 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
164 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 162 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
165 163
166 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 164 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
167 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 165 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
168 166
169 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 167 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
170 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 168 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
171 169
172 /* 170 /*
173 * For booting Linux, the board info and command line data 171 * For booting Linux, the board info and command line data
174 * have to be in the first 8 MB of memory, since this is 172 * have to be in the first 8 MB of memory, since this is
175 * the maximum mapped by the Linux kernel during initialization ?? 173 * the maximum mapped by the Linux kernel during initialization ??
176 */ 174 */
177 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 175 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
178 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 176 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
179 177
180 /*----------------------------------------------------------------------- 178 /*-----------------------------------------------------------------------
181 * FLASH organization 179 * FLASH organization
182 */ 180 */
183 #define CONFIG_SYS_FLASH_CFI 181 #define CONFIG_SYS_FLASH_CFI
184 #ifdef CONFIG_SYS_FLASH_CFI 182 #ifdef CONFIG_SYS_FLASH_CFI
185 # define CONFIG_FLASH_CFI_DRIVER 1 183 # define CONFIG_FLASH_CFI_DRIVER 1
186 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 184 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
187 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 185 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
188 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 186 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
189 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 187 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
190 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 188 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
191 #endif 189 #endif
192 190
193 #ifdef CONFIG_NANDFLASH_SIZE 191 #ifdef CONFIG_NANDFLASH_SIZE
194 # define CONFIG_SYS_MAX_NAND_DEVICE 1 192 # define CONFIG_SYS_MAX_NAND_DEVICE 1
195 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 193 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
196 # define CONFIG_SYS_NAND_SIZE 1 194 # define CONFIG_SYS_NAND_SIZE 1
197 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 195 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
198 # define NAND_ALLOW_ERASE_ALL 1 196 # define NAND_ALLOW_ERASE_ALL 1
199 # define CONFIG_JFFS2_NAND 1 197 # define CONFIG_JFFS2_NAND 1
200 # define CONFIG_JFFS2_DEV "nand0" 198 # define CONFIG_JFFS2_DEV "nand0"
201 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 199 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
202 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 200 # define CONFIG_JFFS2_PART_OFFSET 0x00000000
203 #endif 201 #endif
204 202
205 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 203 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
206 204
207 /* Configuration for environment 205 /* Configuration for environment
208 * Environment is embedded in u-boot in the second sector of the flash 206 * Environment is embedded in u-boot in the second sector of the flash
209 */ 207 */
210 #define CONFIG_ENV_OFFSET 0x4000 208 #define CONFIG_ENV_OFFSET 0x4000
211 #define CONFIG_ENV_SECT_SIZE 0x2000 209 #define CONFIG_ENV_SECT_SIZE 0x2000
212 #define CONFIG_ENV_IS_IN_FLASH 1 210 #define CONFIG_ENV_IS_IN_FLASH 1
213 211
214 /*----------------------------------------------------------------------- 212 /*-----------------------------------------------------------------------
215 * Cache Configuration 213 * Cache Configuration
216 */ 214 */
217 #define CONFIG_SYS_CACHELINE_SIZE 16 215 #define CONFIG_SYS_CACHELINE_SIZE 16
218 216
219 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 217 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
220 CONFIG_SYS_INIT_RAM_SIZE - 8) 218 CONFIG_SYS_INIT_RAM_SIZE - 8)
221 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 219 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
222 CONFIG_SYS_INIT_RAM_SIZE - 4) 220 CONFIG_SYS_INIT_RAM_SIZE - 4)
223 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 221 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
224 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 222 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
225 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 223 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
226 CF_ACR_EN | CF_ACR_SM_ALL) 224 CF_ACR_EN | CF_ACR_SM_ALL)
227 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 225 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
228 CF_CACR_DCM_P) 226 CF_CACR_DCM_P)
229 227
230 /*----------------------------------------------------------------------- 228 /*-----------------------------------------------------------------------
231 * Chipselect bank definitions 229 * Chipselect bank definitions
232 */ 230 */
233 /* 231 /*
234 * CS0 - NOR Flash 1, 2, 4, or 8MB 232 * CS0 - NOR Flash 1, 2, 4, or 8MB
235 * CS1 - CompactFlash and registers 233 * CS1 - CompactFlash and registers
236 * CS2 - NAND Flash 16, 32, or 64MB 234 * CS2 - NAND Flash 16, 32, or 64MB
237 * CS3 - Available 235 * CS3 - Available
238 * CS4 - Available 236 * CS4 - Available
239 * CS5 - Available 237 * CS5 - Available
240 */ 238 */
241 #define CONFIG_SYS_CS0_BASE 0 239 #define CONFIG_SYS_CS0_BASE 0
242 #define CONFIG_SYS_CS0_MASK 0x007f0001 240 #define CONFIG_SYS_CS0_MASK 0x007f0001
243 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 241 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
244 242
245 #define CONFIG_SYS_CS1_BASE 0x10000000 243 #define CONFIG_SYS_CS1_BASE 0x10000000
246 #define CONFIG_SYS_CS1_MASK 0x001f0001 244 #define CONFIG_SYS_CS1_MASK 0x001f0001
247 #define CONFIG_SYS_CS1_CTRL 0x002A3780 245 #define CONFIG_SYS_CS1_CTRL 0x002A3780
248 246
249 #ifdef CONFIG_NANDFLASH_SIZE 247 #ifdef CONFIG_NANDFLASH_SIZE
250 #define CONFIG_SYS_CS2_BASE 0x20000000 248 #define CONFIG_SYS_CS2_BASE 0x20000000
251 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 249 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
252 #define CONFIG_SYS_CS2_CTRL 0x00001f60 250 #define CONFIG_SYS_CS2_CTRL 0x00001f60
253 #endif 251 #endif
254 252
255 #endif /* _M5373EVB_H */ 253 #endif /* _M5373EVB_H */
256 254
include/configs/astro_mcf5373l.h
Diff comments   View file @ c155ab7
1 /* 1 /*
2 * Configuration settings for the Sentec Cobra Board. 2 * Configuration settings for the Sentec Cobra Board.
3 * 3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 /* 9 /*
10 * configuration for ASTRO "Urmel" board. 10 * configuration for ASTRO "Urmel" board.
11 * Originating from Cobra5272 configuration, messed up by 11 * Originating from Cobra5272 configuration, messed up by
12 * Wolfgang Wegner <w.wegner@astro-kom.de> 12 * Wolfgang Wegner <w.wegner@astro-kom.de>
13 * Please do not bother the original author with bug reports 13 * Please do not bother the original author with bug reports
14 * concerning this file. 14 * concerning this file.
15 */ 15 */
16 16
17 #ifndef _CONFIG_ASTRO_MCF5373L_H 17 #ifndef _CONFIG_ASTRO_MCF5373L_H
18 #define _CONFIG_ASTRO_MCF5373L_H 18 #define _CONFIG_ASTRO_MCF5373L_H
19 19
20 #include <linux/stringify.h> 20 #include <linux/stringify.h>
21 21
22 /* 22 /*
23 * set the card type to actually compile for; either of 23 * set the card type to actually compile for; either of
24 * the possibilities listed below has to be used! 24 * the possibilities listed below has to be used!
25 */ 25 */
26 #define CONFIG_ASTRO_V532 1 26 #define CONFIG_ASTRO_V532 1
27 27
28 #if CONFIG_ASTRO_V532 28 #if CONFIG_ASTRO_V532
29 #define ASTRO_ID 0xF8 29 #define ASTRO_ID 0xF8
30 #elif CONFIG_ASTRO_V512 30 #elif CONFIG_ASTRO_V512
31 #define ASTRO_ID 0xFA 31 #define ASTRO_ID 0xFA
32 #elif CONFIG_ASTRO_TWIN7S2 32 #elif CONFIG_ASTRO_TWIN7S2
33 #define ASTRO_ID 0xF9 33 #define ASTRO_ID 0xF9
34 #elif CONFIG_ASTRO_V912 34 #elif CONFIG_ASTRO_V912
35 #define ASTRO_ID 0xFC 35 #define ASTRO_ID 0xFC
36 #elif CONFIG_ASTRO_COFDMDUOS2 36 #elif CONFIG_ASTRO_COFDMDUOS2
37 #define ASTRO_ID 0xFB 37 #define ASTRO_ID 0xFB
38 #else 38 #else
39 #error No card type defined! 39 #error No card type defined!
40 #endif 40 #endif
41 41
42 /*
43 * Define processor
44 * possible values for Urmel board: only Coldfire M5373 processor supported
45 * (please do not change)
46 */
47
48 /* it seems not clear yet which processor defines we should use */
49 #define CONFIG_MCF537x /* define processor family */
50 #define CONFIG_MCF532x /* define processor family */
51 #define CONFIG_M5373 /* define processor type */
52 #define CONFIG_ASTRO5373L /* define board type */ 42 #define CONFIG_ASTRO5373L /* define board type */
53 43
54 /* Command line configuration */ 44 /* Command line configuration */
55 #include <config_cmd_default.h> 45 #include <config_cmd_default.h>
56 46
57 /* 47 /*
58 * CONFIG_RAM defines if u-boot is loaded via BDM (or started from 48 * CONFIG_RAM defines if u-boot is loaded via BDM (or started from
59 * a different bootloader that has already performed RAM setup) or 49 * a different bootloader that has already performed RAM setup) or
60 * started directly from flash, which is the regular case for production 50 * started directly from flash, which is the regular case for production
61 * boards. 51 * boards.
62 */ 52 */
63 #ifdef CONFIG_RAM 53 #ifdef CONFIG_RAM
64 #define CONFIG_MONITOR_IS_IN_RAM 54 #define CONFIG_MONITOR_IS_IN_RAM
65 #define CONFIG_SYS_TEXT_BASE 0x40020000 55 #define CONFIG_SYS_TEXT_BASE 0x40020000
66 #define ENABLE_JFFS 0 56 #define ENABLE_JFFS 0
67 #else 57 #else
68 #define CONFIG_SYS_TEXT_BASE 0x00000000 58 #define CONFIG_SYS_TEXT_BASE 0x00000000
69 #define ENABLE_JFFS 1 59 #define ENABLE_JFFS 1
70 #endif 60 #endif
71 61
72 /* Define which commmands should be available at u-boot command prompt */ 62 /* Define which commmands should be available at u-boot command prompt */
73 63
74 #define CONFIG_CMD_CACHE 64 #define CONFIG_CMD_CACHE
75 #define CONFIG_CMD_DATE 65 #define CONFIG_CMD_DATE
76 #define CONFIG_CMD_ELF 66 #define CONFIG_CMD_ELF
77 #define CONFIG_CMD_FLASH 67 #define CONFIG_CMD_FLASH
78 #define CONFIG_CMD_I2C 68 #define CONFIG_CMD_I2C
79 #define CONFIG_CMD_MEMORY 69 #define CONFIG_CMD_MEMORY
80 #define CONFIG_CMD_MISC 70 #define CONFIG_CMD_MISC
81 #define CONFIG_CMD_XIMG 71 #define CONFIG_CMD_XIMG
82 #undef CONFIG_CMD_NET 72 #undef CONFIG_CMD_NET
83 #undef CONFIG_CMD_NFS 73 #undef CONFIG_CMD_NFS
84 #if ENABLE_JFFS 74 #if ENABLE_JFFS
85 #define CONFIG_CMD_JFFS2 75 #define CONFIG_CMD_JFFS2
86 #endif 76 #endif
87 #define CONFIG_CMD_REGINFO 77 #define CONFIG_CMD_REGINFO
88 #define CONFIG_CMD_LOADS 78 #define CONFIG_CMD_LOADS
89 #define CONFIG_CMD_LOADB 79 #define CONFIG_CMD_LOADB
90 #define CONFIG_CMD_FPGA 80 #define CONFIG_CMD_FPGA
91 #define CONFIG_CMD_FPGA_LOADMK 81 #define CONFIG_CMD_FPGA_LOADMK
92 #define CONFIG_CMDLINE_EDITING 82 #define CONFIG_CMDLINE_EDITING
93 83
94 #define CONFIG_SYS_HUSH_PARSER 84 #define CONFIG_SYS_HUSH_PARSER
95 85
96 #define CONFIG_MCFRTC 86 #define CONFIG_MCFRTC
97 #undef RTC_DEBUG 87 #undef RTC_DEBUG
98 88
99 /* Timer */ 89 /* Timer */
100 #define CONFIG_MCFTMR 90 #define CONFIG_MCFTMR
101 #undef CONFIG_MCFPIT 91 #undef CONFIG_MCFPIT
102 92
103 /* I2C */ 93 /* I2C */
104 #define CONFIG_SYS_I2C 94 #define CONFIG_SYS_I2C
105 #define CONFIG_SYS_I2C_FSL 95 #define CONFIG_SYS_I2C_FSL
106 #define CONFIG_SYS_FSL_I2C_SPEED 80000 96 #define CONFIG_SYS_FSL_I2C_SPEED 80000
107 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 97 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
108 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 98 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
109 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 99 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
110 100
111 /* 101 /*
112 * Defines processor clock - important for correct timings concerning serial 102 * Defines processor clock - important for correct timings concerning serial
113 * interface etc. 103 * interface etc.
114 */ 104 */
115 105
116 #define CONFIG_SYS_CLK 80000000 106 #define CONFIG_SYS_CLK 80000000
117 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) 107 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
118 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 108 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
119 109
120 #define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 110 #define CONFIG_SYS_CORE_SRAM_SIZE 0x8000
121 #define CONFIG_SYS_CORE_SRAM 0x80000000 111 #define CONFIG_SYS_CORE_SRAM 0x80000000
122 112
123 #define CONFIG_SYS_UNIFY_CACHE 113 #define CONFIG_SYS_UNIFY_CACHE
124 114
125 /* 115 /*
126 * Define baudrate for UART1 (console output, tftp, ...) 116 * Define baudrate for UART1 (console output, tftp, ...)
127 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud 117 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
128 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected 118 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
129 * in u-boot command interface 119 * in u-boot command interface
130 */ 120 */
131 121
132 #define CONFIG_BAUDRATE 115200 122 #define CONFIG_BAUDRATE 115200
133 123
134 #define CONFIG_MCFUART 124 #define CONFIG_MCFUART
135 #define CONFIG_SYS_UART_PORT (2) 125 #define CONFIG_SYS_UART_PORT (2)
136 #define CONFIG_SYS_UART2_ALT3_GPIO 126 #define CONFIG_SYS_UART2_ALT3_GPIO
137 127
138 /* 128 /*
139 * Watchdog configuration; Watchdog is disabled for running from RAM 129 * Watchdog configuration; Watchdog is disabled for running from RAM
140 * and set to highest possible value else. Beware there is no check 130 * and set to highest possible value else. Beware there is no check
141 * in the watchdog code to validate the timeout value set here! 131 * in the watchdog code to validate the timeout value set here!
142 */ 132 */
143 133
144 #ifndef CONFIG_MONITOR_IS_IN_RAM 134 #ifndef CONFIG_MONITOR_IS_IN_RAM
145 #define CONFIG_WATCHDOG 135 #define CONFIG_WATCHDOG
146 #define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ 136 #define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */
147 #endif 137 #endif
148 138
149 /* 139 /*
150 * Configuration for environment 140 * Configuration for environment
151 * Environment is located in the last sector of the flash 141 * Environment is located in the last sector of the flash
152 */ 142 */
153 143
154 #ifndef CONFIG_MONITOR_IS_IN_RAM 144 #ifndef CONFIG_MONITOR_IS_IN_RAM
155 #define CONFIG_ENV_OFFSET 0x1FF8000 145 #define CONFIG_ENV_OFFSET 0x1FF8000
156 #define CONFIG_ENV_SECT_SIZE 0x8000 146 #define CONFIG_ENV_SECT_SIZE 0x8000
157 #define CONFIG_ENV_IS_IN_FLASH 1 147 #define CONFIG_ENV_IS_IN_FLASH 1
158 #else 148 #else
159 /* 149 /*
160 * environment in RAM - This is used to use a single PC-based application 150 * environment in RAM - This is used to use a single PC-based application
161 * to load an image, load U-Boot, load an environment and then start U-Boot 151 * to load an image, load U-Boot, load an environment and then start U-Boot
162 * to execute the commands from the environment. Feedback is done via setting 152 * to execute the commands from the environment. Feedback is done via setting
163 * and reading memory locations. 153 * and reading memory locations.
164 */ 154 */
165 #define CONFIG_ENV_ADDR 0x40060000 155 #define CONFIG_ENV_ADDR 0x40060000
166 #define CONFIG_ENV_SECT_SIZE 0x8000 156 #define CONFIG_ENV_SECT_SIZE 0x8000
167 #define CONFIG_ENV_IS_IN_FLASH 1 157 #define CONFIG_ENV_IS_IN_FLASH 1
168 #endif 158 #endif
169 159
170 /* here we put our FPGA configuration... */ 160 /* here we put our FPGA configuration... */
171 #define CONFIG_MISC_INIT_R 1 161 #define CONFIG_MISC_INIT_R 1
172 162
173 /* Define user parameters that have to be customized most likely */ 163 /* Define user parameters that have to be customized most likely */
174 164
175 /* AUTOBOOT settings - booting images automatically by u-boot after power on */ 165 /* AUTOBOOT settings - booting images automatically by u-boot after power on */
176 166
177 /* 167 /*
178 * used for autoboot, delay in seconds u-boot will wait before starting 168 * used for autoboot, delay in seconds u-boot will wait before starting
179 * defined (auto-)boot command, setting to -1 disables delay, setting to 169 * defined (auto-)boot command, setting to -1 disables delay, setting to
180 * 0 will too prevent access to u-boot command interface: u-boot then has 170 * 0 will too prevent access to u-boot command interface: u-boot then has
181 * to be reflashed 171 * to be reflashed
182 * beware - watchdog is not serviced during autoboot delay time! 172 * beware - watchdog is not serviced during autoboot delay time!
183 */ 173 */
184 #ifdef CONFIG_MONITOR_IS_IN_RAM 174 #ifdef CONFIG_MONITOR_IS_IN_RAM
185 #define CONFIG_BOOTDELAY 1 175 #define CONFIG_BOOTDELAY 1
186 #else 176 #else
187 #define CONFIG_BOOTDELAY 1 177 #define CONFIG_BOOTDELAY 1
188 #endif 178 #endif
189 179
190 /* 180 /*
191 * The following settings will be contained in the environment block ; if you 181 * The following settings will be contained in the environment block ; if you
192 * want to use a neutral environment all those settings can be manually set in 182 * want to use a neutral environment all those settings can be manually set in
193 * u-boot: 'set' command 183 * u-boot: 'set' command
194 */ 184 */
195 185
196 #define CONFIG_EXTRA_ENV_SETTINGS \ 186 #define CONFIG_EXTRA_ENV_SETTINGS \
197 "loaderversion=11\0" \ 187 "loaderversion=11\0" \
198 "card_id="__stringify(ASTRO_ID)"\0" \ 188 "card_id="__stringify(ASTRO_ID)"\0" \
199 "alterafile=0\0" \ 189 "alterafile=0\0" \
200 "xilinxfile=0\0" \ 190 "xilinxfile=0\0" \
201 "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ 191 "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
202 "fpga load 0 0x41000000 $filesize\0" \ 192 "fpga load 0 0x41000000 $filesize\0" \
203 "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ 193 "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
204 "fpga load 1 0x41000000 $filesize\0" \ 194 "fpga load 1 0x41000000 $filesize\0" \
205 "env_default=1\0" \ 195 "env_default=1\0" \
206 "env_check=if test $env_default -eq 1;"\ 196 "env_check=if test $env_default -eq 1;"\
207 " then setenv env_default 0;saveenv;fi\0" 197 " then setenv env_default 0;saveenv;fi\0"
208 198
209 /* 199 /*
210 * "update" is a non-standard command that has to be supplied 200 * "update" is a non-standard command that has to be supplied
211 * by external update.c; This is not included in mainline because 201 * by external update.c; This is not included in mainline because
212 * it needs non-blocking CFI routines. 202 * it needs non-blocking CFI routines.
213 */ 203 */
214 #ifdef CONFIG_MONITOR_IS_IN_RAM 204 #ifdef CONFIG_MONITOR_IS_IN_RAM
215 #define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ 205 #define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */
216 #else 206 #else
217 #if CONFIG_ASTRO_V532 207 #if CONFIG_ASTRO_V532
218 #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ 208 #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\
219 "run xilinxload&&run alteraload&&bootm 0x80000;"\ 209 "run xilinxload&&run alteraload&&bootm 0x80000;"\
220 "update;reset" 210 "update;reset"
221 #else 211 #else
222 #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ 212 #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\
223 "run xilinxload&&bootm 0x80000;update;reset" 213 "run xilinxload&&bootm 0x80000;update;reset"
224 #endif 214 #endif
225 #endif 215 #endif
226 216
227 /* default bootargs that are considered during boot */ 217 /* default bootargs that are considered during boot */
228 #define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\ 218 #define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\
229 " loaderversion=$loaderversion" 219 " loaderversion=$loaderversion"
230 220
231 #define CONFIG_SYS_PROMPT "URMEL > " 221 #define CONFIG_SYS_PROMPT "URMEL > "
232 222
233 /* default RAM address for user programs */ 223 /* default RAM address for user programs */
234 #define CONFIG_SYS_LOAD_ADDR 0x20000 224 #define CONFIG_SYS_LOAD_ADDR 0x20000
235 225
236 #define CONFIG_SYS_LONGHELP 226 #define CONFIG_SYS_LONGHELP
237 227
238 #if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) 228 #if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
239 #define CONFIG_SYS_CBSIZE 1024 229 #define CONFIG_SYS_CBSIZE 1024
240 #else 230 #else
241 #define CONFIG_SYS_CBSIZE 256 231 #define CONFIG_SYS_CBSIZE 256
242 #endif 232 #endif
243 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 233 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
244 #define CONFIG_SYS_MAXARGS 16 234 #define CONFIG_SYS_MAXARGS 16
245 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 235 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
246 236
247 #define CONFIG_FPGA_COUNT 1 237 #define CONFIG_FPGA_COUNT 1
248 #define CONFIG_FPGA 238 #define CONFIG_FPGA
249 #define CONFIG_FPGA_XILINX 239 #define CONFIG_FPGA_XILINX
250 #define CONFIG_FPGA_SPARTAN3 240 #define CONFIG_FPGA_SPARTAN3
251 #define CONFIG_FPGA_ALTERA 241 #define CONFIG_FPGA_ALTERA
252 #define CONFIG_FPGA_CYCLON2 242 #define CONFIG_FPGA_CYCLON2
253 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 243 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
254 #define CONFIG_SYS_FPGA_WAIT 1000 244 #define CONFIG_SYS_FPGA_WAIT 1000
255 245
256 /* End of user parameters to be customized */ 246 /* End of user parameters to be customized */
257 247
258 /* Defines memory range for test */ 248 /* Defines memory range for test */
259 249
260 #define CONFIG_SYS_MEMTEST_START 0x40020000 250 #define CONFIG_SYS_MEMTEST_START 0x40020000
261 #define CONFIG_SYS_MEMTEST_END 0x41ffffff 251 #define CONFIG_SYS_MEMTEST_END 0x41ffffff
262 252
263 /* 253 /*
264 * Low Level Configuration Settings 254 * Low Level Configuration Settings
265 * (address mappings, register initial values, etc.) 255 * (address mappings, register initial values, etc.)
266 * You should know what you are doing if you make changes here. 256 * You should know what you are doing if you make changes here.
267 */ 257 */
268 258
269 /* Base register address */ 259 /* Base register address */
270 260
271 #define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ 261 #define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
272 262
273 /* System Conf. Reg. & System Protection Reg. */ 263 /* System Conf. Reg. & System Protection Reg. */
274 264
275 #define CONFIG_SYS_SCR 0x0003; 265 #define CONFIG_SYS_SCR 0x0003;
276 #define CONFIG_SYS_SPR 0xffff; 266 #define CONFIG_SYS_SPR 0xffff;
277 267
278 /* 268 /*
279 * Definitions for initial stack pointer and data area (in internal SRAM) 269 * Definitions for initial stack pointer and data area (in internal SRAM)
280 */ 270 */
281 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 271 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
282 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 272 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000
283 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 273 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
284 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 274 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
285 GENERATED_GBL_DATA_SIZE) 275 GENERATED_GBL_DATA_SIZE)
286 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 276 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
287 277
288 /* 278 /*
289 * Start addresses for the final memory configuration 279 * Start addresses for the final memory configuration
290 * (Set up by the startup code) 280 * (Set up by the startup code)
291 * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 281 * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
292 */ 282 */
293 #define CONFIG_SYS_SDRAM_BASE 0x40000000 283 #define CONFIG_SYS_SDRAM_BASE 0x40000000
294 284
295 /* 285 /*
296 * Chipselect bank definitions 286 * Chipselect bank definitions
297 * 287 *
298 * CS0 - Flash 32MB (first 16MB) 288 * CS0 - Flash 32MB (first 16MB)
299 * CS1 - Flash 32MB (second half) 289 * CS1 - Flash 32MB (second half)
300 * CS2 - FPGA 290 * CS2 - FPGA
301 * CS3 - FPGA 291 * CS3 - FPGA
302 * CS4 - unused 292 * CS4 - unused
303 * CS5 - unused 293 * CS5 - unused
304 */ 294 */
305 #define CONFIG_SYS_CS0_BASE 0 295 #define CONFIG_SYS_CS0_BASE 0
306 #define CONFIG_SYS_CS0_MASK 0x00ff0001 296 #define CONFIG_SYS_CS0_MASK 0x00ff0001
307 #define CONFIG_SYS_CS0_CTRL 0x00001fc0 297 #define CONFIG_SYS_CS0_CTRL 0x00001fc0
308 298
309 #define CONFIG_SYS_CS1_BASE 0x01000000 299 #define CONFIG_SYS_CS1_BASE 0x01000000
310 #define CONFIG_SYS_CS1_MASK 0x00ff0001 300 #define CONFIG_SYS_CS1_MASK 0x00ff0001
311 #define CONFIG_SYS_CS1_CTRL 0x00001fc0 301 #define CONFIG_SYS_CS1_CTRL 0x00001fc0
312 302
313 #define CONFIG_SYS_CS2_BASE 0x20000000 303 #define CONFIG_SYS_CS2_BASE 0x20000000
314 #define CONFIG_SYS_CS2_MASK 0x00ff0001 304 #define CONFIG_SYS_CS2_MASK 0x00ff0001
315 #define CONFIG_SYS_CS2_CTRL 0x0000fec0 305 #define CONFIG_SYS_CS2_CTRL 0x0000fec0
316 306
317 #define CONFIG_SYS_CS3_BASE 0x21000000 307 #define CONFIG_SYS_CS3_BASE 0x21000000
318 #define CONFIG_SYS_CS3_MASK 0x00ff0001 308 #define CONFIG_SYS_CS3_MASK 0x00ff0001
319 #define CONFIG_SYS_CS3_CTRL 0x0000fec0 309 #define CONFIG_SYS_CS3_CTRL 0x0000fec0
320 310
321 #define CONFIG_SYS_FLASH_BASE 0x00000000 311 #define CONFIG_SYS_FLASH_BASE 0x00000000
322 312
323 #ifdef CONFIG_MONITOR_IS_IN_RAM 313 #ifdef CONFIG_MONITOR_IS_IN_RAM
324 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 314 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
325 #else 315 #else
326 /* This is mainly used during relocation in start.S */ 316 /* This is mainly used during relocation in start.S */
327 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 317 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
328 #endif 318 #endif
329 /* Reserve 256 kB for Monitor */ 319 /* Reserve 256 kB for Monitor */
330 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 320 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
331 321
332 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 322 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
333 /* Reserve 128 kB for malloc() */ 323 /* Reserve 128 kB for malloc() */
334 #define CONFIG_SYS_MALLOC_LEN (128 << 10) 324 #define CONFIG_SYS_MALLOC_LEN (128 << 10)
335 325
336 /* 326 /*
337 * For booting Linux, the board info and command line data 327 * For booting Linux, the board info and command line data
338 * have to be in the first 8 MB of memory, since this is 328 * have to be in the first 8 MB of memory, since this is
339 * the maximum mapped by the Linux kernel during initialization ?? 329 * the maximum mapped by the Linux kernel during initialization ??
340 */ 330 */
341 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 331 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
342 (CONFIG_SYS_SDRAM_SIZE << 20)) 332 (CONFIG_SYS_SDRAM_SIZE << 20))
343 333
344 /* FLASH organization */ 334 /* FLASH organization */
345 #define CONFIG_SYS_MAX_FLASH_BANKS 1 335 #define CONFIG_SYS_MAX_FLASH_BANKS 1
346 #define CONFIG_SYS_MAX_FLASH_SECT 259 336 #define CONFIG_SYS_MAX_FLASH_SECT 259
347 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 337 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
348 338
349 #define CONFIG_SYS_FLASH_CFI 1 339 #define CONFIG_SYS_FLASH_CFI 1
350 #define CONFIG_FLASH_CFI_DRIVER 1 340 #define CONFIG_FLASH_CFI_DRIVER 1
351 #define CONFIG_SYS_FLASH_SIZE 0x2000000 341 #define CONFIG_SYS_FLASH_SIZE 0x2000000
352 #define CONFIG_SYS_FLASH_PROTECTION 1 342 #define CONFIG_SYS_FLASH_PROTECTION 1
353 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 343 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
354 #define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 344 #define CONFIG_SYS_FLASH_CFI_NONBLOCK 1
355 345
356 #if ENABLE_JFFS 346 #if ENABLE_JFFS
357 /* JFFS Partition offset set */ 347 /* JFFS Partition offset set */
358 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 348 #define CONFIG_SYS_JFFS2_FIRST_BANK 0
359 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 349 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
360 /* 512k reserved for u-boot */ 350 /* 512k reserved for u-boot */
361 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 351 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40
362 #endif 352 #endif
363 353
364 /* Cache Configuration */ 354 /* Cache Configuration */
365 #define CONFIG_SYS_CACHELINE_SIZE 16 355 #define CONFIG_SYS_CACHELINE_SIZE 16
366 356
367 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 357 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
368 CONFIG_SYS_INIT_RAM_SIZE - 8) 358 CONFIG_SYS_INIT_RAM_SIZE - 8)
369 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 359 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
370 CONFIG_SYS_INIT_RAM_SIZE - 4) 360 CONFIG_SYS_INIT_RAM_SIZE - 4)
371 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 361 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
372 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 362 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
373 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 363 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
374 CF_ACR_EN | CF_ACR_SM_ALL) 364 CF_ACR_EN | CF_ACR_SM_ALL)
375 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 365 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
376 CF_CACR_DCM_P) 366 CF_CACR_DCM_P)
377 367
378 #endif /* _CONFIG_ASTRO_MCF5373L_H */ 368 #endif /* _CONFIG_ASTRO_MCF5373L_H */
379 369