Eric Lee / smarc-uboot

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Commit c35bf3b38c416cb89111003d20eb8842b5b561ef

Authored by Peng Fan
1 parent 559a70913b
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 1 other branch smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-20373-4 imx8: update mem map table 

Update mem map table for xen uboot.
xen console and some magic pages needs to be mappe as normal memory.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
(cherry picked from commit c96a9844cd3342f6e31627ccc4f3e63544ffd78e)
(cherry picked from commit 30b2d9f4a7c0cfc9b3f999f1c3a1a8c466d66a68)
(cherry picked from commit 152de9a5752881e43dd7afc9b47afa56b3b230e8)

Showing 1 changed file with 20 additions and 9 deletions Inline Diff

arch/arm/mach-imx/imx8/cpu.c
Diff comments   View file @ c35bf3b
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017-2020 NXP 3 * Copyright 2017-2020 NXP
4 */ 4 */
5 5
6 #include <common.h> 6 #include <common.h>
7 #include <clk.h> 7 #include <clk.h>
8 #include <cpu.h> 8 #include <cpu.h>
9 #include <cpu_func.h> 9 #include <cpu_func.h>
10 #include <dm.h> 10 #include <dm.h>
11 #include <init.h> 11 #include <init.h>
12 #include <dm/device-internal.h> 12 #include <dm/device-internal.h>
13 #include <dm/lists.h> 13 #include <dm/lists.h>
14 #include <dm/uclass.h> 14 #include <dm/uclass.h>
15 #include <errno.h> 15 #include <errno.h>
16 #include <asm/arch/clock.h> 16 #include <asm/arch/clock.h>
17 #include <power-domain.h> 17 #include <power-domain.h>
18 #include <dm/device.h> 18 #include <dm/device.h>
19 #include <dm/uclass-internal.h> 19 #include <dm/uclass-internal.h>
20 #include <thermal.h> 20 #include <thermal.h>
21 #include <asm/arch/sci/sci.h> 21 #include <asm/arch/sci/sci.h>
22 #include <power-domain.h> 22 #include <power-domain.h>
23 #include <elf.h> 23 #include <elf.h>
24 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch-imx/cpu.h> 25 #include <asm/arch-imx/cpu.h>
26 #include <asm/armv8/cpu.h> 26 #include <asm/armv8/cpu.h>
27 #include <asm/armv8/mmu.h> 27 #include <asm/armv8/mmu.h>
28 #include <asm/setup.h> 28 #include <asm/setup.h>
29 #include <asm/mach-imx/boot_mode.h> 29 #include <asm/mach-imx/boot_mode.h>
30 #include <asm/mach-imx/imx_vservice.h> 30 #include <asm/mach-imx/imx_vservice.h>
31 #include <spl.h> 31 #include <spl.h>
32 #include <usb/ci_udc.h> 32 #include <usb/ci_udc.h>
33 33
34 DECLARE_GLOBAL_DATA_PTR; 34 DECLARE_GLOBAL_DATA_PTR;
35 35
36 #define BT_PASSOVER_TAG 0x504F 36 #define BT_PASSOVER_TAG 0x504F
37 struct pass_over_info_t *get_pass_over_info(void) 37 struct pass_over_info_t *get_pass_over_info(void)
38 { 38 {
39 struct pass_over_info_t *p = 39 struct pass_over_info_t *p =
40 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR; 40 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
41 41
42 if (p->barker != BT_PASSOVER_TAG || 42 if (p->barker != BT_PASSOVER_TAG ||
43 p->len != sizeof(struct pass_over_info_t)) 43 p->len != sizeof(struct pass_over_info_t))
44 return NULL; 44 return NULL;
45 45
46 return p; 46 return p;
47 } 47 }
48 48
49 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION) 49 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION)
50 char __data_save_start[0] __attribute__((section(".__data_save_start"))); 50 char __data_save_start[0] __attribute__((section(".__data_save_start")));
51 char __data_save_end[0] __attribute__((section(".__data_save_end"))); 51 char __data_save_end[0] __attribute__((section(".__data_save_end")));
52 52
53 u32 cold_reboot_flag = 1; 53 u32 cold_reboot_flag = 1;
54 54
55 static void save_restore_data(void) 55 static void save_restore_data(void)
56 { 56 {
57 u32 data_size = __data_save_end - __data_save_start; 57 u32 data_size = __data_save_end - __data_save_start;
58 58
59 if (cold_reboot_flag == 1) { 59 if (cold_reboot_flag == 1) {
60 /* Save data section to data_save section */ 60 /* Save data section to data_save section */
61 memcpy(__data_save_start, __data_save_start - data_size, data_size); 61 memcpy(__data_save_start, __data_save_start - data_size, data_size);
62 } else { 62 } else {
63 /* Restore the data_save section to data section */ 63 /* Restore the data_save section to data section */
64 memcpy(__data_save_start - data_size, __data_save_start, data_size); 64 memcpy(__data_save_start - data_size, __data_save_start, data_size);
65 } 65 }
66 cold_reboot_flag++; 66 cold_reboot_flag++;
67 } 67 }
68 #endif 68 #endif
69 69
70 int arch_cpu_init(void) 70 int arch_cpu_init(void)
71 { 71 {
72 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION) 72 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION)
73 save_restore_data(); 73 save_restore_data();
74 #endif 74 #endif
75 75
76 return 0; 76 return 0;
77 } 77 }
78 78
79 static void power_off_all_usb(void); 79 static void power_off_all_usb(void);
80 80
81 int arch_cpu_init_dm(void) 81 int arch_cpu_init_dm(void)
82 { 82 {
83 struct udevice *devp; 83 struct udevice *devp;
84 int node, ret; 84 int node, ret;
85 85
86 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu"); 86 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
87 87
88 ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); 88 ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
89 if (ret) { 89 if (ret) {
90 printf("could not get scu %d\n", ret); 90 printf("could not get scu %d\n", ret);
91 return ret; 91 return ret;
92 } 92 }
93 93
94 if (IS_ENABLED(CONFIG_XEN)) 94 if (IS_ENABLED(CONFIG_XEN))
95 return 0; 95 return 0;
96 96
97 struct pass_over_info_t *pass_over; 97 struct pass_over_info_t *pass_over;
98 98
99 if ((is_imx8qm() || is_imx8qxp()) && is_soc_rev(CHIP_REV_A)) { 99 if ((is_imx8qm() || is_imx8qxp()) && is_soc_rev(CHIP_REV_A)) {
100 pass_over = get_pass_over_info(); 100 pass_over = get_pass_over_info();
101 if (pass_over && pass_over->g_ap_mu == 0) { 101 if (pass_over && pass_over->g_ap_mu == 0) {
102 /* 102 /*
103 * When ap_mu is 0, means the U-Boot booted 103 * When ap_mu is 0, means the U-Boot booted
104 * from first container 104 * from first container
105 */ 105 */
106 sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS); 106 sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
107 } 107 }
108 } 108 }
109 109
110 if (is_imx8qm()) { 110 if (is_imx8qm()) {
111 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU, 111 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
112 SC_PM_PW_MODE_ON); 112 SC_PM_PW_MODE_ON);
113 if (ret) 113 if (ret)
114 return ret; 114 return ret;
115 } 115 }
116 116
117 power_off_all_usb(); 117 power_off_all_usb();
118 118
119 return 0; 119 return 0;
120 } 120 }
121 121
122 #ifdef CONFIG_IMX_BOOTAUX 122 #ifdef CONFIG_IMX_BOOTAUX
123 123
124 #ifdef CONFIG_IMX8QM 124 #ifdef CONFIG_IMX8QM
125 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) 125 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
126 { 126 {
127 sc_rsrc_t core_rsrc, mu_rsrc; 127 sc_rsrc_t core_rsrc, mu_rsrc;
128 sc_faddr_t tcml_addr; 128 sc_faddr_t tcml_addr;
129 u32 tcm_size = SZ_256K; /* TCML + TCMU */ 129 u32 tcm_size = SZ_256K; /* TCML + TCMU */
130 ulong addr; 130 ulong addr;
131 131
132 132
133 switch (core_id) { 133 switch (core_id) {
134 case 0: 134 case 0:
135 core_rsrc = SC_R_M4_0_PID0; 135 core_rsrc = SC_R_M4_0_PID0;
136 tcml_addr = 0x34FE0000; 136 tcml_addr = 0x34FE0000;
137 mu_rsrc = SC_R_M4_0_MU_1A; 137 mu_rsrc = SC_R_M4_0_MU_1A;
138 break; 138 break;
139 case 1: 139 case 1:
140 core_rsrc = SC_R_M4_1_PID0; 140 core_rsrc = SC_R_M4_1_PID0;
141 tcml_addr = 0x38FE0000; 141 tcml_addr = 0x38FE0000;
142 mu_rsrc = SC_R_M4_1_MU_1A; 142 mu_rsrc = SC_R_M4_1_MU_1A;
143 break; 143 break;
144 default: 144 default:
145 printf("Not support this core boot up, ID:%u\n", core_id); 145 printf("Not support this core boot up, ID:%u\n", core_id);
146 return -EINVAL; 146 return -EINVAL;
147 } 147 }
148 148
149 addr = (sc_faddr_t)boot_private_data; 149 addr = (sc_faddr_t)boot_private_data;
150 150
151 if (addr >= tcml_addr && addr <= tcml_addr + tcm_size) { 151 if (addr >= tcml_addr && addr <= tcml_addr + tcm_size) {
152 printf("Wrong image address 0x%lx, should not in TCML\n", 152 printf("Wrong image address 0x%lx, should not in TCML\n",
153 addr); 153 addr);
154 return -EINVAL; 154 return -EINVAL;
155 } 155 }
156 156
157 printf("Power on M4 and MU\n"); 157 printf("Power on M4 and MU\n");
158 158
159 if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 159 if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
160 return -EIO; 160 return -EIO;
161 161
162 if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 162 if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
163 return -EIO; 163 return -EIO;
164 164
165 printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr); 165 printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
166 166
167 if (addr != tcml_addr) 167 if (addr != tcml_addr)
168 memcpy((void *)tcml_addr, (void *)addr, tcm_size); 168 memcpy((void *)tcml_addr, (void *)addr, tcm_size);
169 169
170 printf("Start M4 %u\n", core_id); 170 printf("Start M4 %u\n", core_id);
171 if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE) 171 if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
172 return -EIO; 172 return -EIO;
173 173
174 printf("bootaux complete\n"); 174 printf("bootaux complete\n");
175 return 0; 175 return 0;
176 } 176 }
177 #endif 177 #endif
178 178
179 #if defined(CONFIG_IMX8QXP) || defined(CONFIG_IMX8DXL) 179 #if defined(CONFIG_IMX8QXP) || defined(CONFIG_IMX8DXL)
180 static unsigned long load_elf_image_shdr(unsigned long addr) 180 static unsigned long load_elf_image_shdr(unsigned long addr)
181 { 181 {
182 Elf32_Ehdr *ehdr; /* Elf header structure pointer */ 182 Elf32_Ehdr *ehdr; /* Elf header structure pointer */
183 Elf32_Shdr *shdr; /* Section header structure pointer */ 183 Elf32_Shdr *shdr; /* Section header structure pointer */
184 unsigned char *strtab = 0; /* String table pointer */ 184 unsigned char *strtab = 0; /* String table pointer */
185 unsigned char *image; /* Binary image pointer */ 185 unsigned char *image; /* Binary image pointer */
186 int i; /* Loop counter */ 186 int i; /* Loop counter */
187 187
188 ehdr = (Elf32_Ehdr *)addr; 188 ehdr = (Elf32_Ehdr *)addr;
189 189
190 /* Find the section header string table for output info */ 190 /* Find the section header string table for output info */
191 shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + 191 shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
192 (ehdr->e_shstrndx * sizeof(Elf32_Shdr))); 192 (ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
193 193
194 if (shdr->sh_type == SHT_STRTAB) 194 if (shdr->sh_type == SHT_STRTAB)
195 strtab = (unsigned char *)(addr + shdr->sh_offset); 195 strtab = (unsigned char *)(addr + shdr->sh_offset);
196 196
197 /* Load each appropriate section */ 197 /* Load each appropriate section */
198 for (i = 0; i < ehdr->e_shnum; ++i) { 198 for (i = 0; i < ehdr->e_shnum; ++i) {
199 shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + 199 shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
200 (i * sizeof(Elf32_Shdr))); 200 (i * sizeof(Elf32_Shdr)));
201 201
202 if (!(shdr->sh_flags & SHF_ALLOC) || 202 if (!(shdr->sh_flags & SHF_ALLOC) ||
203 shdr->sh_addr == 0 || shdr->sh_size == 0) { 203 shdr->sh_addr == 0 || shdr->sh_size == 0) {
204 continue; 204 continue;
205 } 205 }
206 206
207 if (strtab) { 207 if (strtab) {
208 debug("%sing %s @ 0x%08lx (%ld bytes)\n", 208 debug("%sing %s @ 0x%08lx (%ld bytes)\n",
209 (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load", 209 (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
210 &strtab[shdr->sh_name], 210 &strtab[shdr->sh_name],
211 (unsigned long)shdr->sh_addr, 211 (unsigned long)shdr->sh_addr,
212 (long)shdr->sh_size); 212 (long)shdr->sh_size);
213 } 213 }
214 214
215 if (shdr->sh_type == SHT_NOBITS) { 215 if (shdr->sh_type == SHT_NOBITS) {
216 memset((void *)(uintptr_t)shdr->sh_addr, 0, 216 memset((void *)(uintptr_t)shdr->sh_addr, 0,
217 shdr->sh_size); 217 shdr->sh_size);
218 } else { 218 } else {
219 image = (unsigned char *)addr + shdr->sh_offset; 219 image = (unsigned char *)addr + shdr->sh_offset;
220 memcpy((void *)(uintptr_t)shdr->sh_addr, 220 memcpy((void *)(uintptr_t)shdr->sh_addr,
221 (const void *)image, shdr->sh_size); 221 (const void *)image, shdr->sh_size);
222 } 222 }
223 flush_cache(shdr->sh_addr, shdr->sh_size); 223 flush_cache(shdr->sh_addr, shdr->sh_size);
224 } 224 }
225 225
226 return ehdr->e_entry; 226 return ehdr->e_entry;
227 } 227 }
228 228
229 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) 229 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
230 { 230 {
231 sc_rsrc_t core_rsrc, mu_rsrc = -1; 231 sc_rsrc_t core_rsrc, mu_rsrc = -1;
232 sc_faddr_t aux_core_ram; 232 sc_faddr_t aux_core_ram;
233 u32 size; 233 u32 size;
234 ulong addr; 234 ulong addr;
235 235
236 switch (core_id) { 236 switch (core_id) {
237 case 0: 237 case 0:
238 core_rsrc = SC_R_M4_0_PID0; 238 core_rsrc = SC_R_M4_0_PID0;
239 aux_core_ram = 0x34FE0000; 239 aux_core_ram = 0x34FE0000;
240 mu_rsrc = SC_R_M4_0_MU_1A; 240 mu_rsrc = SC_R_M4_0_MU_1A;
241 size = SZ_256K; 241 size = SZ_256K;
242 break; 242 break;
243 case 1: 243 case 1:
244 core_rsrc = SC_R_DSP; 244 core_rsrc = SC_R_DSP;
245 aux_core_ram = 0x596f8000; 245 aux_core_ram = 0x596f8000;
246 size = SZ_2K; 246 size = SZ_2K;
247 break; 247 break;
248 default: 248 default:
249 printf("Not support this core boot up, ID:%u\n", core_id); 249 printf("Not support this core boot up, ID:%u\n", core_id);
250 return -EINVAL; 250 return -EINVAL;
251 } 251 }
252 252
253 addr = (sc_faddr_t)boot_private_data; 253 addr = (sc_faddr_t)boot_private_data;
254 254
255 if (addr >= aux_core_ram && addr <= aux_core_ram + size) { 255 if (addr >= aux_core_ram && addr <= aux_core_ram + size) {
256 printf("Wrong image address 0x%lx, should not in aux core ram\n", 256 printf("Wrong image address 0x%lx, should not in aux core ram\n",
257 addr); 257 addr);
258 return -EINVAL; 258 return -EINVAL;
259 } 259 }
260 260
261 printf("Power on aux core %d\n", core_id); 261 printf("Power on aux core %d\n", core_id);
262 262
263 if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 263 if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
264 return -EIO; 264 return -EIO;
265 265
266 if (mu_rsrc != -1) { 266 if (mu_rsrc != -1) {
267 if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 267 if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
268 return -EIO; 268 return -EIO;
269 } 269 }
270 270
271 if (core_id == 1) { 271 if (core_id == 1) {
272 struct power_domain pd; 272 struct power_domain pd;
273 273
274 if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) { 274 if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
275 printf("Error enable clock\n"); 275 printf("Error enable clock\n");
276 return -EIO; 276 return -EIO;
277 } 277 }
278 278
279 if (!power_domain_lookup_name("audio_sai0", &pd)) { 279 if (!power_domain_lookup_name("audio_sai0", &pd)) {
280 if (power_domain_on(&pd)) { 280 if (power_domain_on(&pd)) {
281 printf("Error power on SAI0\n"); 281 printf("Error power on SAI0\n");
282 return -EIO; 282 return -EIO;
283 } 283 }
284 } 284 }
285 285
286 if (!power_domain_lookup_name("audio_ocram", &pd)) { 286 if (!power_domain_lookup_name("audio_ocram", &pd)) {
287 if (power_domain_on(&pd)) { 287 if (power_domain_on(&pd)) {
288 printf("Error power on HIFI RAM\n"); 288 printf("Error power on HIFI RAM\n");
289 return -EIO; 289 return -EIO;
290 } 290 }
291 } 291 }
292 } 292 }
293 293
294 printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram); 294 printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);
295 if (core_id == 0) { 295 if (core_id == 0) {
296 /* M4 use bin file */ 296 /* M4 use bin file */
297 memcpy((void *)aux_core_ram, (void *)addr, size); 297 memcpy((void *)aux_core_ram, (void *)addr, size);
298 } else { 298 } else {
299 /* HIFI use elf file */ 299 /* HIFI use elf file */
300 if (!valid_elf_image(addr)) 300 if (!valid_elf_image(addr))
301 return -1; 301 return -1;
302 addr = load_elf_image_shdr(addr); 302 addr = load_elf_image_shdr(addr);
303 } 303 }
304 304
305 printf("Start %s\n", core_id == 0 ? "M4" : "HIFI"); 305 printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
306 306
307 if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE) 307 if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
308 return -EIO; 308 return -EIO;
309 309
310 printf("bootaux complete\n"); 310 printf("bootaux complete\n");
311 return 0; 311 return 0;
312 } 312 }
313 #endif 313 #endif
314 314
315 int arch_auxiliary_core_check_up(u32 core_id) 315 int arch_auxiliary_core_check_up(u32 core_id)
316 { 316 {
317 sc_rsrc_t core_rsrc; 317 sc_rsrc_t core_rsrc;
318 sc_pm_power_mode_t power_mode; 318 sc_pm_power_mode_t power_mode;
319 319
320 switch (core_id) { 320 switch (core_id) {
321 case 0: 321 case 0:
322 core_rsrc = SC_R_M4_0_PID0; 322 core_rsrc = SC_R_M4_0_PID0;
323 break; 323 break;
324 #ifdef CONFIG_IMX8QM 324 #ifdef CONFIG_IMX8QM
325 case 1: 325 case 1:
326 core_rsrc = SC_R_M4_1_PID0; 326 core_rsrc = SC_R_M4_1_PID0;
327 break; 327 break;
328 #endif 328 #endif
329 default: 329 default:
330 printf("Not support this core, ID:%u\n", core_id); 330 printf("Not support this core, ID:%u\n", core_id);
331 return 0; 331 return 0;
332 } 332 }
333 333
334 if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE) 334 if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE)
335 return 0; 335 return 0;
336 336
337 if (power_mode != SC_PM_PW_MODE_OFF) 337 if (power_mode != SC_PM_PW_MODE_OFF)
338 return 1; 338 return 1;
339 339
340 return 0; 340 return 0;
341 } 341 }
342 #endif 342 #endif
343 343
344 int print_bootinfo(void) 344 int print_bootinfo(void)
345 { 345 {
346 enum boot_device bt_dev = get_boot_device(); 346 enum boot_device bt_dev = get_boot_device();
347 347
348 puts("Boot: "); 348 puts("Boot: ");
349 switch (bt_dev) { 349 switch (bt_dev) {
350 case SD1_BOOT: 350 case SD1_BOOT:
351 puts("SD0\n"); 351 puts("SD0\n");
352 break; 352 break;
353 case SD2_BOOT: 353 case SD2_BOOT:
354 puts("SD1\n"); 354 puts("SD1\n");
355 break; 355 break;
356 case SD3_BOOT: 356 case SD3_BOOT:
357 puts("SD2\n"); 357 puts("SD2\n");
358 break; 358 break;
359 case MMC1_BOOT: 359 case MMC1_BOOT:
360 puts("MMC0\n"); 360 puts("MMC0\n");
361 break; 361 break;
362 case MMC2_BOOT: 362 case MMC2_BOOT:
363 puts("MMC1\n"); 363 puts("MMC1\n");
364 break; 364 break;
365 case MMC3_BOOT: 365 case MMC3_BOOT:
366 puts("MMC2\n"); 366 puts("MMC2\n");
367 break; 367 break;
368 case FLEXSPI_BOOT: 368 case FLEXSPI_BOOT:
369 puts("FLEXSPI\n"); 369 puts("FLEXSPI\n");
370 break; 370 break;
371 case SATA_BOOT: 371 case SATA_BOOT:
372 puts("SATA\n"); 372 puts("SATA\n");
373 break; 373 break;
374 case NAND_BOOT: 374 case NAND_BOOT:
375 puts("NAND\n"); 375 puts("NAND\n");
376 break; 376 break;
377 case USB_BOOT: 377 case USB_BOOT:
378 puts("USB\n"); 378 puts("USB\n");
379 break; 379 break;
380 default: 380 default:
381 printf("Unknown device %u\n", bt_dev); 381 printf("Unknown device %u\n", bt_dev);
382 break; 382 break;
383 } 383 }
384 384
385 return 0; 385 return 0;
386 } 386 }
387 387
388 enum boot_device get_boot_device(void) 388 enum boot_device get_boot_device(void)
389 { 389 {
390 enum boot_device boot_dev = SD1_BOOT; 390 enum boot_device boot_dev = SD1_BOOT;
391 391
392 sc_rsrc_t dev_rsrc; 392 sc_rsrc_t dev_rsrc;
393 393
394 /* Note we only support android in EMMC SDHC0 */ 394 /* Note we only support android in EMMC SDHC0 */
395 if (IS_ENABLED(CONFIG_XEN)) 395 if (IS_ENABLED(CONFIG_XEN))
396 return MMC1_BOOT; 396 return MMC1_BOOT;
397 397
398 sc_misc_get_boot_dev(-1, &dev_rsrc); 398 sc_misc_get_boot_dev(-1, &dev_rsrc);
399 399
400 switch (dev_rsrc) { 400 switch (dev_rsrc) {
401 case SC_R_SDHC_0: 401 case SC_R_SDHC_0:
402 boot_dev = MMC1_BOOT; 402 boot_dev = MMC1_BOOT;
403 break; 403 break;
404 case SC_R_SDHC_1: 404 case SC_R_SDHC_1:
405 boot_dev = SD2_BOOT; 405 boot_dev = SD2_BOOT;
406 break; 406 break;
407 case SC_R_SDHC_2: 407 case SC_R_SDHC_2:
408 boot_dev = SD3_BOOT; 408 boot_dev = SD3_BOOT;
409 break; 409 break;
410 case SC_R_NAND: 410 case SC_R_NAND:
411 boot_dev = NAND_BOOT; 411 boot_dev = NAND_BOOT;
412 break; 412 break;
413 case SC_R_FSPI_0: 413 case SC_R_FSPI_0:
414 boot_dev = FLEXSPI_BOOT; 414 boot_dev = FLEXSPI_BOOT;
415 break; 415 break;
416 case SC_R_SATA_0: 416 case SC_R_SATA_0:
417 boot_dev = SATA_BOOT; 417 boot_dev = SATA_BOOT;
418 break; 418 break;
419 case SC_R_USB_0: 419 case SC_R_USB_0:
420 case SC_R_USB_1: 420 case SC_R_USB_1:
421 case SC_R_USB_2: 421 case SC_R_USB_2:
422 boot_dev = USB_BOOT; 422 boot_dev = USB_BOOT;
423 break; 423 break;
424 default: 424 default:
425 break; 425 break;
426 } 426 }
427 427
428 return boot_dev; 428 return boot_dev;
429 } 429 }
430 430
431 bool is_usb_boot(void) 431 bool is_usb_boot(void)
432 { 432 {
433 return get_boot_device() == USB_BOOT; 433 return get_boot_device() == USB_BOOT;
434 } 434 }
435 435
436 #ifdef CONFIG_SERIAL_TAG 436 #ifdef CONFIG_SERIAL_TAG
437 #define FUSE_UNIQUE_ID_WORD0 16 437 #define FUSE_UNIQUE_ID_WORD0 16
438 #define FUSE_UNIQUE_ID_WORD1 17 438 #define FUSE_UNIQUE_ID_WORD1 17
439 void get_board_serial(struct tag_serialnr *serialnr) 439 void get_board_serial(struct tag_serialnr *serialnr)
440 { 440 {
441 sc_err_t err; 441 sc_err_t err;
442 uint32_t val1 = 0, val2 = 0; 442 uint32_t val1 = 0, val2 = 0;
443 uint32_t word1, word2; 443 uint32_t word1, word2;
444 444
445 word1 = FUSE_UNIQUE_ID_WORD0; 445 word1 = FUSE_UNIQUE_ID_WORD0;
446 word2 = FUSE_UNIQUE_ID_WORD1; 446 word2 = FUSE_UNIQUE_ID_WORD1;
447 447
448 err = sc_misc_otp_fuse_read(-1, word1, &val1); 448 err = sc_misc_otp_fuse_read(-1, word1, &val1);
449 if (err != SC_ERR_NONE) { 449 if (err != SC_ERR_NONE) {
450 printf("%s fuse %d read error: %d\n", __func__,word1, err); 450 printf("%s fuse %d read error: %d\n", __func__,word1, err);
451 return; 451 return;
452 } 452 }
453 453
454 err = sc_misc_otp_fuse_read(-1, word2, &val2); 454 err = sc_misc_otp_fuse_read(-1, word2, &val2);
455 if (err != SC_ERR_NONE) { 455 if (err != SC_ERR_NONE) {
456 printf("%s fuse %d read error: %d\n", __func__, word2, err); 456 printf("%s fuse %d read error: %d\n", __func__, word2, err);
457 return; 457 return;
458 } 458 }
459 serialnr->low = val1; 459 serialnr->low = val1;
460 serialnr->high = val2; 460 serialnr->high = val2;
461 } 461 }
462 #endif /*CONFIG_SERIAL_TAG*/ 462 #endif /*CONFIG_SERIAL_TAG*/
463 463
464 __weak int board_mmc_get_env_dev(int devno) 464 __weak int board_mmc_get_env_dev(int devno)
465 { 465 {
466 return devno; 466 return devno;
467 } 467 }
468 468
469 int mmc_get_env_dev(void) 469 int mmc_get_env_dev(void)
470 { 470 {
471 sc_rsrc_t dev_rsrc; 471 sc_rsrc_t dev_rsrc;
472 int devno; 472 int devno;
473 473
474 sc_misc_get_boot_dev(-1, &dev_rsrc); 474 sc_misc_get_boot_dev(-1, &dev_rsrc);
475 475
476 switch (dev_rsrc) { 476 switch (dev_rsrc) {
477 case SC_R_SDHC_0: 477 case SC_R_SDHC_0:
478 devno = 0; 478 devno = 0;
479 break; 479 break;
480 case SC_R_SDHC_1: 480 case SC_R_SDHC_1:
481 devno = 1; 481 devno = 1;
482 break; 482 break;
483 case SC_R_SDHC_2: 483 case SC_R_SDHC_2:
484 devno = 2; 484 devno = 2;
485 break; 485 break;
486 default: 486 default:
487 /* If not boot from sd/mmc, use default value */ 487 /* If not boot from sd/mmc, use default value */
488 return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); 488 return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
489 } 489 }
490 490
491 return board_mmc_get_env_dev(devno); 491 return board_mmc_get_env_dev(devno);
492 } 492 }
493 493
494 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */ 494 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
495 495
496 static sc_faddr_t reserve_optee_shm(sc_faddr_t addr_start) 496 static sc_faddr_t reserve_optee_shm(sc_faddr_t addr_start)
497 { 497 {
498 /* OPTEE has a share memory at its top address, 498 /* OPTEE has a share memory at its top address,
499 * ATF assigns the share memory to non-secure os partition for share with kernel 499 * ATF assigns the share memory to non-secure os partition for share with kernel
500 * We should not add this share memory to DDR bank, as this memory is dedicated for 500 * We should not add this share memory to DDR bank, as this memory is dedicated for
501 * optee, optee driver will memremap it and can't be used by system malloc. 501 * optee, optee driver will memremap it and can't be used by system malloc.
502 */ 502 */
503 503
504 sc_faddr_t optee_start = rom_pointer[0]; 504 sc_faddr_t optee_start = rom_pointer[0];
505 sc_faddr_t optee_size = rom_pointer[1]; 505 sc_faddr_t optee_size = rom_pointer[1];
506 506
507 if (optee_size && optee_start <= addr_start && 507 if (optee_size && optee_start <= addr_start &&
508 addr_start < optee_start + optee_size) { 508 addr_start < optee_start + optee_size) {
509 debug("optee 0x%llx 0x%llx, addr_start 0x%llx\n", 509 debug("optee 0x%llx 0x%llx, addr_start 0x%llx\n",
510 optee_start, optee_size, addr_start); 510 optee_start, optee_size, addr_start);
511 return optee_start + optee_size; 511 return optee_start + optee_size;
512 } 512 }
513 513
514 return addr_start; 514 return addr_start;
515 } 515 }
516 516
517 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, 517 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
518 sc_faddr_t *addr_end) 518 sc_faddr_t *addr_end)
519 { 519 {
520 sc_faddr_t start, end; 520 sc_faddr_t start, end;
521 int ret; 521 int ret;
522 bool owned; 522 bool owned;
523 523
524 owned = sc_rm_is_memreg_owned(-1, mr); 524 owned = sc_rm_is_memreg_owned(-1, mr);
525 if (owned) { 525 if (owned) {
526 ret = sc_rm_get_memreg_info(-1, mr, &start, &end); 526 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
527 if (ret) { 527 if (ret) {
528 printf("Memreg get info failed, %d\n", ret); 528 printf("Memreg get info failed, %d\n", ret);
529 return -EINVAL; 529 return -EINVAL;
530 } 530 }
531 debug("0x%llx -- 0x%llx\n", start, end); 531 debug("0x%llx -- 0x%llx\n", start, end);
532 *addr_start = reserve_optee_shm(start); 532 *addr_start = reserve_optee_shm(start);
533 *addr_end = end; 533 *addr_end = end;
534 534
535 return 0; 535 return 0;
536 } 536 }
537 537
538 return -EINVAL; 538 return -EINVAL;
539 } 539 }
540 540
541 phys_size_t get_effective_memsize(void) 541 phys_size_t get_effective_memsize(void)
542 { 542 {
543 sc_rm_mr_t mr; 543 sc_rm_mr_t mr;
544 sc_faddr_t start, end, end1, start_aligned; 544 sc_faddr_t start, end, end1, start_aligned;
545 int err; 545 int err;
546 546
547 if (IS_ENABLED(CONFIG_XEN)) 547 if (IS_ENABLED(CONFIG_XEN))
548 return PHYS_SDRAM_1_SIZE; 548 return PHYS_SDRAM_1_SIZE;
549 549
550 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; 550 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
551 for (mr = 0; mr < 64; mr++) { 551 for (mr = 0; mr < 64; mr++) {
552 err = get_owned_memreg(mr, &start, &end); 552 err = get_owned_memreg(mr, &start, &end);
553 if (!err) { 553 if (!err) {
554 start_aligned = roundup(start, MEMSTART_ALIGNMENT); 554 start_aligned = roundup(start, MEMSTART_ALIGNMENT);
555 /* Too small memory region, not use it */ 555 /* Too small memory region, not use it */
556 if (start_aligned > end) 556 if (start_aligned > end)
557 continue; 557 continue;
558 558
559 /* Find the memory region runs the U-Boot */ 559 /* Find the memory region runs the U-Boot */
560 if (start >= PHYS_SDRAM_1 && start <= end1 && 560 if (start >= PHYS_SDRAM_1 && start <= end1 &&
561 (start <= CONFIG_SYS_TEXT_BASE && 561 (start <= CONFIG_SYS_TEXT_BASE &&
562 end >= CONFIG_SYS_TEXT_BASE)) { 562 end >= CONFIG_SYS_TEXT_BASE)) {
563 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + 563 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
564 PHYS_SDRAM_1_SIZE)) 564 PHYS_SDRAM_1_SIZE))
565 return (end - PHYS_SDRAM_1 + 1); 565 return (end - PHYS_SDRAM_1 + 1);
566 else 566 else
567 return PHYS_SDRAM_1_SIZE; 567 return PHYS_SDRAM_1_SIZE;
568 } 568 }
569 } 569 }
570 } 570 }
571 571
572 return PHYS_SDRAM_1_SIZE; 572 return PHYS_SDRAM_1_SIZE;
573 } 573 }
574 574
575 int dram_init(void) 575 int dram_init(void)
576 { 576 {
577 sc_rm_mr_t mr; 577 sc_rm_mr_t mr;
578 sc_faddr_t start, end, end1, end2; 578 sc_faddr_t start, end, end1, end2;
579 int err; 579 int err;
580 580
581 if (IS_ENABLED(CONFIG_XEN)) { 581 if (IS_ENABLED(CONFIG_XEN)) {
582 gd->ram_size = PHYS_SDRAM_1_SIZE; 582 gd->ram_size = PHYS_SDRAM_1_SIZE;
583 gd->ram_size += PHYS_SDRAM_2_SIZE; 583 gd->ram_size += PHYS_SDRAM_2_SIZE;
584 584
585 return 0; 585 return 0;
586 } 586 }
587 587
588 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; 588 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
589 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; 589 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
590 for (mr = 0; mr < 64; mr++) { 590 for (mr = 0; mr < 64; mr++) {
591 err = get_owned_memreg(mr, &start, &end); 591 err = get_owned_memreg(mr, &start, &end);
592 if (!err) { 592 if (!err) {
593 start = roundup(start, MEMSTART_ALIGNMENT); 593 start = roundup(start, MEMSTART_ALIGNMENT);
594 /* Too small memory region, not use it */ 594 /* Too small memory region, not use it */
595 if (start > end) 595 if (start > end)
596 continue; 596 continue;
597 597
598 if (start >= PHYS_SDRAM_1 && start <= end1) { 598 if (start >= PHYS_SDRAM_1 && start <= end1) {
599 if ((end + 1) <= end1) 599 if ((end + 1) <= end1)
600 gd->ram_size += end - start + 1; 600 gd->ram_size += end - start + 1;
601 else 601 else
602 gd->ram_size += end1 - start; 602 gd->ram_size += end1 - start;
603 } else if (start >= PHYS_SDRAM_2 && start <= end2) { 603 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
604 if ((end + 1) <= end2) 604 if ((end + 1) <= end2)
605 gd->ram_size += end - start + 1; 605 gd->ram_size += end - start + 1;
606 else 606 else
607 gd->ram_size += end2 - start; 607 gd->ram_size += end2 - start;
608 } 608 }
609 } 609 }
610 } 610 }
611 611
612 /* If error, set to the default value */ 612 /* If error, set to the default value */
613 if (!gd->ram_size) { 613 if (!gd->ram_size) {
614 gd->ram_size = PHYS_SDRAM_1_SIZE; 614 gd->ram_size = PHYS_SDRAM_1_SIZE;
615 gd->ram_size += PHYS_SDRAM_2_SIZE; 615 gd->ram_size += PHYS_SDRAM_2_SIZE;
616 } 616 }
617 return 0; 617 return 0;
618 } 618 }
619 619
620 static void dram_bank_sort(int current_bank) 620 static void dram_bank_sort(int current_bank)
621 { 621 {
622 phys_addr_t start; 622 phys_addr_t start;
623 phys_size_t size; 623 phys_size_t size;
624 624
625 while (current_bank > 0) { 625 while (current_bank > 0) {
626 if (gd->bd->bi_dram[current_bank - 1].start > 626 if (gd->bd->bi_dram[current_bank - 1].start >
627 gd->bd->bi_dram[current_bank].start) { 627 gd->bd->bi_dram[current_bank].start) {
628 start = gd->bd->bi_dram[current_bank - 1].start; 628 start = gd->bd->bi_dram[current_bank - 1].start;
629 size = gd->bd->bi_dram[current_bank - 1].size; 629 size = gd->bd->bi_dram[current_bank - 1].size;
630 630
631 gd->bd->bi_dram[current_bank - 1].start = 631 gd->bd->bi_dram[current_bank - 1].start =
632 gd->bd->bi_dram[current_bank].start; 632 gd->bd->bi_dram[current_bank].start;
633 gd->bd->bi_dram[current_bank - 1].size = 633 gd->bd->bi_dram[current_bank - 1].size =
634 gd->bd->bi_dram[current_bank].size; 634 gd->bd->bi_dram[current_bank].size;
635 635
636 gd->bd->bi_dram[current_bank].start = start; 636 gd->bd->bi_dram[current_bank].start = start;
637 gd->bd->bi_dram[current_bank].size = size; 637 gd->bd->bi_dram[current_bank].size = size;
638 } 638 }
639 current_bank--; 639 current_bank--;
640 } 640 }
641 } 641 }
642 642
643 int dram_init_banksize(void) 643 int dram_init_banksize(void)
644 { 644 {
645 sc_rm_mr_t mr; 645 sc_rm_mr_t mr;
646 sc_faddr_t start, end, end1, end2; 646 sc_faddr_t start, end, end1, end2;
647 int i = 0; 647 int i = 0;
648 int err; 648 int err;
649 649
650 if (IS_ENABLED(CONFIG_XEN)) { 650 if (IS_ENABLED(CONFIG_XEN)) {
651 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 651 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
652 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 652 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
653 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 653 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
654 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 654 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
655 655
656 return 0; 656 return 0;
657 } 657 }
658 658
659 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; 659 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
660 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; 660 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
661 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { 661 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
662 err = get_owned_memreg(mr, &start, &end); 662 err = get_owned_memreg(mr, &start, &end);
663 if (!err) { 663 if (!err) {
664 start = roundup(start, MEMSTART_ALIGNMENT); 664 start = roundup(start, MEMSTART_ALIGNMENT);
665 if (start > end) /* Small memory region, no use it */ 665 if (start > end) /* Small memory region, no use it */
666 continue; 666 continue;
667 667
668 if (start >= PHYS_SDRAM_1 && start <= end1) { 668 if (start >= PHYS_SDRAM_1 && start <= end1) {
669 gd->bd->bi_dram[i].start = start; 669 gd->bd->bi_dram[i].start = start;
670 670
671 if ((end + 1) <= end1) 671 if ((end + 1) <= end1)
672 gd->bd->bi_dram[i].size = 672 gd->bd->bi_dram[i].size =
673 end - start + 1; 673 end - start + 1;
674 else 674 else
675 gd->bd->bi_dram[i].size = end1 - start; 675 gd->bd->bi_dram[i].size = end1 - start;
676 676
677 dram_bank_sort(i); 677 dram_bank_sort(i);
678 i++; 678 i++;
679 } else if (start >= PHYS_SDRAM_2 && start <= end2) { 679 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
680 gd->bd->bi_dram[i].start = start; 680 gd->bd->bi_dram[i].start = start;
681 681
682 if ((end + 1) <= end2) 682 if ((end + 1) <= end2)
683 gd->bd->bi_dram[i].size = 683 gd->bd->bi_dram[i].size =
684 end - start + 1; 684 end - start + 1;
685 else 685 else
686 gd->bd->bi_dram[i].size = end2 - start; 686 gd->bd->bi_dram[i].size = end2 - start;
687 687
688 dram_bank_sort(i); 688 dram_bank_sort(i);
689 i++; 689 i++;
690 } 690 }
691 } 691 }
692 } 692 }
693 693
694 /* If error, set to the default value */ 694 /* If error, set to the default value */
695 if (!i) { 695 if (!i) {
696 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 696 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
697 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 697 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
698 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 698 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
699 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 699 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
700 } 700 }
701 701
702 return 0; 702 return 0;
703 } 703 }
704 704
705 static u64 get_block_attrs(sc_faddr_t addr_start) 705 static u64 get_block_attrs(sc_faddr_t addr_start)
706 { 706 {
707 u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | 707 u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
708 PTE_BLOCK_PXN | PTE_BLOCK_UXN; 708 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
709 709
710 if ((addr_start >= PHYS_SDRAM_1 && 710 if ((addr_start >= PHYS_SDRAM_1 &&
711 addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) || 711 addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
712 (addr_start >= PHYS_SDRAM_2 && 712 (addr_start >= PHYS_SDRAM_2 &&
713 addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) 713 addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
714 #ifdef CONFIG_IMX_TRUSTY_OS 714 #ifdef CONFIG_IMX_TRUSTY_OS
715 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); 715 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE);
716 #else 716 #else
717 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); 717 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
718 #endif 718 #endif
719 719
720 return attr; 720 return attr;
721 } 721 }
722 722
723 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end) 723 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
724 { 724 {
725 sc_faddr_t end1, end2; 725 sc_faddr_t end1, end2;
726 726
727 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; 727 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
728 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; 728 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
729 729
730 if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) { 730 if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
731 if ((addr_end + 1) > end1) 731 if ((addr_end + 1) > end1)
732 return end1 - addr_start; 732 return end1 - addr_start;
733 } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) { 733 } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
734 if ((addr_end + 1) > end2) 734 if ((addr_end + 1) > end2)
735 return end2 - addr_start; 735 return end2 - addr_start;
736 } 736 }
737 737
738 return (addr_end - addr_start + 1); 738 return (addr_end - addr_start + 1);
739 } 739 }
740 740
741 #define MAX_PTE_ENTRIES 512 741 #define MAX_PTE_ENTRIES 512
742 #define MAX_MEM_MAP_REGIONS 16 742 #define MAX_MEM_MAP_REGIONS 16
743 743
744 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS]; 744 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
745 struct mm_region *mem_map = imx8_mem_map; 745 struct mm_region *mem_map = imx8_mem_map;
746 746
747 void enable_caches(void) 747 void enable_caches(void)
748 { 748 {
749 sc_rm_mr_t mr; 749 sc_rm_mr_t mr;
750 sc_faddr_t start, end; 750 sc_faddr_t start, end;
751 int err, i; 751 int err, i;
752 752
753 if (IS_ENABLED(CONFIG_XEN)) { 753 if (IS_ENABLED(CONFIG_XEN)) {
754 imx8_mem_map[0].virt = 0x00000000UL; 754 imx8_mem_map[0].virt = 0x00000000UL;
755 imx8_mem_map[0].phys = 0x00000000UL; 755 imx8_mem_map[0].phys = 0x00000000UL;
756 imx8_mem_map[0].size = 0x80000000UL; 756 imx8_mem_map[0].size = 0x39000000UL;
757 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 757 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
758 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; 758 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
759 imx8_mem_map[1].virt = 0x80000000UL; 759 imx8_mem_map[1].virt = 0x39000000UL;
760 imx8_mem_map[1].phys = 0x80000000UL; 760 imx8_mem_map[1].phys = 0x39000000UL;
761 imx8_mem_map[1].size = 0x80000000UL; 761 imx8_mem_map[1].size = 0x01000000UL;
762 imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); 762 imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE);
763 763
764 imx8_mem_map[2].virt = 0x100000000UL; 764 imx8_mem_map[2].virt = 0x40000000UL;
765 imx8_mem_map[2].phys = 0x100000000UL; 765 imx8_mem_map[2].phys = 0x40000000UL;
766 imx8_mem_map[2].size = 0x100000000UL; 766 imx8_mem_map[2].size = 0x40000000UL;
767 imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 767 imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
768 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
769
770 imx8_mem_map[3].virt = 0x80000000UL;
771 imx8_mem_map[3].phys = 0x80000000UL;
772 imx8_mem_map[3].size = 0x80000000UL;
773 imx8_mem_map[3].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE);
774
775 imx8_mem_map[4].virt = 0x100000000UL;
776 imx8_mem_map[4].phys = 0x100000000UL;
777 imx8_mem_map[4].size = 0x100000000UL;
778 imx8_mem_map[4].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
768 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; 779 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
769 780
770 icache_enable(); 781 icache_enable();
771 dcache_enable(); 782 dcache_enable();
772 783
773 return; 784 return;
774 } 785 }
775 786
776 /* Create map for registers access from 0x1c000000 to 0x80000000*/ 787 /* Create map for registers access from 0x1c000000 to 0x80000000*/
777 imx8_mem_map[0].virt = 0x1c000000UL; 788 imx8_mem_map[0].virt = 0x1c000000UL;
778 imx8_mem_map[0].phys = 0x1c000000UL; 789 imx8_mem_map[0].phys = 0x1c000000UL;
779 imx8_mem_map[0].size = 0x64000000UL; 790 imx8_mem_map[0].size = 0x64000000UL;
780 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 791 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
781 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; 792 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
782 793
783 i = 1; 794 i = 1;
784 795
785 #ifdef CONFIG_IMX_VSERVICE_SHARED_BUFFER 796 #ifdef CONFIG_IMX_VSERVICE_SHARED_BUFFER
786 imx8_mem_map[i].virt = CONFIG_IMX_VSERVICE_SHARED_BUFFER; 797 imx8_mem_map[i].virt = CONFIG_IMX_VSERVICE_SHARED_BUFFER;
787 imx8_mem_map[i].phys = CONFIG_IMX_VSERVICE_SHARED_BUFFER; 798 imx8_mem_map[i].phys = CONFIG_IMX_VSERVICE_SHARED_BUFFER;
788 imx8_mem_map[i].size = CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE; 799 imx8_mem_map[i].size = CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE;
789 imx8_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 800 imx8_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
790 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; 801 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
791 i++; 802 i++;
792 #endif 803 #endif
793 804
794 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) { 805 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
795 err = get_owned_memreg(mr, &start, &end); 806 err = get_owned_memreg(mr, &start, &end);
796 if (!err) { 807 if (!err) {
797 imx8_mem_map[i].virt = start; 808 imx8_mem_map[i].virt = start;
798 imx8_mem_map[i].phys = start; 809 imx8_mem_map[i].phys = start;
799 imx8_mem_map[i].size = get_block_size(start, end); 810 imx8_mem_map[i].size = get_block_size(start, end);
800 imx8_mem_map[i].attrs = get_block_attrs(start); 811 imx8_mem_map[i].attrs = get_block_attrs(start);
801 i++; 812 i++;
802 } 813 }
803 } 814 }
804 815
805 if (i < MAX_MEM_MAP_REGIONS) { 816 if (i < MAX_MEM_MAP_REGIONS) {
806 imx8_mem_map[i].size = 0; 817 imx8_mem_map[i].size = 0;
807 imx8_mem_map[i].attrs = 0; 818 imx8_mem_map[i].attrs = 0;
808 } else { 819 } else {
809 puts("Error, need more MEM MAP REGIONS reserved\n"); 820 puts("Error, need more MEM MAP REGIONS reserved\n");
810 icache_enable(); 821 icache_enable();
811 return; 822 return;
812 } 823 }
813 824
814 for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) { 825 for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
815 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n", 826 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
816 i, imx8_mem_map[i].virt, imx8_mem_map[i].phys, 827 i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
817 imx8_mem_map[i].size, imx8_mem_map[i].attrs); 828 imx8_mem_map[i].size, imx8_mem_map[i].attrs);
818 } 829 }
819 830
820 icache_enable(); 831 icache_enable();
821 dcache_enable(); 832 dcache_enable();
822 } 833 }
823 834
824 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) 835 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
825 u64 get_page_table_size(void) 836 u64 get_page_table_size(void)
826 { 837 {
827 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); 838 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
828 u64 size = 0; 839 u64 size = 0;
829 840
830 /* 841 /*
831 * For each memory region, the max table size: 842 * For each memory region, the max table size:
832 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table 843 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
833 */ 844 */
834 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt; 845 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
835 846
836 /* 847 /*
837 * We need to duplicate our page table once to have an emergency pt to 848 * We need to duplicate our page table once to have an emergency pt to
838 * resort to when splitting page tables later on 849 * resort to when splitting page tables later on
839 */ 850 */
840 size *= 2; 851 size *= 2;
841 852
842 /* 853 /*
843 * We may need to split page tables later on if dcache settings change, 854 * We may need to split page tables later on if dcache settings change,
844 * so reserve up to 4 (random pick) page tables for that. 855 * so reserve up to 4 (random pick) page tables for that.
845 */ 856 */
846 size += one_pt * 4; 857 size += one_pt * 4;
847 858
848 return size; 859 return size;
849 } 860 }
850 #endif 861 #endif
851 862
852 #if defined(CONFIG_IMX8QM) 863 #if defined(CONFIG_IMX8QM)
853 #define FUSE_MAC0_WORD0 452 864 #define FUSE_MAC0_WORD0 452
854 #define FUSE_MAC0_WORD1 453 865 #define FUSE_MAC0_WORD1 453
855 #define FUSE_MAC1_WORD0 454 866 #define FUSE_MAC1_WORD0 454
856 #define FUSE_MAC1_WORD1 455 867 #define FUSE_MAC1_WORD1 455
857 #elif defined(CONFIG_IMX8QXP) || defined (CONFIG_IMX8DXL) 868 #elif defined(CONFIG_IMX8QXP) || defined (CONFIG_IMX8DXL)
858 #define FUSE_MAC0_WORD0 708 869 #define FUSE_MAC0_WORD0 708
859 #define FUSE_MAC0_WORD1 709 870 #define FUSE_MAC0_WORD1 709
860 #define FUSE_MAC1_WORD0 710 871 #define FUSE_MAC1_WORD0 710
861 #define FUSE_MAC1_WORD1 711 872 #define FUSE_MAC1_WORD1 711
862 #endif 873 #endif
863 874
864 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 875 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
865 { 876 {
866 u32 word[2], val[2] = {}; 877 u32 word[2], val[2] = {};
867 int i, ret; 878 int i, ret;
868 879
869 if (dev_id == 0) { 880 if (dev_id == 0) {
870 word[0] = FUSE_MAC0_WORD0; 881 word[0] = FUSE_MAC0_WORD0;
871 word[1] = FUSE_MAC0_WORD1; 882 word[1] = FUSE_MAC0_WORD1;
872 } else { 883 } else {
873 word[0] = FUSE_MAC1_WORD0; 884 word[0] = FUSE_MAC1_WORD0;
874 word[1] = FUSE_MAC1_WORD1; 885 word[1] = FUSE_MAC1_WORD1;
875 } 886 }
876 887
877 for (i = 0; i < 2; i++) { 888 for (i = 0; i < 2; i++) {
878 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]); 889 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
879 if (ret < 0) 890 if (ret < 0)
880 goto err; 891 goto err;
881 } 892 }
882 893
883 mac[0] = val[0]; 894 mac[0] = val[0];
884 mac[1] = val[0] >> 8; 895 mac[1] = val[0] >> 8;
885 mac[2] = val[0] >> 16; 896 mac[2] = val[0] >> 16;
886 mac[3] = val[0] >> 24; 897 mac[3] = val[0] >> 24;
887 mac[4] = val[1]; 898 mac[4] = val[1];
888 mac[5] = val[1] >> 8; 899 mac[5] = val[1] >> 8;
889 900
890 debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", 901 debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
891 __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 902 __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
892 return; 903 return;
893 err: 904 err:
894 printf("%s: fuse %d, err: %d\n", __func__, word[i], ret); 905 printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
895 } 906 }
896 907
897 u32 get_cpu_rev(void) 908 u32 get_cpu_rev(void)
898 { 909 {
899 u32 id = 0, rev = 0; 910 u32 id = 0, rev = 0;
900 int ret; 911 int ret;
901 912
902 ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id); 913 ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
903 if (ret) 914 if (ret)
904 return 0; 915 return 0;
905 916
906 rev = (id >> 5) & 0xf; 917 rev = (id >> 5) & 0xf;
907 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ 918 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
908 919
909 return (id << 12) | rev; 920 return (id << 12) | rev;
910 } 921 }
911 922
912 static bool check_device_power_off(struct udevice *dev, 923 static bool check_device_power_off(struct udevice *dev,
913 const char* permanent_on_devices[], int size) 924 const char* permanent_on_devices[], int size)
914 { 925 {
915 int i; 926 int i;
916 927
917 for (i = 0; i < size; i++) { 928 for (i = 0; i < size; i++) {
918 if (!strcmp(dev->name, permanent_on_devices[i])) 929 if (!strcmp(dev->name, permanent_on_devices[i]))
919 return false; 930 return false;
920 } 931 }
921 932
922 return true; 933 return true;
923 } 934 }
924 935
925 void power_off_pd_devices(const char* permanent_on_devices[], int size) 936 void power_off_pd_devices(const char* permanent_on_devices[], int size)
926 { 937 {
927 struct udevice *dev; 938 struct udevice *dev;
928 struct power_domain pd; 939 struct power_domain pd;
929 940
930 for (uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); dev; 941 for (uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); dev;
931 uclass_find_next_device(&dev)) { 942 uclass_find_next_device(&dev)) {
932 943
933 if (device_active(dev)) { 944 if (device_active(dev)) {
934 /* Power off active pd devices except the permanent power on devices */ 945 /* Power off active pd devices except the permanent power on devices */
935 if (check_device_power_off(dev, permanent_on_devices, size)) { 946 if (check_device_power_off(dev, permanent_on_devices, size)) {
936 pd.dev = dev; 947 pd.dev = dev;
937 power_domain_off(&pd); 948 power_domain_off(&pd);
938 } 949 }
939 } 950 }
940 } 951 }
941 } 952 }
942 953
943 void disconnect_from_pc(void) 954 void disconnect_from_pc(void)
944 { 955 {
945 int ret; 956 int ret;
946 struct power_domain pd; 957 struct power_domain pd;
947 958
948 if (!power_domain_lookup_name("conn_usb0", &pd)) { 959 if (!power_domain_lookup_name("conn_usb0", &pd)) {
949 ret = power_domain_on(&pd); 960 ret = power_domain_on(&pd);
950 if (ret) { 961 if (ret) {
951 printf("conn_usb0 Power up failed! (error = %d)\n", ret); 962 printf("conn_usb0 Power up failed! (error = %d)\n", ret);
952 return; 963 return;
953 } 964 }
954 965
955 writel(0x0, USB_BASE_ADDR + 0x140); 966 writel(0x0, USB_BASE_ADDR + 0x140);
956 967
957 ret = power_domain_off(&pd); 968 ret = power_domain_off(&pd);
958 if (ret) { 969 if (ret) {
959 printf("conn_usb0 Power off failed! (error = %d)\n", ret); 970 printf("conn_usb0 Power off failed! (error = %d)\n", ret);
960 return; 971 return;
961 } 972 }
962 } else { 973 } else {
963 printf("conn_usb0 finding failed!\n"); 974 printf("conn_usb0 finding failed!\n");
964 return; 975 return;
965 } 976 }
966 } 977 }
967 978
968 bool check_owned_udevice(struct udevice *dev) 979 bool check_owned_udevice(struct udevice *dev)
969 { 980 {
970 int ret; 981 int ret;
971 sc_rsrc_t resource_id; 982 sc_rsrc_t resource_id;
972 struct ofnode_phandle_args args; 983 struct ofnode_phandle_args args;
973 984
974 /* Get the resource id from its power-domain */ 985 /* Get the resource id from its power-domain */
975 ret = dev_read_phandle_with_args(dev, "power-domains", 986 ret = dev_read_phandle_with_args(dev, "power-domains",
976 "#power-domain-cells", 0, 0, &args); 987 "#power-domain-cells", 0, 0, &args);
977 if (ret) { 988 if (ret) {
978 printf("no power-domains found\n"); 989 printf("no power-domains found\n");
979 return false; 990 return false;
980 } 991 }
981 992
982 /* Get the owner partition for resource*/ 993 /* Get the owner partition for resource*/
983 resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE); 994 resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE);
984 if (resource_id == SC_R_NONE) { 995 if (resource_id == SC_R_NONE) {
985 printf("Can't find the resource id for udev %s\n", dev->name); 996 printf("Can't find the resource id for udev %s\n", dev->name);
986 return false; 997 return false;
987 } 998 }
988 999
989 debug("udev %s, resource id %d\n", dev->name, resource_id); 1000 debug("udev %s, resource id %d\n", dev->name, resource_id);
990 1001
991 return sc_rm_is_resource_owned(-1, resource_id); 1002 return sc_rm_is_resource_owned(-1, resource_id);
992 } 1003 }
993 1004
994 bool check_m4_parts_boot(void) 1005 bool check_m4_parts_boot(void)
995 { 1006 {
996 sc_rm_pt_t m4_parts[2]; 1007 sc_rm_pt_t m4_parts[2];
997 int err; 1008 int err;
998 1009
999 err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]); 1010 err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
1000 if (err != SC_ERR_NONE) { 1011 if (err != SC_ERR_NONE) {
1001 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err); 1012 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err);
1002 return false; 1013 return false;
1003 } 1014 }
1004 1015
1005 if (sc_pm_is_partition_started(-1, m4_parts[0])) 1016 if (sc_pm_is_partition_started(-1, m4_parts[0]))
1006 return true; 1017 return true;
1007 1018
1008 if (is_imx8qm()) { 1019 if (is_imx8qm()) {
1009 err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]); 1020 err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
1010 if (err != SC_ERR_NONE) { 1021 if (err != SC_ERR_NONE) {
1011 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err); 1022 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err);
1012 return false; 1023 return false;
1013 } 1024 }
1014 1025
1015 if (sc_pm_is_partition_started(-1, m4_parts[1])) 1026 if (sc_pm_is_partition_started(-1, m4_parts[1]))
1016 return true; 1027 return true;
1017 } 1028 }
1018 1029
1019 return false; 1030 return false;
1020 } 1031 }
1021 1032
1022 #ifdef CONFIG_IMX_VSERVICE 1033 #ifdef CONFIG_IMX_VSERVICE
1023 struct udevice * board_imx_vservice_find_mu(struct udevice *dev) 1034 struct udevice * board_imx_vservice_find_mu(struct udevice *dev)
1024 { 1035 {
1025 int ret; 1036 int ret;
1026 const char *m4_mu_name[2] = { 1037 const char *m4_mu_name[2] = {
1027 "mu@5d230000", 1038 "mu@5d230000",
1028 "mu@5d240000" 1039 "mu@5d240000"
1029 }; 1040 };
1030 struct udevice *m4_mu[2]; 1041 struct udevice *m4_mu[2];
1031 sc_rm_pt_t m4_parts[2]; 1042 sc_rm_pt_t m4_parts[2];
1032 int err; 1043 int err;
1033 struct ofnode_phandle_args args; 1044 struct ofnode_phandle_args args;
1034 sc_rsrc_t resource_id; 1045 sc_rsrc_t resource_id;
1035 sc_rm_pt_t resource_part; 1046 sc_rm_pt_t resource_part;
1036 1047
1037 /* Get the resource id from its power-domain */ 1048 /* Get the resource id from its power-domain */
1038 ret = dev_read_phandle_with_args(dev, "power-domains", 1049 ret = dev_read_phandle_with_args(dev, "power-domains",
1039 "#power-domain-cells", 0, 0, &args); 1050 "#power-domain-cells", 0, 0, &args);
1040 if (ret) { 1051 if (ret) {
1041 printf("Can't find the power-domains property for udev %s\n", dev->name); 1052 printf("Can't find the power-domains property for udev %s\n", dev->name);
1042 return NULL; 1053 return NULL;
1043 } 1054 }
1044 1055
1045 /* Get the owner partition for resource*/ 1056 /* Get the owner partition for resource*/
1046 resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE); 1057 resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE);
1047 if (resource_id == SC_R_NONE) { 1058 if (resource_id == SC_R_NONE) {
1048 printf("Can't find the resource id for udev %s\n", dev->name); 1059 printf("Can't find the resource id for udev %s\n", dev->name);
1049 return NULL; 1060 return NULL;
1050 } 1061 }
1051 1062
1052 err = sc_rm_get_resource_owner(-1, resource_id, &resource_part); 1063 err = sc_rm_get_resource_owner(-1, resource_id, &resource_part);
1053 if (err != SC_ERR_NONE) { 1064 if (err != SC_ERR_NONE) {
1054 printf("%s get resource [%d] owner error: %d\n", __func__, resource_id, err); 1065 printf("%s get resource [%d] owner error: %d\n", __func__, resource_id, err);
1055 return NULL; 1066 return NULL;
1056 } 1067 }
1057 1068
1058 debug("udev %s, resource id %d, resource part %d\n", dev->name, resource_id, resource_part); 1069 debug("udev %s, resource id %d, resource part %d\n", dev->name, resource_id, resource_part);
1059 1070
1060 /* MU8 for communication between M4_0 and u-boot, MU9 for M4_1 and u-boot */ 1071 /* MU8 for communication between M4_0 and u-boot, MU9 for M4_1 and u-boot */
1061 err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]); 1072 err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
1062 if (err != SC_ERR_NONE) { 1073 if (err != SC_ERR_NONE) {
1063 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err); 1074 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err);
1064 return NULL; 1075 return NULL;
1065 } 1076 }
1066 1077
1067 ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[0], &m4_mu[0]); 1078 ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[0], &m4_mu[0]);
1068 if (!ret) { 1079 if (!ret) {
1069 /* If the i2c is in m4_0 partition, return the mu8 */ 1080 /* If the i2c is in m4_0 partition, return the mu8 */
1070 if (resource_part == m4_parts[0]) 1081 if (resource_part == m4_parts[0])
1071 return m4_mu[0]; 1082 return m4_mu[0];
1072 } 1083 }
1073 1084
1074 if (is_imx8qm()) { 1085 if (is_imx8qm()) {
1075 err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]); 1086 err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
1076 if (err != SC_ERR_NONE) { 1087 if (err != SC_ERR_NONE) {
1077 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err); 1088 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err);
1078 return NULL; 1089 return NULL;
1079 } 1090 }
1080 1091
1081 ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[1], &m4_mu[1]); 1092 ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[1], &m4_mu[1]);
1082 if (!ret) { 1093 if (!ret) {
1083 /* If the i2c is in m4_1 partition, return the mu9 */ 1094 /* If the i2c is in m4_1 partition, return the mu9 */
1084 if (resource_part == m4_parts[1]) 1095 if (resource_part == m4_parts[1])
1085 return m4_mu[1]; 1096 return m4_mu[1];
1086 } 1097 }
1087 } 1098 }
1088 1099
1089 return NULL; 1100 return NULL;
1090 } 1101 }
1091 1102
1092 void * board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size) 1103 void * board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size)
1093 { 1104 {
1094 const char *m4_mu_name[2] = { 1105 const char *m4_mu_name[2] = {
1095 "mu@5d230000", 1106 "mu@5d230000",
1096 "mu@5d240000" 1107 "mu@5d240000"
1097 }; 1108 };
1098 1109
1099 /* Each MU ownes 1M buffer */ 1110 /* Each MU ownes 1M buffer */
1100 if (size <= 0x100000) { 1111 if (size <= 0x100000) {
1101 if (!strcmp(node->mu_dev->name, m4_mu_name[0])) 1112 if (!strcmp(node->mu_dev->name, m4_mu_name[0]))
1102 return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER; 1113 return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER;
1103 else if (!strcmp(node->mu_dev->name, m4_mu_name[1])) 1114 else if (!strcmp(node->mu_dev->name, m4_mu_name[1]))
1104 return (void * )(CONFIG_IMX_VSERVICE_SHARED_BUFFER + 0x100000); 1115 return (void * )(CONFIG_IMX_VSERVICE_SHARED_BUFFER + 0x100000);
1105 else 1116 else
1106 return NULL; 1117 return NULL;
1107 } 1118 }
1108 1119
1109 return NULL; 1120 return NULL;
1110 } 1121 }
1111 #endif 1122 #endif
1112 1123
1113 /* imx8qxp i2c1 has lots of devices may used by both M4 and A core 1124 /* imx8qxp i2c1 has lots of devices may used by both M4 and A core
1114 * If A core partition does not own the resource, we will start 1125 * If A core partition does not own the resource, we will start
1115 * virtual i2c driver. Otherwise use local i2c driver. 1126 * virtual i2c driver. Otherwise use local i2c driver.
1116 */ 1127 */
1117 int board_imx_virt_i2c_bind(struct udevice *dev) 1128 int board_imx_virt_i2c_bind(struct udevice *dev)
1118 { 1129 {
1119 if (check_owned_udevice(dev)) 1130 if (check_owned_udevice(dev))
1120 return -ENODEV; 1131 return -ENODEV;
1121 1132
1122 return 0; 1133 return 0;
1123 } 1134 }
1124 1135
1125 int board_imx_lpi2c_bind(struct udevice *dev) 1136 int board_imx_lpi2c_bind(struct udevice *dev)
1126 { 1137 {
1127 if (check_owned_udevice(dev)) 1138 if (check_owned_udevice(dev))
1128 return 0; 1139 return 0;
1129 1140
1130 return -ENODEV; 1141 return -ENODEV;
1131 } 1142 }
1132 1143
1133 void board_boot_order(u32 *spl_boot_list) 1144 void board_boot_order(u32 *spl_boot_list)
1134 { 1145 {
1135 spl_boot_list[0] = spl_boot_device(); 1146 spl_boot_list[0] = spl_boot_device();
1136 1147
1137 if (spl_boot_list[0] == BOOT_DEVICE_SPI) { 1148 if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
1138 /* Check whether we own the flexspi0, if not, use NOR boot */ 1149 /* Check whether we own the flexspi0, if not, use NOR boot */
1139 if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) 1150 if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
1140 spl_boot_list[0] = BOOT_DEVICE_NOR; 1151 spl_boot_list[0] = BOOT_DEVICE_NOR;
1141 } 1152 }
1142 } 1153 }
1143 1154
1144 #ifdef CONFIG_USB_PORT_AUTO 1155 #ifdef CONFIG_USB_PORT_AUTO
1145 static int usb_port_auto_check(void) 1156 static int usb_port_auto_check(void)
1146 { 1157 {
1147 int ret; 1158 int ret;
1148 u32 usb2_data; 1159 u32 usb2_data;
1149 struct power_domain pd; 1160 struct power_domain pd;
1150 struct power_domain phy_pd; 1161 struct power_domain phy_pd;
1151 1162
1152 if (!power_domain_lookup_name("conn_usb0", &pd)) { 1163 if (!power_domain_lookup_name("conn_usb0", &pd)) {
1153 ret = power_domain_on(&pd); 1164 ret = power_domain_on(&pd);
1154 if (ret) { 1165 if (ret) {
1155 printf("conn_usb0 Power up failed!\n"); 1166 printf("conn_usb0 Power up failed!\n");
1156 return ret; 1167 return ret;
1157 } 1168 }
1158 1169
1159 if (!power_domain_lookup_name("conn_usb0_phy", &phy_pd)) { 1170 if (!power_domain_lookup_name("conn_usb0_phy", &phy_pd)) {
1160 ret = power_domain_on(&phy_pd); 1171 ret = power_domain_on(&phy_pd);
1161 if (ret) { 1172 if (ret) {
1162 printf("conn_usb0_phy Power up failed!\n"); 1173 printf("conn_usb0_phy Power up failed!\n");
1163 return ret; 1174 return ret;
1164 } 1175 }
1165 } else { 1176 } else {
1166 return -1; 1177 return -1;
1167 } 1178 }
1168 1179
1169 enable_usboh3_clk(1); 1180 enable_usboh3_clk(1);
1170 usb2_data = ci_udc_check_bus_active(USB_BASE_ADDR, USB_PHY0_BASE_ADDR, 0); 1181 usb2_data = ci_udc_check_bus_active(USB_BASE_ADDR, USB_PHY0_BASE_ADDR, 0);
1171 1182
1172 ret = power_domain_off(&phy_pd); 1183 ret = power_domain_off(&phy_pd);
1173 if (ret) { 1184 if (ret) {
1174 printf("conn_usb0_phy Power off failed!\n"); 1185 printf("conn_usb0_phy Power off failed!\n");
1175 return ret; 1186 return ret;
1176 } 1187 }
1177 ret = power_domain_off(&pd); 1188 ret = power_domain_off(&pd);
1178 if (ret) { 1189 if (ret) {
1179 printf("conn_usb0 Power off failed!\n"); 1190 printf("conn_usb0 Power off failed!\n");
1180 return ret; 1191 return ret;
1181 } 1192 }
1182 1193
1183 if (!usb2_data) 1194 if (!usb2_data)
1184 return 1; 1195 return 1;
1185 else 1196 else
1186 return 0; 1197 return 0;
1187 } 1198 }
1188 return -1; 1199 return -1;
1189 } 1200 }
1190 1201
1191 int board_usb_gadget_port_auto(void) 1202 int board_usb_gadget_port_auto(void)
1192 { 1203 {
1193 int usb_boot_index; 1204 int usb_boot_index;
1194 usb_boot_index = usb_port_auto_check(); 1205 usb_boot_index = usb_port_auto_check();
1195 1206
1196 if (usb_boot_index < 0) 1207 if (usb_boot_index < 0)
1197 usb_boot_index = 0; 1208 usb_boot_index = 0;
1198 1209
1199 printf("auto usb %d\n", usb_boot_index); 1210 printf("auto usb %d\n", usb_boot_index);
1200 1211
1201 return usb_boot_index; 1212 return usb_boot_index;
1202 } 1213 }
1203 #endif 1214 #endif
1204 1215
1205 static void power_off_all_usb(void) 1216 static void power_off_all_usb(void)
1206 { 1217 {
1207 if (is_usb_boot()) { 1218 if (is_usb_boot()) {
1208 /* Turn off all usb resource to let conn SS power down */ 1219 /* Turn off all usb resource to let conn SS power down */
1209 sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_OFF); 1220 sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_OFF);
1210 sc_pm_set_resource_power_mode(-1, SC_R_USB_1_PHY, SC_PM_PW_MODE_OFF); 1221 sc_pm_set_resource_power_mode(-1, SC_R_USB_1_PHY, SC_PM_PW_MODE_OFF);
1211 sc_pm_set_resource_power_mode(-1, SC_R_USB_2_PHY, SC_PM_PW_MODE_OFF); 1222 sc_pm_set_resource_power_mode(-1, SC_R_USB_2_PHY, SC_PM_PW_MODE_OFF);
1212 1223
1213 sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_OFF); 1224 sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_OFF);
1214 sc_pm_set_resource_power_mode(-1, SC_R_USB_1, SC_PM_PW_MODE_OFF); 1225 sc_pm_set_resource_power_mode(-1, SC_R_USB_1, SC_PM_PW_MODE_OFF);
1215 sc_pm_set_resource_power_mode(-1, SC_R_USB_2, SC_PM_PW_MODE_OFF); 1226 sc_pm_set_resource_power_mode(-1, SC_R_USB_2, SC_PM_PW_MODE_OFF);
1216 } 1227 }
1217 } 1228 }
1218 1229