Eric Lee / smarc-uboot

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Commit c9b59bf795804a25b9654e729a491363ef9e6a54

Authored by Nobuhiro Iwamatsu
Committed by Nobuhiro Iwamatsu
1 parent 69191fedf4
Exists in v2017.01-smarct4x and in 38 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: rmobile: alt: Add external RAM boot 

If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0x70000000.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 3 changed files with 15 additions and 1 deletions Inline Diff

arch/arm/cpu/armv7/rmobile/Kconfig
Diff comments   View file @ c9b59bf
1 if RMOBILE 1 if RMOBILE
2 2
3 choice 3 choice
4 prompt "Renesus ARM SoCs board select" 4 prompt "Renesus ARM SoCs board select"
5 5
6 config TARGET_ARMADILLO_800EVA 6 config TARGET_ARMADILLO_800EVA
7 bool "armadillo 800 eva board" 7 bool "armadillo 800 eva board"
8 8
9 config TARGET_KOELSCH 9 config TARGET_KOELSCH
10 bool "Koelsch board" 10 bool "Koelsch board"
11 11
12 config TARGET_LAGER 12 config TARGET_LAGER
13 bool "Lager board" 13 bool "Lager board"
14 14
15 config TARGET_KZM9G 15 config TARGET_KZM9G
16 bool "KZM9D board" 16 bool "KZM9D board"
17 17
18 config TARGET_ALT 18 config TARGET_ALT
19 bool "Alt board" 19 bool "Alt board"
20 20
21 endchoice 21 endchoice
22 22
23 config SYS_SOC 23 config SYS_SOC
24 default "rmobile" 24 default "rmobile"
25 25
26 config RMOBILE_EXTRAM_BOOT 26 config RMOBILE_EXTRAM_BOOT
27 bool "Enable boot from RAM" 27 bool "Enable boot from RAM"
28 depends on TARGET_LAGER || TARGET_KOELSCH 28 depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
29 default n 29 default n
30 30
31 source "board/atmark-techno/armadillo-800eva/Kconfig" 31 source "board/atmark-techno/armadillo-800eva/Kconfig"
32 source "board/renesas/koelsch/Kconfig" 32 source "board/renesas/koelsch/Kconfig"
33 source "board/renesas/lager/Kconfig" 33 source "board/renesas/lager/Kconfig"
34 source "board/kmc/kzm9g/Kconfig" 34 source "board/kmc/kzm9g/Kconfig"
35 source "board/renesas/alt/Kconfig" 35 source "board/renesas/alt/Kconfig"
36 36
37 endif 37 endif
38 38
board/renesas/alt/qos.c
Diff comments   View file @ c9b59bf
1 /* 1 /*
2 * board/renesas/alt/qos.c 2 * board/renesas/alt/qos.c
3 * 3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0 6 * SPDX-License-Identifier: GPL-2.0
7 * 7 *
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <asm/processor.h> 11 #include <asm/processor.h>
12 #include <asm/mach-types.h> 12 #include <asm/mach-types.h>
13 #include <asm/io.h> 13 #include <asm/io.h>
14 #include <asm/arch/rmobile.h> 14 #include <asm/arch/rmobile.h>
15 15
16 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
16 /* QoS version 0.11 */ 17 /* QoS version 0.11 */
17 18
18 enum { 19 enum {
19 DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, 20 DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
20 DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, 21 DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
21 DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, 22 DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
22 DBSC3_15, 23 DBSC3_15,
23 DBSC3_NR, 24 DBSC3_NR,
24 }; 25 };
25 26
26 static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { 27 static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
27 [DBSC3_00] = DBSC3_0_QOS_R0_BASE, 28 [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
28 [DBSC3_01] = DBSC3_0_QOS_R1_BASE, 29 [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
29 [DBSC3_02] = DBSC3_0_QOS_R2_BASE, 30 [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
30 [DBSC3_03] = DBSC3_0_QOS_R3_BASE, 31 [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
31 [DBSC3_04] = DBSC3_0_QOS_R4_BASE, 32 [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
32 [DBSC3_05] = DBSC3_0_QOS_R5_BASE, 33 [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
33 [DBSC3_06] = DBSC3_0_QOS_R6_BASE, 34 [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
34 [DBSC3_07] = DBSC3_0_QOS_R7_BASE, 35 [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
35 [DBSC3_08] = DBSC3_0_QOS_R8_BASE, 36 [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
36 [DBSC3_09] = DBSC3_0_QOS_R9_BASE, 37 [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
37 [DBSC3_10] = DBSC3_0_QOS_R10_BASE, 38 [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
38 [DBSC3_11] = DBSC3_0_QOS_R11_BASE, 39 [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
39 [DBSC3_12] = DBSC3_0_QOS_R12_BASE, 40 [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
40 [DBSC3_13] = DBSC3_0_QOS_R13_BASE, 41 [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
41 [DBSC3_14] = DBSC3_0_QOS_R14_BASE, 42 [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
42 [DBSC3_15] = DBSC3_0_QOS_R15_BASE, 43 [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
43 }; 44 };
44 45
45 static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { 46 static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
46 [DBSC3_00] = DBSC3_0_QOS_W0_BASE, 47 [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
47 [DBSC3_01] = DBSC3_0_QOS_W1_BASE, 48 [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
48 [DBSC3_02] = DBSC3_0_QOS_W2_BASE, 49 [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
49 [DBSC3_03] = DBSC3_0_QOS_W3_BASE, 50 [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
50 [DBSC3_04] = DBSC3_0_QOS_W4_BASE, 51 [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
51 [DBSC3_05] = DBSC3_0_QOS_W5_BASE, 52 [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
52 [DBSC3_06] = DBSC3_0_QOS_W6_BASE, 53 [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
53 [DBSC3_07] = DBSC3_0_QOS_W7_BASE, 54 [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
54 [DBSC3_08] = DBSC3_0_QOS_W8_BASE, 55 [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
55 [DBSC3_09] = DBSC3_0_QOS_W9_BASE, 56 [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
56 [DBSC3_10] = DBSC3_0_QOS_W10_BASE, 57 [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
57 [DBSC3_11] = DBSC3_0_QOS_W11_BASE, 58 [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
58 [DBSC3_12] = DBSC3_0_QOS_W12_BASE, 59 [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
59 [DBSC3_13] = DBSC3_0_QOS_W13_BASE, 60 [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
60 [DBSC3_14] = DBSC3_0_QOS_W14_BASE, 61 [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
61 [DBSC3_15] = DBSC3_0_QOS_W15_BASE, 62 [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
62 }; 63 };
63 64
64 void qos_init(void) 65 void qos_init(void)
65 { 66 {
66 int i; 67 int i;
67 struct rcar_s3c *s3c; 68 struct rcar_s3c *s3c;
68 struct rcar_s3c_qos *s3c_qos; 69 struct rcar_s3c_qos *s3c_qos;
69 struct rcar_dbsc3_qos *qos_addr; 70 struct rcar_dbsc3_qos *qos_addr;
70 struct rcar_mxi *mxi; 71 struct rcar_mxi *mxi;
71 struct rcar_mxi_qos *mxi_qos; 72 struct rcar_mxi_qos *mxi_qos;
72 struct rcar_axi_qos *axi_qos; 73 struct rcar_axi_qos *axi_qos;
73 74
74 /* DBSC DBADJ2 */ 75 /* DBSC DBADJ2 */
75 writel(0x20042004, DBSC3_0_DBADJ2); 76 writel(0x20042004, DBSC3_0_DBADJ2);
76 77
77 /* S3C -QoS */ 78 /* S3C -QoS */
78 s3c = (struct rcar_s3c *)S3C_BASE; 79 s3c = (struct rcar_s3c *)S3C_BASE;
79 writel(0x1F0D0B0A, &s3c->s3crorr); 80 writel(0x1F0D0B0A, &s3c->s3crorr);
80 writel(0x1F0D0B09, &s3c->s3cworr); 81 writel(0x1F0D0B09, &s3c->s3cworr);
81 82
82 /* QoS Control Registers */ 83 /* QoS Control Registers */
83 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; 84 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
84 writel(0x00890089, &s3c_qos->s3cqos0); 85 writel(0x00890089, &s3c_qos->s3cqos0);
85 writel(0x20960010, &s3c_qos->s3cqos1); 86 writel(0x20960010, &s3c_qos->s3cqos1);
86 writel(0x20302030, &s3c_qos->s3cqos2); 87 writel(0x20302030, &s3c_qos->s3cqos2);
87 writel(0x20AA2200, &s3c_qos->s3cqos3); 88 writel(0x20AA2200, &s3c_qos->s3cqos3);
88 writel(0x00002032, &s3c_qos->s3cqos4); 89 writel(0x00002032, &s3c_qos->s3cqos4);
89 writel(0x20960010, &s3c_qos->s3cqos5); 90 writel(0x20960010, &s3c_qos->s3cqos5);
90 writel(0x20302030, &s3c_qos->s3cqos6); 91 writel(0x20302030, &s3c_qos->s3cqos6);
91 writel(0x20AA2200, &s3c_qos->s3cqos7); 92 writel(0x20AA2200, &s3c_qos->s3cqos7);
92 writel(0x00002032, &s3c_qos->s3cqos8); 93 writel(0x00002032, &s3c_qos->s3cqos8);
93 94
94 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; 95 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
95 writel(0x00890089, &s3c_qos->s3cqos0); 96 writel(0x00890089, &s3c_qos->s3cqos0);
96 writel(0x20960010, &s3c_qos->s3cqos1); 97 writel(0x20960010, &s3c_qos->s3cqos1);
97 writel(0x20302030, &s3c_qos->s3cqos2); 98 writel(0x20302030, &s3c_qos->s3cqos2);
98 writel(0x20AA2200, &s3c_qos->s3cqos3); 99 writel(0x20AA2200, &s3c_qos->s3cqos3);
99 writel(0x00002032, &s3c_qos->s3cqos4); 100 writel(0x00002032, &s3c_qos->s3cqos4);
100 writel(0x20960010, &s3c_qos->s3cqos5); 101 writel(0x20960010, &s3c_qos->s3cqos5);
101 writel(0x20302030, &s3c_qos->s3cqos6); 102 writel(0x20302030, &s3c_qos->s3cqos6);
102 writel(0x20AA2200, &s3c_qos->s3cqos7); 103 writel(0x20AA2200, &s3c_qos->s3cqos7);
103 writel(0x00002032, &s3c_qos->s3cqos8); 104 writel(0x00002032, &s3c_qos->s3cqos8);
104 105
105 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; 106 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
106 writel(0x80928092, &s3c_qos->s3cqos0); 107 writel(0x80928092, &s3c_qos->s3cqos0);
107 writel(0x20960020, &s3c_qos->s3cqos1); 108 writel(0x20960020, &s3c_qos->s3cqos1);
108 writel(0x20302030, &s3c_qos->s3cqos2); 109 writel(0x20302030, &s3c_qos->s3cqos2);
109 writel(0x20AA20DC, &s3c_qos->s3cqos3); 110 writel(0x20AA20DC, &s3c_qos->s3cqos3);
110 writel(0x00002032, &s3c_qos->s3cqos4); 111 writel(0x00002032, &s3c_qos->s3cqos4);
111 writel(0x20960020, &s3c_qos->s3cqos5); 112 writel(0x20960020, &s3c_qos->s3cqos5);
112 writel(0x20302030, &s3c_qos->s3cqos6); 113 writel(0x20302030, &s3c_qos->s3cqos6);
113 writel(0x20AA20DC, &s3c_qos->s3cqos7); 114 writel(0x20AA20DC, &s3c_qos->s3cqos7);
114 writel(0x00002032, &s3c_qos->s3cqos8); 115 writel(0x00002032, &s3c_qos->s3cqos8);
115 116
116 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; 117 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
117 writel(0x00820082, &s3c_qos->s3cqos0); 118 writel(0x00820082, &s3c_qos->s3cqos0);
118 writel(0x20960020, &s3c_qos->s3cqos1); 119 writel(0x20960020, &s3c_qos->s3cqos1);
119 writel(0x20302030, &s3c_qos->s3cqos2); 120 writel(0x20302030, &s3c_qos->s3cqos2);
120 writel(0x20AA20FA, &s3c_qos->s3cqos3); 121 writel(0x20AA20FA, &s3c_qos->s3cqos3);
121 writel(0x00002032, &s3c_qos->s3cqos4); 122 writel(0x00002032, &s3c_qos->s3cqos4);
122 writel(0x20960020, &s3c_qos->s3cqos5); 123 writel(0x20960020, &s3c_qos->s3cqos5);
123 writel(0x20302030, &s3c_qos->s3cqos6); 124 writel(0x20302030, &s3c_qos->s3cqos6);
124 writel(0x20AA20FA, &s3c_qos->s3cqos7); 125 writel(0x20AA20FA, &s3c_qos->s3cqos7);
125 writel(0x00002032, &s3c_qos->s3cqos8); 126 writel(0x00002032, &s3c_qos->s3cqos8);
126 127
127 /* DBSC -QoS */ 128 /* DBSC -QoS */
128 /* DBSC0 - Read */ 129 /* DBSC0 - Read */
129 for (i = DBSC3_00; i < DBSC3_NR; i++) { 130 for (i = DBSC3_00; i < DBSC3_NR; i++) {
130 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; 131 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
131 writel(0x00000002, &qos_addr->dblgcnt); 132 writel(0x00000002, &qos_addr->dblgcnt);
132 writel(0x0000207D, &qos_addr->dbtmval0); 133 writel(0x0000207D, &qos_addr->dbtmval0);
133 writel(0x00002053, &qos_addr->dbtmval1); 134 writel(0x00002053, &qos_addr->dbtmval1);
134 writel(0x0000202A, &qos_addr->dbtmval2); 135 writel(0x0000202A, &qos_addr->dbtmval2);
135 writel(0x00001FBD, &qos_addr->dbtmval3); 136 writel(0x00001FBD, &qos_addr->dbtmval3);
136 writel(0x00000001, &qos_addr->dbrqctr); 137 writel(0x00000001, &qos_addr->dbrqctr);
137 writel(0x00002064, &qos_addr->dbthres0); 138 writel(0x00002064, &qos_addr->dbthres0);
138 writel(0x0000203E, &qos_addr->dbthres1); 139 writel(0x0000203E, &qos_addr->dbthres1);
139 writel(0x00002019, &qos_addr->dbthres2); 140 writel(0x00002019, &qos_addr->dbthres2);
140 writel(0x00000001, &qos_addr->dblgqon); 141 writel(0x00000001, &qos_addr->dblgqon);
141 } 142 }
142 143
143 /* DBSC0 - Write */ 144 /* DBSC0 - Write */
144 for (i = DBSC3_00; i < DBSC3_NR; i++) { 145 for (i = DBSC3_00; i < DBSC3_NR; i++) {
145 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; 146 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
146 writel(0x00000002, &qos_addr->dblgcnt); 147 writel(0x00000002, &qos_addr->dblgcnt);
147 writel(0x0000207D, &qos_addr->dbtmval0); 148 writel(0x0000207D, &qos_addr->dbtmval0);
148 writel(0x00002053, &qos_addr->dbtmval1); 149 writel(0x00002053, &qos_addr->dbtmval1);
149 writel(0x00002043, &qos_addr->dbtmval2); 150 writel(0x00002043, &qos_addr->dbtmval2);
150 writel(0x00002030, &qos_addr->dbtmval3); 151 writel(0x00002030, &qos_addr->dbtmval3);
151 writel(0x00000001, &qos_addr->dbrqctr); 152 writel(0x00000001, &qos_addr->dbrqctr);
152 writel(0x00002064, &qos_addr->dbthres0); 153 writel(0x00002064, &qos_addr->dbthres0);
153 writel(0x0000203E, &qos_addr->dbthres1); 154 writel(0x0000203E, &qos_addr->dbthres1);
154 writel(0x00002031, &qos_addr->dbthres2); 155 writel(0x00002031, &qos_addr->dbthres2);
155 writel(0x00000001, &qos_addr->dblgqon); 156 writel(0x00000001, &qos_addr->dblgqon);
156 } 157 }
157 158
158 /* CCI-400 -QoS */ 159 /* CCI-400 -QoS */
159 writel(0x20000800, CCI_400_MAXOT_1); 160 writel(0x20000800, CCI_400_MAXOT_1);
160 writel(0x20000800, CCI_400_MAXOT_2); 161 writel(0x20000800, CCI_400_MAXOT_2);
161 writel(0x0000000C, CCI_400_QOSCNTL_1); 162 writel(0x0000000C, CCI_400_QOSCNTL_1);
162 writel(0x0000000C, CCI_400_QOSCNTL_2); 163 writel(0x0000000C, CCI_400_QOSCNTL_2);
163 164
164 /* MXI -QoS */ 165 /* MXI -QoS */
165 /* Transaction Control (MXI) */ 166 /* Transaction Control (MXI) */
166 mxi = (struct rcar_mxi *)MXI_BASE; 167 mxi = (struct rcar_mxi *)MXI_BASE;
167 writel(0x00000013, &mxi->mxrtcr); 168 writel(0x00000013, &mxi->mxrtcr);
168 writel(0x00000013, &mxi->mxwtcr); 169 writel(0x00000013, &mxi->mxwtcr);
169 writel(0x00780080, &mxi->mxsaar0); 170 writel(0x00780080, &mxi->mxsaar0);
170 writel(0x02000800, &mxi->mxsaar1); 171 writel(0x02000800, &mxi->mxsaar1);
171 172
172 /* QoS Control (MXI) */ 173 /* QoS Control (MXI) */
173 mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; 174 mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
174 writel(0x0000000C, &mxi_qos->vspdu0); 175 writel(0x0000000C, &mxi_qos->vspdu0);
175 writel(0x0000000E, &mxi_qos->du0); 176 writel(0x0000000E, &mxi_qos->du0);
176 177
177 /* AXI -QoS */ 178 /* AXI -QoS */
178 /* Transaction Control (MXI) */ 179 /* Transaction Control (MXI) */
179 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; 180 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
180 writel(0x00000002, &axi_qos->qosconf); 181 writel(0x00000002, &axi_qos->qosconf);
181 writel(0x00002245, &axi_qos->qosctset0); 182 writel(0x00002245, &axi_qos->qosctset0);
182 writel(0x00002096, &axi_qos->qosctset1); 183 writel(0x00002096, &axi_qos->qosctset1);
183 writel(0x00002030, &axi_qos->qosctset2); 184 writel(0x00002030, &axi_qos->qosctset2);
184 writel(0x00002030, &axi_qos->qosctset3); 185 writel(0x00002030, &axi_qos->qosctset3);
185 writel(0x00000001, &axi_qos->qosreqctr); 186 writel(0x00000001, &axi_qos->qosreqctr);
186 writel(0x00002064, &axi_qos->qosthres0); 187 writel(0x00002064, &axi_qos->qosthres0);
187 writel(0x00002004, &axi_qos->qosthres1); 188 writel(0x00002004, &axi_qos->qosthres1);
188 writel(0x00000000, &axi_qos->qosthres2); 189 writel(0x00000000, &axi_qos->qosthres2);
189 writel(0x00000001, &axi_qos->qosqon); 190 writel(0x00000001, &axi_qos->qosqon);
190 191
191 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; 192 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
192 writel(0x00000000, &axi_qos->qosconf); 193 writel(0x00000000, &axi_qos->qosconf);
193 writel(0x000020A6, &axi_qos->qosctset0); 194 writel(0x000020A6, &axi_qos->qosctset0);
194 writel(0x00000001, &axi_qos->qosreqctr); 195 writel(0x00000001, &axi_qos->qosreqctr);
195 writel(0x00002064, &axi_qos->qosthres0); 196 writel(0x00002064, &axi_qos->qosthres0);
196 writel(0x00002004, &axi_qos->qosthres1); 197 writel(0x00002004, &axi_qos->qosthres1);
197 writel(0x00000000, &axi_qos->qosthres2); 198 writel(0x00000000, &axi_qos->qosthres2);
198 writel(0x00000001, &axi_qos->qosqon); 199 writel(0x00000001, &axi_qos->qosqon);
199 200
200 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; 201 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
201 writel(0x00000002, &axi_qos->qosconf); 202 writel(0x00000002, &axi_qos->qosconf);
202 writel(0x00002245, &axi_qos->qosctset0); 203 writel(0x00002245, &axi_qos->qosctset0);
203 writel(0x00002096, &axi_qos->qosctset1); 204 writel(0x00002096, &axi_qos->qosctset1);
204 writel(0x00002030, &axi_qos->qosctset2); 205 writel(0x00002030, &axi_qos->qosctset2);
205 writel(0x00002030, &axi_qos->qosctset3); 206 writel(0x00002030, &axi_qos->qosctset3);
206 writel(0x00000001, &axi_qos->qosreqctr); 207 writel(0x00000001, &axi_qos->qosreqctr);
207 writel(0x00002064, &axi_qos->qosthres0); 208 writel(0x00002064, &axi_qos->qosthres0);
208 writel(0x00002004, &axi_qos->qosthres1); 209 writel(0x00002004, &axi_qos->qosthres1);
209 writel(0x00000000, &axi_qos->qosthres2); 210 writel(0x00000000, &axi_qos->qosthres2);
210 writel(0x00000001, &axi_qos->qosqon); 211 writel(0x00000001, &axi_qos->qosqon);
211 212
212 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; 213 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
213 writel(0x00000002, &axi_qos->qosconf); 214 writel(0x00000002, &axi_qos->qosconf);
214 writel(0x00002245, &axi_qos->qosctset0); 215 writel(0x00002245, &axi_qos->qosctset0);
215 writel(0x00002096, &axi_qos->qosctset1); 216 writel(0x00002096, &axi_qos->qosctset1);
216 writel(0x00002030, &axi_qos->qosctset2); 217 writel(0x00002030, &axi_qos->qosctset2);
217 writel(0x00002030, &axi_qos->qosctset3); 218 writel(0x00002030, &axi_qos->qosctset3);
218 writel(0x00000001, &axi_qos->qosreqctr); 219 writel(0x00000001, &axi_qos->qosreqctr);
219 writel(0x00002064, &axi_qos->qosthres0); 220 writel(0x00002064, &axi_qos->qosthres0);
220 writel(0x00002004, &axi_qos->qosthres1); 221 writel(0x00002004, &axi_qos->qosthres1);
221 writel(0x00000000, &axi_qos->qosthres2); 222 writel(0x00000000, &axi_qos->qosthres2);
222 writel(0x00000001, &axi_qos->qosqon); 223 writel(0x00000001, &axi_qos->qosqon);
223 224
224 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; 225 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
225 writel(0x00000002, &axi_qos->qosconf); 226 writel(0x00000002, &axi_qos->qosconf);
226 writel(0x00002245, &axi_qos->qosctset0); 227 writel(0x00002245, &axi_qos->qosctset0);
227 writel(0x00002096, &axi_qos->qosctset1); 228 writel(0x00002096, &axi_qos->qosctset1);
228 writel(0x00002030, &axi_qos->qosctset2); 229 writel(0x00002030, &axi_qos->qosctset2);
229 writel(0x00002030, &axi_qos->qosctset3); 230 writel(0x00002030, &axi_qos->qosctset3);
230 writel(0x00000001, &axi_qos->qosreqctr); 231 writel(0x00000001, &axi_qos->qosreqctr);
231 writel(0x00002064, &axi_qos->qosthres0); 232 writel(0x00002064, &axi_qos->qosthres0);
232 writel(0x00002004, &axi_qos->qosthres1); 233 writel(0x00002004, &axi_qos->qosthres1);
233 writel(0x00000000, &axi_qos->qosthres2); 234 writel(0x00000000, &axi_qos->qosthres2);
234 writel(0x00000001, &axi_qos->qosqon); 235 writel(0x00000001, &axi_qos->qosqon);
235 236
236 axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; 237 axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
237 writel(0x00000000, &axi_qos->qosconf); 238 writel(0x00000000, &axi_qos->qosconf);
238 writel(0x0000214C, &axi_qos->qosctset0); 239 writel(0x0000214C, &axi_qos->qosctset0);
239 writel(0x00000001, &axi_qos->qosreqctr); 240 writel(0x00000001, &axi_qos->qosreqctr);
240 writel(0x00002064, &axi_qos->qosthres0); 241 writel(0x00002064, &axi_qos->qosthres0);
241 writel(0x00002004, &axi_qos->qosthres1); 242 writel(0x00002004, &axi_qos->qosthres1);
242 writel(0x00000000, &axi_qos->qosthres2); 243 writel(0x00000000, &axi_qos->qosthres2);
243 writel(0x00000001, &axi_qos->qosqon); 244 writel(0x00000001, &axi_qos->qosqon);
244 245
245 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; 246 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
246 writel(0x00000001, &axi_qos->qosconf); 247 writel(0x00000001, &axi_qos->qosconf);
247 writel(0x00002004, &axi_qos->qosctset0); 248 writel(0x00002004, &axi_qos->qosctset0);
248 writel(0x00002096, &axi_qos->qosctset1); 249 writel(0x00002096, &axi_qos->qosctset1);
249 writel(0x00002030, &axi_qos->qosctset2); 250 writel(0x00002030, &axi_qos->qosctset2);
250 writel(0x00002030, &axi_qos->qosctset3); 251 writel(0x00002030, &axi_qos->qosctset3);
251 writel(0x00000001, &axi_qos->qosreqctr); 252 writel(0x00000001, &axi_qos->qosreqctr);
252 writel(0x00002064, &axi_qos->qosthres0); 253 writel(0x00002064, &axi_qos->qosthres0);
253 writel(0x00002004, &axi_qos->qosthres1); 254 writel(0x00002004, &axi_qos->qosthres1);
254 writel(0x00000000, &axi_qos->qosthres2); 255 writel(0x00000000, &axi_qos->qosthres2);
255 writel(0x00000001, &axi_qos->qosqon); 256 writel(0x00000001, &axi_qos->qosqon);
256 257
257 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; 258 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
258 writel(0x00000001, &axi_qos->qosconf); 259 writel(0x00000001, &axi_qos->qosconf);
259 writel(0x00002004, &axi_qos->qosctset0); 260 writel(0x00002004, &axi_qos->qosctset0);
260 writel(0x00002096, &axi_qos->qosctset1); 261 writel(0x00002096, &axi_qos->qosctset1);
261 writel(0x00002030, &axi_qos->qosctset2); 262 writel(0x00002030, &axi_qos->qosctset2);
262 writel(0x00002030, &axi_qos->qosctset3); 263 writel(0x00002030, &axi_qos->qosctset3);
263 writel(0x00000001, &axi_qos->qosreqctr); 264 writel(0x00000001, &axi_qos->qosreqctr);
264 writel(0x00002064, &axi_qos->qosthres0); 265 writel(0x00002064, &axi_qos->qosthres0);
265 writel(0x00002004, &axi_qos->qosthres1); 266 writel(0x00002004, &axi_qos->qosthres1);
266 writel(0x00000000, &axi_qos->qosthres2); 267 writel(0x00000000, &axi_qos->qosthres2);
267 writel(0x00000001, &axi_qos->qosqon); 268 writel(0x00000001, &axi_qos->qosqon);
268 269
269 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; 270 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
270 writel(0x00000001, &axi_qos->qosconf); 271 writel(0x00000001, &axi_qos->qosconf);
271 writel(0x00002004, &axi_qos->qosctset0); 272 writel(0x00002004, &axi_qos->qosctset0);
272 writel(0x00002096, &axi_qos->qosctset1); 273 writel(0x00002096, &axi_qos->qosctset1);
273 writel(0x00002030, &axi_qos->qosctset2); 274 writel(0x00002030, &axi_qos->qosctset2);
274 writel(0x00002030, &axi_qos->qosctset3); 275 writel(0x00002030, &axi_qos->qosctset3);
275 writel(0x00000001, &axi_qos->qosreqctr); 276 writel(0x00000001, &axi_qos->qosreqctr);
276 writel(0x00002064, &axi_qos->qosthres0); 277 writel(0x00002064, &axi_qos->qosthres0);
277 writel(0x00002004, &axi_qos->qosthres1); 278 writel(0x00002004, &axi_qos->qosthres1);
278 writel(0x00000000, &axi_qos->qosthres2); 279 writel(0x00000000, &axi_qos->qosthres2);
279 writel(0x00000001, &axi_qos->qosqon); 280 writel(0x00000001, &axi_qos->qosqon);
280 281
281 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; 282 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
282 writel(0x00000001, &axi_qos->qosconf); 283 writel(0x00000001, &axi_qos->qosconf);
283 writel(0x00002004, &axi_qos->qosctset0); 284 writel(0x00002004, &axi_qos->qosctset0);
284 writel(0x00002096, &axi_qos->qosctset1); 285 writel(0x00002096, &axi_qos->qosctset1);
285 writel(0x00002030, &axi_qos->qosctset2); 286 writel(0x00002030, &axi_qos->qosctset2);
286 writel(0x00002030, &axi_qos->qosctset3); 287 writel(0x00002030, &axi_qos->qosctset3);
287 writel(0x00000001, &axi_qos->qosreqctr); 288 writel(0x00000001, &axi_qos->qosreqctr);
288 writel(0x00002064, &axi_qos->qosthres0); 289 writel(0x00002064, &axi_qos->qosthres0);
289 writel(0x00002004, &axi_qos->qosthres1); 290 writel(0x00002004, &axi_qos->qosthres1);
290 writel(0x00000000, &axi_qos->qosthres2); 291 writel(0x00000000, &axi_qos->qosthres2);
291 writel(0x00000001, &axi_qos->qosqon); 292 writel(0x00000001, &axi_qos->qosqon);
292 293
293 axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; 294 axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
294 writel(0x00000002, &axi_qos->qosconf); 295 writel(0x00000002, &axi_qos->qosconf);
295 writel(0x00002245, &axi_qos->qosctset0); 296 writel(0x00002245, &axi_qos->qosctset0);
296 writel(0x00002096, &axi_qos->qosctset1); 297 writel(0x00002096, &axi_qos->qosctset1);
297 writel(0x00002030, &axi_qos->qosctset2); 298 writel(0x00002030, &axi_qos->qosctset2);
298 writel(0x00002030, &axi_qos->qosctset3); 299 writel(0x00002030, &axi_qos->qosctset3);
299 writel(0x00000001, &axi_qos->qosreqctr); 300 writel(0x00000001, &axi_qos->qosreqctr);
300 writel(0x00002064, &axi_qos->qosthres0); 301 writel(0x00002064, &axi_qos->qosthres0);
301 writel(0x00002004, &axi_qos->qosthres1); 302 writel(0x00002004, &axi_qos->qosthres1);
302 writel(0x00000000, &axi_qos->qosthres2); 303 writel(0x00000000, &axi_qos->qosthres2);
303 writel(0x00000001, &axi_qos->qosqon); 304 writel(0x00000001, &axi_qos->qosqon);
304 305
305 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; 306 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
306 writel(0x00000000, &axi_qos->qosconf); 307 writel(0x00000000, &axi_qos->qosconf);
307 writel(0x000020A6, &axi_qos->qosctset0); 308 writel(0x000020A6, &axi_qos->qosctset0);
308 writel(0x00000001, &axi_qos->qosreqctr); 309 writel(0x00000001, &axi_qos->qosreqctr);
309 writel(0x00002064, &axi_qos->qosthres0); 310 writel(0x00002064, &axi_qos->qosthres0);
310 writel(0x00002004, &axi_qos->qosthres1); 311 writel(0x00002004, &axi_qos->qosthres1);
311 writel(0x00000000, &axi_qos->qosthres2); 312 writel(0x00000000, &axi_qos->qosthres2);
312 writel(0x00000001, &axi_qos->qosqon); 313 writel(0x00000001, &axi_qos->qosqon);
313 314
314 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; 315 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
315 writel(0x00000000, &axi_qos->qosconf); 316 writel(0x00000000, &axi_qos->qosconf);
316 writel(0x000020A6, &axi_qos->qosctset0); 317 writel(0x000020A6, &axi_qos->qosctset0);
317 writel(0x00000001, &axi_qos->qosreqctr); 318 writel(0x00000001, &axi_qos->qosreqctr);
318 writel(0x00002064, &axi_qos->qosthres0); 319 writel(0x00002064, &axi_qos->qosthres0);
319 writel(0x00002004, &axi_qos->qosthres1); 320 writel(0x00002004, &axi_qos->qosthres1);
320 writel(0x00000000, &axi_qos->qosthres2); 321 writel(0x00000000, &axi_qos->qosthres2);
321 writel(0x00000001, &axi_qos->qosqon); 322 writel(0x00000001, &axi_qos->qosqon);
322 323
323 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; 324 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
324 writel(0x00000000, &axi_qos->qosconf); 325 writel(0x00000000, &axi_qos->qosconf);
325 writel(0x00002053, &axi_qos->qosctset0); 326 writel(0x00002053, &axi_qos->qosctset0);
326 writel(0x00000001, &axi_qos->qosreqctr); 327 writel(0x00000001, &axi_qos->qosreqctr);
327 writel(0x00002064, &axi_qos->qosthres0); 328 writel(0x00002064, &axi_qos->qosthres0);
328 writel(0x00002004, &axi_qos->qosthres1); 329 writel(0x00002004, &axi_qos->qosthres1);
329 writel(0x00000000, &axi_qos->qosthres2); 330 writel(0x00000000, &axi_qos->qosthres2);
330 writel(0x00000001, &axi_qos->qosqon); 331 writel(0x00000001, &axi_qos->qosqon);
331 332
332 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; 333 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
333 writel(0x00000000, &axi_qos->qosconf); 334 writel(0x00000000, &axi_qos->qosconf);
334 writel(0x00002053, &axi_qos->qosctset0); 335 writel(0x00002053, &axi_qos->qosctset0);
335 writel(0x00000001, &axi_qos->qosreqctr); 336 writel(0x00000001, &axi_qos->qosreqctr);
336 writel(0x00002064, &axi_qos->qosthres0); 337 writel(0x00002064, &axi_qos->qosthres0);
337 writel(0x00002004, &axi_qos->qosthres1); 338 writel(0x00002004, &axi_qos->qosthres1);
338 writel(0x00000000, &axi_qos->qosthres2); 339 writel(0x00000000, &axi_qos->qosthres2);
339 writel(0x00000001, &axi_qos->qosqon); 340 writel(0x00000001, &axi_qos->qosqon);
340 341
341 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; 342 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
342 writel(0x00000002, &axi_qos->qosconf); 343 writel(0x00000002, &axi_qos->qosconf);
343 writel(0x00002245, &axi_qos->qosctset0); 344 writel(0x00002245, &axi_qos->qosctset0);
344 writel(0x00000001, &axi_qos->qosreqctr); 345 writel(0x00000001, &axi_qos->qosreqctr);
345 writel(0x00002064, &axi_qos->qosthres0); 346 writel(0x00002064, &axi_qos->qosthres0);
346 writel(0x00002004, &axi_qos->qosthres1); 347 writel(0x00002004, &axi_qos->qosthres1);
347 writel(0x00000000, &axi_qos->qosthres2); 348 writel(0x00000000, &axi_qos->qosthres2);
348 writel(0x00000001, &axi_qos->qosqon); 349 writel(0x00000001, &axi_qos->qosqon);
349 350
350 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; 351 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
351 writel(0x00000000, &axi_qos->qosconf); 352 writel(0x00000000, &axi_qos->qosconf);
352 writel(0x00002029, &axi_qos->qosctset0); 353 writel(0x00002029, &axi_qos->qosctset0);
353 writel(0x00000001, &axi_qos->qosreqctr); 354 writel(0x00000001, &axi_qos->qosreqctr);
354 writel(0x00002064, &axi_qos->qosthres0); 355 writel(0x00002064, &axi_qos->qosthres0);
355 writel(0x00002004, &axi_qos->qosthres1); 356 writel(0x00002004, &axi_qos->qosthres1);
356 writel(0x00000000, &axi_qos->qosthres2); 357 writel(0x00000000, &axi_qos->qosthres2);
357 writel(0x00000001, &axi_qos->qosqon); 358 writel(0x00000001, &axi_qos->qosqon);
358 359
359 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; 360 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
360 writel(0x00000002, &axi_qos->qosconf); 361 writel(0x00000002, &axi_qos->qosconf);
361 writel(0x00002245, &axi_qos->qosctset0); 362 writel(0x00002245, &axi_qos->qosctset0);
362 writel(0x00000001, &axi_qos->qosreqctr); 363 writel(0x00000001, &axi_qos->qosreqctr);
363 writel(0x00002064, &axi_qos->qosthres0); 364 writel(0x00002064, &axi_qos->qosthres0);
364 writel(0x00002004, &axi_qos->qosthres1); 365 writel(0x00002004, &axi_qos->qosthres1);
365 writel(0x00000000, &axi_qos->qosthres2); 366 writel(0x00000000, &axi_qos->qosthres2);
366 writel(0x00000001, &axi_qos->qosqon); 367 writel(0x00000001, &axi_qos->qosqon);
367 368
368 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; 369 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
369 writel(0x00000000, &axi_qos->qosconf); 370 writel(0x00000000, &axi_qos->qosconf);
370 writel(0x00002053, &axi_qos->qosctset0); 371 writel(0x00002053, &axi_qos->qosctset0);
371 writel(0x00000001, &axi_qos->qosreqctr); 372 writel(0x00000001, &axi_qos->qosreqctr);
372 writel(0x00002064, &axi_qos->qosthres0); 373 writel(0x00002064, &axi_qos->qosthres0);
373 writel(0x00002004, &axi_qos->qosthres1); 374 writel(0x00002004, &axi_qos->qosthres1);
374 writel(0x00000000, &axi_qos->qosthres2); 375 writel(0x00000000, &axi_qos->qosthres2);
375 writel(0x00000001, &axi_qos->qosqon); 376 writel(0x00000001, &axi_qos->qosqon);
376 377
377 axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; 378 axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
378 writel(0x00000000, &axi_qos->qosconf); 379 writel(0x00000000, &axi_qos->qosconf);
379 writel(0x000020A6, &axi_qos->qosctset0); 380 writel(0x000020A6, &axi_qos->qosctset0);
380 writel(0x00000001, &axi_qos->qosreqctr); 381 writel(0x00000001, &axi_qos->qosreqctr);
381 writel(0x00002064, &axi_qos->qosthres0); 382 writel(0x00002064, &axi_qos->qosthres0);
382 writel(0x00002004, &axi_qos->qosthres1); 383 writel(0x00002004, &axi_qos->qosthres1);
383 writel(0x00000000, &axi_qos->qosthres2); 384 writel(0x00000000, &axi_qos->qosthres2);
384 writel(0x00000001, &axi_qos->qosqon); 385 writel(0x00000001, &axi_qos->qosqon);
385 386
386 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; 387 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
387 writel(0x00000000, &axi_qos->qosconf); 388 writel(0x00000000, &axi_qos->qosconf);
388 writel(0x00002053, &axi_qos->qosctset0); 389 writel(0x00002053, &axi_qos->qosctset0);
389 writel(0x00000001, &axi_qos->qosreqctr); 390 writel(0x00000001, &axi_qos->qosreqctr);
390 writel(0x00002064, &axi_qos->qosthres0); 391 writel(0x00002064, &axi_qos->qosthres0);
391 writel(0x00002004, &axi_qos->qosthres1); 392 writel(0x00002004, &axi_qos->qosthres1);
392 writel(0x00000000, &axi_qos->qosthres2); 393 writel(0x00000000, &axi_qos->qosthres2);
393 writel(0x00000001, &axi_qos->qosqon); 394 writel(0x00000001, &axi_qos->qosqon);
394 395
395 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; 396 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
396 writel(0x00000002, &axi_qos->qosconf); 397 writel(0x00000002, &axi_qos->qosconf);
397 writel(0x00002245, &axi_qos->qosctset0); 398 writel(0x00002245, &axi_qos->qosctset0);
398 writel(0x00000001, &axi_qos->qosreqctr); 399 writel(0x00000001, &axi_qos->qosreqctr);
399 writel(0x00002064, &axi_qos->qosthres0); 400 writel(0x00002064, &axi_qos->qosthres0);
400 writel(0x00002004, &axi_qos->qosthres1); 401 writel(0x00002004, &axi_qos->qosthres1);
401 writel(0x00000000, &axi_qos->qosthres2); 402 writel(0x00000000, &axi_qos->qosthres2);
402 writel(0x00000001, &axi_qos->qosqon); 403 writel(0x00000001, &axi_qos->qosqon);
403 404
404 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; 405 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
405 writel(0x00000000, &axi_qos->qosconf); 406 writel(0x00000000, &axi_qos->qosconf);
406 writel(0x0000214C, &axi_qos->qosctset0); 407 writel(0x0000214C, &axi_qos->qosctset0);
407 writel(0x00000001, &axi_qos->qosreqctr); 408 writel(0x00000001, &axi_qos->qosreqctr);
408 writel(0x00002064, &axi_qos->qosthres0); 409 writel(0x00002064, &axi_qos->qosthres0);
409 writel(0x00002004, &axi_qos->qosthres1); 410 writel(0x00002004, &axi_qos->qosthres1);
410 writel(0x00000000, &axi_qos->qosthres2); 411 writel(0x00000000, &axi_qos->qosthres2);
411 writel(0x00000001, &axi_qos->qosqon); 412 writel(0x00000001, &axi_qos->qosqon);
412 413
413 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; 414 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
414 writel(0x00000000, &axi_qos->qosconf); 415 writel(0x00000000, &axi_qos->qosconf);
415 writel(0x0000214C, &axi_qos->qosctset0); 416 writel(0x0000214C, &axi_qos->qosctset0);
416 writel(0x00000001, &axi_qos->qosreqctr); 417 writel(0x00000001, &axi_qos->qosreqctr);
417 writel(0x00002064, &axi_qos->qosthres0); 418 writel(0x00002064, &axi_qos->qosthres0);
418 writel(0x00002004, &axi_qos->qosthres1); 419 writel(0x00002004, &axi_qos->qosthres1);
419 writel(0x00000000, &axi_qos->qosthres2); 420 writel(0x00000000, &axi_qos->qosthres2);
420 writel(0x00000001, &axi_qos->qosqon); 421 writel(0x00000001, &axi_qos->qosqon);
421 422
422 axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; 423 axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
423 writel(0x00000000, &axi_qos->qosconf); 424 writel(0x00000000, &axi_qos->qosconf);
424 writel(0x000020A6, &axi_qos->qosctset0); 425 writel(0x000020A6, &axi_qos->qosctset0);
425 writel(0x00000001, &axi_qos->qosreqctr); 426 writel(0x00000001, &axi_qos->qosreqctr);
426 writel(0x00002064, &axi_qos->qosthres0); 427 writel(0x00002064, &axi_qos->qosthres0);
427 writel(0x00002004, &axi_qos->qosthres1); 428 writel(0x00002004, &axi_qos->qosthres1);
428 writel(0x00000000, &axi_qos->qosthres2); 429 writel(0x00000000, &axi_qos->qosthres2);
429 writel(0x00000001, &axi_qos->qosqon); 430 writel(0x00000001, &axi_qos->qosqon);
430 431
431 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; 432 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
432 writel(0x00000000, &axi_qos->qosconf); 433 writel(0x00000000, &axi_qos->qosconf);
433 writel(0x00002053, &axi_qos->qosctset0); 434 writel(0x00002053, &axi_qos->qosctset0);
434 writel(0x00000001, &axi_qos->qosreqctr); 435 writel(0x00000001, &axi_qos->qosreqctr);
435 writel(0x00002064, &axi_qos->qosthres0); 436 writel(0x00002064, &axi_qos->qosthres0);
436 writel(0x00002004, &axi_qos->qosthres1); 437 writel(0x00002004, &axi_qos->qosthres1);
437 writel(0x00000000, &axi_qos->qosthres2); 438 writel(0x00000000, &axi_qos->qosthres2);
438 writel(0x00000001, &axi_qos->qosqon); 439 writel(0x00000001, &axi_qos->qosqon);
439 440
440 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; 441 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
441 writel(0x00000000, &axi_qos->qosconf); 442 writel(0x00000000, &axi_qos->qosconf);
442 writel(0x00002053, &axi_qos->qosctset0); 443 writel(0x00002053, &axi_qos->qosctset0);
443 writel(0x00000001, &axi_qos->qosreqctr); 444 writel(0x00000001, &axi_qos->qosreqctr);
444 writel(0x00002064, &axi_qos->qosthres0); 445 writel(0x00002064, &axi_qos->qosthres0);
445 writel(0x00002004, &axi_qos->qosthres1); 446 writel(0x00002004, &axi_qos->qosthres1);
446 writel(0x00000000, &axi_qos->qosthres2); 447 writel(0x00000000, &axi_qos->qosthres2);
447 writel(0x00000001, &axi_qos->qosqon); 448 writel(0x00000001, &axi_qos->qosqon);
448 449
449 /* QoS Register (RT-AXI) */ 450 /* QoS Register (RT-AXI) */
450 axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; 451 axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
451 writel(0x00000000, &axi_qos->qosconf); 452 writel(0x00000000, &axi_qos->qosconf);
452 writel(0x00002053, &axi_qos->qosctset0); 453 writel(0x00002053, &axi_qos->qosctset0);
453 writel(0x00002096, &axi_qos->qosctset1); 454 writel(0x00002096, &axi_qos->qosctset1);
454 writel(0x00002030, &axi_qos->qosctset2); 455 writel(0x00002030, &axi_qos->qosctset2);
455 writel(0x00002030, &axi_qos->qosctset3); 456 writel(0x00002030, &axi_qos->qosctset3);
456 writel(0x00000001, &axi_qos->qosreqctr); 457 writel(0x00000001, &axi_qos->qosreqctr);
457 writel(0x00002064, &axi_qos->qosthres0); 458 writel(0x00002064, &axi_qos->qosthres0);
458 writel(0x00002004, &axi_qos->qosthres1); 459 writel(0x00002004, &axi_qos->qosthres1);
459 writel(0x00000000, &axi_qos->qosthres2); 460 writel(0x00000000, &axi_qos->qosthres2);
460 writel(0x00000001, &axi_qos->qosqon); 461 writel(0x00000001, &axi_qos->qosqon);
461 462
462 axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; 463 axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
463 writel(0x00000000, &axi_qos->qosconf); 464 writel(0x00000000, &axi_qos->qosconf);
464 writel(0x00002053, &axi_qos->qosctset0); 465 writel(0x00002053, &axi_qos->qosctset0);
465 writel(0x00002096, &axi_qos->qosctset1); 466 writel(0x00002096, &axi_qos->qosctset1);
466 writel(0x00002030, &axi_qos->qosctset2); 467 writel(0x00002030, &axi_qos->qosctset2);
467 writel(0x00002030, &axi_qos->qosctset3); 468 writel(0x00002030, &axi_qos->qosctset3);
468 writel(0x00000001, &axi_qos->qosreqctr); 469 writel(0x00000001, &axi_qos->qosreqctr);
469 writel(0x00002064, &axi_qos->qosthres0); 470 writel(0x00002064, &axi_qos->qosthres0);
470 writel(0x00002004, &axi_qos->qosthres1); 471 writel(0x00002004, &axi_qos->qosthres1);
471 writel(0x00000000, &axi_qos->qosthres2); 472 writel(0x00000000, &axi_qos->qosthres2);
472 writel(0x00000001, &axi_qos->qosqon); 473 writel(0x00000001, &axi_qos->qosqon);
473 474
474 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; 475 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
475 writel(0x00000002, &axi_qos->qosconf); 476 writel(0x00000002, &axi_qos->qosconf);
476 writel(0x00002245, &axi_qos->qosctset0); 477 writel(0x00002245, &axi_qos->qosctset0);
477 writel(0x00002096, &axi_qos->qosctset1); 478 writel(0x00002096, &axi_qos->qosctset1);
478 writel(0x00002030, &axi_qos->qosctset2); 479 writel(0x00002030, &axi_qos->qosctset2);
479 writel(0x00002030, &axi_qos->qosctset3); 480 writel(0x00002030, &axi_qos->qosctset3);
480 writel(0x00000001, &axi_qos->qosreqctr); 481 writel(0x00000001, &axi_qos->qosreqctr);
481 writel(0x00002064, &axi_qos->qosthres0); 482 writel(0x00002064, &axi_qos->qosthres0);
482 writel(0x00002004, &axi_qos->qosthres1); 483 writel(0x00002004, &axi_qos->qosthres1);
483 writel(0x00000000, &axi_qos->qosthres2); 484 writel(0x00000000, &axi_qos->qosthres2);
484 writel(0x00000001, &axi_qos->qosqon); 485 writel(0x00000001, &axi_qos->qosqon);
485 486
486 axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; 487 axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
487 writel(0x00000002, &axi_qos->qosconf); 488 writel(0x00000002, &axi_qos->qosconf);
488 writel(0x00002245, &axi_qos->qosctset0); 489 writel(0x00002245, &axi_qos->qosctset0);
489 writel(0x00000001, &axi_qos->qosreqctr); 490 writel(0x00000001, &axi_qos->qosreqctr);
490 writel(0x00002064, &axi_qos->qosthres0); 491 writel(0x00002064, &axi_qos->qosthres0);
491 writel(0x00002004, &axi_qos->qosthres1); 492 writel(0x00002004, &axi_qos->qosthres1);
492 writel(0x00000000, &axi_qos->qosthres2); 493 writel(0x00000000, &axi_qos->qosthres2);
493 writel(0x00000001, &axi_qos->qosqon); 494 writel(0x00000001, &axi_qos->qosqon);
494 495
495 /* QoS Register (MP-AXI) */ 496 /* QoS Register (MP-AXI) */
496 axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; 497 axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
497 writel(0x00000000, &axi_qos->qosconf); 498 writel(0x00000000, &axi_qos->qosconf);
498 writel(0x00002037, &axi_qos->qosctset0); 499 writel(0x00002037, &axi_qos->qosctset0);
499 writel(0x00000001, &axi_qos->qosreqctr); 500 writel(0x00000001, &axi_qos->qosreqctr);
500 writel(0x00002064, &axi_qos->qosthres0); 501 writel(0x00002064, &axi_qos->qosthres0);
501 writel(0x00002004, &axi_qos->qosthres1); 502 writel(0x00002004, &axi_qos->qosthres1);
502 writel(0x00000000, &axi_qos->qosthres2); 503 writel(0x00000000, &axi_qos->qosthres2);
503 writel(0x00000001, &axi_qos->qosqon); 504 writel(0x00000001, &axi_qos->qosqon);
504 505
505 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; 506 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
506 writel(0x00000001, &axi_qos->qosconf); 507 writel(0x00000001, &axi_qos->qosconf);
507 writel(0x00002014, &axi_qos->qosctset0); 508 writel(0x00002014, &axi_qos->qosctset0);
508 writel(0x00000040, &axi_qos->qosreqctr); 509 writel(0x00000040, &axi_qos->qosreqctr);
509 writel(0x00002064, &axi_qos->qosthres0); 510 writel(0x00002064, &axi_qos->qosthres0);
510 writel(0x00002004, &axi_qos->qosthres1); 511 writel(0x00002004, &axi_qos->qosthres1);
511 writel(0x00000000, &axi_qos->qosthres2); 512 writel(0x00000000, &axi_qos->qosthres2);
512 writel(0x00000001, &axi_qos->qosqon); 513 writel(0x00000001, &axi_qos->qosqon);
513 514
514 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; 515 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
515 writel(0x00000001, &axi_qos->qosconf); 516 writel(0x00000001, &axi_qos->qosconf);
516 writel(0x00002014, &axi_qos->qosctset0); 517 writel(0x00002014, &axi_qos->qosctset0);
517 writel(0x00000040, &axi_qos->qosreqctr); 518 writel(0x00000040, &axi_qos->qosreqctr);
518 writel(0x00002064, &axi_qos->qosthres0); 519 writel(0x00002064, &axi_qos->qosthres0);
519 writel(0x00002004, &axi_qos->qosthres1); 520 writel(0x00002004, &axi_qos->qosthres1);
520 writel(0x00000000, &axi_qos->qosthres2); 521 writel(0x00000000, &axi_qos->qosthres2);
521 writel(0x00000001, &axi_qos->qosqon); 522 writel(0x00000001, &axi_qos->qosqon);
522 523
523 axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; 524 axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
524 writel(0x00000001, &axi_qos->qosconf); 525 writel(0x00000001, &axi_qos->qosconf);
525 writel(0x00001FF0, &axi_qos->qosctset0); 526 writel(0x00001FF0, &axi_qos->qosctset0);
526 writel(0x00000020, &axi_qos->qosreqctr); 527 writel(0x00000020, &axi_qos->qosreqctr);
527 writel(0x00002064, &axi_qos->qosthres0); 528 writel(0x00002064, &axi_qos->qosthres0);
528 writel(0x00002004, &axi_qos->qosthres1); 529 writel(0x00002004, &axi_qos->qosthres1);
529 writel(0x00002001, &axi_qos->qosthres2); 530 writel(0x00002001, &axi_qos->qosthres2);
530 writel(0x00000001, &axi_qos->qosqon); 531 writel(0x00000001, &axi_qos->qosqon);
531 532
532 axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; 533 axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
533 writel(0x00000001, &axi_qos->qosconf); 534 writel(0x00000001, &axi_qos->qosconf);
534 writel(0x00002004, &axi_qos->qosctset0); 535 writel(0x00002004, &axi_qos->qosctset0);
535 writel(0x00002096, &axi_qos->qosctset1); 536 writel(0x00002096, &axi_qos->qosctset1);
536 writel(0x00002030, &axi_qos->qosctset2); 537 writel(0x00002030, &axi_qos->qosctset2);
537 writel(0x00002030, &axi_qos->qosctset3); 538 writel(0x00002030, &axi_qos->qosctset3);
538 writel(0x00000001, &axi_qos->qosreqctr); 539 writel(0x00000001, &axi_qos->qosreqctr);
539 writel(0x00002064, &axi_qos->qosthres0); 540 writel(0x00002064, &axi_qos->qosthres0);
540 writel(0x00002004, &axi_qos->qosthres1); 541 writel(0x00002004, &axi_qos->qosthres1);
541 writel(0x00000000, &axi_qos->qosthres2); 542 writel(0x00000000, &axi_qos->qosthres2);
542 writel(0x00000001, &axi_qos->qosqon); 543 writel(0x00000001, &axi_qos->qosqon);
543 544
544 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; 545 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
545 writel(0x00000000, &axi_qos->qosconf); 546 writel(0x00000000, &axi_qos->qosconf);
546 writel(0x00002053, &axi_qos->qosctset0); 547 writel(0x00002053, &axi_qos->qosctset0);
547 writel(0x00000001, &axi_qos->qosreqctr); 548 writel(0x00000001, &axi_qos->qosreqctr);
548 writel(0x00002064, &axi_qos->qosthres0); 549 writel(0x00002064, &axi_qos->qosthres0);
549 writel(0x00002004, &axi_qos->qosthres1); 550 writel(0x00002004, &axi_qos->qosthres1);
550 writel(0x00000000, &axi_qos->qosthres2); 551 writel(0x00000000, &axi_qos->qosthres2);
551 writel(0x00000001, &axi_qos->qosqon); 552 writel(0x00000001, &axi_qos->qosqon);
552 553
553 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; 554 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
554 writel(0x00000000, &axi_qos->qosconf); 555 writel(0x00000000, &axi_qos->qosconf);
555 writel(0x0000206E, &axi_qos->qosctset0); 556 writel(0x0000206E, &axi_qos->qosctset0);
556 writel(0x00000001, &axi_qos->qosreqctr); 557 writel(0x00000001, &axi_qos->qosreqctr);
557 writel(0x00002064, &axi_qos->qosthres0); 558 writel(0x00002064, &axi_qos->qosthres0);
558 writel(0x00002004, &axi_qos->qosthres1); 559 writel(0x00002004, &axi_qos->qosthres1);
559 writel(0x00000000, &axi_qos->qosthres2); 560 writel(0x00000000, &axi_qos->qosthres2);
560 writel(0x00000001, &axi_qos->qosqon); 561 writel(0x00000001, &axi_qos->qosqon);
561 562
562 /* QoS Register (SYS-AXI256) */ 563 /* QoS Register (SYS-AXI256) */
563 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; 564 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
564 writel(0x00000002, &axi_qos->qosconf); 565 writel(0x00000002, &axi_qos->qosconf);
565 writel(0x000020EB, &axi_qos->qosctset0); 566 writel(0x000020EB, &axi_qos->qosctset0);
566 writel(0x00002096, &axi_qos->qosctset1); 567 writel(0x00002096, &axi_qos->qosctset1);
567 writel(0x00002030, &axi_qos->qosctset2); 568 writel(0x00002030, &axi_qos->qosctset2);
568 writel(0x00002030, &axi_qos->qosctset3); 569 writel(0x00002030, &axi_qos->qosctset3);
569 writel(0x00000001, &axi_qos->qosreqctr); 570 writel(0x00000001, &axi_qos->qosreqctr);
570 writel(0x00002064, &axi_qos->qosthres0); 571 writel(0x00002064, &axi_qos->qosthres0);
571 writel(0x00002004, &axi_qos->qosthres1); 572 writel(0x00002004, &axi_qos->qosthres1);
572 writel(0x00000000, &axi_qos->qosthres2); 573 writel(0x00000000, &axi_qos->qosthres2);
573 writel(0x00000001, &axi_qos->qosqon); 574 writel(0x00000001, &axi_qos->qosqon);
574 575
575 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; 576 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
576 writel(0x00000002, &axi_qos->qosconf); 577 writel(0x00000002, &axi_qos->qosconf);
577 writel(0x000020EB, &axi_qos->qosctset0); 578 writel(0x000020EB, &axi_qos->qosctset0);
578 writel(0x00002096, &axi_qos->qosctset1); 579 writel(0x00002096, &axi_qos->qosctset1);
579 writel(0x00002030, &axi_qos->qosctset2); 580 writel(0x00002030, &axi_qos->qosctset2);
580 writel(0x00002030, &axi_qos->qosctset3); 581 writel(0x00002030, &axi_qos->qosctset3);
581 writel(0x00000001, &axi_qos->qosreqctr); 582 writel(0x00000001, &axi_qos->qosreqctr);
582 writel(0x00002064, &axi_qos->qosthres0); 583 writel(0x00002064, &axi_qos->qosthres0);
583 writel(0x00002004, &axi_qos->qosthres1); 584 writel(0x00002004, &axi_qos->qosthres1);
584 writel(0x00000000, &axi_qos->qosthres2); 585 writel(0x00000000, &axi_qos->qosthres2);
585 writel(0x00000001, &axi_qos->qosqon); 586 writel(0x00000001, &axi_qos->qosqon);
586 587
587 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; 588 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
588 writel(0x00000002, &axi_qos->qosconf); 589 writel(0x00000002, &axi_qos->qosconf);
589 writel(0x000020EB, &axi_qos->qosctset0); 590 writel(0x000020EB, &axi_qos->qosctset0);
590 writel(0x00002096, &axi_qos->qosctset1); 591 writel(0x00002096, &axi_qos->qosctset1);
591 writel(0x00002030, &axi_qos->qosctset2); 592 writel(0x00002030, &axi_qos->qosctset2);
592 writel(0x00002030, &axi_qos->qosctset3); 593 writel(0x00002030, &axi_qos->qosctset3);
593 writel(0x00000001, &axi_qos->qosreqctr); 594 writel(0x00000001, &axi_qos->qosreqctr);
594 writel(0x00002064, &axi_qos->qosthres0); 595 writel(0x00002064, &axi_qos->qosthres0);
595 writel(0x00002004, &axi_qos->qosthres1); 596 writel(0x00002004, &axi_qos->qosthres1);
596 writel(0x00000000, &axi_qos->qosthres2); 597 writel(0x00000000, &axi_qos->qosthres2);
597 writel(0x00000001, &axi_qos->qosqon); 598 writel(0x00000001, &axi_qos->qosqon);
598 599
599 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; 600 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
600 writel(0x00000002, &axi_qos->qosconf); 601 writel(0x00000002, &axi_qos->qosconf);
601 writel(0x000020EB, &axi_qos->qosctset0); 602 writel(0x000020EB, &axi_qos->qosctset0);
602 writel(0x00002096, &axi_qos->qosctset1); 603 writel(0x00002096, &axi_qos->qosctset1);
603 writel(0x00002030, &axi_qos->qosctset2); 604 writel(0x00002030, &axi_qos->qosctset2);
604 writel(0x00002030, &axi_qos->qosctset3); 605 writel(0x00002030, &axi_qos->qosctset3);
605 writel(0x00000001, &axi_qos->qosreqctr); 606 writel(0x00000001, &axi_qos->qosreqctr);
606 writel(0x00002064, &axi_qos->qosthres0); 607 writel(0x00002064, &axi_qos->qosthres0);
607 writel(0x00002004, &axi_qos->qosthres1); 608 writel(0x00002004, &axi_qos->qosthres1);
608 writel(0x00000000, &axi_qos->qosthres2); 609 writel(0x00000000, &axi_qos->qosthres2);
609 writel(0x00000001, &axi_qos->qosqon); 610 writel(0x00000001, &axi_qos->qosqon);
610 611
611 /* QoS Register (CCI-AXI) */ 612 /* QoS Register (CCI-AXI) */
612 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; 613 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
613 writel(0x00000001, &axi_qos->qosconf); 614 writel(0x00000001, &axi_qos->qosconf);
614 writel(0x00002004, &axi_qos->qosctset0); 615 writel(0x00002004, &axi_qos->qosctset0);
615 writel(0x00002096, &axi_qos->qosctset1); 616 writel(0x00002096, &axi_qos->qosctset1);
616 writel(0x00002030, &axi_qos->qosctset2); 617 writel(0x00002030, &axi_qos->qosctset2);
617 writel(0x00002030, &axi_qos->qosctset3); 618 writel(0x00002030, &axi_qos->qosctset3);
618 writel(0x00000001, &axi_qos->qosreqctr); 619 writel(0x00000001, &axi_qos->qosreqctr);
619 writel(0x00002064, &axi_qos->qosthres0); 620 writel(0x00002064, &axi_qos->qosthres0);
620 writel(0x00002004, &axi_qos->qosthres1); 621 writel(0x00002004, &axi_qos->qosthres1);
621 writel(0x00000000, &axi_qos->qosthres2); 622 writel(0x00000000, &axi_qos->qosthres2);
622 writel(0x00000001, &axi_qos->qosqon); 623 writel(0x00000001, &axi_qos->qosqon);
623 624
624 axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; 625 axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
625 writel(0x00000002, &axi_qos->qosconf); 626 writel(0x00000002, &axi_qos->qosconf);
626 writel(0x00002245, &axi_qos->qosctset0); 627 writel(0x00002245, &axi_qos->qosctset0);
627 writel(0x00002096, &axi_qos->qosctset1); 628 writel(0x00002096, &axi_qos->qosctset1);
628 writel(0x00002030, &axi_qos->qosctset2); 629 writel(0x00002030, &axi_qos->qosctset2);
629 writel(0x00002030, &axi_qos->qosctset3); 630 writel(0x00002030, &axi_qos->qosctset3);
630 writel(0x00000001, &axi_qos->qosreqctr); 631 writel(0x00000001, &axi_qos->qosreqctr);
631 writel(0x00002064, &axi_qos->qosthres0); 632 writel(0x00002064, &axi_qos->qosthres0);
632 writel(0x00002004, &axi_qos->qosthres1); 633 writel(0x00002004, &axi_qos->qosthres1);
633 writel(0x00000000, &axi_qos->qosthres2); 634 writel(0x00000000, &axi_qos->qosthres2);
634 writel(0x00000001, &axi_qos->qosqon); 635 writel(0x00000001, &axi_qos->qosqon);
635 636
636 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; 637 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
637 writel(0x00000001, &axi_qos->qosconf); 638 writel(0x00000001, &axi_qos->qosconf);
638 writel(0x00002004, &axi_qos->qosctset0); 639 writel(0x00002004, &axi_qos->qosctset0);
639 writel(0x00002096, &axi_qos->qosctset1); 640 writel(0x00002096, &axi_qos->qosctset1);
640 writel(0x00002030, &axi_qos->qosctset2); 641 writel(0x00002030, &axi_qos->qosctset2);
641 writel(0x00002030, &axi_qos->qosctset3); 642 writel(0x00002030, &axi_qos->qosctset3);
642 writel(0x00000001, &axi_qos->qosreqctr); 643 writel(0x00000001, &axi_qos->qosreqctr);
643 writel(0x00002064, &axi_qos->qosthres0); 644 writel(0x00002064, &axi_qos->qosthres0);
644 writel(0x00002004, &axi_qos->qosthres1); 645 writel(0x00002004, &axi_qos->qosthres1);
645 writel(0x00000000, &axi_qos->qosthres2); 646 writel(0x00000000, &axi_qos->qosthres2);
646 writel(0x00000001, &axi_qos->qosqon); 647 writel(0x00000001, &axi_qos->qosqon);
647 648
648 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; 649 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
649 writel(0x00000001, &axi_qos->qosconf); 650 writel(0x00000001, &axi_qos->qosconf);
650 writel(0x00002004, &axi_qos->qosctset0); 651 writel(0x00002004, &axi_qos->qosctset0);
651 writel(0x00002096, &axi_qos->qosctset1); 652 writel(0x00002096, &axi_qos->qosctset1);
652 writel(0x00002030, &axi_qos->qosctset2); 653 writel(0x00002030, &axi_qos->qosctset2);
653 writel(0x00002030, &axi_qos->qosctset3); 654 writel(0x00002030, &axi_qos->qosctset3);
654 writel(0x00000001, &axi_qos->qosreqctr); 655 writel(0x00000001, &axi_qos->qosreqctr);
655 writel(0x00002064, &axi_qos->qosthres0); 656 writel(0x00002064, &axi_qos->qosthres0);
656 writel(0x00002004, &axi_qos->qosthres1); 657 writel(0x00002004, &axi_qos->qosthres1);
657 writel(0x00000000, &axi_qos->qosthres2); 658 writel(0x00000000, &axi_qos->qosthres2);
658 writel(0x00000001, &axi_qos->qosqon); 659 writel(0x00000001, &axi_qos->qosqon);
659 660
660 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; 661 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
661 writel(0x00000001, &axi_qos->qosconf); 662 writel(0x00000001, &axi_qos->qosconf);
662 writel(0x00002004, &axi_qos->qosctset0); 663 writel(0x00002004, &axi_qos->qosctset0);
663 writel(0x00002096, &axi_qos->qosctset1); 664 writel(0x00002096, &axi_qos->qosctset1);
664 writel(0x00002030, &axi_qos->qosctset2); 665 writel(0x00002030, &axi_qos->qosctset2);
665 writel(0x00002030, &axi_qos->qosctset3); 666 writel(0x00002030, &axi_qos->qosctset3);
666 writel(0x00000001, &axi_qos->qosreqctr); 667 writel(0x00000001, &axi_qos->qosreqctr);
667 writel(0x00002064, &axi_qos->qosthres0); 668 writel(0x00002064, &axi_qos->qosthres0);
668 writel(0x00002004, &axi_qos->qosthres1); 669 writel(0x00002004, &axi_qos->qosthres1);
669 writel(0x00000000, &axi_qos->qosthres2); 670 writel(0x00000000, &axi_qos->qosthres2);
670 writel(0x00000001, &axi_qos->qosqon); 671 writel(0x00000001, &axi_qos->qosqon);
671 672
672 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; 673 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
673 writel(0x00000002, &axi_qos->qosconf); 674 writel(0x00000002, &axi_qos->qosconf);
674 writel(0x00002245, &axi_qos->qosctset0); 675 writel(0x00002245, &axi_qos->qosctset0);
675 writel(0x00002096, &axi_qos->qosctset1); 676 writel(0x00002096, &axi_qos->qosctset1);
676 writel(0x00002030, &axi_qos->qosctset2); 677 writel(0x00002030, &axi_qos->qosctset2);
677 writel(0x00002030, &axi_qos->qosctset3); 678 writel(0x00002030, &axi_qos->qosctset3);
678 writel(0x00000001, &axi_qos->qosreqctr); 679 writel(0x00000001, &axi_qos->qosreqctr);
679 writel(0x00002064, &axi_qos->qosthres0); 680 writel(0x00002064, &axi_qos->qosthres0);
680 writel(0x00002004, &axi_qos->qosthres1); 681 writel(0x00002004, &axi_qos->qosthres1);
681 writel(0x00000000, &axi_qos->qosthres2); 682 writel(0x00000000, &axi_qos->qosthres2);
682 writel(0x00000001, &axi_qos->qosqon); 683 writel(0x00000001, &axi_qos->qosqon);
683 684
684 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; 685 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
685 writel(0x00000001, &axi_qos->qosconf); 686 writel(0x00000001, &axi_qos->qosconf);
686 writel(0x00002004, &axi_qos->qosctset0); 687 writel(0x00002004, &axi_qos->qosctset0);
687 writel(0x00002096, &axi_qos->qosctset1); 688 writel(0x00002096, &axi_qos->qosctset1);
688 writel(0x00002030, &axi_qos->qosctset2); 689 writel(0x00002030, &axi_qos->qosctset2);
689 writel(0x00002030, &axi_qos->qosctset3); 690 writel(0x00002030, &axi_qos->qosctset3);
690 writel(0x00000001, &axi_qos->qosreqctr); 691 writel(0x00000001, &axi_qos->qosreqctr);
691 writel(0x00002064, &axi_qos->qosthres0); 692 writel(0x00002064, &axi_qos->qosthres0);
692 writel(0x00002004, &axi_qos->qosthres1); 693 writel(0x00002004, &axi_qos->qosthres1);
693 writel(0x00000000, &axi_qos->qosthres2); 694 writel(0x00000000, &axi_qos->qosthres2);
694 writel(0x00000001, &axi_qos->qosqon); 695 writel(0x00000001, &axi_qos->qosqon);
695 696
696 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; 697 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
697 writel(0x00000001, &axi_qos->qosconf); 698 writel(0x00000001, &axi_qos->qosconf);
698 writel(0x00002004, &axi_qos->qosctset0); 699 writel(0x00002004, &axi_qos->qosctset0);
699 writel(0x00002096, &axi_qos->qosctset1); 700 writel(0x00002096, &axi_qos->qosctset1);
700 writel(0x00002030, &axi_qos->qosctset2); 701 writel(0x00002030, &axi_qos->qosctset2);
701 writel(0x00002030, &axi_qos->qosctset3); 702 writel(0x00002030, &axi_qos->qosctset3);
702 writel(0x00000001, &axi_qos->qosreqctr); 703 writel(0x00000001, &axi_qos->qosreqctr);
703 writel(0x00002064, &axi_qos->qosthres0); 704 writel(0x00002064, &axi_qos->qosthres0);
704 writel(0x00002004, &axi_qos->qosthres1); 705 writel(0x00002004, &axi_qos->qosthres1);
705 writel(0x00000000, &axi_qos->qosthres2); 706 writel(0x00000000, &axi_qos->qosthres2);
706 writel(0x00000001, &axi_qos->qosqon); 707 writel(0x00000001, &axi_qos->qosqon);
707 708
708 /* QoS Register (Media-AXI) */ 709 /* QoS Register (Media-AXI) */
709 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; 710 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
710 writel(0x00000002, &axi_qos->qosconf); 711 writel(0x00000002, &axi_qos->qosconf);
711 writel(0x000020DC, &axi_qos->qosctset0); 712 writel(0x000020DC, &axi_qos->qosctset0);
712 writel(0x00002096, &axi_qos->qosctset1); 713 writel(0x00002096, &axi_qos->qosctset1);
713 writel(0x00002030, &axi_qos->qosctset2); 714 writel(0x00002030, &axi_qos->qosctset2);
714 writel(0x00002030, &axi_qos->qosctset3); 715 writel(0x00002030, &axi_qos->qosctset3);
715 writel(0x00000020, &axi_qos->qosreqctr); 716 writel(0x00000020, &axi_qos->qosreqctr);
716 writel(0x000020AA, &axi_qos->qosthres0); 717 writel(0x000020AA, &axi_qos->qosthres0);
717 writel(0x00002032, &axi_qos->qosthres1); 718 writel(0x00002032, &axi_qos->qosthres1);
718 writel(0x00000001, &axi_qos->qosthres2); 719 writel(0x00000001, &axi_qos->qosthres2);
719 720
720 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; 721 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
721 writel(0x00000002, &axi_qos->qosconf); 722 writel(0x00000002, &axi_qos->qosconf);
722 writel(0x000020DC, &axi_qos->qosctset0); 723 writel(0x000020DC, &axi_qos->qosctset0);
723 writel(0x00002096, &axi_qos->qosctset1); 724 writel(0x00002096, &axi_qos->qosctset1);
724 writel(0x00002030, &axi_qos->qosctset2); 725 writel(0x00002030, &axi_qos->qosctset2);
725 writel(0x00002030, &axi_qos->qosctset3); 726 writel(0x00002030, &axi_qos->qosctset3);
726 writel(0x00000020, &axi_qos->qosreqctr); 727 writel(0x00000020, &axi_qos->qosreqctr);
727 writel(0x000020AA, &axi_qos->qosthres0); 728 writel(0x000020AA, &axi_qos->qosthres0);
728 writel(0x00002032, &axi_qos->qosthres1); 729 writel(0x00002032, &axi_qos->qosthres1);
729 writel(0x00000001, &axi_qos->qosthres2); 730 writel(0x00000001, &axi_qos->qosthres2);
730 731
731 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; 732 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
732 writel(0x00000001, &axi_qos->qosconf); 733 writel(0x00000001, &axi_qos->qosconf);
733 writel(0x00002190, &axi_qos->qosctset0); 734 writel(0x00002190, &axi_qos->qosctset0);
734 writel(0x00000020, &axi_qos->qosreqctr); 735 writel(0x00000020, &axi_qos->qosreqctr);
735 writel(0x00002064, &axi_qos->qosthres0); 736 writel(0x00002064, &axi_qos->qosthres0);
736 writel(0x00002004, &axi_qos->qosthres1); 737 writel(0x00002004, &axi_qos->qosthres1);
737 writel(0x00000001, &axi_qos->qosthres2); 738 writel(0x00000001, &axi_qos->qosthres2);
738 writel(0x00000001, &axi_qos->qosqon); 739 writel(0x00000001, &axi_qos->qosqon);
739 740
740 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; 741 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
741 writel(0x00000001, &axi_qos->qosconf); 742 writel(0x00000001, &axi_qos->qosconf);
742 writel(0x00002190, &axi_qos->qosctset0); 743 writel(0x00002190, &axi_qos->qosctset0);
743 writel(0x00000020, &axi_qos->qosreqctr); 744 writel(0x00000020, &axi_qos->qosreqctr);
744 writel(0x00000001, &axi_qos->qosthres0); 745 writel(0x00000001, &axi_qos->qosthres0);
745 writel(0x00000001, &axi_qos->qosthres1); 746 writel(0x00000001, &axi_qos->qosthres1);
746 writel(0x00000001, &axi_qos->qosthres2); 747 writel(0x00000001, &axi_qos->qosthres2);
747 writel(0x00000001, &axi_qos->qosqon); 748 writel(0x00000001, &axi_qos->qosqon);
748 749
749 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; 750 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
750 writel(0x00000001, &axi_qos->qosconf); 751 writel(0x00000001, &axi_qos->qosconf);
751 writel(0x00002190, &axi_qos->qosctset0); 752 writel(0x00002190, &axi_qos->qosctset0);
752 writel(0x00000020, &axi_qos->qosreqctr); 753 writel(0x00000020, &axi_qos->qosreqctr);
753 writel(0x00002064, &axi_qos->qosthres0); 754 writel(0x00002064, &axi_qos->qosthres0);
754 writel(0x00002004, &axi_qos->qosthres1); 755 writel(0x00002004, &axi_qos->qosthres1);
755 writel(0x00000001, &axi_qos->qosthres2); 756 writel(0x00000001, &axi_qos->qosthres2);
756 writel(0x00000001, &axi_qos->qosqon); 757 writel(0x00000001, &axi_qos->qosqon);
757 758
758 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; 759 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
759 writel(0x00000001, &axi_qos->qosconf); 760 writel(0x00000001, &axi_qos->qosconf);
760 writel(0x00002190, &axi_qos->qosctset0); 761 writel(0x00002190, &axi_qos->qosctset0);
761 writel(0x00000020, &axi_qos->qosreqctr); 762 writel(0x00000020, &axi_qos->qosreqctr);
762 writel(0x00000001, &axi_qos->qosthres0); 763 writel(0x00000001, &axi_qos->qosthres0);
763 writel(0x00000001, &axi_qos->qosthres1); 764 writel(0x00000001, &axi_qos->qosthres1);
764 writel(0x00000001, &axi_qos->qosthres2); 765 writel(0x00000001, &axi_qos->qosthres2);
765 writel(0x00000001, &axi_qos->qosqon); 766 writel(0x00000001, &axi_qos->qosqon);
766 767
767 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; 768 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
768 writel(0x00000001, &axi_qos->qosconf); 769 writel(0x00000001, &axi_qos->qosconf);
769 writel(0x00002190, &axi_qos->qosctset0); 770 writel(0x00002190, &axi_qos->qosctset0);
770 writel(0x00000020, &axi_qos->qosreqctr); 771 writel(0x00000020, &axi_qos->qosreqctr);
771 writel(0x00002064, &axi_qos->qosthres0); 772 writel(0x00002064, &axi_qos->qosthres0);
772 writel(0x00002004, &axi_qos->qosthres1); 773 writel(0x00002004, &axi_qos->qosthres1);
773 writel(0x00000001, &axi_qos->qosthres2); 774 writel(0x00000001, &axi_qos->qosthres2);
774 writel(0x00000001, &axi_qos->qosqon); 775 writel(0x00000001, &axi_qos->qosqon);
775 776
776 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; 777 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
777 writel(0x00000001, &axi_qos->qosconf); 778 writel(0x00000001, &axi_qos->qosconf);
778 writel(0x00002190, &axi_qos->qosctset0); 779 writel(0x00002190, &axi_qos->qosctset0);
779 writel(0x00000020, &axi_qos->qosreqctr); 780 writel(0x00000020, &axi_qos->qosreqctr);
780 writel(0x00000001, &axi_qos->qosthres0); 781 writel(0x00000001, &axi_qos->qosthres0);
781 writel(0x00000001, &axi_qos->qosthres1); 782 writel(0x00000001, &axi_qos->qosthres1);
782 writel(0x00000001, &axi_qos->qosthres2); 783 writel(0x00000001, &axi_qos->qosthres2);
783 writel(0x00000001, &axi_qos->qosqon); 784 writel(0x00000001, &axi_qos->qosqon);
784 785
785 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; 786 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
786 writel(0x00000001, &axi_qos->qosconf); 787 writel(0x00000001, &axi_qos->qosconf);
787 writel(0x00001FF0, &axi_qos->qosctset0); 788 writel(0x00001FF0, &axi_qos->qosctset0);
788 writel(0x00000020, &axi_qos->qosreqctr); 789 writel(0x00000020, &axi_qos->qosreqctr);
789 writel(0x00002064, &axi_qos->qosthres0); 790 writel(0x00002064, &axi_qos->qosthres0);
790 writel(0x00002004, &axi_qos->qosthres1); 791 writel(0x00002004, &axi_qos->qosthres1);
791 writel(0x00002001, &axi_qos->qosthres2); 792 writel(0x00002001, &axi_qos->qosthres2);
792 writel(0x00000001, &axi_qos->qosqon); 793 writel(0x00000001, &axi_qos->qosqon);
793 794
794 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; 795 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
795 writel(0x00000001, &axi_qos->qosconf); 796 writel(0x00000001, &axi_qos->qosconf);
796 writel(0x000020C8, &axi_qos->qosctset0); 797 writel(0x000020C8, &axi_qos->qosctset0);
797 writel(0x00000020, &axi_qos->qosreqctr); 798 writel(0x00000020, &axi_qos->qosreqctr);
798 writel(0x00002064, &axi_qos->qosthres0); 799 writel(0x00002064, &axi_qos->qosthres0);
799 writel(0x00002004, &axi_qos->qosthres1); 800 writel(0x00002004, &axi_qos->qosthres1);
800 writel(0x00000001, &axi_qos->qosthres2); 801 writel(0x00000001, &axi_qos->qosthres2);
801 writel(0x00000001, &axi_qos->qosqon); 802 writel(0x00000001, &axi_qos->qosqon);
802 803
803 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; 804 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
804 writel(0x00000001, &axi_qos->qosconf); 805 writel(0x00000001, &axi_qos->qosconf);
805 writel(0x000020C8, &axi_qos->qosctset0); 806 writel(0x000020C8, &axi_qos->qosctset0);
806 writel(0x00000020, &axi_qos->qosreqctr); 807 writel(0x00000020, &axi_qos->qosreqctr);
807 writel(0x00000001, &axi_qos->qosthres0); 808 writel(0x00000001, &axi_qos->qosthres0);
808 writel(0x00000001, &axi_qos->qosthres1); 809 writel(0x00000001, &axi_qos->qosthres1);
809 writel(0x00000001, &axi_qos->qosthres2); 810 writel(0x00000001, &axi_qos->qosthres2);
810 writel(0x00000001, &axi_qos->qosqon); 811 writel(0x00000001, &axi_qos->qosqon);
811 812
812 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; 813 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
813 writel(0x00000001, &axi_qos->qosconf); 814 writel(0x00000001, &axi_qos->qosconf);
814 writel(0x000020C8, &axi_qos->qosctset0); 815 writel(0x000020C8, &axi_qos->qosctset0);
815 writel(0x00000020, &axi_qos->qosreqctr); 816 writel(0x00000020, &axi_qos->qosreqctr);
816 writel(0x00002064, &axi_qos->qosthres0); 817 writel(0x00002064, &axi_qos->qosthres0);
817 writel(0x00002004, &axi_qos->qosthres1); 818 writel(0x00002004, &axi_qos->qosthres1);
818 writel(0x00000001, &axi_qos->qosthres2); 819 writel(0x00000001, &axi_qos->qosthres2);
819 writel(0x00000001, &axi_qos->qosqon); 820 writel(0x00000001, &axi_qos->qosqon);
820 821
821 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; 822 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
822 writel(0x00000001, &axi_qos->qosconf); 823 writel(0x00000001, &axi_qos->qosconf);
823 writel(0x000020C8, &axi_qos->qosctset0); 824 writel(0x000020C8, &axi_qos->qosctset0);
824 writel(0x00000020, &axi_qos->qosreqctr); 825 writel(0x00000020, &axi_qos->qosreqctr);
825 writel(0x00002064, &axi_qos->qosthres0); 826 writel(0x00002064, &axi_qos->qosthres0);
826 writel(0x00002004, &axi_qos->qosthres1); 827 writel(0x00002004, &axi_qos->qosthres1);
827 writel(0x00000001, &axi_qos->qosthres2); 828 writel(0x00000001, &axi_qos->qosthres2);
828 writel(0x00000001, &axi_qos->qosqon); 829 writel(0x00000001, &axi_qos->qosqon);
829 830
830 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; 831 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
831 writel(0x00000001, &axi_qos->qosconf); 832 writel(0x00000001, &axi_qos->qosconf);
832 writel(0x000020C8, &axi_qos->qosctset0); 833 writel(0x000020C8, &axi_qos->qosctset0);
833 writel(0x00000020, &axi_qos->qosreqctr); 834 writel(0x00000020, &axi_qos->qosreqctr);
834 writel(0x00002064, &axi_qos->qosthres0); 835 writel(0x00002064, &axi_qos->qosthres0);
835 writel(0x00002004, &axi_qos->qosthres1); 836 writel(0x00002004, &axi_qos->qosthres1);
836 writel(0x00000001, &axi_qos->qosthres2); 837 writel(0x00000001, &axi_qos->qosthres2);
837 writel(0x00000001, &axi_qos->qosqon); 838 writel(0x00000001, &axi_qos->qosqon);
838 839
839 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; 840 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
840 writel(0x00000001, &axi_qos->qosconf); 841 writel(0x00000001, &axi_qos->qosconf);
841 writel(0x000020C8, &axi_qos->qosctset0); 842 writel(0x000020C8, &axi_qos->qosctset0);
842 writel(0x00000020, &axi_qos->qosreqctr); 843 writel(0x00000020, &axi_qos->qosreqctr);
843 writel(0x00000001, &axi_qos->qosthres0); 844 writel(0x00000001, &axi_qos->qosthres0);
844 writel(0x00000001, &axi_qos->qosthres1); 845 writel(0x00000001, &axi_qos->qosthres1);
845 writel(0x00000001, &axi_qos->qosthres2); 846 writel(0x00000001, &axi_qos->qosthres2);
846 writel(0x00000001, &axi_qos->qosqon); 847 writel(0x00000001, &axi_qos->qosqon);
847 848
848 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; 849 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
849 writel(0x00000001, &axi_qos->qosconf); 850 writel(0x00000001, &axi_qos->qosconf);
850 writel(0x000020C8, &axi_qos->qosctset0); 851 writel(0x000020C8, &axi_qos->qosctset0);
851 writel(0x00000020, &axi_qos->qosreqctr); 852 writel(0x00000020, &axi_qos->qosreqctr);
852 writel(0x00002064, &axi_qos->qosthres0); 853 writel(0x00002064, &axi_qos->qosthres0);
853 writel(0x00002004, &axi_qos->qosthres1); 854 writel(0x00002004, &axi_qos->qosthres1);
854 writel(0x00000001, &axi_qos->qosthres2); 855 writel(0x00000001, &axi_qos->qosthres2);
855 writel(0x00000001, &axi_qos->qosqon); 856 writel(0x00000001, &axi_qos->qosqon);
856 857
857 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; 858 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
858 writel(0x00000001, &axi_qos->qosconf); 859 writel(0x00000001, &axi_qos->qosconf);
859 writel(0x000020C8, &axi_qos->qosctset0); 860 writel(0x000020C8, &axi_qos->qosctset0);
860 writel(0x00000020, &axi_qos->qosreqctr); 861 writel(0x00000020, &axi_qos->qosreqctr);
861 writel(0x00002064, &axi_qos->qosthres0); 862 writel(0x00002064, &axi_qos->qosthres0);
862 writel(0x00002004, &axi_qos->qosthres1); 863 writel(0x00002004, &axi_qos->qosthres1);
863 writel(0x00000001, &axi_qos->qosthres2); 864 writel(0x00000001, &axi_qos->qosthres2);
864 writel(0x00000001, &axi_qos->qosqon); 865 writel(0x00000001, &axi_qos->qosqon);
865 866
866 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; 867 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
867 writel(0x00000003, &axi_qos->qosconf); 868 writel(0x00000003, &axi_qos->qosconf);
868 writel(0x000020C8, &axi_qos->qosctset0); 869 writel(0x000020C8, &axi_qos->qosctset0);
869 writel(0x00002064, &axi_qos->qosthres0); 870 writel(0x00002064, &axi_qos->qosthres0);
870 writel(0x00002004, &axi_qos->qosthres1); 871 writel(0x00002004, &axi_qos->qosthres1);
871 writel(0x00000001, &axi_qos->qosthres2); 872 writel(0x00000001, &axi_qos->qosthres2);
872 writel(0x00000001, &axi_qos->qosqon); 873 writel(0x00000001, &axi_qos->qosqon);
873 874
874 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; 875 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
875 writel(0x00000003, &axi_qos->qosconf); 876 writel(0x00000003, &axi_qos->qosconf);
876 writel(0x000020C8, &axi_qos->qosctset0); 877 writel(0x000020C8, &axi_qos->qosctset0);
877 writel(0x00002064, &axi_qos->qosthres0); 878 writel(0x00002064, &axi_qos->qosthres0);
878 writel(0x00002004, &axi_qos->qosthres1); 879 writel(0x00002004, &axi_qos->qosthres1);
879 writel(0x00000001, &axi_qos->qosthres2); 880 writel(0x00000001, &axi_qos->qosthres2);
880 writel(0x00000001, &axi_qos->qosqon); 881 writel(0x00000001, &axi_qos->qosqon);
881 882
882 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; 883 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
883 writel(0x00000003, &axi_qos->qosconf); 884 writel(0x00000003, &axi_qos->qosconf);
884 writel(0x00002063, &axi_qos->qosctset0); 885 writel(0x00002063, &axi_qos->qosctset0);
885 writel(0x00000001, &axi_qos->qosreqctr); 886 writel(0x00000001, &axi_qos->qosreqctr);
886 writel(0x00002064, &axi_qos->qosthres0); 887 writel(0x00002064, &axi_qos->qosthres0);
887 writel(0x00002004, &axi_qos->qosthres1); 888 writel(0x00002004, &axi_qos->qosthres1);
888 writel(0x00000001, &axi_qos->qosthres2); 889 writel(0x00000001, &axi_qos->qosthres2);
889 writel(0x00000001, &axi_qos->qosqon); 890 writel(0x00000001, &axi_qos->qosqon);
890 891
891 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; 892 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
892 writel(0x00000003, &axi_qos->qosconf); 893 writel(0x00000003, &axi_qos->qosconf);
893 writel(0x00002063, &axi_qos->qosctset0); 894 writel(0x00002063, &axi_qos->qosctset0);
894 writel(0x00000001, &axi_qos->qosreqctr); 895 writel(0x00000001, &axi_qos->qosreqctr);
895 writel(0x00002064, &axi_qos->qosthres0); 896 writel(0x00002064, &axi_qos->qosthres0);
896 writel(0x00002004, &axi_qos->qosthres1); 897 writel(0x00002004, &axi_qos->qosthres1);
897 writel(0x00000001, &axi_qos->qosthres2); 898 writel(0x00000001, &axi_qos->qosthres2);
898 writel(0x00000001, &axi_qos->qosqon); 899 writel(0x00000001, &axi_qos->qosqon);
899 900
900 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; 901 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
901 writel(0x00000001, &axi_qos->qosconf); 902 writel(0x00000001, &axi_qos->qosconf);
902 writel(0x00002073, &axi_qos->qosctset0); 903 writel(0x00002073, &axi_qos->qosctset0);
903 writel(0x00000020, &axi_qos->qosreqctr); 904 writel(0x00000020, &axi_qos->qosreqctr);
904 writel(0x00002064, &axi_qos->qosthres0); 905 writel(0x00002064, &axi_qos->qosthres0);
905 writel(0x00002004, &axi_qos->qosthres1); 906 writel(0x00002004, &axi_qos->qosthres1);
906 writel(0x00000001, &axi_qos->qosthres2); 907 writel(0x00000001, &axi_qos->qosthres2);
907 writel(0x00000001, &axi_qos->qosqon); 908 writel(0x00000001, &axi_qos->qosqon);
908 909
909 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; 910 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
910 writel(0x00000001, &axi_qos->qosconf); 911 writel(0x00000001, &axi_qos->qosconf);
911 writel(0x00002073, &axi_qos->qosctset0); 912 writel(0x00002073, &axi_qos->qosctset0);
912 writel(0x00000020, &axi_qos->qosreqctr); 913 writel(0x00000020, &axi_qos->qosreqctr);
913 writel(0x00000001, &axi_qos->qosthres0); 914 writel(0x00000001, &axi_qos->qosthres0);
914 writel(0x00000001, &axi_qos->qosthres1); 915 writel(0x00000001, &axi_qos->qosthres1);
915 writel(0x00000001, &axi_qos->qosthres2); 916 writel(0x00000001, &axi_qos->qosthres2);
916 writel(0x00000001, &axi_qos->qosqon); 917 writel(0x00000001, &axi_qos->qosqon);
917 918
918 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; 919 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
919 writel(0x00000001, &axi_qos->qosconf); 920 writel(0x00000001, &axi_qos->qosconf);
920 writel(0x00002073, &axi_qos->qosctset0); 921 writel(0x00002073, &axi_qos->qosctset0);
921 writel(0x00000020, &axi_qos->qosreqctr); 922 writel(0x00000020, &axi_qos->qosreqctr);
922 writel(0x00002064, &axi_qos->qosthres0); 923 writel(0x00002064, &axi_qos->qosthres0);
923 writel(0x00002004, &axi_qos->qosthres1); 924 writel(0x00002004, &axi_qos->qosthres1);
924 writel(0x00000001, &axi_qos->qosthres2); 925 writel(0x00000001, &axi_qos->qosthres2);
925 writel(0x00000001, &axi_qos->qosqon); 926 writel(0x00000001, &axi_qos->qosqon);
926 927
927 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; 928 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
928 writel(0x00000001, &axi_qos->qosconf); 929 writel(0x00000001, &axi_qos->qosconf);
929 writel(0x00002073, &axi_qos->qosctset0); 930 writel(0x00002073, &axi_qos->qosctset0);
930 writel(0x00000020, &axi_qos->qosreqctr); 931 writel(0x00000020, &axi_qos->qosreqctr);
931 writel(0x00000001, &axi_qos->qosthres0); 932 writel(0x00000001, &axi_qos->qosthres0);
932 writel(0x00000001, &axi_qos->qosthres1); 933 writel(0x00000001, &axi_qos->qosthres1);
933 writel(0x00000001, &axi_qos->qosthres2); 934 writel(0x00000001, &axi_qos->qosthres2);
934 writel(0x00000001, &axi_qos->qosqon); 935 writel(0x00000001, &axi_qos->qosqon);
935 936
936 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; 937 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
937 writel(0x00000001, &axi_qos->qosconf); 938 writel(0x00000001, &axi_qos->qosconf);
938 writel(0x00002073, &axi_qos->qosctset0); 939 writel(0x00002073, &axi_qos->qosctset0);
939 writel(0x00000020, &axi_qos->qosreqctr); 940 writel(0x00000020, &axi_qos->qosreqctr);
940 writel(0x00002064, &axi_qos->qosthres0); 941 writel(0x00002064, &axi_qos->qosthres0);
941 writel(0x00002004, &axi_qos->qosthres1); 942 writel(0x00002004, &axi_qos->qosthres1);
942 writel(0x00000001, &axi_qos->qosthres2); 943 writel(0x00000001, &axi_qos->qosthres2);
943 writel(0x00000001, &axi_qos->qosqon); 944 writel(0x00000001, &axi_qos->qosqon);
944 } 945 }
946 #else /* CONFIG_RMOBILE_EXTRAM_BOOT */
947 void qos_init(void)
948 {
949 }
950 #endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
945 951
include/configs/alt.h
Diff comments   View file @ c9b59bf
1 /* 1 /*
2 * include/configs/alt.h 2 * include/configs/alt.h
3 * This file is alt board configuration. 3 * This file is alt board configuration.
4 * 4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0 7 * SPDX-License-Identifier: GPL-2.0
8 */ 8 */
9 9
10 #ifndef __ALT_H 10 #ifndef __ALT_H
11 #define __ALT_H 11 #define __ALT_H
12 12
13 #undef DEBUG 13 #undef DEBUG
14 #define CONFIG_ARMV7 14 #define CONFIG_ARMV7
15 #define CONFIG_R8A7794 15 #define CONFIG_R8A7794
16 #define CONFIG_RMOBILE_BOARD_STRING "Alt" 16 #define CONFIG_RMOBILE_BOARD_STRING "Alt"
17 #define CONFIG_SH_GPIO_PFC 17 #define CONFIG_SH_GPIO_PFC
18 18
19 #include <asm/arch/rmobile.h> 19 #include <asm/arch/rmobile.h>
20 20
21 #define CONFIG_CMD_EDITENV 21 #define CONFIG_CMD_EDITENV
22 #define CONFIG_CMD_SAVEENV 22 #define CONFIG_CMD_SAVEENV
23 #define CONFIG_CMD_MEMORY 23 #define CONFIG_CMD_MEMORY
24 #define CONFIG_CMD_DFL 24 #define CONFIG_CMD_DFL
25 #define CONFIG_CMD_SDRAM 25 #define CONFIG_CMD_SDRAM
26 #define CONFIG_CMD_RUN 26 #define CONFIG_CMD_RUN
27 #define CONFIG_CMD_LOADS 27 #define CONFIG_CMD_LOADS
28 #define CONFIG_CMD_NET 28 #define CONFIG_CMD_NET
29 #define CONFIG_CMD_MII 29 #define CONFIG_CMD_MII
30 #define CONFIG_CMD_PING 30 #define CONFIG_CMD_PING
31 #define CONFIG_CMD_DHCP 31 #define CONFIG_CMD_DHCP
32 #define CONFIG_CMD_NFS 32 #define CONFIG_CMD_NFS
33 #define CONFIG_CMD_BOOTZ 33 #define CONFIG_CMD_BOOTZ
34 #define CONFIG_CMD_SF 34 #define CONFIG_CMD_SF
35 #define CONFIG_CMD_SPI 35 #define CONFIG_CMD_SPI
36 36
37 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
38 #define CONFIG_SYS_TEXT_BASE 0x70000000
39 #else
37 #define CONFIG_SYS_TEXT_BASE 0xE6304000 40 #define CONFIG_SYS_TEXT_BASE 0xE6304000
41 #endif
38 #define CONFIG_SYS_THUMB_BUILD 42 #define CONFIG_SYS_THUMB_BUILD
39 #define CONFIG_SYS_GENERIC_BOARD 43 #define CONFIG_SYS_GENERIC_BOARD
40 44
41 #define CONFIG_CMDLINE_TAG 45 #define CONFIG_CMDLINE_TAG
42 #define CONFIG_SETUP_MEMORY_TAGS 46 #define CONFIG_SETUP_MEMORY_TAGS
43 #define CONFIG_INITRD_TAG 47 #define CONFIG_INITRD_TAG
44 #define CONFIG_CMDLINE_EDITING 48 #define CONFIG_CMDLINE_EDITING
45 49
46 #define CONFIG_OF_LIBFDT 50 #define CONFIG_OF_LIBFDT
47 #define BOARD_LATE_INIT 51 #define BOARD_LATE_INIT
48 52
49 #define CONFIG_BAUDRATE 38400 53 #define CONFIG_BAUDRATE 38400
50 #define CONFIG_BOOTDELAY 3 54 #define CONFIG_BOOTDELAY 3
51 #define CONFIG_BOOTARGS "" 55 #define CONFIG_BOOTARGS ""
52 56
53 #define CONFIG_VERSION_VARIABLE 57 #define CONFIG_VERSION_VARIABLE
54 #undef CONFIG_SHOW_BOOT_PROGRESS 58 #undef CONFIG_SHOW_BOOT_PROGRESS
55 59
56 #define CONFIG_ARCH_CPU_INIT 60 #define CONFIG_ARCH_CPU_INIT
57 #define CONFIG_DISPLAY_CPUINFO 61 #define CONFIG_DISPLAY_CPUINFO
58 #define CONFIG_DISPLAY_BOARDINFO 62 #define CONFIG_DISPLAY_BOARDINFO
59 #define CONFIG_BOARD_EARLY_INIT_F 63 #define CONFIG_BOARD_EARLY_INIT_F
60 #define CONFIG_TMU_TIMER 64 #define CONFIG_TMU_TIMER
61 65
66 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
67 #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
68 #else
62 #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 69 #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
70 #endif
63 #define STACK_AREA_SIZE 0xC000 71 #define STACK_AREA_SIZE 0xC000
64 #define LOW_LEVEL_MERAM_STACK \ 72 #define LOW_LEVEL_MERAM_STACK \
65 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 73 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
66 74
67 /* MEMORY */ 75 /* MEMORY */
68 #define ALT_SDRAM_BASE 0x40000000 76 #define ALT_SDRAM_BASE 0x40000000
69 #define ALT_SDRAM_SIZE (1024u * 1024 * 1024) 77 #define ALT_SDRAM_SIZE (1024u * 1024 * 1024)
70 #define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 78 #define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
71 79
72 #define CONFIG_SYS_LONGHELP 80 #define CONFIG_SYS_LONGHELP
73 #define CONFIG_SYS_CBSIZE 256 81 #define CONFIG_SYS_CBSIZE 256
74 #define CONFIG_SYS_PBSIZE 256 82 #define CONFIG_SYS_PBSIZE 256
75 #define CONFIG_SYS_MAXARGS 16 83 #define CONFIG_SYS_MAXARGS 16
76 #define CONFIG_SYS_BARGSIZE 512 84 #define CONFIG_SYS_BARGSIZE 512
77 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } 85 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
78 86
79 /* SCIF */ 87 /* SCIF */
80 #define CONFIG_SCIF_CONSOLE 88 #define CONFIG_SCIF_CONSOLE
81 #define CONFIG_CONS_SCIF2 89 #define CONFIG_CONS_SCIF2
82 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 90 #undef CONFIG_SYS_CONSOLE_INFO_QUIET
83 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 91 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
84 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 92 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
85 93
86 #define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE) 94 #define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE)
87 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 95 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
88 504 * 1024 * 1024) 96 504 * 1024 * 1024)
89 #undef CONFIG_SYS_ALT_MEMTEST 97 #undef CONFIG_SYS_ALT_MEMTEST
90 #undef CONFIG_SYS_MEMTEST_SCRATCH 98 #undef CONFIG_SYS_MEMTEST_SCRATCH
91 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 99 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
92 100
93 #define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE) 101 #define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE)
94 #define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE) 102 #define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE)
95 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) 103 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
96 #define CONFIG_NR_DRAM_BANKS 1 104 #define CONFIG_NR_DRAM_BANKS 1
97 105
98 #define CONFIG_SYS_MONITOR_BASE 0x00000000 106 #define CONFIG_SYS_MONITOR_BASE 0x00000000
99 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 107 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
100 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 108 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
101 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 109 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
102 110
103 /* FLASH */ 111 /* FLASH */
104 #define CONFIG_SPI 112 #define CONFIG_SPI
105 #define CONFIG_SPI_FLASH_BAR 113 #define CONFIG_SPI_FLASH_BAR
106 #define CONFIG_SH_QSPI 114 #define CONFIG_SH_QSPI
107 #define CONFIG_SPI_FLASH 115 #define CONFIG_SPI_FLASH
108 #define CONFIG_SPI_FLASH_SPANSION 116 #define CONFIG_SPI_FLASH_SPANSION
109 #define CONFIG_SPI_FLASH_QUAD 117 #define CONFIG_SPI_FLASH_QUAD
110 #define CONFIG_SYS_NO_FLASH 118 #define CONFIG_SYS_NO_FLASH
111 119
112 /* ENV setting */ 120 /* ENV setting */
113 #define CONFIG_ENV_IS_IN_SPI_FLASH 121 #define CONFIG_ENV_IS_IN_SPI_FLASH
114 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 122 #define CONFIG_ENV_SECT_SIZE (256 * 1024)
115 #define CONFIG_ENV_ADDR 0xC0000 123 #define CONFIG_ENV_ADDR 0xC0000
116 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 124 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
117 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 125 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
118 126
119 #define CONFIG_EXTRA_ENV_SETTINGS \ 127 #define CONFIG_EXTRA_ENV_SETTINGS \
120 "bootm_low=0x40e00000\0" \ 128 "bootm_low=0x40e00000\0" \
121 "bootm_size=0x100000\0" \ 129 "bootm_size=0x100000\0" \
122 130
123 /* SH Ether */ 131 /* SH Ether */
124 #define CONFIG_NET_MULTI 132 #define CONFIG_NET_MULTI
125 #define CONFIG_SH_ETHER 133 #define CONFIG_SH_ETHER
126 #define CONFIG_SH_ETHER_USE_PORT 0 134 #define CONFIG_SH_ETHER_USE_PORT 0
127 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 135 #define CONFIG_SH_ETHER_PHY_ADDR 0x1
128 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 136 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
129 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 137 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
130 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 138 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
131 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 139 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
132 #define CONFIG_PHYLIB 140 #define CONFIG_PHYLIB
133 #define CONFIG_PHY_MICREL 141 #define CONFIG_PHY_MICREL
134 #define CONFIG_BITBANGMII 142 #define CONFIG_BITBANGMII
135 #define CONFIG_BITBANGMII_MULTI 143 #define CONFIG_BITBANGMII_MULTI
136 144
137 /* Board Clock */ 145 /* Board Clock */
138 #define RMOBILE_XTAL_CLK 20000000u 146 #define RMOBILE_XTAL_CLK 20000000u
139 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 147 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
140 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 148 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
141 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 149 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
142 #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) 150 #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
143 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ 151 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ
144 152
145 #define CONFIG_SYS_TMU_CLK_DIV 4 153 #define CONFIG_SYS_TMU_CLK_DIV 4
146 154
147 /* i2c */ 155 /* i2c */
148 #define CONFIG_CMD_I2C 156 #define CONFIG_CMD_I2C
149 #define CONFIG_SYS_I2C 157 #define CONFIG_SYS_I2C
150 #define CONFIG_SYS_I2C_SH 158 #define CONFIG_SYS_I2C_SH
151 #define CONFIG_SYS_I2C_SLAVE 0x7F 159 #define CONFIG_SYS_I2C_SLAVE 0x7F
152 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 160 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
153 #define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 161 #define CONFIG_SYS_I2C_SH_BASE0 0xE6500000
154 #define CONFIG_SYS_I2C_SH_SPEED0 400000 162 #define CONFIG_SYS_I2C_SH_SPEED0 400000
155 #define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 163 #define CONFIG_SYS_I2C_SH_BASE1 0xE6510000
156 #define CONFIG_SYS_I2C_SH_SPEED1 400000 164 #define CONFIG_SYS_I2C_SH_SPEED1 400000
157 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 165 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
158 #define CONFIG_SYS_I2C_SH_SPEED2 400000 166 #define CONFIG_SYS_I2C_SH_SPEED2 400000
159 #define CONFIG_SH_I2C_DATA_HIGH 4 167 #define CONFIG_SH_I2C_DATA_HIGH 4
160 #define CONFIG_SH_I2C_DATA_LOW 5 168 #define CONFIG_SH_I2C_DATA_LOW 5
161 #define CONFIG_SH_I2C_CLOCK 10000000 169 #define CONFIG_SH_I2C_CLOCK 10000000
162 170
163 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 171 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
164 172
165 #endif /* __ALT_H */ 173 #endif /* __ALT_H */
166 174