Eric Lee / smarc-uboot | Embedian Git Server

Commit cd8c87756a46ae3544e563793ce8c18efd1091d1

Authored by Joakim Tjernlund 2011-04-25 09:39:43 +0800

Committed by Wolfgang Denk 2011-05-13 05:17:52 +0800

Exists in master and in 54 other branches

Fix a few gcc warnings.

Noticed while building all of mpc8xx. Also
constify usage string in timer.c
Warnings fixed are:
timer.c: In function 'timer':
timer.c:189: warning: format not a string literal and no format arguments
timer.c:258: warning: format not a string literal and no format arguments
atm.c: In function 'atmUnload':
atm.c:99: warning: array subscript is above array bounds
atm.c: In function 'atmLoad':
atm.c:65: warning: array subscript is above array bounds
codec.c: In function 'codsp_write_pop_int':
codec.c:678: warning: array subscript is above array bounds
codec.c: In function 'codsp_write_cop_short':
codec.c:585: warning: array subscript is above array bounds
codec.c: In function 'codsp_write_sop_int':
codec.c:512: warning: array subscript is above array bounds

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>

Showing 3 changed files with 8 additions and 8 deletions Inline Diff

board/netta/codec.c
board/siemens/IAD210/atm.c
examples/standalone/timer.c

board/netta/codec.c

Diff comments View file @ cd8c877

1	/*	1	/*
2	* CODEC	2	* CODEC
3	*/	3	*/
4		4
5	#include <common.h>	5	#include <common.h>
6	#include <post.h>	6	#include <post.h>
7		7
8	#include "mpc8xx.h"	8	#include "mpc8xx.h"
9		9
10	/***********************************************/	10	/***********************************************/
11		11
12	#define MAX_DUSLIC 4	12	#define MAX_DUSLIC 4
13		13
14	#define NUM_CHANNELS 2	14	#define NUM_CHANNELS 2
15	#define MAX_SLICS (MAX_DUSLIC * NUM_CHANNELS)	15	#define MAX_SLICS (MAX_DUSLIC * NUM_CHANNELS)
16		16
17	/***********************************************/	17	/***********************************************/
18		18
19	#define SOP_READ_CH_0 0xC4 /* Read SOP Register for Channel A */	19	#define SOP_READ_CH_0 0xC4 /* Read SOP Register for Channel A */
20	#define SOP_READ_CH_1 0xCC /* Read SOP Register for Channel B */	20	#define SOP_READ_CH_1 0xCC /* Read SOP Register for Channel B */
21	#define SOP_WRITE_CH_0 0x44 /* Write SOP Register for Channel A */	21	#define SOP_WRITE_CH_0 0x44 /* Write SOP Register for Channel A */
22	#define SOP_WRITE_CH_1 0x4C /* Write SOP Register for Channel B */	22	#define SOP_WRITE_CH_1 0x4C /* Write SOP Register for Channel B */
23		23
24	#define COP_READ_CH_0 0xC5	24	#define COP_READ_CH_0 0xC5
25	#define COP_READ_CH_1 0xCD	25	#define COP_READ_CH_1 0xCD
26	#define COP_WRITE_CH_0 0x45	26	#define COP_WRITE_CH_0 0x45
27	#define COP_WRITE_CH_1 0x4D	27	#define COP_WRITE_CH_1 0x4D
28		28
29	#define POP_READ_CH_0 0xC6	29	#define POP_READ_CH_0 0xC6
30	#define POP_READ_CH_1 0xCE	30	#define POP_READ_CH_1 0xCE
31	#define POP_WRITE_CH_0 0x46	31	#define POP_WRITE_CH_0 0x46
32	#define POP_WRITE_CH_1 0x4E	32	#define POP_WRITE_CH_1 0x4E
33		33
34	#define RST_CMD_DUSLIC_CHIP 0x40 /* OR 0x48 */	34	#define RST_CMD_DUSLIC_CHIP 0x40 /* OR 0x48 */
35	#define RST_CMD_DUSLIC_CH_A 0x41	35	#define RST_CMD_DUSLIC_CH_A 0x41
36	#define RST_CMD_DUSLIC_CH_B 0x49	36	#define RST_CMD_DUSLIC_CH_B 0x49
37		37
38	#define PCM_RESYNC_CMD_CH_A 0x42	38	#define PCM_RESYNC_CMD_CH_A 0x42
39	#define PCM_RESYNC_CMD_CH_B 0x4A	39	#define PCM_RESYNC_CMD_CH_B 0x4A
40		40
41	#define ACTIVE_HOOK_LEV_4 0	41	#define ACTIVE_HOOK_LEV_4 0
42	#define ACTIVE_HOOK_LEV_12 1	42	#define ACTIVE_HOOK_LEV_12 1
43		43
44	#define SLIC_P_NORMAL 0x01	44	#define SLIC_P_NORMAL 0x01
45		45
46	/************************************************/	46	/************************************************/
47		47
48	#define CODSP_WR 0x00	48	#define CODSP_WR 0x00
49	#define CODSP_RD 0x80	49	#define CODSP_RD 0x80
50	#define CODSP_OP 0x40	50	#define CODSP_OP 0x40
51	#define CODSP_ADR(x) (((unsigned char)(x) & 7) << 3)	51	#define CODSP_ADR(x) (((unsigned char)(x) & 7) << 3)
52	#define CODSP_M(x) ((unsigned char)(x) & 7)	52	#define CODSP_M(x) ((unsigned char)(x) & 7)
53	#define CODSP_CMD(x) ((unsigned char)(x) & 7)	53	#define CODSP_CMD(x) ((unsigned char)(x) & 7)
54		54
55	/************************************************/	55	/************************************************/
56		56
57	/* command indication ops */	57	/* command indication ops */
58	#define CODSP_M_SLEEP_PWRDN 7	58	#define CODSP_M_SLEEP_PWRDN 7
59	#define CODSP_M_PWRDN_HIZ 0	59	#define CODSP_M_PWRDN_HIZ 0
60	#define CODSP_M_ANY_ACT 2	60	#define CODSP_M_ANY_ACT 2
61	#define CODSP_M_RING 5	61	#define CODSP_M_RING 5
62	#define CODSP_M_ACT_MET 6	62	#define CODSP_M_ACT_MET 6
63	#define CODSP_M_GND_START 4	63	#define CODSP_M_GND_START 4
64	#define CODSP_M_RING_PAUSE 1	64	#define CODSP_M_RING_PAUSE 1
65		65
66	/* single byte commands */	66	/* single byte commands */
67	#define CODSP_CMD_SOFT_RESET CODSP_CMD(0)	67	#define CODSP_CMD_SOFT_RESET CODSP_CMD(0)
68	#define CODSP_CMD_RESET_CH CODSP_CMD(1)	68	#define CODSP_CMD_RESET_CH CODSP_CMD(1)
69	#define CODSP_CMD_RESYNC CODSP_CMD(2)	69	#define CODSP_CMD_RESYNC CODSP_CMD(2)
70		70
71	/* two byte commands */	71	/* two byte commands */
72	#define CODSP_CMD_SOP CODSP_CMD(4)	72	#define CODSP_CMD_SOP CODSP_CMD(4)
73	#define CODSP_CMD_COP CODSP_CMD(5)	73	#define CODSP_CMD_COP CODSP_CMD(5)
74	#define CODSP_CMD_POP CODSP_CMD(6)	74	#define CODSP_CMD_POP CODSP_CMD(6)
75		75
76	/************************************************/	76	/************************************************/
77		77
78	/* read as 4-bytes */	78	/* read as 4-bytes */
79	#define CODSP_INTREG_INT_CH 0x80000000	79	#define CODSP_INTREG_INT_CH 0x80000000
80	#define CODSP_INTREG_HOOK 0x40000000	80	#define CODSP_INTREG_HOOK 0x40000000
81	#define CODSP_INTREG_GNDK 0x20000000	81	#define CODSP_INTREG_GNDK 0x20000000
82	#define CODSP_INTREG_GNDP 0x10000000	82	#define CODSP_INTREG_GNDP 0x10000000
83	#define CODSP_INTREG_ICON 0x08000000	83	#define CODSP_INTREG_ICON 0x08000000
84	#define CODSP_INTREG_VRTLIM 0x04000000	84	#define CODSP_INTREG_VRTLIM 0x04000000
85	#define CODSP_INTREG_OTEMP 0x02000000	85	#define CODSP_INTREG_OTEMP 0x02000000
86	#define CODSP_INTREG_SYNC_FAIL 0x01000000	86	#define CODSP_INTREG_SYNC_FAIL 0x01000000
87	#define CODSP_INTREG_LM_THRES 0x00800000	87	#define CODSP_INTREG_LM_THRES 0x00800000
88	#define CODSP_INTREG_READY 0x00400000	88	#define CODSP_INTREG_READY 0x00400000
89	#define CODSP_INTREG_RSTAT 0x00200000	89	#define CODSP_INTREG_RSTAT 0x00200000
90	#define CODSP_INTREG_LM_OK 0x00100000	90	#define CODSP_INTREG_LM_OK 0x00100000
91	#define CODSP_INTREG_IO4_DU 0x00080000	91	#define CODSP_INTREG_IO4_DU 0x00080000
92	#define CODSP_INTREG_IO3_DU 0x00040000	92	#define CODSP_INTREG_IO3_DU 0x00040000
93	#define CODSP_INTREG_IO2_DU 0x00020000	93	#define CODSP_INTREG_IO2_DU 0x00020000
94	#define CODSP_INTREG_IO1_DU 0x00010000	94	#define CODSP_INTREG_IO1_DU 0x00010000
95	#define CODSP_INTREG_DTMF_OK 0x00008000	95	#define CODSP_INTREG_DTMF_OK 0x00008000
96	#define CODSP_INTREG_DTMF_KEY4 0x00004000	96	#define CODSP_INTREG_DTMF_KEY4 0x00004000
97	#define CODSP_INTREG_DTMF_KEY3 0x00002000	97	#define CODSP_INTREG_DTMF_KEY3 0x00002000
98	#define CODSP_INTREG_DTMF_KEY2 0x00001000	98	#define CODSP_INTREG_DTMF_KEY2 0x00001000
99	#define CODSP_INTREG_DTMF_KEY1 0x00000800	99	#define CODSP_INTREG_DTMF_KEY1 0x00000800
100	#define CODSP_INTREG_DTMF_KEY0 0x00000400	100	#define CODSP_INTREG_DTMF_KEY0 0x00000400
101	#define CODSP_INTREG_UTDR_OK 0x00000200	101	#define CODSP_INTREG_UTDR_OK 0x00000200
102	#define CODSP_INTREG_UTDX_OK 0x00000100	102	#define CODSP_INTREG_UTDX_OK 0x00000100
103	#define CODSP_INTREG_EDSP_FAIL 0x00000080	103	#define CODSP_INTREG_EDSP_FAIL 0x00000080
104	#define CODSP_INTREG_CIS_BOF 0x00000008	104	#define CODSP_INTREG_CIS_BOF 0x00000008
105	#define CODSP_INTREG_CIS_BUF 0x00000004	105	#define CODSP_INTREG_CIS_BUF 0x00000004
106	#define CODSP_INTREG_CIS_REQ 0x00000002	106	#define CODSP_INTREG_CIS_REQ 0x00000002
107	#define CODSP_INTREG_CIS_ACT 0x00000001	107	#define CODSP_INTREG_CIS_ACT 0x00000001
108		108
109	/************************************************/	109	/************************************************/
110		110
111	/* ======== SOP REG ADDRESSES =======*/	111	/* ======== SOP REG ADDRESSES =======*/
112		112
113	#define REVISION_ADDR 0x00	113	#define REVISION_ADDR 0x00
114	#define PCMC1_ADDR 0x05	114	#define PCMC1_ADDR 0x05
115	#define XCR_ADDR 0x06	115	#define XCR_ADDR 0x06
116	#define INTREG1_ADDR 0x07	116	#define INTREG1_ADDR 0x07
117	#define INTREG2_ADDR 0x08	117	#define INTREG2_ADDR 0x08
118	#define INTREG3_ADDR 0x09	118	#define INTREG3_ADDR 0x09
119	#define INTREG4_ADDR 0x0A	119	#define INTREG4_ADDR 0x0A
120	#define LMRES1_ADDR 0x0D	120	#define LMRES1_ADDR 0x0D
121	#define MASK_ADDR 0x11	121	#define MASK_ADDR 0x11
122	#define IOCTL3_ADDR 0x14	122	#define IOCTL3_ADDR 0x14
123	#define BCR1_ADDR 0x15	123	#define BCR1_ADDR 0x15
124	#define BCR2_ADDR 0x16	124	#define BCR2_ADDR 0x16
125	#define BCR3_ADDR 0x17	125	#define BCR3_ADDR 0x17
126	#define BCR4_ADDR 0x18	126	#define BCR4_ADDR 0x18
127	#define BCR5_ADDR 0x19	127	#define BCR5_ADDR 0x19
128	#define DSCR_ADDR 0x1A	128	#define DSCR_ADDR 0x1A
129	#define LMCR1_ADDR 0x1C	129	#define LMCR1_ADDR 0x1C
130	#define LMCR2_ADDR 0x1D	130	#define LMCR2_ADDR 0x1D
131	#define LMCR3_ADDR 0x1E	131	#define LMCR3_ADDR 0x1E
132	#define OFR1_ADDR 0x1F	132	#define OFR1_ADDR 0x1F
133	#define PCMR1_ADDR 0x21	133	#define PCMR1_ADDR 0x21
134	#define PCMX1_ADDR 0x25	134	#define PCMX1_ADDR 0x25
135	#define TSTR3_ADDR 0x2B	135	#define TSTR3_ADDR 0x2B
136	#define TSTR4_ADDR 0x2C	136	#define TSTR4_ADDR 0x2C
137	#define TSTR5_ADDR 0x2D	137	#define TSTR5_ADDR 0x2D
138		138
139	/* ========= POP REG ADDRESSES ========*/	139	/* ========= POP REG ADDRESSES ========*/
140		140
141	#define CIS_DAT_ADDR 0x00	141	#define CIS_DAT_ADDR 0x00
142		142
143	#define LEC_LEN_ADDR 0x3A	143	#define LEC_LEN_ADDR 0x3A
144	#define LEC_POWR_ADDR 0x3B	144	#define LEC_POWR_ADDR 0x3B
145	#define LEC_DELP_ADDR 0x3C	145	#define LEC_DELP_ADDR 0x3C
146	#define LEC_DELQ_ADDR 0x3D	146	#define LEC_DELQ_ADDR 0x3D
147	#define LEC_GAIN_XI_ADDR 0x3E	147	#define LEC_GAIN_XI_ADDR 0x3E
148	#define LEC_GAIN_RI_ADDR 0x3F	148	#define LEC_GAIN_RI_ADDR 0x3F
149	#define LEC_GAIN_XO_ADDR 0x40	149	#define LEC_GAIN_XO_ADDR 0x40
150	#define LEC_RES_1_ADDR 0x41	150	#define LEC_RES_1_ADDR 0x41
151	#define LEC_RES_2_ADDR 0x42	151	#define LEC_RES_2_ADDR 0x42
152		152
153	#define NLP_POW_LPF_ADDR 0x30	153	#define NLP_POW_LPF_ADDR 0x30
154	#define NLP_POW_LPS_ADDR 0x31	154	#define NLP_POW_LPS_ADDR 0x31
155	#define NLP_BN_LEV_X_ADDR 0x32	155	#define NLP_BN_LEV_X_ADDR 0x32
156	#define NLP_BN_LEV_R_ADDR 0x33	156	#define NLP_BN_LEV_R_ADDR 0x33
157	#define NLP_BN_INC_ADDR 0x34	157	#define NLP_BN_INC_ADDR 0x34
158	#define NLP_BN_DEC_ADDR 0x35	158	#define NLP_BN_DEC_ADDR 0x35
159	#define NLP_BN_MAX_ADDR 0x36	159	#define NLP_BN_MAX_ADDR 0x36
160	#define NLP_BN_ADJ_ADDR 0x37	160	#define NLP_BN_ADJ_ADDR 0x37
161	#define NLP_RE_MIN_ERLL_ADDR 0x38	161	#define NLP_RE_MIN_ERLL_ADDR 0x38
162	#define NLP_RE_EST_ERLL_ADDR 0x39	162	#define NLP_RE_EST_ERLL_ADDR 0x39
163	#define NLP_SD_LEV_X_ADDR 0x3A	163	#define NLP_SD_LEV_X_ADDR 0x3A
164	#define NLP_SD_LEV_R_ADDR 0x3B	164	#define NLP_SD_LEV_R_ADDR 0x3B
165	#define NLP_SD_LEV_BN_ADDR 0x3C	165	#define NLP_SD_LEV_BN_ADDR 0x3C
166	#define NLP_SD_LEV_RE_ADDR 0x3D	166	#define NLP_SD_LEV_RE_ADDR 0x3D
167	#define NLP_SD_OT_DT_ADDR 0x3E	167	#define NLP_SD_OT_DT_ADDR 0x3E
168	#define NLP_ERL_LIN_LP_ADDR 0x3F	168	#define NLP_ERL_LIN_LP_ADDR 0x3F
169	#define NLP_ERL_LEC_LP_ADDR 0x40	169	#define NLP_ERL_LEC_LP_ADDR 0x40
170	#define NLP_CT_LEV_RE_ADDR 0x41	170	#define NLP_CT_LEV_RE_ADDR 0x41
171	#define NLP_CTRL_ADDR 0x42	171	#define NLP_CTRL_ADDR 0x42
172		172
173	#define UTD_CF_H_ADDR 0x4B	173	#define UTD_CF_H_ADDR 0x4B
174	#define UTD_CF_L_ADDR 0x4C	174	#define UTD_CF_L_ADDR 0x4C
175	#define UTD_BW_H_ADDR 0x4D	175	#define UTD_BW_H_ADDR 0x4D
176	#define UTD_BW_L_ADDR 0x4E	176	#define UTD_BW_L_ADDR 0x4E
177	#define UTD_NLEV_ADDR 0x4F	177	#define UTD_NLEV_ADDR 0x4F
178	#define UTD_SLEV_H_ADDR 0x50	178	#define UTD_SLEV_H_ADDR 0x50
179	#define UTD_SLEV_L_ADDR 0x51	179	#define UTD_SLEV_L_ADDR 0x51
180	#define UTD_DELT_ADDR 0x52	180	#define UTD_DELT_ADDR 0x52
181	#define UTD_RBRK_ADDR 0x53	181	#define UTD_RBRK_ADDR 0x53
182	#define UTD_RTIME_ADDR 0x54	182	#define UTD_RTIME_ADDR 0x54
183	#define UTD_EBRK_ADDR 0x55	183	#define UTD_EBRK_ADDR 0x55
184	#define UTD_ETIME_ADDR 0x56	184	#define UTD_ETIME_ADDR 0x56
185		185
186	#define DTMF_LEV_ADDR 0x30	186	#define DTMF_LEV_ADDR 0x30
187	#define DTMF_TWI_ADDR 0x31	187	#define DTMF_TWI_ADDR 0x31
188	#define DTMF_NCF_H_ADDR 0x32	188	#define DTMF_NCF_H_ADDR 0x32
189	#define DTMF_NCF_L_ADDR 0x33	189	#define DTMF_NCF_L_ADDR 0x33
190	#define DTMF_NBW_H_ADDR 0x34	190	#define DTMF_NBW_H_ADDR 0x34
191	#define DTMF_NBW_L_ADDR 0x35	191	#define DTMF_NBW_L_ADDR 0x35
192	#define DTMF_GAIN_ADDR 0x36	192	#define DTMF_GAIN_ADDR 0x36
193	#define DTMF_RES1_ADDR 0x37	193	#define DTMF_RES1_ADDR 0x37
194	#define DTMF_RES2_ADDR 0x38	194	#define DTMF_RES2_ADDR 0x38
195	#define DTMF_RES3_ADDR 0x39	195	#define DTMF_RES3_ADDR 0x39
196		196
197	#define CIS_LEV_H_ADDR 0x43	197	#define CIS_LEV_H_ADDR 0x43
198	#define CIS_LEV_L_ADDR 0x44	198	#define CIS_LEV_L_ADDR 0x44
199	#define CIS_BRS_ADDR 0x45	199	#define CIS_BRS_ADDR 0x45
200	#define CIS_SEIZ_H_ADDR 0x46	200	#define CIS_SEIZ_H_ADDR 0x46
201	#define CIS_SEIZ_L_ADDR 0x47	201	#define CIS_SEIZ_L_ADDR 0x47
202	#define CIS_MARK_H_ADDR 0x48	202	#define CIS_MARK_H_ADDR 0x48
203	#define CIS_MARK_L_ADDR 0x49	203	#define CIS_MARK_L_ADDR 0x49
204	#define CIS_LEC_MODE_ADDR 0x4A	204	#define CIS_LEC_MODE_ADDR 0x4A
205		205
206	/=====================================/	206	/=====================================/
207		207
208	#define HOOK_LEV_ACT_START_ADDR 0x89	208	#define HOOK_LEV_ACT_START_ADDR 0x89
209	#define RO1_START_ADDR 0x70	209	#define RO1_START_ADDR 0x70
210	#define RO2_START_ADDR 0x95	210	#define RO2_START_ADDR 0x95
211	#define RO3_START_ADDR 0x96	211	#define RO3_START_ADDR 0x96
212		212
213	#define TG1_FREQ_START_ADDR 0x38	213	#define TG1_FREQ_START_ADDR 0x38
214	#define TG1_GAIN_START_ADDR 0x39	214	#define TG1_GAIN_START_ADDR 0x39
215	#define TG1_BANDPASS_START_ADDR 0x3B	215	#define TG1_BANDPASS_START_ADDR 0x3B
216	#define TG1_BANDPASS_END_ADDR 0x3D	216	#define TG1_BANDPASS_END_ADDR 0x3D
217		217
218	#define TG2_FREQ_START_ADDR 0x40	218	#define TG2_FREQ_START_ADDR 0x40
219	#define TG2_GAIN_START_ADDR 0x41	219	#define TG2_GAIN_START_ADDR 0x41
220	#define TG2_BANDPASS_START_ADDR 0x43	220	#define TG2_BANDPASS_START_ADDR 0x43
221	#define TG2_BANDPASS_END_ADDR 0x45	221	#define TG2_BANDPASS_END_ADDR 0x45
222		222
223	/====================================/	223	/====================================/
224		224
225	#define PCM_HW_B 0x80	225	#define PCM_HW_B 0x80
226	#define PCM_HW_A 0x00	226	#define PCM_HW_A 0x00
227	#define PCM_TIME_SLOT_0 0x00 /* Byte 0 of PCM Frame (by default is assigned to channel A ) */	227	#define PCM_TIME_SLOT_0 0x00 /* Byte 0 of PCM Frame (by default is assigned to channel A ) */
228	#define PCM_TIME_SLOT_1 0x01 /* Byte 1 of PCM Frame (by default is assigned to channel B ) */	228	#define PCM_TIME_SLOT_1 0x01 /* Byte 1 of PCM Frame (by default is assigned to channel B ) */
229	#define PCM_TIME_SLOT_4 0x04 /* Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */	229	#define PCM_TIME_SLOT_4 0x04 /* Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
230		230
231	#define RX_LEV_ADDR 0x28	231	#define RX_LEV_ADDR 0x28
232	#define TX_LEV_ADDR 0x30	232	#define TX_LEV_ADDR 0x30
233	#define Ik1_ADDR 0x83	233	#define Ik1_ADDR 0x83
234		234
235	#define AR_ROW 3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */	235	#define AR_ROW 3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */
236	#define AX_ROW 6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */	236	#define AX_ROW 6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */
237	#define DCF_ROW 0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */	237	#define DCF_ROW 0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
238		238
239	/* Mark the start byte of Duslic parameters that we use with configurator */	239	/* Mark the start byte of Duslic parameters that we use with configurator */
240	#define Ik1_START_BYTE 3	240	#define Ik1_START_BYTE 3
241	#define RX_LEV_START_BYTE 0	241	#define RX_LEV_START_BYTE 0
242	#define TX_LEV_START_BYTE 0	242	#define TX_LEV_START_BYTE 0
243		243
244	/************************************************/	244	/************************************************/
245		245
246	#define INTREG4_CIS_ACT (1 << 0)	246	#define INTREG4_CIS_ACT (1 << 0)
247		247
248	#define BCR1_SLEEP 0x20	248	#define BCR1_SLEEP 0x20
249	#define BCR1_REVPOL 0x10	249	#define BCR1_REVPOL 0x10
250	#define BCR1_ACTR 0x08	250	#define BCR1_ACTR 0x08
251	#define BCR1_ACTL 0x04	251	#define BCR1_ACTL 0x04
252	#define BCR1_SLIC_MASK 0x03	252	#define BCR1_SLIC_MASK 0x03
253		253
254	#define BCR2_HARD_POL_REV 0x40	254	#define BCR2_HARD_POL_REV 0x40
255	#define BCR2_TTX 0x20	255	#define BCR2_TTX 0x20
256	#define BCR2_TTX_12K 0x10	256	#define BCR2_TTX_12K 0x10
257	#define BCR2_HIMAN 0x08	257	#define BCR2_HIMAN 0x08
258	#define BCR2_PDOT 0x01	258	#define BCR2_PDOT 0x01
259		259
260	#define BCR3_PCMX_EN (1 << 4)	260	#define BCR3_PCMX_EN (1 << 4)
261		261
262	#define BCR5_DTMF_EN (1 << 0)	262	#define BCR5_DTMF_EN (1 << 0)
263	#define BCR5_DTMF_SRC (1 << 1)	263	#define BCR5_DTMF_SRC (1 << 1)
264	#define BCR5_LEC_EN (1 << 2)	264	#define BCR5_LEC_EN (1 << 2)
265	#define BCR5_LEC_OUT (1 << 3)	265	#define BCR5_LEC_OUT (1 << 3)
266	#define BCR5_CIS_EN (1 << 4)	266	#define BCR5_CIS_EN (1 << 4)
267	#define BCR5_CIS_AUTO (1 << 5)	267	#define BCR5_CIS_AUTO (1 << 5)
268	#define BCR5_UTDX_EN (1 << 6)	268	#define BCR5_UTDX_EN (1 << 6)
269	#define BCR5_UTDR_EN (1 << 7)	269	#define BCR5_UTDR_EN (1 << 7)
270		270
271	#define DSCR_TG1_EN (1 << 0)	271	#define DSCR_TG1_EN (1 << 0)
272	#define DSCR_TG2_EN (1 << 1)	272	#define DSCR_TG2_EN (1 << 1)
273	#define DSCR_PTG (1 << 2)	273	#define DSCR_PTG (1 << 2)
274	#define DSCR_COR8 (1 << 3)	274	#define DSCR_COR8 (1 << 3)
275	#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4)	275	#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4)
276		276
277	#define CIS_LEC_MODE_CIS_V23 (1 << 0)	277	#define CIS_LEC_MODE_CIS_V23 (1 << 0)
278	#define CIS_LEC_MODE_CIS_FRM (1 << 1)	278	#define CIS_LEC_MODE_CIS_FRM (1 << 1)
279	#define CIS_LEC_MODE_NLP_EN (1 << 2)	279	#define CIS_LEC_MODE_NLP_EN (1 << 2)
280	#define CIS_LEC_MODE_UTDR_SUM (1 << 4)	280	#define CIS_LEC_MODE_UTDR_SUM (1 << 4)
281	#define CIS_LEC_MODE_UTDX_SUM (1 << 5)	281	#define CIS_LEC_MODE_UTDX_SUM (1 << 5)
282	#define CIS_LEC_MODE_LEC_FREEZE (1 << 6)	282	#define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
283	#define CIS_LEC_MODE_LEC_ADAPT (1 << 7)	283	#define CIS_LEC_MODE_LEC_ADAPT (1 << 7)
284		284
285	#define TSTR4_COR_64 (1 << 5)	285	#define TSTR4_COR_64 (1 << 5)
286		286
287	#define TSTR3_AC_DLB_8K (1 << 2)	287	#define TSTR3_AC_DLB_8K (1 << 2)
288	#define TSTR3_AC_DLB_32K (1 << 3)	288	#define TSTR3_AC_DLB_32K (1 << 3)
289	#define TSTR3_AC_DLB_4M (1 << 5)	289	#define TSTR3_AC_DLB_4M (1 << 5)
290		290
291		291
292	#define LMCR1_TEST_EN (1 << 7)	292	#define LMCR1_TEST_EN (1 << 7)
293	#define LMCR1_LM_EN (1 << 6)	293	#define LMCR1_LM_EN (1 << 6)
294	#define LMCR1_LM_THM (1 << 5)	294	#define LMCR1_LM_THM (1 << 5)
295	#define LMCR1_LM_ONCE (1 << 2)	295	#define LMCR1_LM_ONCE (1 << 2)
296	#define LMCR1_LM_MASK (1 << 1)	296	#define LMCR1_LM_MASK (1 << 1)
297		297
298	#define LMCR2_LM_RECT (1 << 5)	298	#define LMCR2_LM_RECT (1 << 5)
299	#define LMCR2_LM_SEL_VDD 0x0D	299	#define LMCR2_LM_SEL_VDD 0x0D
300	#define LMCR2_LM_SEL_IO3 0x0A	300	#define LMCR2_LM_SEL_IO3 0x0A
301	#define LMCR2_LM_SEL_IO4 0x0B	301	#define LMCR2_LM_SEL_IO4 0x0B
302	#define LMCR2_LM_SEL_IO4_MINUS_IO3 0x0F	302	#define LMCR2_LM_SEL_IO4_MINUS_IO3 0x0F
303		303
304	#define LMCR3_RTR_SEL (1 << 6)	304	#define LMCR3_RTR_SEL (1 << 6)
305		305
306	#define LMCR3_RNG_OFFSET_NONE 0x00	306	#define LMCR3_RNG_OFFSET_NONE 0x00
307	#define LMCR3_RNG_OFFSET_1 0x01	307	#define LMCR3_RNG_OFFSET_1 0x01
308	#define LMCR3_RNG_OFFSET_2 0x02	308	#define LMCR3_RNG_OFFSET_2 0x02
309	#define LMCR3_RNG_OFFSET_3 0x03	309	#define LMCR3_RNG_OFFSET_3 0x03
310		310
311	#define TSTR5_DC_HOLD (1 << 3)	311	#define TSTR5_DC_HOLD (1 << 3)
312		312
313	/************************************************/	313	/************************************************/
314		314
315	#define TARGET_ONHOOK_BATH_x100 4600 /* 46.0 Volt */	315	#define TARGET_ONHOOK_BATH_x100 4600 /* 46.0 Volt */
316	#define TARGET_ONHOOK_BATL_x100 2500 /* 25.0 Volt */	316	#define TARGET_ONHOOK_BATL_x100 2500 /* 25.0 Volt */
317	#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */	317	#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */
318	#define DIVIDER_RATIO_ACCURx100 (22 * 100)	318	#define DIVIDER_RATIO_ACCURx100 (22 * 100)
319	#define V_AD_x10000 10834L /* VAD = 1.0834 */	319	#define V_AD_x10000 10834L /* VAD = 1.0834 */
320	#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */	320	#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */
321	#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2100 /	321	#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2100 /
322		322
323	#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/	323	#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/
324	#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */	324	#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */
325	#define K_INTDC_RECT_OFF 2 /* 2^2 */	325	#define K_INTDC_RECT_OFF 2 /* 2^2 */
326	#define RNG_FREQ 25	326	#define RNG_FREQ 25
327	#define SAMPLING_FREQ (2000L)	327	#define SAMPLING_FREQ (2000L)
328	#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */	328	#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
329	#define HOOK_THRESH_RING_START_ADDR 0x8B	329	#define HOOK_THRESH_RING_START_ADDR 0x8B
330	#define RING_PARAMS_START_ADDR 0x70	330	#define RING_PARAMS_START_ADDR 0x70
331		331
332	#define V_OUT_BATH_MAX_DIFFx100 300 /* 3.0 x100 */	332	#define V_OUT_BATH_MAX_DIFFx100 300 /* 3.0 x100 */
333	#define V_OUT_BATL_MAX_DIFFx100 400 /* 4.0 x100 */	333	#define V_OUT_BATL_MAX_DIFFx100 400 /* 4.0 x100 */
334	#define MAX_V_RING_MEANx100 50	334	#define MAX_V_RING_MEANx100 50
335	#define TARGET_V_RING_RMSx100 2720	335	#define TARGET_V_RING_RMSx100 2720
336	#define V_RMS_RING_MAX_DIFFx100 250	336	#define V_RMS_RING_MAX_DIFFx100 250
337		337
338	#define LM_OK_SRC_IRG_2 (1 << 4)	338	#define LM_OK_SRC_IRG_2 (1 << 4)
339		339
340	/************************************************/	340	/************************************************/
341		341
342	#define PORTB (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)	342	#define PORTB (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
343	#define PORTC (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)	343	#define PORTC (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
344	#define PORTD (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)	344	#define PORTD (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
345		345
346	#define _PORTD_SET(mask, state) \	346	#define _PORTD_SET(mask, state) \
347	do { \	347	do { \
348	if (state) \	348	if (state) \
349	PORTD \|= mask; \	349	PORTD \|= mask; \
350	else \	350	else \
351	PORTD &= ~mask; \	351	PORTD &= ~mask; \
352	} while (0)	352	} while (0)
353		353
354	#define _PORTB_SET(mask, state) \	354	#define _PORTB_SET(mask, state) \
355	do { \	355	do { \
356	if (state) \	356	if (state) \
357	PORTB \|= mask; \	357	PORTB \|= mask; \
358	else \	358	else \
359	PORTB &= ~mask; \	359	PORTB &= ~mask; \
360	} while (0)	360	} while (0)
361		361
362	#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)	362	#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)
363	#define _PORTB_GET(mask) (!!(PORTB & mask))	363	#define _PORTB_GET(mask) (!!(PORTB & mask))
364		364
365	#define _PORTC_GET(mask) (!!(PORTC & mask))	365	#define _PORTC_GET(mask) (!!(PORTC & mask))
366		366
367	/* port B */	367	/* port B */
368	#define SPI_RXD (1 << (31 - 28))	368	#define SPI_RXD (1 << (31 - 28))
369	#define SPI_TXD (1 << (31 - 29))	369	#define SPI_TXD (1 << (31 - 29))
370	#define SPI_CLK (1 << (31 - 30))	370	#define SPI_CLK (1 << (31 - 30))
371		371
372	/* port C */	372	/* port C */
373	#define COM_HOOK1 (1 << (15 - 9))	373	#define COM_HOOK1 (1 << (15 - 9))
374	#define COM_HOOK2 (1 << (15 - 10))	374	#define COM_HOOK2 (1 << (15 - 10))
375		375
376	#ifndef CONFIG_NETTA_SWAPHOOK	376	#ifndef CONFIG_NETTA_SWAPHOOK
377		377
378	#define COM_HOOK3 (1 << (15 - 11))	378	#define COM_HOOK3 (1 << (15 - 11))
379	#define COM_HOOK4 (1 << (15 - 12))	379	#define COM_HOOK4 (1 << (15 - 12))
380		380
381	#else	381	#else
382		382
383	#define COM_HOOK3 (1 << (15 - 12))	383	#define COM_HOOK3 (1 << (15 - 12))
384	#define COM_HOOK4 (1 << (15 - 11))	384	#define COM_HOOK4 (1 << (15 - 11))
385		385
386	#endif	386	#endif
387		387
388	/* port D */	388	/* port D */
389	#define SPIENC1 (1 << (15 - 9))	389	#define SPIENC1 (1 << (15 - 9))
390	#define SPIENC2 (1 << (15 - 10))	390	#define SPIENC2 (1 << (15 - 10))
391	#define SPIENC3 (1 << (15 - 11))	391	#define SPIENC3 (1 << (15 - 11))
392	#define SPIENC4 (1 << (15 - 14))	392	#define SPIENC4 (1 << (15 - 14))
393		393
394	#define SPI_DELAY() udelay(1)	394	#define SPI_DELAY() udelay(1)
395		395
396	static inline unsigned int __SPI_Transfer(unsigned int tx)	396	static inline unsigned int __SPI_Transfer(unsigned int tx)
397	{	397	{
398	unsigned int rx;	398	unsigned int rx;
399	int b;	399	int b;
400		400
401	rx = 0; b = 8;	401	rx = 0; b = 8;
402	while (--b >= 0) {	402	while (--b >= 0) {
403	_PORTB_SET(SPI_TXD, tx & 0x80);	403	_PORTB_SET(SPI_TXD, tx & 0x80);
404	tx <<= 1;	404	tx <<= 1;
405	_PORTB_TGL(SPI_CLK);	405	_PORTB_TGL(SPI_CLK);
406	SPI_DELAY();	406	SPI_DELAY();
407	rx <<= 1;	407	rx <<= 1;
408	rx \|= _PORTB_GET(SPI_RXD);	408	rx \|= _PORTB_GET(SPI_RXD);
409	_PORTB_TGL(SPI_CLK);	409	_PORTB_TGL(SPI_CLK);
410	SPI_DELAY();	410	SPI_DELAY();
411	}	411	}
412		412
413	return rx;	413	return rx;
414	}	414	}
415		415
416	static const char codsp_dtmf_map = "D1234567890#ABC";	416	static const char codsp_dtmf_map = "D1234567890#ABC";
417		417
418	static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };	418	static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };
419	static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };	419	static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };
420		420
421	static unsigned int codsp_send(int duslic_id, const unsigned char cmd, int cmdlen, unsigned char res, int reslen)	421	static unsigned int codsp_send(int duslic_id, const unsigned char cmd, int cmdlen, unsigned char res, int reslen)
422	{	422	{
423	unsigned int rx;	423	unsigned int rx;
424	int i;	424	int i;
425		425
426	/* just some sanity checks */	426	/* just some sanity checks */
427	if (cmd == 0 \|\| cmdlen < 0)	427	if (cmd == 0 \|\| cmdlen < 0)
428	return -1;	428	return -1;
429		429
430	_PORTD_SET(spienc_mask_tab[duslic_id], 0);	430	_PORTD_SET(spienc_mask_tab[duslic_id], 0);
431		431
432	/* first 2 bytes are without response */	432	/* first 2 bytes are without response */
433	i = 2;	433	i = 2;
434	while (i-- > 0 && cmdlen-- > 0)	434	while (i-- > 0 && cmdlen-- > 0)
435	__SPI_Transfer(*cmd++);	435	__SPI_Transfer(*cmd++);
436		436
437	while (cmdlen-- > 0) {	437	while (cmdlen-- > 0) {
438	rx = __SPI_Transfer(*cmd++);	438	rx = __SPI_Transfer(*cmd++);
439	if (res != 0 && reslen-- > 0)	439	if (res != 0 && reslen-- > 0)
440	*res++ = (unsigned char)rx;	440	*res++ = (unsigned char)rx;
441	}	441	}
442	if (res != 0) {	442	if (res != 0) {
443	while (reslen-- > 0)	443	while (reslen-- > 0)
444	*res++ = __SPI_Transfer(0xFF);	444	*res++ = __SPI_Transfer(0xFF);
445	}	445	}
446		446
447	_PORTD_SET(spienc_mask_tab[duslic_id], 1);	447	_PORTD_SET(spienc_mask_tab[duslic_id], 1);
448		448
449	return 0;	449	return 0;
450	}	450	}
451		451
452	/****************************************************************************/	452	/****************************************************************************/
453		453
454	void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)	454	void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)
455	{	455	{
456	unsigned char cmd = CODSP_WR \| CODSP_ADR(channel) \| CODSP_M(m);	456	unsigned char cmd = CODSP_WR \| CODSP_ADR(channel) \| CODSP_M(m);
457	codsp_send(duslic_id, &cmd, 1, 0, 0);	457	codsp_send(duslic_id, &cmd, 1, 0, 0);
458	}	458	}
459		459
460	void codsp_reset_chip(int duslic_id)	460	void codsp_reset_chip(int duslic_id)
461	{	461	{
462	static const unsigned char cmd = CODSP_WR \| CODSP_OP \| CODSP_CMD_SOFT_RESET;	462	static const unsigned char cmd = CODSP_WR \| CODSP_OP \| CODSP_CMD_SOFT_RESET;
463	codsp_send(duslic_id, &cmd, 1, 0, 0);	463	codsp_send(duslic_id, &cmd, 1, 0, 0);
464	}	464	}
465		465
466	void codsp_reset_channel(int duslic_id, int channel)	466	void codsp_reset_channel(int duslic_id, int channel)
467	{	467	{
468	unsigned char cmd = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_RESET_CH;	468	unsigned char cmd = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_RESET_CH;
469	codsp_send(duslic_id, &cmd, 1, 0, 0);	469	codsp_send(duslic_id, &cmd, 1, 0, 0);
470	}	470	}
471		471
472	void codsp_resync_channel(int duslic_id, int channel)	472	void codsp_resync_channel(int duslic_id, int channel)
473	{	473	{
474	unsigned char cmd = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_RESYNC;	474	unsigned char cmd = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_RESYNC;
475	codsp_send(duslic_id, &cmd, 1, 0, 0);	475	codsp_send(duslic_id, &cmd, 1, 0, 0);
476	}	476	}
477		477
478	/****************************************************************************/	478	/****************************************************************************/
479		479
480	void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)	480	void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
481	{	481	{
482	unsigned char cmd[3];	482	unsigned char cmd[3];
483		483
484	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;	484	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;
485	cmd[1] = regno;	485	cmd[1] = regno;
486	cmd[2] = val;	486	cmd[2] = val;
487		487
488	codsp_send(duslic_id, cmd, 3, 0, 0);	488	codsp_send(duslic_id, cmd, 3, 0, 0);
489	}	489	}
490		490
491	void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)	491	void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
492	{	492	{
493	unsigned char cmd[4];	493	unsigned char cmd[4];
494		494
495	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;	495	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;
496	cmd[1] = regno;	496	cmd[1] = regno;
497	cmd[2] = (unsigned char)(val >> 8);	497	cmd[2] = (unsigned char)(val >> 8);
498	cmd[3] = (unsigned char)val;	498	cmd[3] = (unsigned char)val;
499		499
500	codsp_send(duslic_id, cmd, 4, 0, 0);	500	codsp_send(duslic_id, cmd, 4, 0, 0);
501	}	501	}
502		502
503	void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)	503	void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
504	{	504	{
505	unsigned char cmd[5];	505	unsigned char cmd[6];
506		506
507	cmd[0] = CODSP_WR \| CODSP_ADR(channel) \| CODSP_CMD_SOP;	507	cmd[0] = CODSP_WR \| CODSP_ADR(channel) \| CODSP_CMD_SOP;
508	cmd[1] = regno;	508	cmd[1] = regno;
509	cmd[2] = (unsigned char)(val >> 24);	509	cmd[2] = (unsigned char)(val >> 24);
510	cmd[3] = (unsigned char)(val >> 16);	510	cmd[3] = (unsigned char)(val >> 16);
511	cmd[4] = (unsigned char)(val >> 8);	511	cmd[4] = (unsigned char)(val >> 8);
512	cmd[5] = (unsigned char)val;	512	cmd[5] = (unsigned char)val;
513		513
514	codsp_send(duslic_id, cmd, 6, 0, 0);	514	codsp_send(duslic_id, cmd, 6, 0, 0);
515	}	515	}
516		516
517	unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno)	517	unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno)
518	{	518	{
519	unsigned char cmd[3];	519	unsigned char cmd[3];
520	unsigned char res[2];	520	unsigned char res[2];
521		521
522	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;	522	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;
523	cmd[1] = regno;	523	cmd[1] = regno;
524		524
525	codsp_send(duslic_id, cmd, 2, res, 2);	525	codsp_send(duslic_id, cmd, 2, res, 2);
526		526
527	return res[1];	527	return res[1];
528	}	528	}
529		529
530	unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno)	530	unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno)
531	{	531	{
532	unsigned char cmd[2];	532	unsigned char cmd[2];
533	unsigned char res[3];	533	unsigned char res[3];
534		534
535	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;	535	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;
536	cmd[1] = regno;	536	cmd[1] = regno;
537		537
538	codsp_send(duslic_id, cmd, 2, res, 3);	538	codsp_send(duslic_id, cmd, 2, res, 3);
539		539
540	return ((unsigned short)res[1] << 8) \| res[2];	540	return ((unsigned short)res[1] << 8) \| res[2];
541	}	541	}
542		542
543	unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno)	543	unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno)
544	{	544	{
545	unsigned char cmd[2];	545	unsigned char cmd[2];
546	unsigned char res[5];	546	unsigned char res[5];
547		547
548	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;	548	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_SOP;
549	cmd[1] = regno;	549	cmd[1] = regno;
550		550
551	codsp_send(duslic_id, cmd, 2, res, 5);	551	codsp_send(duslic_id, cmd, 2, res, 5);
552		552
553	return ((unsigned int)res[1] << 24) \| ((unsigned int)res[2] << 16) \| ((unsigned int)res[3] << 8) \| res[4];	553	return ((unsigned int)res[1] << 24) \| ((unsigned int)res[2] << 16) \| ((unsigned int)res[3] << 8) \| res[4];
554	}	554	}
555		555
556	/****************************************************************************/	556	/****************************************************************************/
557		557
558	void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block)	558	void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block)
559	{	559	{
560	unsigned char cmd[10];	560	unsigned char cmd[10];
561		561
562	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;	562	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;
563	cmd[1] = addr;	563	cmd[1] = addr;
564	memcpy(cmd + 2, block, 8);	564	memcpy(cmd + 2, block, 8);
565	codsp_send(duslic_id, cmd, 10, 0, 0);	565	codsp_send(duslic_id, cmd, 10, 0, 0);
566	}	566	}
567		567
568	void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val)	568	void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val)
569	{	569	{
570	unsigned char cmd[3];	570	unsigned char cmd[3];
571		571
572	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;	572	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;
573	cmd[1] = addr;	573	cmd[1] = addr;
574	cmd[2] = val;	574	cmd[2] = val;
575	codsp_send(duslic_id, cmd, 3, 0, 0);	575	codsp_send(duslic_id, cmd, 3, 0, 0);
576	}	576	}
577		577
578	void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val)	578	void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val)
579	{	579	{
580	unsigned char cmd[3];	580	unsigned char cmd[4];
581		581
582	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;	582	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;
583	cmd[1] = addr;	583	cmd[1] = addr;
584	cmd[2] = (unsigned char)(val >> 8);	584	cmd[2] = (unsigned char)(val >> 8);
585	cmd[3] = (unsigned char)val;	585	cmd[3] = (unsigned char)val;
586		586
587	codsp_send(duslic_id, cmd, 4, 0, 0);	587	codsp_send(duslic_id, cmd, 4, 0, 0);
588	}	588	}
589		589
590	void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block)	590	void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block)
591	{	591	{
592	unsigned char cmd[2];	592	unsigned char cmd[2];
593	unsigned char res[9];	593	unsigned char res[9];
594		594
595	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;	595	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;
596	cmd[1] = addr;	596	cmd[1] = addr;
597	codsp_send(duslic_id, cmd, 2, res, 9);	597	codsp_send(duslic_id, cmd, 2, res, 9);
598	memcpy(block, res + 1, 8);	598	memcpy(block, res + 1, 8);
599	}	599	}
600		600
601	unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr)	601	unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr)
602	{	602	{
603	unsigned char cmd[2];	603	unsigned char cmd[2];
604	unsigned char res[2];	604	unsigned char res[2];
605		605
606	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;	606	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;
607	cmd[1] = addr;	607	cmd[1] = addr;
608	codsp_send(duslic_id, cmd, 2, res, 2);	608	codsp_send(duslic_id, cmd, 2, res, 2);
609	return res[1];	609	return res[1];
610	}	610	}
611		611
612	unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr)	612	unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr)
613	{	613	{
614	unsigned char cmd[2];	614	unsigned char cmd[2];
615	unsigned char res[3];	615	unsigned char res[3];
616		616
617	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;	617	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR(channel) \| CODSP_CMD_COP;
618	cmd[1] = addr;	618	cmd[1] = addr;
619		619
620	codsp_send(duslic_id, cmd, 2, res, 3);	620	codsp_send(duslic_id, cmd, 2, res, 3);
621		621
622	return ((unsigned short)res[1] << 8) \| res[2];	622	return ((unsigned short)res[1] << 8) \| res[2];
623	}	623	}
624		624
625	/****************************************************************************/	625	/****************************************************************************/
626		626
627	#define MAX_POP_BLOCK 50	627	#define MAX_POP_BLOCK 50
628		628
629	void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr,	629	void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr,
630	const unsigned char *block, int len)	630	const unsigned char *block, int len)
631	{	631	{
632	unsigned char cmd[2 + MAX_POP_BLOCK];	632	unsigned char cmd[2 + MAX_POP_BLOCK];
633		633
634	if (len > MAX_POP_BLOCK) /* truncate */	634	if (len > MAX_POP_BLOCK) /* truncate */
635	len = MAX_POP_BLOCK;	635	len = MAX_POP_BLOCK;
636		636
637	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;	637	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;
638	cmd[1] = addr;	638	cmd[1] = addr;
639	memcpy (cmd + 2, block, len);	639	memcpy (cmd + 2, block, len);
640	codsp_send (duslic_id, cmd, 2 + len, 0, 0);	640	codsp_send (duslic_id, cmd, 2 + len, 0, 0);
641	}	641	}
642		642
643	void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno,	643	void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno,
644	unsigned char val)	644	unsigned char val)
645	{	645	{
646	unsigned char cmd[3];	646	unsigned char cmd[3];
647		647
648	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;	648	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;
649	cmd[1] = regno;	649	cmd[1] = regno;
650	cmd[2] = val;	650	cmd[2] = val;
651		651
652	codsp_send (duslic_id, cmd, 3, 0, 0);	652	codsp_send (duslic_id, cmd, 3, 0, 0);
653	}	653	}
654		654
655	void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno,	655	void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno,
656	unsigned short val)	656	unsigned short val)
657	{	657	{
658	unsigned char cmd[4];	658	unsigned char cmd[4];
659		659
660	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;	660	cmd[0] = CODSP_WR \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;
661	cmd[1] = regno;	661	cmd[1] = regno;
662	cmd[2] = (unsigned char) (val >> 8);	662	cmd[2] = (unsigned char) (val >> 8);
663	cmd[3] = (unsigned char) val;	663	cmd[3] = (unsigned char) val;
664		664
665	codsp_send (duslic_id, cmd, 4, 0, 0);	665	codsp_send (duslic_id, cmd, 4, 0, 0);
666	}	666	}
667		667
668	void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno,	668	void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno,
669	unsigned int val)	669	unsigned int val)
670	{	670	{
671	unsigned char cmd[5];	671	unsigned char cmd[6];
672		672
673	cmd[0] = CODSP_WR \| CODSP_ADR (channel) \| CODSP_CMD_POP;	673	cmd[0] = CODSP_WR \| CODSP_ADR (channel) \| CODSP_CMD_POP;
674	cmd[1] = regno;	674	cmd[1] = regno;
675	cmd[2] = (unsigned char) (val >> 24);	675	cmd[2] = (unsigned char) (val >> 24);
676	cmd[3] = (unsigned char) (val >> 16);	676	cmd[3] = (unsigned char) (val >> 16);
677	cmd[4] = (unsigned char) (val >> 8);	677	cmd[4] = (unsigned char) (val >> 8);
678	cmd[5] = (unsigned char) val;	678	cmd[5] = (unsigned char) val;
679		679
680	codsp_send (duslic_id, cmd, 6, 0, 0);	680	codsp_send (duslic_id, cmd, 6, 0, 0);
681	}	681	}
682		682
683	unsigned char codsp_read_pop_char (int duslic_id, int channel,	683	unsigned char codsp_read_pop_char (int duslic_id, int channel,
684	unsigned char regno)	684	unsigned char regno)
685	{	685	{
686	unsigned char cmd[3];	686	unsigned char cmd[3];
687	unsigned char res[2];	687	unsigned char res[2];
688		688
689	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;	689	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;
690	cmd[1] = regno;	690	cmd[1] = regno;
691		691
692	codsp_send (duslic_id, cmd, 2, res, 2);	692	codsp_send (duslic_id, cmd, 2, res, 2);
693		693
694	return res[1];	694	return res[1];
695	}	695	}
696		696
697	unsigned short codsp_read_pop_short (int duslic_id, int channel,	697	unsigned short codsp_read_pop_short (int duslic_id, int channel,
698	unsigned char regno)	698	unsigned char regno)
699	{	699	{
700	unsigned char cmd[2];	700	unsigned char cmd[2];
701	unsigned char res[3];	701	unsigned char res[3];
702		702
703	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;	703	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;
704	cmd[1] = regno;	704	cmd[1] = regno;
705		705
706	codsp_send (duslic_id, cmd, 2, res, 3);	706	codsp_send (duslic_id, cmd, 2, res, 3);
707		707
708	return ((unsigned short) res[1] << 8) \| res[2];	708	return ((unsigned short) res[1] << 8) \| res[2];
709	}	709	}
710		710
711	unsigned int codsp_read_pop_int (int duslic_id, int channel,	711	unsigned int codsp_read_pop_int (int duslic_id, int channel,
712	unsigned char regno)	712	unsigned char regno)
713	{	713	{
714	unsigned char cmd[2];	714	unsigned char cmd[2];
715	unsigned char res[5];	715	unsigned char res[5];
716		716
717	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;	717	cmd[0] = CODSP_RD \| CODSP_OP \| CODSP_ADR (channel) \| CODSP_CMD_POP;
718	cmd[1] = regno;	718	cmd[1] = regno;
719		719
720	codsp_send (duslic_id, cmd, 2, res, 5);	720	codsp_send (duslic_id, cmd, 2, res, 5);
721		721
722	return (((unsigned int) res[1] << 24) \|	722	return (((unsigned int) res[1] << 24) \|
723	((unsigned int) res[2] << 16) \|	723	((unsigned int) res[2] << 16) \|
724	((unsigned int) res[3] << 8) \|	724	((unsigned int) res[3] << 8) \|
725	res[4] );	725	res[4] );
726	}	726	}
727	/****************************************************************************/	727	/****************************************************************************/
728		728
729	struct _coeffs {	729	struct _coeffs {
730	unsigned char addr;	730	unsigned char addr;
731	unsigned char values[8];	731	unsigned char values[8];
732	};	732	};
733		733
734	struct _coeffs ac_coeffs[11] = {	734	struct _coeffs ac_coeffs[11] = {
735	{ 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */	735	{ 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
736	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */	736	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
737	{ 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */	737	{ 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */
738	{ 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */	738	{ 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */
739	{ 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */	739	{ 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */
740	{ 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */	740	{ 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */
741	{ 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */	741	{ 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */
742	{ 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */	742	{ 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */
743	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */	743	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
744	{ 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */	744	{ 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
745	{ 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */	745	{ 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */
746	};	746	};
747		747
748	struct _coeffs ac_coeffs_0dB[11] = {	748	struct _coeffs ac_coeffs_0dB[11] = {
749	{ 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} },	749	{ 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} },
750	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} },	750	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} },
751	{ 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} },	751	{ 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} },
752	{ 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} },	752	{ 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} },
753	{ 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} },	753	{ 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} },
754	{ 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} },	754	{ 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} },
755	{ 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} },	755	{ 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} },
756	{ 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} },	756	{ 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} },
757	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} },	757	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} },
758	{ 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} },	758	{ 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} },
759	{ 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} }	759	{ 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} }
760	};	760	};
761		761
762	struct _coeffs dc_coeffs[9] = {	762	struct _coeffs dc_coeffs[9] = {
763	{ 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */	763	{ 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */
764	{ 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */	764	{ 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */
765	{ 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */	765	{ 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */
766	{ 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */	766	{ 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */
767	{ 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */	767	{ 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */
768	{ 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */	768	{ 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */
769	{ 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */	769	{ 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */
770	{ 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */	770	{ 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */
771	{ 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */	771	{ 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */
772	};	772	};
773		773
774	void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)	774	void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)
775	{	775	{
776	int i;	776	int i;
777		777
778	for (i = 0; i < tab_size; i++)	778	for (i = 0; i < tab_size; i++)
779	codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);	779	codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
780	}	780	}
781		781
782	#define SS_OPEN_CIRCUIT 0	782	#define SS_OPEN_CIRCUIT 0
783	#define SS_RING_PAUSE 1	783	#define SS_RING_PAUSE 1
784	#define SS_ACTIVE 2	784	#define SS_ACTIVE 2
785	#define SS_ACTIVE_HIGH 3	785	#define SS_ACTIVE_HIGH 3
786	#define SS_ACTIVE_RING 4	786	#define SS_ACTIVE_RING 4
787	#define SS_RINGING 5	787	#define SS_RINGING 5
788	#define SS_ACTIVE_WITH_METERING 6	788	#define SS_ACTIVE_WITH_METERING 6
789	#define SS_ONHOOKTRNSM 7	789	#define SS_ONHOOKTRNSM 7
790	#define SS_STANDBY 8	790	#define SS_STANDBY 8
791	#define SS_MAX 8	791	#define SS_MAX 8
792		792
793	static void codsp_set_slic(int duslic_id, int channel, int state)	793	static void codsp_set_slic(int duslic_id, int channel, int state)
794	{	794	{
795	unsigned char v;	795	unsigned char v;
796		796
797	v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR);	797	v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR);
798		798
799	switch (state) {	799	switch (state) {
800		800
801	case SS_ACTIVE:	801	case SS_ACTIVE:
802	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) \| BCR1_ACTL);	802	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) \| BCR1_ACTL);
803	codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);	803	codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
804	break;	804	break;
805		805
806	case SS_ACTIVE_HIGH:	806	case SS_ACTIVE_HIGH:
807	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR \| BCR1_ACTL));	807	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR \| BCR1_ACTL));
808	codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);	808	codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
809	break;	809	break;
810		810
811	case SS_ACTIVE_RING:	811	case SS_ACTIVE_RING:
812	case SS_ONHOOKTRNSM:	812	case SS_ONHOOKTRNSM:
813	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) \| BCR1_ACTR);	813	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) \| BCR1_ACTR);
814	codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);	814	codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
815	break;	815	break;
816		816
817	case SS_STANDBY:	817	case SS_STANDBY:
818	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL \| BCR1_ACTR));	818	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL \| BCR1_ACTR));
819	codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN);	819	codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN);
820	break;	820	break;
821		821
822	case SS_OPEN_CIRCUIT:	822	case SS_OPEN_CIRCUIT:
823	codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ);	823	codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ);
824	break;	824	break;
825		825
826	case SS_RINGING:	826	case SS_RINGING:
827	codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING);	827	codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING);
828	break;	828	break;
829		829
830	case SS_RING_PAUSE:	830	case SS_RING_PAUSE:
831	codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE);	831	codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE);
832	break;	832	break;
833	}	833	}
834	}	834	}
835		835
836	const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 };	836	const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 };
837	const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 };	837	const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 };
838		838
839	void retrieve_slic_state(int slic_id)	839	void retrieve_slic_state(int slic_id)
840	{	840	{
841	int duslic_id = slic_id >> 1;	841	int duslic_id = slic_id >> 1;
842	int channel = slic_id & 1;	842	int channel = slic_id & 1;
843		843
844	/* Retrieve the state of the SLICs */	844	/* Retrieve the state of the SLICs */
845	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);	845	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
846		846
847	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */	847	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
848	udelay(10000);	848	udelay(10000);
849		849
850	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK);	850	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK);
851	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);	851	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
852	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);	852	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);
853		853
854	/* Program Default Hook Ring thresholds */	854	/* Program Default Hook Ring thresholds */
855	codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values);	855	codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values);
856		856
857	/* Now program Hook Threshold while Ring and ac RingTrip to max values */	857	/* Now program Hook Threshold while Ring and ac RingTrip to max values */
858	codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values);	858	codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values);
859		859
860	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);	860	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
861		861
862	udelay(40000);	862	udelay(40000);
863	}	863	}
864		864
865	int wait_level_metering_finish(int duslic_id, int channel)	865	int wait_level_metering_finish(int duslic_id, int channel)
866	{	866	{
867	int cnt;	867	int cnt;
868		868
869	for (cnt = 0; cnt < 1000 &&	869	for (cnt = 0; cnt < 1000 &&
870	(codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { }	870	(codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { }
871		871
872	return cnt != 1000;	872	return cnt != 1000;
873	}	873	}
874		874
875	int measure_on_hook_voltages(int slic_id, long *vdd,	875	int measure_on_hook_voltages(int slic_id, long *vdd,
876	long v_oh_H, long v_oh_L, long ring_mean_v, long ring_rms_v)	876	long v_oh_H, long v_oh_L, long ring_mean_v, long ring_rms_v)
877	{	877	{
878	short LM_Result, Offset_Compensation; /* Signed 16 bit */	878	short LM_Result, Offset_Compensation; /* Signed 16 bit */
879	long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;	879	long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
880	unsigned char err_mask = 0;	880	unsigned char err_mask = 0;
881	int duslic_id = slic_id >> 1;	881	int duslic_id = slic_id >> 1;
882	int channel = slic_id & 1;	882	int channel = slic_id & 1;
883	int i;	883	int i;
884		884
885	/* measure VDD */	885	/* measure VDD */
886	/* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */	886	/* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */
887	codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD);	887	codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD);
888		888
889	/* Activate Test Mode ==> To Enable DC Hold !!! */	889	/* Activate Test Mode ==> To Enable DC Hold !!! */
890	/* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */	890	/* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */
891	/* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/	891	/* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/
892	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN \| LMCR1_LM_THM \| LMCR1_LM_MASK);	892	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN \| LMCR1_LM_THM \| LMCR1_LM_MASK);
893		893
894	udelay(40000);	894	udelay(40000);
895		895
896	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */	896	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
897	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD);	897	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD);
898		898
899	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */	899	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
900	udelay(10000);	900	udelay(10000);
901		901
902	/* Now Read the LM Result Registers */	902	/* Now Read the LM Result Registers */
903	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);	903	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
904	VDD = (-1)((((long int)LM_Result) 390L ) >> 15) ; /* VDDx100 */	904	VDD = (-1)((((long int)LM_Result) 390L ) >> 15) ; /* VDDx100 */
905		905
906	*vdd = VDD;	906	*vdd = VDD;
907		907
908	VDD_diff = VDD - TARGET_VDDx100;	908	VDD_diff = VDD - TARGET_VDDx100;
909		909
910	if (VDD_diff < 0)	910	if (VDD_diff < 0)
911	VDD_diff = -VDD_diff;	911	VDD_diff = -VDD_diff;
912		912
913	if (VDD_diff > VDD_MAX_DIFFx100)	913	if (VDD_diff > VDD_MAX_DIFFx100)
914	err_mask \|= 1;	914	err_mask \|= 1;
915		915
916	Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100;	916	Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100;
917		917
918	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);	918	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
919	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK);	919	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK);
920		920
921	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */	921	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */
922		922
923	udelay(40000);	923	udelay(40000);
924		924
925	codsp_write_sop_char(duslic_id, channel,	925	codsp_write_sop_char(duslic_id, channel,
926	LMCR1_ADDR, LMCR1_TEST_EN \| LMCR1_LM_THM \| LMCR1_LM_MASK);	926	LMCR1_ADDR, LMCR1_TEST_EN \| LMCR1_LM_THM \| LMCR1_LM_MASK);
927		927
928	udelay(40000);	928	udelay(40000);
929		929
930	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */	930	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
931	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);	931	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
932		932
933	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */	933	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
934	udelay(10000);	934	udelay(10000);
935		935
936	/* Now Read the LM Result Registers */	936	/* Now Read the LM Result Registers */
937	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);	937	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
938	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/	938	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/
939		939
940	V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */	940	V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
941		941
942	*v_oh_H = V_out;	942	*v_oh_H = V_out;
943		943
944	Vout_diff = V_out - TARGET_ONHOOK_BATH_x100;	944	Vout_diff = V_out - TARGET_ONHOOK_BATH_x100;
945		945
946	if (Vout_diff < 0)	946	if (Vout_diff < 0)
947	Vout_diff = -Vout_diff;	947	Vout_diff = -Vout_diff;
948		948
949	if (Vout_diff > V_OUT_BATH_MAX_DIFFx100)	949	if (Vout_diff > V_OUT_BATH_MAX_DIFFx100)
950	err_mask \|= 2;	950	err_mask \|= 2;
951		951
952	codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */	952	codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */
953		953
954	udelay(40000);	954	udelay(40000);
955		955
956	/* Now Read the LM Result Registers */	956	/* Now Read the LM Result Registers */
957	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);	957	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
958		958
959	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/	959	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/
960		960
961	V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */	961	V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
962		962
963	*v_oh_L = V_out;	963	*v_oh_L = V_out;
964		964
965	Vout_diff = V_out - TARGET_ONHOOK_BATL_x100;	965	Vout_diff = V_out - TARGET_ONHOOK_BATL_x100;
966		966
967	if (Vout_diff < 0)	967	if (Vout_diff < 0)
968	Vout_diff = -Vout_diff;	968	Vout_diff = -Vout_diff;
969		969
970	if (Vout_diff > V_OUT_BATL_MAX_DIFFx100)	970	if (Vout_diff > V_OUT_BATL_MAX_DIFFx100)
971	err_mask \|= 4;	971	err_mask \|= 4;
972		972
973	/* perform ring tests */	973	/* perform ring tests */
974		974
975	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);	975	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
976	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK);	976	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK);
977		977
978	udelay(40000);	978	udelay(40000);
979		979
980	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL \| LMCR3_RNG_OFFSET_NONE);	980	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL \| LMCR3_RNG_OFFSET_NONE);
981		981
982	/* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/	982	/* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/
983	codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz);	983	codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz);
984		984
985	/* By Default RO1 is selected when ringing RNG-OFFSET = 00 */	985	/* By Default RO1 is selected when ringing RNG-OFFSET = 00 */
986		986
987	/* Now program Hook Threshold while Ring and ac RingTrip to max values */	987	/* Now program Hook Threshold while Ring and ac RingTrip to max values */
988	for(i = 0; i < sizeof(Max_HookRingTh); i++)	988	for(i = 0; i < sizeof(Max_HookRingTh); i++)
989	codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]);	989	codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]);
990		990
991	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);	991	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
992		992
993	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */	993	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
994		994
995	/* select source for the levelmeter to be IO4-IO3 */	995	/* select source for the levelmeter to be IO4-IO3 */
996	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);	996	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
997		997
998	udelay(40000);	998	udelay(40000);
999		999
1000	/* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */	1000	/* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */
1001	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF);	1001	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF);
1002		1002
1003	udelay(10000);	1003	udelay(10000);
1004		1004
1005	/* Enable LevelMeter to Integrate only once (Rectifier Disabled) */	1005	/* Enable LevelMeter to Integrate only once (Rectifier Disabled) */
1006	codsp_write_sop_char(duslic_id, channel,	1006	codsp_write_sop_char(duslic_id, channel,
1007	LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_EN \| LMCR1_LM_ONCE);	1007	LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_EN \| LMCR1_LM_ONCE);
1008		1008
1009	udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */	1009	udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
1010		1010
1011	if (wait_level_metering_finish(duslic_id, channel)) {	1011	if (wait_level_metering_finish(duslic_id, channel)) {
1012		1012
1013	udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */	1013	udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */
1014		1014
1015	/* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */	1015	/* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */
1016	Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);	1016	Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
1017	Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES);	1017	Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES);
1018		1018
1019	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */	1019	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
1020	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_ONCE);	1020	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_ONCE);
1021		1021
1022	/* Now programm Integrator Offset Registers !!! */	1022	/* Now programm Integrator Offset Registers !!! */
1023	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);	1023	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
1024		1024
1025	codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */	1025	codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */
1026		1026
1027	udelay(40000);	1027	udelay(40000);
1028		1028
1029	/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */	1029	/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
1030	codsp_write_sop_char(duslic_id, channel,	1030	codsp_write_sop_char(duslic_id, channel,
1031	LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_EN \| LMCR1_LM_ONCE);	1031	LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_EN \| LMCR1_LM_ONCE);
1032		1032
1033	udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */	1033	udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
1034		1034
1035	/* Poll the LM_OK bit to see when Integration Result is Ready */	1035	/* Poll the LM_OK bit to see when Integration Result is Ready */
1036	if (wait_level_metering_finish(duslic_id, channel)) {	1036	if (wait_level_metering_finish(duslic_id, channel)) {
1037		1037
1038	udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */	1038	udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */
1039		1039
1040	/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */	1040	/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
1041	/* ==>After that Result Regs will be updated every 500us !!!) */	1041	/* ==>After that Result Regs will be updated every 500us !!!) */
1042	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);	1042	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
1043	V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ; /* Vin x 10000*/	1043	V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ; /* Vin x 10000*/
1044		1044
1045	V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */	1045	V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
1046		1046
1047	if (V_out < 0)	1047	if (V_out < 0)
1048	V_out= -V_out;	1048	V_out= -V_out;
1049		1049
1050	if (V_out > MAX_V_RING_MEANx100)	1050	if (V_out > MAX_V_RING_MEANx100)
1051	err_mask \|= 8;	1051	err_mask \|= 8;
1052		1052
1053	*ring_mean_v = V_out;	1053	*ring_mean_v = V_out;
1054	} else {	1054	} else {
1055	err_mask \|= 8;	1055	err_mask \|= 8;
1056	*ring_mean_v = 0;	1056	*ring_mean_v = 0;
1057	}	1057	}
1058	} else {	1058	} else {
1059	err_mask \|= 8;	1059	err_mask \|= 8;
1060	*ring_mean_v = 0;	1060	*ring_mean_v = 0;
1061	}	1061	}
1062		1062
1063	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */	1063	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
1064	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,	1064	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
1065	LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_ONCE);	1065	LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_ONCE);
1066	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);	1066	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
1067		1067
1068	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */	1068	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
1069		1069
1070	/* Now Enable Rectifier */	1070	/* Now Enable Rectifier */
1071	/* select source for the levelmeter to be IO4-IO3 */	1071	/* select source for the levelmeter to be IO4-IO3 */
1072	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR,	1072	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR,
1073	LMCR2_LM_SEL_IO4_MINUS_IO3 \| LMCR2_LM_RECT);	1073	LMCR2_LM_SEL_IO4_MINUS_IO3 \| LMCR2_LM_RECT);
1074		1074
1075	/* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */	1075	/* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */
1076	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON);	1076	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON);
1077		1077
1078	udelay(40000);	1078	udelay(40000);
1079		1079
1080	/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */	1080	/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
1081	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,	1081	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
1082	LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_EN \| LMCR1_LM_ONCE);	1082	LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_EN \| LMCR1_LM_ONCE);
1083		1083
1084	udelay(40000);	1084	udelay(40000);
1085		1085
1086	/* Poll the LM_OK bit to see when Integration Result is Ready */	1086	/* Poll the LM_OK bit to see when Integration Result is Ready */
1087	if (wait_level_metering_finish(duslic_id, channel)) {	1087	if (wait_level_metering_finish(duslic_id, channel)) {
1088		1088
1089	udelay(10000);	1089	udelay(10000);
1090		1090
1091	/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */	1091	/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
1092	/* ==>After that Result Regs will be updated every 500us !!!) */	1092	/* ==>After that Result Regs will be updated every 500us !!!) */
1093	Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);	1093	Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
1094	Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);	1094	Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);
1095		1095
1096	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */	1096	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
1097	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_ONCE);	1097	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_ONCE);
1098		1098
1099	/* Now programm Integrator Offset Registers !!! */	1099	/* Now programm Integrator Offset Registers !!! */
1100	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);	1100	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
1101		1101
1102	/* Be sure that a Ring is generated !!!! */	1102	/* Be sure that a Ring is generated !!!! */
1103	codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */	1103	codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */
1104		1104
1105	udelay(40000);	1105	udelay(40000);
1106		1106
1107	/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */	1107	/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
1108	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,	1108	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
1109	LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_EN \| LMCR1_LM_ONCE);	1109	LMCR1_LM_THM \| LMCR1_LM_MASK \| LMCR1_LM_EN \| LMCR1_LM_ONCE);
1110		1110
1111	udelay(40000);	1111	udelay(40000);
1112		1112
1113	/* Poll the LM_OK bit to see when Integration Result is Ready */	1113	/* Poll the LM_OK bit to see when Integration Result is Ready */
1114	if (wait_level_metering_finish(duslic_id, channel)) {	1114	if (wait_level_metering_finish(duslic_id, channel)) {
1115		1115
1116	udelay(10000);	1116	udelay(10000);
1117		1117
1118	/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */	1118	/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
1119	/* ==>After that Result Regs will be updated every 500us !!!) */	1119	/* ==>After that Result Regs will be updated every 500us !!!) */
1120	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);	1120	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
1121	V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ; /* Vin x 10000*/	1121	V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ; /* Vin x 10000*/
1122		1122
1123	V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ; /* Vout_RMS x100 */	1123	V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ; /* Vout_RMS x100 */
1124	if (V_out < 0)	1124	if (V_out < 0)
1125	V_out = -V_out;	1125	V_out = -V_out;
1126		1126
1127	Vout_diff = (V_out - TARGET_V_RING_RMSx100);	1127	Vout_diff = (V_out - TARGET_V_RING_RMSx100);
1128		1128
1129	if (Vout_diff < 0)	1129	if (Vout_diff < 0)
1130	Vout_diff = -Vout_diff;	1130	Vout_diff = -Vout_diff;
1131		1131
1132	if (Vout_diff > V_RMS_RING_MAX_DIFFx100)	1132	if (Vout_diff > V_RMS_RING_MAX_DIFFx100)
1133	err_mask \|= 16;	1133	err_mask \|= 16;
1134		1134
1135	*ring_rms_v = V_out;	1135	*ring_rms_v = V_out;
1136	} else {	1136	} else {
1137	err_mask \|= 16;	1137	err_mask \|= 16;
1138	*ring_rms_v = 0;	1138	*ring_rms_v = 0;
1139	}	1139	}
1140	} else {	1140	} else {
1141	err_mask \|= 16;	1141	err_mask \|= 16;
1142	*ring_rms_v = 0;	1142	*ring_rms_v = 0;
1143	}	1143	}
1144	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */	1144	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
1145	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK);	1145	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM \| LMCR1_LM_MASK);
1146		1146
1147	retrieve_slic_state(slic_id);	1147	retrieve_slic_state(slic_id);
1148		1148
1149	return(err_mask);	1149	return(err_mask);
1150	}	1150	}
1151		1151
1152	int test_dtmf(int slic_id)	1152	int test_dtmf(int slic_id)
1153	{	1153	{
1154	unsigned char code;	1154	unsigned char code;
1155	unsigned char b;	1155	unsigned char b;
1156	unsigned int intreg;	1156	unsigned int intreg;
1157	int duslic_id = slic_id >> 1;	1157	int duslic_id = slic_id >> 1;
1158	int channel = slic_id & 1;	1158	int channel = slic_id & 1;
1159		1159
1160	for (code = 0; code < 16; code++) {	1160	for (code = 0; code < 16; code++) {
1161	b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);	1161	b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
1162	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,	1162	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
1163	(b & ~(DSCR_PTG \| DSCR_DG_KEY(15))) \| DSCR_DG_KEY(code) \| DSCR_TG1_EN \| DSCR_TG2_EN);	1163	(b & ~(DSCR_PTG \| DSCR_DG_KEY(15))) \| DSCR_DG_KEY(code) \| DSCR_TG1_EN \| DSCR_TG2_EN);
1164	udelay(80000);	1164	udelay(80000);
1165		1165
1166	intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);	1166	intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);
1167	if ((intreg & CODSP_INTREG_INT_CH) == 0)	1167	if ((intreg & CODSP_INTREG_INT_CH) == 0)
1168	break;	1168	break;
1169		1169
1170	if ((intreg & CODSP_INTREG_DTMF_OK) == 0 \|\|	1170	if ((intreg & CODSP_INTREG_DTMF_OK) == 0 \|\|
1171	codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])	1171	codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])
1172	break;	1172	break;
1173		1173
1174	b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);	1174	b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
1175	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,	1175	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
1176	b & ~(DSCR_COR8 \| DSCR_TG1_EN \| DSCR_TG2_EN));	1176	b & ~(DSCR_COR8 \| DSCR_TG1_EN \| DSCR_TG2_EN));
1177		1177
1178	udelay(80000);	1178	udelay(80000);
1179		1179
1180	intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */	1180	intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */
1181	}	1181	}
1182		1182
1183	if (code != 16) {	1183	if (code != 16) {
1184	b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */	1184	b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
1185	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,	1185	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
1186	b & ~(DSCR_COR8 \| DSCR_TG1_EN \| DSCR_TG2_EN));	1186	b & ~(DSCR_COR8 \| DSCR_TG1_EN \| DSCR_TG2_EN));
1187	return(1);	1187	return(1);
1188	}	1188	}
1189		1189
1190	return(0);	1190	return(0);
1191	}	1191	}
1192		1192
1193	void data_up_persist_time(int duslic_id, int channel, int time_ms)	1193	void data_up_persist_time(int duslic_id, int channel, int time_ms)
1194	{	1194	{
1195	unsigned char b;	1195	unsigned char b;
1196		1196
1197	b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR);	1197	b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR);
1198	b = (b & 0x0F) \| ((time_ms & 0x0F) << 4);	1198	b = (b & 0x0F) \| ((time_ms & 0x0F) << 4);
1199	codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b);	1199	codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b);
1200	}	1200	}
1201		1201
1202	static void program_dtmf_params(int duslic_id, int channel)	1202	static void program_dtmf_params(int duslic_id, int channel)
1203	{	1203	{
1204	unsigned char b;	1204	unsigned char b;
1205		1205
1206	codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10);	1206	codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10);
1207	codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C);	1207	codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C);
1208	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79);	1208	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79);
1209	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10);	1209	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10);
1210	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02);	1210	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02);
1211	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB);	1211	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB);
1212	codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91);	1212	codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91);
1213	codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00);	1213	codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00);
1214	codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00);	1214	codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00);
1215	codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00);	1215	codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00);
1216		1216
1217	b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR);	1217	b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR);
1218	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b \| BCR5_DTMF_EN);	1218	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b \| BCR5_DTMF_EN);
1219	}	1219	}
1220		1220
1221	static void codsp_channel_full_reset(int duslic_id, int channel)	1221	static void codsp_channel_full_reset(int duslic_id, int channel)
1222	{	1222	{
1223		1223
1224	program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs));	1224	program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs));
1225	program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs));	1225	program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs));
1226		1226
1227	/* program basic configuration registers */	1227	/* program basic configuration registers */
1228	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01);	1228	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01);
1229	codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41);	1229	codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41);
1230	codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43);	1230	codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43);
1231	codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00);	1231	codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00);
1232	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00);	1232	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00);
1233		1233
1234	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04); /* PG */	1234	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04); /* PG */
1235		1235
1236	program_dtmf_params(duslic_id, channel);	1236	program_dtmf_params(duslic_id, channel);
1237		1237
1238	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); /* RingTRip_SEL */	1238	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); /* RingTRip_SEL */
1239		1239
1240	data_up_persist_time(duslic_id, channel, 4);	1240	data_up_persist_time(duslic_id, channel, 4);
1241		1241
1242	codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF); /* All interrupts masked */	1242	codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF); /* All interrupts masked */
1243		1243
1244	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);	1244	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
1245	}	1245	}
1246		1246
1247	static int codsp_chip_full_reset(int duslic_id)	1247	static int codsp_chip_full_reset(int duslic_id)
1248	{	1248	{
1249	int i, cnt;	1249	int i, cnt;
1250	int intreg[NUM_CHANNELS];	1250	int intreg[NUM_CHANNELS];
1251	unsigned char pcm_resync;	1251	unsigned char pcm_resync;
1252	unsigned char revision;	1252	unsigned char revision;
1253		1253
1254	codsp_reset_chip(duslic_id);	1254	codsp_reset_chip(duslic_id);
1255		1255
1256	udelay(2000);	1256	udelay(2000);
1257		1257
1258	for (i = 0; i < NUM_CHANNELS; i++)	1258	for (i = 0; i < NUM_CHANNELS; i++)
1259	intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR);	1259	intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR);
1260		1260
1261	udelay(1500);	1261	udelay(1500);
1262		1262
1263	if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) {	1263	if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) {
1264	printf("_HOOK(%d) stayed low\n", duslic_id);	1264	printf("_HOOK(%d) stayed low\n", duslic_id);
1265	return -1;	1265	return -1;
1266	}	1266	}
1267		1267
1268	for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) {	1268	for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) {
1269	if (intreg[i] & CODSP_INTREG_SYNC_FAIL)	1269	if (intreg[i] & CODSP_INTREG_SYNC_FAIL)
1270	pcm_resync \|= 1 << i;	1270	pcm_resync \|= 1 << i;
1271	}	1271	}
1272		1272
1273	for (cnt = 0; cnt < 5 && pcm_resync; cnt++) {	1273	for (cnt = 0; cnt < 5 && pcm_resync; cnt++) {
1274	for (i = 0; i < NUM_CHANNELS; i++)	1274	for (i = 0; i < NUM_CHANNELS; i++)
1275	codsp_resync_channel(duslic_id, i);	1275	codsp_resync_channel(duslic_id, i);
1276		1276
1277	udelay(2000);	1277	udelay(2000);
1278		1278
1279	pcm_resync = 0;	1279	pcm_resync = 0;
1280		1280
1281	for (i = 0; i < NUM_CHANNELS; i++) {	1281	for (i = 0; i < NUM_CHANNELS; i++) {
1282	if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL)	1282	if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL)
1283	pcm_resync \|= 1 << i;	1283	pcm_resync \|= 1 << i;
1284	}	1284	}
1285	}	1285	}
1286		1286
1287	if (cnt == 5) {	1287	if (cnt == 5) {
1288	printf("PCM_Resync(%u) not completed\n", duslic_id);	1288	printf("PCM_Resync(%u) not completed\n", duslic_id);
1289	return -2;	1289	return -2;
1290	}	1290	}
1291		1291
1292	revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR);	1292	revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR);
1293	printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F);	1293	printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F);
1294		1294
1295	codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80); /* EDSP_EN */	1295	codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80); /* EDSP_EN */
1296		1296
1297	for (i = 0; i < NUM_CHANNELS; i++) {	1297	for (i = 0; i < NUM_CHANNELS; i++) {
1298	codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01);	1298	codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01);
1299	codsp_channel_full_reset(duslic_id, i);	1299	codsp_channel_full_reset(duslic_id, i);
1300	}	1300	}
1301		1301
1302	return 0;	1302	return 0;
1303	}	1303	}
1304		1304
1305	int slic_self_test(int duslic_mask)	1305	int slic_self_test(int duslic_mask)
1306	{	1306	{
1307	int slic;	1307	int slic;
1308	int i;	1308	int i;
1309	int r;	1309	int r;
1310	long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v;	1310	long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v;
1311	const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" };	1311	const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" };
1312	int error = 0;	1312	int error = 0;
1313		1313
1314	for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */	1314	for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */
1315	if (duslic_mask & (1 << (slic >> 1))) {	1315	if (duslic_mask & (1 << (slic >> 1))) {
1316	r = measure_on_hook_voltages(slic, &vdd,	1316	r = measure_on_hook_voltages(slic, &vdd,
1317	&v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);	1317	&v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
1318		1318
1319	printf("SLIC %u measured voltages (x100):\n\t"	1319	printf("SLIC %u measured voltages (x100):\n\t"
1320	"VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",	1320	"VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
1321	slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);	1321	slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
1322		1322
1323	if (r != 0)	1323	if (r != 0)
1324	error \|= 1 << slic;	1324	error \|= 1 << slic;
1325		1325
1326	for (i = 0; i < 5; i++)	1326	for (i = 0; i < 5; i++)
1327	if (r & (1 << i))	1327	if (r & (1 << i))
1328	printf("\t%s out of range\n", err_txt[i]);	1328	printf("\t%s out of range\n", err_txt[i]);
1329	}	1329	}
1330	}	1330	}
1331		1331
1332	for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */	1332	for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */
1333	if (duslic_mask & (1 << (slic >> 1))) {	1333	if (duslic_mask & (1 << (slic >> 1))) {
1334	printf("SLIC %u VOICE PATH...CHECKING", slic);	1334	printf("SLIC %u VOICE PATH...CHECKING", slic);
1335	printf("\rSLIC %u VOICE PATH...%s\n", slic,	1335	printf("\rSLIC %u VOICE PATH...%s\n", slic,
1336	(r = test_dtmf(slic)) != 0 ? "FAILED " : "PASSED ");	1336	(r = test_dtmf(slic)) != 0 ? "FAILED " : "PASSED ");
1337		1337
1338	if (r != 0)	1338	if (r != 0)
1339	error \|= 1 << slic;	1339	error \|= 1 << slic;
1340	}	1340	}
1341	}	1341	}
1342		1342
1343	return(error);	1343	return(error);
1344	}	1344	}
1345		1345
1346	#if defined(CONFIG_NETTA_ISDN)	1346	#if defined(CONFIG_NETTA_ISDN)
1347		1347
1348	#define SPIENS1 (1 << (31 - 15))	1348	#define SPIENS1 (1 << (31 - 15))
1349	#define SPIENS2 (1 << (31 - 19))	1349	#define SPIENS2 (1 << (31 - 19))
1350		1350
1351	static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 };	1351	static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 };
1352	int s_initialized = 0;	1352	int s_initialized = 0;
1353		1353
1354	static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value)	1354	static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value)
1355	{	1355	{
1356	unsigned int rx, v;	1356	unsigned int rx, v;
1357		1357
1358	_PORTB_SET(spiens_mask_tab[s_id], 0);	1358	_PORTB_SET(spiens_mask_tab[s_id], 0);
1359		1359
1360	rx = __SPI_Transfer(address);	1360	rx = __SPI_Transfer(address);
1361		1361
1362	switch (address & 0xF0) {	1362	switch (address & 0xF0) {
1363	case 0x60: /* write byte register */	1363	case 0x60: /* write byte register */
1364	case 0x70:	1364	case 0x70:
1365	rx = __SPI_Transfer(value);	1365	rx = __SPI_Transfer(value);
1366	break;	1366	break;
1367		1367
1368	case 0xE0: /* read R6 register */	1368	case 0xE0: /* read R6 register */
1369	v = __SPI_Transfer(0);	1369	v = __SPI_Transfer(0);
1370		1370
1371	rx = (rx << 8) \| v;	1371	rx = (rx << 8) \| v;
1372		1372
1373	break;	1373	break;
1374		1374
1375	case 0xF0: /* read byte register */	1375	case 0xF0: /* read byte register */
1376	rx = __SPI_Transfer(0);	1376	rx = __SPI_Transfer(0);
1377		1377
1378	break;	1378	break;
1379	}	1379	}
1380		1380
1381	_PORTB_SET(spiens_mask_tab[s_id], 1);	1381	_PORTB_SET(spiens_mask_tab[s_id], 1);
1382		1382
1383	return rx;	1383	return rx;
1384	}	1384	}
1385		1385
1386	static void s_write_BR(int s_id, unsigned int regno, unsigned int val)	1386	static void s_write_BR(int s_id, unsigned int regno, unsigned int val)
1387	{	1387	{
1388	unsigned int address;	1388	unsigned int address;
1389	unsigned int v;	1389	unsigned int v;
1390		1390
1391	address = 0x70 \| (regno & 15);	1391	address = 0x70 \| (regno & 15);
1392	val &= 0xff;	1392	val &= 0xff;
1393		1393
1394	v = s_transfer_internal(s_id, address, val);	1394	v = s_transfer_internal(s_id, address, val);
1395	}	1395	}
1396		1396
1397	static void s_write_OR(int s_id, unsigned int regno, unsigned int val)	1397	static void s_write_OR(int s_id, unsigned int regno, unsigned int val)
1398	{	1398	{
1399	unsigned int address;	1399	unsigned int address;
1400	unsigned int v;	1400	unsigned int v;
1401		1401
1402	address = 0x70 \| (regno & 15);	1402	address = 0x70 \| (regno & 15);
1403	val &= 0xff;	1403	val &= 0xff;
1404		1404
1405	v = s_transfer_internal(s_id, address, val);	1405	v = s_transfer_internal(s_id, address, val);
1406	}	1406	}
1407		1407
1408	static void s_write_NR(int s_id, unsigned int regno, unsigned int val)	1408	static void s_write_NR(int s_id, unsigned int regno, unsigned int val)
1409	{	1409	{
1410	unsigned int address;	1410	unsigned int address;
1411	unsigned int v;	1411	unsigned int v;
1412		1412
1413	address = (regno & 7) << 4;	1413	address = (regno & 7) << 4;
1414	val &= 0xf;	1414	val &= 0xf;
1415		1415
1416	v = s_transfer_internal(s_id, address \| val, 0x00);	1416	v = s_transfer_internal(s_id, address \| val, 0x00);
1417	}	1417	}
1418		1418
1419	#define BR7_IFR 0x08 /* IDL2 free run */	1419	#define BR7_IFR 0x08 /* IDL2 free run */
1420	#define BR7_ICSLSB 0x04 /* IDL2 clock speed LSB */	1420	#define BR7_ICSLSB 0x04 /* IDL2 clock speed LSB */
1421		1421
1422	#define BR15_OVRL_REG_EN 0x80	1422	#define BR15_OVRL_REG_EN 0x80
1423	#define OR7_D3VR 0x80 /* disable 3V regulator */	1423	#define OR7_D3VR 0x80 /* disable 3V regulator */
1424		1424
1425	#define OR8_TEME 0x10 /* TE mode enable */	1425	#define OR8_TEME 0x10 /* TE mode enable */
1426	#define OR8_MME 0x08 /* master mode enable */	1426	#define OR8_MME 0x08 /* master mode enable */
1427		1427
1428	void s_initialize(void)	1428	void s_initialize(void)
1429	{	1429	{
1430	int s_id;	1430	int s_id;
1431		1431
1432	for (s_id = 0; s_id < 2; s_id++) {	1432	for (s_id = 0; s_id < 2; s_id++) {
1433	s_write_BR(s_id, 7, BR7_IFR \| BR7_ICSLSB);	1433	s_write_BR(s_id, 7, BR7_IFR \| BR7_ICSLSB);
1434	s_write_BR(s_id, 15, BR15_OVRL_REG_EN);	1434	s_write_BR(s_id, 15, BR15_OVRL_REG_EN);
1435	s_write_OR(s_id, 8, OR8_TEME \| OR8_MME);	1435	s_write_OR(s_id, 8, OR8_TEME \| OR8_MME);
1436	s_write_OR(s_id, 7, OR7_D3VR);	1436	s_write_OR(s_id, 7, OR7_D3VR);
1437	s_write_OR(s_id, 6, 0);	1437	s_write_OR(s_id, 6, 0);
1438	s_write_BR(s_id, 15, 0);	1438	s_write_BR(s_id, 15, 0);
1439	s_write_NR(s_id, 3, 0);	1439	s_write_NR(s_id, 3, 0);
1440	}	1440	}
1441	}	1441	}
1442		1442
1443	#endif	1443	#endif
1444		1444
1445	int board_post_codec(int flags)	1445	int board_post_codec(int flags)
1446	{	1446	{
1447	int j;	1447	int j;
1448	int r;	1448	int r;
1449	int duslic_mask;	1449	int duslic_mask;
1450		1450
1451	printf("board_post_dsp\n");	1451	printf("board_post_dsp\n");
1452		1452
1453	#if defined(CONFIG_NETTA_ISDN)	1453	#if defined(CONFIG_NETTA_ISDN)
1454	if (s_initialized == 0) {	1454	if (s_initialized == 0) {
1455	s_initialize();	1455	s_initialize();
1456	s_initialized = 1;	1456	s_initialized = 1;
1457		1457
1458	printf("s_initialized\n");	1458	printf("s_initialized\n");
1459		1459
1460	udelay(20000);	1460	udelay(20000);
1461	}	1461	}
1462	#endif	1462	#endif
1463	duslic_mask = 0;	1463	duslic_mask = 0;
1464		1464
1465	for (j = 0; j < MAX_DUSLIC; j++) {	1465	for (j = 0; j < MAX_DUSLIC; j++) {
1466	if (codsp_chip_full_reset(j) < 0)	1466	if (codsp_chip_full_reset(j) < 0)
1467	printf("Error initializing DuSLIC#%d\n", j);	1467	printf("Error initializing DuSLIC#%d\n", j);
1468	else	1468	else
1469	duslic_mask \|= 1 << j;	1469	duslic_mask \|= 1 << j;
1470	}	1470	}
1471		1471
1472	if (duslic_mask != 0) {	1472	if (duslic_mask != 0) {
1473	printf("Testing SLICs...\n");	1473	printf("Testing SLICs...\n");
1474		1474
1475	r = slic_self_test(duslic_mask);	1475	r = slic_self_test(duslic_mask);
1476	for (j = 0; j < MAX_SLICS; j++) {	1476	for (j = 0; j < MAX_SLICS; j++) {
1477	if (duslic_mask & (1 << (j >> 1)))	1477	if (duslic_mask & (1 << (j >> 1)))
1478	printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK");	1478	printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK");
1479	}	1479	}
1480	}	1480	}
1481	printf("DuSLIC self test finished\n");	1481	printf("DuSLIC self test finished\n");
1482		1482
1483	return 0; /* return -1 on error */	1483	return 0; /* return -1 on error */
1484	}	1484	}
1485		1485

board/siemens/IAD210/atm.c

Diff comments View file @ cd8c877

examples/standalone/timer.c

Diff comments View file @ cd8c877

1	/*	1	/*
2	* (C) Copyright 2000	2	* (C) Copyright 2000
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* See file CREDITS for list of people who contributed to this	5	* See file CREDITS for list of people who contributed to this
6	* project.	6	* project.
7	*	7	*
8	* This program is free software; you can redistribute it and/or	8	* This program is free software; you can redistribute it and/or
9	* modify it under the terms of the GNU General Public License as	9	* modify it under the terms of the GNU General Public License as
10	* published by the Free Software Foundation; either version 2 of	10	* published by the Free Software Foundation; either version 2 of
11	* the License, or (at your option) any later version.	11	* the License, or (at your option) any later version.
12	*	12	*
13	* This program is distributed in the hope that it will be useful,	13	* This program is distributed in the hope that it will be useful,
14	* but WITHOUT ANY WARRANTY; without even the implied warranty of	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	* GNU General Public License for more details.	16	* GNU General Public License for more details.
17	*	17	*
18	* You should have received a copy of the GNU General Public License	18	* You should have received a copy of the GNU General Public License
19	* along with this program; if not, write to the Free Software	19	* along with this program; if not, write to the Free Software
20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21	* MA 02111-1307 USA	21	* MA 02111-1307 USA
22	*/	22	*/
23		23
24	#include <common.h>	24	#include <common.h>
25	#include <commproc.h>	25	#include <commproc.h>
26	#include <mpc8xx_irq.h>	26	#include <mpc8xx_irq.h>
27	#include <exports.h>	27	#include <exports.h>
28		28
29	DECLARE_GLOBAL_DATA_PTR;	29	DECLARE_GLOBAL_DATA_PTR;
30		30
31	#undef DEBUG	31	#undef DEBUG
32		32
33	#define TIMER_PERIOD 1000000 /* 1 second clock */	33	#define TIMER_PERIOD 1000000 /* 1 second clock */
34		34
35	static void timer_handler (void *arg);	35	static void timer_handler (void *arg);
36		36
37		37
38	/* Access functions for the Machine State Register */	38	/* Access functions for the Machine State Register */
39	static __inline__ unsigned long get_msr(void)	39	static __inline__ unsigned long get_msr(void)
40	{	40	{
41	unsigned long msr;	41	unsigned long msr;
42		42
43	asm volatile("mfmsr %0" : "=r" (msr) :);	43	asm volatile("mfmsr %0" : "=r" (msr) :);
44	return msr;	44	return msr;
45	}	45	}
46		46
47	static __inline__ void set_msr(unsigned long msr)	47	static __inline__ void set_msr(unsigned long msr)
48	{	48	{
49	asm volatile("mtmsr %0" : : "r" (msr));	49	asm volatile("mtmsr %0" : : "r" (msr));
50	}	50	}
51		51
52	/*	52	/*
53	* Definitions to access the CPM Timer registers	53	* Definitions to access the CPM Timer registers
54	* See 8xx_immap.h for Internal Memory Map layout,	54	* See 8xx_immap.h for Internal Memory Map layout,
55	* and commproc.h for CPM Interrupt vectors (aka "IRQ"s)	55	* and commproc.h for CPM Interrupt vectors (aka "IRQ"s)
56	*/	56	*/
57		57
58	typedef struct tid_8xx_cpmtimer_s {	58	typedef struct tid_8xx_cpmtimer_s {
59	int cpm_vec; /* CPM Interrupt Vector for this timer */	59	int cpm_vec; /* CPM Interrupt Vector for this timer */
60	ushort tgcrp; / Pointer to Timer Global Config Reg. */	60	ushort tgcrp; / Pointer to Timer Global Config Reg. */
61	ushort tmrp; / Pointer to Timer Mode Register */	61	ushort tmrp; / Pointer to Timer Mode Register */
62	ushort trrp; / Pointer to Timer Reference Register */	62	ushort trrp; / Pointer to Timer Reference Register */
63	ushort tcrp; / Pointer to Timer Capture Register */	63	ushort tcrp; / Pointer to Timer Capture Register */
64	ushort tcnp; / Pointer to Timer Counter Register */	64	ushort tcnp; / Pointer to Timer Counter Register */
65	ushort terp; / Pointer to Timer Event Register */	65	ushort terp; / Pointer to Timer Event Register */
66	} tid_8xx_cpmtimer_t;	66	} tid_8xx_cpmtimer_t;
67		67
68	#ifndef CLOCKRATE	68	#ifndef CLOCKRATE
69	# define CLOCKRATE 64	69	# define CLOCKRATE 64
70	#endif	70	#endif
71		71
72	#define CPMT_CLOCK_DIV 16	72	#define CPMT_CLOCK_DIV 16
73	#define CPMT_MAX_PRESCALER 256	73	#define CPMT_MAX_PRESCALER 256
74	#define CPMT_MAX_REFERENCE 65535 /* max. unsigned short */	74	#define CPMT_MAX_REFERENCE 65535 /* max. unsigned short */
75		75
76	#define CPMT_MAX_TICKS (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER)	76	#define CPMT_MAX_TICKS (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER)
77	#define CPMT_MAX_TICKS_WITH_DIV (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER * CPMT_CLOCK_DIV)	77	#define CPMT_MAX_TICKS_WITH_DIV (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER * CPMT_CLOCK_DIV)
78	#define CPMT_MAX_INTERVAL (CPMT_MAX_TICKS_WITH_DIV / CLOCKRATE)	78	#define CPMT_MAX_INTERVAL (CPMT_MAX_TICKS_WITH_DIV / CLOCKRATE)
79		79
80	/* For now: always use max. prescaler value */	80	/* For now: always use max. prescaler value */
81	#define CPMT_PRESCALER (CPMT_MAX_PRESCALER)	81	#define CPMT_PRESCALER (CPMT_MAX_PRESCALER)
82		82
83	/* CPM Timer Event Register Bits */	83	/* CPM Timer Event Register Bits */
84	#define CPMT_EVENT_CAP 0x0001 /* Capture Event */	84	#define CPMT_EVENT_CAP 0x0001 /* Capture Event */
85	#define CPMT_EVENT_REF 0x0002 /* Reference Counter Event */	85	#define CPMT_EVENT_REF 0x0002 /* Reference Counter Event */
86		86
87	/* CPM Timer Global Config Register */	87	/* CPM Timer Global Config Register */
88	#define CPMT_GCR_RST 0x0001 /* Reset Timer */	88	#define CPMT_GCR_RST 0x0001 /* Reset Timer */
89	#define CPMT_GCR_STP 0x0002 /* Stop Timer */	89	#define CPMT_GCR_STP 0x0002 /* Stop Timer */
90	#define CPMT_GCR_FRZ 0x0004 /* Freeze Timer */	90	#define CPMT_GCR_FRZ 0x0004 /* Freeze Timer */
91	#define CPMT_GCR_GM_CAS 0x0008 /* Gate Mode / Cascade Timers */	91	#define CPMT_GCR_GM_CAS 0x0008 /* Gate Mode / Cascade Timers */
92	#define CPMT_GCR_MASK (CPMT_GCR_RST\|CPMT_GCR_STP\|CPMT_GCR_FRZ\|CPMT_GCR_GM_CAS)	92	#define CPMT_GCR_MASK (CPMT_GCR_RST\|CPMT_GCR_STP\|CPMT_GCR_FRZ\|CPMT_GCR_GM_CAS)
93		93
94	/* CPM Timer Mode register */	94	/* CPM Timer Mode register */
95	#define CPMT_MR_GE 0x0001 /* Gate Enable */	95	#define CPMT_MR_GE 0x0001 /* Gate Enable */
96	#define CPMT_MR_ICLK_CASC 0x0000 /* Clock internally cascaded */	96	#define CPMT_MR_ICLK_CASC 0x0000 /* Clock internally cascaded */
97	#define CPMT_MR_ICLK_CLK 0x0002 /* Clock = system clock */	97	#define CPMT_MR_ICLK_CLK 0x0002 /* Clock = system clock */
98	#define CPMT_MR_ICLK_CLKDIV 0x0004 /* Clock = system clock / 16 */	98	#define CPMT_MR_ICLK_CLKDIV 0x0004 /* Clock = system clock / 16 */
99	#define CPMT_MR_ICLK_TIN 0x0006 /* Clock = TINx signal */	99	#define CPMT_MR_ICLK_TIN 0x0006 /* Clock = TINx signal */
100	#define CPMT_MR_FRR 0x0008 /* Free Run / Restart */	100	#define CPMT_MR_FRR 0x0008 /* Free Run / Restart */
101	#define CPMT_MR_ORI 0x0010 /* Out. Reference Interrupt En. */	101	#define CPMT_MR_ORI 0x0010 /* Out. Reference Interrupt En. */
102	#define CPMT_MR_OM 0x0020 /* Output Mode */	102	#define CPMT_MR_OM 0x0020 /* Output Mode */
103	#define CPMT_MR_CE_DIS 0x0000 /* Capture/Interrupt disabled */	103	#define CPMT_MR_CE_DIS 0x0000 /* Capture/Interrupt disabled */
104	#define CPMT_MR_CE_RISE 0x0040 /* Capt./Interr. on rising TIN */	104	#define CPMT_MR_CE_RISE 0x0040 /* Capt./Interr. on rising TIN */
105	#define CPMT_MR_CE_FALL 0x0080 /* Capt./Interr. on falling TIN */	105	#define CPMT_MR_CE_FALL 0x0080 /* Capt./Interr. on falling TIN */
106	#define CPMT_MR_CE_ANY 0x00C0 /* Capt./Interr. on any TIN edge*/	106	#define CPMT_MR_CE_ANY 0x00C0 /* Capt./Interr. on any TIN edge*/
107		107
108		108
109	/*	109	/*
110	* which CPM timer to use - index starts at 0 (= timer 1)	110	* which CPM timer to use - index starts at 0 (= timer 1)
111	*/	111	*/
112	#define TID_TIMER_ID 0 /* use CPM timer 1 */	112	#define TID_TIMER_ID 0 /* use CPM timer 1 */
113		113
114	void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval);	114	void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval);
115		115
116	static char *usage = "\n[q, b, e, ?] ";	116	static const char usage[] = "\n[q, b, e, ?] ";
117		117
118	int timer (int argc, char * const argv[])	118	int timer (int argc, char * const argv[])
119	{	119	{
120	cpmtimer8xx_t cpmtimerp; / Pointer to the CPM Timer structure */	120	cpmtimer8xx_t cpmtimerp; / Pointer to the CPM Timer structure */
121	tid_8xx_cpmtimer_t hw;	121	tid_8xx_cpmtimer_t hw;
122	tid_8xx_cpmtimer_t *hwp = &hw;	122	tid_8xx_cpmtimer_t *hwp = &hw;
123	int c;	123	int c;
124	int running;	124	int running;
125		125
126	app_startup(argv);	126	app_startup(argv);
127		127
128	/* Pointer to CPM Timer structure */	128	/* Pointer to CPM Timer structure */
129	cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer;	129	cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer;
130		130
131	printf ("TIMERS=0x%x\n", (unsigned) cpmtimerp);	131	printf ("TIMERS=0x%x\n", (unsigned) cpmtimerp);
132		132
133	/* Initialize pointers depending on which timer we use */	133	/* Initialize pointers depending on which timer we use */
134	switch (TID_TIMER_ID) {	134	switch (TID_TIMER_ID) {
135	case 0:	135	case 0:
136	hwp->tmrp = &(cpmtimerp->cpmt_tmr1);	136	hwp->tmrp = &(cpmtimerp->cpmt_tmr1);
137	hwp->trrp = &(cpmtimerp->cpmt_trr1);	137	hwp->trrp = &(cpmtimerp->cpmt_trr1);
138	hwp->tcrp = &(cpmtimerp->cpmt_tcr1);	138	hwp->tcrp = &(cpmtimerp->cpmt_tcr1);
139	hwp->tcnp = &(cpmtimerp->cpmt_tcn1);	139	hwp->tcnp = &(cpmtimerp->cpmt_tcn1);
140	hwp->terp = &(cpmtimerp->cpmt_ter1);	140	hwp->terp = &(cpmtimerp->cpmt_ter1);
141	hwp->cpm_vec = CPMVEC_TIMER1;	141	hwp->cpm_vec = CPMVEC_TIMER1;
142	break;	142	break;
143	case 1:	143	case 1:
144	hwp->tmrp = &(cpmtimerp->cpmt_tmr2);	144	hwp->tmrp = &(cpmtimerp->cpmt_tmr2);
145	hwp->trrp = &(cpmtimerp->cpmt_trr2);	145	hwp->trrp = &(cpmtimerp->cpmt_trr2);
146	hwp->tcrp = &(cpmtimerp->cpmt_tcr2);	146	hwp->tcrp = &(cpmtimerp->cpmt_tcr2);
147	hwp->tcnp = &(cpmtimerp->cpmt_tcn2);	147	hwp->tcnp = &(cpmtimerp->cpmt_tcn2);
148	hwp->terp = &(cpmtimerp->cpmt_ter2);	148	hwp->terp = &(cpmtimerp->cpmt_ter2);
149	hwp->cpm_vec = CPMVEC_TIMER2;	149	hwp->cpm_vec = CPMVEC_TIMER2;
150	break;	150	break;
151	case 2:	151	case 2:
152	hwp->tmrp = &(cpmtimerp->cpmt_tmr3);	152	hwp->tmrp = &(cpmtimerp->cpmt_tmr3);
153	hwp->trrp = &(cpmtimerp->cpmt_trr3);	153	hwp->trrp = &(cpmtimerp->cpmt_trr3);
154	hwp->tcrp = &(cpmtimerp->cpmt_tcr3);	154	hwp->tcrp = &(cpmtimerp->cpmt_tcr3);
155	hwp->tcnp = &(cpmtimerp->cpmt_tcn3);	155	hwp->tcnp = &(cpmtimerp->cpmt_tcn3);
156	hwp->terp = &(cpmtimerp->cpmt_ter3);	156	hwp->terp = &(cpmtimerp->cpmt_ter3);
157	hwp->cpm_vec = CPMVEC_TIMER3;	157	hwp->cpm_vec = CPMVEC_TIMER3;
158	break;	158	break;
159	case 3:	159	case 3:
160	hwp->tmrp = &(cpmtimerp->cpmt_tmr4);	160	hwp->tmrp = &(cpmtimerp->cpmt_tmr4);
161	hwp->trrp = &(cpmtimerp->cpmt_trr4);	161	hwp->trrp = &(cpmtimerp->cpmt_trr4);
162	hwp->tcrp = &(cpmtimerp->cpmt_tcr4);	162	hwp->tcrp = &(cpmtimerp->cpmt_tcr4);
163	hwp->tcnp = &(cpmtimerp->cpmt_tcn4);	163	hwp->tcnp = &(cpmtimerp->cpmt_tcn4);
164	hwp->terp = &(cpmtimerp->cpmt_ter4);	164	hwp->terp = &(cpmtimerp->cpmt_ter4);
165	hwp->cpm_vec = CPMVEC_TIMER4;	165	hwp->cpm_vec = CPMVEC_TIMER4;
166	break;	166	break;
167	}	167	}
168		168
169	hwp->tgcrp = &cpmtimerp->cpmt_tgcr;	169	hwp->tgcrp = &cpmtimerp->cpmt_tgcr;
170		170
171	printf ("Using timer %d\n"	171	printf ("Using timer %d\n"
172	"tgcr @ 0x%x, tmr @ 0x%x, trr @ 0x%x,"	172	"tgcr @ 0x%x, tmr @ 0x%x, trr @ 0x%x,"
173	" tcr @ 0x%x, tcn @ 0x%x, ter @ 0x%x\n",	173	" tcr @ 0x%x, tcn @ 0x%x, ter @ 0x%x\n",
174	TID_TIMER_ID + 1,	174	TID_TIMER_ID + 1,
175	(unsigned) hwp->tgcrp,	175	(unsigned) hwp->tgcrp,
176	(unsigned) hwp->tmrp,	176	(unsigned) hwp->tmrp,
177	(unsigned) hwp->trrp,	177	(unsigned) hwp->trrp,
178	(unsigned) hwp->tcrp,	178	(unsigned) hwp->tcrp,
179	(unsigned) hwp->tcnp,	179	(unsigned) hwp->tcnp,
180	(unsigned) hwp->terp	180	(unsigned) hwp->terp
181	);	181	);
182		182
183	/* reset timer */	183	/* reset timer */
184	*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);	184	*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
185		185
186	/* clear all events */	186	/* clear all events */
187	*hwp->terp = (CPMT_EVENT_CAP \| CPMT_EVENT_REF);	187	*hwp->terp = (CPMT_EVENT_CAP \| CPMT_EVENT_REF);
188		188
189	printf (usage);	189	puts(usage);
190	running = 0;	190	running = 0;
191	while ((c = getc()) != 'q') {	191	while ((c = getc()) != 'q') {
192	if (c == 'b') {	192	if (c == 'b') {
193		193
194	setPeriod (hwp, TIMER_PERIOD); /* Set period and start ticking */	194	setPeriod (hwp, TIMER_PERIOD); /* Set period and start ticking */
195		195
196	/* Install interrupt handler (enable timer in CIMR) */	196	/* Install interrupt handler (enable timer in CIMR) */
197	install_hdlr (hwp->cpm_vec, timer_handler, hwp);	197	install_hdlr (hwp->cpm_vec, timer_handler, hwp);
198		198
199	printf ("Enabling timer\n");	199	printf ("Enabling timer\n");
200		200
201	/* enable timer */	201	/* enable timer */
202	*hwp->tgcrp \|= (CPMT_GCR_RST << TID_TIMER_ID);	202	*hwp->tgcrp \|= (CPMT_GCR_RST << TID_TIMER_ID);
203	running = 1;	203	running = 1;
204		204
205	#ifdef DEBUG	205	#ifdef DEBUG
206	printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"	206	printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
207	" tcr=0x%x, tcn=0x%x, ter=0x%x\n",	207	" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
208	hwp->tgcrp, hwp->tmrp, *hwp->trrp,	208	hwp->tgcrp, hwp->tmrp, *hwp->trrp,
209	hwp->tcrp, hwp->tcnp, *hwp->terp	209	hwp->tcrp, hwp->tcnp, *hwp->terp
210	);	210	);
211	#endif	211	#endif
212	} else if (c == 'e') {	212	} else if (c == 'e') {
213		213
214	printf ("Stopping timer\n");	214	printf ("Stopping timer\n");
215		215
216	*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);	216	*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
217	running = 0;	217	running = 0;
218		218
219	#ifdef DEBUG	219	#ifdef DEBUG
220	printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"	220	printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
221	" tcr=0x%x, tcn=0x%x, ter=0x%x\n",	221	" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
222	hwp->tgcrp, hwp->tmrp, *hwp->trrp,	222	hwp->tgcrp, hwp->tmrp, *hwp->trrp,
223	hwp->tcrp, hwp->tcnp, *hwp->terp	223	hwp->tcrp, hwp->tcnp, *hwp->terp
224	);	224	);
225	#endif	225	#endif
226	/* Uninstall interrupt handler */	226	/* Uninstall interrupt handler */
227	free_hdlr (hwp->cpm_vec);	227	free_hdlr (hwp->cpm_vec);
228		228
229	} else if (c == '?') {	229	} else if (c == '?') {
230	#ifdef DEBUG	230	#ifdef DEBUG
231	cpic8xx_t cpm_icp = &((immap_t ) gd->bd->bi_immr_base)->im_cpic;	231	cpic8xx_t cpm_icp = &((immap_t ) gd->bd->bi_immr_base)->im_cpic;
232	sysconf8xx_t siup = &((immap_t ) gd->bd->bi_immr_base)->im_siu_conf;	232	sysconf8xx_t siup = &((immap_t ) gd->bd->bi_immr_base)->im_siu_conf;
233	#endif	233	#endif
234		234
235	printf ("\ntgcr=0x%x, tmr=0x%x, trr=0x%x,"	235	printf ("\ntgcr=0x%x, tmr=0x%x, trr=0x%x,"
236	" tcr=0x%x, tcn=0x%x, ter=0x%x\n",	236	" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
237	hwp->tgcrp, hwp->tmrp, *hwp->trrp,	237	hwp->tgcrp, hwp->tmrp, *hwp->trrp,
238	hwp->tcrp, hwp->tcnp, *hwp->terp	238	hwp->tcrp, hwp->tcnp, *hwp->terp
239	);	239	);
240	#ifdef DEBUG	240	#ifdef DEBUG
241	printf ("SIUMCR=0x%08lx, SYPCR=0x%08lx,"	241	printf ("SIUMCR=0x%08lx, SYPCR=0x%08lx,"
242	" SIMASK=0x%08lx, SIPEND=0x%08lx\n",	242	" SIMASK=0x%08lx, SIPEND=0x%08lx\n",
243	siup->sc_siumcr,	243	siup->sc_siumcr,
244	siup->sc_sypcr,	244	siup->sc_sypcr,
245	siup->sc_simask,	245	siup->sc_simask,
246	siup->sc_sipend	246	siup->sc_sipend
247	);	247	);
248		248
249	printf ("CIMR=0x%08lx, CICR=0x%08lx, CIPR=0x%08lx\n",	249	printf ("CIMR=0x%08lx, CICR=0x%08lx, CIPR=0x%08lx\n",
250	cpm_icp->cpic_cimr,	250	cpm_icp->cpic_cimr,
251	cpm_icp->cpic_cicr,	251	cpm_icp->cpic_cicr,
252	cpm_icp->cpic_cipr	252	cpm_icp->cpic_cipr
253	);	253	);
254	#endif	254	#endif
255	} else {	255	} else {
256	printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n");	256	printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n");
257	}	257	}
258	printf (usage);	258	puts(usage);
259	}	259	}
260	if (running) {	260	if (running) {
261	printf ("Stopping timer\n");	261	printf ("Stopping timer\n");
262	*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);	262	*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
263	free_hdlr (hwp->cpm_vec);	263	free_hdlr (hwp->cpm_vec);
264	}	264	}
265		265
266	return (0);	266	return (0);
267	}	267	}
268		268
269		269
270	/* Set period in microseconds and start.	270	/* Set period in microseconds and start.
271	* Truncate to maximum period if more than this is requested - but warn about it.	271	* Truncate to maximum period if more than this is requested - but warn about it.
272	*/	272	*/
273		273
274	void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval)	274	void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval)
275	{	275	{
276	unsigned short prescaler;	276	unsigned short prescaler;
277	unsigned long ticks;	277	unsigned long ticks;
278		278
279	printf ("Set interval %ld us\n", interval);	279	printf ("Set interval %ld us\n", interval);
280		280
281	/* Warn if requesting longer period than possible */	281	/* Warn if requesting longer period than possible */
282	if (interval > CPMT_MAX_INTERVAL) {	282	if (interval > CPMT_MAX_INTERVAL) {
283	printf ("Truncate interval %ld to maximum (%d)\n",	283	printf ("Truncate interval %ld to maximum (%d)\n",
284	interval, CPMT_MAX_INTERVAL);	284	interval, CPMT_MAX_INTERVAL);
285	interval = CPMT_MAX_INTERVAL;	285	interval = CPMT_MAX_INTERVAL;
286	}	286	}
287	/*	287	/*
288	* Check if we want to use clock divider:	288	* Check if we want to use clock divider:
289	* Since the reference counter can be incremented only in integer steps,	289	* Since the reference counter can be incremented only in integer steps,
290	* we try to keep it as big as possible to allow the resulting period to be	290	* we try to keep it as big as possible to allow the resulting period to be
291	* as precise as possible.	291	* as precise as possible.
292	*/	292	*/
293	/* prescaler, enable interrupt, restart after ref count is reached */	293	/* prescaler, enable interrupt, restart after ref count is reached */
294	prescaler = (ushort) ((CPMT_PRESCALER - 1) << 8) \|	294	prescaler = (ushort) ((CPMT_PRESCALER - 1) << 8) \|
295	CPMT_MR_ORI \|	295	CPMT_MR_ORI \|
296	CPMT_MR_FRR;	296	CPMT_MR_FRR;
297		297
298	ticks = ((ulong) CLOCKRATE * interval);	298	ticks = ((ulong) CLOCKRATE * interval);
299		299
300	if (ticks > CPMT_MAX_TICKS) {	300	if (ticks > CPMT_MAX_TICKS) {
301	ticks /= CPMT_CLOCK_DIV;	301	ticks /= CPMT_CLOCK_DIV;
302	prescaler \|= CPMT_MR_ICLK_CLKDIV; /* use system clock divided by 16 */	302	prescaler \|= CPMT_MR_ICLK_CLKDIV; /* use system clock divided by 16 */
303	} else {	303	} else {
304	prescaler \|= CPMT_MR_ICLK_CLK; /* use system clock without divider */	304	prescaler \|= CPMT_MR_ICLK_CLK; /* use system clock without divider */
305	}	305	}
306		306
307	#ifdef DEBUG	307	#ifdef DEBUG
308	printf ("clock/%d, prescale factor %d, reference %ld, ticks %ld\n",	308	printf ("clock/%d, prescale factor %d, reference %ld, ticks %ld\n",
309	(ticks > CPMT_MAX_TICKS) ? CPMT_CLOCK_DIV : 1,	309	(ticks > CPMT_MAX_TICKS) ? CPMT_CLOCK_DIV : 1,
310	CPMT_PRESCALER,	310	CPMT_PRESCALER,
311	(ticks / CPMT_PRESCALER),	311	(ticks / CPMT_PRESCALER),
312	ticks	312	ticks
313	);	313	);
314	#endif	314	#endif
315		315
316	/* set prescaler register */	316	/* set prescaler register */
317	*hwp->tmrp = prescaler;	317	*hwp->tmrp = prescaler;
318		318
319	/* clear timer counter */	319	/* clear timer counter */
320	*hwp->tcnp = 0;	320	*hwp->tcnp = 0;
321		321
322	/* set reference register */	322	/* set reference register */
323	*hwp->trrp = (unsigned short) (ticks / CPMT_PRESCALER);	323	*hwp->trrp = (unsigned short) (ticks / CPMT_PRESCALER);
324		324
325	#ifdef DEBUG	325	#ifdef DEBUG
326	printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"	326	printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
327	" tcr=0x%x, tcn=0x%x, ter=0x%x\n",	327	" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
328	hwp->tgcrp, hwp->tmrp, *hwp->trrp,	328	hwp->tgcrp, hwp->tmrp, *hwp->trrp,
329	hwp->tcrp, hwp->tcnp, *hwp->terp	329	hwp->tcrp, hwp->tcnp, *hwp->terp
330	);	330	);
331	#endif	331	#endif
332	}	332	}
333		333
334	/*	334	/*
335	* Handler for CPMVEC_TIMER1 interrupt	335	* Handler for CPMVEC_TIMER1 interrupt
336	*/	336	*/
337	static	337	static
338	void timer_handler (void *arg)	338	void timer_handler (void *arg)
339	{	339	{
340	tid_8xx_cpmtimer_t hwp = (tid_8xx_cpmtimer_t )arg;	340	tid_8xx_cpmtimer_t hwp = (tid_8xx_cpmtimer_t )arg;
341		341
342	/* printf (" TER1=%04x ", hwp->terp); /	342	/* printf (" TER1=%04x ", hwp->terp); /
343		343
344	/* just for demonstration */	344	/* just for demonstration */
345	printf (".");	345	printf (".");
346		346
347	/* clear all possible events: Ref. and Cap. */	347	/* clear all possible events: Ref. and Cap. */
348	*hwp->terp = (CPMT_EVENT_CAP \| CPMT_EVENT_REF);	348	*hwp->terp = (CPMT_EVENT_CAP \| CPMT_EVENT_REF);
349	}	349	}
350		350

1	#include <common.h>	1	#include <common.h>
2	#include <mpc8xx.h>	2	#include <mpc8xx.h>
3	#include <commproc.h>	3	#include <commproc.h>
4		4
5	#include "atm.h"	5	#include "atm.h"
6	#include <linux/stddef.h>	6	#include <linux/stddef.h>
7		7
8	#define SYNC __asm__("sync")	8	#define SYNC __asm__("sync")
9	#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))	9	#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
10		10
11	#define FALSE 1	11	#define FALSE 1
12	#define TRUE 0	12	#define TRUE 0
13	#define OK 0	13	#define OK 0
14	#define ERROR -1	14	#define ERROR -1
15		15
16	struct atm_connection_t g_conn[NUM_CONNECTIONS] =	16	struct atm_connection_t g_conn[NUM_CONNECTIONS] =
17	{	17	{
18	{ NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */	18	{ NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */
19	};	19	};
20		20
21	struct atm_driver_t g_atm =	21	struct atm_driver_t g_atm =
22	{	22	{
23	FALSE, /* loaded */	23	FALSE, /* loaded */
24	FALSE, /* started */	24	FALSE, /* started */
25	NULL, /* csram */	25	NULL, /* csram */
26	0, /* csram_size */	26	0, /* csram_size */
27	NULL, /* am_top */	27	NULL, /* am_top */
28	NULL, /* ap_top */	28	NULL, /* ap_top */
29	NULL, /* int_reload_ptr */	29	NULL, /* int_reload_ptr */
30	NULL, /* int_serv_ptr */	30	NULL, /* int_serv_ptr */
31	NULL, /* rbd_base_ptr */	31	NULL, /* rbd_base_ptr */
32	NULL, /* tbd_base_ptr */	32	NULL, /* tbd_base_ptr */
33	0 /* linerate */	33	0 /* linerate */
34	};	34	};
35		35
36	char csram[1024]; /* more than enough for doing nothing*/	36	char csram[1024]; /* more than enough for doing nothing*/
37		37
38	int atmLoad(void);	38	int atmLoad(void);
39	void atmUnload(void);	39	void atmUnload(void);
40	int atmMemInit(void);	40	int atmMemInit(void);