Eric Lee / smarc-uboot

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Commit cde504077e1ce94d9ad34ece0f3e882972404297

Authored by Ye Li
1 parent af92ba299b
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-14422 imx7d: wdog: Overwrite the reset_cpu to turn off internal reset signal 

Set wdog WCR register SRS bit to turn off internal reset signal WDOG_RESET_B_DEB
for mx7d. So that the warm reset is disabled.
The WDA is cleared to output WDOG_B immediately to reset the board.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 6d09863801695d975060fbc240147a9067dbafbf)

Showing 1 changed file with 14 additions and 0 deletions Inline Diff

arch/arm/mach-imx/mx7/soc.c
Diff comments   View file @ cde5040
1 /* 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/clock.h> 11 #include <asm/arch/clock.h>
12 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/boot_mode.h> 13 #include <asm/mach-imx/boot_mode.h>
14 #include <asm/mach-imx/dma.h> 14 #include <asm/mach-imx/dma.h>
15 #include <asm/mach-imx/hab.h> 15 #include <asm/mach-imx/hab.h>
16 #include <asm/mach-imx/rdc-sema.h> 16 #include <asm/mach-imx/rdc-sema.h>
17 #include <asm/arch/imx-rdc.h> 17 #include <asm/arch/imx-rdc.h>
18 #include <asm/arch/crm_regs.h> 18 #include <asm/arch/crm_regs.h>
19 #include <dm.h> 19 #include <dm.h>
20 #include <imx_thermal.h> 20 #include <imx_thermal.h>
21 #include <fsl_sec.h> 21 #include <fsl_sec.h>
22 #include <fsl_wdog.h>
22 23
23 #if defined(CONFIG_IMX_THERMAL) 24 #if defined(CONFIG_IMX_THERMAL)
24 static const struct imx_thermal_plat imx7_thermal_plat = { 25 static const struct imx_thermal_plat imx7_thermal_plat = {
25 .regs = (void *)ANATOP_BASE_ADDR, 26 .regs = (void *)ANATOP_BASE_ADDR,
26 .fuse_bank = 3, 27 .fuse_bank = 3,
27 .fuse_word = 3, 28 .fuse_word = 3,
28 }; 29 };
29 30
30 U_BOOT_DEVICE(imx7_thermal) = { 31 U_BOOT_DEVICE(imx7_thermal) = {
31 .name = "imx_thermal", 32 .name = "imx_thermal",
32 .platdata = &imx7_thermal_plat, 33 .platdata = &imx7_thermal_plat,
33 }; 34 };
34 #endif 35 #endif
35 36
36 #if CONFIG_IS_ENABLED(IMX_RDC) 37 #if CONFIG_IS_ENABLED(IMX_RDC)
37 /* 38 /*
38 * In current design, if any peripheral was assigned to both A7 and M4, 39 * In current design, if any peripheral was assigned to both A7 and M4,
39 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter 40 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
40 * low power mode. So M4 sleep will cause some peripherals fail to work 41 * low power mode. So M4 sleep will cause some peripherals fail to work
41 * at A7 core side. At default, all resources are in domain 0 - 3. 42 * at A7 core side. At default, all resources are in domain 0 - 3.
42 * 43 *
43 * There are 26 peripherals impacted by this IC issue: 44 * There are 26 peripherals impacted by this IC issue:
44 * SIM2(sim2/emvsim2) 45 * SIM2(sim2/emvsim2)
45 * SIM1(sim1/emvsim1) 46 * SIM1(sim1/emvsim1)
46 * UART1/UART2/UART3/UART4/UART5/UART6/UART7 47 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
47 * SAI1/SAI2/SAI3 48 * SAI1/SAI2/SAI3
48 * WDOG1/WDOG2/WDOG3/WDOG4 49 * WDOG1/WDOG2/WDOG3/WDOG4
49 * GPT1/GPT2/GPT3/GPT4 50 * GPT1/GPT2/GPT3/GPT4
50 * PWM1/PWM2/PWM3/PWM4 51 * PWM1/PWM2/PWM3/PWM4
51 * ENET1/ENET2 52 * ENET1/ENET2
52 * Software Workaround: 53 * Software Workaround:
53 * Here we setup some resources to domain 0 where M4 codes will move 54 * Here we setup some resources to domain 0 where M4 codes will move
54 * the M4 out of this domain. Then M4 is not able to access them any longer. 55 * the M4 out of this domain. Then M4 is not able to access them any longer.
55 * This is a workaround for ic issue. So the peripherals are not shared 56 * This is a workaround for ic issue. So the peripherals are not shared
56 * by them. This way requires the uboot implemented the RDC driver and 57 * by them. This way requires the uboot implemented the RDC driver and
57 * set the 26 IPs above to domain 0 only. M4 code will assign resource 58 * set the 26 IPs above to domain 0 only. M4 code will assign resource
58 * to its own domain, if it want to use the resource. 59 * to its own domain, if it want to use the resource.
59 */ 60 */
60 static rdc_peri_cfg_t const resources[] = { 61 static rdc_peri_cfg_t const resources[] = {
61 (RDC_PER_SIM1 | RDC_DOMAIN(0)), 62 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
62 (RDC_PER_SIM2 | RDC_DOMAIN(0)), 63 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
63 (RDC_PER_UART1 | RDC_DOMAIN(0)), 64 (RDC_PER_UART1 | RDC_DOMAIN(0)),
64 (RDC_PER_UART2 | RDC_DOMAIN(0)), 65 (RDC_PER_UART2 | RDC_DOMAIN(0)),
65 (RDC_PER_UART3 | RDC_DOMAIN(0)), 66 (RDC_PER_UART3 | RDC_DOMAIN(0)),
66 (RDC_PER_UART4 | RDC_DOMAIN(0)), 67 (RDC_PER_UART4 | RDC_DOMAIN(0)),
67 (RDC_PER_UART5 | RDC_DOMAIN(0)), 68 (RDC_PER_UART5 | RDC_DOMAIN(0)),
68 (RDC_PER_UART6 | RDC_DOMAIN(0)), 69 (RDC_PER_UART6 | RDC_DOMAIN(0)),
69 (RDC_PER_UART7 | RDC_DOMAIN(0)), 70 (RDC_PER_UART7 | RDC_DOMAIN(0)),
70 (RDC_PER_SAI1 | RDC_DOMAIN(0)), 71 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
71 (RDC_PER_SAI2 | RDC_DOMAIN(0)), 72 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
72 (RDC_PER_SAI3 | RDC_DOMAIN(0)), 73 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
73 (RDC_PER_WDOG1 | RDC_DOMAIN(0)), 74 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
74 (RDC_PER_WDOG2 | RDC_DOMAIN(0)), 75 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
75 (RDC_PER_WDOG3 | RDC_DOMAIN(0)), 76 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
76 (RDC_PER_WDOG4 | RDC_DOMAIN(0)), 77 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
77 (RDC_PER_GPT1 | RDC_DOMAIN(0)), 78 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
78 (RDC_PER_GPT2 | RDC_DOMAIN(0)), 79 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
79 (RDC_PER_GPT3 | RDC_DOMAIN(0)), 80 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
80 (RDC_PER_GPT4 | RDC_DOMAIN(0)), 81 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
81 (RDC_PER_PWM1 | RDC_DOMAIN(0)), 82 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
82 (RDC_PER_PWM2 | RDC_DOMAIN(0)), 83 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
83 (RDC_PER_PWM3 | RDC_DOMAIN(0)), 84 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
84 (RDC_PER_PWM4 | RDC_DOMAIN(0)), 85 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
85 (RDC_PER_ENET1 | RDC_DOMAIN(0)), 86 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
86 (RDC_PER_ENET2 | RDC_DOMAIN(0)), 87 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
87 }; 88 };
88 89
89 static void isolate_resource(void) 90 static void isolate_resource(void)
90 { 91 {
91 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources)); 92 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
92 } 93 }
93 #endif 94 #endif
94 95
95 #if defined(CONFIG_SECURE_BOOT) 96 #if defined(CONFIG_SECURE_BOOT)
96 struct imx_sec_config_fuse_t const imx_sec_config_fuse = { 97 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
97 .bank = 1, 98 .bank = 1,
98 .word = 3, 99 .word = 3,
99 }; 100 };
100 #endif 101 #endif
101 102
102 static bool is_mx7d(void) 103 static bool is_mx7d(void)
103 { 104 {
104 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 105 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
105 struct fuse_bank *bank = &ocotp->bank[1]; 106 struct fuse_bank *bank = &ocotp->bank[1];
106 struct fuse_bank1_regs *fuse = 107 struct fuse_bank1_regs *fuse =
107 (struct fuse_bank1_regs *)bank->fuse_regs; 108 (struct fuse_bank1_regs *)bank->fuse_regs;
108 int val; 109 int val;
109 110
110 val = readl(&fuse->tester4); 111 val = readl(&fuse->tester4);
111 if (val & 1) 112 if (val & 1)
112 return false; 113 return false;
113 else 114 else
114 return true; 115 return true;
115 } 116 }
116 117
117 u32 get_cpu_rev(void) 118 u32 get_cpu_rev(void)
118 { 119 {
119 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) 120 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
120 ANATOP_BASE_ADDR; 121 ANATOP_BASE_ADDR;
121 u32 reg = readl(&ccm_anatop->digprog); 122 u32 reg = readl(&ccm_anatop->digprog);
122 u32 type = (reg >> 16) & 0xff; 123 u32 type = (reg >> 16) & 0xff;
123 124
124 if (!is_mx7d()) 125 if (!is_mx7d())
125 type = MXC_CPU_MX7S; 126 type = MXC_CPU_MX7S;
126 127
127 reg &= 0xff; 128 reg &= 0xff;
128 return (type << 12) | reg; 129 return (type << 12) | reg;
129 } 130 }
130 131
131 #ifdef CONFIG_REVISION_TAG 132 #ifdef CONFIG_REVISION_TAG
132 u32 __weak get_board_rev(void) 133 u32 __weak get_board_rev(void)
133 { 134 {
134 return get_cpu_rev(); 135 return get_cpu_rev();
135 } 136 }
136 #endif 137 #endif
137 138
138 /* enable all periherial can be accessed in nosec mode */ 139 /* enable all periherial can be accessed in nosec mode */
139 static void init_csu(void) 140 static void init_csu(void)
140 { 141 {
141 int i = 0; 142 int i = 0;
142 for (i = 0; i < CSU_NUM_REGS; i++) 143 for (i = 0; i < CSU_NUM_REGS; i++)
143 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4); 144 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
144 } 145 }
145 146
146 static void imx_enet_mdio_fixup(void) 147 static void imx_enet_mdio_fixup(void)
147 { 148 {
148 struct iomuxc_gpr_base_regs *gpr_regs = 149 struct iomuxc_gpr_base_regs *gpr_regs =
149 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 150 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
150 151
151 /* 152 /*
152 * The management data input/output (MDIO) requires open-drain, 153 * The management data input/output (MDIO) requires open-drain,
153 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports 154 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
154 * this feature. So to TO1.1, need to enable open drain by setting 155 * this feature. So to TO1.1, need to enable open drain by setting
155 * bits GPR0[8:7]. 156 * bits GPR0[8:7].
156 */ 157 */
157 158
158 if (soc_rev() >= CHIP_REV_1_1) { 159 if (soc_rev() >= CHIP_REV_1_1) {
159 setbits_le32(&gpr_regs->gpr[0], 160 setbits_le32(&gpr_regs->gpr[0],
160 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); 161 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
161 } 162 }
162 } 163 }
163 164
164 static void set_epdc_qos(void) 165 static void set_epdc_qos(void)
165 { 166 {
166 #define REGS_QOS_BASE QOSC_IPS_BASE_ADDR 167 #define REGS_QOS_BASE QOSC_IPS_BASE_ADDR
167 #define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400) 168 #define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400)
168 #define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00) 169 #define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00)
169 #define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00) 170 #define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00)
170 171
171 writel(0, REGS_QOS_BASE); /* Disable clkgate & soft_reset */ 172 writel(0, REGS_QOS_BASE); /* Disable clkgate & soft_reset */
172 writel(0, REGS_QOS_BASE + 0x60); /* Enable all masters */ 173 writel(0, REGS_QOS_BASE + 0x60); /* Enable all masters */
173 writel(0, REGS_QOS_EPDC); /* Disable clkgate & soft_reset */ 174 writel(0, REGS_QOS_EPDC); /* Disable clkgate & soft_reset */
174 writel(0, REGS_QOS_PXP0); /* Disable clkgate & soft_reset */ 175 writel(0, REGS_QOS_PXP0); /* Disable clkgate & soft_reset */
175 writel(0, REGS_QOS_PXP1); /* Disable clkgate & soft_reset */ 176 writel(0, REGS_QOS_PXP1); /* Disable clkgate & soft_reset */
176 177
177 writel(0x0f020722, REGS_QOS_EPDC + 0xd0); /* WR, init = 7 with red flag */ 178 writel(0x0f020722, REGS_QOS_EPDC + 0xd0); /* WR, init = 7 with red flag */
178 writel(0x0f020722, REGS_QOS_EPDC + 0xe0); /* RD, init = 7 with red flag */ 179 writel(0x0f020722, REGS_QOS_EPDC + 0xe0); /* RD, init = 7 with red flag */
179 180
180 writel(1, REGS_QOS_PXP0); /* OT_CTRL_EN =1 */ 181 writel(1, REGS_QOS_PXP0); /* OT_CTRL_EN =1 */
181 writel(1, REGS_QOS_PXP1); /* OT_CTRL_EN =1 */ 182 writel(1, REGS_QOS_PXP1); /* OT_CTRL_EN =1 */
182 183
183 writel(0x0f020222, REGS_QOS_PXP0 + 0x50); /* WR, init = 2 with red flag */ 184 writel(0x0f020222, REGS_QOS_PXP0 + 0x50); /* WR, init = 2 with red flag */
184 writel(0x0f020222, REGS_QOS_PXP1 + 0x50); /* WR, init = 2 with red flag */ 185 writel(0x0f020222, REGS_QOS_PXP1 + 0x50); /* WR, init = 2 with red flag */
185 writel(0x0f020222, REGS_QOS_PXP0 + 0x60); /* rD, init = 2 with red flag */ 186 writel(0x0f020222, REGS_QOS_PXP0 + 0x60); /* rD, init = 2 with red flag */
186 writel(0x0f020222, REGS_QOS_PXP1 + 0x60); /* rD, init = 2 with red flag */ 187 writel(0x0f020222, REGS_QOS_PXP1 + 0x60); /* rD, init = 2 with red flag */
187 writel(0x0f020422, REGS_QOS_PXP0 + 0x70); /* tOTAL, init = 4 with red flag */ 188 writel(0x0f020422, REGS_QOS_PXP0 + 0x70); /* tOTAL, init = 4 with red flag */
188 writel(0x0f020422, REGS_QOS_PXP1 + 0x70); /* TOTAL, init = 4 with red flag */ 189 writel(0x0f020422, REGS_QOS_PXP1 + 0x70); /* TOTAL, init = 4 with red flag */
189 190
190 writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */ 191 writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */
191 } 192 }
192 193
193 int arch_cpu_init(void) 194 int arch_cpu_init(void)
194 { 195 {
195 init_aips(); 196 init_aips();
196 197
197 init_csu(); 198 init_csu();
198 /* Disable PDE bit of WMCR register */ 199 /* Disable PDE bit of WMCR register */
199 imx_wdog_disable_powerdown(); 200 imx_wdog_disable_powerdown();
200 201
201 imx_enet_mdio_fixup(); 202 imx_enet_mdio_fixup();
202 203
203 set_epdc_qos(); 204 set_epdc_qos();
204 205
205 #ifdef CONFIG_APBH_DMA 206 #ifdef CONFIG_APBH_DMA
206 /* Start APBH DMA */ 207 /* Start APBH DMA */
207 mxs_dma_init(); 208 mxs_dma_init();
208 #endif 209 #endif
209 210
210 #if CONFIG_IS_ENABLED(IMX_RDC) 211 #if CONFIG_IS_ENABLED(IMX_RDC)
211 isolate_resource(); 212 isolate_resource();
212 #endif 213 #endif
213 214
214 return 0; 215 return 0;
215 } 216 }
216 217
217 #ifdef CONFIG_ARCH_MISC_INIT 218 #ifdef CONFIG_ARCH_MISC_INIT
218 int arch_misc_init(void) 219 int arch_misc_init(void)
219 { 220 {
220 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 221 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
221 if (is_mx7d()) 222 if (is_mx7d())
222 env_set("soc", "imx7d"); 223 env_set("soc", "imx7d");
223 else 224 else
224 env_set("soc", "imx7s"); 225 env_set("soc", "imx7s");
225 #endif 226 #endif
226 227
227 #ifdef CONFIG_FSL_CAAM 228 #ifdef CONFIG_FSL_CAAM
228 sec_init(); 229 sec_init();
229 #endif 230 #endif
230 231
231 return 0; 232 return 0;
232 } 233 }
233 #endif 234 #endif
234 235
235 #ifdef CONFIG_SERIAL_TAG 236 #ifdef CONFIG_SERIAL_TAG
236 void get_board_serial(struct tag_serialnr *serialnr) 237 void get_board_serial(struct tag_serialnr *serialnr)
237 { 238 {
238 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 239 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
239 struct fuse_bank *bank = &ocotp->bank[0]; 240 struct fuse_bank *bank = &ocotp->bank[0];
240 struct fuse_bank0_regs *fuse = 241 struct fuse_bank0_regs *fuse =
241 (struct fuse_bank0_regs *)bank->fuse_regs; 242 (struct fuse_bank0_regs *)bank->fuse_regs;
242 243
243 serialnr->low = fuse->tester0; 244 serialnr->low = fuse->tester0;
244 serialnr->high = fuse->tester1; 245 serialnr->high = fuse->tester1;
245 } 246 }
246 #endif 247 #endif
247 248
248 void set_wdog_reset(struct wdog_regs *wdog) 249 void set_wdog_reset(struct wdog_regs *wdog)
249 { 250 {
250 u32 reg = readw(&wdog->wcr); 251 u32 reg = readw(&wdog->wcr);
251 /* 252 /*
252 * Output WDOG_B signal to reset external pmic or POR_B decided by 253 * Output WDOG_B signal to reset external pmic or POR_B decided by
253 * the board desgin. Without external reset, the peripherals/DDR/ 254 * the board desgin. Without external reset, the peripherals/DDR/
254 * PMIC are not reset, that may cause system working abnormal. 255 * PMIC are not reset, that may cause system working abnormal.
255 */ 256 */
256 reg = readw(&wdog->wcr); 257 reg = readw(&wdog->wcr);
257 reg |= 1 << 3; 258 reg |= 1 << 3;
258 /* 259 /*
259 * WDZST bit is write-once only bit. Align this bit in kernel, 260 * WDZST bit is write-once only bit. Align this bit in kernel,
260 * otherwise kernel code will have no chance to set this bit. 261 * otherwise kernel code will have no chance to set this bit.
261 */ 262 */
262 reg |= 1 << 0; 263 reg |= 1 << 0;
263 writew(reg, &wdog->wcr); 264 writew(reg, &wdog->wcr);
264 } 265 }
265 266
266 /* 267 /*
267 * cfg_val will be used for 268 * cfg_val will be used for
268 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] 269 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
269 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] 270 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
270 * to SBMR1, which will determine the boot device. 271 * to SBMR1, which will determine the boot device.
271 */ 272 */
272 const struct boot_mode soc_boot_modes[] = { 273 const struct boot_mode soc_boot_modes[] = {
273 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)}, 274 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
274 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)}, 275 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
275 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)}, 276 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
276 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)}, 277 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
277 278
278 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)}, 279 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
279 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)}, 280 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
280 /* 4 bit bus width */ 281 /* 4 bit bus width */
281 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 282 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
282 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)}, 283 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
283 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)}, 284 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
284 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)}, 285 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
285 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)}, 286 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
286 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)}, 287 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
287 {NULL, 0}, 288 {NULL, 0},
288 }; 289 };
289 290
290 void s_init(void) 291 void s_init(void)
291 { 292 {
292 /* clock configuration. */ 293 /* clock configuration. */
293 clock_init(); 294 clock_init();
294 295
295 return; 296 return;
296 } 297 }
297 298
298 void reset_misc(void) 299 void reset_misc(void)
299 { 300 {
300 #ifdef CONFIG_VIDEO_MXS 301 #ifdef CONFIG_VIDEO_MXS
301 lcdif_power_down(); 302 lcdif_power_down();
302 #endif 303 #endif
304 }
305
306 void reset_cpu(ulong addr)
307 {
308 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
309
310 /* Clear WDA to trigger WDOG_B immediately */
311 writew((WCR_WDE | WCR_SRS), &wdog->wcr);
312
313 while (1) {
314 /*
315 * spin for .5 seconds before reset
316 */
317 }
303 } 318 }
304 319