Commit cdf3eec481bc889feed3356a7d3a2f0be62c18a7
1 parent
c3c6fd4176
Exists in
v2017.01-smarct4x
Fixed SPI Boot will stop problem.
Showing 8 changed files with 17 additions and 24 deletions Inline Diff
- arch/arm/dts/am437x-smarct437x.dts
- arch/arm/mach-omap2/am33xx/board.c
- board/embedian/smarct437x/board.c
- configs/smarct437x_evm_spi_uart0_defconfig
- configs/smarct437x_evm_spi_uart1_defconfig
- configs/smarct437x_evm_spi_uart2_defconfig
- configs/smarct437x_evm_spi_uart3_defconfig
- include/configs/smarct437x_evm.h
arch/arm/dts/am437x-smarct437x.dts
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* AM437x SK EVM */ | 9 | /* AM437x SK EVM */ |
| 10 | 10 | ||
| 11 | /dts-v1/; | 11 | /dts-v1/; |
| 12 | 12 | ||
| 13 | #include "am4372.dtsi" | 13 | #include "am4372.dtsi" |
| 14 | #include <dt-bindings/pinctrl/am43xx.h> | 14 | #include <dt-bindings/pinctrl/am43xx.h> |
| 15 | #include <dt-bindings/pwm/pwm.h> | 15 | #include <dt-bindings/pwm/pwm.h> |
| 16 | #include <dt-bindings/gpio/gpio.h> | 16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/input/input.h> | 17 | #include <dt-bindings/input/input.h> |
| 18 | 18 | ||
| 19 | / { | 19 | / { |
| 20 | model = "TI AM437x SMARCT437X"; | 20 | model = "TI AM437x SMARCT437X"; |
| 21 | compatible = "ti,am437x-smarct437x","ti,am4372","ti,am43"; | 21 | compatible = "ti,am437x-smarct437x","ti,am4372","ti,am43"; |
| 22 | 22 | ||
| 23 | aliases { | 23 | aliases { |
| 24 | display0 = &lcd0; | 24 | display0 = &lcd0; |
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | chosen { | 27 | chosen { |
| 28 | tick-timer = &timer2; | 28 | tick-timer = &timer2; |
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | vmmcwl_fixed: fixedregulator-mmcwl { | 31 | vmmcwl_fixed: fixedregulator-mmcwl { |
| 32 | compatible = "regulator-fixed"; | 32 | compatible = "regulator-fixed"; |
| 33 | regulator-name = "vmmcwl_fixed"; | 33 | regulator-name = "vmmcwl_fixed"; |
| 34 | regulator-min-microvolt = <1800000>; | 34 | regulator-min-microvolt = <1800000>; |
| 35 | regulator-max-microvolt = <1800000>; | 35 | regulator-max-microvolt = <1800000>; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | backlight { | 38 | backlight { |
| 39 | compatible = "pwm-backlight"; | 39 | compatible = "pwm-backlight"; |
| 40 | enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/ | 40 | enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/ |
| 41 | pwms = <&ehrpwm0 1 250000 PWM_POLARITY_INVERTED>; | 41 | pwms = <&ehrpwm0 1 250000 PWM_POLARITY_INVERTED>; |
| 42 | brightness-levels = <0 51 53 56 62 75 128 212 255>; | 42 | brightness-levels = <0 51 53 56 62 75 128 212 255>; |
| 43 | default-brightness-level = <7>; /* 7 is the brightest */ | 43 | default-brightness-level = <7>; /* 7 is the brightest */ |
| 44 | }; | 44 | }; |
| 45 | 45 | ||
| 46 | sound: sound@0 { | 46 | sound: sound@0 { |
| 47 | compatible = "simple-audio-card"; | 47 | compatible = "simple-audio-card"; |
| 48 | simple-audio-card,name = "SMARCT437X SOUND CARD"; | 48 | simple-audio-card,name = "SMARCT437X SOUND CARD"; |
| 49 | simple-audio-card,widgets = | 49 | simple-audio-card,widgets = |
| 50 | "Headphone", "Headphone Jack", | 50 | "Headphone", "Headphone Jack", |
| 51 | "Line", "Line In"; | 51 | "Line", "Line In"; |
| 52 | simple-audio-card,routing = | 52 | simple-audio-card,routing = |
| 53 | "Headphone Jack", "HPLOUT", | 53 | "Headphone Jack", "HPLOUT", |
| 54 | "Headphone Jack", "HPROUT", | 54 | "Headphone Jack", "HPROUT", |
| 55 | "LINE1L", "Line In", | 55 | "LINE1L", "Line In", |
| 56 | "LINE1R", "Line In"; | 56 | "LINE1R", "Line In"; |
| 57 | simple-audio-card,format = "dsp_b"; | 57 | simple-audio-card,format = "dsp_b"; |
| 58 | simple-audio-card,bitclock-master = <&sound_master>; | 58 | simple-audio-card,bitclock-master = <&sound_master>; |
| 59 | simple-audio-card,frame-master = <&sound_master>; | 59 | simple-audio-card,frame-master = <&sound_master>; |
| 60 | simple-audio-card,bitclock-inversion; | 60 | simple-audio-card,bitclock-inversion; |
| 61 | 61 | ||
| 62 | simple-audio-card,cpu { | 62 | simple-audio-card,cpu { |
| 63 | sound-dai = <&mcasp1>; | 63 | sound-dai = <&mcasp1>; |
| 64 | system-clock-frequency = <12000000>; | 64 | system-clock-frequency = <12000000>; |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | /* For TI TLV320AIC3106 Audio Codec */ | 67 | /* For TI TLV320AIC3106 Audio Codec */ |
| 68 | /*sound_master: simple-audio-card,codec { | 68 | /*sound_master: simple-audio-card,codec { |
| 69 | sound-dai = <&tlv320aic3106>; | 69 | sound-dai = <&tlv320aic3106>; |
| 70 | system-clock-frequency = <24576000>;*/ | 70 | system-clock-frequency = <24576000>;*/ |
| 71 | 71 | ||
| 72 | /* For Freescale SGTL5000 Audio Codec */ | 72 | /* For Freescale SGTL5000 Audio Codec */ |
| 73 | sound_master: simple-audio-card,codec { | 73 | sound_master: simple-audio-card,codec { |
| 74 | sound-dai = <&sgtl5000>; | 74 | sound-dai = <&sgtl5000>; |
| 75 | system-clock-frequency = <24000000>; | 75 | system-clock-frequency = <24000000>; |
| 76 | }; | 76 | }; |
| 77 | }; | 77 | }; |
| 78 | 78 | ||
| 79 | audio_mstrclk: mclk_osc { | 79 | audio_mstrclk: mclk_osc { |
| 80 | compatible = "fixed-clock"; | 80 | compatible = "fixed-clock"; |
| 81 | #clock-cells = <0>; | 81 | #clock-cells = <0>; |
| 82 | clock-frequency = <24000000>; | 82 | clock-frequency = <24000000>; |
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | lcd0: display { | 85 | lcd0: display { |
| 86 | compatible = "primeview,pm070wl4", "panel-dpi"; | 86 | compatible = "primeview,pm070wl4", "panel-dpi"; |
| 87 | label = "lcd"; | 87 | label = "lcd"; |
| 88 | 88 | ||
| 89 | pinctrl-names = "default"; | 89 | pinctrl-names = "default"; |
| 90 | pinctrl-0 = <&lcd_pins>; | 90 | pinctrl-0 = <&lcd_pins>; |
| 91 | 91 | ||
| 92 | enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; | 92 | enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; |
| 93 | 93 | ||
| 94 | panel-timing { | 94 | panel-timing { |
| 95 | clock-frequency = <32000000>; | 95 | clock-frequency = <32000000>; |
| 96 | hactive = <800>; | 96 | hactive = <800>; |
| 97 | vactive = <480>; | 97 | vactive = <480>; |
| 98 | hfront-porch = <42>; | 98 | hfront-porch = <42>; |
| 99 | hback-porch = <84>; | 99 | hback-porch = <84>; |
| 100 | hsync-len = <128>; | 100 | hsync-len = <128>; |
| 101 | vback-porch = <33>; | 101 | vback-porch = <33>; |
| 102 | vfront-porch = <10>; | 102 | vfront-porch = <10>; |
| 103 | vsync-len = <2>; | 103 | vsync-len = <2>; |
| 104 | hsync-active = <0>; | 104 | hsync-active = <0>; |
| 105 | vsync-active = <0>; | 105 | vsync-active = <0>; |
| 106 | de-active = <1>; | 106 | de-active = <1>; |
| 107 | pixelclk-active = <1>; | 107 | pixelclk-active = <1>; |
| 108 | }; | 108 | }; |
| 109 | 109 | ||
| 110 | port { | 110 | port { |
| 111 | lcd_in: endpoint { | 111 | lcd_in: endpoint { |
| 112 | remote-endpoint = <&dpi_out>; | 112 | remote-endpoint = <&dpi_out>; |
| 113 | }; | 113 | }; |
| 114 | }; | 114 | }; |
| 115 | }; | 115 | }; |
| 116 | }; | 116 | }; |
| 117 | 117 | ||
| 118 | &am43xx_pinmux { | 118 | &am43xx_pinmux { |
| 119 | pinctrl-names = "default"; | 119 | pinctrl-names = "default"; |
| 120 | pinctrl-0 = <&clkout1_pin &clkout2_pin &gpio_pins_default &wdt_time_out_pins_default &debugss_pins>; | 120 | pinctrl-0 = <&clkout1_pin &clkout2_pin &gpio_pins_default &wdt_time_out_pins_default &debugss_pins>; |
| 121 | 121 | ||
| 122 | i2c0_pins: i2c0_pins { | 122 | i2c0_pins: i2c0_pins { |
| 123 | pinctrl-single,pins = < | 123 | pinctrl-single,pins = < |
| 124 | 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | 124 | 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 125 | 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | 125 | 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| 126 | >; | 126 | >; |
| 127 | }; | 127 | }; |
| 128 | 128 | ||
| 129 | i2c1_pins: i2c1_pins { | 129 | i2c1_pins: i2c1_pins { |
| 130 | pinctrl-single,pins = < | 130 | pinctrl-single,pins = < |
| 131 | 0x110 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_rxerr.i2c1_scl */ | 131 | 0x110 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_rxerr.i2c1_scl */ |
| 132 | 0x10c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_crs.i2c1_sda */ | 132 | 0x10c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_crs.i2c1_sda */ |
| 133 | >; | 133 | >; |
| 134 | }; | 134 | }; |
| 135 | 135 | ||
| 136 | i2c2_pins: i2c2_pins { | 136 | i2c2_pins: i2c2_pins { |
| 137 | pinctrl-single,pins = < | 137 | pinctrl-single,pins = < |
| 138 | 0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ | 138 | 0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ |
| 139 | 0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ | 139 | 0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ |
| 140 | >; | 140 | >; |
| 141 | }; | 141 | }; |
| 142 | 142 | ||
| 143 | mmc1_pins: pinmux_mmc1_pins { | 143 | mmc1_pins: pinmux_mmc1_pins { |
| 144 | pinctrl-single,pins = < | 144 | pinctrl-single,pins = < |
| 145 | 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ | 145 | 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ |
| 146 | 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ | 146 | 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ |
| 147 | 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ | 147 | 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ |
| 148 | 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ | 148 | 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ |
| 149 | 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ | 149 | 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ |
| 150 | 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ | 150 | 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ |
| 151 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | 151 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
| 152 | >; | 152 | >; |
| 153 | }; | 153 | }; |
| 154 | 154 | ||
| 155 | emmc_pins: pinmux_emmc_pins { | 155 | emmc_pins: pinmux_emmc_pins { |
| 156 | pinctrl-single,pins = < | 156 | pinctrl-single,pins = < |
| 157 | 0x80 (PIN_INPUT | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ | 157 | 0x80 (PIN_INPUT | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ |
| 158 | 0x84 (PIN_INPUT | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ | 158 | 0x84 (PIN_INPUT | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ |
| 159 | 0x00 (PIN_INPUT | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ | 159 | 0x00 (PIN_INPUT | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ |
| 160 | 0x04 (PIN_INPUT | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ | 160 | 0x04 (PIN_INPUT | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ |
| 161 | 0x08 (PIN_INPUT | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ | 161 | 0x08 (PIN_INPUT | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ |
| 162 | 0x0c (PIN_INPUT | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ | 162 | 0x0c (PIN_INPUT | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ |
| 163 | 0x10 (PIN_INPUT | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ | 163 | 0x10 (PIN_INPUT | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ |
| 164 | 0x14 (PIN_INPUT | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ | 164 | 0x14 (PIN_INPUT | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ |
| 165 | 0x18 (PIN_INPUT | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ | 165 | 0x18 (PIN_INPUT | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ |
| 166 | 0x1c (PIN_INPUT | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ | 166 | 0x1c (PIN_INPUT | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ |
| 167 | >; | 167 | >; |
| 168 | }; | 168 | }; |
| 169 | 169 | ||
| 170 | sdmmc_pins: pinmux_sdmmc_pins { | 170 | sdmmc_pins: pinmux_sdmmc_pins { |
| 171 | pinctrl-single,pins = < | 171 | pinctrl-single,pins = < |
| 172 | 0x8c (PIN_INPUT | MUX_MODE3) /* gpmc_clk.mmc2_clk */ | 172 | 0x8c (PIN_INPUT | MUX_MODE3) /* gpmc_clk.mmc2_clk */ |
| 173 | 0x88 (PIN_INPUT | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ | 173 | 0x88 (PIN_INPUT | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ |
| 174 | 0x30 (PIN_INPUT | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ | 174 | 0x30 (PIN_INPUT | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ |
| 175 | 0x34 (PIN_INPUT | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ | 175 | 0x34 (PIN_INPUT | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ |
| 176 | 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ | 176 | 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ |
| 177 | 0x3c (PIN_INPUT | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ | 177 | 0x3c (PIN_INPUT | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ |
| 178 | 0x20 (PIN_INPUT | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ | 178 | 0x20 (PIN_INPUT | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ |
| 179 | 0x24 (PIN_INPUT | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ | 179 | 0x24 (PIN_INPUT | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ |
| 180 | 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ | 180 | 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ |
| 181 | 0x2c (PIN_INPUT | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ | 181 | 0x2c (PIN_INPUT | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ |
| 182 | >; | 182 | >; |
| 183 | }; | 183 | }; |
| 184 | 184 | ||
| 185 | ehrpwm0b_pins: backlight_pins { | 185 | ehrpwm0b_pins: backlight_pins { |
| 186 | pinctrl-single,pins = < | 186 | pinctrl-single,pins = < |
| 187 | 0x1d8 (PIN_OUTPUT | MUX_MODE6) /* cam1_vd.ehrpwm0B */ | 187 | 0x1d8 (PIN_OUTPUT | MUX_MODE6) /* cam1_vd.ehrpwm0B */ |
| 188 | >; | 188 | >; |
| 189 | }; | 189 | }; |
| 190 | 190 | ||
| 191 | clkout1_pin: pinmux_clkout1_pin { | 191 | clkout1_pin: pinmux_clkout1_pin { |
| 192 | pinctrl-single,pins = < | 192 | pinctrl-single,pins = < |
| 193 | 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ | 193 | 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ |
| 194 | >; | 194 | >; |
| 195 | }; | 195 | }; |
| 196 | 196 | ||
| 197 | clkout2_pin: pinmux_clkout2_pin { | 197 | clkout2_pin: pinmux_clkout2_pin { |
| 198 | pinctrl-single,pins = < | 198 | pinctrl-single,pins = < |
| 199 | 0x274 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR1/CLKOUT2 */ | 199 | 0x274 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR1/CLKOUT2 */ |
| 200 | >; | 200 | >; |
| 201 | }; | 201 | }; |
| 202 | 202 | ||
| 203 | dcan0_default: dcan0_default_pins { | 203 | dcan0_default: dcan0_default_pins { |
| 204 | pinctrl-single,pins = < | 204 | pinctrl-single,pins = < |
| 205 | 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.dcan0_rx */ | 205 | 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.dcan0_rx */ |
| 206 | 0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.dcan0_tx */ | 206 | 0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.dcan0_tx */ |
| 207 | >; | 207 | >; |
| 208 | }; | 208 | }; |
| 209 | 209 | ||
| 210 | dcan1_default: dcan1_default_pins { | 210 | dcan1_default: dcan1_default_pins { |
| 211 | pinctrl-single,pins = < | 211 | pinctrl-single,pins = < |
| 212 | 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.dcan1_rx */ | 212 | 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.dcan1_rx */ |
| 213 | 0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.dcan1_tx */ | 213 | 0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.dcan1_tx */ |
| 214 | >; | 214 | >; |
| 215 | }; | 215 | }; |
| 216 | 216 | ||
| 217 | uart0_pins: pinmux_uart0_pins { | 217 | uart0_pins: pinmux_uart0_pins { |
| 218 | pinctrl-single,pins = < | 218 | pinctrl-single,pins = < |
| 219 | 0x168 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ | 219 | 0x168 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ |
| 220 | 0x16c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ | 220 | 0x16c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ |
| 221 | 0x170 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | 221 | 0x170 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
| 222 | 0x174 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ | 222 | 0x174 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
| 223 | >; | 223 | >; |
| 224 | }; | 224 | }; |
| 225 | 225 | ||
| 226 | uart0_pins_sleep: pinmux_uart0_pins_sleep { | 226 | uart0_pins_sleep: pinmux_uart0_pins_sleep { |
| 227 | pinctrl-single,pins = < | 227 | pinctrl-single,pins = < |
| 228 | 0x168 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 228 | 0x168 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 229 | 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 229 | 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 230 | 0x170 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 230 | 0x170 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 231 | 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 231 | 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 232 | >; | 232 | >; |
| 233 | }; | 233 | }; |
| 234 | 234 | ||
| 235 | uart3_pins: pinmux_uart3_pins { | 235 | uart3_pins: pinmux_uart3_pins { |
| 236 | pinctrl-single,pins = < | 236 | pinctrl-single,pins = < |
| 237 | 0x228 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_rxd.uart3_rxd */ | 237 | 0x228 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_rxd.uart3_rxd */ |
| 238 | 0x22c (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_txd.uart3_txd */ | 238 | 0x22c (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_txd.uart3_txd */ |
| 239 | >; | 239 | >; |
| 240 | }; | 240 | }; |
| 241 | 241 | ||
| 242 | uart3_pins_sleep: pinmux_uart3_pins_sleep { | 242 | uart3_pins_sleep: pinmux_uart3_pins_sleep { |
| 243 | pinctrl-single,pins = < | 243 | pinctrl-single,pins = < |
| 244 | 0x228 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 244 | 0x228 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 245 | 0x22c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 245 | 0x22c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 246 | >; | 246 | >; |
| 247 | }; | 247 | }; |
| 248 | 248 | ||
| 249 | uart2_pins: pinmux_uart2_pins { | 249 | uart2_pins: pinmux_uart2_pins { |
| 250 | pinctrl-single,pins = < | 250 | pinctrl-single,pins = < |
| 251 | 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data6.uart2_ctsn */ | 251 | 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data6.uart2_ctsn */ |
| 252 | 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data7_rtsn.uart2_rtsn */ | 252 | 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data7_rtsn.uart2_rtsn */ |
| 253 | 0x1f8 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data4_uart2rxd */ | 253 | 0x1f8 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data4_uart2rxd */ |
| 254 | 0x1fc (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data5.uart2_txd */ | 254 | 0x1fc (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data5.uart2_txd */ |
| 255 | >; | 255 | >; |
| 256 | }; | 256 | }; |
| 257 | 257 | ||
| 258 | uart2_pins_sleep: pinmux_uart2_pins_sleep { | 258 | uart2_pins_sleep: pinmux_uart2_pins_sleep { |
| 259 | pinctrl-single,pins = < | 259 | pinctrl-single,pins = < |
| 260 | 0x200 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 260 | 0x200 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 261 | 0x204 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 261 | 0x204 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 262 | 0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 262 | 0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 263 | 0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7) | 263 | 0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 264 | >; | 264 | >; |
| 265 | }; | 265 | }; |
| 266 | 266 | ||
| 267 | uart4_pins: pinmux_uart4_pins { | 267 | uart4_pins: pinmux_uart4_pins { |
| 268 | pinctrl-single,pins = < | 268 | pinctrl-single,pins = < |
| 269 | 0x070 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ | 269 | 0x070 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ |
| 270 | 0x074 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ | 270 | 0x074 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ |
| 271 | >; | 271 | >; |
| 272 | }; | 272 | }; |
| 273 | 273 | ||
| 274 | uart4_pins_sleep: pinmux_uart4_pins_sleep { | 274 | uart4_pins_sleep: pinmux_uart4_pins_sleep { |
| 275 | pinctrl-single,pins = < | 275 | pinctrl-single,pins = < |
| 276 | 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 276 | 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 277 | 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 277 | 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 278 | >; | 278 | >; |
| 279 | }; | 279 | }; |
| 280 | 280 | ||
| 281 | /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/ | 281 | /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/ |
| 282 | gpio_pins_default: pinmux_gpio_pin { | 282 | gpio_pins_default: pinmux_gpio_pin { |
| 283 | pinctrl-single,pins = < | 283 | pinctrl-single,pins = < |
| 284 | 0x26c (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_cs0.gpio0_23 */ | 284 | 0x26c (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_cs0.gpio0_23 */ |
| 285 | 0x264 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d0.gpio0_20 */ | 285 | 0x264 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d0.gpio0_20 */ |
| 286 | 0x268 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d1.gpio0_21 */ | 286 | 0x268 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d1.gpio0_21 */ |
| 287 | 0x260 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_sclk.gpio0_22 */ | 287 | 0x260 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_sclk.gpio0_22 */ |
| 288 | 0x21c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data5.gpio4_27 */ | 288 | 0x21c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data5.gpio4_27 */ |
| 289 | 0x224 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data7.gpio4_29 */ | 289 | 0x224 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data7.gpio4_29 */ |
| 290 | 0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ | 290 | 0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ |
| 291 | 0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0.gpio3_16 */ | 291 | 0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0.gpio3_16 */ |
| 292 | 0x210 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data2.gpio4_24 */ | 292 | 0x210 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data2.gpio4_24 */ |
| 293 | 0x214 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data3.gpio4_25 */ | 293 | 0x214 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data3.gpio4_25 */ |
| 294 | 0x218 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data4.gpio4_26 */ | 294 | 0x218 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data4.gpio4_26 */ |
| 295 | 0x220 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data6.gpio4_28 */ | 295 | 0x220 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data6.gpio4_28 */ |
| 296 | >; | 296 | >; |
| 297 | }; | 297 | }; |
| 298 | 298 | ||
| 299 | wdt_time_out_pins_default: pinmux_wdt_time_out_pin { | 299 | wdt_time_out_pins_default: pinmux_wdt_time_out_pin { |
| 300 | pinctrl-single,pins = < | 300 | pinctrl-single,pins = < |
| 301 | 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* uart3_rtsn.ehrpwm5B */ | 301 | 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* uart3_rtsn.ehrpwm5B */ |
| 302 | >; | 302 | >; |
| 303 | }; | 303 | }; |
| 304 | 304 | ||
| 305 | cpsw_default: cpsw_default { | 305 | cpsw_default: cpsw_default { |
| 306 | pinctrl-single,pins = < | 306 | pinctrl-single,pins = < |
| 307 | /* Slave 1 */ | 307 | /* Slave 1 */ |
| 308 | 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ | 308 | 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ |
| 309 | 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ | 309 | 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ |
| 310 | 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ | 310 | 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ |
| 311 | 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ | 311 | 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ |
| 312 | 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ | 312 | 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ |
| 313 | 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ | 313 | 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ |
| 314 | 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ | 314 | 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ |
| 315 | 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ | 315 | 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ |
| 316 | 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ | 316 | 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ |
| 317 | 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ | 317 | 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ |
| 318 | 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ | 318 | 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ |
| 319 | 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ | 319 | 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ |
| 320 | 320 | ||
| 321 | /* Slave 2 */ | 321 | /* Slave 2 */ |
| 322 | 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ | 322 | 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ |
| 323 | 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ | 323 | 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ |
| 324 | 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ | 324 | 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ |
| 325 | 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ | 325 | 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ |
| 326 | 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ | 326 | 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ |
| 327 | 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ | 327 | 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ |
| 328 | 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ | 328 | 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ |
| 329 | 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ | 329 | 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ |
| 330 | 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ | 330 | 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ |
| 331 | 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ | 331 | 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ |
| 332 | 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ | 332 | 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ |
| 333 | 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ | 333 | 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ |
| 334 | >; | 334 | >; |
| 335 | }; | 335 | }; |
| 336 | 336 | ||
| 337 | cpsw_sleep: cpsw_sleep { | 337 | cpsw_sleep: cpsw_sleep { |
| 338 | pinctrl-single,pins = < | 338 | pinctrl-single,pins = < |
| 339 | /* Slave 1 reset value */ | 339 | /* Slave 1 reset value */ |
| 340 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 340 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 341 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 341 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 342 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 342 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 343 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 343 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 344 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 344 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 345 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 345 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 346 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 346 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 347 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 347 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 348 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 348 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 349 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 349 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 350 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 350 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 351 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 351 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 352 | 352 | ||
| 353 | /* Slave 2 reset value */ | 353 | /* Slave 2 reset value */ |
| 354 | 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 354 | 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 355 | 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 355 | 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 356 | 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 356 | 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 357 | 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 357 | 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 358 | 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 358 | 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 359 | 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 359 | 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 360 | 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 360 | 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 361 | 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 361 | 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 362 | 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 362 | 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 363 | 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 363 | 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 364 | 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 364 | 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 365 | 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 365 | 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 366 | >; | 366 | >; |
| 367 | }; | 367 | }; |
| 368 | 368 | ||
| 369 | davinci_mdio_default: davinci_mdio_default { | 369 | davinci_mdio_default: davinci_mdio_default { |
| 370 | pinctrl-single,pins = < | 370 | pinctrl-single,pins = < |
| 371 | /* MDIO */ | 371 | /* MDIO */ |
| 372 | 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | 372 | 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 373 | 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ | 373 | 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| 374 | >; | 374 | >; |
| 375 | }; | 375 | }; |
| 376 | 376 | ||
| 377 | davinci_mdio_sleep: davinci_mdio_sleep { | 377 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 378 | pinctrl-single,pins = < | 378 | pinctrl-single,pins = < |
| 379 | /* MDIO reset value */ | 379 | /* MDIO reset value */ |
| 380 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 380 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 381 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 381 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 382 | >; | 382 | >; |
| 383 | }; | 383 | }; |
| 384 | 384 | ||
| 385 | dss_pins: dss_pins { | 385 | dss_pins: dss_pins { |
| 386 | pinctrl-single,pins = < | 386 | pinctrl-single,pins = < |
| 387 | 0x1b0 (PIN_OUTPUT | MUX_MODE2) /* cam0_hd.dss_data23 */ | 387 | 0x1b0 (PIN_OUTPUT | MUX_MODE2) /* cam0_hd.dss_data23 */ |
| 388 | 0x1b4 (PIN_OUTPUT | MUX_MODE2) /* cam0_vd.dss_data22 */ | 388 | 0x1b4 (PIN_OUTPUT | MUX_MODE2) /* cam0_vd.dss_data22 */ |
| 389 | 0x1b8 (PIN_OUTPUT | MUX_MODE2) /* cam0_field.dss_data21 */ | 389 | 0x1b8 (PIN_OUTPUT | MUX_MODE2) /* cam0_field.dss_data21 */ |
| 390 | 0x1bc (PIN_OUTPUT | MUX_MODE2) /* cam0_wen.dss_data20 */ | 390 | 0x1bc (PIN_OUTPUT | MUX_MODE2) /* cam0_wen.dss_data20 */ |
| 391 | 0x1c0 (PIN_OUTPUT | MUX_MODE2) /* cam0_pclk.dss_data19 */ | 391 | 0x1c0 (PIN_OUTPUT | MUX_MODE2) /* cam0_pclk.dss_data19 */ |
| 392 | 0x1c4 (PIN_OUTPUT | MUX_MODE2) /* cam0_data8.dss_data18 */ | 392 | 0x1c4 (PIN_OUTPUT | MUX_MODE2) /* cam0_data8.dss_data18 */ |
| 393 | 0x1c8 (PIN_OUTPUT | MUX_MODE2) /* cam0_data9.dss_data17 */ | 393 | 0x1c8 (PIN_OUTPUT | MUX_MODE2) /* cam0_data9.dss_data17 */ |
| 394 | 0x1cc (PIN_OUTPUT | MUX_MODE2) /* cam1_data9.dss_data16 */ | 394 | 0x1cc (PIN_OUTPUT | MUX_MODE2) /* cam1_data9.dss_data16 */ |
| 395 | 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ | 395 | 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ |
| 396 | 0x0a4 (PIN_OUTPUT | MUX_MODE0) | 396 | 0x0a4 (PIN_OUTPUT | MUX_MODE0) |
| 397 | 0x0a8 (PIN_OUTPUT | MUX_MODE0) | 397 | 0x0a8 (PIN_OUTPUT | MUX_MODE0) |
| 398 | 0x0ac (PIN_OUTPUT | MUX_MODE0) | 398 | 0x0ac (PIN_OUTPUT | MUX_MODE0) |
| 399 | 0x0b0 (PIN_OUTPUT | MUX_MODE0) | 399 | 0x0b0 (PIN_OUTPUT | MUX_MODE0) |
| 400 | 0x0b4 (PIN_OUTPUT | MUX_MODE0) | 400 | 0x0b4 (PIN_OUTPUT | MUX_MODE0) |
| 401 | 0x0b8 (PIN_OUTPUT | MUX_MODE0) | 401 | 0x0b8 (PIN_OUTPUT | MUX_MODE0) |
| 402 | 0x0bc (PIN_OUTPUT | MUX_MODE0) | 402 | 0x0bc (PIN_OUTPUT | MUX_MODE0) |
| 403 | 0x0c0 (PIN_OUTPUT | MUX_MODE0) | 403 | 0x0c0 (PIN_OUTPUT | MUX_MODE0) |
| 404 | 0x0c4 (PIN_OUTPUT | MUX_MODE0) | 404 | 0x0c4 (PIN_OUTPUT | MUX_MODE0) |
| 405 | 0x0c8 (PIN_OUTPUT | MUX_MODE0) | 405 | 0x0c8 (PIN_OUTPUT | MUX_MODE0) |
| 406 | 0x0cc (PIN_OUTPUT | MUX_MODE0) | 406 | 0x0cc (PIN_OUTPUT | MUX_MODE0) |
| 407 | 0x0d0 (PIN_OUTPUT | MUX_MODE0) | 407 | 0x0d0 (PIN_OUTPUT | MUX_MODE0) |
| 408 | 0x0d4 (PIN_OUTPUT | MUX_MODE0) | 408 | 0x0d4 (PIN_OUTPUT | MUX_MODE0) |
| 409 | 0x0d8 (PIN_OUTPUT | MUX_MODE0) | 409 | 0x0d8 (PIN_OUTPUT | MUX_MODE0) |
| 410 | 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ | 410 | 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ |
| 411 | 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ | 411 | 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ |
| 412 | 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ | 412 | 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ |
| 413 | 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ | 413 | 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ |
| 414 | 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ | 414 | 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ |
| 415 | 415 | ||
| 416 | >; | 416 | >; |
| 417 | }; | 417 | }; |
| 418 | 418 | ||
| 419 | /* SPI_NOR Pins */ | 419 | /* SPI_NOR Pins */ |
| 420 | spi0_pins: spi0_pins { | 420 | spi0_pins: spi0_pins { |
| 421 | pinctrl-single,pins = < | 421 | pinctrl-single,pins = < |
| 422 | 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ | 422 | 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ |
| 423 | 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ | 423 | 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ |
| 424 | 0x154 (PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ | 424 | 0x154 (PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ |
| 425 | 0x158 (PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ | 425 | 0x158 (PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ |
| 426 | >; | 426 | >; |
| 427 | }; | 427 | }; |
| 428 | 428 | ||
| 429 | /* SPI0 Pins */ | 429 | /* SPI0 Pins */ |
| 430 | spi2_pins: spi2_pins { | 430 | spi2_pins: spi2_pins { |
| 431 | pinctrl-single,pins = < | 431 | pinctrl-single,pins = < |
| 432 | 0x1d4 (PIN_OUTPUT | MUX_MODE4) /* cam1_hd.spi2_cs0 */ | 432 | 0x1d4 (PIN_OUTPUT | MUX_MODE4) /* cam1_hd.spi2_cs0 */ |
| 433 | 0x1e0 (PIN_OUTPUT | MUX_MODE4) /* cam1_field.spi2_cs0 */ | 433 | 0x1e0 (PIN_OUTPUT | MUX_MODE4) /* cam1_field.spi2_cs0 */ |
| 434 | 0x1dc (PIN_INPUT | MUX_MODE4) /* cam1_pclk.spi2_sclk */ | 434 | 0x1dc (PIN_INPUT | MUX_MODE4) /* cam1_pclk.spi2_sclk */ |
| 435 | 0x1d0 (PIN_INPUT | MUX_MODE4) /* cam1_data8.spi2_d0 */ | 435 | 0x1d0 (PIN_INPUT | MUX_MODE4) /* cam1_data8.spi2_d0 */ |
| 436 | 0x1e4 (PIN_OUTPUT | MUX_MODE4) /* cam1_wen.spi2_d1 */ | 436 | 0x1e4 (PIN_OUTPUT | MUX_MODE4) /* cam1_wen.spi2_d1 */ |
| 437 | >; | 437 | >; |
| 438 | }; | 438 | }; |
| 439 | 439 | ||
| 440 | /* SPI1 Pins */ | 440 | /* SPI1 Pins */ |
| 441 | spi4_pins: spi4_pins { | 441 | spi4_pins: spi4_pins { |
| 442 | pinctrl-single,pins = < | 442 | pinctrl-single,pins = < |
| 443 | 0x25c (PIN_OUTPUT | MUX_MODE0) /* spi4_cs0.spi4_cs0 */ | 443 | 0x25c (PIN_OUTPUT | MUX_MODE0) /* spi4_cs0.spi4_cs0 */ |
| 444 | 0x230 (PIN_OUTPUT | MUX_MODE2) /* uart3_cstn.spi4_cs1 */ | 444 | 0x230 (PIN_OUTPUT | MUX_MODE2) /* uart3_cstn.spi4_cs1 */ |
| 445 | 0x250 (PIN_INPUT | MUX_MODE0) /* spi4_sclk.spi4_sclk */ | 445 | 0x250 (PIN_INPUT | MUX_MODE0) /* spi4_sclk.spi4_sclk */ |
| 446 | 0x254 (PIN_INPUT | MUX_MODE0) /* spi4_d0.spi4_d0 */ | 446 | 0x254 (PIN_INPUT | MUX_MODE0) /* spi4_d0.spi4_d0 */ |
| 447 | 0x258 (PIN_OUTPUT | MUX_MODE0) /* spi4_d1.spi4_d1 */ | 447 | 0x258 (PIN_OUTPUT | MUX_MODE0) /* spi4_d1.spi4_d1 */ |
| 448 | >; | 448 | >; |
| 449 | }; | 449 | }; |
| 450 | 450 | ||
| 451 | mcasp1_pins: mcasp1_pins { | 451 | mcasp1_pins: mcasp1_pins { |
| 452 | pinctrl-single,pins = < | 452 | pinctrl-single,pins = < |
| 453 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkr.mcasp1_aclkx */ | 453 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkr.mcasp1_aclkx */ |
| 454 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_fsr.mcasp1_fsx */ | 454 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_fsr.mcasp1_fsx */ |
| 455 | 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */ | 455 | 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */ |
| 456 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_ahclkx.mcasp1_axr1 */ | 456 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_ahclkx.mcasp1_axr1 */ |
| 457 | >; | 457 | >; |
| 458 | }; | 458 | }; |
| 459 | 459 | ||
| 460 | mcasp1_sleep_pins: mcasp1_sleep_pins { | 460 | mcasp1_sleep_pins: mcasp1_sleep_pins { |
| 461 | pinctrl-single,pins = < | 461 | pinctrl-single,pins = < |
| 462 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 462 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 463 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 463 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 464 | 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 464 | 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 465 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) | 465 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 466 | >; | 466 | >; |
| 467 | }; | 467 | }; |
| 468 | 468 | ||
| 469 | lcd_pins: lcd_pins { | 469 | lcd_pins: lcd_pins { |
| 470 | pinctrl-single,pins = < | 470 | pinctrl-single,pins = < |
| 471 | 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_be0n_cle.gpio2_5 */ | 471 | 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_be0n_cle.gpio2_5 */ |
| 472 | >; | 472 | >; |
| 473 | }; | 473 | }; |
| 474 | 474 | ||
| 475 | debugss_pins: pinmux_debugss_pins { | 475 | debugss_pins: pinmux_debugss_pins { |
| 476 | pinctrl-single,pins = < | 476 | pinctrl-single,pins = < |
| 477 | 0x290 (PIN_INPUT_PULLDOWN) | 477 | 0x290 (PIN_INPUT_PULLDOWN) |
| 478 | 0x294 (PIN_INPUT_PULLDOWN) | 478 | 0x294 (PIN_INPUT_PULLDOWN) |
| 479 | 0x298 (PIN_INPUT_PULLDOWN) | 479 | 0x298 (PIN_INPUT_PULLDOWN) |
| 480 | 0x29C (PIN_INPUT_PULLDOWN) | 480 | 0x29C (PIN_INPUT_PULLDOWN) |
| 481 | 0x2A0 (PIN_INPUT_PULLDOWN) | 481 | 0x2A0 (PIN_INPUT_PULLDOWN) |
| 482 | 0x2A4 (PIN_INPUT_PULLDOWN) | 482 | 0x2A4 (PIN_INPUT_PULLDOWN) |
| 483 | 0x2A8 (PIN_INPUT_PULLDOWN) | 483 | 0x2A8 (PIN_INPUT_PULLDOWN) |
| 484 | >; | 484 | >; |
| 485 | }; | 485 | }; |
| 486 | 486 | ||
| 487 | usb1_pins: usb1_pins { | 487 | usb1_pins: usb1_pins { |
| 488 | pinctrl-single,pins = < | 488 | pinctrl-single,pins = < |
| 489 | 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ | 489 | 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ |
| 490 | /* USB0 Over Current */ | 490 | /* USB0 Over Current */ |
| 491 | 0x108 (PIN_INPUT | MUX_MODE9) /* mii1_col.gpio0_0 */ | 491 | 0x108 (PIN_INPUT | MUX_MODE9) /* mii1_col.gpio0_0 */ |
| 492 | >; | 492 | >; |
| 493 | }; | 493 | }; |
| 494 | 494 | ||
| 495 | usb2_pins: usb2_pins { | 495 | usb2_pins: usb2_pins { |
| 496 | pinctrl-single,pins = < | 496 | pinctrl-single,pins = < |
| 497 | 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ | 497 | 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ |
| 498 | /* USB1 Over Current */ | 498 | /* USB1 Over Current */ |
| 499 | 0x078 (PIN_INPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ | 499 | 0x078 (PIN_INPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ |
| 500 | >; | 500 | >; |
| 501 | }; | 501 | }; |
| 502 | }; | 502 | }; |
| 503 | 503 | ||
| 504 | &i2c0 { | 504 | &i2c0 { |
| 505 | status = "okay"; | 505 | status = "okay"; |
| 506 | pinctrl-names = "default"; | 506 | pinctrl-names = "default"; |
| 507 | pinctrl-0 = <&i2c0_pins>; | 507 | pinctrl-0 = <&i2c0_pins>; |
| 508 | clock-frequency = <100000>; | 508 | clock-frequency = <100000>; |
| 509 | }; | 509 | }; |
| 510 | 510 | ||
| 511 | &i2c1 { | 511 | &i2c1 { |
| 512 | status = "okay"; | 512 | status = "okay"; |
| 513 | pinctrl-names = "default"; | 513 | pinctrl-names = "default"; |
| 514 | pinctrl-0 = <&i2c1_pins>; | 514 | pinctrl-0 = <&i2c1_pins>; |
| 515 | clock-frequency = <100000>; | 515 | clock-frequency = <100000>; |
| 516 | 516 | ||
| 517 | tps@24 { | 517 | tps@24 { |
| 518 | compatible = "ti,tps65218"; | 518 | compatible = "ti,tps65218"; |
| 519 | reg = <0x24>; | 519 | reg = <0x24>; |
| 520 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | 520 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 521 | interrupt-controller; | 521 | interrupt-controller; |
| 522 | #interrupt-cells = <2>; | 522 | #interrupt-cells = <2>; |
| 523 | 523 | ||
| 524 | dcdc1: regulator-dcdc1 { | 524 | dcdc1: regulator-dcdc1 { |
| 525 | compatible = "ti,tps65218-dcdc1"; | 525 | compatible = "ti,tps65218-dcdc1"; |
| 526 | /* VDD_CORE limits min of OPP50 and max of OPP100 */ | 526 | /* VDD_CORE limits min of OPP50 and max of OPP100 */ |
| 527 | regulator-name = "vdd_core"; | 527 | regulator-name = "vdd_core"; |
| 528 | regulator-min-microvolt = <912000>; | 528 | regulator-min-microvolt = <912000>; |
| 529 | regulator-max-microvolt = <1144000>; | 529 | regulator-max-microvolt = <1144000>; |
| 530 | regulator-boot-on; | 530 | regulator-boot-on; |
| 531 | regulator-always-on; | 531 | regulator-always-on; |
| 532 | }; | 532 | }; |
| 533 | 533 | ||
| 534 | dcdc2: regulator-dcdc2 { | 534 | dcdc2: regulator-dcdc2 { |
| 535 | compatible = "ti,tps65218-dcdc2"; | 535 | compatible = "ti,tps65218-dcdc2"; |
| 536 | /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ | 536 | /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ |
| 537 | regulator-name = "vdd_mpu"; | 537 | regulator-name = "vdd_mpu"; |
| 538 | regulator-min-microvolt = <912000>; | 538 | regulator-min-microvolt = <912000>; |
| 539 | regulator-max-microvolt = <1378000>; | 539 | regulator-max-microvolt = <1378000>; |
| 540 | regulator-boot-on; | 540 | regulator-boot-on; |
| 541 | regulator-always-on; | 541 | regulator-always-on; |
| 542 | }; | 542 | }; |
| 543 | 543 | ||
| 544 | dcdc3: regulator-dcdc3 { | 544 | dcdc3: regulator-dcdc3 { |
| 545 | compatible = "ti,tps65218-dcdc3"; | 545 | compatible = "ti,tps65218-dcdc3"; |
| 546 | regulator-name = "vdds_ddr"; | 546 | regulator-name = "vdds_ddr"; |
| 547 | regulator-min-microvolt = <1500000>; | 547 | regulator-min-microvolt = <1500000>; |
| 548 | regulator-max-microvolt = <1500000>; | 548 | regulator-max-microvolt = <1500000>; |
| 549 | regulator-boot-on; | 549 | regulator-boot-on; |
| 550 | regulator-always-on; | 550 | regulator-always-on; |
| 551 | regulator-state-mem { | 551 | regulator-state-mem { |
| 552 | regulator-on-in-suspend; | 552 | regulator-on-in-suspend; |
| 553 | }; | 553 | }; |
| 554 | regulator-state-disk { | 554 | regulator-state-disk { |
| 555 | regulator-off-in-suspend; | 555 | regulator-off-in-suspend; |
| 556 | }; | 556 | }; |
| 557 | }; | 557 | }; |
| 558 | 558 | ||
| 559 | dcdc4: regulator-dcdc4 { | 559 | dcdc4: regulator-dcdc4 { |
| 560 | compatible = "ti,tps65218-dcdc4"; | 560 | compatible = "ti,tps65218-dcdc4"; |
| 561 | regulator-name = "v3_3d"; | 561 | regulator-name = "v3_3d"; |
| 562 | regulator-min-microvolt = <3300000>; | 562 | regulator-min-microvolt = <3300000>; |
| 563 | regulator-max-microvolt = <3300000>; | 563 | regulator-max-microvolt = <3300000>; |
| 564 | regulator-boot-on; | 564 | regulator-boot-on; |
| 565 | regulator-always-on; | 565 | regulator-always-on; |
| 566 | }; | 566 | }; |
| 567 | 567 | ||
| 568 | dcdc5: regulator-dcdc5 { | 568 | dcdc5: regulator-dcdc5 { |
| 569 | compatible = "ti,tps65218-dcdc5"; | 569 | compatible = "ti,tps65218-dcdc5"; |
| 570 | regulator-name = "v1_0bat"; | 570 | regulator-name = "v1_0bat"; |
| 571 | regulator-min-microvolt = <1000000>; | 571 | regulator-min-microvolt = <1000000>; |
| 572 | regulator-max-microvolt = <1000000>; | 572 | regulator-max-microvolt = <1000000>; |
| 573 | regulator-boot-on; | 573 | regulator-boot-on; |
| 574 | regulator-always-on; | 574 | regulator-always-on; |
| 575 | regulator-state-mem { | 575 | regulator-state-mem { |
| 576 | regulator-on-in-suspend; | 576 | regulator-on-in-suspend; |
| 577 | }; | 577 | }; |
| 578 | }; | 578 | }; |
| 579 | 579 | ||
| 580 | dcdc6: regulator-dcdc6 { | 580 | dcdc6: regulator-dcdc6 { |
| 581 | compatible = "ti,tps65218-dcdc6"; | 581 | compatible = "ti,tps65218-dcdc6"; |
| 582 | regulator-name = "v1_8bat"; | 582 | regulator-name = "v1_8bat"; |
| 583 | regulator-min-microvolt = <1800000>; | 583 | regulator-min-microvolt = <1800000>; |
| 584 | regulator-max-microvolt = <1800000>; | 584 | regulator-max-microvolt = <1800000>; |
| 585 | regulator-boot-on; | 585 | regulator-boot-on; |
| 586 | regulator-always-on; | 586 | regulator-always-on; |
| 587 | regulator-state-mem { | 587 | regulator-state-mem { |
| 588 | regulator-on-in-suspend; | 588 | regulator-on-in-suspend; |
| 589 | }; | 589 | }; |
| 590 | }; | 590 | }; |
| 591 | 591 | ||
| 592 | ldo1: regulator-ldo1 { | 592 | ldo1: regulator-ldo1 { |
| 593 | compatible = "ti,tps65218-ldo1"; | 593 | compatible = "ti,tps65218-ldo1"; |
| 594 | regulator-name = "v1_8d"; | 594 | regulator-name = "v1_8d"; |
| 595 | regulator-min-microvolt = <1800000>; | 595 | regulator-min-microvolt = <1800000>; |
| 596 | regulator-max-microvolt = <1800000>; | 596 | regulator-max-microvolt = <1800000>; |
| 597 | regulator-boot-on; | 597 | regulator-boot-on; |
| 598 | regulator-always-on; | 598 | regulator-always-on; |
| 599 | }; | 599 | }; |
| 600 | 600 | ||
| 601 | power-button { | 601 | power-button { |
| 602 | compatible = "ti,tps65218-pwrbutton"; | 602 | compatible = "ti,tps65218-pwrbutton"; |
| 603 | status = "okay"; | 603 | status = "okay"; |
| 604 | interrupts = <3 IRQ_TYPE_EDGE_BOTH>; | 604 | interrupts = <3 IRQ_TYPE_EDGE_BOTH>; |
| 605 | }; | 605 | }; |
| 606 | }; | 606 | }; |
| 607 | 607 | ||
| 608 | s35390a: s35390a@30 { | 608 | s35390a: s35390a@30 { |
| 609 | compatible = "s35390a"; | 609 | compatible = "s35390a"; |
| 610 | reg = <0x30>; | 610 | reg = <0x30>; |
| 611 | }; | 611 | }; |
| 612 | 612 | ||
| 613 | at24@50 { | 613 | at24@50 { |
| 614 | compatible = "at24,24c256"; | 614 | compatible = "at24,24c256"; |
| 615 | reg = <0x50>; | 615 | reg = <0x50>; |
| 616 | }; | 616 | }; |
| 617 | 617 | ||
| 618 | at24@57 { | 618 | at24@57 { |
| 619 | compatible = "at24,24c256"; | 619 | compatible = "at24,24c256"; |
| 620 | reg = <0x57>; | 620 | reg = <0x57>; |
| 621 | }; | 621 | }; |
| 622 | 622 | ||
| 623 | /* For TI TLV320AIC3106 Audio Codec */ | 623 | /* For TI TLV320AIC3106 Audio Codec */ |
| 624 | /*tlv320aic3106: tlv320aic3106@1b { | 624 | /*tlv320aic3106: tlv320aic3106@1b { |
| 625 | #sound-dai-cells = <0>; | 625 | #sound-dai-cells = <0>; |
| 626 | compatible = "ti,tlv320aic3106"; | 626 | compatible = "ti,tlv320aic3106"; |
| 627 | reg = <0x1b>; | 627 | reg = <0x1b>; |
| 628 | status = "okay"; | 628 | status = "okay"; |
| 629 | 629 | ||
| 630 | AVDD-supply = <&dcdc4>; | 630 | AVDD-supply = <&dcdc4>; |
| 631 | IOVDD-supply = <&dcdc6>; | 631 | IOVDD-supply = <&dcdc6>; |
| 632 | DRVDD-supply = <&dcdc4>; | 632 | DRVDD-supply = <&dcdc4>; |
| 633 | DVDD-supply = <&ldo1>; | 633 | DVDD-supply = <&ldo1>; |
| 634 | };*/ | 634 | };*/ |
| 635 | 635 | ||
| 636 | /* For Freescale SGTL5000 Audio Codec */ | 636 | /* For Freescale SGTL5000 Audio Codec */ |
| 637 | sgtl5000: sgtl5000@0a { | 637 | sgtl5000: sgtl5000@0a { |
| 638 | #sound-dai-cells = <0>; | 638 | #sound-dai-cells = <0>; |
| 639 | compatible = "fsl,sgtl5000"; | 639 | compatible = "fsl,sgtl5000"; |
| 640 | reg = <0x0a>; | 640 | reg = <0x0a>; |
| 641 | clocks = <&audio_mstrclk>; | 641 | clocks = <&audio_mstrclk>; |
| 642 | VDDA-supply = <&dcdc4>; | 642 | VDDA-supply = <&dcdc4>; |
| 643 | VDDIO-supply = <&dcdc6>; | 643 | VDDIO-supply = <&dcdc6>; |
| 644 | VDDD-supply = <&ldo1>; | 644 | VDDD-supply = <&ldo1>; |
| 645 | }; | 645 | }; |
| 646 | }; | 646 | }; |
| 647 | 647 | ||
| 648 | &i2c2 { | 648 | &i2c2 { |
| 649 | status = "okay"; | 649 | status = "disabled"; |
| 650 | pinctrl-names = "default"; | 650 | pinctrl-names = "default"; |
| 651 | pinctrl-0 = <&i2c2_pins>; | 651 | pinctrl-0 = <&i2c2_pins>; |
| 652 | clock-frequency = <100000>; | 652 | clock-frequency = <100000>; |
| 653 | 653 | ||
| 654 | /* CH7055A Parallel LCD to VGA D-SUB 15 way */ | 654 | /* CH7055A Parallel LCD to VGA D-SUB 15 way */ |
| 655 | eeprom@76 { | 655 | eeprom@76 { |
| 656 | compatible = "at,24c256"; | 656 | compatible = "at,24c256"; |
| 657 | reg = <0x76>; | 657 | reg = <0x76>; |
| 658 | }; | 658 | }; |
| 659 | }; | 659 | }; |
| 660 | 660 | ||
| 661 | 661 | ||
| 662 | &epwmss0 { | 662 | &epwmss0 { |
| 663 | status = "okay"; | 663 | status = "okay"; |
| 664 | 664 | ||
| 665 | ehrpwm0: ehrpwm@48300200 { | 665 | ehrpwm@48300200 { |
| 666 | status = "okay"; | 666 | status = "disabled"; |
| 667 | pinctrl-names = "default"; | 667 | pinctrl-names = "default"; |
| 668 | pinctrl-0 = <&ehrpwm0b_pins>; | 668 | pinctrl-0 = <&ehrpwm0b_pins>; |
| 669 | }; | 669 | }; |
| 670 | }; | 670 | }; |
| 671 | 671 | ||
| 672 | &gpio0 { | 672 | &gpio0 { |
| 673 | status = "okay"; | 673 | status = "okay"; |
| 674 | }; | 674 | }; |
| 675 | 675 | ||
| 676 | &gpio1 { | 676 | &gpio1 { |
| 677 | status = "okay"; | 677 | status = "okay"; |
| 678 | }; | 678 | }; |
| 679 | 679 | ||
| 680 | &gpio2 { | 680 | &gpio2 { |
| 681 | status = "okay"; | 681 | status = "okay"; |
| 682 | }; | 682 | }; |
| 683 | 683 | ||
| 684 | &gpio3 { | 684 | &gpio3 { |
| 685 | status = "okay"; | 685 | status = "okay"; |
| 686 | }; | 686 | }; |
| 687 | 687 | ||
| 688 | &gpio4 { | 688 | &gpio4 { |
| 689 | status = "okay"; | 689 | status = "okay"; |
| 690 | }; | 690 | }; |
| 691 | 691 | ||
| 692 | &gpio5 { | 692 | &gpio5 { |
| 693 | status = "okay"; | 693 | status = "okay"; |
| 694 | }; | 694 | }; |
| 695 | 695 | ||
| 696 | &mmc1 { | 696 | &mmc1 { |
| 697 | status = "okay"; | 697 | status = "okay"; |
| 698 | pinctrl-names = "default"; | 698 | pinctrl-names = "default"; |
| 699 | pinctrl-0 = <&mmc1_pins>; | 699 | pinctrl-0 = <&mmc1_pins>; |
| 700 | 700 | ||
| 701 | vmmc-supply = <&dcdc4>; | 701 | vmmc-supply = <&dcdc4>; |
| 702 | bus-width = <4>; | 702 | bus-width = <4>; |
| 703 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; | 703 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; |
| 704 | }; | 704 | }; |
| 705 | 705 | ||
| 706 | &mmc2 { | 706 | &mmc2 { |
| 707 | pinctrl-names = "default"; | 707 | pinctrl-names = "default"; |
| 708 | pinctrl-0 = <&emmc_pins>; | 708 | pinctrl-0 = <&emmc_pins>; |
| 709 | bus-width = <8>; | 709 | bus-width = <8>; |
| 710 | vmmc-supply = <&vmmcwl_fixed>; | 710 | vmmc-supply = <&vmmcwl_fixed>; |
| 711 | status = "okay"; | 711 | status = "okay"; |
| 712 | ti,non-removable; | 712 | ti,non-removable; |
| 713 | }; | 713 | }; |
| 714 | 714 | ||
| 715 | /*If carrier board eMMC (or 2nd SD slot) is present and used, un-comment out the following nodes. SD card will be emulated /dev/mmcblk2 instead of /dev/mmcblk1*/ | 715 | /*If carrier board eMMC (or 2nd SD slot) is present and used, un-comment out the following nodes. SD card will be emulated /dev/mmcblk2 instead of /dev/mmcblk1*/ |
| 716 | 716 | ||
| 717 | &mmc3 { | 717 | &mmc3 { |
| 718 | status = "okay"; | 718 | status = "disabled"; |
| 719 | dmas = <&edma 30 | 719 | dmas = <&edma 30 |
| 720 | &edma 31>; | 720 | &edma 31>; |
| 721 | dma-names = "tx", "rx"; | 721 | dma-names = "tx", "rx"; |
| 722 | vmmc-supply = <&vmmcwl_fixed>; | 722 | vmmc-supply = <&vmmcwl_fixed>; |
| 723 | bus-width = <8>; | 723 | bus-width = <8>; |
| 724 | pinctrl-names = "default"; | 724 | pinctrl-names = "default"; |
| 725 | pinctrl-0 = <&sdmmc_pins>; | 725 | pinctrl-0 = <&sdmmc_pins>; |
| 726 | keep-power-in-suspend; | 726 | keep-power-in-suspend; |
| 727 | ti,non-removable; | 727 | ti,non-removable; |
| 728 | }; | 728 | }; |
| 729 | 729 | ||
| 730 | &edma { | 730 | &edma { |
| 731 | ti,edma-xbar-event-map = /bits/ 16 <1 30 | 731 | ti,edma-xbar-event-map = /bits/ 16 <1 30 |
| 732 | 2 31>; | 732 | 2 31>; |
| 733 | }; | 733 | }; |
| 734 | 734 | ||
| 735 | /* Four-Wire Resistive Touch */ | 735 | /* Four-Wire Resistive Touch */ |
| 736 | &tscadc { | 736 | &tscadc { |
| 737 | status = "disabled"; | 737 | status = "disabled"; |
| 738 | tsc { | 738 | tsc { |
| 739 | ti,wires = <4>; | 739 | ti,wires = <4>; |
| 740 | ti,x-plate-resistance = <200>; | 740 | ti,x-plate-resistance = <200>; |
| 741 | ti,coordinate-readouts = <5>; | 741 | ti,coordinate-readouts = <5>; |
| 742 | ti,wire-config = <0x00 0x11 0x22 0x33>; | 742 | ti,wire-config = <0x00 0x11 0x22 0x33>; |
| 743 | ti,charge-delay = <0xB000>; | 743 | ti,charge-delay = <0xB000>; |
| 744 | }; | 744 | }; |
| 745 | 745 | ||
| 746 | adc { | 746 | adc { |
| 747 | ti,adc-channels = <0 1 2 3>; | 747 | ti,adc-channels = <0 1 2 3>; |
| 748 | }; | 748 | }; |
| 749 | }; | 749 | }; |
| 750 | 750 | ||
| 751 | &usb2_phy1 { | 751 | &usb2_phy1 { |
| 752 | status = "okay"; | 752 | status = "okay"; |
| 753 | }; | 753 | }; |
| 754 | 754 | ||
| 755 | &usb1 { | 755 | &usb1 { |
| 756 | dr_mode = "host"; | 756 | dr_mode = "host"; |
| 757 | status = "okay"; | 757 | status = "okay"; |
| 758 | pinctrl-names = "default"; | 758 | pinctrl-names = "default"; |
| 759 | pinctrl-0 = <&usb1_pins>; | 759 | pinctrl-0 = <&usb1_pins>; |
| 760 | }; | 760 | }; |
| 761 | 761 | ||
| 762 | &usb2_phy2 { | 762 | &usb2_phy2 { |
| 763 | status = "okay"; | 763 | status = "okay"; |
| 764 | }; | 764 | }; |
| 765 | 765 | ||
| 766 | &usb2 { | 766 | &usb2 { |
| 767 | dr_mode = "host"; | 767 | dr_mode = "host"; |
| 768 | status = "okay"; | 768 | status = "okay"; |
| 769 | pinctrl-names = "default"; | 769 | pinctrl-names = "default"; |
| 770 | pinctrl-0 = <&usb2_pins>; | 770 | pinctrl-0 = <&usb2_pins>; |
| 771 | }; | 771 | }; |
| 772 | 772 | ||
| 773 | &spi0 { | 773 | &spi0 { |
| 774 | ti,spi-num-cs = <1>; | 774 | ti,spi-num-cs = <1>; |
| 775 | status = "okay"; | 775 | status = "okay"; |
| 776 | pinctrl-names = "default"; | 776 | pinctrl-names = "default"; |
| 777 | pinctrl-0 = <&spi0_pins>; | 777 | pinctrl-0 = <&spi0_pins>; |
| 778 | dmas = <&edma 16 | 778 | dmas = <&edma 16 |
| 779 | &edma 17>; | 779 | &edma 17>; |
| 780 | dma-names = "tx0", "rx0"; | 780 | dma-names = "tx0", "rx0"; |
| 781 | 781 | ||
| 782 | flash: mx25u3235f@0 { | 782 | flash: mx25u3235f@0 { |
| 783 | #address-cells = <1>; | 783 | #address-cells = <1>; |
| 784 | #size-cells = <1>; | 784 | #size-cells = <1>; |
| 785 | compatible = "jedec,spi-nor"; | 785 | compatible = "jedec,spi-nor"; |
| 786 | spi-max-frequency = <24000000>; | 786 | spi-max-frequency = <24000000>; |
| 787 | reg = <0>; | 787 | reg = <0>; |
| 788 | 788 | ||
| 789 | /* MTD partition table. | 789 | /* MTD partition table. |
| 790 | * The ROM checks the first 512KiB | 790 | * The ROM checks the first 512KiB |
| 791 | * for a valid file to boot(XIP). | 791 | * for a valid file to boot(XIP). |
| 792 | */ | 792 | */ |
| 793 | partition@0 { | 793 | partition@0 { |
| 794 | label = "U-Boot"; | 794 | label = "U-Boot"; |
| 795 | reg = <0x0 0x100000>; | 795 | reg = <0x0 0x100000>; |
| 796 | }; | 796 | }; |
| 797 | 797 | ||
| 798 | partition@100000 { | 798 | partition@100000 { |
| 799 | label = "U-Boot Environment"; | 799 | label = "U-Boot Environment"; |
| 800 | reg = <0x100000 0x080000>; | 800 | reg = <0x100000 0x080000>; |
| 801 | }; | 801 | }; |
| 802 | 802 | ||
| 803 | partition@180000 { | 803 | partition@180000 { |
| 804 | label = "Flattened Device Tree"; | 804 | label = "Flattened Device Tree"; |
| 805 | reg = <0x180000 0x200000>; | 805 | reg = <0x180000 0x200000>; |
| 806 | }; | 806 | }; |
| 807 | 807 | ||
| 808 | }; | 808 | }; |
| 809 | }; | 809 | }; |
| 810 | 810 | ||
| 811 | &spi2 { | 811 | &spi2 { |
| 812 | ti,spi-num-cs = <2>; | 812 | ti,spi-num-cs = <2>; |
| 813 | status = "okay"; | 813 | status = "disabled"; |
| 814 | pinctrl-names = "default"; | 814 | pinctrl-names = "default"; |
| 815 | pinctrl-0 = <&spi2_pins>; | 815 | pinctrl-0 = <&spi2_pins>; |
| 816 | dmas = <&edma 18 | 816 | dmas = <&edma 18 |
| 817 | &edma 19 | 817 | &edma 19 |
| 818 | &edma 20 | 818 | &edma 20 |
| 819 | &edma 21>; | 819 | &edma 21>; |
| 820 | dma-names = "tx0", "rx0", "tx1", "rx1"; | 820 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 821 | 821 | ||
| 822 | spidev1: spidev@0 { | 822 | spidev1: spidev@0 { |
| 823 | #address-cells = <1>; | 823 | #address-cells = <1>; |
| 824 | #size-cells = <0>; | 824 | #size-cells = <0>; |
| 825 | compatible = "spidev"; | 825 | compatible = "spidev"; |
| 826 | reg = <0>; | 826 | reg = <0>; |
| 827 | spi-max-frequency = <24000000>; | 827 | spi-max-frequency = <24000000>; |
| 828 | }; | 828 | }; |
| 829 | 829 | ||
| 830 | spidev2: spidev@1 { | 830 | spidev2: spidev@1 { |
| 831 | #address-cells = <1>; | 831 | #address-cells = <1>; |
| 832 | #size-cells = <0>; | 832 | #size-cells = <0>; |
| 833 | compatible = "spidev"; | 833 | compatible = "spidev"; |
| 834 | reg = <1>; | 834 | reg = <1>; |
| 835 | spi-max-frequency = <24000000>; | 835 | spi-max-frequency = <24000000>; |
| 836 | }; | 836 | }; |
| 837 | }; | 837 | }; |
| 838 | 838 | ||
| 839 | &spi4 { | 839 | &spi4 { |
| 840 | ti,spi-num-cs = <2>; | 840 | ti,spi-num-cs = <2>; |
| 841 | status = "okay"; | 841 | status = "disabled"; |
| 842 | pinctrl-names = "default"; | 842 | pinctrl-names = "default"; |
| 843 | pinctrl-0 = <&spi4_pins>; | 843 | pinctrl-0 = <&spi4_pins>; |
| 844 | dmas = <&edma 26 | 844 | dmas = <&edma 26 |
| 845 | &edma 27 | 845 | &edma 27 |
| 846 | &edma 28 | 846 | &edma 28 |
| 847 | &edma 29>; | 847 | &edma 29>; |
| 848 | dma-names = "tx0", "rx0", "tx1", "rx1"; | 848 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 849 | 849 | ||
| 850 | spidev3: spidev@0 { | 850 | spidev3: spidev@0 { |
| 851 | #address-cells = <1>; | 851 | #address-cells = <1>; |
| 852 | #size-cells = <0>; | 852 | #size-cells = <0>; |
| 853 | compatible = "spidev"; | 853 | compatible = "spidev"; |
| 854 | reg = <0>; | 854 | reg = <0>; |
| 855 | spi-max-frequency = <24000000>; | 855 | spi-max-frequency = <24000000>; |
| 856 | }; | 856 | }; |
| 857 | 857 | ||
| 858 | spidev4: spidev@1 { | 858 | spidev4: spidev@1 { |
| 859 | #address-cells = <1>; | 859 | #address-cells = <1>; |
| 860 | #size-cells = <0>; | 860 | #size-cells = <0>; |
| 861 | compatible = "spidev"; | 861 | compatible = "spidev"; |
| 862 | reg = <1>; | 862 | reg = <1>; |
| 863 | spi-max-frequency = <24000000>; | 863 | spi-max-frequency = <24000000>; |
| 864 | }; | 864 | }; |
| 865 | }; | 865 | }; |
| 866 | 866 | ||
| 867 | &uart0 { | 867 | &uart0 { |
| 868 | pinctrl-names = "default"; | 868 | pinctrl-names = "default"; |
| 869 | pinctrl-0 = <&uart0_pins>; | 869 | pinctrl-0 = <&uart0_pins>; |
| 870 | pinctrl-1 = <&uart0_pins_sleep>; | 870 | pinctrl-1 = <&uart0_pins_sleep>; |
| 871 | 871 | ||
| 872 | status = "okay"; | 872 | status = "okay"; |
| 873 | }; | 873 | }; |
| 874 | 874 | ||
| 875 | &uart3 { | 875 | &uart3 { |
| 876 | pinctrl-names = "default"; | 876 | pinctrl-names = "default"; |
| 877 | pinctrl-0 = <&uart3_pins>; | 877 | pinctrl-0 = <&uart3_pins>; |
| 878 | pinctrl-1 = <&uart3_pins_sleep>; | 878 | pinctrl-1 = <&uart3_pins_sleep>; |
| 879 | 879 | ||
| 880 | status = "okay"; | 880 | status = "okay"; |
| 881 | }; | 881 | }; |
| 882 | 882 | ||
| 883 | &uart2 { | 883 | &uart2 { |
| 884 | pinctrl-names = "default"; | 884 | pinctrl-names = "default"; |
| 885 | pinctrl-0 = <&uart2_pins>; | 885 | pinctrl-0 = <&uart2_pins>; |
| 886 | pinctrl-1 = <&uart2_pins_sleep>; | 886 | pinctrl-1 = <&uart2_pins_sleep>; |
| 887 | 887 | ||
| 888 | status = "okay"; | 888 | status = "okay"; |
| 889 | }; | 889 | }; |
| 890 | 890 | ||
| 891 | &uart4 { | 891 | &uart4 { |
| 892 | pinctrl-names = "default"; | 892 | pinctrl-names = "default"; |
| 893 | pinctrl-0 = <&uart4_pins>; | 893 | pinctrl-0 = <&uart4_pins>; |
| 894 | pinctrl-1 = <&uart4_pins_sleep>; | 894 | pinctrl-1 = <&uart4_pins_sleep>; |
| 895 | 895 | ||
| 896 | status = "okay"; | 896 | status = "okay"; |
| 897 | }; | 897 | }; |
| 898 | 898 | ||
| 899 | &dcan0 { | 899 | &dcan0 { |
| 900 | pinctrl-names = "default"; | 900 | pinctrl-names = "default"; |
| 901 | pinctrl-0 = <&dcan0_default>; | 901 | pinctrl-0 = <&dcan0_default>; |
| 902 | status = "okay"; | 902 | status = "disabled"; |
| 903 | }; | 903 | }; |
| 904 | 904 | ||
| 905 | &dcan1 { | 905 | &dcan1 { |
| 906 | pinctrl-names = "default"; | 906 | pinctrl-names = "default"; |
| 907 | pinctrl-0 = <&dcan1_default>; | 907 | pinctrl-0 = <&dcan1_default>; |
| 908 | status = "okay"; | 908 | status = "disabled"; |
| 909 | }; | 909 | }; |
| 910 | 910 | ||
| 911 | &mac { | 911 | &mac { |
| 912 | pinctrl-names = "default", "sleep"; | 912 | pinctrl-names = "default", "sleep"; |
| 913 | pinctrl-0 = <&cpsw_default>; | 913 | pinctrl-0 = <&cpsw_default>; |
| 914 | pinctrl-1 = <&cpsw_sleep>; | 914 | pinctrl-1 = <&cpsw_sleep>; |
| 915 | dual_emac = <1>; | 915 | dual_emac = <1>; |
| 916 | status = "okay"; | 916 | status = "okay"; |
| 917 | }; | 917 | }; |
| 918 | 918 | ||
| 919 | &davinci_mdio { | 919 | &davinci_mdio { |
| 920 | pinctrl-names = "default", "sleep"; | 920 | pinctrl-names = "default", "sleep"; |
| 921 | pinctrl-0 = <&davinci_mdio_default>; | 921 | pinctrl-0 = <&davinci_mdio_default>; |
| 922 | pinctrl-1 = <&davinci_mdio_sleep>; | 922 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 923 | status = "okay"; | 923 | status = "okay"; |
| 924 | }; | 924 | }; |
| 925 | 925 | ||
| 926 | &cpsw_emac0 { | 926 | &cpsw_emac0 { |
| 927 | phy_id = <&davinci_mdio>, <6>; | 927 | phy_id = <&davinci_mdio>, <6>; |
| 928 | phy-mode = "rgmii"; | 928 | phy-mode = "rgmii"; |
| 929 | dual_emac_res_vlan = <1>; | 929 | dual_emac_res_vlan = <1>; |
| 930 | }; | 930 | }; |
| 931 | 931 | ||
| 932 | &cpsw_emac1 { | 932 | &cpsw_emac1 { |
| 933 | phy_id = <&davinci_mdio>, <7>; | 933 | phy_id = <&davinci_mdio>, <7>; |
| 934 | phy-mode = "rgmii"; | 934 | phy-mode = "rgmii"; |
| 935 | dual_emac_res_vlan = <2>; | 935 | dual_emac_res_vlan = <2>; |
| 936 | }; | 936 | }; |
| 937 | 937 | ||
| 938 | &elm { | 938 | &elm { |
| 939 | status = "okay"; | 939 | status = "okay"; |
| 940 | }; | 940 | }; |
| 941 | 941 | ||
| 942 | &mcasp1 { | 942 | &mcasp1 { |
| 943 | #sound-dai-cells = <0>; | 943 | #sound-dai-cells = <0>; |
| 944 | pinctrl-names = "default", "sleep"; | 944 | pinctrl-names = "default", "sleep"; |
| 945 | pinctrl-0 = <&mcasp1_pins>; | 945 | pinctrl-0 = <&mcasp1_pins>; |
| 946 | pinctrl-1 = <&mcasp1_sleep_pins>; | 946 | pinctrl-1 = <&mcasp1_sleep_pins>; |
| 947 | 947 | ||
| 948 | status = "okay"; | 948 | status = "disabled"; |
| 949 | 949 | ||
| 950 | op-mode = <0>; /* MCASP_IIS_MODE */ | 950 | op-mode = <0>; /* MCASP_IIS_MODE */ |
| 951 | tdm-slots = <2>; | 951 | tdm-slots = <2>; |
| 952 | /* 4 serializers */ | 952 | /* 4 serializers */ |
| 953 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | 953 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 954 | 1 2 0 0 | 954 | 1 2 0 0 |
| 955 | >; | 955 | >; |
| 956 | 956 | ||
| 957 | tx-num-evt = <1>; | 957 | tx-num-evt = <1>; |
| 958 | rx-num-evt = <1>; | 958 | rx-num-evt = <1>; |
| 959 | }; | 959 | }; |
| 960 | 960 | ||
| 961 | &dss { | 961 | &dss { |
| 962 | status = "okay"; | 962 | status = "disabled"; |
| 963 | 963 | ||
| 964 | pinctrl-names = "default"; | 964 | pinctrl-names = "default"; |
| 965 | pinctrl-0 = <&dss_pins>; | 965 | pinctrl-0 = <&dss_pins>; |
| 966 | 966 | ||
| 967 | port { | 967 | port { |
| 968 | dpi_out: endpoint@0 { | 968 | dpi_out: endpoint@0 { |
| 969 | remote-endpoint = <&lcd_in>; | 969 | remote-endpoint = <&lcd_in>; |
| 970 | data-lines = <24>; | 970 | data-lines = <24>; |
| 971 | }; | 971 | }; |
| 972 | }; | 972 | }; |
| 973 | }; | 973 | }; |
| 974 | 974 | ||
| 975 | &rtc { | 975 | &rtc { |
| 976 | status = "disabled"; /* Use Seiko S35390A on Module instead */ | 976 | status = "disabled"; /* Use Seiko S35390A on Module instead */ |
| 977 | ext-clk-src; | 977 | ext-clk-src; |
| 978 | }; | 978 | }; |
| 979 | 979 | ||
| 980 | &wdt { | 980 | &wdt { |
| 981 | status = "okay"; | 981 | status = "okay"; |
| 982 | }; | 982 | }; |
| 983 | 983 | ||
| 984 | &cpu { | 984 | &cpu { |
| 985 | cpu0-supply = <&dcdc2>; | 985 | cpu0-supply = <&dcdc2>; |
| 986 | }; | 986 | }; |
| 987 | 987 | ||
| 988 | 988 |
arch/arm/mach-omap2/am33xx/board.c
| 1 | /* | 1 | /* |
| 2 | * board.c | 2 | * board.c |
| 3 | * | 3 | * |
| 4 | * Common board functions for AM33XX based boards | 4 | * Common board functions for AM33XX based boards |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ | 6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
| 7 | * | 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <common.h> | 11 | #include <common.h> |
| 12 | #include <dm.h> | 12 | #include <dm.h> |
| 13 | #include <errno.h> | 13 | #include <errno.h> |
| 14 | #include <ns16550.h> | 14 | #include <ns16550.h> |
| 15 | #include <spl.h> | 15 | #include <spl.h> |
| 16 | #include <asm/arch/cpu.h> | 16 | #include <asm/arch/cpu.h> |
| 17 | #include <asm/arch/hardware.h> | 17 | #include <asm/arch/hardware.h> |
| 18 | #include <asm/arch/omap.h> | 18 | #include <asm/arch/omap.h> |
| 19 | #include <asm/arch/ddr_defs.h> | 19 | #include <asm/arch/ddr_defs.h> |
| 20 | #include <asm/arch/clock.h> | 20 | #include <asm/arch/clock.h> |
| 21 | #include <asm/arch/gpio.h> | 21 | #include <asm/arch/gpio.h> |
| 22 | #include <asm/arch/mem.h> | 22 | #include <asm/arch/mem.h> |
| 23 | #include <asm/arch/mmc_host_def.h> | 23 | #include <asm/arch/mmc_host_def.h> |
| 24 | #include <asm/arch/sys_proto.h> | 24 | #include <asm/arch/sys_proto.h> |
| 25 | #include <asm/io.h> | 25 | #include <asm/io.h> |
| 26 | #include <asm/emif.h> | 26 | #include <asm/emif.h> |
| 27 | #include <asm/gpio.h> | 27 | #include <asm/gpio.h> |
| 28 | #include <i2c.h> | 28 | #include <i2c.h> |
| 29 | #include <miiphy.h> | 29 | #include <miiphy.h> |
| 30 | #include <cpsw.h> | 30 | #include <cpsw.h> |
| 31 | #include <linux/errno.h> | 31 | #include <linux/errno.h> |
| 32 | #include <linux/compiler.h> | 32 | #include <linux/compiler.h> |
| 33 | #include <linux/usb/ch9.h> | 33 | #include <linux/usb/ch9.h> |
| 34 | #include <linux/usb/gadget.h> | 34 | #include <linux/usb/gadget.h> |
| 35 | #include <linux/usb/musb.h> | 35 | #include <linux/usb/musb.h> |
| 36 | #include <asm/omap_musb.h> | 36 | #include <asm/omap_musb.h> |
| 37 | #include <asm/davinci_rtc.h> | 37 | #include <asm/davinci_rtc.h> |
| 38 | 38 | ||
| 39 | DECLARE_GLOBAL_DATA_PTR; | 39 | DECLARE_GLOBAL_DATA_PTR; |
| 40 | 40 | ||
| 41 | #if !CONFIG_IS_ENABLED(OF_CONTROL) | 41 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
| 42 | static const struct ns16550_platdata am33xx_serial[] = { | 42 | static const struct ns16550_platdata am33xx_serial[] = { |
| 43 | { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, | 43 | { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, |
| 44 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, | 44 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
| 45 | # ifdef CONFIG_SYS_NS16550_COM2 | 45 | # ifdef CONFIG_SYS_NS16550_COM2 |
| 46 | { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, | 46 | { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, |
| 47 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, | 47 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
| 48 | # ifdef CONFIG_SYS_NS16550_COM3 | 48 | # ifdef CONFIG_SYS_NS16550_COM3 |
| 49 | { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, | 49 | { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, |
| 50 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, | 50 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
| 51 | { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, | 51 | { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, |
| 52 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, | 52 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
| 53 | { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, | 53 | { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, |
| 54 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, | 54 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
| 55 | { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, | 55 | { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, |
| 56 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, | 56 | .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
| 57 | # endif | 57 | # endif |
| 58 | # endif | 58 | # endif |
| 59 | }; | 59 | }; |
| 60 | 60 | ||
| 61 | U_BOOT_DEVICES(am33xx_uarts) = { | 61 | U_BOOT_DEVICES(am33xx_uarts) = { |
| 62 | { "ns16550_serial", &am33xx_serial[0] }, | 62 | { "ns16550_serial", &am33xx_serial[0] }, |
| 63 | # ifdef CONFIG_SYS_NS16550_COM2 | 63 | # ifdef CONFIG_SYS_NS16550_COM2 |
| 64 | { "ns16550_serial", &am33xx_serial[1] }, | 64 | { "ns16550_serial", &am33xx_serial[1] }, |
| 65 | # ifdef CONFIG_SYS_NS16550_COM3 | 65 | # ifdef CONFIG_SYS_NS16550_COM3 |
| 66 | { "ns16550_serial", &am33xx_serial[2] }, | 66 | { "ns16550_serial", &am33xx_serial[2] }, |
| 67 | { "ns16550_serial", &am33xx_serial[3] }, | 67 | { "ns16550_serial", &am33xx_serial[3] }, |
| 68 | { "ns16550_serial", &am33xx_serial[4] }, | 68 | { "ns16550_serial", &am33xx_serial[4] }, |
| 69 | { "ns16550_serial", &am33xx_serial[5] }, | 69 | { "ns16550_serial", &am33xx_serial[5] }, |
| 70 | # endif | 70 | # endif |
| 71 | # endif | 71 | # endif |
| 72 | }; | 72 | }; |
| 73 | 73 | ||
| 74 | #ifdef CONFIG_DM_GPIO | 74 | #ifdef CONFIG_DM_GPIO |
| 75 | static const struct omap_gpio_platdata am33xx_gpio[] = { | 75 | static const struct omap_gpio_platdata am33xx_gpio[] = { |
| 76 | { 0, AM33XX_GPIO0_BASE }, | 76 | { 0, AM33XX_GPIO0_BASE }, |
| 77 | { 1, AM33XX_GPIO1_BASE }, | 77 | { 1, AM33XX_GPIO1_BASE }, |
| 78 | { 2, AM33XX_GPIO2_BASE }, | 78 | { 2, AM33XX_GPIO2_BASE }, |
| 79 | { 3, AM33XX_GPIO3_BASE }, | 79 | { 3, AM33XX_GPIO3_BASE }, |
| 80 | #ifdef CONFIG_AM43XX | 80 | #ifdef CONFIG_AM43XX |
| 81 | { 4, AM33XX_GPIO4_BASE }, | 81 | { 4, AM33XX_GPIO4_BASE }, |
| 82 | { 5, AM33XX_GPIO5_BASE }, | 82 | { 5, AM33XX_GPIO5_BASE }, |
| 83 | #endif | 83 | #endif |
| 84 | }; | 84 | }; |
| 85 | 85 | ||
| 86 | U_BOOT_DEVICES(am33xx_gpios) = { | 86 | U_BOOT_DEVICES(am33xx_gpios) = { |
| 87 | { "gpio_omap", &am33xx_gpio[0] }, | 87 | { "gpio_omap", &am33xx_gpio[0] }, |
| 88 | { "gpio_omap", &am33xx_gpio[1] }, | 88 | { "gpio_omap", &am33xx_gpio[1] }, |
| 89 | { "gpio_omap", &am33xx_gpio[2] }, | 89 | { "gpio_omap", &am33xx_gpio[2] }, |
| 90 | { "gpio_omap", &am33xx_gpio[3] }, | 90 | { "gpio_omap", &am33xx_gpio[3] }, |
| 91 | #ifdef CONFIG_AM43XX | 91 | #ifdef CONFIG_AM43XX |
| 92 | { "gpio_omap", &am33xx_gpio[4] }, | 92 | { "gpio_omap", &am33xx_gpio[4] }, |
| 93 | { "gpio_omap", &am33xx_gpio[5] }, | 93 | { "gpio_omap", &am33xx_gpio[5] }, |
| 94 | #endif | 94 | #endif |
| 95 | }; | 95 | }; |
| 96 | #endif | 96 | #endif |
| 97 | #endif | 97 | #endif |
| 98 | 98 | ||
| 99 | #ifndef CONFIG_DM_GPIO | 99 | #ifndef CONFIG_DM_GPIO |
| 100 | static const struct gpio_bank gpio_bank_am33xx[] = { | 100 | static const struct gpio_bank gpio_bank_am33xx[] = { |
| 101 | { (void *)AM33XX_GPIO0_BASE }, | 101 | { (void *)AM33XX_GPIO0_BASE }, |
| 102 | { (void *)AM33XX_GPIO1_BASE }, | 102 | { (void *)AM33XX_GPIO1_BASE }, |
| 103 | { (void *)AM33XX_GPIO2_BASE }, | 103 | { (void *)AM33XX_GPIO2_BASE }, |
| 104 | { (void *)AM33XX_GPIO3_BASE }, | 104 | { (void *)AM33XX_GPIO3_BASE }, |
| 105 | #ifdef CONFIG_AM43XX | 105 | #ifdef CONFIG_AM43XX |
| 106 | { (void *)AM33XX_GPIO4_BASE }, | 106 | { (void *)AM33XX_GPIO4_BASE }, |
| 107 | { (void *)AM33XX_GPIO5_BASE }, | 107 | { (void *)AM33XX_GPIO5_BASE }, |
| 108 | #endif | 108 | #endif |
| 109 | }; | 109 | }; |
| 110 | 110 | ||
| 111 | const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; | 111 | const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; |
| 112 | #endif | 112 | #endif |
| 113 | 113 | ||
| 114 | #if defined(CONFIG_OMAP_HSMMC) | 114 | #if defined(CONFIG_OMAP_HSMMC) |
| 115 | int cpu_mmc_init(bd_t *bis) | 115 | int cpu_mmc_init(bd_t *bis) |
| 116 | { | 116 | { |
| 117 | int ret; | 117 | omap_mmc_init(0, 0, 0, -1, -1); |
| 118 | 118 | omap_mmc_init(1, 0, 0, -1, -1); | |
| 119 | ret = omap_mmc_init(0, 0, 0, -1, -1); | 119 | omap_mmc_init(2, 0, 0, -1, -1); |
| 120 | if (ret) | 120 | return 0; |
| 121 | return ret; | ||
| 122 | |||
| 123 | return omap_mmc_init(2, 0, 0, -1, -1); | ||
| 124 | } | 121 | } |
| 125 | #endif | 122 | #endif |
| 126 | 123 | ||
| 127 | /* | 124 | /* |
| 128 | * RTC only mode magic value, checked against during boot to see if we have | 125 | * RTC only mode magic value, checked against during boot to see if we have |
| 129 | * a valid config | 126 | * a valid config |
| 130 | */ | 127 | */ |
| 131 | #define RTC_MAGIC_VAL 0x8cd0 | 128 | #define RTC_MAGIC_VAL 0x8cd0 |
| 132 | 129 | ||
| 133 | /* Board type field bit shift for RTC only mode */ | 130 | /* Board type field bit shift for RTC only mode */ |
| 134 | #define RTC_BOARD_TYPE_SHIFT 16 | 131 | #define RTC_BOARD_TYPE_SHIFT 16 |
| 135 | 132 | ||
| 136 | /* AM33XX has two MUSB controllers which can be host or gadget */ | 133 | /* AM33XX has two MUSB controllers which can be host or gadget */ |
| 137 | #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ | 134 | #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ |
| 138 | (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ | 135 | (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ |
| 139 | (!defined(CONFIG_DM_USB)) | 136 | (!defined(CONFIG_DM_USB)) |
| 140 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; | 137 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 141 | 138 | ||
| 142 | /* USB 2.0 PHY Control */ | 139 | /* USB 2.0 PHY Control */ |
| 143 | #define CM_PHY_PWRDN (1 << 0) | 140 | #define CM_PHY_PWRDN (1 << 0) |
| 144 | #define CM_PHY_OTG_PWRDN (1 << 1) | 141 | #define CM_PHY_OTG_PWRDN (1 << 1) |
| 145 | #define OTGVDET_EN (1 << 19) | 142 | #define OTGVDET_EN (1 << 19) |
| 146 | #define OTGSESSENDEN (1 << 20) | 143 | #define OTGSESSENDEN (1 << 20) |
| 147 | 144 | ||
| 148 | static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) | 145 | static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) |
| 149 | { | 146 | { |
| 150 | if (on) { | 147 | if (on) { |
| 151 | clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, | 148 | clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, |
| 152 | OTGVDET_EN | OTGSESSENDEN); | 149 | OTGVDET_EN | OTGSESSENDEN); |
| 153 | } else { | 150 | } else { |
| 154 | clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); | 151 | clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); |
| 155 | } | 152 | } |
| 156 | } | 153 | } |
| 157 | 154 | ||
| 158 | static struct musb_hdrc_config musb_config = { | 155 | static struct musb_hdrc_config musb_config = { |
| 159 | .multipoint = 1, | 156 | .multipoint = 1, |
| 160 | .dyn_fifo = 1, | 157 | .dyn_fifo = 1, |
| 161 | .num_eps = 16, | 158 | .num_eps = 16, |
| 162 | .ram_bits = 12, | 159 | .ram_bits = 12, |
| 163 | }; | 160 | }; |
| 164 | 161 | ||
| 165 | #ifdef CONFIG_AM335X_USB0 | 162 | #ifdef CONFIG_AM335X_USB0 |
| 166 | static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) | 163 | static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) |
| 167 | { | 164 | { |
| 168 | am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); | 165 | am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); |
| 169 | } | 166 | } |
| 170 | 167 | ||
| 171 | struct omap_musb_board_data otg0_board_data = { | 168 | struct omap_musb_board_data otg0_board_data = { |
| 172 | .set_phy_power = am33xx_otg0_set_phy_power, | 169 | .set_phy_power = am33xx_otg0_set_phy_power, |
| 173 | }; | 170 | }; |
| 174 | 171 | ||
| 175 | static struct musb_hdrc_platform_data otg0_plat = { | 172 | static struct musb_hdrc_platform_data otg0_plat = { |
| 176 | .mode = CONFIG_AM335X_USB0_MODE, | 173 | .mode = CONFIG_AM335X_USB0_MODE, |
| 177 | .config = &musb_config, | 174 | .config = &musb_config, |
| 178 | .power = 50, | 175 | .power = 50, |
| 179 | .platform_ops = &musb_dsps_ops, | 176 | .platform_ops = &musb_dsps_ops, |
| 180 | .board_data = &otg0_board_data, | 177 | .board_data = &otg0_board_data, |
| 181 | }; | 178 | }; |
| 182 | #endif | 179 | #endif |
| 183 | 180 | ||
| 184 | #ifdef CONFIG_AM335X_USB1 | 181 | #ifdef CONFIG_AM335X_USB1 |
| 185 | static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) | 182 | static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) |
| 186 | { | 183 | { |
| 187 | am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); | 184 | am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); |
| 188 | } | 185 | } |
| 189 | 186 | ||
| 190 | struct omap_musb_board_data otg1_board_data = { | 187 | struct omap_musb_board_data otg1_board_data = { |
| 191 | .set_phy_power = am33xx_otg1_set_phy_power, | 188 | .set_phy_power = am33xx_otg1_set_phy_power, |
| 192 | }; | 189 | }; |
| 193 | 190 | ||
| 194 | static struct musb_hdrc_platform_data otg1_plat = { | 191 | static struct musb_hdrc_platform_data otg1_plat = { |
| 195 | .mode = CONFIG_AM335X_USB1_MODE, | 192 | .mode = CONFIG_AM335X_USB1_MODE, |
| 196 | .config = &musb_config, | 193 | .config = &musb_config, |
| 197 | .power = 50, | 194 | .power = 50, |
| 198 | .platform_ops = &musb_dsps_ops, | 195 | .platform_ops = &musb_dsps_ops, |
| 199 | .board_data = &otg1_board_data, | 196 | .board_data = &otg1_board_data, |
| 200 | }; | 197 | }; |
| 201 | #endif | 198 | #endif |
| 202 | #endif | 199 | #endif |
| 203 | 200 | ||
| 204 | int arch_misc_init(void) | 201 | int arch_misc_init(void) |
| 205 | { | 202 | { |
| 206 | #ifndef CONFIG_DM_USB | 203 | #ifndef CONFIG_DM_USB |
| 207 | #ifdef CONFIG_AM335X_USB0 | 204 | #ifdef CONFIG_AM335X_USB0 |
| 208 | musb_register(&otg0_plat, &otg0_board_data, | 205 | musb_register(&otg0_plat, &otg0_board_data, |
| 209 | (void *)USB0_OTG_BASE); | 206 | (void *)USB0_OTG_BASE); |
| 210 | #endif | 207 | #endif |
| 211 | #ifdef CONFIG_AM335X_USB1 | 208 | #ifdef CONFIG_AM335X_USB1 |
| 212 | musb_register(&otg1_plat, &otg1_board_data, | 209 | musb_register(&otg1_plat, &otg1_board_data, |
| 213 | (void *)USB1_OTG_BASE); | 210 | (void *)USB1_OTG_BASE); |
| 214 | #endif | 211 | #endif |
| 215 | #else | 212 | #else |
| 216 | struct udevice *dev; | 213 | struct udevice *dev; |
| 217 | int ret; | 214 | int ret; |
| 218 | 215 | ||
| 219 | ret = uclass_first_device(UCLASS_MISC, &dev); | 216 | ret = uclass_first_device(UCLASS_MISC, &dev); |
| 220 | if (ret || !dev) | 217 | if (ret || !dev) |
| 221 | return ret; | 218 | return ret; |
| 222 | 219 | ||
| 223 | ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev); | 220 | ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev); |
| 224 | if (ret) | 221 | if (ret) |
| 225 | return ret; | 222 | return ret; |
| 226 | #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) | 223 | #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) |
| 227 | ret = usb_ether_init(); | 224 | ret = usb_ether_init(); |
| 228 | if (ret) { | 225 | if (ret) { |
| 229 | error("USB ether init failed\n"); | 226 | error("USB ether init failed\n"); |
| 230 | return ret; | 227 | return ret; |
| 231 | } | 228 | } |
| 232 | #endif | 229 | #endif |
| 233 | #endif | 230 | #endif |
| 234 | return 0; | 231 | return 0; |
| 235 | } | 232 | } |
| 236 | 233 | ||
| 237 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | 234 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 238 | 235 | ||
| 239 | #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ | 236 | #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ |
| 240 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)) | 237 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)) |
| 241 | static void rtc32k_unlock(struct davinci_rtc *rtc) | 238 | static void rtc32k_unlock(struct davinci_rtc *rtc) |
| 242 | { | 239 | { |
| 243 | /* | 240 | /* |
| 244 | * Unlock the RTC's registers. For more details please see the | 241 | * Unlock the RTC's registers. For more details please see the |
| 245 | * RTC_SS section of the TRM. In order to unlock we need to | 242 | * RTC_SS section of the TRM. In order to unlock we need to |
| 246 | * write these specific values (keys) in this order. | 243 | * write these specific values (keys) in this order. |
| 247 | */ | 244 | */ |
| 248 | writel(RTC_KICK0R_WE, &rtc->kick0r); | 245 | writel(RTC_KICK0R_WE, &rtc->kick0r); |
| 249 | writel(RTC_KICK1R_WE, &rtc->kick1r); | 246 | writel(RTC_KICK1R_WE, &rtc->kick1r); |
| 250 | } | 247 | } |
| 251 | #endif | 248 | #endif |
| 252 | 249 | ||
| 253 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) | 250 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) |
| 254 | /* | 251 | /* |
| 255 | * Write contents of the RTC_SCRATCH1 register based on board type | 252 | * Write contents of the RTC_SCRATCH1 register based on board type |
| 256 | * Two things are passed | 253 | * Two things are passed |
| 257 | * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the | 254 | * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the |
| 258 | * control gets to kernel, kernel reads the scratchpad register and gets to | 255 | * control gets to kernel, kernel reads the scratchpad register and gets to |
| 259 | * know that bootloader has rtc_only support. | 256 | * know that bootloader has rtc_only support. |
| 260 | * | 257 | * |
| 261 | * Second important thing is the board type (16:31). This is needed in the | 258 | * Second important thing is the board type (16:31). This is needed in the |
| 262 | * rtc_only boot where in we want to avoid costly i2c reads to eeprom to | 259 | * rtc_only boot where in we want to avoid costly i2c reads to eeprom to |
| 263 | * identify the board type and we go ahead and copy the board strings to | 260 | * identify the board type and we go ahead and copy the board strings to |
| 264 | * am43xx_board_name. | 261 | * am43xx_board_name. |
| 265 | */ | 262 | */ |
| 266 | void update_rtc_magic(void) | 263 | void update_rtc_magic(void) |
| 267 | { | 264 | { |
| 268 | struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; | 265 | struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; |
| 269 | u32 magic = RTC_MAGIC_VAL; | 266 | u32 magic = RTC_MAGIC_VAL; |
| 270 | 267 | ||
| 271 | magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT); | 268 | magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT); |
| 272 | 269 | ||
| 273 | rtc32k_unlock(rtc); | 270 | rtc32k_unlock(rtc); |
| 274 | 271 | ||
| 275 | /* write magic */ | 272 | /* write magic */ |
| 276 | writel(magic, &rtc->scratch1); | 273 | writel(magic, &rtc->scratch1); |
| 277 | } | 274 | } |
| 278 | #endif | 275 | #endif |
| 279 | 276 | ||
| 280 | /* | 277 | /* |
| 281 | * In the case of non-SPL based booting we'll want to call these | 278 | * In the case of non-SPL based booting we'll want to call these |
| 282 | * functions a tiny bit later as it will require gd to be set and cleared | 279 | * functions a tiny bit later as it will require gd to be set and cleared |
| 283 | * and that's not true in s_init in this case so we cannot do it there. | 280 | * and that's not true in s_init in this case so we cannot do it there. |
| 284 | */ | 281 | */ |
| 285 | int board_early_init_f(void) | 282 | int board_early_init_f(void) |
| 286 | { | 283 | { |
| 287 | prcm_init(); | 284 | prcm_init(); |
| 288 | set_mux_conf_regs(); | 285 | set_mux_conf_regs(); |
| 289 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) | 286 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) |
| 290 | update_rtc_magic(); | 287 | update_rtc_magic(); |
| 291 | #endif | 288 | #endif |
| 292 | return 0; | 289 | return 0; |
| 293 | } | 290 | } |
| 294 | 291 | ||
| 295 | /* | 292 | /* |
| 296 | * This function is the place to do per-board things such as ramp up the | 293 | * This function is the place to do per-board things such as ramp up the |
| 297 | * MPU clock frequency. | 294 | * MPU clock frequency. |
| 298 | */ | 295 | */ |
| 299 | __weak void am33xx_spl_board_init(void) | 296 | __weak void am33xx_spl_board_init(void) |
| 300 | { | 297 | { |
| 301 | } | 298 | } |
| 302 | 299 | ||
| 303 | #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) | 300 | #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) |
| 304 | static void rtc32k_enable(void) | 301 | static void rtc32k_enable(void) |
| 305 | { | 302 | { |
| 306 | struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; | 303 | struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; |
| 307 | 304 | ||
| 308 | rtc32k_unlock(rtc); | 305 | rtc32k_unlock(rtc); |
| 309 | 306 | ||
| 310 | /* Enable the RTC 32K OSC by setting bits 3 and 6. */ | 307 | /* Enable the RTC 32K OSC by setting bits 3 and 6. */ |
| 311 | writel((1 << 3) | (1 << 6), &rtc->osc); | 308 | writel((1 << 3) | (1 << 6), &rtc->osc); |
| 312 | } | 309 | } |
| 313 | #endif | 310 | #endif |
| 314 | 311 | ||
| 315 | static void uart_soft_reset(void) | 312 | static void uart_soft_reset(void) |
| 316 | { | 313 | { |
| 317 | struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; | 314 | struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; |
| 318 | u32 regval; | 315 | u32 regval; |
| 319 | 316 | ||
| 320 | regval = readl(&uart_base->uartsyscfg); | 317 | regval = readl(&uart_base->uartsyscfg); |
| 321 | regval |= UART_RESET; | 318 | regval |= UART_RESET; |
| 322 | writel(regval, &uart_base->uartsyscfg); | 319 | writel(regval, &uart_base->uartsyscfg); |
| 323 | while ((readl(&uart_base->uartsyssts) & | 320 | while ((readl(&uart_base->uartsyssts) & |
| 324 | UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) | 321 | UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) |
| 325 | ; | 322 | ; |
| 326 | 323 | ||
| 327 | /* Disable smart idle */ | 324 | /* Disable smart idle */ |
| 328 | regval = readl(&uart_base->uartsyscfg); | 325 | regval = readl(&uart_base->uartsyscfg); |
| 329 | regval |= UART_SMART_IDLE_EN; | 326 | regval |= UART_SMART_IDLE_EN; |
| 330 | writel(regval, &uart_base->uartsyscfg); | 327 | writel(regval, &uart_base->uartsyscfg); |
| 331 | } | 328 | } |
| 332 | 329 | ||
| 333 | static void watchdog_disable(void) | 330 | static void watchdog_disable(void) |
| 334 | { | 331 | { |
| 335 | struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; | 332 | struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; |
| 336 | 333 | ||
| 337 | writel(0xAAAA, &wdtimer->wdtwspr); | 334 | writel(0xAAAA, &wdtimer->wdtwspr); |
| 338 | while (readl(&wdtimer->wdtwwps) != 0x0) | 335 | while (readl(&wdtimer->wdtwwps) != 0x0) |
| 339 | ; | 336 | ; |
| 340 | writel(0x5555, &wdtimer->wdtwspr); | 337 | writel(0x5555, &wdtimer->wdtwspr); |
| 341 | while (readl(&wdtimer->wdtwwps) != 0x0) | 338 | while (readl(&wdtimer->wdtwwps) != 0x0) |
| 342 | ; | 339 | ; |
| 343 | } | 340 | } |
| 344 | 341 | ||
| 345 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) | 342 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) |
| 346 | /* | 343 | /* |
| 347 | * Check if we are executing rtc-only mode, and resume from it if needed | 344 | * Check if we are executing rtc-only mode, and resume from it if needed |
| 348 | */ | 345 | */ |
| 349 | static void rtc_only(void) | 346 | static void rtc_only(void) |
| 350 | { | 347 | { |
| 351 | struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; | 348 | struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; |
| 352 | struct prm_device_inst *prm_device = | 349 | struct prm_device_inst *prm_device = |
| 353 | (struct prm_device_inst *)PRM_DEVICE_INST; | 350 | (struct prm_device_inst *)PRM_DEVICE_INST; |
| 354 | 351 | ||
| 355 | u32 scratch1; | 352 | u32 scratch1; |
| 356 | void (*resume_func)(void); | 353 | void (*resume_func)(void); |
| 357 | 354 | ||
| 358 | scratch1 = readl(&rtc->scratch1); | 355 | scratch1 = readl(&rtc->scratch1); |
| 359 | 356 | ||
| 360 | /* | 357 | /* |
| 361 | * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only | 358 | * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only |
| 362 | * written to this register when we want to wake up from RTC only | 359 | * written to this register when we want to wake up from RTC only |
| 363 | * mode. Contents of the RTC_SCRATCH1: | 360 | * mode. Contents of the RTC_SCRATCH1: |
| 364 | * bits 0-15: RTC_MAGIC_VAL | 361 | * bits 0-15: RTC_MAGIC_VAL |
| 365 | * bits 16-31: board type (needed for sdram_init) | 362 | * bits 16-31: board type (needed for sdram_init) |
| 366 | */ | 363 | */ |
| 367 | if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) | 364 | if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) |
| 368 | return; | 365 | return; |
| 369 | 366 | ||
| 370 | rtc32k_unlock(rtc); | 367 | rtc32k_unlock(rtc); |
| 371 | 368 | ||
| 372 | /* Clear RTC magic */ | 369 | /* Clear RTC magic */ |
| 373 | writel(0, &rtc->scratch1); | 370 | writel(0, &rtc->scratch1); |
| 374 | 371 | ||
| 375 | /* | 372 | /* |
| 376 | * Update board type based on value stored on RTC_SCRATCH1, this | 373 | * Update board type based on value stored on RTC_SCRATCH1, this |
| 377 | * is done so that we don't need to read the board type from eeprom | 374 | * is done so that we don't need to read the board type from eeprom |
| 378 | * over i2c bus which is expensive | 375 | * over i2c bus which is expensive |
| 379 | */ | 376 | */ |
| 380 | rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); | 377 | rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); |
| 381 | 378 | ||
| 382 | /* | 379 | /* |
| 383 | * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we | 380 | * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we |
| 384 | * are resuming from self-refresh. This avoids an unnecessary re-init | 381 | * are resuming from self-refresh. This avoids an unnecessary re-init |
| 385 | * of the DDR. The re-init takes time and we would need to wait for | 382 | * of the DDR. The re-init takes time and we would need to wait for |
| 386 | * it to complete before accessing DDR to avoid L3 NOC errors. | 383 | * it to complete before accessing DDR to avoid L3 NOC errors. |
| 387 | */ | 384 | */ |
| 388 | writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl); | 385 | writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl); |
| 389 | 386 | ||
| 390 | rtc_only_prcm_init(); | 387 | rtc_only_prcm_init(); |
| 391 | sdram_init(); | 388 | sdram_init(); |
| 392 | 389 | ||
| 393 | /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ | 390 | /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ |
| 394 | writel(0, &prm_device->emif_ctrl); | 391 | writel(0, &prm_device->emif_ctrl); |
| 395 | 392 | ||
| 396 | resume_func = (void *)readl(&rtc->scratch0); | 393 | resume_func = (void *)readl(&rtc->scratch0); |
| 397 | if (resume_func) | 394 | if (resume_func) |
| 398 | resume_func(); | 395 | resume_func(); |
| 399 | } | 396 | } |
| 400 | #endif | 397 | #endif |
| 401 | 398 | ||
| 402 | void s_init(void) | 399 | void s_init(void) |
| 403 | { | 400 | { |
| 404 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) | 401 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) |
| 405 | rtc_only(); | 402 | rtc_only(); |
| 406 | #endif | 403 | #endif |
| 407 | } | 404 | } |
| 408 | 405 | ||
| 409 | void early_system_init(void) | 406 | void early_system_init(void) |
| 410 | { | 407 | { |
| 411 | /* | 408 | /* |
| 412 | * The ROM will only have set up sufficient pinmux to allow for the | 409 | * The ROM will only have set up sufficient pinmux to allow for the |
| 413 | * first 4KiB NOR to be read, we must finish doing what we know of | 410 | * first 4KiB NOR to be read, we must finish doing what we know of |
| 414 | * the NOR mux in this space in order to continue. | 411 | * the NOR mux in this space in order to continue. |
| 415 | */ | 412 | */ |
| 416 | #ifdef CONFIG_NOR_BOOT | 413 | #ifdef CONFIG_NOR_BOOT |
| 417 | enable_norboot_pin_mux(); | 414 | enable_norboot_pin_mux(); |
| 418 | #endif | 415 | #endif |
| 419 | watchdog_disable(); | 416 | watchdog_disable(); |
| 420 | set_uart_mux_conf(); | 417 | set_uart_mux_conf(); |
| 421 | setup_early_clocks(); | 418 | setup_early_clocks(); |
| 422 | uart_soft_reset(); | 419 | uart_soft_reset(); |
| 423 | #ifdef CONFIG_SPL_BUILD | 420 | #ifdef CONFIG_SPL_BUILD |
| 424 | /* | 421 | /* |
| 425 | * Save the boot parameters passed from romcode. | 422 | * Save the boot parameters passed from romcode. |
| 426 | * We cannot delay the saving further than this, | 423 | * We cannot delay the saving further than this, |
| 427 | * to prevent overwrites. | 424 | * to prevent overwrites. |
| 428 | */ | 425 | */ |
| 429 | save_omap_boot_params(); | 426 | save_omap_boot_params(); |
| 430 | #endif | 427 | #endif |
| 431 | #ifdef CONFIG_TI_I2C_BOARD_DETECT | 428 | #ifdef CONFIG_TI_I2C_BOARD_DETECT |
| 432 | do_board_detect(); | 429 | do_board_detect(); |
| 433 | #endif | 430 | #endif |
| 434 | #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) | 431 | #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) |
| 435 | /* Enable RTC32K clock */ | 432 | /* Enable RTC32K clock */ |
| 436 | rtc32k_enable(); | 433 | rtc32k_enable(); |
| 437 | #endif | 434 | #endif |
| 438 | } | 435 | } |
| 439 | 436 | ||
| 440 | #ifdef CONFIG_SPL_BUILD | 437 | #ifdef CONFIG_SPL_BUILD |
| 441 | void board_init_f(ulong dummy) | 438 | void board_init_f(ulong dummy) |
| 442 | { | 439 | { |
| 443 | early_system_init(); | 440 | early_system_init(); |
| 444 | board_early_init_f(); | 441 | board_early_init_f(); |
| 445 | sdram_init(); | 442 | sdram_init(); |
| 446 | /* dram_init must store complete ramsize in gd->ram_size */ | 443 | /* dram_init must store complete ramsize in gd->ram_size */ |
| 447 | gd->ram_size = get_ram_size( | 444 | gd->ram_size = get_ram_size( |
| 448 | (void *)CONFIG_SYS_SDRAM_BASE, | 445 | (void *)CONFIG_SYS_SDRAM_BASE, |
| 449 | CONFIG_MAX_RAM_BANK_SIZE); | 446 | CONFIG_MAX_RAM_BANK_SIZE); |
| 450 | } | 447 | } |
| 451 | #endif | 448 | #endif |
| 452 | 449 | ||
| 453 | #endif | 450 | #endif |
| 454 | 451 | ||
| 455 | int arch_cpu_init_dm(void) | 452 | int arch_cpu_init_dm(void) |
| 456 | { | 453 | { |
| 457 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | 454 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 458 | early_system_init(); | 455 | early_system_init(); |
| 459 | #endif | 456 | #endif |
| 460 | return 0; | 457 | return 0; |
| 461 | } | 458 | } |
| 462 | 459 |
board/embedian/smarct437x/board.c
| 1 | /* | 1 | /* |
| 2 | * board.c | 2 | * board.c |
| 3 | * | 3 | * |
| 4 | * Board functions for TI AM43XX based boards | 4 | * Board functions for TI AM43XX based boards |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ | 6 | * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ |
| 7 | * | 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <common.h> | 11 | #include <common.h> |
| 12 | #include <i2c.h> | 12 | #include <i2c.h> |
| 13 | #include <linux/errno.h> | 13 | #include <linux/errno.h> |
| 14 | #include <spl.h> | 14 | #include <spl.h> |
| 15 | #include <usb.h> | 15 | #include <usb.h> |
| 16 | #include <asm/omap_sec_common.h> | 16 | #include <asm/omap_sec_common.h> |
| 17 | #include <asm/arch/clock.h> | 17 | #include <asm/arch/clock.h> |
| 18 | #include <asm/arch/sys_proto.h> | 18 | #include <asm/arch/sys_proto.h> |
| 19 | #include <asm/arch/mux.h> | 19 | #include <asm/arch/mux.h> |
| 20 | #include <asm/arch/ddr_defs.h> | 20 | #include <asm/arch/ddr_defs.h> |
| 21 | #include <asm/arch/gpio.h> | 21 | #include <asm/arch/gpio.h> |
| 22 | #include <asm/gpio.h> | 22 | #include <asm/gpio.h> |
| 23 | #include <asm/emif.h> | 23 | #include <asm/emif.h> |
| 24 | #include "../common/board_detect.h" | 24 | #include "../common/board_detect.h" |
| 25 | #include "board.h" | 25 | #include "board.h" |
| 26 | #include <power/pmic.h> | 26 | #include <power/pmic.h> |
| 27 | #include <power/tps65218.h> | 27 | #include <power/tps65218.h> |
| 28 | #include <power/tps62362.h> | 28 | #include <power/tps62362.h> |
| 29 | #include <miiphy.h> | 29 | #include <miiphy.h> |
| 30 | #include <cpsw.h> | 30 | #include <cpsw.h> |
| 31 | #include <linux/usb/gadget.h> | 31 | #include <linux/usb/gadget.h> |
| 32 | #include <dwc3-uboot.h> | 32 | #include <dwc3-uboot.h> |
| 33 | #include <dwc3-omap-uboot.h> | 33 | #include <dwc3-omap-uboot.h> |
| 34 | #include <ti-usb-phy-uboot.h> | 34 | #include <ti-usb-phy-uboot.h> |
| 35 | 35 | ||
| 36 | DECLARE_GLOBAL_DATA_PTR; | 36 | DECLARE_GLOBAL_DATA_PTR; |
| 37 | 37 | ||
| 38 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; | 38 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 39 | 39 | ||
| 40 | /* | 40 | /* |
| 41 | * Read header information from EEPROM into global structure. | 41 | * Read header information from EEPROM into global structure. |
| 42 | */ | 42 | */ |
| 43 | #ifdef CONFIG_TI_I2C_BOARD_DETECT | 43 | #ifdef CONFIG_TI_I2C_BOARD_DETECT |
| 44 | void do_board_detect(void) | 44 | void do_board_detect(void) |
| 45 | { | 45 | { |
| 46 | i2c_set_bus_num(1); | 46 | i2c_set_bus_num(1); |
| 47 | if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR)) | 47 | if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR)) |
| 48 | printf("ti_i2c_eeprom_init failed\n"); | 48 | printf("ti_i2c_eeprom_init failed\n"); |
| 49 | } | 49 | } |
| 50 | #endif | 50 | #endif |
| 51 | 51 | ||
| 52 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | 52 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 53 | 53 | ||
| 54 | const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { | 54 | const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { |
| 55 | { /* 19.2 MHz */ | 55 | { /* 19.2 MHz */ |
| 56 | {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ | 56 | {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ |
| 57 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ | 57 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ |
| 58 | {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ | 58 | {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ |
| 59 | {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ | 59 | {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ |
| 60 | {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ | 60 | {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ |
| 61 | {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ | 61 | {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ |
| 62 | }, | 62 | }, |
| 63 | { /* 24 MHz */ | 63 | { /* 24 MHz */ |
| 64 | {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ | 64 | {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ |
| 65 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ | 65 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ |
| 66 | {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ | 66 | {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ |
| 67 | {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ | 67 | {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ |
| 68 | {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ | 68 | {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ |
| 69 | {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ | 69 | {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ |
| 70 | }, | 70 | }, |
| 71 | { /* 25 MHz */ | 71 | { /* 25 MHz */ |
| 72 | {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ | 72 | {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ |
| 73 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ | 73 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ |
| 74 | {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ | 74 | {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ |
| 75 | {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ | 75 | {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ |
| 76 | {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ | 76 | {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ |
| 77 | {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ | 77 | {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ |
| 78 | }, | 78 | }, |
| 79 | { /* 26 MHz */ | 79 | { /* 26 MHz */ |
| 80 | {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ | 80 | {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ |
| 81 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ | 81 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ |
| 82 | {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ | 82 | {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ |
| 83 | {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ | 83 | {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ |
| 84 | {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ | 84 | {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ |
| 85 | {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ | 85 | {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ |
| 86 | }, | 86 | }, |
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| 89 | const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { | 89 | const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { |
| 90 | {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ | 90 | {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ |
| 91 | {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ | 91 | {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ |
| 92 | {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ | 92 | {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ |
| 93 | {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ | 93 | {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ |
| 94 | }; | 94 | }; |
| 95 | 95 | ||
| 96 | const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { | 96 | const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { |
| 97 | {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ | 97 | {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 98 | {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ | 98 | {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ |
| 99 | {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ | 99 | {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ |
| 100 | {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ | 100 | {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ |
| 101 | }; | 101 | }; |
| 102 | 102 | ||
| 103 | const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { | 103 | const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { |
| 104 | {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ | 104 | {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ |
| 105 | {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ | 105 | {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ |
| 106 | {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ | 106 | {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ |
| 107 | {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ | 107 | {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ |
| 108 | }; | 108 | }; |
| 109 | 109 | ||
| 110 | const struct dpll_params gp_evm_dpll_ddr = { | 110 | const struct dpll_params gp_evm_dpll_ddr = { |
| 111 | 50, 2, 1, -1, 2, -1, -1}; | 111 | 50, 2, 1, -1, 2, -1, -1}; |
| 112 | 112 | ||
| 113 | static const struct dpll_params idk_dpll_ddr = { | 113 | static const struct dpll_params idk_dpll_ddr = { |
| 114 | 400, 23, 1, -1, 2, -1, -1 | 114 | 400, 23, 1, -1, 2, -1, -1 |
| 115 | }; | 115 | }; |
| 116 | 116 | ||
| 117 | static const u32 ext_phy_ctrl_const_base_lpddr2[] = { | 117 | static const u32 ext_phy_ctrl_const_base_lpddr2[] = { |
| 118 | 0x00500050, | 118 | 0x00500050, |
| 119 | 0x00350035, | 119 | 0x00350035, |
| 120 | 0x00350035, | 120 | 0x00350035, |
| 121 | 0x00350035, | 121 | 0x00350035, |
| 122 | 0x00350035, | 122 | 0x00350035, |
| 123 | 0x00350035, | 123 | 0x00350035, |
| 124 | 0x00000000, | 124 | 0x00000000, |
| 125 | 0x00000000, | 125 | 0x00000000, |
| 126 | 0x00000000, | 126 | 0x00000000, |
| 127 | 0x00000000, | 127 | 0x00000000, |
| 128 | 0x00000000, | 128 | 0x00000000, |
| 129 | 0x00000000, | 129 | 0x00000000, |
| 130 | 0x00000000, | 130 | 0x00000000, |
| 131 | 0x00000000, | 131 | 0x00000000, |
| 132 | 0x00000000, | 132 | 0x00000000, |
| 133 | 0x00000000, | 133 | 0x00000000, |
| 134 | 0x00000000, | 134 | 0x00000000, |
| 135 | 0x00000000, | 135 | 0x00000000, |
| 136 | 0x40001000, | 136 | 0x40001000, |
| 137 | 0x08102040 | 137 | 0x08102040 |
| 138 | }; | 138 | }; |
| 139 | 139 | ||
| 140 | const struct ctrl_ioregs ioregs_lpddr2 = { | 140 | const struct ctrl_ioregs ioregs_lpddr2 = { |
| 141 | .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, | 141 | .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, |
| 142 | .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, | 142 | .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, |
| 143 | .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, | 143 | .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, |
| 144 | .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, | 144 | .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, |
| 145 | .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, | 145 | .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, |
| 146 | .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, | 146 | .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, |
| 147 | .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, | 147 | .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, |
| 148 | .emif_sdram_config_ext = 0x1, | 148 | .emif_sdram_config_ext = 0x1, |
| 149 | }; | 149 | }; |
| 150 | 150 | ||
| 151 | const struct emif_regs emif_regs_lpddr2 = { | 151 | const struct emif_regs emif_regs_lpddr2 = { |
| 152 | .sdram_config = 0x808012BA, | 152 | .sdram_config = 0x808012BA, |
| 153 | .ref_ctrl = 0x0000040D, | 153 | .ref_ctrl = 0x0000040D, |
| 154 | .sdram_tim1 = 0xEA86B411, | 154 | .sdram_tim1 = 0xEA86B411, |
| 155 | .sdram_tim2 = 0x103A094A, | 155 | .sdram_tim2 = 0x103A094A, |
| 156 | .sdram_tim3 = 0x0F6BA37F, | 156 | .sdram_tim3 = 0x0F6BA37F, |
| 157 | .read_idle_ctrl = 0x00050000, | 157 | .read_idle_ctrl = 0x00050000, |
| 158 | .zq_config = 0x50074BE4, | 158 | .zq_config = 0x50074BE4, |
| 159 | .temp_alert_config = 0x0, | 159 | .temp_alert_config = 0x0, |
| 160 | .emif_rd_wr_lvl_rmp_win = 0x0, | 160 | .emif_rd_wr_lvl_rmp_win = 0x0, |
| 161 | .emif_rd_wr_lvl_rmp_ctl = 0x0, | 161 | .emif_rd_wr_lvl_rmp_ctl = 0x0, |
| 162 | .emif_rd_wr_lvl_ctl = 0x0, | 162 | .emif_rd_wr_lvl_ctl = 0x0, |
| 163 | .emif_ddr_phy_ctlr_1 = 0x0E284006, | 163 | .emif_ddr_phy_ctlr_1 = 0x0E284006, |
| 164 | .emif_rd_wr_exec_thresh = 0x80000405, | 164 | .emif_rd_wr_exec_thresh = 0x80000405, |
| 165 | .emif_ddr_ext_phy_ctrl_1 = 0x04010040, | 165 | .emif_ddr_ext_phy_ctrl_1 = 0x04010040, |
| 166 | .emif_ddr_ext_phy_ctrl_2 = 0x00500050, | 166 | .emif_ddr_ext_phy_ctrl_2 = 0x00500050, |
| 167 | .emif_ddr_ext_phy_ctrl_3 = 0x00500050, | 167 | .emif_ddr_ext_phy_ctrl_3 = 0x00500050, |
| 168 | .emif_ddr_ext_phy_ctrl_4 = 0x00500050, | 168 | .emif_ddr_ext_phy_ctrl_4 = 0x00500050, |
| 169 | .emif_ddr_ext_phy_ctrl_5 = 0x00500050, | 169 | .emif_ddr_ext_phy_ctrl_5 = 0x00500050, |
| 170 | .emif_prio_class_serv_map = 0x80000001, | 170 | .emif_prio_class_serv_map = 0x80000001, |
| 171 | .emif_connect_id_serv_1_map = 0x80000094, | 171 | .emif_connect_id_serv_1_map = 0x80000094, |
| 172 | .emif_connect_id_serv_2_map = 0x00000000, | 172 | .emif_connect_id_serv_2_map = 0x00000000, |
| 173 | .emif_cos_config = 0x000FFFFF | 173 | .emif_cos_config = 0x000FFFFF |
| 174 | }; | 174 | }; |
| 175 | 175 | ||
| 176 | const struct ctrl_ioregs ioregs_ddr3 = { | 176 | const struct ctrl_ioregs ioregs_ddr3 = { |
| 177 | .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, | 177 | .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, |
| 178 | .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, | 178 | .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, |
| 179 | .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, | 179 | .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, |
| 180 | .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, | 180 | .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, |
| 181 | .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, | 181 | .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, |
| 182 | .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, | 182 | .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, |
| 183 | .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, | 183 | .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, |
| 184 | .emif_sdram_config_ext = 0xc163, | 184 | .emif_sdram_config_ext = 0xc163, |
| 185 | }; | 185 | }; |
| 186 | 186 | ||
| 187 | const struct emif_regs ddr3_emif_regs_400Mhz = { | 187 | const struct emif_regs ddr3_emif_regs_400Mhz = { |
| 188 | .sdram_config = 0x638413B2, | 188 | .sdram_config = 0x638413B2, |
| 189 | .ref_ctrl = 0x00000C30, | 189 | .ref_ctrl = 0x00000C30, |
| 190 | .sdram_tim1 = 0xEAAAD4DB, | 190 | .sdram_tim1 = 0xEAAAD4DB, |
| 191 | .sdram_tim2 = 0x266B7FDA, | 191 | .sdram_tim2 = 0x266B7FDA, |
| 192 | .sdram_tim3 = 0x107F8678, | 192 | .sdram_tim3 = 0x107F8678, |
| 193 | .read_idle_ctrl = 0x00050000, | 193 | .read_idle_ctrl = 0x00050000, |
| 194 | .zq_config = 0x50074BE4, | 194 | .zq_config = 0x50074BE4, |
| 195 | .temp_alert_config = 0x0, | 195 | .temp_alert_config = 0x0, |
| 196 | .emif_ddr_phy_ctlr_1 = 0x0E004008, | 196 | .emif_ddr_phy_ctlr_1 = 0x0E004008, |
| 197 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, | 197 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 198 | .emif_ddr_ext_phy_ctrl_2 = 0x00400040, | 198 | .emif_ddr_ext_phy_ctrl_2 = 0x00400040, |
| 199 | .emif_ddr_ext_phy_ctrl_3 = 0x00400040, | 199 | .emif_ddr_ext_phy_ctrl_3 = 0x00400040, |
| 200 | .emif_ddr_ext_phy_ctrl_4 = 0x00400040, | 200 | .emif_ddr_ext_phy_ctrl_4 = 0x00400040, |
| 201 | .emif_ddr_ext_phy_ctrl_5 = 0x00400040, | 201 | .emif_ddr_ext_phy_ctrl_5 = 0x00400040, |
| 202 | .emif_rd_wr_lvl_rmp_win = 0x0, | 202 | .emif_rd_wr_lvl_rmp_win = 0x0, |
| 203 | .emif_rd_wr_lvl_rmp_ctl = 0x0, | 203 | .emif_rd_wr_lvl_rmp_ctl = 0x0, |
| 204 | .emif_rd_wr_lvl_ctl = 0x0, | 204 | .emif_rd_wr_lvl_ctl = 0x0, |
| 205 | .emif_rd_wr_exec_thresh = 0x80000405, | 205 | .emif_rd_wr_exec_thresh = 0x80000405, |
| 206 | .emif_prio_class_serv_map = 0x80000001, | 206 | .emif_prio_class_serv_map = 0x80000001, |
| 207 | .emif_connect_id_serv_1_map = 0x80000094, | 207 | .emif_connect_id_serv_1_map = 0x80000094, |
| 208 | .emif_connect_id_serv_2_map = 0x00000000, | 208 | .emif_connect_id_serv_2_map = 0x00000000, |
| 209 | .emif_cos_config = 0x000FFFFF | 209 | .emif_cos_config = 0x000FFFFF |
| 210 | }; | 210 | }; |
| 211 | 211 | ||
| 212 | /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ | 212 | /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ |
| 213 | const struct emif_regs ddr3_emif_regs_400Mhz_beta = { | 213 | const struct emif_regs ddr3_emif_regs_400Mhz_beta = { |
| 214 | .sdram_config = 0x638413B2, | 214 | .sdram_config = 0x638413B2, |
| 215 | .ref_ctrl = 0x00000C30, | 215 | .ref_ctrl = 0x00000C30, |
| 216 | .sdram_tim1 = 0xEAAAD4DB, | 216 | .sdram_tim1 = 0xEAAAD4DB, |
| 217 | .sdram_tim2 = 0x266B7FDA, | 217 | .sdram_tim2 = 0x266B7FDA, |
| 218 | .sdram_tim3 = 0x107F8678, | 218 | .sdram_tim3 = 0x107F8678, |
| 219 | .read_idle_ctrl = 0x00050000, | 219 | .read_idle_ctrl = 0x00050000, |
| 220 | .zq_config = 0x50074BE4, | 220 | .zq_config = 0x50074BE4, |
| 221 | .temp_alert_config = 0x0, | 221 | .temp_alert_config = 0x0, |
| 222 | .emif_ddr_phy_ctlr_1 = 0x0E004008, | 222 | .emif_ddr_phy_ctlr_1 = 0x0E004008, |
| 223 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, | 223 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 224 | .emif_ddr_ext_phy_ctrl_2 = 0x00000065, | 224 | .emif_ddr_ext_phy_ctrl_2 = 0x00000065, |
| 225 | .emif_ddr_ext_phy_ctrl_3 = 0x00000091, | 225 | .emif_ddr_ext_phy_ctrl_3 = 0x00000091, |
| 226 | .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, | 226 | .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, |
| 227 | .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, | 227 | .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, |
| 228 | .emif_rd_wr_exec_thresh = 0x80000405, | 228 | .emif_rd_wr_exec_thresh = 0x80000405, |
| 229 | .emif_prio_class_serv_map = 0x80000001, | 229 | .emif_prio_class_serv_map = 0x80000001, |
| 230 | .emif_connect_id_serv_1_map = 0x80000094, | 230 | .emif_connect_id_serv_1_map = 0x80000094, |
| 231 | .emif_connect_id_serv_2_map = 0x00000000, | 231 | .emif_connect_id_serv_2_map = 0x00000000, |
| 232 | .emif_cos_config = 0x000FFFFF | 232 | .emif_cos_config = 0x000FFFFF |
| 233 | }; | 233 | }; |
| 234 | 234 | ||
| 235 | /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ | 235 | /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ |
| 236 | const struct emif_regs ddr3_emif_regs_400Mhz_production = { | 236 | const struct emif_regs ddr3_emif_regs_400Mhz_production = { |
| 237 | .sdram_config = 0x638413B2, | 237 | .sdram_config = 0x638413B2, |
| 238 | .ref_ctrl = 0x00000C30, | 238 | .ref_ctrl = 0x00000C30, |
| 239 | .sdram_tim1 = 0xEAAAD4DB, | 239 | .sdram_tim1 = 0xEAAAD4DB, |
| 240 | .sdram_tim2 = 0x266B7FDA, | 240 | .sdram_tim2 = 0x266B7FDA, |
| 241 | .sdram_tim3 = 0x107F8678, | 241 | .sdram_tim3 = 0x107F8678, |
| 242 | .read_idle_ctrl = 0x00050000, | 242 | .read_idle_ctrl = 0x00050000, |
| 243 | .zq_config = 0x50074BE4, | 243 | .zq_config = 0x50074BE4, |
| 244 | .temp_alert_config = 0x0, | 244 | .temp_alert_config = 0x0, |
| 245 | .emif_ddr_phy_ctlr_1 = 0x0E004008, | 245 | .emif_ddr_phy_ctlr_1 = 0x0E004008, |
| 246 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, | 246 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 247 | .emif_ddr_ext_phy_ctrl_2 = 0x00000066, | 247 | .emif_ddr_ext_phy_ctrl_2 = 0x00000066, |
| 248 | .emif_ddr_ext_phy_ctrl_3 = 0x00000091, | 248 | .emif_ddr_ext_phy_ctrl_3 = 0x00000091, |
| 249 | .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, | 249 | .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, |
| 250 | .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, | 250 | .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, |
| 251 | .emif_rd_wr_exec_thresh = 0x80000405, | 251 | .emif_rd_wr_exec_thresh = 0x80000405, |
| 252 | .emif_prio_class_serv_map = 0x80000001, | 252 | .emif_prio_class_serv_map = 0x80000001, |
| 253 | .emif_connect_id_serv_1_map = 0x80000094, | 253 | .emif_connect_id_serv_1_map = 0x80000094, |
| 254 | .emif_connect_id_serv_2_map = 0x00000000, | 254 | .emif_connect_id_serv_2_map = 0x00000000, |
| 255 | .emif_cos_config = 0x000FFFFF | 255 | .emif_cos_config = 0x000FFFFF |
| 256 | }; | 256 | }; |
| 257 | 257 | ||
| 258 | static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { | 258 | static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { |
| 259 | .sdram_config = 0x638413b2, | 259 | .sdram_config = 0x638413b2, |
| 260 | .sdram_config2 = 0x00000000, | 260 | .sdram_config2 = 0x00000000, |
| 261 | .ref_ctrl = 0x00000c30, | 261 | .ref_ctrl = 0x00000c30, |
| 262 | .sdram_tim1 = 0xeaaad4db, | 262 | .sdram_tim1 = 0xeaaad4db, |
| 263 | .sdram_tim2 = 0x266b7fda, | 263 | .sdram_tim2 = 0x266b7fda, |
| 264 | .sdram_tim3 = 0x107f8678, | 264 | .sdram_tim3 = 0x107f8678, |
| 265 | .read_idle_ctrl = 0x00050000, | 265 | .read_idle_ctrl = 0x00050000, |
| 266 | .zq_config = 0x50074be4, | 266 | .zq_config = 0x50074be4, |
| 267 | .temp_alert_config = 0x0, | 267 | .temp_alert_config = 0x0, |
| 268 | .emif_ddr_phy_ctlr_1 = 0x0e084008, | 268 | .emif_ddr_phy_ctlr_1 = 0x0e084008, |
| 269 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, | 269 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 270 | .emif_ddr_ext_phy_ctrl_2 = 0x89, | 270 | .emif_ddr_ext_phy_ctrl_2 = 0x89, |
| 271 | .emif_ddr_ext_phy_ctrl_3 = 0x90, | 271 | .emif_ddr_ext_phy_ctrl_3 = 0x90, |
| 272 | .emif_ddr_ext_phy_ctrl_4 = 0x8e, | 272 | .emif_ddr_ext_phy_ctrl_4 = 0x8e, |
| 273 | .emif_ddr_ext_phy_ctrl_5 = 0x8d, | 273 | .emif_ddr_ext_phy_ctrl_5 = 0x8d, |
| 274 | .emif_rd_wr_lvl_rmp_win = 0x0, | 274 | .emif_rd_wr_lvl_rmp_win = 0x0, |
| 275 | .emif_rd_wr_lvl_rmp_ctl = 0x00000000, | 275 | .emif_rd_wr_lvl_rmp_ctl = 0x00000000, |
| 276 | .emif_rd_wr_lvl_ctl = 0x00000000, | 276 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 277 | .emif_rd_wr_exec_thresh = 0x80000000, | 277 | .emif_rd_wr_exec_thresh = 0x80000000, |
| 278 | .emif_prio_class_serv_map = 0x80000001, | 278 | .emif_prio_class_serv_map = 0x80000001, |
| 279 | .emif_connect_id_serv_1_map = 0x80000094, | 279 | .emif_connect_id_serv_1_map = 0x80000094, |
| 280 | .emif_connect_id_serv_2_map = 0x00000000, | 280 | .emif_connect_id_serv_2_map = 0x00000000, |
| 281 | .emif_cos_config = 0x000FFFFF | 281 | .emif_cos_config = 0x000FFFFF |
| 282 | }; | 282 | }; |
| 283 | 283 | ||
| 284 | static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { | 284 | static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { |
| 285 | .sdram_config = 0x61a11b32, | 285 | .sdram_config = 0x61a11b32, |
| 286 | .sdram_config2 = 0x00000000, | 286 | .sdram_config2 = 0x00000000, |
| 287 | .ref_ctrl = 0x00000c30, | 287 | .ref_ctrl = 0x00000c30, |
| 288 | .sdram_tim1 = 0xeaaad4db, | 288 | .sdram_tim1 = 0xeaaad4db, |
| 289 | .sdram_tim2 = 0x266b7fda, | 289 | .sdram_tim2 = 0x266b7fda, |
| 290 | .sdram_tim3 = 0x107f8678, | 290 | .sdram_tim3 = 0x107f8678, |
| 291 | .read_idle_ctrl = 0x00050000, | 291 | .read_idle_ctrl = 0x00050000, |
| 292 | .zq_config = 0x50074be4, | 292 | .zq_config = 0x50074be4, |
| 293 | .temp_alert_config = 0x00000000, | 293 | .temp_alert_config = 0x00000000, |
| 294 | .emif_ddr_phy_ctlr_1 = 0x00008009, | 294 | .emif_ddr_phy_ctlr_1 = 0x00008009, |
| 295 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, | 295 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 296 | .emif_ddr_ext_phy_ctrl_2 = 0x00000040, | 296 | .emif_ddr_ext_phy_ctrl_2 = 0x00000040, |
| 297 | .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, | 297 | .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, |
| 298 | .emif_ddr_ext_phy_ctrl_4 = 0x00000051, | 298 | .emif_ddr_ext_phy_ctrl_4 = 0x00000051, |
| 299 | .emif_ddr_ext_phy_ctrl_5 = 0x00000051, | 299 | .emif_ddr_ext_phy_ctrl_5 = 0x00000051, |
| 300 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | 300 | .emif_rd_wr_lvl_rmp_win = 0x00000000, |
| 301 | .emif_rd_wr_lvl_rmp_ctl = 0x00000000, | 301 | .emif_rd_wr_lvl_rmp_ctl = 0x00000000, |
| 302 | .emif_rd_wr_lvl_ctl = 0x00000000, | 302 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 303 | .emif_rd_wr_exec_thresh = 0x00000405, | 303 | .emif_rd_wr_exec_thresh = 0x00000405, |
| 304 | .emif_prio_class_serv_map = 0x00000000, | 304 | .emif_prio_class_serv_map = 0x00000000, |
| 305 | .emif_connect_id_serv_1_map = 0x00000000, | 305 | .emif_connect_id_serv_1_map = 0x00000000, |
| 306 | .emif_connect_id_serv_2_map = 0x00000000, | 306 | .emif_connect_id_serv_2_map = 0x00000000, |
| 307 | .emif_cos_config = 0x00ffffff | 307 | .emif_cos_config = 0x00ffffff |
| 308 | }; | 308 | }; |
| 309 | 309 | ||
| 310 | static const struct emif_regs ddr3_smarc80_emif_regs_400Mhz = { | 310 | static const struct emif_regs ddr3_smarc80_emif_regs_400Mhz = { |
| 311 | .sdram_config = 0x63841372, | 311 | .sdram_config = 0x63841372, |
| 312 | .sdram_config2 = 0x00000000, | 312 | .sdram_config2 = 0x00000000, |
| 313 | .ref_ctrl = 0x00000c30, | 313 | .ref_ctrl = 0x00000c30, |
| 314 | .sdram_tim1 = 0xeaaad4db, | 314 | .sdram_tim1 = 0xeaaad4db, |
| 315 | .sdram_tim2 = 0x266b7fda, | 315 | .sdram_tim2 = 0x266b7fda, |
| 316 | .sdram_tim3 = 0x107f8678, | 316 | .sdram_tim3 = 0x107f8678, |
| 317 | .read_idle_ctrl = 0x00050000, | 317 | .read_idle_ctrl = 0x00050000, |
| 318 | .zq_config = 0x50074be4, | 318 | .zq_config = 0x50074be4, |
| 319 | .temp_alert_config = 0x0, | 319 | .temp_alert_config = 0x0, |
| 320 | .emif_ddr_phy_ctlr_1 = 0x0e084008, | 320 | .emif_ddr_phy_ctlr_1 = 0x0e084008, |
| 321 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, | 321 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 322 | .emif_ddr_ext_phy_ctrl_2 = 0x89, | 322 | .emif_ddr_ext_phy_ctrl_2 = 0x89, |
| 323 | .emif_ddr_ext_phy_ctrl_3 = 0x90, | 323 | .emif_ddr_ext_phy_ctrl_3 = 0x90, |
| 324 | .emif_ddr_ext_phy_ctrl_4 = 0x8e, | 324 | .emif_ddr_ext_phy_ctrl_4 = 0x8e, |
| 325 | .emif_ddr_ext_phy_ctrl_5 = 0x8d, | 325 | .emif_ddr_ext_phy_ctrl_5 = 0x8d, |
| 326 | .emif_rd_wr_lvl_rmp_win = 0x0, | 326 | .emif_rd_wr_lvl_rmp_win = 0x0, |
| 327 | .emif_rd_wr_lvl_rmp_ctl = 0x00000000, | 327 | .emif_rd_wr_lvl_rmp_ctl = 0x00000000, |
| 328 | .emif_rd_wr_lvl_ctl = 0x00000000, | 328 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 329 | .emif_rd_wr_exec_thresh = 0x80000000, | 329 | .emif_rd_wr_exec_thresh = 0x80000000, |
| 330 | .emif_prio_class_serv_map = 0x80000001, | 330 | .emif_prio_class_serv_map = 0x80000001, |
| 331 | .emif_connect_id_serv_1_map = 0x80000094, | 331 | .emif_connect_id_serv_1_map = 0x80000094, |
| 332 | .emif_connect_id_serv_2_map = 0x00000000, | 332 | .emif_connect_id_serv_2_map = 0x00000000, |
| 333 | .emif_cos_config = 0x000FFFFF | 333 | .emif_cos_config = 0x000FFFFF |
| 334 | }; | 334 | }; |
| 335 | 335 | ||
| 336 | static const struct emif_regs ddr3_smarc1g_emif_regs_400Mhz = { | 336 | static const struct emif_regs ddr3_smarc1g_emif_regs_400Mhz = { |
| 337 | .sdram_config = 0x638413b2, | 337 | .sdram_config = 0x638413b2, |
| 338 | .sdram_config2 = 0x00000000, | 338 | .sdram_config2 = 0x00000000, |
| 339 | .ref_ctrl = 0x00000c30, | 339 | .ref_ctrl = 0x00000c30, |
| 340 | .sdram_tim1 = 0xeaaad4db, | 340 | .sdram_tim1 = 0xeaaad4db, |
| 341 | .sdram_tim2 = 0x266b7fda, | 341 | .sdram_tim2 = 0x266b7fda, |
| 342 | .sdram_tim3 = 0x107f8678, | 342 | .sdram_tim3 = 0x107f8678, |
| 343 | .read_idle_ctrl = 0x00050000, | 343 | .read_idle_ctrl = 0x00050000, |
| 344 | .zq_config = 0x50074be4, | 344 | .zq_config = 0x50074be4, |
| 345 | .temp_alert_config = 0x0, | 345 | .temp_alert_config = 0x0, |
| 346 | .emif_ddr_phy_ctlr_1 = 0x0e084008, | 346 | .emif_ddr_phy_ctlr_1 = 0x0e084008, |
| 347 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, | 347 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 348 | .emif_ddr_ext_phy_ctrl_2 = 0x89, | 348 | .emif_ddr_ext_phy_ctrl_2 = 0x89, |
| 349 | .emif_ddr_ext_phy_ctrl_3 = 0x90, | 349 | .emif_ddr_ext_phy_ctrl_3 = 0x90, |
| 350 | .emif_ddr_ext_phy_ctrl_4 = 0x8e, | 350 | .emif_ddr_ext_phy_ctrl_4 = 0x8e, |
| 351 | .emif_ddr_ext_phy_ctrl_5 = 0x8d, | 351 | .emif_ddr_ext_phy_ctrl_5 = 0x8d, |
| 352 | .emif_rd_wr_lvl_rmp_win = 0x0, | 352 | .emif_rd_wr_lvl_rmp_win = 0x0, |
| 353 | .emif_rd_wr_lvl_rmp_ctl = 0x00000000, | 353 | .emif_rd_wr_lvl_rmp_ctl = 0x00000000, |
| 354 | .emif_rd_wr_lvl_ctl = 0x00000000, | 354 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 355 | .emif_rd_wr_exec_thresh = 0x80000000, | 355 | .emif_rd_wr_exec_thresh = 0x80000000, |
| 356 | .emif_prio_class_serv_map = 0x80000001, | 356 | .emif_prio_class_serv_map = 0x80000001, |
| 357 | .emif_connect_id_serv_1_map = 0x80000094, | 357 | .emif_connect_id_serv_1_map = 0x80000094, |
| 358 | .emif_connect_id_serv_2_map = 0x00000000, | 358 | .emif_connect_id_serv_2_map = 0x00000000, |
| 359 | .emif_cos_config = 0x000FFFFF | 359 | .emif_cos_config = 0x000FFFFF |
| 360 | }; | 360 | }; |
| 361 | 361 | ||
| 362 | void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) | 362 | void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) |
| 363 | { | 363 | { |
| 364 | if (board_is_eposevm()) { | 364 | if (board_is_eposevm()) { |
| 365 | *regs = ext_phy_ctrl_const_base_lpddr2; | 365 | *regs = ext_phy_ctrl_const_base_lpddr2; |
| 366 | *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); | 366 | *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); |
| 367 | } | 367 | } |
| 368 | 368 | ||
| 369 | return; | 369 | return; |
| 370 | } | 370 | } |
| 371 | 371 | ||
| 372 | const struct dpll_params *get_dpll_ddr_params(void) | 372 | const struct dpll_params *get_dpll_ddr_params(void) |
| 373 | { | 373 | { |
| 374 | int ind = get_sys_clk_index(); | 374 | int ind = get_sys_clk_index(); |
| 375 | 375 | ||
| 376 | if (board_is_eposevm()) | 376 | if (board_is_eposevm()) |
| 377 | return &epos_evm_dpll_ddr[ind]; | 377 | return &epos_evm_dpll_ddr[ind]; |
| 378 | else if (board_is_evm() || board_is_sk() || board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) | 378 | else if (board_is_evm() || board_is_sk() || board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) |
| 379 | return &gp_evm_dpll_ddr; | 379 | return &gp_evm_dpll_ddr; |
| 380 | else if (board_is_idk()) | 380 | else if (board_is_idk()) |
| 381 | return &idk_dpll_ddr; | 381 | return &idk_dpll_ddr; |
| 382 | else | 382 | else |
| 383 | printf(" Board '%s' not supported\n", board_ti_get_name()); | 383 | printf(" Board '%s' not supported\n", board_ti_get_name()); |
| 384 | return &gp_evm_dpll_ddr; | 384 | return &gp_evm_dpll_ddr; |
| 385 | } | 385 | } |
| 386 | 386 | ||
| 387 | 387 | ||
| 388 | /* | 388 | /* |
| 389 | * get_opp_offset: | 389 | * get_opp_offset: |
| 390 | * Returns the index for safest OPP of the device to boot. | 390 | * Returns the index for safest OPP of the device to boot. |
| 391 | * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. | 391 | * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. |
| 392 | * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. | 392 | * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. |
| 393 | * This data is read from dev_attribute register which is e-fused. | 393 | * This data is read from dev_attribute register which is e-fused. |
| 394 | * A'1' in bit indicates OPP disabled and not available, a '0' indicates | 394 | * A'1' in bit indicates OPP disabled and not available, a '0' indicates |
| 395 | * OPP available. Lowest OPP starts with min_off. So returning the | 395 | * OPP available. Lowest OPP starts with min_off. So returning the |
| 396 | * bit with rightmost '0'. | 396 | * bit with rightmost '0'. |
| 397 | */ | 397 | */ |
| 398 | static int get_opp_offset(int max_off, int min_off) | 398 | static int get_opp_offset(int max_off, int min_off) |
| 399 | { | 399 | { |
| 400 | struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; | 400 | struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; |
| 401 | int opp, offset, i; | 401 | int opp, offset, i; |
| 402 | 402 | ||
| 403 | /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ | 403 | /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ |
| 404 | opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; | 404 | opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; |
| 405 | 405 | ||
| 406 | for (i = max_off; i >= min_off; i--) { | 406 | for (i = max_off; i >= min_off; i--) { |
| 407 | offset = opp & (1 << i); | 407 | offset = opp & (1 << i); |
| 408 | if (!offset) | 408 | if (!offset) |
| 409 | return i; | 409 | return i; |
| 410 | } | 410 | } |
| 411 | 411 | ||
| 412 | return min_off; | 412 | return min_off; |
| 413 | } | 413 | } |
| 414 | 414 | ||
| 415 | const struct dpll_params *get_dpll_mpu_params(void) | 415 | const struct dpll_params *get_dpll_mpu_params(void) |
| 416 | { | 416 | { |
| 417 | int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); | 417 | int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); |
| 418 | u32 ind = get_sys_clk_index(); | 418 | u32 ind = get_sys_clk_index(); |
| 419 | 419 | ||
| 420 | return &dpll_mpu[ind][opp]; | 420 | return &dpll_mpu[ind][opp]; |
| 421 | } | 421 | } |
| 422 | 422 | ||
| 423 | const struct dpll_params *get_dpll_core_params(void) | 423 | const struct dpll_params *get_dpll_core_params(void) |
| 424 | { | 424 | { |
| 425 | int ind = get_sys_clk_index(); | 425 | int ind = get_sys_clk_index(); |
| 426 | 426 | ||
| 427 | return &dpll_core[ind]; | 427 | return &dpll_core[ind]; |
| 428 | } | 428 | } |
| 429 | 429 | ||
| 430 | const struct dpll_params *get_dpll_per_params(void) | 430 | const struct dpll_params *get_dpll_per_params(void) |
| 431 | { | 431 | { |
| 432 | int ind = get_sys_clk_index(); | 432 | int ind = get_sys_clk_index(); |
| 433 | 433 | ||
| 434 | return &dpll_per[ind]; | 434 | return &dpll_per[ind]; |
| 435 | } | 435 | } |
| 436 | 436 | ||
| 437 | void scale_vcores_generic(u32 m) | 437 | void scale_vcores_generic(u32 m) |
| 438 | { | 438 | { |
| 439 | int mpu_vdd; | 439 | int mpu_vdd; |
| 440 | 440 | ||
| 441 | if (i2c_probe(TPS65218_CHIP_PM)) | 441 | if (i2c_probe(TPS65218_CHIP_PM)) |
| 442 | return; | 442 | return; |
| 443 | 443 | ||
| 444 | switch (m) { | 444 | switch (m) { |
| 445 | case 1000: | 445 | case 1000: |
| 446 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; | 446 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; |
| 447 | break; | 447 | break; |
| 448 | case 800: | 448 | case 800: |
| 449 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; | 449 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; |
| 450 | break; | 450 | break; |
| 451 | case 720: | 451 | case 720: |
| 452 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; | 452 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; |
| 453 | break; | 453 | break; |
| 454 | case 600: | 454 | case 600: |
| 455 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; | 455 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; |
| 456 | break; | 456 | break; |
| 457 | case 300: | 457 | case 300: |
| 458 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; | 458 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; |
| 459 | break; | 459 | break; |
| 460 | default: | 460 | default: |
| 461 | puts("Unknown MPU clock, not scaling\n"); | 461 | puts("Unknown MPU clock, not scaling\n"); |
| 462 | return; | 462 | return; |
| 463 | } | 463 | } |
| 464 | 464 | ||
| 465 | /* Set DCDC1 (CORE) voltage to 1.1V */ | 465 | /* Set DCDC1 (CORE) voltage to 1.1V */ |
| 466 | if (tps65218_voltage_update(TPS65218_DCDC1, | 466 | if (tps65218_voltage_update(TPS65218_DCDC1, |
| 467 | TPS65218_DCDC_VOLT_SEL_1100MV)) { | 467 | TPS65218_DCDC_VOLT_SEL_1100MV)) { |
| 468 | printf("%s failure\n", __func__); | 468 | printf("%s failure\n", __func__); |
| 469 | return; | 469 | return; |
| 470 | } | 470 | } |
| 471 | 471 | ||
| 472 | /* Set DCDC2 (MPU) voltage */ | 472 | /* Set DCDC2 (MPU) voltage */ |
| 473 | if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { | 473 | if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { |
| 474 | printf("%s failure\n", __func__); | 474 | printf("%s failure\n", __func__); |
| 475 | return; | 475 | return; |
| 476 | } | 476 | } |
| 477 | 477 | ||
| 478 | /* Set DCDC3 (DDR) voltage */ | 478 | /* Set DCDC3 (DDR) voltage */ |
| 479 | if (tps65218_voltage_update(TPS65218_DCDC3, | 479 | if (tps65218_voltage_update(TPS65218_DCDC3, |
| 480 | TPS65218_DCDC3_VOLT_SEL_1350MV)) { | 480 | TPS65218_DCDC3_VOLT_SEL_1350MV)) { |
| 481 | printf("%s failure\n", __func__); | 481 | printf("%s failure\n", __func__); |
| 482 | return; | 482 | return; |
| 483 | } | 483 | } |
| 484 | } | 484 | } |
| 485 | 485 | ||
| 486 | void scale_vcores_idk(u32 m) | 486 | void scale_vcores_idk(u32 m) |
| 487 | { | 487 | { |
| 488 | int mpu_vdd; | 488 | int mpu_vdd; |
| 489 | 489 | ||
| 490 | if (i2c_probe(TPS62362_I2C_ADDR)) | 490 | if (i2c_probe(TPS62362_I2C_ADDR)) |
| 491 | return; | 491 | return; |
| 492 | 492 | ||
| 493 | switch (m) { | 493 | switch (m) { |
| 494 | case 1000: | 494 | case 1000: |
| 495 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; | 495 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; |
| 496 | break; | 496 | break; |
| 497 | case 800: | 497 | case 800: |
| 498 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; | 498 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; |
| 499 | break; | 499 | break; |
| 500 | case 720: | 500 | case 720: |
| 501 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; | 501 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; |
| 502 | break; | 502 | break; |
| 503 | case 600: | 503 | case 600: |
| 504 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; | 504 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; |
| 505 | break; | 505 | break; |
| 506 | case 300: | 506 | case 300: |
| 507 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; | 507 | mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; |
| 508 | break; | 508 | break; |
| 509 | default: | 509 | default: |
| 510 | puts("Unknown MPU clock, not scaling\n"); | 510 | puts("Unknown MPU clock, not scaling\n"); |
| 511 | return; | 511 | return; |
| 512 | } | 512 | } |
| 513 | 513 | ||
| 514 | /* Set VDD_MPU voltage */ | 514 | /* Set VDD_MPU voltage */ |
| 515 | if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { | 515 | if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { |
| 516 | printf("%s failure\n", __func__); | 516 | printf("%s failure\n", __func__); |
| 517 | return; | 517 | return; |
| 518 | } | 518 | } |
| 519 | } | 519 | } |
| 520 | 520 | ||
| 521 | void gpi2c_init(void) | 521 | void gpi2c_init(void) |
| 522 | { | 522 | { |
| 523 | /* When needed to be invoked prior to BSS initialization */ | 523 | /* When needed to be invoked prior to BSS initialization */ |
| 524 | static bool first_time = true; | 524 | static bool first_time = true; |
| 525 | 525 | ||
| 526 | if (first_time) { | 526 | if (first_time) { |
| 527 | enable_i2c1_pin_mux(); | 527 | enable_i2c1_pin_mux(); |
| 528 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, | 528 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, |
| 529 | CONFIG_SYS_OMAP24_I2C_SLAVE); | 529 | CONFIG_SYS_OMAP24_I2C_SLAVE); |
| 530 | first_time = false; | 530 | first_time = false; |
| 531 | } | 531 | } |
| 532 | } | 532 | } |
| 533 | 533 | ||
| 534 | void scale_vcores(void) | 534 | void scale_vcores(void) |
| 535 | { | 535 | { |
| 536 | const struct dpll_params *mpu_params; | 536 | const struct dpll_params *mpu_params; |
| 537 | 537 | ||
| 538 | /* Ensure I2C is initialized for PMIC configuration */ | 538 | /* Ensure I2C is initialized for PMIC configuration */ |
| 539 | gpi2c_init(); | 539 | gpi2c_init(); |
| 540 | 540 | ||
| 541 | /* Get the frequency */ | 541 | /* Get the frequency */ |
| 542 | mpu_params = get_dpll_mpu_params(); | 542 | mpu_params = get_dpll_mpu_params(); |
| 543 | 543 | ||
| 544 | if (board_is_idk()) | 544 | if (board_is_idk()) |
| 545 | scale_vcores_idk(mpu_params->m); | 545 | scale_vcores_idk(mpu_params->m); |
| 546 | else | 546 | else |
| 547 | scale_vcores_generic(mpu_params->m); | 547 | scale_vcores_generic(mpu_params->m); |
| 548 | } | 548 | } |
| 549 | 549 | ||
| 550 | void set_uart_mux_conf(void) | 550 | void set_uart_mux_conf(void) |
| 551 | { | 551 | { |
| 552 | #if CONFIG_CONS_INDEX == 1 | 552 | #if CONFIG_CONS_INDEX == 1 |
| 553 | enable_uart0_pin_mux(); | 553 | enable_uart0_pin_mux(); |
| 554 | #elif CONFIG_CONS_INDEX == 2 | 554 | #elif CONFIG_CONS_INDEX == 2 |
| 555 | enable_uart1_pin_mux(); | 555 | enable_uart1_pin_mux(); |
| 556 | #elif CONFIG_CONS_INDEX == 3 | 556 | #elif CONFIG_CONS_INDEX == 3 |
| 557 | enable_uart2_pin_mux(); | 557 | enable_uart2_pin_mux(); |
| 558 | #elif CONFIG_CONS_INDEX == 4 | 558 | #elif CONFIG_CONS_INDEX == 4 |
| 559 | enable_uart3_pin_mux(); | 559 | enable_uart3_pin_mux(); |
| 560 | #elif CONFIG_CONS_INDEX == 5 | 560 | #elif CONFIG_CONS_INDEX == 5 |
| 561 | enable_uart4_pin_mux(); | 561 | enable_uart4_pin_mux(); |
| 562 | #elif CONFIG_CONS_INDEX == 6 | 562 | #elif CONFIG_CONS_INDEX == 6 |
| 563 | enable_uart5_pin_mux(); | 563 | enable_uart5_pin_mux(); |
| 564 | #endif | 564 | #endif |
| 565 | } | 565 | } |
| 566 | 566 | ||
| 567 | void set_mux_conf_regs(void) | 567 | void set_mux_conf_regs(void) |
| 568 | { | 568 | { |
| 569 | enable_board_pin_mux(); | 569 | enable_board_pin_mux(); |
| 570 | } | 570 | } |
| 571 | 571 | ||
| 572 | static void enable_vtt_regulator(void) | 572 | static void enable_vtt_regulator(void) |
| 573 | { | 573 | { |
| 574 | u32 temp; | 574 | u32 temp; |
| 575 | 575 | ||
| 576 | /* enable module */ | 576 | /* enable module */ |
| 577 | writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); | 577 | writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); |
| 578 | 578 | ||
| 579 | /* enable output for GPIO5_7 */ | 579 | /* enable output for GPIO5_7 */ |
| 580 | writel(GPIO_SETDATAOUT(7), | 580 | writel(GPIO_SETDATAOUT(7), |
| 581 | AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); | 581 | AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); |
| 582 | temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); | 582 | temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); |
| 583 | temp = temp & ~(GPIO_OE_ENABLE(7)); | 583 | temp = temp & ~(GPIO_OE_ENABLE(7)); |
| 584 | writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); | 584 | writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); |
| 585 | } | 585 | } |
| 586 | 586 | ||
| 587 | enum { | 587 | enum { |
| 588 | RTC_BOARD_EPOS = 1, | 588 | RTC_BOARD_EPOS = 1, |
| 589 | RTC_BOARD_EVM14, | 589 | RTC_BOARD_EVM14, |
| 590 | RTC_BOARD_EVM12, | 590 | RTC_BOARD_EVM12, |
| 591 | RTC_BOARD_GPEVM, | 591 | RTC_BOARD_GPEVM, |
| 592 | RTC_BOARD_SK, | 592 | RTC_BOARD_SK, |
| 593 | RTC_BOARD_SMARC_T437X_800, | 593 | RTC_BOARD_SMARC_T437X_800, |
| 594 | RTC_BOARD_SMARC_T437X_01G, | 594 | RTC_BOARD_SMARC_T437X_01G, |
| 595 | }; | 595 | }; |
| 596 | 596 | ||
| 597 | /* | 597 | /* |
| 598 | * In the rtc_only boot path we have the board type info in the rtc scratch pad | 598 | * In the rtc_only boot path we have the board type info in the rtc scratch pad |
| 599 | * register hence we bypass the costly i2c reads to eeprom and directly program | 599 | * register hence we bypass the costly i2c reads to eeprom and directly program |
| 600 | * the board name string | 600 | * the board name string |
| 601 | */ | 601 | */ |
| 602 | void rtc_only_update_board_type(u32 btype) | 602 | void rtc_only_update_board_type(u32 btype) |
| 603 | { | 603 | { |
| 604 | const char *name = ""; | 604 | const char *name = ""; |
| 605 | const char *rev = "1.0"; | 605 | const char *rev = "1.0"; |
| 606 | 606 | ||
| 607 | switch (btype) { | 607 | switch (btype) { |
| 608 | case RTC_BOARD_EPOS: | 608 | case RTC_BOARD_EPOS: |
| 609 | name = "AM43EPOS"; | 609 | name = "AM43EPOS"; |
| 610 | break; | 610 | break; |
| 611 | case RTC_BOARD_EVM14: | 611 | case RTC_BOARD_EVM14: |
| 612 | name = "AM43__GP"; | 612 | name = "AM43__GP"; |
| 613 | rev = "1.4"; | 613 | rev = "1.4"; |
| 614 | break; | 614 | break; |
| 615 | case RTC_BOARD_EVM12: | 615 | case RTC_BOARD_EVM12: |
| 616 | name = "AM43__GP"; | 616 | name = "AM43__GP"; |
| 617 | rev = "1.2"; | 617 | rev = "1.2"; |
| 618 | break; | 618 | break; |
| 619 | case RTC_BOARD_GPEVM: | 619 | case RTC_BOARD_GPEVM: |
| 620 | name = "AM43__GP"; | 620 | name = "AM43__GP"; |
| 621 | break; | 621 | break; |
| 622 | case RTC_BOARD_SK: | 622 | case RTC_BOARD_SK: |
| 623 | name = "AM43__SK"; | 623 | name = "AM43__SK"; |
| 624 | break; | 624 | break; |
| 625 | case RTC_BOARD_SMARC_T437X_800: | 625 | case RTC_BOARD_SMARC_T437X_800: |
| 626 | name = "SMCT4X80"; | 626 | name = "SMCT4X80"; |
| 627 | break; | 627 | break; |
| 628 | case RTC_BOARD_SMARC_T437X_01G: | 628 | case RTC_BOARD_SMARC_T437X_01G: |
| 629 | name = "SMCT4X1G"; | 629 | name = "SMCT4X1G"; |
| 630 | break; | 630 | break; |
| 631 | } | 631 | } |
| 632 | ti_i2c_eeprom_am_set(name, rev); | 632 | ti_i2c_eeprom_am_set(name, rev); |
| 633 | } | 633 | } |
| 634 | 634 | ||
| 635 | u32 rtc_only_get_board_type(void) | 635 | u32 rtc_only_get_board_type(void) |
| 636 | { | 636 | { |
| 637 | if (board_is_eposevm()) | 637 | if (board_is_eposevm()) |
| 638 | return RTC_BOARD_EPOS; | 638 | return RTC_BOARD_EPOS; |
| 639 | else if (board_is_evm_14_or_later()) | 639 | else if (board_is_evm_14_or_later()) |
| 640 | return RTC_BOARD_EVM14; | 640 | return RTC_BOARD_EVM14; |
| 641 | else if (board_is_evm_12_or_later()) | 641 | else if (board_is_evm_12_or_later()) |
| 642 | return RTC_BOARD_EVM12; | 642 | return RTC_BOARD_EVM12; |
| 643 | else if (board_is_gpevm()) | 643 | else if (board_is_gpevm()) |
| 644 | return RTC_BOARD_GPEVM; | 644 | return RTC_BOARD_GPEVM; |
| 645 | else if (board_is_sk()) | 645 | else if (board_is_sk()) |
| 646 | return RTC_BOARD_SK; | 646 | return RTC_BOARD_SK; |
| 647 | else if (board_is_smarc_t437x_800()) | 647 | else if (board_is_smarc_t437x_800()) |
| 648 | return RTC_BOARD_SMARC_T437X_800; | 648 | return RTC_BOARD_SMARC_T437X_800; |
| 649 | else if (board_is_smarc_t437x_01g()) | 649 | else if (board_is_smarc_t437x_01g()) |
| 650 | return RTC_BOARD_SMARC_T437X_01G; | 650 | return RTC_BOARD_SMARC_T437X_01G; |
| 651 | 651 | ||
| 652 | return 0; | 652 | return 0; |
| 653 | } | 653 | } |
| 654 | 654 | ||
| 655 | void sdram_init(void) | 655 | void sdram_init(void) |
| 656 | { | 656 | { |
| 657 | /* | 657 | /* |
| 658 | * EPOS EVM has 1GB LPDDR2 connected to EMIF. | 658 | * EPOS EVM has 1GB LPDDR2 connected to EMIF. |
| 659 | * GP EMV has 1GB DDR3 connected to EMIF | 659 | * GP EMV has 1GB DDR3 connected to EMIF |
| 660 | * along with VTT regulator. | 660 | * along with VTT regulator. |
| 661 | */ | 661 | */ |
| 662 | if (board_is_eposevm()) { | 662 | if (board_is_eposevm()) { |
| 663 | config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); | 663 | config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); |
| 664 | } else if (board_is_evm_14_or_later()) { | 664 | } else if (board_is_evm_14_or_later()) { |
| 665 | enable_vtt_regulator(); | 665 | enable_vtt_regulator(); |
| 666 | config_ddr(0, &ioregs_ddr3, NULL, NULL, | 666 | config_ddr(0, &ioregs_ddr3, NULL, NULL, |
| 667 | &ddr3_emif_regs_400Mhz_production, 0); | 667 | &ddr3_emif_regs_400Mhz_production, 0); |
| 668 | } else if (board_is_evm_12_or_later()) { | 668 | } else if (board_is_evm_12_or_later()) { |
| 669 | enable_vtt_regulator(); | 669 | enable_vtt_regulator(); |
| 670 | config_ddr(0, &ioregs_ddr3, NULL, NULL, | 670 | config_ddr(0, &ioregs_ddr3, NULL, NULL, |
| 671 | &ddr3_emif_regs_400Mhz_beta, 0); | 671 | &ddr3_emif_regs_400Mhz_beta, 0); |
| 672 | } else if (board_is_evm()) { | 672 | } else if (board_is_evm()) { |
| 673 | enable_vtt_regulator(); | 673 | enable_vtt_regulator(); |
| 674 | config_ddr(0, &ioregs_ddr3, NULL, NULL, | 674 | config_ddr(0, &ioregs_ddr3, NULL, NULL, |
| 675 | &ddr3_emif_regs_400Mhz, 0); | 675 | &ddr3_emif_regs_400Mhz, 0); |
| 676 | } else if (board_is_sk()) { | 676 | } else if (board_is_sk()) { |
| 677 | config_ddr(400, &ioregs_ddr3, NULL, NULL, | 677 | config_ddr(400, &ioregs_ddr3, NULL, NULL, |
| 678 | &ddr3_sk_emif_regs_400Mhz, 0); | 678 | &ddr3_sk_emif_regs_400Mhz, 0); |
| 679 | } else if (board_is_idk()) { | 679 | } else if (board_is_idk()) { |
| 680 | config_ddr(400, &ioregs_ddr3, NULL, NULL, | 680 | config_ddr(400, &ioregs_ddr3, NULL, NULL, |
| 681 | &ddr3_idk_emif_regs_400Mhz, 0); | 681 | &ddr3_idk_emif_regs_400Mhz, 0); |
| 682 | } else if (board_is_smarc_t437x_800()) { | 682 | } else if (board_is_smarc_t437x_800()) { |
| 683 | config_ddr(400, &ioregs_ddr3, NULL, NULL, | 683 | config_ddr(400, &ioregs_ddr3, NULL, NULL, |
| 684 | &ddr3_smarc80_emif_regs_400Mhz, 0); | 684 | &ddr3_smarc80_emif_regs_400Mhz, 0); |
| 685 | } else if (board_is_smarc_t437x_01g()) { | 685 | } else if (board_is_smarc_t437x_01g()) { |
| 686 | config_ddr(400, &ioregs_ddr3, NULL, NULL, | 686 | config_ddr(400, &ioregs_ddr3, NULL, NULL, |
| 687 | &ddr3_smarc1g_emif_regs_400Mhz, 0); | 687 | &ddr3_smarc1g_emif_regs_400Mhz, 0); |
| 688 | } else { | 688 | } else { |
| 689 | config_ddr(400, &ioregs_ddr3, NULL, NULL, | 689 | config_ddr(400, &ioregs_ddr3, NULL, NULL, |
| 690 | &ddr3_smarc80_emif_regs_400Mhz, 0); | 690 | &ddr3_smarc80_emif_regs_400Mhz, 0); |
| 691 | } | 691 | } |
| 692 | } | 692 | } |
| 693 | #endif | 693 | #endif |
| 694 | 694 | ||
| 695 | /* setup board specific PMIC */ | 695 | /* setup board specific PMIC */ |
| 696 | int power_init_board(void) | 696 | int power_init_board(void) |
| 697 | { | 697 | { |
| 698 | struct pmic *p; | 698 | struct pmic *p; |
| 699 | 699 | ||
| 700 | if (board_is_idk()) { | 700 | if (board_is_idk()) { |
| 701 | power_tps62362_init(I2C_PMIC); | 701 | power_tps62362_init(I2C_PMIC); |
| 702 | p = pmic_get("TPS62362"); | 702 | p = pmic_get("TPS62362"); |
| 703 | if (p && !pmic_probe(p)) | 703 | if (p && !pmic_probe(p)) |
| 704 | puts("PMIC: TPS62362\n"); | 704 | puts("PMIC: TPS62362\n"); |
| 705 | } else { | 705 | } else { |
| 706 | power_tps65218_init(I2C_PMIC); | 706 | power_tps65218_init(I2C_PMIC); |
| 707 | p = pmic_get("TPS65218_PMIC"); | 707 | p = pmic_get("TPS65218_PMIC"); |
| 708 | if (p && !pmic_probe(p)) | 708 | if (p && !pmic_probe(p)) |
| 709 | puts("PMIC: TPS65218\n"); | 709 | puts("PMIC: TPS65218\n"); |
| 710 | } | 710 | } |
| 711 | 711 | ||
| 712 | return 0; | 712 | return 0; |
| 713 | } | 713 | } |
| 714 | 714 | ||
| 715 | int board_init(void) | 715 | int board_init(void) |
| 716 | { | 716 | { |
| 717 | u32 sys_reboot; | 717 | u32 sys_reboot; |
| 718 | 718 | ||
| 719 | sys_reboot = readl(PRM_RSTST); | 719 | sys_reboot = readl(PRM_RSTST); |
| 720 | if (sys_reboot & (1 << 9)) | 720 | if (sys_reboot & (1 << 9)) |
| 721 | puts("Reset Source: IcePick reset has occurred.\n"); | 721 | puts("Reset Source: IcePick reset has occurred.\n"); |
| 722 | 722 | ||
| 723 | if (sys_reboot & (1 << 5)) | 723 | if (sys_reboot & (1 << 5)) |
| 724 | puts("Reset Source: Global external warm reset has occurred.\n"); | 724 | puts("Reset Source: Global external warm reset has occurred.\n"); |
| 725 | 725 | ||
| 726 | if (sys_reboot & (1 << 4)) | 726 | if (sys_reboot & (1 << 4)) |
| 727 | puts("Reset Source: watchdog reset has occurred.\n"); | 727 | puts("Reset Source: watchdog reset has occurred.\n"); |
| 728 | 728 | ||
| 729 | if (sys_reboot & (1 << 1)) | 729 | if (sys_reboot & (1 << 1)) |
| 730 | puts("Reset Source: Global warm SW reset has occurred.\n"); | 730 | puts("Reset Source: Global warm SW reset has occurred.\n"); |
| 731 | 731 | ||
| 732 | if (sys_reboot & (1 << 0)) | 732 | if (sys_reboot & (1 << 0)) |
| 733 | puts("Reset Source: Power-on reset has occurred.\n"); | 733 | puts("Reset Source: Power-on reset has occurred.\n"); |
| 734 | 734 | ||
| 735 | struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; | 735 | struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; |
| 736 | u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, | 736 | u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, |
| 737 | modena_init0_bw_integer, modena_init0_watermark_0; | 737 | modena_init0_bw_integer, modena_init0_watermark_0; |
| 738 | 738 | ||
| 739 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; | 739 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
| 740 | gpmc_init(); | 740 | gpmc_init(); |
| 741 | 741 | ||
| 742 | /* Clear all important bits for DSS errata that may need to be tweaked*/ | 742 | /* Clear all important bits for DSS errata that may need to be tweaked*/ |
| 743 | mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & | 743 | mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & |
| 744 | MREQPRIO_0_SAB_INIT0_MASK; | 744 | MREQPRIO_0_SAB_INIT0_MASK; |
| 745 | 745 | ||
| 746 | mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; | 746 | mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; |
| 747 | 747 | ||
| 748 | modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & | 748 | modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & |
| 749 | BW_LIMITER_BW_FRAC_MASK; | 749 | BW_LIMITER_BW_FRAC_MASK; |
| 750 | 750 | ||
| 751 | modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & | 751 | modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & |
| 752 | BW_LIMITER_BW_INT_MASK; | 752 | BW_LIMITER_BW_INT_MASK; |
| 753 | 753 | ||
| 754 | modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & | 754 | modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & |
| 755 | BW_LIMITER_BW_WATERMARK_MASK; | 755 | BW_LIMITER_BW_WATERMARK_MASK; |
| 756 | 756 | ||
| 757 | /* Setting MReq Priority of the DSS*/ | 757 | /* Setting MReq Priority of the DSS*/ |
| 758 | mreqprio_0 |= 0x77; | 758 | mreqprio_0 |= 0x77; |
| 759 | 759 | ||
| 760 | /* | 760 | /* |
| 761 | * Set L3 Fast Configuration Register | 761 | * Set L3 Fast Configuration Register |
| 762 | * Limiting bandwith for ARM core to 700 MBPS | 762 | * Limiting bandwith for ARM core to 700 MBPS |
| 763 | */ | 763 | */ |
| 764 | modena_init0_bw_fractional |= 0x10; | 764 | modena_init0_bw_fractional |= 0x10; |
| 765 | modena_init0_bw_integer |= 0x3; | 765 | modena_init0_bw_integer |= 0x3; |
| 766 | 766 | ||
| 767 | writel(mreqprio_0, &cdev->mreqprio_0); | 767 | writel(mreqprio_0, &cdev->mreqprio_0); |
| 768 | writel(mreqprio_1, &cdev->mreqprio_1); | 768 | writel(mreqprio_1, &cdev->mreqprio_1); |
| 769 | 769 | ||
| 770 | writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); | 770 | writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); |
| 771 | writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); | 771 | writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); |
| 772 | writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); | 772 | writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); |
| 773 | 773 | ||
| 774 | return 0; | 774 | return 0; |
| 775 | } | 775 | } |
| 776 | 776 | ||
| 777 | #ifdef CONFIG_BOARD_LATE_INIT | 777 | #ifdef CONFIG_BOARD_LATE_INIT |
| 778 | int board_late_init(void) | 778 | int board_late_init(void) |
| 779 | { | 779 | { |
| 780 | struct ti_am_eeprom data; | 780 | struct ti_am_eeprom data; |
| 781 | 781 | ||
| 782 | if (board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) { | 782 | if (board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) { |
| 783 | 783 | ||
| 784 | /* Read Board Info from EEPROM */ | 784 | /* Read Board Info from EEPROM */ |
| 785 | puts("-----------------------------------------\n"); | 785 | puts("-----------------------------------------\n"); |
| 786 | printf("Board ID: %.*s\n", | 786 | printf("Board ID: %.*s\n", |
| 787 | sizeof(data.name), board_ti_get_name()); | 787 | sizeof(data.name), board_ti_get_name()); |
| 788 | printf("Board Revision: %.*s\n", | 788 | printf("Board Revision: %.*s\n", |
| 789 | sizeof(data.version), board_ti_get_rev()); | 789 | sizeof(data.version), board_ti_get_rev()); |
| 790 | printf("Board Serial#: %.*s\n", | 790 | printf("Board Serial#: %.*s\n", |
| 791 | sizeof(data.serial), board_ti_get_serial()); | 791 | sizeof(data.serial), board_ti_get_serial()); |
| 792 | puts("-----------------------------------------\n"); | 792 | puts("-----------------------------------------\n"); |
| 793 | 793 | ||
| 794 | } else { | 794 | } else { |
| 795 | puts("Bad EEPROM or unknown board!\n"); | 795 | puts("Bad EEPROM or unknown board!\n"); |
| 796 | return 0; | 796 | return 0; |
| 797 | } | 797 | } |
| 798 | 798 | ||
| 799 | /* LCD and Backlight Enable Pin */ | 799 | /* LCD and Backlight Enable Pin */ |
| 800 | #define GPIO_LCD_BKLT_EN 68 | 800 | #define GPIO_LCD_BKLT_EN 68 |
| 801 | #define GPIO_LCD_PWM_EN 138 | 801 | #define GPIO_LCD_PWM_EN 138 |
| 802 | /* BOOT_SEL Pin */ | 802 | /* BOOT_SEL Pin */ |
| 803 | #define GPIO_BOOT_SEL1 168 | 803 | #define GPIO_BOOT_SEL1 168 |
| 804 | #define GPIO_BOOT_SEL2 169 | 804 | #define GPIO_BOOT_SEL2 169 |
| 805 | #define GPIO_BOOT_SEL3 170 | 805 | #define GPIO_BOOT_SEL3 170 |
| 806 | gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en"); | 806 | gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en"); |
| 807 | gpio_direction_output(GPIO_LCD_BKLT_EN, 1); | 807 | gpio_direction_output(GPIO_LCD_BKLT_EN, 1); |
| 808 | gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en"); | 808 | gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en"); |
| 809 | gpio_direction_output(GPIO_LCD_PWM_EN, 1); | 809 | gpio_direction_output(GPIO_LCD_PWM_EN, 1); |
| 810 | 810 | ||
| 811 | gpio_request(GPIO_BOOT_SEL1, "boot_sel1"); | 811 | gpio_request(GPIO_BOOT_SEL1, "boot_sel1"); |
| 812 | gpio_direction_input(GPIO_BOOT_SEL1); | 812 | gpio_direction_input(GPIO_BOOT_SEL1); |
| 813 | gpio_request(GPIO_BOOT_SEL2, "boot_sel2"); | 813 | gpio_request(GPIO_BOOT_SEL2, "boot_sel2"); |
| 814 | gpio_direction_input(GPIO_BOOT_SEL2); | 814 | gpio_direction_input(GPIO_BOOT_SEL2); |
| 815 | gpio_request(GPIO_BOOT_SEL3, "boot_sel3"); | 815 | gpio_request(GPIO_BOOT_SEL3, "boot_sel3"); |
| 816 | gpio_direction_input(GPIO_BOOT_SEL3); | 816 | gpio_direction_input(GPIO_BOOT_SEL3); |
| 817 | 817 | ||
| 818 | /*Read BOOT_SEL Configuration */ | 818 | /*Read BOOT_SEL Configuration */ |
| 819 | if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 0)) { | 819 | if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 0)) { |
| 820 | puts("BOOT_SEL Detected: OFF OFF OFF, SATA Boot Up Not Defined...\n"); | 820 | puts("BOOT_SEL Detected: OFF OFF OFF, SATA Boot Up Not Defined...\n"); |
| 821 | hang(); | 821 | hang(); |
| 822 | } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 0)) { | 822 | } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 0)) { |
| 823 | puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n"); | 823 | puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n"); |
| 824 | setenv_ulong("mmcdev", 2); | 824 | setenv_ulong("mmcdev", 2); |
| 825 | setenv("bootcmd", "run findfdt; run mmcboot;"); | 825 | setenv("bootcmd", "run findfdt; run mmcboot;"); |
| 826 | } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 0)) { | 826 | } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 0)) { |
| 827 | puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n"); | 827 | puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n"); |
| 828 | setenv_ulong("mmcdev", 0); | 828 | setenv_ulong("mmcdev", 0); |
| 829 | setenv("bootcmd", "run findfdt; run mmcboot;"); | 829 | setenv("bootcmd", "run findfdt; run mmcboot;"); |
| 830 | } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 1)) { | 830 | } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 1)) { |
| 831 | puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n"); | 831 | puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n"); |
| 832 | setenv_ulong("mmcdev", 1); | 832 | setenv_ulong("mmcdev", 1); |
| 833 | setenv("bootcmd", "mmc rescan; run findfdt; run mmcboot;"); | 833 | setenv("bootcmd", "mmc rescan; run findfdt; run mmcboot;"); |
| 834 | } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 1)) { | 834 | } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 1)) { |
| 835 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); | 835 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); |
| 836 | setenv("bootcmd", "dhcp;"); | 836 | setenv("bootcmd", "dhcp;"); |
| 837 | } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 0)) { | 837 | } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 0)) { |
| 838 | puts("BOOT_SEL Detected: ON ON OFF, Carrier SPI Boot Not Supported...\n"); | 838 | puts("BOOT_SEL Detected: ON ON OFF, Carrier SPI Boot Not Supported...\n"); |
| 839 | hang(); | 839 | hang(); |
| 840 | } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 1)) { | 840 | } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 1)) { |
| 841 | puts("BOOT_SEL Detected: OFF OFF ON, Load zImage from USB1...\n"); | 841 | puts("BOOT_SEL Detected: OFF OFF ON, Load zImage from USB1...\n"); |
| 842 | setenv_ulong("usbdev", 0); | 842 | setenv_ulong("usbdev", 0); |
| 843 | setenv("bootcmd", "run findfdt; run usbboot;"); | 843 | setenv("bootcmd", "run findfdt; run usbboot;"); |
| 844 | } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 1)) { | 844 | } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 1)) { |
| 845 | puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n"); | 845 | puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n"); |
| 846 | setenv_ulong("mmcdev", 1); | 846 | setenv_ulong("mmcdev", 1); |
| 847 | setenv("bootcmd", "run findfdt; run mmcboot;"); | 847 | setenv("bootcmd", "run findfdt; run mmcboot;"); |
| 848 | } else { | 848 | } else { |
| 849 | puts("unsupported boot up devices\n"); | 849 | puts("unsupported boot up devices\n"); |
| 850 | return 0; | 850 | return 0; |
| 851 | } | 851 | } |
| 852 | 852 | ||
| 853 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | 853 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 854 | set_board_info_env(NULL); | 854 | set_board_info_env(NULL); |
| 855 | 855 | ||
| 856 | /* | 856 | /* |
| 857 | * Default FIT boot on HS devices. Non FIT images are not allowed | 857 | * Default FIT boot on HS devices. Non FIT images are not allowed |
| 858 | * on HS devices. | 858 | * on HS devices. |
| 859 | */ | 859 | */ |
| 860 | if (get_device_type() == HS_DEVICE) | 860 | if (get_device_type() == HS_DEVICE) |
| 861 | setenv("boot_fit", "1"); | 861 | setenv("boot_fit", "1"); |
| 862 | #endif | 862 | #endif |
| 863 | return 0; | 863 | return 0; |
| 864 | } | 864 | } |
| 865 | #endif | 865 | #endif |
| 866 | 866 | ||
| 867 | #ifdef CONFIG_USB_DWC3 | 867 | #ifdef CONFIG_USB_DWC3 |
| 868 | static struct dwc3_device usb_otg_ss1 = { | 868 | static struct dwc3_device usb_otg_ss1 = { |
| 869 | .maximum_speed = USB_SPEED_HIGH, | 869 | .maximum_speed = USB_SPEED_HIGH, |
| 870 | .base = USB_OTG_SS1_BASE, | 870 | .base = USB_OTG_SS1_BASE, |
| 871 | .tx_fifo_resize = false, | 871 | .tx_fifo_resize = false, |
| 872 | .index = 0, | 872 | .index = 0, |
| 873 | }; | 873 | }; |
| 874 | 874 | ||
| 875 | static struct dwc3_omap_device usb_otg_ss1_glue = { | 875 | static struct dwc3_omap_device usb_otg_ss1_glue = { |
| 876 | .base = (void *)USB_OTG_SS1_GLUE_BASE, | 876 | .base = (void *)USB_OTG_SS1_GLUE_BASE, |
| 877 | .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, | 877 | .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, |
| 878 | .index = 0, | 878 | .index = 0, |
| 879 | }; | 879 | }; |
| 880 | 880 | ||
| 881 | static struct ti_usb_phy_device usb_phy1_device = { | 881 | static struct ti_usb_phy_device usb_phy1_device = { |
| 882 | .usb2_phy_power = (void *)USB2_PHY1_POWER, | 882 | .usb2_phy_power = (void *)USB2_PHY1_POWER, |
| 883 | .index = 0, | 883 | .index = 0, |
| 884 | }; | 884 | }; |
| 885 | 885 | ||
| 886 | static struct dwc3_device usb_otg_ss2 = { | 886 | static struct dwc3_device usb_otg_ss2 = { |
| 887 | .maximum_speed = USB_SPEED_HIGH, | 887 | .maximum_speed = USB_SPEED_HIGH, |
| 888 | .base = USB_OTG_SS2_BASE, | 888 | .base = USB_OTG_SS2_BASE, |
| 889 | .tx_fifo_resize = false, | 889 | .tx_fifo_resize = false, |
| 890 | .index = 1, | 890 | .index = 1, |
| 891 | }; | 891 | }; |
| 892 | 892 | ||
| 893 | static struct dwc3_omap_device usb_otg_ss2_glue = { | 893 | static struct dwc3_omap_device usb_otg_ss2_glue = { |
| 894 | .base = (void *)USB_OTG_SS2_GLUE_BASE, | 894 | .base = (void *)USB_OTG_SS2_GLUE_BASE, |
| 895 | .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, | 895 | .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, |
| 896 | .index = 1, | 896 | .index = 1, |
| 897 | }; | 897 | }; |
| 898 | 898 | ||
| 899 | static struct ti_usb_phy_device usb_phy2_device = { | 899 | static struct ti_usb_phy_device usb_phy2_device = { |
| 900 | .usb2_phy_power = (void *)USB2_PHY2_POWER, | 900 | .usb2_phy_power = (void *)USB2_PHY2_POWER, |
| 901 | .index = 1, | 901 | .index = 1, |
| 902 | }; | 902 | }; |
| 903 | 903 | ||
| 904 | int usb_gadget_handle_interrupts(int index) | 904 | int usb_gadget_handle_interrupts(int index) |
| 905 | { | 905 | { |
| 906 | u32 status; | 906 | u32 status; |
| 907 | 907 | ||
| 908 | status = dwc3_omap_uboot_interrupt_status(index); | 908 | status = dwc3_omap_uboot_interrupt_status(index); |
| 909 | if (status) | 909 | if (status) |
| 910 | dwc3_uboot_handle_interrupt(index); | 910 | dwc3_uboot_handle_interrupt(index); |
| 911 | 911 | ||
| 912 | return 0; | 912 | return 0; |
| 913 | } | 913 | } |
| 914 | #endif /* CONFIG_USB_DWC3 */ | 914 | #endif /* CONFIG_USB_DWC3 */ |
| 915 | 915 | ||
| 916 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) | 916 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) |
| 917 | int board_usb_init(int index, enum usb_init_type init) | 917 | int board_usb_init(int index, enum usb_init_type init) |
| 918 | { | 918 | { |
| 919 | enable_usb_clocks(index); | 919 | enable_usb_clocks(index); |
| 920 | #ifdef CONFIG_USB_DWC3 | 920 | #ifdef CONFIG_USB_DWC3 |
| 921 | switch (index) { | 921 | switch (index) { |
| 922 | case 0: | 922 | case 0: |
| 923 | if (init == USB_INIT_DEVICE) { | 923 | if (init == USB_INIT_DEVICE) { |
| 924 | usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; | 924 | usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; |
| 925 | usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; | 925 | usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; |
| 926 | dwc3_omap_uboot_init(&usb_otg_ss1_glue); | 926 | dwc3_omap_uboot_init(&usb_otg_ss1_glue); |
| 927 | ti_usb_phy_uboot_init(&usb_phy1_device); | 927 | ti_usb_phy_uboot_init(&usb_phy1_device); |
| 928 | dwc3_uboot_init(&usb_otg_ss1); | 928 | dwc3_uboot_init(&usb_otg_ss1); |
| 929 | } | 929 | } |
| 930 | break; | 930 | break; |
| 931 | case 1: | 931 | case 1: |
| 932 | if (init == USB_INIT_DEVICE) { | 932 | if (init == USB_INIT_DEVICE) { |
| 933 | usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; | 933 | usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; |
| 934 | usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; | 934 | usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; |
| 935 | ti_usb_phy_uboot_init(&usb_phy2_device); | 935 | ti_usb_phy_uboot_init(&usb_phy2_device); |
| 936 | dwc3_omap_uboot_init(&usb_otg_ss2_glue); | 936 | dwc3_omap_uboot_init(&usb_otg_ss2_glue); |
| 937 | dwc3_uboot_init(&usb_otg_ss2); | 937 | dwc3_uboot_init(&usb_otg_ss2); |
| 938 | } | 938 | } |
| 939 | break; | 939 | break; |
| 940 | default: | 940 | default: |
| 941 | printf("Invalid Controller Index\n"); | 941 | printf("Invalid Controller Index\n"); |
| 942 | } | 942 | } |
| 943 | #endif | 943 | #endif |
| 944 | 944 | ||
| 945 | return 0; | 945 | return 0; |
| 946 | } | 946 | } |
| 947 | 947 | ||
| 948 | int board_usb_cleanup(int index, enum usb_init_type init) | 948 | int board_usb_cleanup(int index, enum usb_init_type init) |
| 949 | { | 949 | { |
| 950 | #ifdef CONFIG_USB_DWC3 | 950 | #ifdef CONFIG_USB_DWC3 |
| 951 | switch (index) { | 951 | switch (index) { |
| 952 | case 0: | 952 | case 0: |
| 953 | case 1: | 953 | case 1: |
| 954 | if (init == USB_INIT_DEVICE) { | 954 | if (init == USB_INIT_DEVICE) { |
| 955 | ti_usb_phy_uboot_exit(index); | 955 | ti_usb_phy_uboot_exit(index); |
| 956 | dwc3_uboot_exit(index); | 956 | dwc3_uboot_exit(index); |
| 957 | dwc3_omap_uboot_exit(index); | 957 | dwc3_omap_uboot_exit(index); |
| 958 | } | 958 | } |
| 959 | break; | 959 | break; |
| 960 | default: | 960 | default: |
| 961 | printf("Invalid Controller Index\n"); | 961 | printf("Invalid Controller Index\n"); |
| 962 | } | 962 | } |
| 963 | #endif | 963 | #endif |
| 964 | disable_usb_clocks(index); | 964 | disable_usb_clocks(index); |
| 965 | 965 | ||
| 966 | return 0; | 966 | return 0; |
| 967 | } | 967 | } |
| 968 | #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ | 968 | #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ |
| 969 | 969 | ||
| 970 | #ifndef CONFIG_DM_ETH | 970 | #ifndef CONFIG_DM_ETH |
| 971 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ | 971 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
| 972 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) | 972 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
| 973 | static void cpsw_control(int enabled) | 973 | static void cpsw_control(int enabled) |
| 974 | { | 974 | { |
| 975 | /* Additional controls can be added here */ | 975 | /* Additional controls can be added here */ |
| 976 | return; | 976 | return; |
| 977 | } | 977 | } |
| 978 | 978 | ||
| 979 | static struct cpsw_slave_data cpsw_slaves[] = { | 979 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 980 | { | 980 | { |
| 981 | .slave_reg_ofs = 0x208, | 981 | .slave_reg_ofs = 0x208, |
| 982 | .sliver_reg_ofs = 0xd80, | 982 | .sliver_reg_ofs = 0xd80, |
| 983 | .phy_addr = 16, | 983 | .phy_addr = 16, |
| 984 | }, | 984 | }, |
| 985 | { | 985 | { |
| 986 | .slave_reg_ofs = 0x308, | 986 | .slave_reg_ofs = 0x308, |
| 987 | .sliver_reg_ofs = 0xdc0, | 987 | .sliver_reg_ofs = 0xdc0, |
| 988 | .phy_addr = 1, | 988 | .phy_addr = 1, |
| 989 | }, | 989 | }, |
| 990 | }; | 990 | }; |
| 991 | 991 | ||
| 992 | static struct cpsw_platform_data cpsw_data = { | 992 | static struct cpsw_platform_data cpsw_data = { |
| 993 | .mdio_base = CPSW_MDIO_BASE, | 993 | .mdio_base = CPSW_MDIO_BASE, |
| 994 | .cpsw_base = CPSW_BASE, | 994 | .cpsw_base = CPSW_BASE, |
| 995 | .mdio_div = 0xff, | 995 | .mdio_div = 0xff, |
| 996 | .channels = 8, | 996 | .channels = 8, |
| 997 | .cpdma_reg_ofs = 0x800, | 997 | .cpdma_reg_ofs = 0x800, |
| 998 | .slaves = 1, | 998 | .slaves = 1, |
| 999 | .slave_data = cpsw_slaves, | 999 | .slave_data = cpsw_slaves, |
| 1000 | .ale_reg_ofs = 0xd00, | 1000 | .ale_reg_ofs = 0xd00, |
| 1001 | .ale_entries = 1024, | 1001 | .ale_entries = 1024, |
| 1002 | .host_port_reg_ofs = 0x108, | 1002 | .host_port_reg_ofs = 0x108, |
| 1003 | .hw_stats_reg_ofs = 0x900, | 1003 | .hw_stats_reg_ofs = 0x900, |
| 1004 | .bd_ram_ofs = 0x2000, | 1004 | .bd_ram_ofs = 0x2000, |
| 1005 | .mac_control = (1 << 5), | 1005 | .mac_control = (1 << 5), |
| 1006 | .control = cpsw_control, | 1006 | .control = cpsw_control, |
| 1007 | .host_port_num = 0, | 1007 | .host_port_num = 0, |
| 1008 | .version = CPSW_CTRL_VERSION_2, | 1008 | .version = CPSW_CTRL_VERSION_2, |
| 1009 | }; | 1009 | }; |
| 1010 | #endif | 1010 | #endif |
| 1011 | 1011 | ||
| 1012 | 1012 | ||
| 1013 | /* | 1013 | /* |
| 1014 | * This function will: | 1014 | * This function will: |
| 1015 | * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr | 1015 | * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr |
| 1016 | * in the environment | 1016 | * in the environment |
| 1017 | * Perform fixups to the PHY present on certain boards. We only need this | 1017 | * Perform fixups to the PHY present on certain boards. We only need this |
| 1018 | * function in: | 1018 | * function in: |
| 1019 | * - SPL with either CPSW or USB ethernet support | 1019 | * - SPL with either CPSW or USB ethernet support |
| 1020 | * - Full U-Boot, with either CPSW or USB ethernet | 1020 | * - Full U-Boot, with either CPSW or USB ethernet |
| 1021 | * Build in only these cases to avoid warnings about unused variables | 1021 | * Build in only these cases to avoid warnings about unused variables |
| 1022 | * when we build an SPL that has neither option but full U-Boot will. | 1022 | * when we build an SPL that has neither option but full U-Boot will. |
| 1023 | */ | 1023 | */ |
| 1024 | #if ((defined(CONFIG_SPL_ETH_SUPPORT) || \ | 1024 | #if ((defined(CONFIG_SPL_ETH_SUPPORT) || \ |
| 1025 | defined(CONFIG_SPL_USBETH_SUPPORT)) && \ | 1025 | defined(CONFIG_SPL_USBETH_SUPPORT)) && \ |
| 1026 | defined(CONFIG_SPL_BUILD)) || \ | 1026 | defined(CONFIG_SPL_BUILD)) || \ |
| 1027 | ((defined(CONFIG_DRIVER_TI_CPSW) || \ | 1027 | ((defined(CONFIG_DRIVER_TI_CPSW) || \ |
| 1028 | defined(CONFIG_USB_ETHER)) && !defined(CONFIG_SPL_BUILD)) | 1028 | defined(CONFIG_USB_ETHER)) && !defined(CONFIG_SPL_BUILD)) |
| 1029 | int board_eth_init(bd_t *bis) | 1029 | int board_eth_init(bd_t *bis) |
| 1030 | { | 1030 | { |
| 1031 | int rv; | 1031 | int rv; |
| 1032 | uint8_t mac_addr[6]; | 1032 | uint8_t mac_addr[6]; |
| 1033 | uint32_t mac_hi, mac_lo; | 1033 | uint32_t mac_hi, mac_lo; |
| 1034 | 1034 | ||
| 1035 | /* try reading mac address from efuse */ | 1035 | /* try reading mac address from efuse */ |
| 1036 | mac_lo = readl(&cdev->macid0l); | 1036 | mac_lo = readl(&cdev->macid0l); |
| 1037 | mac_hi = readl(&cdev->macid0h); | 1037 | mac_hi = readl(&cdev->macid0h); |
| 1038 | mac_addr[0] = mac_hi & 0xFF; | 1038 | mac_addr[0] = mac_hi & 0xFF; |
| 1039 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; | 1039 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 1040 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; | 1040 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 1041 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; | 1041 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 1042 | mac_addr[4] = mac_lo & 0xFF; | 1042 | mac_addr[4] = mac_lo & 0xFF; |
| 1043 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; | 1043 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 1044 | 1044 | ||
| 1045 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ | 1045 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
| 1046 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) | 1046 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
| 1047 | if (!getenv("ethaddr")) { | 1047 | if (!getenv("ethaddr")) { |
| 1048 | puts("<ethaddr> not set. Validating first E-fuse MAC\n"); | 1048 | puts("<ethaddr> not set. Validating first E-fuse MAC\n"); |
| 1049 | if (is_valid_ethaddr(mac_addr)) | 1049 | if (is_valid_ethaddr(mac_addr)) |
| 1050 | eth_setenv_enetaddr("ethaddr", mac_addr); | 1050 | eth_setenv_enetaddr("ethaddr", mac_addr); |
| 1051 | } | 1051 | } |
| 1052 | 1052 | ||
| 1053 | #ifndef CONFIG_SPL_BUILD | 1053 | #ifndef CONFIG_SPL_BUILD |
| 1054 | mac_lo = readl(&cdev->macid1l); | 1054 | mac_lo = readl(&cdev->macid1l); |
| 1055 | mac_hi = readl(&cdev->macid1h); | 1055 | mac_hi = readl(&cdev->macid1h); |
| 1056 | mac_addr[0] = mac_hi & 0xFF; | 1056 | mac_addr[0] = mac_hi & 0xFF; |
| 1057 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; | 1057 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 1058 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; | 1058 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 1059 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; | 1059 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 1060 | mac_addr[4] = mac_lo & 0xFF; | 1060 | mac_addr[4] = mac_lo & 0xFF; |
| 1061 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; | 1061 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 1062 | 1062 | ||
| 1063 | if (!getenv("eth1addr")) { | 1063 | if (!getenv("eth1addr")) { |
| 1064 | if (is_valid_ethaddr(mac_addr)) | 1064 | if (is_valid_ethaddr(mac_addr)) |
| 1065 | eth_setenv_enetaddr("eth1addr", mac_addr); | 1065 | eth_setenv_enetaddr("eth1addr", mac_addr); |
| 1066 | } | 1066 | } |
| 1067 | #endif | 1067 | #endif |
| 1068 | if (board_is_eposevm()) { | 1068 | if (board_is_eposevm()) { |
| 1069 | writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); | 1069 | writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); |
| 1070 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; | 1070 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; |
| 1071 | cpsw_slaves[0].phy_addr = 16; | 1071 | cpsw_slaves[0].phy_addr = 16; |
| 1072 | } else if (board_is_sk()) { | 1072 | } else if (board_is_sk()) { |
| 1073 | writel(RGMII_MODE_ENABLE, &cdev->miisel); | 1073 | writel(RGMII_MODE_ENABLE, &cdev->miisel); |
| 1074 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; | 1074 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; |
| 1075 | cpsw_slaves[0].phy_addr = 4; | 1075 | cpsw_slaves[0].phy_addr = 4; |
| 1076 | cpsw_slaves[1].phy_addr = 5; | 1076 | cpsw_slaves[1].phy_addr = 5; |
| 1077 | } else if (board_is_idk()) { | 1077 | } else if (board_is_idk()) { |
| 1078 | writel(RGMII_MODE_ENABLE, &cdev->miisel); | 1078 | writel(RGMII_MODE_ENABLE, &cdev->miisel); |
| 1079 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; | 1079 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; |
| 1080 | cpsw_slaves[0].phy_addr = 0; | 1080 | cpsw_slaves[0].phy_addr = 0; |
| 1081 | } else if (board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) { | 1081 | } else if (board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) { |
| 1082 | writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); | 1082 | writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); |
| 1083 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; | 1083 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; |
| 1084 | cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; | 1084 | cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; |
| 1085 | cpsw_slaves[0].phy_addr = 6; | 1085 | cpsw_slaves[0].phy_addr = 6; |
| 1086 | cpsw_slaves[1].phy_addr = 7; | 1086 | cpsw_slaves[1].phy_addr = 7; |
| 1087 | } else { | 1087 | } else { |
| 1088 | writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); | 1088 | writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); |
| 1089 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; | 1089 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; |
| 1090 | cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; | 1090 | cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; |
| 1091 | cpsw_slaves[0].phy_addr = 6; | 1091 | cpsw_slaves[0].phy_addr = 6; |
| 1092 | cpsw_slaves[1].phy_addr = 7; | 1092 | cpsw_slaves[1].phy_addr = 7; |
| 1093 | } | 1093 | } |
| 1094 | 1094 | ||
| 1095 | rv = cpsw_register(&cpsw_data); | 1095 | rv = cpsw_register(&cpsw_data); |
| 1096 | if (rv < 0) { | 1096 | if (rv < 0) { |
| 1097 | printf("Error %d registering CPSW switch\n", rv); | 1097 | printf("Error %d registering CPSW switch\n", rv); |
| 1098 | return rv; | 1098 | return rv; |
| 1099 | } | 1099 | } |
| 1100 | #endif | 1100 | #endif |
| 1101 | #if defined(CONFIG_USB_ETHER) && \ | 1101 | #if defined(CONFIG_USB_ETHER) && \ |
| 1102 | (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) | 1102 | (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) |
| 1103 | if (is_valid_ethaddr(mac_addr)) | 1103 | if (is_valid_ethaddr(mac_addr)) |
| 1104 | eth_setenv_enetaddr("usbnet_devaddr", mac_addr); | 1104 | eth_setenv_enetaddr("usbnet_devaddr", mac_addr); |
| 1105 | 1105 | ||
| 1106 | rv = usb_eth_initialize(bis); | 1106 | rv = usb_eth_initialize(bis); |
| 1107 | if (rv < 0) | 1107 | if (rv < 0) |
| 1108 | printf("Error %d registering USB_ETHER\n", rv); | 1108 | printf("Error %d registering USB_ETHER\n", rv); |
| 1109 | #endif | 1109 | #endif |
| 1110 | 1110 | ||
| 1111 | return rv; | 1111 | return rv; |
| 1112 | } | 1112 | } |
| 1113 | #endif | 1113 | #endif |
| 1114 | #endif | 1114 | #endif |
| 1115 | 1115 | ||
| 1116 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | 1116 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
| 1117 | int ft_board_setup(void *blob, bd_t *bd) | 1117 | int ft_board_setup(void *blob, bd_t *bd) |
| 1118 | { | 1118 | { |
| 1119 | ft_cpu_setup(blob, bd); | 1119 | ft_cpu_setup(blob, bd); |
| 1120 | 1120 | ||
| 1121 | return 0; | 1121 | return 0; |
| 1122 | } | 1122 | } |
| 1123 | #endif | 1123 | #endif |
| 1124 | 1124 | ||
| 1125 | #ifdef CONFIG_SPL_LOAD_FIT | 1125 | #ifdef CONFIG_SPL_LOAD_FIT |
| 1126 | int board_fit_config_name_match(const char *name) | 1126 | int board_fit_config_name_match(const char *name) |
| 1127 | { | 1127 | { |
| 1128 | if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) | 1128 | if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) |
| 1129 | return 0; | 1129 | return 0; |
| 1130 | else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) | 1130 | else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) |
| 1131 | return 0; | 1131 | return 0; |
| 1132 | else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) | 1132 | else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) |
| 1133 | return 0; | 1133 | return 0; |
| 1134 | else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) | 1134 | else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) |
| 1135 | return 0; | 1135 | return 0; |
| 1136 | else if (board_is_smarc_t437x_800() && !strcmp(name, "am437x-smarct437x")) | 1136 | else if (board_is_smarc_t437x_800() && !strcmp(name, "SMCT4X80")) |
| 1137 | return 0; | 1137 | return 0; |
| 1138 | else if (board_is_smarc_t437x_01g() && !strcmp(name, "am437x-smarct437xSMCT4X1G")) | 1138 | else if (board_is_smarc_t437x_01g() && !strcmp(name, "SMCT4X1G")) |
| 1139 | return 0; | 1139 | return 0; |
| 1140 | else | 1140 | else |
| 1141 | return -1; | 1141 | return -1; |
| 1142 | } | 1142 | } |
| 1143 | #endif | 1143 | #endif |
| 1144 | 1144 | ||
| 1145 | #ifdef CONFIG_TI_SECURE_DEVICE | 1145 | #ifdef CONFIG_TI_SECURE_DEVICE |
| 1146 | void board_fit_image_post_process(void **p_image, size_t *p_size) | 1146 | void board_fit_image_post_process(void **p_image, size_t *p_size) |
| 1147 | { | 1147 | { |
| 1148 | secure_boot_verify_image(p_image, p_size); | 1148 | secure_boot_verify_image(p_image, p_size); |
| 1149 | } | 1149 | } |
| 1150 | 1150 | ||
| 1151 | void board_tee_image_process(ulong tee_image, size_t tee_size) | 1151 | void board_tee_image_process(ulong tee_image, size_t tee_size) |
| 1152 | { | 1152 | { |
| 1153 | secure_tee_install((u32)tee_image); | 1153 | secure_tee_install((u32)tee_image); |
| 1154 | } | 1154 | } |
| 1155 | 1155 | ||
| 1156 | U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); | 1156 | U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); |
| 1157 | #endif | 1157 | #endif |
| 1158 | 1158 |
configs/smarct437x_evm_spi_uart0_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_AM43XX=y | 2 | CONFIG_AM43XX=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_TARGET_SMARCT437X_EVM=y | 4 | CONFIG_TARGET_SMARCT437X_EVM=y |
| 5 | CONFIG_SYS_PROMPT="U-Boot# " | 5 | CONFIG_SYS_PROMPT="U-Boot# " |
| 6 | CONFIG_SPL_STACK_R_ADDR=0x82000000 | 6 | CONFIG_SPL_STACK_R_ADDR=0x82000000 |
| 7 | CONFIG_SPL_YMODEM_SUPPORT=y | 7 | CONFIG_SPL_YMODEM_SUPPORT=y |
| 8 | CONFIG_SPL=y | 8 | CONFIG_SPL=y |
| 9 | CONFIG_SPL_STACK_R=y | 9 | CONFIG_SPL_STACK_R=y |
| 10 | CONFIG_SPL_SEPARATE_BSS=y | 10 | CONFIG_SPL_SEPARATE_BSS=y |
| 11 | CONFIG_SPL_RTC_ONLY_SUPPORT=y | 11 | CONFIG_SPL_RTC_ONLY_SUPPORT=y |
| 12 | CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" | 12 | CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" |
| 13 | CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,SPI_BOOT" | 13 | CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,SPI_BOOT" |
| 14 | #CONFIG_QSPI_BOOT=y | ||
| 15 | CONFIG_SYS_CONSOLE_INFO_QUIET=y | 14 | CONFIG_SYS_CONSOLE_INFO_QUIET=y |
| 16 | CONFIG_VERSION_VARIABLE=y | 15 | CONFIG_VERSION_VARIABLE=y |
| 17 | CONFIG_HUSH_PARSER=y | 16 | CONFIG_HUSH_PARSER=y |
| 18 | CONFIG_CMD_BOOTZ=y | 17 | CONFIG_CMD_BOOTZ=y |
| 19 | # CONFIG_CMD_IMLS is not set | 18 | # CONFIG_CMD_IMLS is not set |
| 20 | CONFIG_CMD_ASKENV=y | 19 | CONFIG_CMD_ASKENV=y |
| 21 | # CONFIG_CMD_FLASH is not set | 20 | # CONFIG_CMD_FLASH is not set |
| 22 | CONFIG_CMD_MMC=y | 21 | CONFIG_CMD_MMC=y |
| 23 | CONFIG_CMD_SF=y | 22 | CONFIG_CMD_SF=y |
| 24 | CONFIG_CMD_SPI=y | 23 | CONFIG_CMD_SPI=y |
| 25 | CONFIG_CMD_I2C=y | 24 | CONFIG_CMD_I2C=y |
| 26 | CONFIG_CMD_USB=y | 25 | CONFIG_CMD_USB=y |
| 27 | CONFIG_CMD_DFU=y | 26 | CONFIG_CMD_DFU=y |
| 28 | CONFIG_CMD_GPIO=y | 27 | CONFIG_CMD_GPIO=y |
| 29 | # CONFIG_CMD_SETEXPR is not set | 28 | # CONFIG_CMD_SETEXPR is not set |
| 30 | CONFIG_CMD_DHCP=y | 29 | CONFIG_CMD_DHCP=y |
| 31 | CONFIG_CMD_MII=y | 30 | CONFIG_CMD_MII=y |
| 32 | CONFIG_CMD_PING=y | 31 | CONFIG_CMD_PING=y |
| 33 | CONFIG_CMD_EXT2=y | 32 | CONFIG_CMD_EXT2=y |
| 34 | CONFIG_CMD_EXT4=y | 33 | CONFIG_CMD_EXT4=y |
| 35 | CONFIG_CMD_EXT4_WRITE=y | 34 | CONFIG_CMD_EXT4_WRITE=y |
| 36 | CONFIG_CMD_FAT=y | 35 | CONFIG_CMD_FAT=y |
| 37 | CONFIG_CMD_FS_GENERIC=y | 36 | CONFIG_CMD_FS_GENERIC=y |
| 38 | CONFIG_OF_CONTROL=y | 37 | CONFIG_OF_CONTROL=y |
| 39 | CONFIG_DM=y | 38 | CONFIG_DM=y |
| 40 | CONFIG_SPL_DM=y | 39 | CONFIG_SPL_DM=y |
| 41 | CONFIG_SPL_DM_SEQ_ALIAS=y | 40 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 42 | CONFIG_SPL_OF_TRANSLATE=y | 41 | CONFIG_SPL_OF_TRANSLATE=y |
| 43 | CONFIG_DFU_MMC=y | 42 | CONFIG_DFU_MMC=y |
| 44 | CONFIG_DFU_RAM=y | 43 | CONFIG_DFU_RAM=y |
| 45 | CONFIG_DFU_SF=y | 44 | CONFIG_DFU_SF=y |
| 46 | CONFIG_SPI_FLASH=y | 45 | CONFIG_SPI_FLASH=y |
| 47 | CONFIG_SPI_FLASH_BAR=y | 46 | CONFIG_SPI_FLASH_BAR=y |
| 48 | CONFIG_SPI_FLASH_MACRONIX=y | 47 | CONFIG_SPI_FLASH_MACRONIX=y |
| 49 | CONFIG_SYS_NS16550=y | 48 | CONFIG_SYS_NS16550=y |
| 50 | CONFIG_USB=y | 49 | CONFIG_USB=y |
| 51 | CONFIG_USB_XHCI_HCD=y | 50 | CONFIG_USB_XHCI_HCD=y |
| 52 | CONFIG_USB_XHCI_DWC3=y | 51 | CONFIG_USB_XHCI_DWC3=y |
| 53 | CONFIG_USB_DWC3=y | 52 | CONFIG_USB_DWC3=y |
| 54 | CONFIG_USB_DWC3_GADGET=y | 53 | CONFIG_USB_DWC3_GADGET=y |
| 55 | CONFIG_USB_DWC3_OMAP=y | 54 | CONFIG_USB_DWC3_OMAP=y |
| 56 | CONFIG_USB_DWC3_PHY_OMAP=y | 55 | CONFIG_USB_DWC3_PHY_OMAP=y |
| 57 | CONFIG_USB_STORAGE=y | 56 | CONFIG_USB_STORAGE=y |
| 58 | CONFIG_USB_GADGET=y | 57 | CONFIG_USB_GADGET=y |
| 59 | CONFIG_USB_GADGET_DOWNLOAD=y | 58 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 60 | CONFIG_G_DNL_MANUFACTURER="Texas Instruments" | 59 | CONFIG_G_DNL_MANUFACTURER="Texas Instruments" |
| 61 | CONFIG_G_DNL_VENDOR_NUM=0x0403 | 60 | CONFIG_G_DNL_VENDOR_NUM=0x0403 |
| 62 | CONFIG_G_DNL_PRODUCT_NUM=0xbd00 | 61 | CONFIG_G_DNL_PRODUCT_NUM=0xbd00 |
| 63 | CONFIG_OF_LIBFDT=y | 62 | CONFIG_OF_LIBFDT=y |
| 64 | CONFIG_TIMER=y | 63 | CONFIG_TIMER=y |
| 65 | CONFIG_OMAP_TIMER=y | 64 | CONFIG_OMAP_TIMER=y |
| 66 | 65 |
configs/smarct437x_evm_spi_uart1_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_AM43XX=y | 2 | CONFIG_AM43XX=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_TARGET_SMARCT437X_EVM=y | 4 | CONFIG_TARGET_SMARCT437X_EVM=y |
| 5 | CONFIG_SYS_PROMPT="U-Boot# " | 5 | CONFIG_SYS_PROMPT="U-Boot# " |
| 6 | CONFIG_SPL_STACK_R_ADDR=0x82000000 | 6 | CONFIG_SPL_STACK_R_ADDR=0x82000000 |
| 7 | CONFIG_SPL_YMODEM_SUPPORT=y | 7 | CONFIG_SPL_YMODEM_SUPPORT=y |
| 8 | CONFIG_SPL=y | 8 | CONFIG_SPL=y |
| 9 | CONFIG_SPL_STACK_R=y | 9 | CONFIG_SPL_STACK_R=y |
| 10 | CONFIG_SPL_SEPARATE_BSS=y | 10 | CONFIG_SPL_SEPARATE_BSS=y |
| 11 | CONFIG_SPL_RTC_ONLY_SUPPORT=y | 11 | CONFIG_SPL_RTC_ONLY_SUPPORT=y |
| 12 | CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" | 12 | CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" |
| 13 | CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=4,SPI_BOOT" | 13 | CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=4,SPI_BOOT" |
| 14 | #CONFIG_QSPI_BOOT=y | ||
| 15 | CONFIG_SYS_CONSOLE_INFO_QUIET=y | 14 | CONFIG_SYS_CONSOLE_INFO_QUIET=y |
| 16 | CONFIG_VERSION_VARIABLE=y | 15 | CONFIG_VERSION_VARIABLE=y |
| 17 | CONFIG_HUSH_PARSER=y | 16 | CONFIG_HUSH_PARSER=y |
| 18 | CONFIG_CMD_BOOTZ=y | 17 | CONFIG_CMD_BOOTZ=y |
| 19 | # CONFIG_CMD_IMLS is not set | 18 | # CONFIG_CMD_IMLS is not set |
| 20 | CONFIG_CMD_ASKENV=y | 19 | CONFIG_CMD_ASKENV=y |
| 21 | # CONFIG_CMD_FLASH is not set | 20 | # CONFIG_CMD_FLASH is not set |
| 22 | CONFIG_CMD_MMC=y | 21 | CONFIG_CMD_MMC=y |
| 23 | CONFIG_CMD_SF=y | 22 | CONFIG_CMD_SF=y |
| 24 | CONFIG_CMD_SPI=y | 23 | CONFIG_CMD_SPI=y |
| 25 | CONFIG_CMD_I2C=y | 24 | CONFIG_CMD_I2C=y |
| 26 | CONFIG_CMD_USB=y | 25 | CONFIG_CMD_USB=y |
| 27 | CONFIG_CMD_DFU=y | 26 | CONFIG_CMD_DFU=y |
| 28 | CONFIG_CMD_GPIO=y | 27 | CONFIG_CMD_GPIO=y |
| 29 | # CONFIG_CMD_SETEXPR is not set | 28 | # CONFIG_CMD_SETEXPR is not set |
| 30 | CONFIG_CMD_DHCP=y | 29 | CONFIG_CMD_DHCP=y |
| 31 | CONFIG_CMD_MII=y | 30 | CONFIG_CMD_MII=y |
| 32 | CONFIG_CMD_PING=y | 31 | CONFIG_CMD_PING=y |
| 33 | CONFIG_CMD_EXT2=y | 32 | CONFIG_CMD_EXT2=y |
| 34 | CONFIG_CMD_EXT4=y | 33 | CONFIG_CMD_EXT4=y |
| 35 | CONFIG_CMD_EXT4_WRITE=y | 34 | CONFIG_CMD_EXT4_WRITE=y |
| 36 | CONFIG_CMD_FAT=y | 35 | CONFIG_CMD_FAT=y |
| 37 | CONFIG_CMD_FS_GENERIC=y | 36 | CONFIG_CMD_FS_GENERIC=y |
| 38 | CONFIG_OF_CONTROL=y | 37 | CONFIG_OF_CONTROL=y |
| 39 | CONFIG_DM=y | 38 | CONFIG_DM=y |
| 40 | CONFIG_SPL_DM=y | 39 | CONFIG_SPL_DM=y |
| 41 | CONFIG_SPL_DM_SEQ_ALIAS=y | 40 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 42 | CONFIG_SPL_OF_TRANSLATE=y | 41 | CONFIG_SPL_OF_TRANSLATE=y |
| 43 | CONFIG_DFU_MMC=y | 42 | CONFIG_DFU_MMC=y |
| 44 | CONFIG_DFU_RAM=y | 43 | CONFIG_DFU_RAM=y |
| 45 | CONFIG_DFU_SF=y | 44 | CONFIG_DFU_SF=y |
| 46 | CONFIG_SPI_FLASH=y | 45 | CONFIG_SPI_FLASH=y |
| 47 | CONFIG_SPI_FLASH_BAR=y | 46 | CONFIG_SPI_FLASH_BAR=y |
| 48 | CONFIG_SPI_FLASH_MACRONIX=y | 47 | CONFIG_SPI_FLASH_MACRONIX=y |
| 49 | CONFIG_SYS_NS16550=y | 48 | CONFIG_SYS_NS16550=y |
| 50 | CONFIG_USB=y | 49 | CONFIG_USB=y |
| 51 | CONFIG_USB_XHCI_HCD=y | 50 | CONFIG_USB_XHCI_HCD=y |
| 52 | CONFIG_USB_XHCI_DWC3=y | 51 | CONFIG_USB_XHCI_DWC3=y |
| 53 | CONFIG_USB_DWC3=y | 52 | CONFIG_USB_DWC3=y |
| 54 | CONFIG_USB_DWC3_GADGET=y | 53 | CONFIG_USB_DWC3_GADGET=y |
| 55 | CONFIG_USB_DWC3_OMAP=y | 54 | CONFIG_USB_DWC3_OMAP=y |
| 56 | CONFIG_USB_DWC3_PHY_OMAP=y | 55 | CONFIG_USB_DWC3_PHY_OMAP=y |
| 57 | CONFIG_USB_STORAGE=y | 56 | CONFIG_USB_STORAGE=y |
| 58 | CONFIG_USB_GADGET=y | 57 | CONFIG_USB_GADGET=y |
| 59 | CONFIG_USB_GADGET_DOWNLOAD=y | 58 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 60 | CONFIG_G_DNL_MANUFACTURER="Texas Instruments" | 59 | CONFIG_G_DNL_MANUFACTURER="Texas Instruments" |
| 61 | CONFIG_G_DNL_VENDOR_NUM=0x0403 | 60 | CONFIG_G_DNL_VENDOR_NUM=0x0403 |
| 62 | CONFIG_G_DNL_PRODUCT_NUM=0xbd00 | 61 | CONFIG_G_DNL_PRODUCT_NUM=0xbd00 |
| 63 | CONFIG_OF_LIBFDT=y | 62 | CONFIG_OF_LIBFDT=y |
| 64 | CONFIG_TIMER=y | 63 | CONFIG_TIMER=y |
| 65 | CONFIG_OMAP_TIMER=y | 64 | CONFIG_OMAP_TIMER=y |
| 66 | 65 |
configs/smarct437x_evm_spi_uart2_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_AM43XX=y | 2 | CONFIG_AM43XX=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_TARGET_SMARCT437X_EVM=y | 4 | CONFIG_TARGET_SMARCT437X_EVM=y |
| 5 | CONFIG_SYS_PROMPT="U-Boot# " | 5 | CONFIG_SYS_PROMPT="U-Boot# " |
| 6 | CONFIG_SPL_STACK_R_ADDR=0x82000000 | 6 | CONFIG_SPL_STACK_R_ADDR=0x82000000 |
| 7 | CONFIG_SPL_YMODEM_SUPPORT=y | 7 | CONFIG_SPL_YMODEM_SUPPORT=y |
| 8 | CONFIG_SPL=y | 8 | CONFIG_SPL=y |
| 9 | CONFIG_SPL_STACK_R=y | 9 | CONFIG_SPL_STACK_R=y |
| 10 | CONFIG_SPL_SEPARATE_BSS=y | 10 | CONFIG_SPL_SEPARATE_BSS=y |
| 11 | CONFIG_SPL_RTC_ONLY_SUPPORT=y | 11 | CONFIG_SPL_RTC_ONLY_SUPPORT=y |
| 12 | CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" | 12 | CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" |
| 13 | CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPI_BOOT" | 13 | CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPI_BOOT" |
| 14 | #CONFIG_QSPI_BOOT=y | ||
| 15 | CONFIG_SYS_CONSOLE_INFO_QUIET=y | 14 | CONFIG_SYS_CONSOLE_INFO_QUIET=y |
| 16 | CONFIG_VERSION_VARIABLE=y | 15 | CONFIG_VERSION_VARIABLE=y |
| 17 | CONFIG_HUSH_PARSER=y | 16 | CONFIG_HUSH_PARSER=y |
| 18 | CONFIG_CMD_BOOTZ=y | 17 | CONFIG_CMD_BOOTZ=y |
| 19 | # CONFIG_CMD_IMLS is not set | 18 | # CONFIG_CMD_IMLS is not set |
| 20 | CONFIG_CMD_ASKENV=y | 19 | CONFIG_CMD_ASKENV=y |
| 21 | # CONFIG_CMD_FLASH is not set | 20 | # CONFIG_CMD_FLASH is not set |
| 22 | CONFIG_CMD_MMC=y | 21 | CONFIG_CMD_MMC=y |
| 23 | CONFIG_CMD_SF=y | 22 | CONFIG_CMD_SF=y |
| 24 | CONFIG_CMD_SPI=y | 23 | CONFIG_CMD_SPI=y |
| 25 | CONFIG_CMD_I2C=y | 24 | CONFIG_CMD_I2C=y |
| 26 | CONFIG_CMD_USB=y | 25 | CONFIG_CMD_USB=y |
| 27 | CONFIG_CMD_DFU=y | 26 | CONFIG_CMD_DFU=y |
| 28 | CONFIG_CMD_GPIO=y | 27 | CONFIG_CMD_GPIO=y |
| 29 | # CONFIG_CMD_SETEXPR is not set | 28 | # CONFIG_CMD_SETEXPR is not set |
| 30 | CONFIG_CMD_DHCP=y | 29 | CONFIG_CMD_DHCP=y |
| 31 | CONFIG_CMD_MII=y | 30 | CONFIG_CMD_MII=y |
| 32 | CONFIG_CMD_PING=y | 31 | CONFIG_CMD_PING=y |
| 33 | CONFIG_CMD_EXT2=y | 32 | CONFIG_CMD_EXT2=y |
| 34 | CONFIG_CMD_EXT4=y | 33 | CONFIG_CMD_EXT4=y |
| 35 | CONFIG_CMD_EXT4_WRITE=y | 34 | CONFIG_CMD_EXT4_WRITE=y |
| 36 | CONFIG_CMD_FAT=y | 35 | CONFIG_CMD_FAT=y |
| 37 | CONFIG_CMD_FS_GENERIC=y | 36 | CONFIG_CMD_FS_GENERIC=y |
| 38 | CONFIG_OF_CONTROL=y | 37 | CONFIG_OF_CONTROL=y |
| 39 | CONFIG_DM=y | 38 | CONFIG_DM=y |
| 40 | CONFIG_SPL_DM=y | 39 | CONFIG_SPL_DM=y |
| 41 | CONFIG_SPL_DM_SEQ_ALIAS=y | 40 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 42 | CONFIG_SPL_OF_TRANSLATE=y | 41 | CONFIG_SPL_OF_TRANSLATE=y |
| 43 | CONFIG_DFU_MMC=y | 42 | CONFIG_DFU_MMC=y |
| 44 | CONFIG_DFU_RAM=y | 43 | CONFIG_DFU_RAM=y |
| 45 | CONFIG_DFU_SF=y | 44 | CONFIG_DFU_SF=y |
| 46 | CONFIG_SPI_FLASH=y | 45 | CONFIG_SPI_FLASH=y |
| 47 | CONFIG_SPI_FLASH_BAR=y | 46 | CONFIG_SPI_FLASH_BAR=y |
| 48 | CONFIG_SPI_FLASH_MACRONIX=y | 47 | CONFIG_SPI_FLASH_MACRONIX=y |
| 49 | CONFIG_SYS_NS16550=y | 48 | CONFIG_SYS_NS16550=y |
| 50 | CONFIG_USB=y | 49 | CONFIG_USB=y |
| 51 | CONFIG_USB_XHCI_HCD=y | 50 | CONFIG_USB_XHCI_HCD=y |
| 52 | CONFIG_USB_XHCI_DWC3=y | 51 | CONFIG_USB_XHCI_DWC3=y |
| 53 | CONFIG_USB_DWC3=y | 52 | CONFIG_USB_DWC3=y |
| 54 | CONFIG_USB_DWC3_GADGET=y | 53 | CONFIG_USB_DWC3_GADGET=y |
| 55 | CONFIG_USB_DWC3_OMAP=y | 54 | CONFIG_USB_DWC3_OMAP=y |
| 56 | CONFIG_USB_DWC3_PHY_OMAP=y | 55 | CONFIG_USB_DWC3_PHY_OMAP=y |
| 57 | CONFIG_USB_STORAGE=y | 56 | CONFIG_USB_STORAGE=y |
| 58 | CONFIG_USB_GADGET=y | 57 | CONFIG_USB_GADGET=y |
| 59 | CONFIG_USB_GADGET_DOWNLOAD=y | 58 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 60 | CONFIG_G_DNL_MANUFACTURER="Texas Instruments" | 59 | CONFIG_G_DNL_MANUFACTURER="Texas Instruments" |
| 61 | CONFIG_G_DNL_VENDOR_NUM=0x0403 | 60 | CONFIG_G_DNL_VENDOR_NUM=0x0403 |
| 62 | CONFIG_G_DNL_PRODUCT_NUM=0xbd00 | 61 | CONFIG_G_DNL_PRODUCT_NUM=0xbd00 |
| 63 | CONFIG_OF_LIBFDT=y | 62 | CONFIG_OF_LIBFDT=y |
| 64 | CONFIG_TIMER=y | 63 | CONFIG_TIMER=y |
| 65 | CONFIG_OMAP_TIMER=y | 64 | CONFIG_OMAP_TIMER=y |
| 66 | 65 |
configs/smarct437x_evm_spi_uart3_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_AM43XX=y | 2 | CONFIG_AM43XX=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_TARGET_SMARCT437X_EVM=y | 4 | CONFIG_TARGET_SMARCT437X_EVM=y |
| 5 | CONFIG_SYS_PROMPT="U-Boot# " | 5 | CONFIG_SYS_PROMPT="U-Boot# " |
| 6 | CONFIG_SPL_STACK_R_ADDR=0x82000000 | 6 | CONFIG_SPL_STACK_R_ADDR=0x82000000 |
| 7 | CONFIG_SPL_YMODEM_SUPPORT=y | 7 | CONFIG_SPL_YMODEM_SUPPORT=y |
| 8 | CONFIG_SPL=y | 8 | CONFIG_SPL=y |
| 9 | CONFIG_SPL_STACK_R=y | 9 | CONFIG_SPL_STACK_R=y |
| 10 | CONFIG_SPL_SEPARATE_BSS=y | 10 | CONFIG_SPL_SEPARATE_BSS=y |
| 11 | CONFIG_SPL_RTC_ONLY_SUPPORT=y | 11 | CONFIG_SPL_RTC_ONLY_SUPPORT=y |
| 12 | CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" | 12 | CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" |
| 13 | CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5,SPI_BOOT" | 13 | CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5,SPI_BOOT" |
| 14 | #CONFIG_QSPI_BOOT=y | ||
| 15 | CONFIG_SYS_CONSOLE_INFO_QUIET=y | 14 | CONFIG_SYS_CONSOLE_INFO_QUIET=y |
| 16 | CONFIG_VERSION_VARIABLE=y | 15 | CONFIG_VERSION_VARIABLE=y |
| 17 | CONFIG_HUSH_PARSER=y | 16 | CONFIG_HUSH_PARSER=y |
| 18 | CONFIG_CMD_BOOTZ=y | 17 | CONFIG_CMD_BOOTZ=y |
| 19 | # CONFIG_CMD_IMLS is not set | 18 | # CONFIG_CMD_IMLS is not set |
| 20 | CONFIG_CMD_ASKENV=y | 19 | CONFIG_CMD_ASKENV=y |
| 21 | # CONFIG_CMD_FLASH is not set | 20 | # CONFIG_CMD_FLASH is not set |
| 22 | CONFIG_CMD_MMC=y | 21 | CONFIG_CMD_MMC=y |
| 23 | CONFIG_CMD_SF=y | 22 | CONFIG_CMD_SF=y |
| 24 | CONFIG_CMD_SPI=y | 23 | CONFIG_CMD_SPI=y |
| 25 | CONFIG_CMD_I2C=y | 24 | CONFIG_CMD_I2C=y |
| 26 | CONFIG_CMD_USB=y | 25 | CONFIG_CMD_USB=y |
| 27 | CONFIG_CMD_DFU=y | 26 | CONFIG_CMD_DFU=y |
| 28 | CONFIG_CMD_GPIO=y | 27 | CONFIG_CMD_GPIO=y |
| 29 | # CONFIG_CMD_SETEXPR is not set | 28 | # CONFIG_CMD_SETEXPR is not set |
| 30 | CONFIG_CMD_DHCP=y | 29 | CONFIG_CMD_DHCP=y |
| 31 | CONFIG_CMD_MII=y | 30 | CONFIG_CMD_MII=y |
| 32 | CONFIG_CMD_PING=y | 31 | CONFIG_CMD_PING=y |
| 33 | CONFIG_CMD_EXT2=y | 32 | CONFIG_CMD_EXT2=y |
| 34 | CONFIG_CMD_EXT4=y | 33 | CONFIG_CMD_EXT4=y |
| 35 | CONFIG_CMD_EXT4_WRITE=y | 34 | CONFIG_CMD_EXT4_WRITE=y |
| 36 | CONFIG_CMD_FAT=y | 35 | CONFIG_CMD_FAT=y |
| 37 | CONFIG_CMD_FS_GENERIC=y | 36 | CONFIG_CMD_FS_GENERIC=y |
| 38 | CONFIG_OF_CONTROL=y | 37 | CONFIG_OF_CONTROL=y |
| 39 | CONFIG_DM=y | 38 | CONFIG_DM=y |
| 40 | CONFIG_SPL_DM=y | 39 | CONFIG_SPL_DM=y |
| 41 | CONFIG_SPL_DM_SEQ_ALIAS=y | 40 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 42 | CONFIG_SPL_OF_TRANSLATE=y | 41 | CONFIG_SPL_OF_TRANSLATE=y |
| 43 | CONFIG_DFU_MMC=y | 42 | CONFIG_DFU_MMC=y |
| 44 | CONFIG_DFU_RAM=y | 43 | CONFIG_DFU_RAM=y |
| 45 | CONFIG_DFU_SF=y | 44 | CONFIG_DFU_SF=y |
| 46 | CONFIG_SPI_FLASH=y | 45 | CONFIG_SPI_FLASH=y |
| 47 | CONFIG_SPI_FLASH_BAR=y | 46 | CONFIG_SPI_FLASH_BAR=y |
| 48 | CONFIG_SPI_FLASH_MACRONIX=y | 47 | CONFIG_SPI_FLASH_MACRONIX=y |
| 49 | CONFIG_SYS_NS16550=y | 48 | CONFIG_SYS_NS16550=y |
| 50 | CONFIG_USB=y | 49 | CONFIG_USB=y |
| 51 | CONFIG_USB_XHCI_HCD=y | 50 | CONFIG_USB_XHCI_HCD=y |
| 52 | CONFIG_USB_XHCI_DWC3=y | 51 | CONFIG_USB_XHCI_DWC3=y |
| 53 | CONFIG_USB_DWC3=y | 52 | CONFIG_USB_DWC3=y |
| 54 | CONFIG_USB_DWC3_GADGET=y | 53 | CONFIG_USB_DWC3_GADGET=y |
| 55 | CONFIG_USB_DWC3_OMAP=y | 54 | CONFIG_USB_DWC3_OMAP=y |
| 56 | CONFIG_USB_DWC3_PHY_OMAP=y | 55 | CONFIG_USB_DWC3_PHY_OMAP=y |
| 57 | CONFIG_USB_STORAGE=y | 56 | CONFIG_USB_STORAGE=y |
| 58 | CONFIG_USB_GADGET=y | 57 | CONFIG_USB_GADGET=y |
| 59 | CONFIG_USB_GADGET_DOWNLOAD=y | 58 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 60 | CONFIG_G_DNL_MANUFACTURER="Texas Instruments" | 59 | CONFIG_G_DNL_MANUFACTURER="Texas Instruments" |
| 61 | CONFIG_G_DNL_VENDOR_NUM=0x0403 | 60 | CONFIG_G_DNL_VENDOR_NUM=0x0403 |
| 62 | CONFIG_G_DNL_PRODUCT_NUM=0xbd00 | 61 | CONFIG_G_DNL_PRODUCT_NUM=0xbd00 |
| 63 | CONFIG_OF_LIBFDT=y | 62 | CONFIG_OF_LIBFDT=y |
| 64 | CONFIG_TIMER=y | 63 | CONFIG_TIMER=y |
| 65 | CONFIG_OMAP_TIMER=y | 64 | CONFIG_OMAP_TIMER=y |
| 66 | 65 |
include/configs/smarct437x_evm.h
| 1 | /* | 1 | /* |
| 2 | * smarct437x_evm.h | 2 | * smarct437x_evm.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * | 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #ifndef __CONFIG_SMARCT437X_EVM_H | 9 | #ifndef __CONFIG_SMARCT437X_EVM_H |
| 10 | #define __CONFIG_SMARCT437X_EVM_H | 10 | #define __CONFIG_SMARCT437X_EVM_H |
| 11 | 11 | ||
| 12 | #define CONFIG_BOARD_LATE_INIT | 12 | #define CONFIG_BOARD_LATE_INIT |
| 13 | #define CONFIG_ARCH_CPU_INIT | 13 | #define CONFIG_ARCH_CPU_INIT |
| 14 | #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ | 14 | #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ |
| 15 | #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ | 15 | #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ |
| 16 | 16 | ||
| 17 | #include <asm/arch/omap.h> | 17 | #include <asm/arch/omap.h> |
| 18 | #define CONFIG_ENV_IS_NOWHERE | 18 | #define CONFIG_ENV_IS_NOWHERE |
| 19 | 19 | ||
| 20 | /* NS16550 Configuration */ | 20 | /* NS16550 Configuration */ |
| 21 | #define CONFIG_SYS_NS16550_CLK 48000000 | 21 | #define CONFIG_SYS_NS16550_CLK 48000000 |
| 22 | #if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) | 22 | #if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) |
| 23 | #define CONFIG_SYS_NS16550_SERIAL | 23 | #define CONFIG_SYS_NS16550_SERIAL |
| 24 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | 24 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 25 | #define CONFIG_SYS_NS16550_SERIAL | 25 | #define CONFIG_SYS_NS16550_SERIAL |
| 26 | #endif | 26 | #endif |
| 27 | 27 | ||
| 28 | /* I2C Configuration */ | 28 | /* I2C Configuration */ |
| 29 | #define CONFIG_CMD_EEPROM | 29 | #define CONFIG_CMD_EEPROM |
| 30 | #define CONFIG_ENV_EEPROM_IS_ON_I2C | 30 | #define CONFIG_ENV_EEPROM_IS_ON_I2C |
| 31 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ | 31 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ |
| 32 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | 32 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| 33 | 33 | ||
| 34 | /* Power */ | 34 | /* Power */ |
| 35 | #define CONFIG_POWER | 35 | #define CONFIG_POWER |
| 36 | #define CONFIG_POWER_I2C | 36 | #define CONFIG_POWER_I2C |
| 37 | #define CONFIG_POWER_TPS65218 | 37 | #define CONFIG_POWER_TPS65218 |
| 38 | #define CONFIG_POWER_TPS62362 | 38 | #define CONFIG_POWER_TPS62362 |
| 39 | 39 | ||
| 40 | /* SPL defines. */ | 40 | /* SPL defines. */ |
| 41 | #define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR | 41 | #define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR |
| 42 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ | 42 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
| 43 | (128 << 20)) | 43 | (128 << 20)) |
| 44 | 44 | ||
| 45 | /* Enabling L2 Cache */ | 45 | /* Enabling L2 Cache */ |
| 46 | #define CONFIG_SYS_L2_PL310 | 46 | #define CONFIG_SYS_L2_PL310 |
| 47 | #define CONFIG_SYS_PL310_BASE 0x48242000 | 47 | #define CONFIG_SYS_PL310_BASE 0x48242000 |
| 48 | 48 | ||
| 49 | /* | 49 | /* |
| 50 | * Since SPL did pll and ddr initialization for us, | 50 | * Since SPL did pll and ddr initialization for us, |
| 51 | * we don't need to do it twice. | 51 | * we don't need to do it twice. |
| 52 | */ | 52 | */ |
| 53 | #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPI_BOOT) | 53 | #if !defined(CONFIG_SPL_BUILD) /*&& !defined(CONFIG_SPI_BOOT)*/ |
| 54 | #define CONFIG_SKIP_LOWLEVEL_INIT | 54 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 55 | #endif | 55 | #endif |
| 56 | 56 | ||
| 57 | /* | 57 | /* |
| 58 | * When building U-Boot such that there is no previous loader | 58 | * When building U-Boot such that there is no previous loader |
| 59 | * we need to call board_early_init_f. This is taken care of in | 59 | * we need to call board_early_init_f. This is taken care of in |
| 60 | * s_init when we have SPL used. | 60 | * s_init when we have SPL used. |
| 61 | */ | 61 | */ |
| 62 | #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) | 62 | #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) |
| 63 | #define CONFIG_BOARD_EARLY_INIT_F | 63 | #define CONFIG_BOARD_EARLY_INIT_F |
| 64 | #endif | 64 | #endif |
| 65 | 65 | ||
| 66 | /* Now bring in the rest of the common code. */ | 66 | /* Now bring in the rest of the common code. */ |
| 67 | #include <configs/embedian_armv7_omap.h> | 67 | #include <configs/embedian_armv7_omap.h> |
| 68 | 68 | ||
| 69 | /* Always 64 KiB env size */ | 69 | /* Always 64 KiB env size */ |
| 70 | #define CONFIG_ENV_SIZE (64 << 10) | 70 | #define CONFIG_ENV_SIZE (64 << 10) |
| 71 | 71 | ||
| 72 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | 72 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 73 | 73 | ||
| 74 | /* Clock Defines */ | 74 | /* Clock Defines */ |
| 75 | #define V_OSCK 24000000 /* Clock output from T2 */ | 75 | #define V_OSCK 24000000 /* Clock output from T2 */ |
| 76 | #define V_SCLK (V_OSCK) | 76 | #define V_SCLK (V_OSCK) |
| 77 | 77 | ||
| 78 | /* NS16550 Configuration */ | 78 | /* NS16550 Configuration */ |
| 79 | #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ | 79 | #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ |
| 80 | #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ | 80 | #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ |
| 81 | #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ | 81 | #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ |
| 82 | #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ | 82 | #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ |
| 83 | #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ | 83 | #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ |
| 84 | #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ | 84 | #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ |
| 85 | #define CONFIG_BAUDRATE 115200 | 85 | #define CONFIG_BAUDRATE 115200 |
| 86 | 86 | ||
| 87 | #if !defined(CONFIG_ENV_IS_NOWHERE) | 87 | #if !defined(CONFIG_ENV_IS_NOWHERE) |
| 88 | #define CONFIG_ENV_IS_IN_FAT | 88 | #define CONFIG_ENV_IS_IN_FAT |
| 89 | #define FAT_ENV_INTERFACE "mmc" | 89 | #define FAT_ENV_INTERFACE "mmc" |
| 90 | #define FAT_ENV_DEVICE_AND_PART "0:1" | 90 | #define FAT_ENV_DEVICE_AND_PART "0:1" |
| 91 | #define FAT_ENV_FILE "uboot.env" | 91 | #define FAT_ENV_FILE "uboot.env" |
| 92 | #define CONFIG_FAT_WRITE | 92 | #define CONFIG_FAT_WRITE |
| 93 | #endif | 93 | #endif |
| 94 | 94 | ||
| 95 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" | 95 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" |
| 96 | 96 | ||
| 97 | /* SPL USB Support */ | 97 | /* SPL USB Support */ |
| 98 | 98 | ||
| 99 | #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) | 99 | #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) |
| 100 | #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 | 100 | #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 |
| 101 | #define CONFIG_USB_XHCI_OMAP | 101 | #define CONFIG_USB_XHCI_OMAP |
| 102 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | 102 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
| 103 | 103 | ||
| 104 | #define CONFIG_OMAP_USB_PHY | 104 | #define CONFIG_OMAP_USB_PHY |
| 105 | #define CONFIG_AM437X_USB2PHY2_HOST | 105 | #define CONFIG_AM437X_USB2PHY2_HOST |
| 106 | #endif | 106 | #endif |
| 107 | 107 | ||
| 108 | #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT) | 108 | #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT) |
| 109 | #undef CONFIG_USB_DWC3_PHY_OMAP | 109 | #undef CONFIG_USB_DWC3_PHY_OMAP |
| 110 | #undef CONFIG_USB_DWC3_OMAP | 110 | #undef CONFIG_USB_DWC3_OMAP |
| 111 | #undef CONFIG_USB_DWC3 | 111 | #undef CONFIG_USB_DWC3 |
| 112 | #undef CONFIG_USB_DWC3_GADGET | 112 | #undef CONFIG_USB_DWC3_GADGET |
| 113 | 113 | ||
| 114 | #undef CONFIG_USB_GADGET_DOWNLOAD | 114 | #undef CONFIG_USB_GADGET_DOWNLOAD |
| 115 | #undef CONFIG_USB_GADGET_VBUS_DRAW | 115 | #undef CONFIG_USB_GADGET_VBUS_DRAW |
| 116 | #undef CONFIG_G_DNL_MANUFACTURER | 116 | #undef CONFIG_G_DNL_MANUFACTURER |
| 117 | #undef CONFIG_G_DNL_VENDOR_NUM | 117 | #undef CONFIG_G_DNL_VENDOR_NUM |
| 118 | #undef CONFIG_G_DNL_PRODUCT_NUM | 118 | #undef CONFIG_G_DNL_PRODUCT_NUM |
| 119 | #undef CONFIG_USB_GADGET_DUALSPEED | 119 | #undef CONFIG_USB_GADGET_DUALSPEED |
| 120 | #endif | 120 | #endif |
| 121 | 121 | ||
| 122 | #if !defined(CONFIG_SPL_BUILD) || \ | 122 | #if !defined(CONFIG_SPL_BUILD) || \ |
| 123 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)) | 123 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)) |
| 124 | #define CONFIG_USB_ETHER | 124 | #define CONFIG_USB_ETHER |
| 125 | #define CONFIG_USB_ETH_RNDIS | 125 | #define CONFIG_USB_ETH_RNDIS |
| 126 | #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" | 126 | #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" |
| 127 | #endif | 127 | #endif |
| 128 | 128 | ||
| 129 | #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80800000 | 129 | #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80800000 |
| 130 | 130 | ||
| 131 | /* | 131 | /* |
| 132 | * Disable MMC DM for SPL build and can be re-enabled after adding | 132 | * Disable MMC DM for SPL build and can be re-enabled after adding |
| 133 | * DM support in SPL | 133 | * DM support in SPL |
| 134 | */ | 134 | */ |
| 135 | #ifdef CONFIG_SPL_BUILD | 135 | #ifdef CONFIG_SPL_BUILD |
| 136 | #undef CONFIG_TIMER | 136 | #undef CONFIG_TIMER |
| 137 | #undef CONFIG_DM_NAND | 137 | #undef CONFIG_DM_NAND |
| 138 | #endif | 138 | #endif |
| 139 | 139 | ||
| 140 | #ifndef CONFIG_SPL_BUILD | 140 | #ifndef CONFIG_SPL_BUILD |
| 141 | /* USB Device Firmware Update support */ | 141 | /* USB Device Firmware Update support */ |
| 142 | #define DFUARGS \ | 142 | #define DFUARGS \ |
| 143 | "dfu_bufsiz=0x10000\0" \ | 143 | "dfu_bufsiz=0x10000\0" \ |
| 144 | DFU_ALT_INFO_MMC \ | 144 | DFU_ALT_INFO_MMC \ |
| 145 | DFU_ALT_INFO_EMMC \ | 145 | DFU_ALT_INFO_EMMC \ |
| 146 | DFU_ALT_INFO_RAM | 146 | DFU_ALT_INFO_RAM |
| 147 | #else | 147 | #else |
| 148 | #define DFUARGS | 148 | #define DFUARGS |
| 149 | #endif | 149 | #endif |
| 150 | 150 | ||
| 151 | /* | 151 | /* |
| 152 | * Default to using SPI for environment, etc. | 152 | * Default to using SPI for environment, etc. |
| 153 | * 0x000000 - 0x020000 : SPL (128KiB) | 153 | * 0x000000 - 0x020000 : SPL (128KiB) |
| 154 | * 0x020000 - 0x0A0000 : U-Boot (512KiB) | 154 | * 0x020000 - 0x0A0000 : U-Boot (512KiB) |
| 155 | * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) | 155 | * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) |
| 156 | * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) | 156 | * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) |
| 157 | * 0x0E0000 - 0x442000 : Linux Kernel | 157 | * 0x0E0000 - 0x442000 : Linux Kernel |
| 158 | * 0x442000 - 0x800000 : Userland | 158 | * 0x442000 - 0x800000 : Userland |
| 159 | */ | 159 | */ |
| 160 | #if defined(CONFIG_SPI_BOOT) | 160 | #if defined(CONFIG_SPI_BOOT) |
| 161 | /* SPL related */ | 161 | /* SPL related */ |
| 162 | #undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ | 162 | #undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ |
| 163 | #define CONFIG_SPL_SPI_SUPPORT | 163 | #define CONFIG_SPL_SPI_SUPPORT |
| 164 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | 164 | #define CONFIG_SPL_SPI_FLASH_SUPPORT |
| 165 | #define CONFIG_SPL_SPI_LOAD | 165 | #define CONFIG_SPL_SPI_LOAD |
| 166 | /*#define CONFIG_SPL_SPI_BUS 0 | 166 | /*#define CONFIG_SPL_SPI_BUS 0 |
| 167 | #define CONFIG_SPL_SPI_CS 0*/ | 167 | #define CONFIG_SPL_SPI_CS 0*/ |
| 168 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 | 168 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 |
| 169 | 169 | ||
| 170 | #undef CONFIG_ENV_IS_NOWHERE | 170 | #undef CONFIG_ENV_IS_NOWHERE |
| 171 | #undef CONFIG_ENV_IS_IN_FAT | 171 | #undef CONFIG_ENV_IS_IN_FAT |
| 172 | #define CONFIG_ENV_IS_IN_SPI_FLASH | 172 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 173 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | 173 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
| 174 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | 174 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
| 175 | #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ | 175 | #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ |
| 176 | #define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ | 176 | #define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ |
| 177 | #define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ | 177 | #define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ |
| 178 | #define MTDIDS_DEFAULT "nor0=m25p80-flash.0" | 178 | #define MTDIDS_DEFAULT "nor0=m25p80-flash.0" |
| 179 | #define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ | 179 | #define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ |
| 180 | "512k(u-boot),128k(u-boot-env1)," \ | 180 | "512k(u-boot),128k(u-boot-env1)," \ |
| 181 | "128k(u-boot-env2),3464k(kernel)," \ | 181 | "128k(u-boot-env2),3464k(kernel)," \ |
| 182 | "-(rootfs)" | 182 | "-(rootfs)" |
| 183 | #endif | 183 | #endif |
| 184 | 184 | ||
| 185 | #ifdef CONFIG_QSPI_BOOT | 185 | #ifdef CONFIG_QSPI_BOOT |
| 186 | #ifndef CONFIG_SYS_TEXT_BASE | 186 | #ifndef CONFIG_SYS_TEXT_BASE |
| 187 | #define CONFIG_SYS_TEXT_BASE CONFIG_ISW_ENTRY_ADDR | 187 | #define CONFIG_SYS_TEXT_BASE CONFIG_ISW_ENTRY_ADDR |
| 188 | #endif | 188 | #endif |
| 189 | #undef CONFIG_ENV_IS_IN_FAT | 189 | #undef CONFIG_ENV_IS_IN_FAT |
| 190 | #define CONFIG_ENV_IS_IN_SPI_FLASH | 190 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 191 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | 191 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
| 192 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | 192 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
| 193 | #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ | 193 | #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ |
| 194 | #define CONFIG_ENV_OFFSET 0x110000 | 194 | #define CONFIG_ENV_OFFSET 0x110000 |
| 195 | #define CONFIG_ENV_OFFSET_REDUND 0x120000 | 195 | #define CONFIG_ENV_OFFSET_REDUND 0x120000 |
| 196 | #ifdef MTDIDS_DEFAULT | 196 | #ifdef MTDIDS_DEFAULT |
| 197 | #undef MTDIDS_DEFAULT | 197 | #undef MTDIDS_DEFAULT |
| 198 | #endif | 198 | #endif |
| 199 | #ifdef MTDPARTS_DEFAULT | 199 | #ifdef MTDPARTS_DEFAULT |
| 200 | #undef MTDPARTS_DEFAULT | 200 | #undef MTDPARTS_DEFAULT |
| 201 | #endif | 201 | #endif |
| 202 | #define MTDPARTS_DEFAULT "mtdparts=qspi.0:512k(QSPI.u-boot)," \ | 202 | #define MTDPARTS_DEFAULT "mtdparts=qspi.0:512k(QSPI.u-boot)," \ |
| 203 | "512k(QSPI.u-boot.backup)," \ | 203 | "512k(QSPI.u-boot.backup)," \ |
| 204 | "512k(QSPI.u-boot-spl-os)," \ | 204 | "512k(QSPI.u-boot-spl-os)," \ |
| 205 | "64k(QSPI.u-boot-env)," \ | 205 | "64k(QSPI.u-boot-env)," \ |
| 206 | "64k(QSPI.u-boot-env.backup)," \ | 206 | "64k(QSPI.u-boot-env.backup)," \ |
| 207 | "8m(QSPI.kernel)," \ | 207 | "8m(QSPI.kernel)," \ |
| 208 | "-(QSPI.file-system)" | 208 | "-(QSPI.file-system)" |
| 209 | #endif | 209 | #endif |
| 210 | 210 | ||
| 211 | #if defined(CONFIG_EMMC_BOOT) | 211 | #if defined(CONFIG_EMMC_BOOT) |
| 212 | #undef CONFIG_SPL_OS_BOOT | 212 | #undef CONFIG_SPL_OS_BOOT |
| 213 | #undef CONFIG_ENV_IS_NOWHERE | 213 | #undef CONFIG_ENV_IS_NOWHERE |
| 214 | #define CONFIG_ENV_IS_IN_MMC | 214 | #define CONFIG_ENV_IS_IN_MMC |
| 215 | #define CONFIG_SYS_MMC_ENV_DEV 0 | 215 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 216 | #define CONFIG_SYS_MMC_ENV_PART 0 | 216 | #define CONFIG_SYS_MMC_ENV_PART 0 |
| 217 | 217 | ||
| 218 | #define CONFIG_ENV_OFFSET 0x0 | 218 | #define CONFIG_ENV_OFFSET 0x0 |
| 219 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | 219 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
| 220 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | 220 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
| 221 | #endif | 221 | #endif |
| 222 | 222 | ||
| 223 | /* SPI */ | 223 | /* SPI */ |
| 224 | #define CONFIG_SF_DEFAULT_BUS 0 | 224 | #define CONFIG_SF_DEFAULT_BUS 0 |
| 225 | #define CONFIG_SF_DEFAULT_SPEED 24000000 | 225 | #define CONFIG_SF_DEFAULT_SPEED 24000000 |
| 226 | #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 | 226 | #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 |
| 227 | #define CONFIG_TI_EDMA3 | 227 | #define CONFIG_TI_EDMA3 |
| 228 | 228 | ||
| 229 | /* Enhance our eMMC support / experience. */ | 229 | /* Enhance our eMMC support / experience. */ |
| 230 | #define CONFIG_CMD_GPT | 230 | #define CONFIG_CMD_GPT |
| 231 | #define CONFIG_EFI_PARTITION | 231 | #define CONFIG_EFI_PARTITION |
| 232 | 232 | ||
| 233 | #ifndef CONFIG_SPL_BUILD | 233 | #ifndef CONFIG_SPL_BUILD |
| 234 | #include <environment/ti/dfu.h> | 234 | #include <environment/ti/dfu.h> |
| 235 | #include <environment/ti/mmc.h> | 235 | #include <environment/ti/mmc.h> |
| 236 | 236 | ||
| 237 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 237 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 238 | DEFAULT_LINUX_BOOT_ENV \ | 238 | DEFAULT_LINUX_BOOT_ENV \ |
| 239 | DEFAULT_MMC_TI_ARGS \ | 239 | DEFAULT_MMC_TI_ARGS \ |
| 240 | DEFAULT_FIT_TI_ARGS \ | 240 | DEFAULT_FIT_TI_ARGS \ |
| 241 | "boot_fdt=try\0" \ | 241 | "boot_fdt=try\0" \ |
| 242 | "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ | 242 | "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ |
| 243 | "fdtfile=am437x-smarct437x.dtb\0" \ | 243 | "fdtfile=am437x-smarct437x.dtb\0" \ |
| 244 | "bootpart=${mmcdev}:1\0" \ | 244 | "bootpart=${mmcdev}:1\0" \ |
| 245 | "bootdir=\0" \ | 245 | "bootdir=\0" \ |
| 246 | "fdtdir=/dtbs\0" \ | 246 | "fdtdir=/dtbs\0" \ |
| 247 | "bootfile=zImage\0" \ | 247 | "bootfile=zImage\0" \ |
| 248 | "console=ttyO0,115200n8\0" \ | 248 | "console=ttyO0,115200n8\0" \ |
| 249 | "partitions=" \ | 249 | "partitions=" \ |
| 250 | "uuid_disk=${uuid_gpt_disk};" \ | 250 | "uuid_disk=${uuid_gpt_disk};" \ |
| 251 | "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ | 251 | "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ |
| 252 | "optargs=\0" \ | 252 | "optargs=\0" \ |
| 253 | "cmdline=\0" \ | 253 | "cmdline=\0" \ |
| 254 | "mmcpart=1\0" \ | 254 | "mmcpart=1\0" \ |
| 255 | "mmcroot=/dev/mmcblk0p2 ro\0" \ | 255 | "mmcroot=/dev/mmcblk0p2 ro\0" \ |
| 256 | "usbroot=/dev/sda2 rw\0" \ | 256 | "usbroot=/dev/sda2 rw\0" \ |
| 257 | "usbrootfstype=ext4 rootwait\0" \ | 257 | "usbrootfstype=ext4 rootwait\0" \ |
| 258 | "usbdev=0\0" \ | 258 | "usbdev=0\0" \ |
| 259 | "ramroot=/dev/ram0 rw\0" \ | 259 | "ramroot=/dev/ram0 rw\0" \ |
| 260 | "ramrootfstype=ext2\0" \ | 260 | "ramrootfstype=ext2\0" \ |
| 261 | "usbargs=setenv bootargs console=${console} " \ | 261 | "usbargs=setenv bootargs console=${console} " \ |
| 262 | "${optargs} " \ | 262 | "${optargs} " \ |
| 263 | "root=${usbroot} " \ | 263 | "root=${usbroot} " \ |
| 264 | "rootfstype=${usbrootfstype}\0" \ | 264 | "rootfstype=${usbrootfstype}\0" \ |
| 265 | "bootenv=uEnv.txt\0" \ | 265 | "bootenv=uEnv.txt\0" \ |
| 266 | "script=boot.scr\0" \ | 266 | "script=boot.scr\0" \ |
| 267 | "scriptfile=${script}\0" \ | 267 | "scriptfile=${script}\0" \ |
| 268 | "loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \ | 268 | "loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \ |
| 269 | "bootscript=echo Running bootscript from mmc${bootpart} ...; " \ | 269 | "bootscript=echo Running bootscript from mmc${bootpart} ...; " \ |
| 270 | "source ${loadaddr}\0" \ | 270 | "source ${loadaddr}\0" \ |
| 271 | "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \ | 271 | "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \ |
| 272 | "loadusbbootenv=load usb ${bootpart} ${loadaddr} ${bootenv}\0" \ | 272 | "loadusbbootenv=load usb ${bootpart} ${loadaddr} ${bootenv}\0" \ |
| 273 | "importbootenv=echo Importing environment from mmc ...; " \ | 273 | "importbootenv=echo Importing environment from mmc ...; " \ |
| 274 | "env import -t -r $loadaddr $filesize\0" \ | 274 | "env import -t -r $loadaddr $filesize\0" \ |
| 275 | "importusbbootenv=echo Importing environment from usb ...; " \ | 275 | "importusbbootenv=echo Importing environment from usb ...; " \ |
| 276 | "env import -t -r $loadaddr $filesize\0" \ | 276 | "env import -t -r $loadaddr $filesize\0" \ |
| 277 | "ramargs=setenv bootargs console=${console} " \ | 277 | "ramargs=setenv bootargs console=${console} " \ |
| 278 | "${optargs} " \ | 278 | "${optargs} " \ |
| 279 | "root=${ramroot} " \ | 279 | "root=${ramroot} " \ |
| 280 | "rootfstype=${ramrootfstype}\0" \ | 280 | "rootfstype=${ramrootfstype}\0" \ |
| 281 | "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ | 281 | "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ |
| 282 | "loadimage=load ${devtype} ${mmcdev}:1 ${loadaddr} ${bootdir}/${bootfile}\0" \ | 282 | "loadimage=load ${devtype} ${mmcdev}:1 ${loadaddr} ${bootdir}/${bootfile}\0" \ |
| 283 | "loadfdt=echo loading ${fdtdir}/${fdtfile} ...; load ${devtype} ${mmcdev}:1 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ | 283 | "loadfdt=echo loading ${fdtdir}/${fdtfile} ...; load ${devtype} ${mmcdev}:1 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ |
| 284 | "mmcboot=mmc dev ${mmcdev}; " \ | 284 | "mmcboot=mmc dev ${mmcdev}; " \ |
| 285 | "setenv devnum ${mmcdev}; " \ | 285 | "setenv devnum ${mmcdev}; " \ |
| 286 | "setenv bootpart ${mmcdev}:1; "\ | 286 | "setenv bootpart ${mmcdev}:1; "\ |
| 287 | "setenv devtype mmc; " \ | 287 | "setenv devtype mmc; " \ |
| 288 | "if mmc rescan; then " \ | 288 | "if mmc rescan; then " \ |
| 289 | "echo SD/MMC found on device ${devnum};" \ | 289 | "echo SD/MMC found on device ${devnum};" \ |
| 290 | "if run loadbootenv; then " \ | 290 | "if run loadbootenv; then " \ |
| 291 | "echo Loaded environment from ${bootenv};" \ | 291 | "echo Loaded environment from ${bootenv};" \ |
| 292 | "run importbootenv;" \ | 292 | "run importbootenv;" \ |
| 293 | "fi;" \ | 293 | "fi;" \ |
| 294 | "if test -n $uenvcmd; then " \ | 294 | "if test -n $uenvcmd; then " \ |
| 295 | "echo Running uenvcmd ...;" \ | 295 | "echo Running uenvcmd ...;" \ |
| 296 | "run uenvcmd;" \ | 296 | "run uenvcmd;" \ |
| 297 | "fi;" \ | 297 | "fi;" \ |
| 298 | "if run loadimage; then " \ | 298 | "if run loadimage; then " \ |
| 299 | "run loadfdt; " \ | 299 | "run loadfdt; " \ |
| 300 | "echo Booting from mmc${mmcdev} ...; " \ | 300 | "echo Booting from mmc${mmcdev} ...; " \ |
| 301 | "run args_mmc; " \ | 301 | "run args_mmc; " \ |
| 302 | "bootz ${loadaddr} - ${fdtaddr}; " \ | 302 | "bootz ${loadaddr} - ${fdtaddr}; " \ |
| 303 | "fi;" \ | 303 | "fi;" \ |
| 304 | "fi;\0" \ | 304 | "fi;\0" \ |
| 305 | "usbboot=" \ | 305 | "usbboot=" \ |
| 306 | "setenv devnum ${usbdev}; " \ | 306 | "setenv devnum ${usbdev}; " \ |
| 307 | "setenv devtype usb; " \ | 307 | "setenv devtype usb; " \ |
| 308 | "usb start ${usbdev}; " \ | 308 | "usb start ${usbdev}; " \ |
| 309 | "if usb dev ${usbdev}; then " \ | 309 | "if usb dev ${usbdev}; then " \ |
| 310 | "if run loadusbbootenv; then " \ | 310 | "if run loadusbbootenv; then " \ |
| 311 | "echo Loaded environment from ${bootenv};" \ | 311 | "echo Loaded environment from ${bootenv};" \ |
| 312 | "run importusbbootenv;" \ | 312 | "run importusbbootenv;" \ |
| 313 | "fi;" \ | 313 | "fi;" \ |
| 314 | "if test -n $uenvcmd; then " \ | 314 | "if test -n $uenvcmd; then " \ |
| 315 | "echo Running uenvcmd ...;" \ | 315 | "echo Running uenvcmd ...;" \ |
| 316 | "run uenvcmd;" \ | 316 | "run uenvcmd;" \ |
| 317 | "fi;" \ | 317 | "fi;" \ |
| 318 | "if run loadimage; then " \ | 318 | "if run loadimage; then " \ |
| 319 | "run loadfdt; " \ | 319 | "run loadfdt; " \ |
| 320 | "echo Booting from usb ${usbdev}...; " \ | 320 | "echo Booting from usb ${usbdev}...; " \ |
| 321 | "run usbargs;" \ | 321 | "run usbargs;" \ |
| 322 | "bootz ${loadaddr} - ${fdtaddr}; " \ | 322 | "bootz ${loadaddr} - ${fdtaddr}; " \ |
| 323 | "fi;" \ | 323 | "fi;" \ |
| 324 | "fi\0" \ | 324 | "fi\0" \ |
| 325 | "fi;" \ | 325 | "fi;" \ |
| 326 | "usb stop ${usbdev};\0" \ | 326 | "usb stop ${usbdev};\0" \ |
| 327 | "findfdt="\ | 327 | "findfdt="\ |
| 328 | "if test $board_name = AM43EPOS; then " \ | 328 | "if test $board_name = AM43EPOS; then " \ |
| 329 | "setenv fdtfile am43x-epos-evm.dtb; fi; " \ | 329 | "setenv fdtfile am43x-epos-evm.dtb; fi; " \ |
| 330 | "if test $board_name = AM43__GP; then " \ | 330 | "if test $board_name = AM43__GP; then " \ |
| 331 | "setenv fdtfile am437x-gp-evm.dtb; fi; " \ | 331 | "setenv fdtfile am437x-gp-evm.dtb; fi; " \ |
| 332 | "if test $board_name = AM43XXHS; then " \ | 332 | "if test $board_name = AM43XXHS; then " \ |
| 333 | "setenv fdtfile am437x-gp-evm.dtb; fi; " \ | 333 | "setenv fdtfile am437x-gp-evm.dtb; fi; " \ |
| 334 | "if test $board_name = AM43__SK; then " \ | 334 | "if test $board_name = AM43__SK; then " \ |
| 335 | "setenv fdtfile am437x-sk-evm.dtb; fi; " \ | 335 | "setenv fdtfile am437x-sk-evm.dtb; fi; " \ |
| 336 | "if test $board_name = AM43_IDK; then " \ | 336 | "if test $board_name = AM43_IDK; then " \ |
| 337 | "setenv fdtfile am437x-idk-evm.dtb; fi; " \ | 337 | "setenv fdtfile am437x-idk-evm.dtb; fi; " \ |
| 338 | "if test $board_name = SMCT4X80; then " \ | 338 | "if test $board_name = SMCT4X80; then " \ |
| 339 | "setenv fdtfile am437x-smarct437x.dtb; fi; " \ | 339 | "setenv fdtfile am437x-smarct437x.dtb; fi; " \ |
| 340 | "if test $board_name = SMCT4X1G; then " \ | 340 | "if test $board_name = SMCT4X1G; then " \ |
| 341 | "setenv fdtfile am437x-smarct437x.dtb; fi; " \ | 341 | "setenv fdtfile am437x-smarct437x.dtb; fi; " \ |
| 342 | "if test $fdtfile = undefined; then " \ | 342 | "if test $fdtfile = undefined; then " \ |
| 343 | "echo WARNING: Could not determine device tree; fi; \0" \ | 343 | "echo WARNING: Could not determine device tree; fi; \0" \ |
| 344 | NANDARGS \ | 344 | NANDARGS \ |
| 345 | NETARGS \ | 345 | NETARGS \ |
| 346 | DFUARGS \ | 346 | DFUARGS \ |
| 347 | 347 | ||
| 348 | #define CONFIG_BOOTCOMMAND \ | 348 | #define CONFIG_BOOTCOMMAND \ |
| 349 | "if test ${boot_fit} -eq 1; then " \ | 349 | "if test ${boot_fit} -eq 1; then " \ |
| 350 | "run update_to_fit;" \ | 350 | "run update_to_fit;" \ |
| 351 | "fi;" \ | 351 | "fi;" \ |
| 352 | "run findfdt; " \ | 352 | "run findfdt; " \ |
| 353 | "run envboot;" \ | 353 | "run envboot;" \ |
| 354 | "run mmcboot;" \ | 354 | "run mmcboot;" \ |
| 355 | "run usbboot;" \ | 355 | "run usbboot;" \ |
| 356 | NANDBOOT \ | 356 | NANDBOOT \ |
| 357 | 357 | ||
| 358 | #endif | 358 | #endif |
| 359 | 359 | ||
| 360 | #ifndef CONFIG_SPL_BUILD | 360 | #ifndef CONFIG_SPL_BUILD |
| 361 | /* CPSW Ethernet */ | 361 | /* CPSW Ethernet */ |
| 362 | #define CONFIG_MII | 362 | #define CONFIG_MII |
| 363 | #define CONFIG_BOOTP_DEFAULT | 363 | #define CONFIG_BOOTP_DEFAULT |
| 364 | #define CONFIG_BOOTP_DNS | 364 | #define CONFIG_BOOTP_DNS |
| 365 | #define CONFIG_BOOTP_DNS2 | 365 | #define CONFIG_BOOTP_DNS2 |
| 366 | #define CONFIG_BOOTP_SEND_HOSTNAME | 366 | #define CONFIG_BOOTP_SEND_HOSTNAME |
| 367 | #define CONFIG_BOOTP_GATEWAY | 367 | #define CONFIG_BOOTP_GATEWAY |
| 368 | #define CONFIG_BOOTP_SUBNETMASK | 368 | #define CONFIG_BOOTP_SUBNETMASK |
| 369 | #define CONFIG_NET_RETRY_COUNT 10 | 369 | #define CONFIG_NET_RETRY_COUNT 10 |
| 370 | #define CONFIG_PHY_GIGE | 370 | #define CONFIG_PHY_GIGE |
| 371 | #endif | 371 | #endif |
| 372 | 372 | ||
| 373 | #define CONFIG_DRIVER_TI_CPSW | 373 | #define CONFIG_DRIVER_TI_CPSW |
| 374 | #define CONFIG_PHYLIB | 374 | #define CONFIG_PHYLIB |
| 375 | #define CONFIG_PHY_ATHEROS | 375 | #define CONFIG_PHY_ATHEROS |
| 376 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ | 376 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ |
| 377 | 377 | ||
| 378 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT) | 378 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT) |
| 379 | #undef CONFIG_ENV_IS_IN_FAT | 379 | #undef CONFIG_ENV_IS_IN_FAT |
| 380 | #define CONFIG_ENV_IS_NOWHERE | 380 | #define CONFIG_ENV_IS_NOWHERE |
| 381 | #define CONFIG_SPL_NET_SUPPORT | 381 | #define CONFIG_SPL_NET_SUPPORT |
| 382 | #endif | 382 | #endif |
| 383 | 383 | ||
| 384 | #define CONFIG_SYS_RX_ETH_BUFFER 64 | 384 | #define CONFIG_SYS_RX_ETH_BUFFER 64 |
| 385 | 385 | ||
| 386 | /* NAND support */ | 386 | /* NAND support */ |
| 387 | #ifdef CONFIG_NAND | 387 | #ifdef CONFIG_NAND |
| 388 | /* NAND: device related configs */ | 388 | /* NAND: device related configs */ |
| 389 | #define CONFIG_SYS_NAND_PAGE_SIZE 4096 | 389 | #define CONFIG_SYS_NAND_PAGE_SIZE 4096 |
| 390 | #define CONFIG_SYS_NAND_OOBSIZE 224 | 390 | #define CONFIG_SYS_NAND_OOBSIZE 224 |
| 391 | #define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024) | 391 | #define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024) |
| 392 | #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ | 392 | #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ |
| 393 | CONFIG_SYS_NAND_PAGE_SIZE) | 393 | CONFIG_SYS_NAND_PAGE_SIZE) |
| 394 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | 394 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 395 | /* NAND: driver related configs */ | 395 | /* NAND: driver related configs */ |
| 396 | #define CONFIG_NAND_OMAP_GPMC | 396 | #define CONFIG_NAND_OMAP_GPMC |
| 397 | #define CONFIG_NAND_OMAP_ELM | 397 | #define CONFIG_NAND_OMAP_ELM |
| 398 | #define CONFIG_SYS_NAND_ONFI_DETECTION | 398 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 399 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW | 399 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW |
| 400 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | 400 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS |
| 401 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ | 401 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ |
| 402 | 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ | 402 | 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ |
| 403 | 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ | 403 | 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ |
| 404 | 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ | 404 | 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ |
| 405 | 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ | 405 | 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ |
| 406 | 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ | 406 | 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ |
| 407 | 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ | 407 | 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ |
| 408 | 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ | 408 | 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ |
| 409 | 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ | 409 | 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ |
| 410 | 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ | 410 | 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ |
| 411 | 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ | 411 | 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ |
| 412 | 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ | 412 | 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ |
| 413 | 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ | 413 | 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ |
| 414 | 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ | 414 | 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ |
| 415 | 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ | 415 | 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ |
| 416 | 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ | 416 | 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ |
| 417 | 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ | 417 | 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ |
| 418 | 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ | 418 | 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ |
| 419 | 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ | 419 | 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ |
| 420 | 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ | 420 | 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ |
| 421 | 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ | 421 | 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ |
| 422 | } | 422 | } |
| 423 | #define CONFIG_SYS_NAND_ECCSIZE 512 | 423 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
| 424 | #define CONFIG_SYS_NAND_ECCBYTES 26 | 424 | #define CONFIG_SYS_NAND_ECCBYTES 26 |
| 425 | #define MTDIDS_DEFAULT "nand0=nand.0" | 425 | #define MTDIDS_DEFAULT "nand0=nand.0" |
| 426 | #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ | 426 | #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ |
| 427 | "256k(NAND.SPL)," \ | 427 | "256k(NAND.SPL)," \ |
| 428 | "256k(NAND.SPL.backup1)," \ | 428 | "256k(NAND.SPL.backup1)," \ |
| 429 | "256k(NAND.SPL.backup2)," \ | 429 | "256k(NAND.SPL.backup2)," \ |
| 430 | "256k(NAND.SPL.backup3)," \ | 430 | "256k(NAND.SPL.backup3)," \ |
| 431 | "512k(NAND.u-boot-spl-os)," \ | 431 | "512k(NAND.u-boot-spl-os)," \ |
| 432 | "1m(NAND.u-boot)," \ | 432 | "1m(NAND.u-boot)," \ |
| 433 | "256k(NAND.u-boot-env)," \ | 433 | "256k(NAND.u-boot-env)," \ |
| 434 | "256k(NAND.u-boot-env.backup1)," \ | 434 | "256k(NAND.u-boot-env.backup1)," \ |
| 435 | "7m(NAND.kernel)," \ | 435 | "7m(NAND.kernel)," \ |
| 436 | "-(NAND.file-system)" | 436 | "-(NAND.file-system)" |
| 437 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000 | 437 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000 |
| 438 | /* NAND: SPL related configs */ | 438 | /* NAND: SPL related configs */ |
| 439 | #ifdef CONFIG_SPL_NAND_SUPPORT | 439 | #ifdef CONFIG_SPL_NAND_SUPPORT |
| 440 | #define CONFIG_SPL_NAND_AM33XX_BCH | 440 | #define CONFIG_SPL_NAND_AM33XX_BCH |
| 441 | #endif | 441 | #endif |
| 442 | /* NAND: SPL falcon mode configs */ | 442 | /* NAND: SPL falcon mode configs */ |
| 443 | #ifdef CONFIG_SPL_OS_BOOT | 443 | #ifdef CONFIG_SPL_OS_BOOT |
| 444 | #define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */ | 444 | #define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */ |
| 445 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ | 445 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ |
| 446 | #define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | 446 | #define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| 447 | #endif | 447 | #endif |
| 448 | #define NANDARGS \ | 448 | #define NANDARGS \ |
| 449 | "mtdids=" MTDIDS_DEFAULT "\0" \ | 449 | "mtdids=" MTDIDS_DEFAULT "\0" \ |
| 450 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | 450 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ |
| 451 | "nandargs=setenv bootargs console=${console} " \ | 451 | "nandargs=setenv bootargs console=${console} " \ |
| 452 | "${optargs} " \ | 452 | "${optargs} " \ |
| 453 | "root=${nandroot} " \ | 453 | "root=${nandroot} " \ |
| 454 | "rootfstype=${nandrootfstype}\0" \ | 454 | "rootfstype=${nandrootfstype}\0" \ |
| 455 | "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \ | 455 | "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \ |
| 456 | "nandrootfstype=ubifs rootwait=1\0" \ | 456 | "nandrootfstype=ubifs rootwait=1\0" \ |
| 457 | "nandboot=echo Booting from nand ...; " \ | 457 | "nandboot=echo Booting from nand ...; " \ |
| 458 | "run nandargs; " \ | 458 | "run nandargs; " \ |
| 459 | "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ | 459 | "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ |
| 460 | "nand read ${loadaddr} NAND.kernel; " \ | 460 | "nand read ${loadaddr} NAND.kernel; " \ |
| 461 | "bootz ${loadaddr} - ${fdtaddr}\0" | 461 | "bootz ${loadaddr} - ${fdtaddr}\0" |
| 462 | #define NANDBOOT "run nandboot; " | 462 | #define NANDBOOT "run nandboot; " |
| 463 | #else /* !CONFIG_NAND */ | 463 | #else /* !CONFIG_NAND */ |
| 464 | #define NANDARGS | 464 | #define NANDARGS |
| 465 | #define NANDBOOT | 465 | #define NANDBOOT |
| 466 | #endif /* CONFIG_NAND */ | 466 | #endif /* CONFIG_NAND */ |
| 467 | 467 | ||
| 468 | #if defined(CONFIG_TI_SECURE_DEVICE) | 468 | #if defined(CONFIG_TI_SECURE_DEVICE) |
| 469 | /* Avoid relocating onto firewalled area at end of DRAM */ | 469 | /* Avoid relocating onto firewalled area at end of DRAM */ |
| 470 | #define CONFIG_PRAM (64 * 1024) | 470 | #define CONFIG_PRAM (64 * 1024) |
| 471 | #endif /* CONFIG_TI_SECURE_DEVICE */ | 471 | #endif /* CONFIG_TI_SECURE_DEVICE */ |
| 472 | 472 | ||
| 473 | #endif /* __CONFIG_SMARCT437X_EVM_H */ | 473 | #endif /* __CONFIG_SMARCT437X_EVM_H */ |
| 474 | 474 |