Eric Lee / smarc-uboot | Embedian Git Server

Commit ce3c9a59afd0591a105a316335d7015d8d902367

Authored by Vipul Kumar 2018-02-16 21:37:20 +0800

Committed by Michal Simek 2018-03-01 15:03:01 +0800

Exists in smarc_8mq_lf_v2020.04 and in 17 other branches

i2c: Added Kconfig support for CONFIG_SYS_I2C_ZYNQ_SPEED

This patch added Kconfig support for CONFIG_SYS_I2C_ZYNQ_SPEED
and set it to default value 100000.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Showing 3 changed files with 7 additions and 2 deletions Inline Diff

drivers/i2c/Kconfig
include/configs/xilinx_zynqmp.h
include/configs/zynq-common.h

drivers/i2c/Kconfig

Diff comments View file @ ce3c9a5

 #
 # I2C subsystem configuration
 #
 menu "I2C support"
 config DM_I2C
 	bool "Enable Driver Model for I2C drivers"
 	depends on DM
 	help
 	  Enable driver model for I2C. The I2C uclass interface: probe, read,
 	  write and speed, is implemented with the bus drivers operations,
 	  which provide methods for bus setting and data transfer. Each chip
 	  device (bus child) info is kept as parent platdata. The interface
 	  is defined in include/i2c.h. When i2c bus driver supports the i2c
 	  uclass, but the device drivers not, then DM_I2C_COMPAT config can
 	  be used as compatibility layer.
 config DM_I2C_COMPAT
 	bool "Enable I2C compatibility layer"
 	depends on DM
 	help
 	  Enable old-style I2C functions for compatibility with existing code.
 	  This option can be enabled as a temporary measure to avoid needing
 	  to convert all code for a board in a single commit. It should not
 	  be enabled for any board in an official release.
 config I2C_CROS_EC_TUNNEL
 	tristate "Chrome OS EC tunnel I2C bus"
 	depends on CROS_EC
 	help
 	  This provides an I2C bus that will tunnel i2c commands through to
 	  the other side of the Chrome OS EC to the I2C bus connected there.
 	  This will work whatever the interface used to talk to the EC (SPI,
 	  I2C or LPC). Some Chromebooks use this when the hardware design
 	  does not allow direct access to the main PMIC from the AP.
 config I2C_CROS_EC_LDO
 	bool "Provide access to LDOs on the Chrome OS EC"
 	depends on CROS_EC
 	---help---
 	On many Chromebooks the main PMIC is inaccessible to the AP. This is
 	often dealt with by using an I2C pass-through interface provided by
 	the EC. On some unfortunate models (e.g. Spring) the pass-through
 	is not available, and an LDO message is available instead. This
 	option enables a driver which provides very basic access to those
 	regulators, via the EC. We implement this as an I2C bus	which
 	emulates just the TPS65090 messages we know about. This is done to
 	avoid duplicating the logic in the TPS65090 regulator driver for
 	enabling/disabling an LDO.
 config I2C_SET_DEFAULT_BUS_NUM
 	bool "Set default I2C bus number"
 	depends on DM_I2C
 	help
 	  Set default number of I2C bus to be accessed. This option provides
 	  behaviour similar to old (i.e. pre DM) I2C bus driver.
 config I2C_DEFAULT_BUS_NUMBER
 	hex "I2C default bus number"
 	depends on I2C_SET_DEFAULT_BUS_NUM
 	default 0x0
 	help
 	  Number of default I2C bus to use
 config DM_I2C_GPIO
 	bool "Enable Driver Model for software emulated I2C bus driver"
 	depends on DM_I2C && DM_GPIO
 	help
 	  Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
 	  configuration is given by the device tree. Kernel-style device tree
 	  bindings are supported.
 	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
 config SYS_I2C_AT91
 	bool "Atmel I2C driver"
 	depends on DM_I2C && ARCH_AT91
 	help
 	  Add support for the Atmel I2C driver. A serious problem is that there
 	  is no documented way to issue repeated START conditions for more than
 	  two messages, as needed to support combined I2C messages. Use the
 	  i2c-gpio driver unless your system can cope with this limitation.
 	  Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
 config SYS_I2C_FSL
        bool "Freescale I2C bus driver"
        depends on DM_I2C
        help
 	  Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
 	  MPC85xx processors.
 config SYS_I2C_CADENCE
 	tristate "Cadence I2C Controller"
 	depends on DM_I2C && (ARCH_ZYNQ || ARM64)
 	help
 	  Say yes here to select Cadence I2C Host Controller. This controller is
 	  e.g. used by Xilinx Zynq.
 config SYS_I2C_DW
 	bool "Designware I2C Controller"
 	default n
 	help
 	  Say yes here to select the Designware I2C Host Controller. This
 	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
 	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
 config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
 	bool "DW I2C Enable Status Register not supported"
 	depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
 		TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
 	default y
 	help
 	  Some versions of the Designware I2C controller do not support the
 	  enable status register. This config option can be enabled in such
 	  cases.
 config SYS_I2C_ASPEED
 	bool "Aspeed I2C Controller"
 	depends on DM_I2C && ARCH_ASPEED
 	help
 	  Say yes here to select Aspeed I2C Host Controller. The driver
 	  supports AST2500 and AST2400 controllers, but is very limited.
 	  Only single master mode is supported and only byte-by-byte
 	  synchronous reads and writes are supported, no Pool Buffers or DMA.
 config SYS_I2C_INTEL
 	bool "Intel I2C/SMBUS driver"
 	depends on DM_I2C
 	help
 	  Add support for the Intel SMBUS driver. So far this driver is just
 	  a stub which perhaps some basic init. There is no implementation of
 	  the I2C API meaning that any I2C operations will immediately fail
 	  for now.
 config SYS_I2C_IMX_LPI2C
 	bool "NXP i.MX LPI2C driver"
 	help
 	  Add support for the NXP i.MX LPI2C driver.
 config SYS_I2C_MESON
 	bool "Amlogic Meson I2C driver"
 	depends on DM_I2C && ARCH_MESON
 	help
 	  Add support for the I2C controller available in Amlogic Meson
 	  SoCs. The controller supports programmable bus speed including
 	  standard (100kbits/s) and fast (400kbit/s) speed and allows the
 	  software to define a flexible format of the bit streams. It has an
 	  internal buffer holding up to 8 bytes for transfers and supports
 	  both 7-bit and 10-bit addresses.
 config SYS_I2C_MXC
 	bool "NXP i.MX I2C driver"
 	depends on MX6
 	help
 	  Add support for the NXP i.MX I2C driver. This supports upto for bus
 	  channels and operating on standard mode upto 100 kbits/s and fast
 	  mode upto 400 kbits/s.
 config SYS_I2C_OMAP24XX
 	bool "TI OMAP2+ I2C driver"
 	depends on ARCH_OMAP2PLUS
 	help
 	  Add support for the OMAP2+ I2C driver.
 if SYS_I2C_OMAP24XX
 config SYS_OMAP24_I2C_SLAVE
 	int "I2C Slave addr channel 0"
 	default 1
 	help
 	  OMAP24xx I2C Slave address channel 0
 config SYS_OMAP24_I2C_SPEED
 	int "I2C Slave channel 0 speed"
 	default 100000
 	help
 	  OMAP24xx Slave speed channel 0
 endif
 config SYS_I2C_RCAR_IIC
 	bool "Renesas RCar Gen3 IIC driver"
 	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
 	help
 	  Support for Renesas RCar Gen3 IIC controller.
 config SYS_I2C_ROCKCHIP
 	bool "Rockchip I2C driver"
 	depends on DM_I2C
 	help
 	  Add support for the Rockchip I2C driver. This is used with various
 	  Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
 	  have several I2C ports and all are provided, controled by the
 	  device tree.
 config SYS_I2C_SANDBOX
 	bool "Sandbox I2C driver"
 	depends on SANDBOX && DM_I2C
 	help
 	  Enable I2C support for sandbox. This is an emulation of a real I2C
 	  bus. Devices can be attached to the bus using the device tree
 	  which specifies the driver to use.  See sandbox.dts as an example.
 config SYS_I2C_S3C24X0
 	bool "Samsung I2C driver"
 	depends on ARCH_EXYNOS4 && DM_I2C
 	help
 	  Support for Samsung I2C controller as Samsung SoCs.
 config SYS_I2C_STM32F7
 	bool "STMicroelectronics STM32F7 I2C support"
 	depends on (STM32F7 || STM32H7) && DM_I2C
 	help
 	  Enable this option to add support for STM32 I2C controller
 	  introduced with STM32F7/H7 SoCs. This I2C controller supports :
 	   _ Slave and master modes
 	   _ Multimaster capability
 	   _ Standard-mode (up to 100 kHz)
 	   _ Fast-mode (up to 400 kHz)
 	   _ Fast-mode Plus (up to 1 MHz)
 	   _ 7-bit and 10-bit addressing mode
 	   _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
 	   _ All 7-bit addresses acknowledge mode
 	   _ General call
 	   _ Programmable setup and hold times
 	   _ Easy to use event management
 	   _ Optional clock stretching
 	   _ Software reset
 config SYS_I2C_UNIPHIER
 	bool "UniPhier I2C driver"
 	depends on ARCH_UNIPHIER && DM_I2C
 	default y
 	help
 	  Support for UniPhier I2C controller driver.  This I2C controller
 	  is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
 config SYS_I2C_UNIPHIER_F
 	bool "UniPhier FIFO-builtin I2C driver"
 	depends on ARCH_UNIPHIER && DM_I2C
 	default y
 	help
 	  Support for UniPhier FIFO-builtin I2C controller driver.
 	  This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
 config SYS_I2C_MVTWSI
 	bool "Marvell I2C driver"
 	depends on DM_I2C
 	help
 	  Support for Marvell I2C controllers as used on the orion5x and
 	  kirkwood SoC families.
 config TEGRA186_BPMP_I2C
 	bool "Enable Tegra186 BPMP-based I2C driver"
 	depends on TEGRA186_BPMP
 	help
 	  Support for Tegra I2C controllers managed by the BPMP (Boot and
 	  Power Management Processor). On Tegra186, some I2C controllers are
 	  directly controlled by the main CPU, whereas others are controlled
 	  by the BPMP, and can only be accessed by the main CPU via IPC
 	  requests to the BPMP. This driver covers the latter case.
 config SYS_I2C_BUS_MAX
 	int "Max I2C busses"
 	depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
 	default 2 if TI816X
 	default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
 	default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
 	default 5 if OMAP54XX
 	help
 	  Define the maximum number of available I2C buses.
 config SYS_I2C_ZYNQ
 	bool "Xilinx I2C driver"
 	depends on ARCH_ZYNQMP || ARCH_ZYNQ
 	help
 	  Support for Xilinx I2C controller.
 config SYS_I2C_ZYNQ_SLAVE
 	hex "Set slave addr"
 	depends on SYS_I2C_ZYNQ
 	default 0
 	help
 	  Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr.
+config SYS_I2C_ZYNQ_SPEED
+	int "Set I2C speed"
+	depends on SYS_I2C_ZYNQ
+	default 100000
+	help
+	  Set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting.
 config SYS_I2C_IHS
         bool "gdsys IHS I2C driver"
         depends on DM_I2C
         help
           Support for gdsys IHS I2C driver on FPGA bus.
 source "drivers/i2c/muxes/Kconfig"
 endmenu

include/configs/xilinx_zynqmp.h

Diff comments View file @ ce3c9a5

 /*
  * Configuration for Xilinx ZynqMP
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
  * Michal Simek <michal.simek@xilinx.com>
  *
  * Based on Configuration for Versatile Express
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __XILINX_ZYNQMP_H
 #define __XILINX_ZYNQMP_H
 #define CONFIG_REMAKE_ELF
 /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
 /* Generic Interrupt Controller Definitions */
 #define CONFIG_GICV2
 #define GICD_BASE	0xF9010000
 #define GICC_BASE	0xF9020000
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_SCRATCH	0xfffc0000
 #ifndef CONFIG_NR_DRAM_BANKS
 # define CONFIG_NR_DRAM_BANKS		2
 #endif
 #define CONFIG_SYS_MEMTEST_START	0
 #define CONFIG_SYS_MEMTEST_END		1000
 #define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
 /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
 #if !defined(COUNTER_FREQUENCY)
 # define COUNTER_FREQUENCY		100000000
 #endif
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x2000000)
 /* Serial setup */
 #define CONFIG_ARM_DCC
 #define CONFIG_CPU_ARMV8
 #define CONFIG_CONS_INDEX		0
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{ 4800, 9600, 19200, 38400, 57600, 115200 }
 /* Command line configuration */
 #define CONFIG_MP
 /* BOOTP options */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_MAY_FAIL
 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
 # define CONFIG_SUPPORT_EMMC_BOOT
 # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
 #  define CONFIG_ZYNQ_SDHCI_MAX_FREQ	200000000
 # endif
 #endif
 #ifdef CONFIG_NAND_ARASAN
 # define CONFIG_SYS_MAX_NAND_DEVICE	1
 # define CONFIG_SYS_NAND_ONFI_DETECTION
 # define CONFIG_MTD_DEVICE
 #endif
 #if defined(CONFIG_SPL_BUILD)
 #define CONFIG_ZYNQMP_PSU_INIT_ENABLED
 #endif
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR		0x8000000
 #if defined(CONFIG_ZYNQMP_USB)
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 #define CONFIG_USB_CABLE_CHECK
 #define CONFIG_THOR_RESET_OFF
 #define DFU_ALT_INFO_RAM \
 	"dfu_ram_info=" \
 	"setenv dfu_alt_info " \
 	"Image ram $kernel_addr $kernel_size\\\\;" \
 	"system.dtb ram $fdt_addr $fdt_size\0" \
 	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
 	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
 #define DFU_ALT_INFO  \
 		DFU_ALT_INFO_RAM
 #ifndef CONFIG_SPL_BUILD
 # define PARTS_DEFAULT \
 	"partitions=uuid_disk=${uuid_gpt_disk};" \
 	"name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \
 	"name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0"
 #endif
 #endif
 #if !defined(DFU_ALT_INFO)
 # define DFU_ALT_INFO
 #endif
 #if !defined(PARTS_DEFAULT)
 # define PARTS_DEFAULT
 #endif
 /* Do not preserve environment */
 #define CONFIG_ENV_SIZE			0x8000
 /* Monitor Command Prompt */
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		2048
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define CONFIG_PANIC_HANG
 #define CONFIG_SYS_MAXARGS		64
 /* Ethernet driver */
 #if defined(CONFIG_ZYNQ_GEM)
 # define CONFIG_MII
 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 # define PHY_ANEG_TIMEOUT       20000
 #endif
 /* I2C */
 #if defined(CONFIG_SYS_I2C_ZYNQ)
 # define CONFIG_SYS_I2C
-# define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
 #endif
 /* EEPROM */
 #ifdef CONFIG_ZYNQMP_EEPROM
 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
 # define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
 # define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
 # define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
 # define CONFIG_SYS_EEPROM_SIZE			(64 * 1024)
 #endif
 #ifdef CONFIG_SATA_CEVA
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 					 CONFIG_SYS_SCSI_MAX_LUN)
 #endif
 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_CLOCKS
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"fdt_high=10000000\0" \
 	"initrd_high=10000000\0" \
 	"fdt_addr_r=0x40000000\0" \
 	"pxefile_addr_r=0x10000000\0" \
 	"kernel_addr_r=0x18000000\0" \
 	"scriptaddr=0x02000000\0" \
 	"ramdisk_addr_r=0x02100000\0" \
 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
 # define BOOT_TARGET_DEVICES_MMC(func)	func(MMC, mmc, 0) func(MMC, mmc, 1)
 #else
 # define BOOT_TARGET_DEVICES_MMC(func)
 #endif
 #if defined(CONFIG_SATA_CEVA)
 # define BOOT_TARGET_DEVICES_SCSI(func)	func(SCSI, scsi, 0)
 #else
 # define BOOT_TARGET_DEVICES_SCSI(func)
 #endif
 #if defined(CONFIG_ZYNQMP_USB)
 # define BOOT_TARGET_DEVICES_USB(func)	func(USB, usb, 0) func(USB, usb, 1)
 #else
 # define BOOT_TARGET_DEVICES_USB(func)
 #endif
 #define BOOT_TARGET_DEVICES(func) \
 	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_USB(func) \
 	BOOT_TARGET_DEVICES_SCSI(func) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 /* Initial environment variables */
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	BOOTENV \
 	DFU_ALT_INFO
 #endif
 /* SPL can't handle all huge variables - define just DFU */
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT)
 #undef CONFIG_EXTRA_ENV_SETTINGS
 # define CONFIG_EXTRA_ENV_SETTINGS \
 	"dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \
 			  "atf-uboot.ub ram 0x10000000 0x1000000;" \
 			  "Image ram 0x80000 0x3f80000;" \
 			  "system.dtb ram 0x4000000 0x100000\0" \
 	"dfu_bufsiz=0x1000\0"
 #endif
 #define CONFIG_SPL_TEXT_BASE		0xfffc0000
 #define CONFIG_SPL_STACK		0xfffffffc
 #define CONFIG_SPL_MAX_SIZE		0x40000
 /* Just random location in OCM */
 #define CONFIG_SPL_BSS_START_ADDR	0x0
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
 #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
 # define CONFIG_SPL_SPI_LOAD
 # define CONFIG_SYS_SPI_KERNEL_OFFS	0x80000
 # define CONFIG_SYS_SPI_ARGS_OFFS	0xa0000
 # define CONFIG_SYS_SPI_ARGS_SIZE	0xa0000
 # define CONFIG_SYS_SPI_U_BOOT_OFFS	0x170000
 #endif
 /* u-boot is like dtb */
 #define CONFIG_SPL_FS_LOAD_ARGS_NAME	"u-boot.bin"
 #define CONFIG_SYS_SPL_ARGS_ADDR	0x8000000
 /* ATF is my kernel image */
 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"atf-uboot.ub"
 /* FIT load address for RAM boot */
 #define CONFIG_SPL_LOAD_FIT_ADDRESS	0x10000000
 /* MMC support */
 #ifdef CONFIG_MMC_SDHCI_ZYNQ
 # define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
 # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0 /* unused */
 # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0 /* unused */
 # define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0 /* unused */
 # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 #endif
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT)
 # undef CONFIG_CMD_BOOTD
 # define CONFIG_SPL_ENV_SUPPORT
 # define CONFIG_SPL_HASH_SUPPORT
 # define CONFIG_ENV_MAX_ENTRIES	10
 #endif
 #define CONFIG_SYS_SPL_MALLOC_START	0x20000000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
 # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
 #endif
 #define CONFIG_BOARD_EARLY_INIT_F
 #endif /* __XILINX_ZYNQMP_H */

include/configs/zynq-common.h

Diff comments View file @ ce3c9a5

 /*
  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
  * (C) Copyright 2013 - 2018 Xilinx, Inc.
  *
  * Common configuration options for all Zynq boards.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_ZYNQ_COMMON_H
 #define __CONFIG_ZYNQ_COMMON_H
 /* CPU clock */
 #ifndef CONFIG_CPU_FREQ_HZ
 # define CONFIG_CPU_FREQ_HZ	800000000
 #endif
 /* Cache options */
 #define CONFIG_SYS_L2CACHE_OFF
 #ifndef CONFIG_SYS_L2CACHE_OFF
 # define CONFIG_SYS_L2_PL310
 # define CONFIG_SYS_PL310_BASE		0xf8f02000
 #endif
 #define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
 #define CONFIG_SYS_TIMERBASE		ZYNQ_SCUTIMER_BASEADDR
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
 /* Serial drivers */
 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 #define CONFIG_ARM_DCC
 /* Ethernet driver */
 #if defined(CONFIG_ZYNQ_GEM)
 # define CONFIG_MII
 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 # define CONFIG_BOOTP_MAY_FAIL
 #endif
 /* SPI */
 #ifdef CONFIG_ZYNQ_SPI
 #endif
 /* QSPI */
 #ifdef CONFIG_ZYNQ_QSPI
 # define CONFIG_SF_DEFAULT_SPEED	30000000
 # define CONFIG_SPI_FLASH_ISSI
 #endif
 /* NOR */
 #ifdef CONFIG_MTD_NOR_FLASH
 # define CONFIG_SYS_FLASH_BASE		0xE2000000
 # define CONFIG_SYS_FLASH_SIZE		(16 * 1024 * 1024)
 # define CONFIG_SYS_MAX_FLASH_BANKS	1
 # define CONFIG_SYS_MAX_FLASH_SECT	512
 # define CONFIG_SYS_FLASH_ERASE_TOUT	1000
 # define CONFIG_SYS_FLASH_WRITE_TOUT	5000
 # define CONFIG_FLASH_SHOW_PROGRESS	10
 # define CONFIG_SYS_FLASH_CFI
 # undef CONFIG_SYS_FLASH_EMPTY_INFO
 # define CONFIG_FLASH_CFI_DRIVER
 # undef CONFIG_SYS_FLASH_PROTECTION
 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 #ifdef CONFIG_NAND_ZYNQ
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_MTD_DEVICE
 #endif
 /* MMC */
 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
 # define CONFIG_ZYNQ_SDHCI_MAX_FREQ	52000000
 #endif
 #ifdef CONFIG_USB_EHCI_ZYNQ
 # define CONFIG_EHCI_IS_TDI
 # define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x600000
 # define DFU_DEFAULT_POLL_TIMEOUT	300
 # define CONFIG_USB_CABLE_CHECK
 # define CONFIG_THOR_RESET_OFF
 # define DFU_ALT_INFO_RAM \
 	"dfu_ram_info=" \
 	"set dfu_alt_info " \
 	"${kernel_image} ram 0x3000000 0x500000\\\\;" \
 	"${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
 	"${ramdisk_image} ram 0x2000000 0x600000\0" \
 	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
 	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
 # if defined(CONFIG_MMC_SDHCI_ZYNQ)
 #  define DFU_ALT_INFO_MMC \
 	"dfu_mmc_info=" \
 	"set dfu_alt_info " \
 	"${kernel_image} fat 0 1\\\\;" \
 	"${devicetree_image} fat 0 1\\\\;" \
 	"${ramdisk_image} fat 0 1\0" \
 	"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
 	"thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
 #  define DFU_ALT_INFO	\
 	DFU_ALT_INFO_RAM \
 	DFU_ALT_INFO_MMC
 # else
 #  define DFU_ALT_INFO	\
 	DFU_ALT_INFO_RAM
 # endif
 #endif
 #if !defined(DFU_ALT_INFO)
 # define DFU_ALT_INFO
 #endif
 /* I2C */
 #if defined(CONFIG_SYS_I2C_ZYNQ)
 # define CONFIG_SYS_I2C
-# define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
 #endif
 /* EEPROM */
 #ifdef CONFIG_ZYNQ_EEPROM
 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
 # define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
 # define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
 # define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
 # define CONFIG_SYS_EEPROM_SIZE			1024 /* Bytes */
 #endif
 /* Total Size of Environment Sector */
 #define CONFIG_ENV_SIZE			(128 << 10)
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 /* Environment */
 #ifndef CONFIG_ENV_IS_NOWHERE
 # define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
 # define CONFIG_ENV_OFFSET		0xE0000
 #endif
 /* enable preboot to be loaded before CONFIG_BOOTDELAY */
 #define CONFIG_PREBOOT
 /* Boot configuration */
 #define CONFIG_SYS_LOAD_ADDR		0 /* default? */
 /* Distro boot enablement */
 #ifdef CONFIG_SPL_BUILD
 #define BOOTENV
 #else
 #ifdef CONFIG_CMD_MMC
 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 #else
 #define BOOT_TARGET_DEVICES_MMC(func)
 #endif
 #ifdef CONFIG_CMD_USB
 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
 #else
 #define BOOT_TARGET_DEVICES_USB(func)
 #endif
 #if defined(CONFIG_CMD_PXE)
 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 #else
 #define BOOT_TARGET_DEVICES_PXE(func)
 #endif
 #if defined(CONFIG_CMD_DHCP)
 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
 #else
 #define BOOT_TARGET_DEVICES_DHCP(func)
 #endif
 #define BOOT_TARGET_DEVICES(func) \
 	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_USB(func) \
 	BOOT_TARGET_DEVICES_PXE(func) \
 	BOOT_TARGET_DEVICES_DHCP(func)
 #include <config_distro_bootcmd.h>
 #endif /* CONFIG_SPL_BUILD */
 /* Default environment */
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"fit_image=fit.itb\0"		\
 	"load_addr=0x2000000\0"		\
 	"fit_size=0x800000\0"		\
 	"flash_off=0x100000\0"		\
 	"nor_flash_off=0xE2100000\0"	\
 	"fdt_high=0x20000000\0"		\
 	"initrd_high=0x20000000\0"	\
 	"loadbootenv_addr=0x2000000\0" \
 	"fdt_addr_r=0x1f00000\0"        \
 	"pxefile_addr_r=0x2000000\0"    \
 	"kernel_addr_r=0x2000000\0"     \
 	"scriptaddr=0x3000000\0"        \
 	"ramdisk_addr_r=0x3100000\0"    \
 	"bootenv=uEnv.txt\0" \
 	"bootenv_dev=mmc\0" \
 	"loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
 	"importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
 		"env import -t ${loadbootenv_addr} $filesize\0" \
 	"bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
 	"setbootenv=if env run bootenv_existence_test; then " \
 			"if env run loadbootenv; then " \
 				"env run importbootenv; " \
 			"fi; " \
 		"fi; \0" \
 	"sd_loadbootenv=set bootenv_dev mmc && " \
 			"run setbootenv \0" \
 	"usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \
 	"preboot=if test $modeboot = sdboot; then " \
 			"run sd_loadbootenv; " \
 			"echo Checking if uenvcmd is set ...; " \
 			"if test -n $uenvcmd; then " \
 				"echo Running uenvcmd ...; " \
 				"run uenvcmd; " \
 			"fi; " \
 		"fi; \0" \
 	"norboot=echo Copying FIT from NOR flash to RAM... && " \
 		"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
 		"bootm ${load_addr}\0" \
 	"sdboot=echo Copying FIT from SD to RAM... && " \
 		"load mmc 0 ${load_addr} ${fit_image} && " \
 		"bootm ${load_addr}\0" \
 	"jtagboot=echo TFTPing FIT to RAM... && " \
 		"tftpboot ${load_addr} ${fit_image} && " \
 		"bootm ${load_addr}\0" \
 	"usbboot=if usb start; then " \
 			"echo Copying FIT from USB to RAM... && " \
 			"load usb 0 ${load_addr} ${fit_image} && " \
 			"bootm ${load_addr}; fi\0" \
 		DFU_ALT_INFO \
 		BOOTENV
 #endif
 /* Miscellaneous configurable options */
 #define CONFIG_CLOCKS
 #define CONFIG_SYS_MAXARGS		32 /* max number of command args */
 #ifndef CONFIG_NR_DRAM_BANKS
 # define CONFIG_NR_DRAM_BANKS		1
 #endif
 #define CONFIG_SYS_MEMTEST_START	0
 #define CONFIG_SYS_MEMTEST_END		0x1000
 #define CONFIG_SYS_MALLOC_LEN		0x1400000
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
 					CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 /* FIT support */
 #define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
 /* Extend size of kernel image for uncompression */
 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
 /* Boot FreeBSD/vxWorks from an ELF image */
 #define CONFIG_SYS_MMC_MAX_DEVICE	1
 #define CONFIG_SYS_LDSCRIPT  "arch/arm/mach-zynq/u-boot.lds"
 /* Commands */
 /* SPL part */
 /* MMC support */
 #ifdef CONFIG_MMC_SDHCI_ZYNQ
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
 #endif
 /* Disable dcache for SPL just for sure */
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_DCACHE_OFF
 #endif
 /* Address in RAM where the parameters must be copied by SPL. */
 #define CONFIG_SYS_SPL_ARGS_ADDR	0x10000000
 #define CONFIG_SPL_FS_LOAD_ARGS_NAME		"system.dtb"
 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
 /* Not using MMC raw mode - just for compilation purpose */
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0
 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0
 /* qspi mode is working fine */
 #ifdef CONFIG_ZYNQ_QSPI
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
 #define CONFIG_SYS_SPI_ARGS_OFFS	0x200000
 #define CONFIG_SYS_SPI_ARGS_SIZE	0x80000
 #define CONFIG_SYS_SPI_KERNEL_OFFS	(CONFIG_SYS_SPI_ARGS_OFFS + \
 					CONFIG_SYS_SPI_ARGS_SIZE)
 #endif
 /* for booting directly linux */
 /* SP location before relocation, must use scratch RAM */
 #define CONFIG_SPL_TEXT_BASE	0x0
 /* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
 #define CONFIG_SPL_MAX_SIZE	0x30000
 /* On the top of OCM space */
 #define CONFIG_SYS_SPL_MALLOC_START	CONFIG_SPL_STACK_R_ADDR
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x2000000
 /*
  * SPL stack position - and stack goes down
  * 0xfffffe00 is used for putting wfi loop.
  * Set it up as limit for now.
  */
 #define CONFIG_SPL_STACK	0xfffffe00
 /* BSS setup */
 #define CONFIG_SPL_BSS_START_ADDR	0x100000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x100000
 #define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
 #endif /* __CONFIG_ZYNQ_COMMON_H */