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Commit cff14475967f90ba49c81128f47923a3bd2a66bd

Authored by Wasim Khan
Committed by Priyanka Jain
1 parent 254a7e3ff9
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

armv8: lx2: SVR_SOC_VER: Mask CAN_FD and security bit 

Multiple LX2(LX2160A/LX2162A SoC) personality variants
exists based on CAN-FD and security bit in SVR.

Currenly SVR_SOC_VER mask only security bit.
Update SVR_SOC_VER to mask CAN_FD and security bit
for LX2 products.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>

Showing 1 changed file with 5 additions and 2 deletions Inline Diff

arch/arm/include/asm/arch-fsl-layerscape/soc.h
Diff comments   View file @ cff1447
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2017-2020 NXP 3 * Copyright 2017-2021 NXP
4 * Copyright 2015 Freescale Semiconductor 4 * Copyright 2015 Freescale Semiconductor
5 */ 5 */
6 6
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
9 9
10 #ifndef __ASSEMBLY__ 10 #ifndef __ASSEMBLY__
11 #include <linux/types.h> 11 #include <linux/types.h>
12 #ifdef CONFIG_FSL_LSCH2 12 #ifdef CONFIG_FSL_LSCH2
13 #include <asm/arch/immap_lsch2.h> 13 #include <asm/arch/immap_lsch2.h>
14 #endif 14 #endif
15 #ifdef CONFIG_FSL_LSCH3 15 #ifdef CONFIG_FSL_LSCH3
16 #include <asm/arch/immap_lsch3.h> 16 #include <asm/arch/immap_lsch3.h>
17 #endif 17 #endif
18 #endif 18 #endif
19 #include <asm/arch/svr.h> 19 #include <asm/arch/svr.h>
20 20
21 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 21 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
22 #define gur_in32(a) in_le32(a) 22 #define gur_in32(a) in_le32(a)
23 #define gur_out32(a, v) out_le32(a, v) 23 #define gur_out32(a, v) out_le32(a, v)
24 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) 24 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
25 #define gur_in32(a) in_be32(a) 25 #define gur_in32(a) in_be32(a)
26 #define gur_out32(a, v) out_be32(a, v) 26 #define gur_out32(a, v) out_be32(a, v)
27 #endif 27 #endif
28 28
29 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE 29 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
30 #define scfg_in32(a) in_le32(a) 30 #define scfg_in32(a) in_le32(a)
31 #define scfg_out32(a, v) out_le32(a, v) 31 #define scfg_out32(a, v) out_le32(a, v)
32 #define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear) 32 #define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
33 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set) 33 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
34 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) 34 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
35 #define scfg_in32(a) in_be32(a) 35 #define scfg_in32(a) in_be32(a)
36 #define scfg_out32(a, v) out_be32(a, v) 36 #define scfg_out32(a, v) out_be32(a, v)
37 #define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear) 37 #define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
38 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set) 38 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
39 #endif 39 #endif
40 40
41 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE 41 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE
42 #define pex_lut_in32(a) in_le32(a) 42 #define pex_lut_in32(a) in_le32(a)
43 #define pex_lut_out32(a, v) out_le32(a, v) 43 #define pex_lut_out32(a, v) out_le32(a, v)
44 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) 44 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
45 #define pex_lut_in32(a) in_be32(a) 45 #define pex_lut_in32(a) in_be32(a)
46 #define pex_lut_out32(a, v) out_be32(a, v) 46 #define pex_lut_out32(a, v) out_be32(a, v)
47 #endif 47 #endif
48 #ifndef __ASSEMBLY__ 48 #ifndef __ASSEMBLY__
49 struct cpu_type { 49 struct cpu_type {
50 char name[15]; 50 char name[15];
51 u32 soc_ver; 51 u32 soc_ver;
52 u32 num_cores; 52 u32 num_cores;
53 }; 53 };
54 54
55 #define CPU_TYPE_ENTRY(n, v, nc) \ 55 #define CPU_TYPE_ENTRY(n, v, nc) \
56 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 56 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
57 57
58 #ifdef CONFIG_TFABOOT 58 #ifdef CONFIG_TFABOOT
59 #define SMC_DRAM_BANK_INFO (0xC200FF12) 59 #define SMC_DRAM_BANK_INFO (0xC200FF12)
60 #define SIP_SVC_RCW 0xC200FF18 60 #define SIP_SVC_RCW 0xC200FF18
61 61
62 phys_size_t tfa_get_dram_size(void); 62 phys_size_t tfa_get_dram_size(void);
63 63
64 enum boot_src { 64 enum boot_src {
65 BOOT_SOURCE_RESERVED = 0, 65 BOOT_SOURCE_RESERVED = 0,
66 BOOT_SOURCE_IFC_NOR, 66 BOOT_SOURCE_IFC_NOR,
67 BOOT_SOURCE_IFC_NAND, 67 BOOT_SOURCE_IFC_NAND,
68 BOOT_SOURCE_QSPI_NOR, 68 BOOT_SOURCE_QSPI_NOR,
69 BOOT_SOURCE_QSPI_NAND, 69 BOOT_SOURCE_QSPI_NAND,
70 BOOT_SOURCE_XSPI_NOR, 70 BOOT_SOURCE_XSPI_NOR,
71 BOOT_SOURCE_XSPI_NAND, 71 BOOT_SOURCE_XSPI_NAND,
72 BOOT_SOURCE_SD_MMC, 72 BOOT_SOURCE_SD_MMC,
73 BOOT_SOURCE_SD_MMC2, 73 BOOT_SOURCE_SD_MMC2,
74 BOOT_SOURCE_I2C1_EXTENDED, 74 BOOT_SOURCE_I2C1_EXTENDED,
75 }; 75 };
76 76
77 enum boot_src get_boot_src(void); 77 enum boot_src get_boot_src(void);
78 #endif 78 #endif
79 #endif 79 #endif
80 #define SVR_WO_E 0xFFFFFE 80 #define SVR_WO_E 0xFFFFFE
81 81
82 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 82 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
83 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 83 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
84 #define SVR_REV(svr) (((svr) >> 0) & 0xff) 84 #define SVR_REV(svr) (((svr) >> 0) & 0xff)
85 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
86 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 85 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
87 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) 86 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
88 #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) 87 #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
88 #define SVR_WO_CE 0xFFFFEE
89 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE)
90 #else
91 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
89 #endif 92 #endif
90 #ifdef CONFIG_ARCH_LS1028A 93 #ifdef CONFIG_ARCH_LS1028A
91 #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) 94 #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1))
92 #endif 95 #endif
93 #define IS_SVR_REV(svr, maj, min) \ 96 #define IS_SVR_REV(svr, maj, min) \
94 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) 97 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
95 #define SVR_DEV(svr) ((svr) >> 8) 98 #define SVR_DEV(svr) ((svr) >> 8)
96 #define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) 99 #define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
97 100
98 #ifndef __ASSEMBLY__ 101 #ifndef __ASSEMBLY__
99 #ifdef CONFIG_FSL_LSCH3 102 #ifdef CONFIG_FSL_LSCH3
100 void fsl_lsch3_early_init_f(void); 103 void fsl_lsch3_early_init_f(void);
101 int get_core_volt_from_fuse(void); 104 int get_core_volt_from_fuse(void);
102 #elif defined(CONFIG_FSL_LSCH2) 105 #elif defined(CONFIG_FSL_LSCH2)
103 void fsl_lsch2_early_init_f(void); 106 void fsl_lsch2_early_init_f(void);
104 int setup_chip_volt(void); 107 int setup_chip_volt(void);
105 /* Setup core vdd in unit mV */ 108 /* Setup core vdd in unit mV */
106 int board_setup_core_volt(u32 vdd); 109 int board_setup_core_volt(u32 vdd);
107 #ifdef CONFIG_FSL_PFE 110 #ifdef CONFIG_FSL_PFE
108 void init_pfe_scfg_dcfg_regs(void); 111 void init_pfe_scfg_dcfg_regs(void);
109 #endif 112 #endif
110 #endif 113 #endif
111 #ifdef CONFIG_QSPI_AHB_INIT 114 #ifdef CONFIG_QSPI_AHB_INIT
112 int qspi_ahb_init(void); 115 int qspi_ahb_init(void);
113 #endif 116 #endif
114 117
115 #ifdef CONFIG_FSPI_AHB_EN_4BYTE 118 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
116 #define SYS_NXP_FSPI_LUTCR_LOCK 0x00000001 119 #define SYS_NXP_FSPI_LUTCR_LOCK 0x00000001
117 #define SYS_NXP_FSPI_LUTCR_UNLOCK 0x00000002 120 #define SYS_NXP_FSPI_LUTCR_UNLOCK 0x00000002
118 #define SYS_NXP_FSPI_LUTKEY 0x5AF05AF0 121 #define SYS_NXP_FSPI_LUTKEY 0x5AF05AF0
119 int fspi_ahb_init(void); 122 int fspi_ahb_init(void);
120 #endif 123 #endif
121 124
122 void cpu_name(char *name); 125 void cpu_name(char *name);
123 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 126 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
124 void erratum_a009635(void); 127 void erratum_a009635(void);
125 #endif 128 #endif
126 129
127 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 130 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
128 void erratum_a010315(void); 131 void erratum_a010315(void);
129 #endif 132 #endif
130 133
131 bool soc_has_dp_ddr(void); 134 bool soc_has_dp_ddr(void);
132 bool soc_has_aiop(void); 135 bool soc_has_aiop(void);
133 #endif 136 #endif
134 137
135 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ 138 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */