Eric Lee / smarc-uboot | Embedian Git Server

Commit d00ce09040d3100e2c7998ef56db62c2d20d9ee3

Authored by Wolfgang Denk 2008-04-25 18:44:08 +0800

Exists in master and in 54 other branches

USB: fix more GCC 4.2.x aliasing warnings

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Markus Klotzbuecher <mk@denx.de>

Showing 3 changed files with 6 additions and 6 deletions Inline Diff

cpu/arm920t/s3c24x0/usb_ohci.c
cpu/mpc5xxx/usb_ohci.c
cpu/ppc4xx/usb_ohci.c

cpu/arm920t/s3c24x0/usb_ohci.c

Diff comments View file @ d00ce09

1	/*	1	/*
2	* URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.	2	* URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
3	*	3	*
4	* (C) Copyright 2003	4	* (C) Copyright 2003
5	* Gary Jennejohn, DENX Software Engineering <gj@denx.de>	5	* Gary Jennejohn, DENX Software Engineering <gj@denx.de>
6	*	6	*
7	* Note: Much of this code has been derived from Linux 2.4	7	* Note: Much of this code has been derived from Linux 2.4
8	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>	8	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
9	* (C) Copyright 2000-2002 David Brownell	9	* (C) Copyright 2000-2002 David Brownell
10	*	10	*
11	* See file CREDITS for list of people who contributed to this	11	* See file CREDITS for list of people who contributed to this
12	* project.	12	* project.
13	*	13	*
14	* This program is free software; you can redistribute it and/or	14	* This program is free software; you can redistribute it and/or
15	* modify it under the terms of the GNU General Public License as	15	* modify it under the terms of the GNU General Public License as
16	* published by the Free Software Foundation; either version 2 of	16	* published by the Free Software Foundation; either version 2 of
17	* the License, or (at your option) any later version.	17	* the License, or (at your option) any later version.
18	*	18	*
19	* This program is distributed in the hope that it will be useful,	19	* This program is distributed in the hope that it will be useful,
20	* but WITHOUT ANY WARRANTY; without even the implied warranty of	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22	* GNU General Public License for more details.	22	* GNU General Public License for more details.
23	*	23	*
24	* You should have received a copy of the GNU General Public License	24	* You should have received a copy of the GNU General Public License
25	* along with this program; if not, write to the Free Software	25	* along with this program; if not, write to the Free Software
26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27	* MA 02111-1307 USA	27	* MA 02111-1307 USA
28	*	28	*
29	*/	29	*/
30	/*	30	/*
31	* IMPORTANT NOTES	31	* IMPORTANT NOTES
32	* 1 - you MUST define LITTLEENDIAN in the configuration file for the	32	* 1 - you MUST define LITTLEENDIAN in the configuration file for the
33	* board or this driver will NOT work!	33	* board or this driver will NOT work!
34	* 2 - this driver is intended for use with USB Mass Storage Devices	34	* 2 - this driver is intended for use with USB Mass Storage Devices
35	* (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!	35	* (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
36	*/	36	*/
37		37
38	#include <common.h>	38	#include <common.h>
39	/* #include <pci.h> no PCI on the S3C24X0 */	39	/* #include <pci.h> no PCI on the S3C24X0 */
40		40
41	#ifdef CONFIG_USB_OHCI	41	#ifdef CONFIG_USB_OHCI
42		42
43	#if defined(CONFIG_S3C2400)	43	#if defined(CONFIG_S3C2400)
44	#include <s3c2400.h>	44	#include <s3c2400.h>
45	#elif defined(CONFIG_S3C2410)	45	#elif defined(CONFIG_S3C2410)
46	#include <s3c2410.h>	46	#include <s3c2410.h>
47	#endif	47	#endif
48		48
49	#include <malloc.h>	49	#include <malloc.h>
50	#include <usb.h>	50	#include <usb.h>
51	#include "usb_ohci.h"	51	#include "usb_ohci.h"
52		52
53	#define OHCI_USE_NPS /* force NoPowerSwitching mode */	53	#define OHCI_USE_NPS /* force NoPowerSwitching mode */
54	#undef OHCI_VERBOSE_DEBUG /* not always helpful */	54	#undef OHCI_VERBOSE_DEBUG /* not always helpful */
55		55
56		56
57	/* For initializing controller (mask in an HCFS mode too) */	57	/* For initializing controller (mask in an HCFS mode too) */
58	#define OHCI_CONTROL_INIT \	58	#define OHCI_CONTROL_INIT \
59	(OHCI_CTRL_CBSR & 0x3) \| OHCI_CTRL_IE \| OHCI_CTRL_PLE	59	(OHCI_CTRL_CBSR & 0x3) \| OHCI_CTRL_IE \| OHCI_CTRL_PLE
60		60
61	#define readl(a) (((vu_long )(a)))	61	#define readl(a) (((volatile u32 )(a)))
62	#define writel(a, b) (((vu_long )(b)) = ((vu_long)a))	62	#define writel(a, b) (((volatile u32 )(b)) = ((volatile u32)a))
63		63
64	#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })	64	#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
65		65
66	#undef DEBUG	66	#undef DEBUG
67	#ifdef DEBUG	67	#ifdef DEBUG
68	#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)	68	#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
69	#else	69	#else
70	#define dbg(format, arg...) do {} while(0)	70	#define dbg(format, arg...) do {} while(0)
71	#endif /* DEBUG */	71	#endif /* DEBUG */
72	#define err(format, arg...) printf("ERROR: " format "\n", ## arg)	72	#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
73	#undef SHOW_INFO	73	#undef SHOW_INFO
74	#ifdef SHOW_INFO	74	#ifdef SHOW_INFO
75	#define info(format, arg...) printf("INFO: " format "\n", ## arg)	75	#define info(format, arg...) printf("INFO: " format "\n", ## arg)
76	#else	76	#else
77	#define info(format, arg...) do {} while(0)	77	#define info(format, arg...) do {} while(0)
78	#endif	78	#endif
79		79
80	#define m16_swap(x) swap_16(x)	80	#define m16_swap(x) swap_16(x)
81	#define m32_swap(x) swap_32(x)	81	#define m32_swap(x) swap_32(x)
82		82
83	/* global ohci_t */	83	/* global ohci_t */
84	static ohci_t gohci;	84	static ohci_t gohci;
85	/* this must be aligned to a 256 byte boundary */	85	/* this must be aligned to a 256 byte boundary */
86	struct ohci_hcca ghcca[1];	86	struct ohci_hcca ghcca[1];
87	/* a pointer to the aligned storage */	87	/* a pointer to the aligned storage */
88	struct ohci_hcca *phcca;	88	struct ohci_hcca *phcca;
89	/* this allocates EDs for all possible endpoints */	89	/* this allocates EDs for all possible endpoints */
90	struct ohci_device ohci_dev;	90	struct ohci_device ohci_dev;
91	/* urb_priv */	91	/* urb_priv */
92	urb_priv_t urb_priv;	92	urb_priv_t urb_priv;
93	/* RHSC flag */	93	/* RHSC flag */
94	int got_rhsc;	94	int got_rhsc;
95	/* device which was disconnected */	95	/* device which was disconnected */
96	struct usb_device *devgone;	96	struct usb_device *devgone;
97	/* flag guarding URB transation */	97	/* flag guarding URB transation */
98	int urb_finished = 0;	98	int urb_finished = 0;
99		99
100	/-------------------------------------------------------------------------/	100	/-------------------------------------------------------------------------/
101		101
102	/* AMD-756 (D2 rev) reports corrupt register contents in some cases.	102	/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
103	* The erratum (#4) description is incorrect. AMD's workaround waits	103	* The erratum (#4) description is incorrect. AMD's workaround waits
104	* till some bits (mostly reserved) are clear; ok for all revs.	104	* till some bits (mostly reserved) are clear; ok for all revs.
105	*/	105	*/
106	#define OHCI_QUIRK_AMD756 0xabcd	106	#define OHCI_QUIRK_AMD756 0xabcd
107	#define read_roothub(hc, register, mask) ({ \	107	#define read_roothub(hc, register, mask) ({ \
108	u32 temp = readl (&hc->regs->roothub.register); \	108	u32 temp = readl (&hc->regs->roothub.register); \
109	if (hc->flags & OHCI_QUIRK_AMD756) \	109	if (hc->flags & OHCI_QUIRK_AMD756) \
110	while (temp & mask) \	110	while (temp & mask) \
111	temp = readl (&hc->regs->roothub.register); \	111	temp = readl (&hc->regs->roothub.register); \
112	temp; })	112	temp; })
113		113
114	static u32 roothub_a (struct ohci *hc)	114	static u32 roothub_a (struct ohci *hc)
115	{ return read_roothub (hc, a, 0xfc0fe000); }	115	{ return read_roothub (hc, a, 0xfc0fe000); }
116	static inline u32 roothub_b (struct ohci *hc)	116	static inline u32 roothub_b (struct ohci *hc)
117	{ return readl (&hc->regs->roothub.b); }	117	{ return readl (&hc->regs->roothub.b); }
118	static inline u32 roothub_status (struct ohci *hc)	118	static inline u32 roothub_status (struct ohci *hc)
119	{ return readl (&hc->regs->roothub.status); }	119	{ return readl (&hc->regs->roothub.status); }
120	static u32 roothub_portstatus (struct ohci *hc, int i)	120	static u32 roothub_portstatus (struct ohci *hc, int i)
121	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }	121	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
122		122
123		123
124	/* forward declaration */	124	/* forward declaration */
125	static int hc_interrupt (void);	125	static int hc_interrupt (void);
126	static void	126	static void
127	td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,	127	td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
128	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);	128	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
129		129
130	/-------------------------------------------------------------------------	130	/-------------------------------------------------------------------------
131	* URB support functions	131	* URB support functions
132	-------------------------------------------------------------------------/	132	-------------------------------------------------------------------------/
133		133
134	/* free HCD-private data associated with this URB */	134	/* free HCD-private data associated with this URB */
135		135
136	static void urb_free_priv (urb_priv_t * urb)	136	static void urb_free_priv (urb_priv_t * urb)
137	{	137	{
138	int i;	138	int i;
139	int last;	139	int last;
140	struct td * td;	140	struct td * td;
141		141
142	last = urb->length - 1;	142	last = urb->length - 1;
143	if (last >= 0) {	143	if (last >= 0) {
144	for (i = 0; i <= last; i++) {	144	for (i = 0; i <= last; i++) {
145	td = urb->td[i];	145	td = urb->td[i];
146	if (td) {	146	if (td) {
147	td->usb_dev = NULL;	147	td->usb_dev = NULL;
148	urb->td[i] = NULL;	148	urb->td[i] = NULL;
149	}	149	}
150	}	150	}
151	}	151	}
152	}	152	}
153		153
154	/-------------------------------------------------------------------------/	154	/-------------------------------------------------------------------------/
155		155
156	#ifdef DEBUG	156	#ifdef DEBUG
157	static int sohci_get_current_frame_number (struct usb_device * dev);	157	static int sohci_get_current_frame_number (struct usb_device * dev);
158		158
159	/* debug\| print the main components of an URB	159	/* debug\| print the main components of an URB
160	* small: 0) header + data packets 1) just header */	160	* small: 0) header + data packets 1) just header */
161		161
162	static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,	162	static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
163	int transfer_len, struct devrequest * setup, char * str, int small)	163	int transfer_len, struct devrequest * setup, char * str, int small)
164	{	164	{
165	urb_priv_t * purb = &urb_priv;	165	urb_priv_t * purb = &urb_priv;
166		166
167	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",	167	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
168	str,	168	str,
169	sohci_get_current_frame_number (dev),	169	sohci_get_current_frame_number (dev),
170	usb_pipedevice (pipe),	170	usb_pipedevice (pipe),
171	usb_pipeendpoint (pipe),	171	usb_pipeendpoint (pipe),
172	usb_pipeout (pipe)? 'O': 'I',	172	usb_pipeout (pipe)? 'O': 'I',
173	usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):	173	usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
174	(usb_pipecontrol (pipe)? "CTRL": "BULK"),	174	(usb_pipecontrol (pipe)? "CTRL": "BULK"),
175	purb->actual_length,	175	purb->actual_length,
176	transfer_len, dev->status);	176	transfer_len, dev->status);
177	#ifdef OHCI_VERBOSE_DEBUG	177	#ifdef OHCI_VERBOSE_DEBUG
178	if (!small) {	178	if (!small) {
179	int i, len;	179	int i, len;
180		180
181	if (usb_pipecontrol (pipe)) {	181	if (usb_pipecontrol (pipe)) {
182	printf (__FILE__ ": cmd(8):");	182	printf (__FILE__ ": cmd(8):");
183	for (i = 0; i < 8 ; i++)	183	for (i = 0; i < 8 ; i++)
184	printf (" %02x", ((__u8 *) setup) [i]);	184	printf (" %02x", ((__u8 *) setup) [i]);
185	printf ("\n");	185	printf ("\n");
186	}	186	}
187	if (transfer_len > 0 && buffer) {	187	if (transfer_len > 0 && buffer) {
188	printf (__FILE__ ": data(%d/%d):",	188	printf (__FILE__ ": data(%d/%d):",
189	purb->actual_length,	189	purb->actual_length,
190	transfer_len);	190	transfer_len);
191	len = usb_pipeout (pipe)?	191	len = usb_pipeout (pipe)?
192	transfer_len: purb->actual_length;	192	transfer_len: purb->actual_length;
193	for (i = 0; i < 16 && i < len; i++)	193	for (i = 0; i < 16 && i < len; i++)
194	printf (" %02x", ((__u8 *) buffer) [i]);	194	printf (" %02x", ((__u8 *) buffer) [i]);
195	printf ("%s\n", i < len? "...": "");	195	printf ("%s\n", i < len? "...": "");
196	}	196	}
197	}	197	}
198	#endif	198	#endif
199	}	199	}
200		200
201	/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/	201	/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
202	void ep_print_int_eds (ohci_t ohci, char str) {	202	void ep_print_int_eds (ohci_t ohci, char str) {
203	int i, j;	203	int i, j;
204	__u32 * ed_p;	204	__u32 * ed_p;
205	for (i= 0; i < 32; i++) {	205	for (i= 0; i < 32; i++) {
206	j = 5;	206	j = 5;
207	ed_p = &(ohci->hcca->int_table [i]);	207	ed_p = &(ohci->hcca->int_table [i]);
208	if (*ed_p == 0)	208	if (*ed_p == 0)
209	continue;	209	continue;
210	printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);	210	printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
211	while (*ed_p != 0 && j--) {	211	while (*ed_p != 0 && j--) {
212	ed_t ed = (ed_t )m32_swap(ed_p);	212	ed_t ed = (ed_t )m32_swap(ed_p);
213	printf (" ed: %4x;", ed->hwINFO);	213	printf (" ed: %4x;", ed->hwINFO);
214	ed_p = &ed->hwNextED;	214	ed_p = &ed->hwNextED;
215	}	215	}
216	printf ("\n");	216	printf ("\n");
217	}	217	}
218	}	218	}
219		219
220	static void ohci_dump_intr_mask (char *label, __u32 mask)	220	static void ohci_dump_intr_mask (char *label, __u32 mask)
221	{	221	{
222	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",	222	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
223	label,	223	label,
224	mask,	224	mask,
225	(mask & OHCI_INTR_MIE) ? " MIE" : "",	225	(mask & OHCI_INTR_MIE) ? " MIE" : "",
226	(mask & OHCI_INTR_OC) ? " OC" : "",	226	(mask & OHCI_INTR_OC) ? " OC" : "",
227	(mask & OHCI_INTR_RHSC) ? " RHSC" : "",	227	(mask & OHCI_INTR_RHSC) ? " RHSC" : "",
228	(mask & OHCI_INTR_FNO) ? " FNO" : "",	228	(mask & OHCI_INTR_FNO) ? " FNO" : "",
229	(mask & OHCI_INTR_UE) ? " UE" : "",	229	(mask & OHCI_INTR_UE) ? " UE" : "",
230	(mask & OHCI_INTR_RD) ? " RD" : "",	230	(mask & OHCI_INTR_RD) ? " RD" : "",
231	(mask & OHCI_INTR_SF) ? " SF" : "",	231	(mask & OHCI_INTR_SF) ? " SF" : "",
232	(mask & OHCI_INTR_WDH) ? " WDH" : "",	232	(mask & OHCI_INTR_WDH) ? " WDH" : "",
233	(mask & OHCI_INTR_SO) ? " SO" : ""	233	(mask & OHCI_INTR_SO) ? " SO" : ""
234	);	234	);
235	}	235	}
236		236
237	static void maybe_print_eds (char *label, __u32 value)	237	static void maybe_print_eds (char *label, __u32 value)
238	{	238	{
239	ed_t edp = (ed_t )value;	239	ed_t edp = (ed_t )value;
240		240
241	if (value) {	241	if (value) {
242	dbg ("%s %08x", label, value);	242	dbg ("%s %08x", label, value);
243	dbg ("%08x", edp->hwINFO);	243	dbg ("%08x", edp->hwINFO);
244	dbg ("%08x", edp->hwTailP);	244	dbg ("%08x", edp->hwTailP);
245	dbg ("%08x", edp->hwHeadP);	245	dbg ("%08x", edp->hwHeadP);
246	dbg ("%08x", edp->hwNextED);	246	dbg ("%08x", edp->hwNextED);
247	}	247	}
248	}	248	}
249		249
250	static char * hcfs2string (int state)	250	static char * hcfs2string (int state)
251	{	251	{
252	switch (state) {	252	switch (state) {
253	case OHCI_USB_RESET: return "reset";	253	case OHCI_USB_RESET: return "reset";
254	case OHCI_USB_RESUME: return "resume";	254	case OHCI_USB_RESUME: return "resume";
255	case OHCI_USB_OPER: return "operational";	255	case OHCI_USB_OPER: return "operational";
256	case OHCI_USB_SUSPEND: return "suspend";	256	case OHCI_USB_SUSPEND: return "suspend";
257	}	257	}
258	return "?";	258	return "?";
259	}	259	}
260		260
261	/* dump control and status registers */	261	/* dump control and status registers */
262	static void ohci_dump_status (ohci_t *controller)	262	static void ohci_dump_status (ohci_t *controller)
263	{	263	{
264	struct ohci_regs *regs = controller->regs;	264	struct ohci_regs *regs = controller->regs;
265	__u32 temp;	265	__u32 temp;
266		266
267	temp = readl (&regs->revision) & 0xff;	267	temp = readl (&regs->revision) & 0xff;
268	if (temp != 0x10)	268	if (temp != 0x10)
269	dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));	269	dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
270		270
271	temp = readl (&regs->control);	271	temp = readl (&regs->control);
272	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,	272	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
273	(temp & OHCI_CTRL_RWE) ? " RWE" : "",	273	(temp & OHCI_CTRL_RWE) ? " RWE" : "",
274	(temp & OHCI_CTRL_RWC) ? " RWC" : "",	274	(temp & OHCI_CTRL_RWC) ? " RWC" : "",
275	(temp & OHCI_CTRL_IR) ? " IR" : "",	275	(temp & OHCI_CTRL_IR) ? " IR" : "",
276	hcfs2string (temp & OHCI_CTRL_HCFS),	276	hcfs2string (temp & OHCI_CTRL_HCFS),
277	(temp & OHCI_CTRL_BLE) ? " BLE" : "",	277	(temp & OHCI_CTRL_BLE) ? " BLE" : "",
278	(temp & OHCI_CTRL_CLE) ? " CLE" : "",	278	(temp & OHCI_CTRL_CLE) ? " CLE" : "",
279	(temp & OHCI_CTRL_IE) ? " IE" : "",	279	(temp & OHCI_CTRL_IE) ? " IE" : "",
280	(temp & OHCI_CTRL_PLE) ? " PLE" : "",	280	(temp & OHCI_CTRL_PLE) ? " PLE" : "",
281	temp & OHCI_CTRL_CBSR	281	temp & OHCI_CTRL_CBSR
282	);	282	);
283		283
284	temp = readl (&regs->cmdstatus);	284	temp = readl (&regs->cmdstatus);
285	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,	285	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
286	(temp & OHCI_SOC) >> 16,	286	(temp & OHCI_SOC) >> 16,
287	(temp & OHCI_OCR) ? " OCR" : "",	287	(temp & OHCI_OCR) ? " OCR" : "",
288	(temp & OHCI_BLF) ? " BLF" : "",	288	(temp & OHCI_BLF) ? " BLF" : "",
289	(temp & OHCI_CLF) ? " CLF" : "",	289	(temp & OHCI_CLF) ? " CLF" : "",
290	(temp & OHCI_HCR) ? " HCR" : ""	290	(temp & OHCI_HCR) ? " HCR" : ""
291	);	291	);
292		292
293	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));	293	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
294	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));	294	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
295		295
296	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));	296	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
297		297
298	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));	298	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
299	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));	299	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
300		300
301	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));	301	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
302	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));	302	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
303		303
304	maybe_print_eds ("donehead", readl (&regs->donehead));	304	maybe_print_eds ("donehead", readl (&regs->donehead));
305	}	305	}
306		306
307	static void ohci_dump_roothub (ohci_t *controller, int verbose)	307	static void ohci_dump_roothub (ohci_t *controller, int verbose)
308	{	308	{
309	__u32 temp, ndp, i;	309	__u32 temp, ndp, i;
310		310
311	temp = roothub_a (controller);	311	temp = roothub_a (controller);
312	ndp = (temp & RH_A_NDP);	312	ndp = (temp & RH_A_NDP);
313		313
314	if (verbose) {	314	if (verbose) {
315	dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,	315	dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
316	((temp & RH_A_POTPGT) >> 24) & 0xff,	316	((temp & RH_A_POTPGT) >> 24) & 0xff,
317	(temp & RH_A_NOCP) ? " NOCP" : "",	317	(temp & RH_A_NOCP) ? " NOCP" : "",
318	(temp & RH_A_OCPM) ? " OCPM" : "",	318	(temp & RH_A_OCPM) ? " OCPM" : "",
319	(temp & RH_A_DT) ? " DT" : "",	319	(temp & RH_A_DT) ? " DT" : "",
320	(temp & RH_A_NPS) ? " NPS" : "",	320	(temp & RH_A_NPS) ? " NPS" : "",
321	(temp & RH_A_PSM) ? " PSM" : "",	321	(temp & RH_A_PSM) ? " PSM" : "",
322	ndp	322	ndp
323	);	323	);
324	temp = roothub_b (controller);	324	temp = roothub_b (controller);
325	dbg ("roothub.b: %08x PPCM=%04x DR=%04x",	325	dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
326	temp,	326	temp,
327	(temp & RH_B_PPCM) >> 16,	327	(temp & RH_B_PPCM) >> 16,
328	(temp & RH_B_DR)	328	(temp & RH_B_DR)
329	);	329	);
330	temp = roothub_status (controller);	330	temp = roothub_status (controller);
331	dbg ("roothub.status: %08x%s%s%s%s%s%s",	331	dbg ("roothub.status: %08x%s%s%s%s%s%s",
332	temp,	332	temp,
333	(temp & RH_HS_CRWE) ? " CRWE" : "",	333	(temp & RH_HS_CRWE) ? " CRWE" : "",
334	(temp & RH_HS_OCIC) ? " OCIC" : "",	334	(temp & RH_HS_OCIC) ? " OCIC" : "",
335	(temp & RH_HS_LPSC) ? " LPSC" : "",	335	(temp & RH_HS_LPSC) ? " LPSC" : "",
336	(temp & RH_HS_DRWE) ? " DRWE" : "",	336	(temp & RH_HS_DRWE) ? " DRWE" : "",
337	(temp & RH_HS_OCI) ? " OCI" : "",	337	(temp & RH_HS_OCI) ? " OCI" : "",
338	(temp & RH_HS_LPS) ? " LPS" : ""	338	(temp & RH_HS_LPS) ? " LPS" : ""
339	);	339	);
340	}	340	}
341		341
342	for (i = 0; i < ndp; i++) {	342	for (i = 0; i < ndp; i++) {
343	temp = roothub_portstatus (controller, i);	343	temp = roothub_portstatus (controller, i);
344	dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",	344	dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
345	i,	345	i,
346	temp,	346	temp,
347	(temp & RH_PS_PRSC) ? " PRSC" : "",	347	(temp & RH_PS_PRSC) ? " PRSC" : "",
348	(temp & RH_PS_OCIC) ? " OCIC" : "",	348	(temp & RH_PS_OCIC) ? " OCIC" : "",
349	(temp & RH_PS_PSSC) ? " PSSC" : "",	349	(temp & RH_PS_PSSC) ? " PSSC" : "",
350	(temp & RH_PS_PESC) ? " PESC" : "",	350	(temp & RH_PS_PESC) ? " PESC" : "",
351	(temp & RH_PS_CSC) ? " CSC" : "",	351	(temp & RH_PS_CSC) ? " CSC" : "",
352		352
353	(temp & RH_PS_LSDA) ? " LSDA" : "",	353	(temp & RH_PS_LSDA) ? " LSDA" : "",
354	(temp & RH_PS_PPS) ? " PPS" : "",	354	(temp & RH_PS_PPS) ? " PPS" : "",
355	(temp & RH_PS_PRS) ? " PRS" : "",	355	(temp & RH_PS_PRS) ? " PRS" : "",
356	(temp & RH_PS_POCI) ? " POCI" : "",	356	(temp & RH_PS_POCI) ? " POCI" : "",
357	(temp & RH_PS_PSS) ? " PSS" : "",	357	(temp & RH_PS_PSS) ? " PSS" : "",
358		358
359	(temp & RH_PS_PES) ? " PES" : "",	359	(temp & RH_PS_PES) ? " PES" : "",
360	(temp & RH_PS_CCS) ? " CCS" : ""	360	(temp & RH_PS_CCS) ? " CCS" : ""
361	);	361	);
362	}	362	}
363	}	363	}
364		364
365	static void ohci_dump (ohci_t *controller, int verbose)	365	static void ohci_dump (ohci_t *controller, int verbose)
366	{	366	{
367	dbg ("OHCI controller usb-%s state", controller->slot_name);	367	dbg ("OHCI controller usb-%s state", controller->slot_name);
368		368
369	/* dumps some of the state we know about */	369	/* dumps some of the state we know about */
370	ohci_dump_status (controller);	370	ohci_dump_status (controller);
371	if (verbose)	371	if (verbose)
372	ep_print_int_eds (controller, "hcca");	372	ep_print_int_eds (controller, "hcca");
373	dbg ("hcca frame #%04x", controller->hcca->frame_no);	373	dbg ("hcca frame #%04x", controller->hcca->frame_no);
374	ohci_dump_roothub (controller, 1);	374	ohci_dump_roothub (controller, 1);
375	}	375	}
376		376
377		377
378	#endif /* DEBUG */	378	#endif /* DEBUG */
379		379
380	/-------------------------------------------------------------------------	380	/-------------------------------------------------------------------------
381	* Interface functions (URB)	381	* Interface functions (URB)
382	-------------------------------------------------------------------------/	382	-------------------------------------------------------------------------/
383		383
384	/* get a transfer request */	384	/* get a transfer request */
385		385
386	int sohci_submit_job(struct usb_device dev, unsigned long pipe, void buffer,	386	int sohci_submit_job(struct usb_device dev, unsigned long pipe, void buffer,
387	int transfer_len, struct devrequest *setup, int interval)	387	int transfer_len, struct devrequest *setup, int interval)
388	{	388	{
389	ohci_t *ohci;	389	ohci_t *ohci;
390	ed_t * ed;	390	ed_t * ed;
391	urb_priv_t *purb_priv;	391	urb_priv_t *purb_priv;
392	int i, size = 0;	392	int i, size = 0;
393		393
394	ohci = &gohci;	394	ohci = &gohci;
395		395
396	/* when controller's hung, permit only roothub cleanup attempts	396	/* when controller's hung, permit only roothub cleanup attempts
397	* such as powering down ports */	397	* such as powering down ports */
398	if (ohci->disabled) {	398	if (ohci->disabled) {
399	err("sohci_submit_job: EPIPE");	399	err("sohci_submit_job: EPIPE");
400	return -1;	400	return -1;
401	}	401	}
402		402
403	/* if we have an unfinished URB from previous transaction let's	403	/* if we have an unfinished URB from previous transaction let's
404	* fail and scream as quickly as possible so as not to corrupt	404	* fail and scream as quickly as possible so as not to corrupt
405	* further communication */	405	* further communication */
406	if (!urb_finished) {	406	if (!urb_finished) {
407	err("sohci_submit_job: URB NOT FINISHED");	407	err("sohci_submit_job: URB NOT FINISHED");
408	return -1;	408	return -1;
409	}	409	}
410	/* we're about to begin a new transaction here so mark the URB unfinished */	410	/* we're about to begin a new transaction here so mark the URB unfinished */
411	urb_finished = 0;	411	urb_finished = 0;
412		412
413	/* every endpoint has a ed, locate and fill it */	413	/* every endpoint has a ed, locate and fill it */
414	if (!(ed = ep_add_ed (dev, pipe))) {	414	if (!(ed = ep_add_ed (dev, pipe))) {
415	err("sohci_submit_job: ENOMEM");	415	err("sohci_submit_job: ENOMEM");
416	return -1;	416	return -1;
417	}	417	}
418		418
419	/* for the private part of the URB we need the number of TDs (size) */	419	/* for the private part of the URB we need the number of TDs (size) */
420	switch (usb_pipetype (pipe)) {	420	switch (usb_pipetype (pipe)) {
421	case PIPE_BULK: /* one TD for every 4096 Byte */	421	case PIPE_BULK: /* one TD for every 4096 Byte */
422	size = (transfer_len - 1) / 4096 + 1;	422	size = (transfer_len - 1) / 4096 + 1;
423	break;	423	break;
424	case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */	424	case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
425	size = (transfer_len == 0)? 2:	425	size = (transfer_len == 0)? 2:
426	(transfer_len - 1) / 4096 + 3;	426	(transfer_len - 1) / 4096 + 3;
427	break;	427	break;
428	}	428	}
429		429
430	if (size >= (N_URB_TD - 1)) {	430	if (size >= (N_URB_TD - 1)) {
431	err("need %d TDs, only have %d", size, N_URB_TD);	431	err("need %d TDs, only have %d", size, N_URB_TD);
432	return -1;	432	return -1;
433	}	433	}
434	purb_priv = &urb_priv;	434	purb_priv = &urb_priv;
435	purb_priv->pipe = pipe;	435	purb_priv->pipe = pipe;
436		436
437	/* fill the private part of the URB */	437	/* fill the private part of the URB */
438	purb_priv->length = size;	438	purb_priv->length = size;
439	purb_priv->ed = ed;	439	purb_priv->ed = ed;
440	purb_priv->actual_length = 0;	440	purb_priv->actual_length = 0;
441		441
442	/* allocate the TDs */	442	/* allocate the TDs */
443	/* note that td[0] was allocated in ep_add_ed */	443	/* note that td[0] was allocated in ep_add_ed */
444	for (i = 0; i < size; i++) {	444	for (i = 0; i < size; i++) {
445	purb_priv->td[i] = td_alloc (dev);	445	purb_priv->td[i] = td_alloc (dev);
446	if (!purb_priv->td[i]) {	446	if (!purb_priv->td[i]) {
447	purb_priv->length = i;	447	purb_priv->length = i;
448	urb_free_priv (purb_priv);	448	urb_free_priv (purb_priv);
449	err("sohci_submit_job: ENOMEM");	449	err("sohci_submit_job: ENOMEM");
450	return -1;	450	return -1;
451	}	451	}
452	}	452	}
453		453
454	if (ed->state == ED_NEW \|\| (ed->state & ED_DEL)) {	454	if (ed->state == ED_NEW \|\| (ed->state & ED_DEL)) {
455	urb_free_priv (purb_priv);	455	urb_free_priv (purb_priv);
456	err("sohci_submit_job: EINVAL");	456	err("sohci_submit_job: EINVAL");
457	return -1;	457	return -1;
458	}	458	}
459		459
460	/* link the ed into a chain if is not already */	460	/* link the ed into a chain if is not already */
461	if (ed->state != ED_OPER)	461	if (ed->state != ED_OPER)
462	ep_link (ohci, ed);	462	ep_link (ohci, ed);
463		463
464	/* fill the TDs and link it to the ed */	464	/* fill the TDs and link it to the ed */
465	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);	465	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
466		466
467	return 0;	467	return 0;
468	}	468	}
469		469
470	/-------------------------------------------------------------------------/	470	/-------------------------------------------------------------------------/
471		471
472	#ifdef DEBUG	472	#ifdef DEBUG
473	/* tell us the current USB frame number */	473	/* tell us the current USB frame number */
474		474
475	static int sohci_get_current_frame_number (struct usb_device *usb_dev)	475	static int sohci_get_current_frame_number (struct usb_device *usb_dev)
476	{	476	{
477	ohci_t *ohci = &gohci;	477	ohci_t *ohci = &gohci;
478		478
479	return m16_swap (ohci->hcca->frame_no);	479	return m16_swap (ohci->hcca->frame_no);
480	}	480	}
481	#endif	481	#endif
482		482
483	/-------------------------------------------------------------------------	483	/-------------------------------------------------------------------------
484	* ED handling functions	484	* ED handling functions
485	-------------------------------------------------------------------------/	485	-------------------------------------------------------------------------/
486		486
487	/* link an ed into one of the HC chains */	487	/* link an ed into one of the HC chains */
488		488
489	static int ep_link (ohci_t ohci, ed_t edi)	489	static int ep_link (ohci_t ohci, ed_t edi)
490	{	490	{
491	volatile ed_t *ed = edi;	491	volatile ed_t *ed = edi;
492		492
493	ed->state = ED_OPER;	493	ed->state = ED_OPER;
494		494
495	switch (ed->type) {	495	switch (ed->type) {
496	case PIPE_CONTROL:	496	case PIPE_CONTROL:
497	ed->hwNextED = 0;	497	ed->hwNextED = 0;
498	if (ohci->ed_controltail == NULL) {	498	if (ohci->ed_controltail == NULL) {
499	writel (ed, &ohci->regs->ed_controlhead);	499	writel (ed, &ohci->regs->ed_controlhead);
500	} else {	500	} else {
501	ohci->ed_controltail->hwNextED = (__u32)m32_swap (ed);	501	ohci->ed_controltail->hwNextED = (__u32)m32_swap (ed);
502	}	502	}
503	ed->ed_prev = ohci->ed_controltail;	503	ed->ed_prev = ohci->ed_controltail;
504	if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&	504	if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
505	!ohci->ed_rm_list[1] && !ohci->sleeping) {	505	!ohci->ed_rm_list[1] && !ohci->sleeping) {
506	ohci->hc_control \|= OHCI_CTRL_CLE;	506	ohci->hc_control \|= OHCI_CTRL_CLE;
507	writel (ohci->hc_control, &ohci->regs->control);	507	writel (ohci->hc_control, &ohci->regs->control);
508	}	508	}
509	ohci->ed_controltail = edi;	509	ohci->ed_controltail = edi;
510	break;	510	break;
511		511
512	case PIPE_BULK:	512	case PIPE_BULK:
513	ed->hwNextED = 0;	513	ed->hwNextED = 0;
514	if (ohci->ed_bulktail == NULL) {	514	if (ohci->ed_bulktail == NULL) {
515	writel (ed, &ohci->regs->ed_bulkhead);	515	writel (ed, &ohci->regs->ed_bulkhead);
516	} else {	516	} else {
517	ohci->ed_bulktail->hwNextED = (__u32)m32_swap (ed);	517	ohci->ed_bulktail->hwNextED = (__u32)m32_swap (ed);
518	}	518	}
519	ed->ed_prev = ohci->ed_bulktail;	519	ed->ed_prev = ohci->ed_bulktail;
520	if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&	520	if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
521	!ohci->ed_rm_list[1] && !ohci->sleeping) {	521	!ohci->ed_rm_list[1] && !ohci->sleeping) {
522	ohci->hc_control \|= OHCI_CTRL_BLE;	522	ohci->hc_control \|= OHCI_CTRL_BLE;
523	writel (ohci->hc_control, &ohci->regs->control);	523	writel (ohci->hc_control, &ohci->regs->control);
524	}	524	}
525	ohci->ed_bulktail = edi;	525	ohci->ed_bulktail = edi;
526	break;	526	break;
527	}	527	}
528	return 0;	528	return 0;
529	}	529	}
530		530
531	/-------------------------------------------------------------------------/	531	/-------------------------------------------------------------------------/
532		532
533	/* unlink an ed from one of the HC chains.	533	/* unlink an ed from one of the HC chains.
534	* just the link to the ed is unlinked.	534	* just the link to the ed is unlinked.
535	* the link from the ed still points to another operational ed or 0	535	* the link from the ed still points to another operational ed or 0
536	* so the HC can eventually finish the processing of the unlinked ed */	536	* so the HC can eventually finish the processing of the unlinked ed */
537		537
538	static int ep_unlink (ohci_t ohci, ed_t ed)	538	static int ep_unlink (ohci_t ohci, ed_t ed)
539	{	539	{
540	ed->hwINFO \|= m32_swap (OHCI_ED_SKIP);	540	ed->hwINFO \|= m32_swap (OHCI_ED_SKIP);
541		541
542	switch (ed->type) {	542	switch (ed->type) {
543	case PIPE_CONTROL:	543	case PIPE_CONTROL:
544	if (ed->ed_prev == NULL) {	544	if (ed->ed_prev == NULL) {
545	if (!ed->hwNextED) {	545	if (!ed->hwNextED) {
546	ohci->hc_control &= ~OHCI_CTRL_CLE;	546	ohci->hc_control &= ~OHCI_CTRL_CLE;
547	writel (ohci->hc_control, &ohci->regs->control);	547	writel (ohci->hc_control, &ohci->regs->control);
548	}	548	}
549	writel (m32_swap (((__u32 )&ed->hwNextED)), &ohci->regs->ed_controlhead);	549	writel (m32_swap (((__u32 )&ed->hwNextED)), &ohci->regs->ed_controlhead);
550	} else {	550	} else {
551	ed->ed_prev->hwNextED = ed->hwNextED;	551	ed->ed_prev->hwNextED = ed->hwNextED;
552	}	552	}
553	if (ohci->ed_controltail == ed) {	553	if (ohci->ed_controltail == ed) {
554	ohci->ed_controltail = ed->ed_prev;	554	ohci->ed_controltail = ed->ed_prev;
555	} else {	555	} else {
556	((ed_t )m32_swap (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;	556	((ed_t )m32_swap (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
557	}	557	}
558	break;	558	break;
559		559
560	case PIPE_BULK:	560	case PIPE_BULK:
561	if (ed->ed_prev == NULL) {	561	if (ed->ed_prev == NULL) {
562	if (!ed->hwNextED) {	562	if (!ed->hwNextED) {
563	ohci->hc_control &= ~OHCI_CTRL_BLE;	563	ohci->hc_control &= ~OHCI_CTRL_BLE;
564	writel (ohci->hc_control, &ohci->regs->control);	564	writel (ohci->hc_control, &ohci->regs->control);
565	}	565	}
566	writel (m32_swap (((__u32 )&ed->hwNextED)), &ohci->regs->ed_bulkhead);	566	writel (m32_swap (((__u32 )&ed->hwNextED)), &ohci->regs->ed_bulkhead);
567	} else {	567	} else {
568	ed->ed_prev->hwNextED = ed->hwNextED;	568	ed->ed_prev->hwNextED = ed->hwNextED;
569	}	569	}
570	if (ohci->ed_bulktail == ed) {	570	if (ohci->ed_bulktail == ed) {
571	ohci->ed_bulktail = ed->ed_prev;	571	ohci->ed_bulktail = ed->ed_prev;
572	} else {	572	} else {
573	((ed_t )m32_swap (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;	573	((ed_t )m32_swap (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
574	}	574	}
575	break;	575	break;
576	}	576	}
577	ed->state = ED_UNLINK;	577	ed->state = ED_UNLINK;
578	return 0;	578	return 0;
579	}	579	}
580		580
581		581
582	/-------------------------------------------------------------------------/	582	/-------------------------------------------------------------------------/
583		583
584	/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,	584	/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
585	* but the USB stack is a little bit stateless so we do it at every transaction	585	* but the USB stack is a little bit stateless so we do it at every transaction
586	* if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK	586	* if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
587	* in all other cases the state is left unchanged	587	* in all other cases the state is left unchanged
588	* the ed info fields are setted anyway even though most of them should not change */	588	* the ed info fields are setted anyway even though most of them should not change */
589		589
590	static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)	590	static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
591	{	591	{
592	td_t *td;	592	td_t *td;
593	ed_t *ed_ret;	593	ed_t *ed_ret;
594	volatile ed_t *ed;	594	volatile ed_t *ed;
595		595
596	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) \|	596	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) \|
597	(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];	597	(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
598		598
599	if ((ed->state & ED_DEL) \|\| (ed->state & ED_URB_DEL)) {	599	if ((ed->state & ED_DEL) \|\| (ed->state & ED_URB_DEL)) {
600	err("ep_add_ed: pending delete");	600	err("ep_add_ed: pending delete");
601	/* pending delete request */	601	/* pending delete request */
602	return NULL;	602	return NULL;
603	}	603	}
604		604
605	if (ed->state == ED_NEW) {	605	if (ed->state == ED_NEW) {
606	ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */	606	ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
607	/* dummy td; end of td list for ed */	607	/* dummy td; end of td list for ed */
608	td = td_alloc (usb_dev);	608	td = td_alloc (usb_dev);
609	ed->hwTailP = (__u32)m32_swap (td);	609	ed->hwTailP = (__u32)m32_swap (td);
610	ed->hwHeadP = ed->hwTailP;	610	ed->hwHeadP = ed->hwTailP;
611	ed->state = ED_UNLINK;	611	ed->state = ED_UNLINK;
612	ed->type = usb_pipetype (pipe);	612	ed->type = usb_pipetype (pipe);
613	ohci_dev.ed_cnt++;	613	ohci_dev.ed_cnt++;
614	}	614	}
615		615
616	ed->hwINFO = m32_swap (usb_pipedevice (pipe)	616	ed->hwINFO = m32_swap (usb_pipedevice (pipe)
617	\| usb_pipeendpoint (pipe) << 7	617	\| usb_pipeendpoint (pipe) << 7
618	\| (usb_pipeisoc (pipe)? 0x8000: 0)	618	\| (usb_pipeisoc (pipe)? 0x8000: 0)
619	\| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))	619	\| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
620	\| usb_pipeslow (pipe) << 13	620	\| usb_pipeslow (pipe) << 13
621	\| usb_maxpacket (usb_dev, pipe) << 16);	621	\| usb_maxpacket (usb_dev, pipe) << 16);
622		622
623	return ed_ret;	623	return ed_ret;
624	}	624	}
625		625
626	/-------------------------------------------------------------------------	626	/-------------------------------------------------------------------------
627	* TD handling functions	627	* TD handling functions
628	-------------------------------------------------------------------------/	628	-------------------------------------------------------------------------/
629		629
630	/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */	630	/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
631		631
632	static void td_fill (ohci_t *ohci, unsigned int info,	632	static void td_fill (ohci_t *ohci, unsigned int info,
633	void *data, int len,	633	void *data, int len,
634	struct usb_device dev, int index, urb_priv_t urb_priv)	634	struct usb_device dev, int index, urb_priv_t urb_priv)
635	{	635	{
636	volatile td_t td, td_pt;	636	volatile td_t td, td_pt;
637	#ifdef OHCI_FILL_TRACE	637	#ifdef OHCI_FILL_TRACE
638	int i;	638	int i;
639	#endif	639	#endif
640		640
641	if (index > urb_priv->length) {	641	if (index > urb_priv->length) {
642	err("index > length");	642	err("index > length");
643	return;	643	return;
644	}	644	}
645	/* use this td as the next dummy */	645	/* use this td as the next dummy */
646	td_pt = urb_priv->td [index];	646	td_pt = urb_priv->td [index];
647	td_pt->hwNextTD = 0;	647	td_pt->hwNextTD = 0;
648		648
649	/* fill the old dummy TD */	649	/* fill the old dummy TD */
650	td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);	650	td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
651		651
652	td->ed = urb_priv->ed;	652	td->ed = urb_priv->ed;
653	td->next_dl_td = NULL;	653	td->next_dl_td = NULL;
654	td->index = index;	654	td->index = index;
655	td->data = (__u32)data;	655	td->data = (__u32)data;
656	#ifdef OHCI_FILL_TRACE	656	#ifdef OHCI_FILL_TRACE
657	if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {	657	if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
658	for (i = 0; i < len; i++)	658	for (i = 0; i < len; i++)
659	printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);	659	printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
660	printf("\n");	660	printf("\n");
661	}	661	}
662	#endif	662	#endif
663	if (!len)	663	if (!len)
664	data = 0;	664	data = 0;
665		665
666	td->hwINFO = (__u32)m32_swap (info);	666	td->hwINFO = (__u32)m32_swap (info);
667	td->hwCBP = (__u32)m32_swap (data);	667	td->hwCBP = (__u32)m32_swap (data);
668	if (data)	668	if (data)
669	td->hwBE = (__u32)m32_swap (data + len - 1);	669	td->hwBE = (__u32)m32_swap (data + len - 1);
670	else	670	else
671	td->hwBE = 0;	671	td->hwBE = 0;
672	td->hwNextTD = (__u32)m32_swap (td_pt);	672	td->hwNextTD = (__u32)m32_swap (td_pt);
673		673
674	/* append to queue */	674	/* append to queue */
675	td->ed->hwTailP = td->hwNextTD;	675	td->ed->hwTailP = td->hwNextTD;
676	}	676	}
677		677
678	/-------------------------------------------------------------------------/	678	/-------------------------------------------------------------------------/
679		679
680	/* prepare all TDs of a transfer */	680	/* prepare all TDs of a transfer */
681		681
682	static void td_submit_job (struct usb_device dev, unsigned long pipe, void buffer,	682	static void td_submit_job (struct usb_device dev, unsigned long pipe, void buffer,
683	int transfer_len, struct devrequest setup, urb_priv_t urb, int interval)	683	int transfer_len, struct devrequest setup, urb_priv_t urb, int interval)
684	{	684	{
685	ohci_t *ohci = &gohci;	685	ohci_t *ohci = &gohci;
686	int data_len = transfer_len;	686	int data_len = transfer_len;
687	void *data;	687	void *data;
688	int cnt = 0;	688	int cnt = 0;
689	__u32 info = 0;	689	__u32 info = 0;
690	unsigned int toggle = 0;	690	unsigned int toggle = 0;
691		691
692	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */	692	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
693	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {	693	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
694	toggle = TD_T_TOGGLE;	694	toggle = TD_T_TOGGLE;
695	} else {	695	} else {
696	toggle = TD_T_DATA0;	696	toggle = TD_T_DATA0;
697	usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);	697	usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
698	}	698	}
699	urb->td_cnt = 0;	699	urb->td_cnt = 0;
700	if (data_len)	700	if (data_len)
701	data = buffer;	701	data = buffer;
702	else	702	else
703	data = 0;	703	data = 0;
704		704
705	switch (usb_pipetype (pipe)) {	705	switch (usb_pipetype (pipe)) {
706	case PIPE_BULK:	706	case PIPE_BULK:
707	info = usb_pipeout (pipe)?	707	info = usb_pipeout (pipe)?
708	TD_CC \| TD_DP_OUT : TD_CC \| TD_DP_IN ;	708	TD_CC \| TD_DP_OUT : TD_CC \| TD_DP_IN ;
709	while(data_len > 4096) {	709	while(data_len > 4096) {
710	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);	710	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
711	data += 4096; data_len -= 4096; cnt++;	711	data += 4096; data_len -= 4096; cnt++;
712	}	712	}
713	info = usb_pipeout (pipe)?	713	info = usb_pipeout (pipe)?
714	TD_CC \| TD_DP_OUT : TD_CC \| TD_R \| TD_DP_IN ;	714	TD_CC \| TD_DP_OUT : TD_CC \| TD_R \| TD_DP_IN ;
715	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);	715	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
716	cnt++;	716	cnt++;
717		717
718	if (!ohci->sleeping)	718	if (!ohci->sleeping)
719	writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */	719	writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
720	break;	720	break;
721		721
722	case PIPE_CONTROL:	722	case PIPE_CONTROL:
723	info = TD_CC \| TD_DP_SETUP \| TD_T_DATA0;	723	info = TD_CC \| TD_DP_SETUP \| TD_T_DATA0;
724	td_fill (ohci, info, setup, 8, dev, cnt++, urb);	724	td_fill (ohci, info, setup, 8, dev, cnt++, urb);
725	if (data_len > 0) {	725	if (data_len > 0) {
726	info = usb_pipeout (pipe)?	726	info = usb_pipeout (pipe)?
727	TD_CC \| TD_R \| TD_DP_OUT \| TD_T_DATA1 : TD_CC \| TD_R \| TD_DP_IN \| TD_T_DATA1;	727	TD_CC \| TD_R \| TD_DP_OUT \| TD_T_DATA1 : TD_CC \| TD_R \| TD_DP_IN \| TD_T_DATA1;
728	/* NOTE: mishandles transfers >8K, some >4K */	728	/* NOTE: mishandles transfers >8K, some >4K */
729	td_fill (ohci, info, data, data_len, dev, cnt++, urb);	729	td_fill (ohci, info, data, data_len, dev, cnt++, urb);
730	}	730	}
731	info = usb_pipeout (pipe)?	731	info = usb_pipeout (pipe)?
732	TD_CC \| TD_DP_IN \| TD_T_DATA1: TD_CC \| TD_DP_OUT \| TD_T_DATA1;	732	TD_CC \| TD_DP_IN \| TD_T_DATA1: TD_CC \| TD_DP_OUT \| TD_T_DATA1;
733	td_fill (ohci, info, data, 0, dev, cnt++, urb);	733	td_fill (ohci, info, data, 0, dev, cnt++, urb);
734	if (!ohci->sleeping)	734	if (!ohci->sleeping)
735	writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */	735	writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
736	break;	736	break;
737	}	737	}
738	if (urb->length != cnt)	738	if (urb->length != cnt)
739	dbg("TD LENGTH %d != CNT %d", urb->length, cnt);	739	dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
740	}	740	}
741		741
742	/-------------------------------------------------------------------------	742	/-------------------------------------------------------------------------
743	* Done List handling functions	743	* Done List handling functions
744	-------------------------------------------------------------------------/	744	-------------------------------------------------------------------------/
745		745
746		746
747	/* calculate the transfer length and update the urb */	747	/* calculate the transfer length and update the urb */
748		748
749	static void dl_transfer_length(td_t * td)	749	static void dl_transfer_length(td_t * td)
750	{	750	{
751	__u32 tdINFO, tdBE, tdCBP;	751	__u32 tdINFO, tdBE, tdCBP;
752	urb_priv_t *lurb_priv = &urb_priv;	752	urb_priv_t *lurb_priv = &urb_priv;
753		753
754	tdINFO = m32_swap (td->hwINFO);	754	tdINFO = m32_swap (td->hwINFO);
755	tdBE = m32_swap (td->hwBE);	755	tdBE = m32_swap (td->hwBE);
756	tdCBP = m32_swap (td->hwCBP);	756	tdCBP = m32_swap (td->hwCBP);
757		757
758		758
759	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&	759	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
760	((td->index == 0) \|\| (td->index == lurb_priv->length - 1)))) {	760	((td->index == 0) \|\| (td->index == lurb_priv->length - 1)))) {
761	if (tdBE != 0) {	761	if (tdBE != 0) {
762	if (td->hwCBP == 0)	762	if (td->hwCBP == 0)
763	lurb_priv->actual_length += tdBE - td->data + 1;	763	lurb_priv->actual_length += tdBE - td->data + 1;
764	else	764	else
765	lurb_priv->actual_length += tdCBP - td->data;	765	lurb_priv->actual_length += tdCBP - td->data;
766	}	766	}
767	}	767	}
768	}	768	}
769		769
770	/-------------------------------------------------------------------------/	770	/-------------------------------------------------------------------------/
771		771
772	/* replies to the request have to be on a FIFO basis so	772	/* replies to the request have to be on a FIFO basis so
773	* we reverse the reversed done-list */	773	* we reverse the reversed done-list */
774		774
775	static td_t * dl_reverse_done_list (ohci_t *ohci)	775	static td_t * dl_reverse_done_list (ohci_t *ohci)
776	{	776	{
777	__u32 td_list_hc;	777	__u32 td_list_hc;
778	td_t *td_rev = NULL;	778	td_t *td_rev = NULL;
779	td_t *td_list = NULL;	779	td_t *td_list = NULL;
780	urb_priv_t *lurb_priv = NULL;	780	urb_priv_t *lurb_priv = NULL;
781		781
782	td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;	782	td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
783	ohci->hcca->done_head = 0;	783	ohci->hcca->done_head = 0;
784		784
785	while (td_list_hc) {	785	while (td_list_hc) {
786	td_list = (td_t *)td_list_hc;	786	td_list = (td_t *)td_list_hc;
787		787
788	if (TD_CC_GET (m32_swap (td_list->hwINFO))) {	788	if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
789	lurb_priv = &urb_priv;	789	lurb_priv = &urb_priv;
790	dbg(" USB-error/status: %x : %p",	790	dbg(" USB-error/status: %x : %p",
791	TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);	791	TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
792	if (td_list->ed->hwHeadP & m32_swap (0x1)) {	792	if (td_list->ed->hwHeadP & m32_swap (0x1)) {
793	if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {	793	if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
794	td_list->ed->hwHeadP =	794	td_list->ed->hwHeadP =
795	(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) \|	795	(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) \|
796	(td_list->ed->hwHeadP & m32_swap (0x2));	796	(td_list->ed->hwHeadP & m32_swap (0x2));
797	lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;	797	lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
798	} else	798	} else
799	td_list->ed->hwHeadP &= m32_swap (0xfffffff2);	799	td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
800	}	800	}
801	}	801	}
802		802
803	td_list->next_dl_td = td_rev;	803	td_list->next_dl_td = td_rev;
804	td_rev = td_list;	804	td_rev = td_list;
805	td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;	805	td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
806	}	806	}
807		807
808	return td_list;	808	return td_list;
809	}	809	}
810		810
811	/-------------------------------------------------------------------------/	811	/-------------------------------------------------------------------------/
812		812
813	/* td done list */	813	/* td done list */
814	static int dl_done_list (ohci_t ohci, td_t td_list)	814	static int dl_done_list (ohci_t ohci, td_t td_list)
815	{	815	{
816	td_t *td_list_next = NULL;	816	td_t *td_list_next = NULL;
817	ed_t *ed;	817	ed_t *ed;
818	int cc = 0;	818	int cc = 0;
819	int stat = 0;	819	int stat = 0;
820	/* urb_t urb; /	820	/* urb_t urb; /
821	urb_priv_t *lurb_priv;	821	urb_priv_t *lurb_priv;
822	__u32 tdINFO, edHeadP, edTailP;	822	__u32 tdINFO, edHeadP, edTailP;
823		823
824	while (td_list) {	824	while (td_list) {
825	td_list_next = td_list->next_dl_td;	825	td_list_next = td_list->next_dl_td;
826		826
827	lurb_priv = &urb_priv;	827	lurb_priv = &urb_priv;
828	tdINFO = m32_swap (td_list->hwINFO);	828	tdINFO = m32_swap (td_list->hwINFO);
829		829
830	ed = td_list->ed;	830	ed = td_list->ed;
831		831
832	dl_transfer_length(td_list);	832	dl_transfer_length(td_list);
833		833
834	/* error code of transfer */	834	/* error code of transfer */
835	cc = TD_CC_GET (tdINFO);	835	cc = TD_CC_GET (tdINFO);
836	if (cc != 0) {	836	if (cc != 0) {
837	dbg("ConditionCode %#x", cc);	837	dbg("ConditionCode %#x", cc);
838	stat = cc_to_error[cc];	838	stat = cc_to_error[cc];
839	}	839	}
840		840
841	/* see if this done list makes for all TD's of current URB,	841	/* see if this done list makes for all TD's of current URB,
842	* and mark the URB finished if so */	842	* and mark the URB finished if so */
843	if (++(lurb_priv->td_cnt) == lurb_priv->length) {	843	if (++(lurb_priv->td_cnt) == lurb_priv->length) {
844	if ((ed->state & (ED_OPER \| ED_UNLINK)))	844	if ((ed->state & (ED_OPER \| ED_UNLINK)))
845	urb_finished = 1;	845	urb_finished = 1;
846	else	846	else
847	dbg("dl_done_list: strange.., ED state %x, ed->state\n");	847	dbg("dl_done_list: strange.., ED state %x, ed->state\n");
848	} else	848	} else
849	dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,	849	dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
850	lurb_priv->length);	850	lurb_priv->length);
851		851
852	if (ed->state != ED_NEW) {	852	if (ed->state != ED_NEW) {
853	edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;	853	edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
854	edTailP = m32_swap (ed->hwTailP);	854	edTailP = m32_swap (ed->hwTailP);
855		855
856	/* unlink eds if they are not busy */	856	/* unlink eds if they are not busy */
857	if ((edHeadP == edTailP) && (ed->state == ED_OPER))	857	if ((edHeadP == edTailP) && (ed->state == ED_OPER))
858	ep_unlink (ohci, ed);	858	ep_unlink (ohci, ed);
859	}	859	}
860		860
861	td_list = td_list_next;	861	td_list = td_list_next;
862	}	862	}
863	return stat;	863	return stat;
864	}	864	}
865		865
866	/-------------------------------------------------------------------------	866	/-------------------------------------------------------------------------
867	* Virtual Root Hub	867	* Virtual Root Hub
868	-------------------------------------------------------------------------/	868	-------------------------------------------------------------------------/
869		869
870	/* Device descriptor */	870	/* Device descriptor */
871	static __u8 root_hub_dev_des[] =	871	static __u8 root_hub_dev_des[] =
872	{	872	{
873	0x12, /* __u8 bLength; */	873	0x12, /* __u8 bLength; */
874	0x01, /* __u8 bDescriptorType; Device */	874	0x01, /* __u8 bDescriptorType; Device */
875	0x10, /* __u16 bcdUSB; v1.1 */	875	0x10, /* __u16 bcdUSB; v1.1 */
876	0x01,	876	0x01,
877	0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */	877	0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
878	0x00, /* __u8 bDeviceSubClass; */	878	0x00, /* __u8 bDeviceSubClass; */
879	0x00, /* __u8 bDeviceProtocol; */	879	0x00, /* __u8 bDeviceProtocol; */
880	0x08, /* __u8 bMaxPacketSize0; 8 Bytes */	880	0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
881	0x00, /* __u16 idVendor; */	881	0x00, /* __u16 idVendor; */
882	0x00,	882	0x00,
883	0x00, /* __u16 idProduct; */	883	0x00, /* __u16 idProduct; */
884	0x00,	884	0x00,
885	0x00, /* __u16 bcdDevice; */	885	0x00, /* __u16 bcdDevice; */
886	0x00,	886	0x00,
887	0x00, /* __u8 iManufacturer; */	887	0x00, /* __u8 iManufacturer; */
888	0x01, /* __u8 iProduct; */	888	0x01, /* __u8 iProduct; */
889	0x00, /* __u8 iSerialNumber; */	889	0x00, /* __u8 iSerialNumber; */
890	0x01 /* __u8 bNumConfigurations; */	890	0x01 /* __u8 bNumConfigurations; */
891	};	891	};
892		892
893		893
894	/* Configuration descriptor */	894	/* Configuration descriptor */
895	static __u8 root_hub_config_des[] =	895	static __u8 root_hub_config_des[] =
896	{	896	{
897	0x09, /* __u8 bLength; */	897	0x09, /* __u8 bLength; */
898	0x02, /* __u8 bDescriptorType; Configuration */	898	0x02, /* __u8 bDescriptorType; Configuration */
899	0x19, /* __u16 wTotalLength; */	899	0x19, /* __u16 wTotalLength; */
900	0x00,	900	0x00,
901	0x01, /* __u8 bNumInterfaces; */	901	0x01, /* __u8 bNumInterfaces; */
902	0x01, /* __u8 bConfigurationValue; */	902	0x01, /* __u8 bConfigurationValue; */
903	0x00, /* __u8 iConfiguration; */	903	0x00, /* __u8 iConfiguration; */
904	0x40, /* __u8 bmAttributes;	904	0x40, /* __u8 bmAttributes;
905	Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */	905	Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
906	0x00, /* __u8 MaxPower; */	906	0x00, /* __u8 MaxPower; */
907		907
908	/* interface */	908	/* interface */
909	0x09, /* __u8 if_bLength; */	909	0x09, /* __u8 if_bLength; */
910	0x04, /* __u8 if_bDescriptorType; Interface */	910	0x04, /* __u8 if_bDescriptorType; Interface */
911	0x00, /* __u8 if_bInterfaceNumber; */	911	0x00, /* __u8 if_bInterfaceNumber; */
912	0x00, /* __u8 if_bAlternateSetting; */	912	0x00, /* __u8 if_bAlternateSetting; */
913	0x01, /* __u8 if_bNumEndpoints; */	913	0x01, /* __u8 if_bNumEndpoints; */
914	0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */	914	0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
915	0x00, /* __u8 if_bInterfaceSubClass; */	915	0x00, /* __u8 if_bInterfaceSubClass; */
916	0x00, /* __u8 if_bInterfaceProtocol; */	916	0x00, /* __u8 if_bInterfaceProtocol; */
917	0x00, /* __u8 if_iInterface; */	917	0x00, /* __u8 if_iInterface; */
918		918
919	/* endpoint */	919	/* endpoint */
920	0x07, /* __u8 ep_bLength; */	920	0x07, /* __u8 ep_bLength; */
921	0x05, /* __u8 ep_bDescriptorType; Endpoint */	921	0x05, /* __u8 ep_bDescriptorType; Endpoint */
922	0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */	922	0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
923	0x03, /* __u8 ep_bmAttributes; Interrupt */	923	0x03, /* __u8 ep_bmAttributes; Interrupt */
924	0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */	924	0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
925	0x00,	925	0x00,
926	0xff /* __u8 ep_bInterval; 255 ms */	926	0xff /* __u8 ep_bInterval; 255 ms */
927	};	927	};
928		928
929	static unsigned char root_hub_str_index0[] =	929	static unsigned char root_hub_str_index0[] =
930	{	930	{
931	0x04, /* __u8 bLength; */	931	0x04, /* __u8 bLength; */
932	0x03, /* __u8 bDescriptorType; String-descriptor */	932	0x03, /* __u8 bDescriptorType; String-descriptor */
933	0x09, /* __u8 lang ID */	933	0x09, /* __u8 lang ID */
934	0x04, /* __u8 lang ID */	934	0x04, /* __u8 lang ID */
935	};	935	};
936		936
937	static unsigned char root_hub_str_index1[] =	937	static unsigned char root_hub_str_index1[] =
938	{	938	{
939	28, /* __u8 bLength; */	939	28, /* __u8 bLength; */
940	0x03, /* __u8 bDescriptorType; String-descriptor */	940	0x03, /* __u8 bDescriptorType; String-descriptor */
941	'O', /* __u8 Unicode */	941	'O', /* __u8 Unicode */
942	0, /* __u8 Unicode */	942	0, /* __u8 Unicode */
943	'H', /* __u8 Unicode */	943	'H', /* __u8 Unicode */
944	0, /* __u8 Unicode */	944	0, /* __u8 Unicode */
945	'C', /* __u8 Unicode */	945	'C', /* __u8 Unicode */
946	0, /* __u8 Unicode */	946	0, /* __u8 Unicode */
947	'I', /* __u8 Unicode */	947	'I', /* __u8 Unicode */
948	0, /* __u8 Unicode */	948	0, /* __u8 Unicode */
949	' ', /* __u8 Unicode */	949	' ', /* __u8 Unicode */
950	0, /* __u8 Unicode */	950	0, /* __u8 Unicode */
951	'R', /* __u8 Unicode */	951	'R', /* __u8 Unicode */
952	0, /* __u8 Unicode */	952	0, /* __u8 Unicode */
953	'o', /* __u8 Unicode */	953	'o', /* __u8 Unicode */
954	0, /* __u8 Unicode */	954	0, /* __u8 Unicode */
955	'o', /* __u8 Unicode */	955	'o', /* __u8 Unicode */
956	0, /* __u8 Unicode */	956	0, /* __u8 Unicode */
957	't', /* __u8 Unicode */	957	't', /* __u8 Unicode */
958	0, /* __u8 Unicode */	958	0, /* __u8 Unicode */
959	' ', /* __u8 Unicode */	959	' ', /* __u8 Unicode */
960	0, /* __u8 Unicode */	960	0, /* __u8 Unicode */
961	'H', /* __u8 Unicode */	961	'H', /* __u8 Unicode */
962	0, /* __u8 Unicode */	962	0, /* __u8 Unicode */
963	'u', /* __u8 Unicode */	963	'u', /* __u8 Unicode */
964	0, /* __u8 Unicode */	964	0, /* __u8 Unicode */
965	'b', /* __u8 Unicode */	965	'b', /* __u8 Unicode */
966	0, /* __u8 Unicode */	966	0, /* __u8 Unicode */
967	};	967	};
968		968
969	/* Hub class-specific descriptor is constructed dynamically */	969	/* Hub class-specific descriptor is constructed dynamically */
970		970
971		971
972	/-------------------------------------------------------------------------/	972	/-------------------------------------------------------------------------/
973		973
974	#define OK(x) len = (x); break	974	#define OK(x) len = (x); break
975	#ifdef DEBUG	975	#ifdef DEBUG
976	#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}	976	#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
977	#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}	977	#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
978	#else	978	#else
979	#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)	979	#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
980	#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])	980	#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
981	#endif	981	#endif
982	#define RD_RH_STAT roothub_status(&gohci)	982	#define RD_RH_STAT roothub_status(&gohci)
983	#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)	983	#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
984		984
985	/* request to virtual root hub */	985	/* request to virtual root hub */
986		986
987	int rh_check_port_status(ohci_t *controller)	987	int rh_check_port_status(ohci_t *controller)
988	{	988	{
989	__u32 temp, ndp, i;	989	__u32 temp, ndp, i;
990	int res;	990	int res;
991		991
992	res = -1;	992	res = -1;
993	temp = roothub_a (controller);	993	temp = roothub_a (controller);
994	ndp = (temp & RH_A_NDP);	994	ndp = (temp & RH_A_NDP);
995	for (i = 0; i < ndp; i++) {	995	for (i = 0; i < ndp; i++) {
996	temp = roothub_portstatus (controller, i);	996	temp = roothub_portstatus (controller, i);
997	/* check for a device disconnect */	997	/* check for a device disconnect */
998	if (((temp & (RH_PS_PESC \| RH_PS_CSC)) ==	998	if (((temp & (RH_PS_PESC \| RH_PS_CSC)) ==
999	(RH_PS_PESC \| RH_PS_CSC)) &&	999	(RH_PS_PESC \| RH_PS_CSC)) &&
1000	((temp & RH_PS_CCS) == 0)) {	1000	((temp & RH_PS_CCS) == 0)) {
1001	res = i;	1001	res = i;
1002	break;	1002	break;
1003	}	1003	}
1004	}	1004	}
1005	return res;	1005	return res;
1006	}	1006	}
1007		1007
1008	static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,	1008	static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1009	void buffer, int transfer_len, struct devrequest cmd)	1009	void buffer, int transfer_len, struct devrequest cmd)
1010	{	1010	{
1011	void * data = buffer;	1011	void * data = buffer;
1012	int leni = transfer_len;	1012	int leni = transfer_len;
1013	int len = 0;	1013	int len = 0;
1014	int stat = 0;	1014	int stat = 0;
1015	__u32 datab[4];	1015	__u32 datab[4];
1016	__u8 data_buf = (__u8 )datab;	1016	__u8 data_buf = (__u8 )datab;
1017	__u16 bmRType_bReq;	1017	__u16 bmRType_bReq;
1018	__u16 wValue;	1018	__u16 wValue;
1019	__u16 wIndex;	1019	__u16 wIndex;
1020	__u16 wLength;	1020	__u16 wLength;
1021		1021
1022	#ifdef DEBUG	1022	#ifdef DEBUG
1023	urb_priv.actual_length = 0;	1023	urb_priv.actual_length = 0;
1024	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));	1024	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1025	#else	1025	#else
1026	wait_ms(1);	1026	wait_ms(1);
1027	#endif	1027	#endif
1028	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {	1028	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1029	info("Root-Hub submit IRQ: NOT implemented");	1029	info("Root-Hub submit IRQ: NOT implemented");
1030	return 0;	1030	return 0;
1031	}	1031	}
1032		1032
1033	bmRType_bReq = cmd->requesttype \| (cmd->request << 8);	1033	bmRType_bReq = cmd->requesttype \| (cmd->request << 8);
1034	wValue = m16_swap (cmd->value);	1034	wValue = m16_swap (cmd->value);
1035	wIndex = m16_swap (cmd->index);	1035	wIndex = m16_swap (cmd->index);
1036	wLength = m16_swap (cmd->length);	1036	wLength = m16_swap (cmd->length);
1037		1037
1038	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",	1038	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1039	dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);	1039	dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1040		1040
1041	switch (bmRType_bReq) {	1041	switch (bmRType_bReq) {
1042	/* Request Destination:	1042	/* Request Destination:
1043	without flags: Device,	1043	without flags: Device,
1044	RH_INTERFACE: interface,	1044	RH_INTERFACE: interface,
1045	RH_ENDPOINT: endpoint,	1045	RH_ENDPOINT: endpoint,
1046	RH_CLASS means HUB here,	1046	RH_CLASS means HUB here,
1047	RH_OTHER \| RH_CLASS almost ever means HUB_PORT here	1047	RH_OTHER \| RH_CLASS almost ever means HUB_PORT here
1048	*/	1048	*/
1049		1049
1050	case RH_GET_STATUS:	1050	case RH_GET_STATUS:
1051	(__u16 ) data_buf = m16_swap (1); OK (2);	1051	(__u16 ) data_buf = m16_swap (1); OK (2);
1052	case RH_GET_STATUS \| RH_INTERFACE:	1052	case RH_GET_STATUS \| RH_INTERFACE:
1053	(__u16 ) data_buf = m16_swap (0); OK (2);	1053	(__u16 ) data_buf = m16_swap (0); OK (2);
1054	case RH_GET_STATUS \| RH_ENDPOINT:	1054	case RH_GET_STATUS \| RH_ENDPOINT:
1055	(__u16 ) data_buf = m16_swap (0); OK (2);	1055	(__u16 ) data_buf = m16_swap (0); OK (2);
1056	case RH_GET_STATUS \| RH_CLASS:	1056	case RH_GET_STATUS \| RH_CLASS:
1057	(__u32 ) data_buf = m32_swap (	1057	(__u32 ) data_buf = m32_swap (
1058	RD_RH_STAT & ~(RH_HS_CRWE \| RH_HS_DRWE));	1058	RD_RH_STAT & ~(RH_HS_CRWE \| RH_HS_DRWE));
1059	OK (4);	1059	OK (4);
1060	case RH_GET_STATUS \| RH_OTHER \| RH_CLASS:	1060	case RH_GET_STATUS \| RH_OTHER \| RH_CLASS:
1061	(__u32 ) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);	1061	(__u32 ) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
1062		1062
1063	case RH_CLEAR_FEATURE \| RH_ENDPOINT:	1063	case RH_CLEAR_FEATURE \| RH_ENDPOINT:
1064	switch (wValue) {	1064	switch (wValue) {
1065	case (RH_ENDPOINT_STALL): OK (0);	1065	case (RH_ENDPOINT_STALL): OK (0);
1066	}	1066	}
1067	break;	1067	break;
1068		1068
1069	case RH_CLEAR_FEATURE \| RH_CLASS:	1069	case RH_CLEAR_FEATURE \| RH_CLASS:
1070	switch (wValue) {	1070	switch (wValue) {
1071	case RH_C_HUB_LOCAL_POWER:	1071	case RH_C_HUB_LOCAL_POWER:
1072	OK(0);	1072	OK(0);
1073	case (RH_C_HUB_OVER_CURRENT):	1073	case (RH_C_HUB_OVER_CURRENT):
1074	WR_RH_STAT(RH_HS_OCIC); OK (0);	1074	WR_RH_STAT(RH_HS_OCIC); OK (0);
1075	}	1075	}
1076	break;	1076	break;
1077		1077
1078	case RH_CLEAR_FEATURE \| RH_OTHER \| RH_CLASS:	1078	case RH_CLEAR_FEATURE \| RH_OTHER \| RH_CLASS:
1079	switch (wValue) {	1079	switch (wValue) {
1080	case (RH_PORT_ENABLE):	1080	case (RH_PORT_ENABLE):
1081	WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);	1081	WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1082	case (RH_PORT_SUSPEND):	1082	case (RH_PORT_SUSPEND):
1083	WR_RH_PORTSTAT (RH_PS_POCI); OK (0);	1083	WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1084	case (RH_PORT_POWER):	1084	case (RH_PORT_POWER):
1085	WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);	1085	WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1086	case (RH_C_PORT_CONNECTION):	1086	case (RH_C_PORT_CONNECTION):
1087	WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);	1087	WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1088	case (RH_C_PORT_ENABLE):	1088	case (RH_C_PORT_ENABLE):
1089	WR_RH_PORTSTAT (RH_PS_PESC); OK (0);	1089	WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1090	case (RH_C_PORT_SUSPEND):	1090	case (RH_C_PORT_SUSPEND):
1091	WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);	1091	WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1092	case (RH_C_PORT_OVER_CURRENT):	1092	case (RH_C_PORT_OVER_CURRENT):
1093	WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);	1093	WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1094	case (RH_C_PORT_RESET):	1094	case (RH_C_PORT_RESET):
1095	WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);	1095	WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1096	}	1096	}
1097	break;	1097	break;
1098		1098
1099	case RH_SET_FEATURE \| RH_OTHER \| RH_CLASS:	1099	case RH_SET_FEATURE \| RH_OTHER \| RH_CLASS:
1100	switch (wValue) {	1100	switch (wValue) {
1101	case (RH_PORT_SUSPEND):	1101	case (RH_PORT_SUSPEND):
1102	WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);	1102	WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1103	case (RH_PORT_RESET): /* BUG IN HUP CODE *********/	1103	case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1104	if (RD_RH_PORTSTAT & RH_PS_CCS)	1104	if (RD_RH_PORTSTAT & RH_PS_CCS)
1105	WR_RH_PORTSTAT (RH_PS_PRS);	1105	WR_RH_PORTSTAT (RH_PS_PRS);
1106	OK (0);	1106	OK (0);
1107	case (RH_PORT_POWER):	1107	case (RH_PORT_POWER):
1108	WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);	1108	WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
1109	case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/	1109	case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1110	if (RD_RH_PORTSTAT & RH_PS_CCS)	1110	if (RD_RH_PORTSTAT & RH_PS_CCS)
1111	WR_RH_PORTSTAT (RH_PS_PES );	1111	WR_RH_PORTSTAT (RH_PS_PES );
1112	OK (0);	1112	OK (0);
1113	}	1113	}
1114	break;	1114	break;
1115		1115
1116	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);	1116	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1117		1117
1118	case RH_GET_DESCRIPTOR:	1118	case RH_GET_DESCRIPTOR:
1119	switch ((wValue & 0xff00) >> 8) {	1119	switch ((wValue & 0xff00) >> 8) {
1120	case (0x01): /* device descriptor */	1120	case (0x01): /* device descriptor */
1121	len = min_t(unsigned int,	1121	len = min_t(unsigned int,
1122	leni,	1122	leni,
1123	min_t(unsigned int,	1123	min_t(unsigned int,
1124	sizeof (root_hub_dev_des),	1124	sizeof (root_hub_dev_des),
1125	wLength));	1125	wLength));
1126	data_buf = root_hub_dev_des; OK(len);	1126	data_buf = root_hub_dev_des; OK(len);
1127	case (0x02): /* configuration descriptor */	1127	case (0x02): /* configuration descriptor */
1128	len = min_t(unsigned int,	1128	len = min_t(unsigned int,
1129	leni,	1129	leni,
1130	min_t(unsigned int,	1130	min_t(unsigned int,
1131	sizeof (root_hub_config_des),	1131	sizeof (root_hub_config_des),
1132	wLength));	1132	wLength));
1133	data_buf = root_hub_config_des; OK(len);	1133	data_buf = root_hub_config_des; OK(len);
1134	case (0x03): /* string descriptors */	1134	case (0x03): /* string descriptors */
1135	if(wValue==0x0300) {	1135	if(wValue==0x0300) {
1136	len = min_t(unsigned int,	1136	len = min_t(unsigned int,
1137	leni,	1137	leni,
1138	min_t(unsigned int,	1138	min_t(unsigned int,
1139	sizeof (root_hub_str_index0),	1139	sizeof (root_hub_str_index0),
1140	wLength));	1140	wLength));
1141	data_buf = root_hub_str_index0;	1141	data_buf = root_hub_str_index0;
1142	OK(len);	1142	OK(len);
1143	}	1143	}
1144	if(wValue==0x0301) {	1144	if(wValue==0x0301) {
1145	len = min_t(unsigned int,	1145	len = min_t(unsigned int,
1146	leni,	1146	leni,
1147	min_t(unsigned int,	1147	min_t(unsigned int,
1148	sizeof (root_hub_str_index1),	1148	sizeof (root_hub_str_index1),
1149	wLength));	1149	wLength));
1150	data_buf = root_hub_str_index1;	1150	data_buf = root_hub_str_index1;
1151	OK(len);	1151	OK(len);
1152	}	1152	}
1153	default:	1153	default:
1154	stat = USB_ST_STALLED;	1154	stat = USB_ST_STALLED;
1155	}	1155	}
1156	break;	1156	break;
1157		1157
1158	case RH_GET_DESCRIPTOR \| RH_CLASS:	1158	case RH_GET_DESCRIPTOR \| RH_CLASS:
1159	{	1159	{
1160	__u32 temp = roothub_a (&gohci);	1160	__u32 temp = roothub_a (&gohci);
1161		1161
1162	data_buf [0] = 9; /* min length; */	1162	data_buf [0] = 9; /* min length; */
1163	data_buf [1] = 0x29;	1163	data_buf [1] = 0x29;
1164	data_buf [2] = temp & RH_A_NDP;	1164	data_buf [2] = temp & RH_A_NDP;
1165	data_buf [3] = 0;	1165	data_buf [3] = 0;
1166	if (temp & RH_A_PSM) /* per-port power switching? */	1166	if (temp & RH_A_PSM) /* per-port power switching? */
1167	data_buf [3] \|= 0x1;	1167	data_buf [3] \|= 0x1;
1168	if (temp & RH_A_NOCP) /* no overcurrent reporting? */	1168	if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1169	data_buf [3] \|= 0x10;	1169	data_buf [3] \|= 0x10;
1170	else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */	1170	else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1171	data_buf [3] \|= 0x8;	1171	data_buf [3] \|= 0x8;
1172		1172
1173	/* corresponds to data_buf[4-7] */	1173	/* corresponds to data_buf[4-7] */
1174	datab [1] = 0;	1174	datab [1] = 0;
1175	data_buf [5] = (temp & RH_A_POTPGT) >> 24;	1175	data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1176	temp = roothub_b (&gohci);	1176	temp = roothub_b (&gohci);
1177	data_buf [7] = temp & RH_B_DR;	1177	data_buf [7] = temp & RH_B_DR;
1178	if (data_buf [2] < 7) {	1178	if (data_buf [2] < 7) {
1179	data_buf [8] = 0xff;	1179	data_buf [8] = 0xff;
1180	} else {	1180	} else {
1181	data_buf [0] += 2;	1181	data_buf [0] += 2;
1182	data_buf [8] = (temp & RH_B_DR) >> 8;	1182	data_buf [8] = (temp & RH_B_DR) >> 8;
1183	data_buf [10] = data_buf [9] = 0xff;	1183	data_buf [10] = data_buf [9] = 0xff;
1184	}	1184	}
1185		1185
1186	len = min_t(unsigned int, leni,	1186	len = min_t(unsigned int, leni,
1187	min_t(unsigned int, data_buf [0], wLength));	1187	min_t(unsigned int, data_buf [0], wLength));
1188	OK (len);	1188	OK (len);
1189	}	1189	}
1190		1190
1191	case RH_GET_CONFIGURATION: (__u8 ) data_buf = 0x01; OK (1);	1191	case RH_GET_CONFIGURATION: (__u8 ) data_buf = 0x01; OK (1);
1192		1192
1193	case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);	1193	case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1194		1194
1195	default:	1195	default:
1196	dbg ("unsupported root hub command");	1196	dbg ("unsupported root hub command");
1197	stat = USB_ST_STALLED;	1197	stat = USB_ST_STALLED;
1198	}	1198	}
1199		1199
1200	#ifdef DEBUG	1200	#ifdef DEBUG
1201	ohci_dump_roothub (&gohci, 1);	1201	ohci_dump_roothub (&gohci, 1);
1202	#else	1202	#else
1203	wait_ms(1);	1203	wait_ms(1);
1204	#endif	1204	#endif
1205		1205
1206	len = min_t(int, len, leni);	1206	len = min_t(int, len, leni);
1207	if (data != data_buf)	1207	if (data != data_buf)
1208	memcpy (data, data_buf, len);	1208	memcpy (data, data_buf, len);
1209	dev->act_len = len;	1209	dev->act_len = len;
1210	dev->status = stat;	1210	dev->status = stat;
1211		1211
1212	#ifdef DEBUG	1212	#ifdef DEBUG
1213	if (transfer_len)	1213	if (transfer_len)
1214	urb_priv.actual_length = transfer_len;	1214	urb_priv.actual_length = transfer_len;
1215	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/usb_pipein(pipe)/);	1215	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/usb_pipein(pipe)/);
1216	#else	1216	#else
1217	wait_ms(1);	1217	wait_ms(1);
1218	#endif	1218	#endif
1219		1219
1220	return stat;	1220	return stat;
1221	}	1221	}
1222		1222
1223	/-------------------------------------------------------------------------/	1223	/-------------------------------------------------------------------------/
1224		1224
1225	/* common code for handling submit messages - used for all but root hub */	1225	/* common code for handling submit messages - used for all but root hub */
1226	/* accesses. */	1226	/* accesses. */
1227	int submit_common_msg(struct usb_device dev, unsigned long pipe, void buffer,	1227	int submit_common_msg(struct usb_device dev, unsigned long pipe, void buffer,
1228	int transfer_len, struct devrequest *setup, int interval)	1228	int transfer_len, struct devrequest *setup, int interval)
1229	{	1229	{
1230	int stat = 0;	1230	int stat = 0;
1231	int maxsize = usb_maxpacket(dev, pipe);	1231	int maxsize = usb_maxpacket(dev, pipe);
1232	int timeout;	1232	int timeout;
1233		1233
1234	/* device pulled? Shortcut the action. */	1234	/* device pulled? Shortcut the action. */
1235	if (devgone == dev) {	1235	if (devgone == dev) {
1236	dev->status = USB_ST_CRC_ERR;	1236	dev->status = USB_ST_CRC_ERR;
1237	return 0;	1237	return 0;
1238	}	1238	}
1239		1239
1240	#ifdef DEBUG	1240	#ifdef DEBUG
1241	urb_priv.actual_length = 0;	1241	urb_priv.actual_length = 0;
1242	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));	1242	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1243	#else	1243	#else
1244	wait_ms(1);	1244	wait_ms(1);
1245	#endif	1245	#endif
1246	if (!maxsize) {	1246	if (!maxsize) {
1247	err("submit_common_message: pipesize for pipe %lx is zero",	1247	err("submit_common_message: pipesize for pipe %lx is zero",
1248	pipe);	1248	pipe);
1249	return -1;	1249	return -1;
1250	}	1250	}
1251		1251
1252	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {	1252	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1253	err("sohci_submit_job failed");	1253	err("sohci_submit_job failed");
1254	return -1;	1254	return -1;
1255	}	1255	}
1256		1256
1257	wait_ms(10);	1257	wait_ms(10);
1258	/* ohci_dump_status(&gohci); */	1258	/* ohci_dump_status(&gohci); */
1259		1259
1260	/* allow more time for a BULK device to react - some are slow */	1260	/* allow more time for a BULK device to react - some are slow */
1261	#define BULK_TO 5000 /* timeout in milliseconds */	1261	#define BULK_TO 5000 /* timeout in milliseconds */
1262	if (usb_pipetype (pipe) == PIPE_BULK)	1262	if (usb_pipetype (pipe) == PIPE_BULK)
1263	timeout = BULK_TO;	1263	timeout = BULK_TO;
1264	else	1264	else
1265	timeout = 100;	1265	timeout = 100;
1266		1266
1267	/* wait for it to complete */	1267	/* wait for it to complete */
1268	for (;;) {	1268	for (;;) {
1269	/* check whether the controller is done */	1269	/* check whether the controller is done */
1270	stat = hc_interrupt();	1270	stat = hc_interrupt();
1271		1271
1272	if (stat < 0) {	1272	if (stat < 0) {
1273	stat = USB_ST_CRC_ERR;	1273	stat = USB_ST_CRC_ERR;
1274	break;	1274	break;
1275	}	1275	}
1276		1276
1277	/* NOTE: since we are not interrupt driven in U-Boot and always	1277	/* NOTE: since we are not interrupt driven in U-Boot and always
1278	* handle only one URB at a time, we cannot assume the	1278	* handle only one URB at a time, we cannot assume the
1279	* transaction finished on the first successful return from	1279	* transaction finished on the first successful return from
1280	* hc_interrupt().. unless the flag for current URB is set,	1280	* hc_interrupt().. unless the flag for current URB is set,
1281	* meaning that all TD's to/from device got actually	1281	* meaning that all TD's to/from device got actually
1282	* transferred and processed. If the current URB is not	1282	* transferred and processed. If the current URB is not
1283	* finished we need to re-iterate this loop so as	1283	* finished we need to re-iterate this loop so as
1284	* hc_interrupt() gets called again as there needs to be some	1284	* hc_interrupt() gets called again as there needs to be some
1285	* more TD's to process still */	1285	* more TD's to process still */
1286	if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {	1286	if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
1287	/* 0xff is returned for an SF-interrupt */	1287	/* 0xff is returned for an SF-interrupt */
1288	break;	1288	break;
1289	}	1289	}
1290		1290
1291	if (--timeout) {	1291	if (--timeout) {
1292	wait_ms(1);	1292	wait_ms(1);
1293	if (!urb_finished)	1293	if (!urb_finished)
1294	dbg("\%");	1294	dbg("\%");
1295		1295
1296	} else {	1296	} else {
1297	err("CTL:TIMEOUT ");	1297	err("CTL:TIMEOUT ");
1298	dbg("submit_common_msg: TO status %x\n", stat);	1298	dbg("submit_common_msg: TO status %x\n", stat);
1299	stat = USB_ST_CRC_ERR;	1299	stat = USB_ST_CRC_ERR;
1300	urb_finished = 1;	1300	urb_finished = 1;
1301	break;	1301	break;
1302	}	1302	}
1303	}	1303	}
1304		1304
1305	#if 0	1305	#if 0
1306	/* we got an Root Hub Status Change interrupt */	1306	/* we got an Root Hub Status Change interrupt */
1307	if (got_rhsc) {	1307	if (got_rhsc) {
1308	#ifdef DEBUG	1308	#ifdef DEBUG
1309	ohci_dump_roothub (&gohci, 1);	1309	ohci_dump_roothub (&gohci, 1);
1310	#endif	1310	#endif
1311	got_rhsc = 0;	1311	got_rhsc = 0;
1312	/* abuse timeout */	1312	/* abuse timeout */
1313	timeout = rh_check_port_status(&gohci);	1313	timeout = rh_check_port_status(&gohci);
1314	if (timeout >= 0) {	1314	if (timeout >= 0) {
1315	#if 0 /* this does nothing useful, but leave it here in case that changes */	1315	#if 0 /* this does nothing useful, but leave it here in case that changes */
1316	/* the called routine adds 1 to the passed value */	1316	/* the called routine adds 1 to the passed value */
1317	usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);	1317	usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1318	#endif	1318	#endif
1319	/*	1319	/*
1320	* XXX	1320	* XXX
1321	* This is potentially dangerous because it assumes	1321	* This is potentially dangerous because it assumes
1322	* that only one device is ever plugged in!	1322	* that only one device is ever plugged in!
1323	*/	1323	*/
1324	devgone = dev;	1324	devgone = dev;
1325	}	1325	}
1326	}	1326	}
1327	#endif	1327	#endif
1328		1328
1329	dev->status = stat;	1329	dev->status = stat;
1330	dev->act_len = transfer_len;	1330	dev->act_len = transfer_len;
1331		1331
1332	#ifdef DEBUG	1332	#ifdef DEBUG
1333	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));	1333	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1334	#else	1334	#else
1335	wait_ms(1);	1335	wait_ms(1);
1336	#endif	1336	#endif
1337		1337
1338	/* free TDs in urb_priv */	1338	/* free TDs in urb_priv */
1339	urb_free_priv (&urb_priv);	1339	urb_free_priv (&urb_priv);
1340	return 0;	1340	return 0;
1341	}	1341	}
1342		1342
1343	/* submit routines called from usb.c */	1343	/* submit routines called from usb.c */
1344	int submit_bulk_msg(struct usb_device dev, unsigned long pipe, void buffer,	1344	int submit_bulk_msg(struct usb_device dev, unsigned long pipe, void buffer,
1345	int transfer_len)	1345	int transfer_len)
1346	{	1346	{
1347	info("submit_bulk_msg");	1347	info("submit_bulk_msg");
1348	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);	1348	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1349	}	1349	}
1350		1350
1351	int submit_control_msg(struct usb_device dev, unsigned long pipe, void buffer,	1351	int submit_control_msg(struct usb_device dev, unsigned long pipe, void buffer,
1352	int transfer_len, struct devrequest *setup)	1352	int transfer_len, struct devrequest *setup)
1353	{	1353	{
1354	int maxsize = usb_maxpacket(dev, pipe);	1354	int maxsize = usb_maxpacket(dev, pipe);
1355		1355
1356	info("submit_control_msg");	1356	info("submit_control_msg");
1357	#ifdef DEBUG	1357	#ifdef DEBUG
1358	urb_priv.actual_length = 0;	1358	urb_priv.actual_length = 0;
1359	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));	1359	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1360	#else	1360	#else
1361	wait_ms(1);	1361	wait_ms(1);
1362	#endif	1362	#endif
1363	if (!maxsize) {	1363	if (!maxsize) {
1364	err("submit_control_message: pipesize for pipe %lx is zero",	1364	err("submit_control_message: pipesize for pipe %lx is zero",
1365	pipe);	1365	pipe);
1366	return -1;	1366	return -1;
1367	}	1367	}
1368	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {	1368	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1369	gohci.rh.dev = dev;	1369	gohci.rh.dev = dev;
1370	/* root hub - redirect */	1370	/* root hub - redirect */
1371	return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,	1371	return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1372	setup);	1372	setup);
1373	}	1373	}
1374		1374
1375	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);	1375	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1376	}	1376	}
1377		1377
1378	int submit_int_msg(struct usb_device dev, unsigned long pipe, void buffer,	1378	int submit_int_msg(struct usb_device dev, unsigned long pipe, void buffer,
1379	int transfer_len, int interval)	1379	int transfer_len, int interval)
1380	{	1380	{
1381	info("submit_int_msg");	1381	info("submit_int_msg");
1382	return -1;	1382	return -1;
1383	}	1383	}
1384		1384
1385	/-------------------------------------------------------------------------	1385	/-------------------------------------------------------------------------
1386	* HC functions	1386	* HC functions
1387	-------------------------------------------------------------------------/	1387	-------------------------------------------------------------------------/
1388		1388
1389	/* reset the HC and BUS */	1389	/* reset the HC and BUS */
1390		1390
1391	static int hc_reset (ohci_t *ohci)	1391	static int hc_reset (ohci_t *ohci)
1392	{	1392	{
1393	int timeout = 30;	1393	int timeout = 30;
1394	int smm_timeout = 50; /* 0,5 sec */	1394	int smm_timeout = 50; /* 0,5 sec */
1395		1395
1396	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */	1396	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1397	writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */	1397	writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1398	info("USB HC TakeOver from SMM");	1398	info("USB HC TakeOver from SMM");
1399	while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {	1399	while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1400	wait_ms (10);	1400	wait_ms (10);
1401	if (--smm_timeout == 0) {	1401	if (--smm_timeout == 0) {
1402	err("USB HC TakeOver failed!");	1402	err("USB HC TakeOver failed!");
1403	return -1;	1403	return -1;
1404	}	1404	}
1405	}	1405	}
1406	}	1406	}
1407		1407
1408	/* Disable HC interrupts */	1408	/* Disable HC interrupts */
1409	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);	1409	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1410		1410
1411	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",	1411	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1412	ohci->slot_name,	1412	ohci->slot_name,
1413	readl (&ohci->regs->control));	1413	readl (&ohci->regs->control));
1414		1414
1415	/* Reset USB (needed by some controllers) */	1415	/* Reset USB (needed by some controllers) */
1416	writel (0, &ohci->regs->control);	1416	writel (0, &ohci->regs->control);
1417		1417
1418	/* HC Reset requires max 10 us delay */	1418	/* HC Reset requires max 10 us delay */
1419	writel (OHCI_HCR, &ohci->regs->cmdstatus);	1419	writel (OHCI_HCR, &ohci->regs->cmdstatus);
1420	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {	1420	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1421	if (--timeout == 0) {	1421	if (--timeout == 0) {
1422	err("USB HC reset timed out!");	1422	err("USB HC reset timed out!");
1423	return -1;	1423	return -1;
1424	}	1424	}
1425	udelay (1);	1425	udelay (1);
1426	}	1426	}
1427	return 0;	1427	return 0;
1428	}	1428	}
1429		1429
1430	/-------------------------------------------------------------------------/	1430	/-------------------------------------------------------------------------/
1431		1431
1432	/* Start an OHCI controller, set the BUS operational	1432	/* Start an OHCI controller, set the BUS operational
1433	* enable interrupts	1433	* enable interrupts
1434	* connect the virtual root hub */	1434	* connect the virtual root hub */
1435		1435
1436	static int hc_start (ohci_t * ohci)	1436	static int hc_start (ohci_t * ohci)
1437	{	1437	{
1438	__u32 mask;	1438	__u32 mask;
1439	unsigned int fminterval;	1439	unsigned int fminterval;
1440		1440
1441	ohci->disabled = 1;	1441	ohci->disabled = 1;
1442		1442
1443	/* Tell the controller where the control and bulk lists are	1443	/* Tell the controller where the control and bulk lists are
1444	* The lists are empty now. */	1444	* The lists are empty now. */
1445		1445
1446	writel (0, &ohci->regs->ed_controlhead);	1446	writel (0, &ohci->regs->ed_controlhead);
1447	writel (0, &ohci->regs->ed_bulkhead);	1447	writel (0, &ohci->regs->ed_bulkhead);
1448		1448
1449	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */	1449	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1450		1450
1451	fminterval = 0x2edf;	1451	fminterval = 0x2edf;
1452	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);	1452	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1453	fminterval \|= ((((fminterval - 210) * 6) / 7) << 16);	1453	fminterval \|= ((((fminterval - 210) * 6) / 7) << 16);
1454	writel (fminterval, &ohci->regs->fminterval);	1454	writel (fminterval, &ohci->regs->fminterval);
1455	writel (0x628, &ohci->regs->lsthresh);	1455	writel (0x628, &ohci->regs->lsthresh);
1456		1456
1457	/* start controller operations */	1457	/* start controller operations */
1458	ohci->hc_control = OHCI_CONTROL_INIT \| OHCI_USB_OPER;	1458	ohci->hc_control = OHCI_CONTROL_INIT \| OHCI_USB_OPER;
1459	ohci->disabled = 0;	1459	ohci->disabled = 0;
1460	writel (ohci->hc_control, &ohci->regs->control);	1460	writel (ohci->hc_control, &ohci->regs->control);
1461		1461
1462	/* disable all interrupts */	1462	/* disable all interrupts */
1463	mask = (OHCI_INTR_SO \| OHCI_INTR_WDH \| OHCI_INTR_SF \| OHCI_INTR_RD \|	1463	mask = (OHCI_INTR_SO \| OHCI_INTR_WDH \| OHCI_INTR_SF \| OHCI_INTR_RD \|
1464	OHCI_INTR_UE \| OHCI_INTR_FNO \| OHCI_INTR_RHSC \|	1464	OHCI_INTR_UE \| OHCI_INTR_FNO \| OHCI_INTR_RHSC \|
1465	OHCI_INTR_OC \| OHCI_INTR_MIE);	1465	OHCI_INTR_OC \| OHCI_INTR_MIE);
1466	writel (mask, &ohci->regs->intrdisable);	1466	writel (mask, &ohci->regs->intrdisable);
1467	/* clear all interrupts */	1467	/* clear all interrupts */
1468	mask &= ~OHCI_INTR_MIE;	1468	mask &= ~OHCI_INTR_MIE;
1469	writel (mask, &ohci->regs->intrstatus);	1469	writel (mask, &ohci->regs->intrstatus);
1470	/* Choose the interrupts we care about now - but w/o MIE */	1470	/* Choose the interrupts we care about now - but w/o MIE */
1471	mask = OHCI_INTR_RHSC \| OHCI_INTR_UE \| OHCI_INTR_WDH \| OHCI_INTR_SO;	1471	mask = OHCI_INTR_RHSC \| OHCI_INTR_UE \| OHCI_INTR_WDH \| OHCI_INTR_SO;
1472	writel (mask, &ohci->regs->intrenable);	1472	writel (mask, &ohci->regs->intrenable);
1473		1473
1474	#ifdef OHCI_USE_NPS	1474	#ifdef OHCI_USE_NPS
1475	/* required for AMD-756 and some Mac platforms */	1475	/* required for AMD-756 and some Mac platforms */
1476	writel ((roothub_a (ohci) \| RH_A_NPS) & ~RH_A_PSM,	1476	writel ((roothub_a (ohci) \| RH_A_NPS) & ~RH_A_PSM,
1477	&ohci->regs->roothub.a);	1477	&ohci->regs->roothub.a);
1478	writel (RH_HS_LPSC, &ohci->regs->roothub.status);	1478	writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1479	#endif /* OHCI_USE_NPS */	1479	#endif /* OHCI_USE_NPS */
1480		1480
1481	#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})	1481	#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1482	/* POTPGT delay is bits 24-31, in 2 ms units. */	1482	/* POTPGT delay is bits 24-31, in 2 ms units. */
1483	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);	1483	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1484		1484
1485	/* connect the virtual root hub */	1485	/* connect the virtual root hub */
1486	ohci->rh.devnum = 0;	1486	ohci->rh.devnum = 0;
1487		1487
1488	return 0;	1488	return 0;
1489	}	1489	}
1490		1490
1491	/-------------------------------------------------------------------------/	1491	/-------------------------------------------------------------------------/
1492		1492
1493	/* an interrupt happens */	1493	/* an interrupt happens */
1494		1494
1495	static int	1495	static int
1496	hc_interrupt (void)	1496	hc_interrupt (void)
1497	{	1497	{
1498	ohci_t *ohci = &gohci;	1498	ohci_t *ohci = &gohci;
1499	struct ohci_regs *regs = ohci->regs;	1499	struct ohci_regs *regs = ohci->regs;
1500	int ints;	1500	int ints;
1501	int stat = -1;	1501	int stat = -1;
1502		1502
1503	if ((ohci->hcca->done_head != 0) &&	1503	if ((ohci->hcca->done_head != 0) &&
1504	!(m32_swap (ohci->hcca->done_head) & 0x01)) {	1504	!(m32_swap (ohci->hcca->done_head) & 0x01)) {
1505		1505
1506	ints = OHCI_INTR_WDH;	1506	ints = OHCI_INTR_WDH;
1507		1507
1508	} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {	1508	} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
1509	ohci->disabled++;	1509	ohci->disabled++;
1510	err ("%s device removed!", ohci->slot_name);	1510	err ("%s device removed!", ohci->slot_name);
1511	return -1;	1511	return -1;
1512		1512
1513	} else if ((ints &= readl (&regs->intrenable)) == 0) {	1513	} else if ((ints &= readl (&regs->intrenable)) == 0) {
1514	dbg("hc_interrupt: returning..\n");	1514	dbg("hc_interrupt: returning..\n");
1515	return 0xff;	1515	return 0xff;
1516	}	1516	}
1517		1517
1518	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */	1518	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1519		1519
1520	if (ints & OHCI_INTR_RHSC) {	1520	if (ints & OHCI_INTR_RHSC) {
1521	got_rhsc = 1;	1521	got_rhsc = 1;
1522	stat = 0xff;	1522	stat = 0xff;
1523	}	1523	}
1524		1524
1525	if (ints & OHCI_INTR_UE) {	1525	if (ints & OHCI_INTR_UE) {
1526	ohci->disabled++;	1526	ohci->disabled++;
1527	err ("OHCI Unrecoverable Error, controller usb-%s disabled",	1527	err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1528	ohci->slot_name);	1528	ohci->slot_name);
1529	/* e.g. due to PCI Master/Target Abort */	1529	/* e.g. due to PCI Master/Target Abort */
1530		1530
1531	#ifdef DEBUG	1531	#ifdef DEBUG
1532	ohci_dump (ohci, 1);	1532	ohci_dump (ohci, 1);
1533	#else	1533	#else
1534	wait_ms(1);	1534	wait_ms(1);
1535	#endif	1535	#endif
1536	/* FIXME: be optimistic, hope that bug won't repeat often. */	1536	/* FIXME: be optimistic, hope that bug won't repeat often. */
1537	/* Make some non-interrupt context restart the controller. */	1537	/* Make some non-interrupt context restart the controller. */
1538	/* Count and limit the retries though; either hardware or */	1538	/* Count and limit the retries though; either hardware or */
1539	/* software errors can go forever... */	1539	/* software errors can go forever... */
1540	hc_reset (ohci);	1540	hc_reset (ohci);
1541	return -1;	1541	return -1;
1542	}	1542	}
1543		1543
1544	if (ints & OHCI_INTR_WDH) {	1544	if (ints & OHCI_INTR_WDH) {
1545	wait_ms(1);	1545	wait_ms(1);
1546		1546
1547	writel (OHCI_INTR_WDH, &regs->intrdisable);	1547	writel (OHCI_INTR_WDH, &regs->intrdisable);
1548	stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));	1548	stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1549	writel (OHCI_INTR_WDH, &regs->intrenable);	1549	writel (OHCI_INTR_WDH, &regs->intrenable);
1550	}	1550	}
1551		1551
1552	if (ints & OHCI_INTR_SO) {	1552	if (ints & OHCI_INTR_SO) {
1553	dbg("USB Schedule overrun\n");	1553	dbg("USB Schedule overrun\n");
1554	writel (OHCI_INTR_SO, &regs->intrenable);	1554	writel (OHCI_INTR_SO, &regs->intrenable);
1555	stat = -1;	1555	stat = -1;
1556	}	1556	}
1557		1557
1558	/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */	1558	/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1559	if (ints & OHCI_INTR_SF) {	1559	if (ints & OHCI_INTR_SF) {
1560	unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;	1560	unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1561	wait_ms(1);	1561	wait_ms(1);
1562	writel (OHCI_INTR_SF, &regs->intrdisable);	1562	writel (OHCI_INTR_SF, &regs->intrdisable);
1563	if (ohci->ed_rm_list[frame] != NULL)	1563	if (ohci->ed_rm_list[frame] != NULL)
1564	writel (OHCI_INTR_SF, &regs->intrenable);	1564	writel (OHCI_INTR_SF, &regs->intrenable);
1565	stat = 0xff;	1565	stat = 0xff;
1566	}	1566	}
1567		1567
1568	writel (ints, &regs->intrstatus);	1568	writel (ints, &regs->intrstatus);
1569	return stat;	1569	return stat;
1570	}	1570	}
1571		1571
1572	/-------------------------------------------------------------------------/	1572	/-------------------------------------------------------------------------/
1573		1573
1574	/-------------------------------------------------------------------------/	1574	/-------------------------------------------------------------------------/
1575		1575
1576	/* De-allocate all resources.. */	1576	/* De-allocate all resources.. */
1577		1577
1578	static void hc_release_ohci (ohci_t *ohci)	1578	static void hc_release_ohci (ohci_t *ohci)
1579	{	1579	{
1580	dbg ("USB HC release ohci usb-%s", ohci->slot_name);	1580	dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1581		1581
1582	if (!ohci->disabled)	1582	if (!ohci->disabled)
1583	hc_reset (ohci);	1583	hc_reset (ohci);
1584	}	1584	}
1585		1585
1586	/-------------------------------------------------------------------------/	1586	/-------------------------------------------------------------------------/
1587		1587
1588	/*	1588	/*
1589	* low level initalisation routine, called from usb.c	1589	* low level initalisation routine, called from usb.c
1590	*/	1590	*/
1591	static char ohci_inited = 0;	1591	static char ohci_inited = 0;
1592		1592
1593	int usb_lowlevel_init(void)	1593	int usb_lowlevel_init(void)
1594	{	1594	{
1595	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();	1595	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1596	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();	1596	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1597		1597
1598	/*	1598	/*
1599	* Set the 48 MHz UPLL clocking. Values are taken from	1599	* Set the 48 MHz UPLL clocking. Values are taken from
1600	* "PLL value selection guide", 6-23, s3c2400_UM.pdf.	1600	* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
1601	*/	1601	*/
1602	clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);	1602	clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
1603	gpio->MISCCR \|= 0x8; /* 1 = use pads related USB for USB host */	1603	gpio->MISCCR \|= 0x8; /* 1 = use pads related USB for USB host */
1604		1604
1605	/*	1605	/*
1606	* Enable USB host clock.	1606	* Enable USB host clock.
1607	*/	1607	*/
1608	clk_power->CLKCON \|= (1 << 4);	1608	clk_power->CLKCON \|= (1 << 4);
1609		1609
1610	memset (&gohci, 0, sizeof (ohci_t));	1610	memset (&gohci, 0, sizeof (ohci_t));
1611	memset (&urb_priv, 0, sizeof (urb_priv_t));	1611	memset (&urb_priv, 0, sizeof (urb_priv_t));
1612		1612
1613	/* align the storage */	1613	/* align the storage */
1614	if ((__u32)&ghcca[0] & 0xff) {	1614	if ((__u32)&ghcca[0] & 0xff) {
1615	err("HCCA not aligned!!");	1615	err("HCCA not aligned!!");
1616	return -1;	1616	return -1;
1617	}	1617	}
1618	phcca = &ghcca[0];	1618	phcca = &ghcca[0];
1619	info("aligned ghcca %p", phcca);	1619	info("aligned ghcca %p", phcca);
1620	memset(&ohci_dev, 0, sizeof(struct ohci_device));	1620	memset(&ohci_dev, 0, sizeof(struct ohci_device));
1621	if ((__u32)&ohci_dev.ed[0] & 0x7) {	1621	if ((__u32)&ohci_dev.ed[0] & 0x7) {
1622	err("EDs not aligned!!");	1622	err("EDs not aligned!!");
1623	return -1;	1623	return -1;
1624	}	1624	}
1625	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));	1625	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1626	if ((__u32)gtd & 0x7) {	1626	if ((__u32)gtd & 0x7) {
1627	err("TDs not aligned!!");	1627	err("TDs not aligned!!");
1628	return -1;	1628	return -1;
1629	}	1629	}
1630	ptd = gtd;	1630	ptd = gtd;
1631	gohci.hcca = phcca;	1631	gohci.hcca = phcca;
1632	memset (phcca, 0, sizeof (struct ohci_hcca));	1632	memset (phcca, 0, sizeof (struct ohci_hcca));
1633		1633
1634	gohci.disabled = 1;	1634	gohci.disabled = 1;
1635	gohci.sleeping = 0;	1635	gohci.sleeping = 0;
1636	gohci.irq = -1;	1636	gohci.irq = -1;
1637	gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;	1637	gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
1638		1638
1639	gohci.flags = 0;	1639	gohci.flags = 0;
1640	gohci.slot_name = "s3c2400";	1640	gohci.slot_name = "s3c2400";
1641		1641
1642	if (hc_reset (&gohci) < 0) {	1642	if (hc_reset (&gohci) < 0) {
1643	hc_release_ohci (&gohci);	1643	hc_release_ohci (&gohci);
1644	/* Initialization failed */	1644	/* Initialization failed */
1645	clk_power->CLKCON &= ~(1 << 4);	1645	clk_power->CLKCON &= ~(1 << 4);
1646	return -1;	1646	return -1;
1647	}	1647	}
1648		1648
1649	/* FIXME this is a second HC reset; why?? */	1649	/* FIXME this is a second HC reset; why?? */
1650	gohci.hc_control = OHCI_USB_RESET;	1650	gohci.hc_control = OHCI_USB_RESET;
1651	writel (gohci.hc_control, &gohci.regs->control);	1651	writel (gohci.hc_control, &gohci.regs->control);
1652	wait_ms (10);	1652	wait_ms (10);
1653		1653
1654	if (hc_start (&gohci) < 0) {	1654	if (hc_start (&gohci) < 0) {
1655	err ("can't start usb-%s", gohci.slot_name);	1655	err ("can't start usb-%s", gohci.slot_name);
1656	hc_release_ohci (&gohci);	1656	hc_release_ohci (&gohci);
1657	/* Initialization failed */	1657	/* Initialization failed */
1658	clk_power->CLKCON &= ~(1 << 4);	1658	clk_power->CLKCON &= ~(1 << 4);
1659	return -1;	1659	return -1;
1660	}	1660	}
1661		1661
1662	#ifdef DEBUG	1662	#ifdef DEBUG
1663	ohci_dump (&gohci, 1);	1663	ohci_dump (&gohci, 1);
1664	#else	1664	#else
1665	wait_ms(1);	1665	wait_ms(1);
1666	#endif	1666	#endif
1667	ohci_inited = 1;	1667	ohci_inited = 1;
1668	urb_finished = 1;	1668	urb_finished = 1;
1669		1669
1670	return 0;	1670	return 0;
1671	}	1671	}
1672		1672
1673	int usb_lowlevel_stop(void)	1673	int usb_lowlevel_stop(void)
1674	{	1674	{
1675	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();	1675	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1676		1676
1677	/* this gets called really early - before the controller has */	1677	/* this gets called really early - before the controller has */
1678	/* even been initialized! */	1678	/* even been initialized! */
1679	if (!ohci_inited)	1679	if (!ohci_inited)
1680	return 0;	1680	return 0;
1681	/* TODO release any interrupts, etc. */	1681	/* TODO release any interrupts, etc. */
1682	/* call hc_release_ohci() here ? */	1682	/* call hc_release_ohci() here ? */
1683	hc_reset (&gohci);	1683	hc_reset (&gohci);
1684	/* may not want to do this */	1684	/* may not want to do this */
1685	clk_power->CLKCON &= ~(1 << 4);	1685	clk_power->CLKCON &= ~(1 << 4);
1686	return 0;	1686	return 0;
1687	}	1687	}
1688		1688
1689	#endif /* CONFIG_USB_OHCI */	1689	#endif /* CONFIG_USB_OHCI */
1690		1690

cpu/mpc5xxx/usb_ohci.c

Diff comments View file @ d00ce09

1	/*	1	/*
2	* URB OHCI HCD (Host Controller Driver) for USB on the MPC5200.	2	* URB OHCI HCD (Host Controller Driver) for USB on the MPC5200.
3	*	3	*
4	* (C) Copyright 2003-2004	4	* (C) Copyright 2003-2004
5	* Gary Jennejohn, DENX Software Engineering <gj@denx.de>	5	* Gary Jennejohn, DENX Software Engineering <gj@denx.de>
6	*	6	*
7	* (C) Copyright 2004	7	* (C) Copyright 2004
8	* Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>	8	* Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
9	*	9	*
10	* Note: Much of this code has been derived from Linux 2.4	10	* Note: Much of this code has been derived from Linux 2.4
11	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>	11	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
12	* (C) Copyright 2000-2002 David Brownell	12	* (C) Copyright 2000-2002 David Brownell
13	*	13	*
14	* See file CREDITS for list of people who contributed to this	14	* See file CREDITS for list of people who contributed to this
15	* project.	15	* project.
16	*	16	*
17	* This program is free software; you can redistribute it and/or	17	* This program is free software; you can redistribute it and/or
18	* modify it under the terms of the GNU General Public License as	18	* modify it under the terms of the GNU General Public License as
19	* published by the Free Software Foundation; either version 2 of	19	* published by the Free Software Foundation; either version 2 of
20	* the License, or (at your option) any later version.	20	* the License, or (at your option) any later version.
21	*	21	*
22	* This program is distributed in the hope that it will be useful,	22	* This program is distributed in the hope that it will be useful,
23	* but WITHOUT ANY WARRANTY; without even the implied warranty of	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25	* GNU General Public License for more details.	25	* GNU General Public License for more details.
26	*	26	*
27	* You should have received a copy of the GNU General Public License	27	* You should have received a copy of the GNU General Public License
28	* along with this program; if not, write to the Free Software	28	* along with this program; if not, write to the Free Software
29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30	* MA 02111-1307 USA	30	* MA 02111-1307 USA
31	*	31	*
32	*/	32	*/
33	/*	33	/*
34	* IMPORTANT NOTES	34	* IMPORTANT NOTES
35	* 1 - this driver is intended for use with USB Mass Storage Devices	35	* 1 - this driver is intended for use with USB Mass Storage Devices
36	* (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!	36	* (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
37	*/	37	*/
38		38
39	#include <common.h>	39	#include <common.h>
40		40
41	#ifdef CONFIG_USB_OHCI	41	#ifdef CONFIG_USB_OHCI
42		42
43	#include <malloc.h>	43	#include <malloc.h>
44	#include <usb.h>	44	#include <usb.h>
45	#include "usb_ohci.h"	45	#include "usb_ohci.h"
46		46
47	#include <mpc5xxx.h>	47	#include <mpc5xxx.h>
48		48
49	#define OHCI_USE_NPS /* force NoPowerSwitching mode */	49	#define OHCI_USE_NPS /* force NoPowerSwitching mode */
50	#undef OHCI_VERBOSE_DEBUG /* not always helpful */	50	#undef OHCI_VERBOSE_DEBUG /* not always helpful */
51	#undef DEBUG	51	#undef DEBUG
52	#undef SHOW_INFO	52	#undef SHOW_INFO
53	#undef OHCI_FILL_TRACE	53	#undef OHCI_FILL_TRACE
54		54
55	/* For initializing controller (mask in an HCFS mode too) */	55	/* For initializing controller (mask in an HCFS mode too) */
56	#define OHCI_CONTROL_INIT \	56	#define OHCI_CONTROL_INIT \
57	(OHCI_CTRL_CBSR & 0x3) \| OHCI_CTRL_IE \| OHCI_CTRL_PLE	57	(OHCI_CTRL_CBSR & 0x3) \| OHCI_CTRL_IE \| OHCI_CTRL_PLE
58		58
59	#define readl(a) (((vu_long )(a)))	59	#define readl(a) (((volatile u32 )(a)))
60	#define writel(a, b) (((vu_long )(b)) = ((vu_long)a))	60	#define writel(a, b) (((volatile u32 )(b)) = ((volatile u32)a))
61		61
62	#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })	62	#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
63		63
64	#ifdef DEBUG	64	#ifdef DEBUG
65	#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)	65	#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
66	#else	66	#else
67	#define dbg(format, arg...) do {} while(0)	67	#define dbg(format, arg...) do {} while(0)
68	#endif /* DEBUG */	68	#endif /* DEBUG */
69	#define err(format, arg...) printf("ERROR: " format "\n", ## arg)	69	#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
70	#ifdef SHOW_INFO	70	#ifdef SHOW_INFO
71	#define info(format, arg...) printf("INFO: " format "\n", ## arg)	71	#define info(format, arg...) printf("INFO: " format "\n", ## arg)
72	#else	72	#else
73	#define info(format, arg...) do {} while(0)	73	#define info(format, arg...) do {} while(0)
74	#endif	74	#endif
75		75
76	#define m16_swap(x) swap_16(x)	76	#define m16_swap(x) swap_16(x)
77	#define m32_swap(x) swap_32(x)	77	#define m32_swap(x) swap_32(x)
78		78
79	#ifdef CONFIG_MPC5200	79	#ifdef CONFIG_MPC5200
80	#define ohci_cpu_to_le16(x) (x)	80	#define ohci_cpu_to_le16(x) (x)
81	#define ohci_cpu_to_le32(x) (x)	81	#define ohci_cpu_to_le32(x) (x)
82	#else	82	#else
83	#define ohci_cpu_to_le16(x) swap_16(x)	83	#define ohci_cpu_to_le16(x) swap_16(x)
84	#define ohci_cpu_to_le32(x) swap_32(x)	84	#define ohci_cpu_to_le32(x) swap_32(x)
85	#endif	85	#endif
86		86
87	/* global ohci_t */	87	/* global ohci_t */
88	static ohci_t gohci;	88	static ohci_t gohci;
89	/* this must be aligned to a 256 byte boundary */	89	/* this must be aligned to a 256 byte boundary */
90	struct ohci_hcca ghcca[1];	90	struct ohci_hcca ghcca[1];
91	/* a pointer to the aligned storage */	91	/* a pointer to the aligned storage */
92	struct ohci_hcca *phcca;	92	struct ohci_hcca *phcca;
93	/* this allocates EDs for all possible endpoints */	93	/* this allocates EDs for all possible endpoints */
94	struct ohci_device ohci_dev;	94	struct ohci_device ohci_dev;
95	/* urb_priv */	95	/* urb_priv */
96	urb_priv_t urb_priv;	96	urb_priv_t urb_priv;
97	/* RHSC flag */	97	/* RHSC flag */
98	int got_rhsc;	98	int got_rhsc;
99	/* device which was disconnected */	99	/* device which was disconnected */
100	struct usb_device *devgone;	100	struct usb_device *devgone;
101	/* flag guarding URB transation */	101	/* flag guarding URB transation */
102	int urb_finished = 0;	102	int urb_finished = 0;
103		103
104	/-------------------------------------------------------------------------/	104	/-------------------------------------------------------------------------/
105		105
106	/* AMD-756 (D2 rev) reports corrupt register contents in some cases.	106	/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
107	* The erratum (#4) description is incorrect. AMD's workaround waits	107	* The erratum (#4) description is incorrect. AMD's workaround waits
108	* till some bits (mostly reserved) are clear; ok for all revs.	108	* till some bits (mostly reserved) are clear; ok for all revs.
109	*/	109	*/
110	#define OHCI_QUIRK_AMD756 0xabcd	110	#define OHCI_QUIRK_AMD756 0xabcd
111	#define read_roothub(hc, register, mask) ({ \	111	#define read_roothub(hc, register, mask) ({ \
112	u32 temp = readl (&hc->regs->roothub.register); \	112	u32 temp = readl (&hc->regs->roothub.register); \
113	if (hc->flags & OHCI_QUIRK_AMD756) \	113	if (hc->flags & OHCI_QUIRK_AMD756) \
114	while (temp & mask) \	114	while (temp & mask) \
115	temp = readl (&hc->regs->roothub.register); \	115	temp = readl (&hc->regs->roothub.register); \
116	temp; })	116	temp; })
117		117
118	static u32 roothub_a (struct ohci *hc)	118	static u32 roothub_a (struct ohci *hc)
119	{ return read_roothub (hc, a, 0xfc0fe000); }	119	{ return read_roothub (hc, a, 0xfc0fe000); }
120	static inline u32 roothub_b (struct ohci *hc)	120	static inline u32 roothub_b (struct ohci *hc)
121	{ return readl (&hc->regs->roothub.b); }	121	{ return readl (&hc->regs->roothub.b); }
122	static inline u32 roothub_status (struct ohci *hc)	122	static inline u32 roothub_status (struct ohci *hc)
123	{ return readl (&hc->regs->roothub.status); }	123	{ return readl (&hc->regs->roothub.status); }
124	static u32 roothub_portstatus (struct ohci *hc, int i)	124	static u32 roothub_portstatus (struct ohci *hc, int i)
125	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }	125	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
126		126
127		127
128	/* forward declaration */	128	/* forward declaration */
129	static int hc_interrupt (void);	129	static int hc_interrupt (void);
130	static void	130	static void
131	td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,	131	td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
132	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);	132	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
133		133
134	/-------------------------------------------------------------------------	134	/-------------------------------------------------------------------------
135	* URB support functions	135	* URB support functions
136	-------------------------------------------------------------------------/	136	-------------------------------------------------------------------------/
137		137
138	/* free HCD-private data associated with this URB */	138	/* free HCD-private data associated with this URB */
139		139
140	static void urb_free_priv (urb_priv_t * urb)	140	static void urb_free_priv (urb_priv_t * urb)
141	{	141	{
142	int i;	142	int i;
143	int last;	143	int last;
144	struct td * td;	144	struct td * td;
145		145
146	last = urb->length - 1;	146	last = urb->length - 1;
147	if (last >= 0) {	147	if (last >= 0) {
148	for (i = 0; i <= last; i++) {	148	for (i = 0; i <= last; i++) {
149	td = urb->td[i];	149	td = urb->td[i];
150	if (td) {	150	if (td) {
151	td->usb_dev = NULL;	151	td->usb_dev = NULL;
152	urb->td[i] = NULL;	152	urb->td[i] = NULL;
153	}	153	}
154	}	154	}
155	}	155	}
156	}	156	}
157		157
158	/-------------------------------------------------------------------------/	158	/-------------------------------------------------------------------------/
159		159
160	#ifdef DEBUG	160	#ifdef DEBUG
161	static int sohci_get_current_frame_number (struct usb_device * dev);	161	static int sohci_get_current_frame_number (struct usb_device * dev);
162		162
163	/* debug\| print the main components of an URB	163	/* debug\| print the main components of an URB
164	* small: 0) header + data packets 1) just header */	164	* small: 0) header + data packets 1) just header */
165		165
166	static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,	166	static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
167	int transfer_len, struct devrequest * setup, char * str, int small)	167	int transfer_len, struct devrequest * setup, char * str, int small)
168	{	168	{
169	urb_priv_t * purb = &urb_priv;	169	urb_priv_t * purb = &urb_priv;
170		170
171	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",	171	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
172	str,	172	str,
173	sohci_get_current_frame_number (dev),	173	sohci_get_current_frame_number (dev),
174	usb_pipedevice (pipe),	174	usb_pipedevice (pipe),
175	usb_pipeendpoint (pipe),	175	usb_pipeendpoint (pipe),
176	usb_pipeout (pipe)? 'O': 'I',	176	usb_pipeout (pipe)? 'O': 'I',
177	usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):	177	usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
178	(usb_pipecontrol (pipe)? "CTRL": "BULK"),	178	(usb_pipecontrol (pipe)? "CTRL": "BULK"),
179	purb->actual_length,	179	purb->actual_length,
180	transfer_len, dev->status);	180	transfer_len, dev->status);
181	#ifdef OHCI_VERBOSE_DEBUG	181	#ifdef OHCI_VERBOSE_DEBUG
182	if (!small) {	182	if (!small) {
183	int i, len;	183	int i, len;
184		184
185	if (usb_pipecontrol (pipe)) {	185	if (usb_pipecontrol (pipe)) {
186	printf (__FILE__ ": cmd(8):");	186	printf (__FILE__ ": cmd(8):");
187	for (i = 0; i < 8 ; i++)	187	for (i = 0; i < 8 ; i++)
188	printf (" %02x", ((__u8 *) setup) [i]);	188	printf (" %02x", ((__u8 *) setup) [i]);
189	printf ("\n");	189	printf ("\n");
190	}	190	}
191	if (transfer_len > 0 && buffer) {	191	if (transfer_len > 0 && buffer) {
192	printf (__FILE__ ": data(%d/%d):",	192	printf (__FILE__ ": data(%d/%d):",
193	purb->actual_length,	193	purb->actual_length,
194	transfer_len);	194	transfer_len);
195	len = usb_pipeout (pipe)?	195	len = usb_pipeout (pipe)?
196	transfer_len: purb->actual_length;	196	transfer_len: purb->actual_length;
197	for (i = 0; i < 16 && i < len; i++)	197	for (i = 0; i < 16 && i < len; i++)
198	printf (" %02x", ((__u8 *) buffer) [i]);	198	printf (" %02x", ((__u8 *) buffer) [i]);
199	printf ("%s\n", i < len? "...": "");	199	printf ("%s\n", i < len? "...": "");
200	}	200	}
201	}	201	}
202	#endif	202	#endif
203	}	203	}
204		204
205	/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/	205	/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
206	void ep_print_int_eds (ohci_t ohci, char str) {	206	void ep_print_int_eds (ohci_t ohci, char str) {
207	int i, j;	207	int i, j;
208	__u32 * ed_p;	208	__u32 * ed_p;
209	for (i= 0; i < 32; i++) {	209	for (i= 0; i < 32; i++) {
210	j = 5;	210	j = 5;
211	ed_p = &(ohci->hcca->int_table [i]);	211	ed_p = &(ohci->hcca->int_table [i]);
212	if (*ed_p == 0)	212	if (*ed_p == 0)
213	continue;	213	continue;
214	printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);	214	printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
215	while (*ed_p != 0 && j--) {	215	while (*ed_p != 0 && j--) {
216	ed_t ed = (ed_t )ohci_cpu_to_le32(ed_p);	216	ed_t ed = (ed_t )ohci_cpu_to_le32(ed_p);
217	printf (" ed: %4x;", ed->hwINFO);	217	printf (" ed: %4x;", ed->hwINFO);
218	ed_p = &ed->hwNextED;	218	ed_p = &ed->hwNextED;
219	}	219	}
220	printf ("\n");	220	printf ("\n");
221	}	221	}
222	}	222	}
223		223
224	static void ohci_dump_intr_mask (char *label, __u32 mask)	224	static void ohci_dump_intr_mask (char *label, __u32 mask)
225	{	225	{
226	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",	226	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
227	label,	227	label,
228	mask,	228	mask,
229	(mask & OHCI_INTR_MIE) ? " MIE" : "",	229	(mask & OHCI_INTR_MIE) ? " MIE" : "",
230	(mask & OHCI_INTR_OC) ? " OC" : "",	230	(mask & OHCI_INTR_OC) ? " OC" : "",
231	(mask & OHCI_INTR_RHSC) ? " RHSC" : "",	231	(mask & OHCI_INTR_RHSC) ? " RHSC" : "",
232	(mask & OHCI_INTR_FNO) ? " FNO" : "",	232	(mask & OHCI_INTR_FNO) ? " FNO" : "",
233	(mask & OHCI_INTR_UE) ? " UE" : "",	233	(mask & OHCI_INTR_UE) ? " UE" : "",
234	(mask & OHCI_INTR_RD) ? " RD" : "",	234	(mask & OHCI_INTR_RD) ? " RD" : "",
235	(mask & OHCI_INTR_SF) ? " SF" : "",	235	(mask & OHCI_INTR_SF) ? " SF" : "",
236	(mask & OHCI_INTR_WDH) ? " WDH" : "",	236	(mask & OHCI_INTR_WDH) ? " WDH" : "",
237	(mask & OHCI_INTR_SO) ? " SO" : ""	237	(mask & OHCI_INTR_SO) ? " SO" : ""
238	);	238	);
239	}	239	}
240		240
241	static void maybe_print_eds (char *label, __u32 value)	241	static void maybe_print_eds (char *label, __u32 value)
242	{	242	{
243	ed_t edp = (ed_t )value;	243	ed_t edp = (ed_t )value;
244		244
245	if (value) {	245	if (value) {
246	dbg ("%s %08x", label, value);	246	dbg ("%s %08x", label, value);
247	dbg ("%08x", edp->hwINFO);	247	dbg ("%08x", edp->hwINFO);
248	dbg ("%08x", edp->hwTailP);	248	dbg ("%08x", edp->hwTailP);
249	dbg ("%08x", edp->hwHeadP);	249	dbg ("%08x", edp->hwHeadP);
250	dbg ("%08x", edp->hwNextED);	250	dbg ("%08x", edp->hwNextED);
251	}	251	}
252	}	252	}
253		253
254	static char * hcfs2string (int state)	254	static char * hcfs2string (int state)
255	{	255	{
256	switch (state) {	256	switch (state) {
257	case OHCI_USB_RESET: return "reset";	257	case OHCI_USB_RESET: return "reset";
258	case OHCI_USB_RESUME: return "resume";	258	case OHCI_USB_RESUME: return "resume";
259	case OHCI_USB_OPER: return "operational";	259	case OHCI_USB_OPER: return "operational";
260	case OHCI_USB_SUSPEND: return "suspend";	260	case OHCI_USB_SUSPEND: return "suspend";
261	}	261	}
262	return "?";	262	return "?";
263	}	263	}
264		264
265	/* dump control and status registers */	265	/* dump control and status registers */
266	static void ohci_dump_status (ohci_t *controller)	266	static void ohci_dump_status (ohci_t *controller)
267	{	267	{
268	struct ohci_regs *regs = controller->regs;	268	struct ohci_regs *regs = controller->regs;
269	__u32 temp;	269	__u32 temp;
270		270
271	temp = readl (&regs->revision) & 0xff;	271	temp = readl (&regs->revision) & 0xff;
272	if (temp != 0x10)	272	if (temp != 0x10)
273	dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));	273	dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
274		274
275	temp = readl (&regs->control);	275	temp = readl (&regs->control);
276	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,	276	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
277	(temp & OHCI_CTRL_RWE) ? " RWE" : "",	277	(temp & OHCI_CTRL_RWE) ? " RWE" : "",
278	(temp & OHCI_CTRL_RWC) ? " RWC" : "",	278	(temp & OHCI_CTRL_RWC) ? " RWC" : "",
279	(temp & OHCI_CTRL_IR) ? " IR" : "",	279	(temp & OHCI_CTRL_IR) ? " IR" : "",
280	hcfs2string (temp & OHCI_CTRL_HCFS),	280	hcfs2string (temp & OHCI_CTRL_HCFS),
281	(temp & OHCI_CTRL_BLE) ? " BLE" : "",	281	(temp & OHCI_CTRL_BLE) ? " BLE" : "",
282	(temp & OHCI_CTRL_CLE) ? " CLE" : "",	282	(temp & OHCI_CTRL_CLE) ? " CLE" : "",
283	(temp & OHCI_CTRL_IE) ? " IE" : "",	283	(temp & OHCI_CTRL_IE) ? " IE" : "",
284	(temp & OHCI_CTRL_PLE) ? " PLE" : "",	284	(temp & OHCI_CTRL_PLE) ? " PLE" : "",
285	temp & OHCI_CTRL_CBSR	285	temp & OHCI_CTRL_CBSR
286	);	286	);
287		287
288	temp = readl (&regs->cmdstatus);	288	temp = readl (&regs->cmdstatus);
289	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,	289	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
290	(temp & OHCI_SOC) >> 16,	290	(temp & OHCI_SOC) >> 16,
291	(temp & OHCI_OCR) ? " OCR" : "",	291	(temp & OHCI_OCR) ? " OCR" : "",
292	(temp & OHCI_BLF) ? " BLF" : "",	292	(temp & OHCI_BLF) ? " BLF" : "",
293	(temp & OHCI_CLF) ? " CLF" : "",	293	(temp & OHCI_CLF) ? " CLF" : "",
294	(temp & OHCI_HCR) ? " HCR" : ""	294	(temp & OHCI_HCR) ? " HCR" : ""
295	);	295	);
296		296
297	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));	297	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
298	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));	298	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
299		299
300	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));	300	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
301		301
302	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));	302	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
303	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));	303	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
304		304
305	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));	305	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
306	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));	306	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
307		307
308	maybe_print_eds ("donehead", readl (&regs->donehead));	308	maybe_print_eds ("donehead", readl (&regs->donehead));
309	}	309	}
310		310
311	static void ohci_dump_roothub (ohci_t *controller, int verbose)	311	static void ohci_dump_roothub (ohci_t *controller, int verbose)
312	{	312	{
313	__u32 temp, ndp, i;	313	__u32 temp, ndp, i;
314		314
315	temp = roothub_a (controller);	315	temp = roothub_a (controller);
316	ndp = (temp & RH_A_NDP);	316	ndp = (temp & RH_A_NDP);
317		317
318	if (verbose) {	318	if (verbose) {
319	dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,	319	dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
320	((temp & RH_A_POTPGT) >> 24) & 0xff,	320	((temp & RH_A_POTPGT) >> 24) & 0xff,
321	(temp & RH_A_NOCP) ? " NOCP" : "",	321	(temp & RH_A_NOCP) ? " NOCP" : "",
322	(temp & RH_A_OCPM) ? " OCPM" : "",	322	(temp & RH_A_OCPM) ? " OCPM" : "",
323	(temp & RH_A_DT) ? " DT" : "",	323	(temp & RH_A_DT) ? " DT" : "",
324	(temp & RH_A_NPS) ? " NPS" : "",	324	(temp & RH_A_NPS) ? " NPS" : "",
325	(temp & RH_A_PSM) ? " PSM" : "",	325	(temp & RH_A_PSM) ? " PSM" : "",
326	ndp	326	ndp
327	);	327	);
328	temp = roothub_b (controller);	328	temp = roothub_b (controller);
329	dbg ("roothub.b: %08x PPCM=%04x DR=%04x",	329	dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
330	temp,	330	temp,
331	(temp & RH_B_PPCM) >> 16,	331	(temp & RH_B_PPCM) >> 16,
332	(temp & RH_B_DR)	332	(temp & RH_B_DR)
333	);	333	);
334	temp = roothub_status (controller);	334	temp = roothub_status (controller);
335	dbg ("roothub.status: %08x%s%s%s%s%s%s",	335	dbg ("roothub.status: %08x%s%s%s%s%s%s",
336	temp,	336	temp,
337	(temp & RH_HS_CRWE) ? " CRWE" : "",	337	(temp & RH_HS_CRWE) ? " CRWE" : "",
338	(temp & RH_HS_OCIC) ? " OCIC" : "",	338	(temp & RH_HS_OCIC) ? " OCIC" : "",
339	(temp & RH_HS_LPSC) ? " LPSC" : "",	339	(temp & RH_HS_LPSC) ? " LPSC" : "",
340	(temp & RH_HS_DRWE) ? " DRWE" : "",	340	(temp & RH_HS_DRWE) ? " DRWE" : "",
341	(temp & RH_HS_OCI) ? " OCI" : "",	341	(temp & RH_HS_OCI) ? " OCI" : "",
342	(temp & RH_HS_LPS) ? " LPS" : ""	342	(temp & RH_HS_LPS) ? " LPS" : ""
343	);	343	);
344	}	344	}
345		345
346	for (i = 0; i < ndp; i++) {	346	for (i = 0; i < ndp; i++) {
347	temp = roothub_portstatus (controller, i);	347	temp = roothub_portstatus (controller, i);
348	dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",	348	dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
349	i,	349	i,
350	temp,	350	temp,
351	(temp & RH_PS_PRSC) ? " PRSC" : "",	351	(temp & RH_PS_PRSC) ? " PRSC" : "",
352	(temp & RH_PS_OCIC) ? " OCIC" : "",	352	(temp & RH_PS_OCIC) ? " OCIC" : "",
353	(temp & RH_PS_PSSC) ? " PSSC" : "",	353	(temp & RH_PS_PSSC) ? " PSSC" : "",
354	(temp & RH_PS_PESC) ? " PESC" : "",	354	(temp & RH_PS_PESC) ? " PESC" : "",
355	(temp & RH_PS_CSC) ? " CSC" : "",	355	(temp & RH_PS_CSC) ? " CSC" : "",
356		356
357	(temp & RH_PS_LSDA) ? " LSDA" : "",	357	(temp & RH_PS_LSDA) ? " LSDA" : "",
358	(temp & RH_PS_PPS) ? " PPS" : "",	358	(temp & RH_PS_PPS) ? " PPS" : "",
359	(temp & RH_PS_PRS) ? " PRS" : "",	359	(temp & RH_PS_PRS) ? " PRS" : "",
360	(temp & RH_PS_POCI) ? " POCI" : "",	360	(temp & RH_PS_POCI) ? " POCI" : "",
361	(temp & RH_PS_PSS) ? " PSS" : "",	361	(temp & RH_PS_PSS) ? " PSS" : "",
362		362
363	(temp & RH_PS_PES) ? " PES" : "",	363	(temp & RH_PS_PES) ? " PES" : "",
364	(temp & RH_PS_CCS) ? " CCS" : ""	364	(temp & RH_PS_CCS) ? " CCS" : ""
365	);	365	);
366	}	366	}
367	}	367	}
368		368
369	static void ohci_dump (ohci_t *controller, int verbose)	369	static void ohci_dump (ohci_t *controller, int verbose)
370	{	370	{
371	dbg ("OHCI controller usb-%s state", controller->slot_name);	371	dbg ("OHCI controller usb-%s state", controller->slot_name);
372		372
373	/* dumps some of the state we know about */	373	/* dumps some of the state we know about */
374	ohci_dump_status (controller);	374	ohci_dump_status (controller);
375	if (verbose)	375	if (verbose)
376	ep_print_int_eds (controller, "hcca");	376	ep_print_int_eds (controller, "hcca");
377	dbg ("hcca frame #%04x", controller->hcca->frame_no);	377	dbg ("hcca frame #%04x", controller->hcca->frame_no);
378	ohci_dump_roothub (controller, 1);	378	ohci_dump_roothub (controller, 1);
379	}	379	}
380		380
381		381
382	#endif /* DEBUG */	382	#endif /* DEBUG */
383		383
384	/-------------------------------------------------------------------------	384	/-------------------------------------------------------------------------
385	* Interface functions (URB)	385	* Interface functions (URB)
386	-------------------------------------------------------------------------/	386	-------------------------------------------------------------------------/
387		387
388	/* get a transfer request */	388	/* get a transfer request */
389		389
390	int sohci_submit_job(struct usb_device dev, unsigned long pipe, void buffer,	390	int sohci_submit_job(struct usb_device dev, unsigned long pipe, void buffer,
391	int transfer_len, struct devrequest *setup, int interval)	391	int transfer_len, struct devrequest *setup, int interval)
392	{	392	{
393	ohci_t *ohci;	393	ohci_t *ohci;
394	ed_t * ed;	394	ed_t * ed;
395	urb_priv_t *purb_priv;	395	urb_priv_t *purb_priv;
396	int i, size = 0;	396	int i, size = 0;
397		397
398	ohci = &gohci;	398	ohci = &gohci;
399		399
400	/* when controller's hung, permit only roothub cleanup attempts	400	/* when controller's hung, permit only roothub cleanup attempts
401	* such as powering down ports */	401	* such as powering down ports */
402	if (ohci->disabled) {	402	if (ohci->disabled) {
403	err("sohci_submit_job: EPIPE");	403	err("sohci_submit_job: EPIPE");
404	return -1;	404	return -1;
405	}	405	}
406		406
407	/* if we have an unfinished URB from previous transaction let's	407	/* if we have an unfinished URB from previous transaction let's
408	* fail and scream as quickly as possible so as not to corrupt	408	* fail and scream as quickly as possible so as not to corrupt
409	* further communication */	409	* further communication */
410	if (!urb_finished) {	410	if (!urb_finished) {
411	err("sohci_submit_job: URB NOT FINISHED");	411	err("sohci_submit_job: URB NOT FINISHED");
412	return -1;	412	return -1;
413	}	413	}
414	/* we're about to begin a new transaction here so mark the URB unfinished */	414	/* we're about to begin a new transaction here so mark the URB unfinished */
415	urb_finished = 0;	415	urb_finished = 0;
416		416
417	/* every endpoint has a ed, locate and fill it */	417	/* every endpoint has a ed, locate and fill it */
418	if (!(ed = ep_add_ed (dev, pipe))) {	418	if (!(ed = ep_add_ed (dev, pipe))) {
419	err("sohci_submit_job: ENOMEM");	419	err("sohci_submit_job: ENOMEM");
420	return -1;	420	return -1;
421	}	421	}
422		422
423	/* for the private part of the URB we need the number of TDs (size) */	423	/* for the private part of the URB we need the number of TDs (size) */
424	switch (usb_pipetype (pipe)) {	424	switch (usb_pipetype (pipe)) {
425	case PIPE_BULK: /* one TD for every 4096 Byte */	425	case PIPE_BULK: /* one TD for every 4096 Byte */
426	size = (transfer_len - 1) / 4096 + 1;	426	size = (transfer_len - 1) / 4096 + 1;
427	break;	427	break;
428	case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */	428	case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
429	size = (transfer_len == 0)? 2:	429	size = (transfer_len == 0)? 2:
430	(transfer_len - 1) / 4096 + 3;	430	(transfer_len - 1) / 4096 + 3;
431	break;	431	break;
432	}	432	}
433		433
434	if (size >= (N_URB_TD - 1)) {	434	if (size >= (N_URB_TD - 1)) {
435	err("need %d TDs, only have %d", size, N_URB_TD);	435	err("need %d TDs, only have %d", size, N_URB_TD);
436	return -1;	436	return -1;
437	}	437	}
438	purb_priv = &urb_priv;	438	purb_priv = &urb_priv;
439	purb_priv->pipe = pipe;	439	purb_priv->pipe = pipe;
440		440
441	/* fill the private part of the URB */	441	/* fill the private part of the URB */
442	purb_priv->length = size;	442	purb_priv->length = size;
443	purb_priv->ed = ed;	443	purb_priv->ed = ed;
444	purb_priv->actual_length = 0;	444	purb_priv->actual_length = 0;
445		445
446	/* allocate the TDs */	446	/* allocate the TDs */
447	/* note that td[0] was allocated in ep_add_ed */	447	/* note that td[0] was allocated in ep_add_ed */
448	for (i = 0; i < size; i++) {	448	for (i = 0; i < size; i++) {
449	purb_priv->td[i] = td_alloc (dev);	449	purb_priv->td[i] = td_alloc (dev);
450	if (!purb_priv->td[i]) {	450	if (!purb_priv->td[i]) {
451	purb_priv->length = i;	451	purb_priv->length = i;
452	urb_free_priv (purb_priv);	452	urb_free_priv (purb_priv);
453	err("sohci_submit_job: ENOMEM");	453	err("sohci_submit_job: ENOMEM");
454	return -1;	454	return -1;
455	}	455	}
456	}	456	}
457		457
458	if (ed->state == ED_NEW \|\| (ed->state & ED_DEL)) {	458	if (ed->state == ED_NEW \|\| (ed->state & ED_DEL)) {
459	urb_free_priv (purb_priv);	459	urb_free_priv (purb_priv);
460	err("sohci_submit_job: EINVAL");	460	err("sohci_submit_job: EINVAL");
461	return -1;	461	return -1;
462	}	462	}
463		463
464	/* link the ed into a chain if is not already */	464	/* link the ed into a chain if is not already */
465	if (ed->state != ED_OPER)	465	if (ed->state != ED_OPER)
466	ep_link (ohci, ed);	466	ep_link (ohci, ed);
467		467
468	/* fill the TDs and link it to the ed */	468	/* fill the TDs and link it to the ed */
469	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);	469	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
470		470
471	return 0;	471	return 0;
472	}	472	}
473		473
474	/-------------------------------------------------------------------------/	474	/-------------------------------------------------------------------------/
475		475
476	#ifdef DEBUG	476	#ifdef DEBUG
477	/* tell us the current USB frame number */	477	/* tell us the current USB frame number */
478		478
479	static int sohci_get_current_frame_number (struct usb_device *usb_dev)	479	static int sohci_get_current_frame_number (struct usb_device *usb_dev)
480	{	480	{
481	ohci_t *ohci = &gohci;	481	ohci_t *ohci = &gohci;
482		482
483	return ohci_cpu_to_le16 (ohci->hcca->frame_no);	483	return ohci_cpu_to_le16 (ohci->hcca->frame_no);
484	}	484	}
485	#endif	485	#endif
486		486
487	/-------------------------------------------------------------------------	487	/-------------------------------------------------------------------------
488	* ED handling functions	488	* ED handling functions
489	-------------------------------------------------------------------------/	489	-------------------------------------------------------------------------/
490		490
491	/* link an ed into one of the HC chains */	491	/* link an ed into one of the HC chains */
492		492
493	static int ep_link (ohci_t ohci, ed_t edi)	493	static int ep_link (ohci_t ohci, ed_t edi)
494	{	494	{
495	volatile ed_t *ed = edi;	495	volatile ed_t *ed = edi;
496		496
497	ed->state = ED_OPER;	497	ed->state = ED_OPER;
498		498
499	switch (ed->type) {	499	switch (ed->type) {
500	case PIPE_CONTROL:	500	case PIPE_CONTROL:
501	ed->hwNextED = 0;	501	ed->hwNextED = 0;
502	if (ohci->ed_controltail == NULL) {	502	if (ohci->ed_controltail == NULL) {
503	writel (ed, &ohci->regs->ed_controlhead);	503	writel (ed, &ohci->regs->ed_controlhead);
504	} else {	504	} else {
505	ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);	505	ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
506	}	506	}
507	ed->ed_prev = ohci->ed_controltail;	507	ed->ed_prev = ohci->ed_controltail;
508	if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&	508	if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
509	!ohci->ed_rm_list[1] && !ohci->sleeping) {	509	!ohci->ed_rm_list[1] && !ohci->sleeping) {
510	ohci->hc_control \|= OHCI_CTRL_CLE;	510	ohci->hc_control \|= OHCI_CTRL_CLE;
511	writel (ohci->hc_control, &ohci->regs->control);	511	writel (ohci->hc_control, &ohci->regs->control);
512	}	512	}
513	ohci->ed_controltail = edi;	513	ohci->ed_controltail = edi;
514	break;	514	break;
515		515
516	case PIPE_BULK:	516	case PIPE_BULK:
517	ed->hwNextED = 0;	517	ed->hwNextED = 0;
518	if (ohci->ed_bulktail == NULL) {	518	if (ohci->ed_bulktail == NULL) {
519	writel (ed, &ohci->regs->ed_bulkhead);	519	writel (ed, &ohci->regs->ed_bulkhead);
520	} else {	520	} else {
521	ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);	521	ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
522	}	522	}
523	ed->ed_prev = ohci->ed_bulktail;	523	ed->ed_prev = ohci->ed_bulktail;
524	if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&	524	if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
525	!ohci->ed_rm_list[1] && !ohci->sleeping) {	525	!ohci->ed_rm_list[1] && !ohci->sleeping) {
526	ohci->hc_control \|= OHCI_CTRL_BLE;	526	ohci->hc_control \|= OHCI_CTRL_BLE;
527	writel (ohci->hc_control, &ohci->regs->control);	527	writel (ohci->hc_control, &ohci->regs->control);
528	}	528	}
529	ohci->ed_bulktail = edi;	529	ohci->ed_bulktail = edi;
530	break;	530	break;
531	}	531	}
532	return 0;	532	return 0;
533	}	533	}
534		534
535	/-------------------------------------------------------------------------/	535	/-------------------------------------------------------------------------/
536		536
537	/* unlink an ed from one of the HC chains.	537	/* unlink an ed from one of the HC chains.
538	* just the link to the ed is unlinked.	538	* just the link to the ed is unlinked.
539	* the link from the ed still points to another operational ed or 0	539	* the link from the ed still points to another operational ed or 0
540	* so the HC can eventually finish the processing of the unlinked ed */	540	* so the HC can eventually finish the processing of the unlinked ed */
541		541
542	static int ep_unlink (ohci_t ohci, ed_t edi)	542	static int ep_unlink (ohci_t ohci, ed_t edi)
543	{	543	{
544	volatile ed_t *ed = edi;	544	volatile ed_t *ed = edi;
545		545
546	ed->hwINFO \|= ohci_cpu_to_le32 (OHCI_ED_SKIP);	546	ed->hwINFO \|= ohci_cpu_to_le32 (OHCI_ED_SKIP);
547		547
548	switch (ed->type) {	548	switch (ed->type) {
549	case PIPE_CONTROL:	549	case PIPE_CONTROL:
550	if (ed->ed_prev == NULL) {	550	if (ed->ed_prev == NULL) {
551	if (!ed->hwNextED) {	551	if (!ed->hwNextED) {
552	ohci->hc_control &= ~OHCI_CTRL_CLE;	552	ohci->hc_control &= ~OHCI_CTRL_CLE;
553	writel (ohci->hc_control, &ohci->regs->control);	553	writel (ohci->hc_control, &ohci->regs->control);
554	}	554	}
555	writel (ohci_cpu_to_le32 (((__u32 )&ed->hwNextED)), &ohci->regs->ed_controlhead);	555	writel (ohci_cpu_to_le32 (((__u32 )&ed->hwNextED)), &ohci->regs->ed_controlhead);
556	} else {	556	} else {
557	ed->ed_prev->hwNextED = ed->hwNextED;	557	ed->ed_prev->hwNextED = ed->hwNextED;
558	}	558	}
559	if (ohci->ed_controltail == ed) {	559	if (ohci->ed_controltail == ed) {
560	ohci->ed_controltail = ed->ed_prev;	560	ohci->ed_controltail = ed->ed_prev;
561	} else {	561	} else {
562	((ed_t )ohci_cpu_to_le32 (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;	562	((ed_t )ohci_cpu_to_le32 (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
563	}	563	}
564	break;	564	break;
565		565
566	case PIPE_BULK:	566	case PIPE_BULK:
567	if (ed->ed_prev == NULL) {	567	if (ed->ed_prev == NULL) {
568	if (!ed->hwNextED) {	568	if (!ed->hwNextED) {
569	ohci->hc_control &= ~OHCI_CTRL_BLE;	569	ohci->hc_control &= ~OHCI_CTRL_BLE;
570	writel (ohci->hc_control, &ohci->regs->control);	570	writel (ohci->hc_control, &ohci->regs->control);
571	}	571	}
572	writel (ohci_cpu_to_le32 (((__u32 )&ed->hwNextED)), &ohci->regs->ed_bulkhead);	572	writel (ohci_cpu_to_le32 (((__u32 )&ed->hwNextED)), &ohci->regs->ed_bulkhead);
573	} else {	573	} else {
574	ed->ed_prev->hwNextED = ed->hwNextED;	574	ed->ed_prev->hwNextED = ed->hwNextED;
575	}	575	}
576	if (ohci->ed_bulktail == ed) {	576	if (ohci->ed_bulktail == ed) {
577	ohci->ed_bulktail = ed->ed_prev;	577	ohci->ed_bulktail = ed->ed_prev;
578	} else {	578	} else {
579	((ed_t )ohci_cpu_to_le32 (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;	579	((ed_t )ohci_cpu_to_le32 (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
580	}	580	}
581	break;	581	break;
582	}	582	}
583	ed->state = ED_UNLINK;	583	ed->state = ED_UNLINK;
584	return 0;	584	return 0;
585	}	585	}
586		586
587		587
588	/-------------------------------------------------------------------------/	588	/-------------------------------------------------------------------------/
589		589
590	/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,	590	/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
591	* but the USB stack is a little bit stateless so we do it at every transaction	591	* but the USB stack is a little bit stateless so we do it at every transaction
592	* if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK	592	* if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
593	* in all other cases the state is left unchanged	593	* in all other cases the state is left unchanged
594	* the ed info fields are setted anyway even though most of them should not change */	594	* the ed info fields are setted anyway even though most of them should not change */
595		595
596	static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)	596	static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
597	{	597	{
598	td_t *td;	598	td_t *td;
599	ed_t *ed_ret;	599	ed_t *ed_ret;
600	volatile ed_t *ed;	600	volatile ed_t *ed;
601		601
602	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) \|	602	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) \|
603	(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];	603	(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
604		604
605	if ((ed->state & ED_DEL) \|\| (ed->state & ED_URB_DEL)) {	605	if ((ed->state & ED_DEL) \|\| (ed->state & ED_URB_DEL)) {
606	err("ep_add_ed: pending delete");	606	err("ep_add_ed: pending delete");
607	/* pending delete request */	607	/* pending delete request */
608	return NULL;	608	return NULL;
609	}	609	}
610		610
611	if (ed->state == ED_NEW) {	611	if (ed->state == ED_NEW) {
612	ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */	612	ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
613	/* dummy td; end of td list for ed */	613	/* dummy td; end of td list for ed */
614	td = td_alloc (usb_dev);	614	td = td_alloc (usb_dev);
615	ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);	615	ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
616	ed->hwHeadP = ed->hwTailP;	616	ed->hwHeadP = ed->hwTailP;
617	ed->state = ED_UNLINK;	617	ed->state = ED_UNLINK;
618	ed->type = usb_pipetype (pipe);	618	ed->type = usb_pipetype (pipe);
619	ohci_dev.ed_cnt++;	619	ohci_dev.ed_cnt++;
620	}	620	}
621		621
622	ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)	622	ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
623	\| usb_pipeendpoint (pipe) << 7	623	\| usb_pipeendpoint (pipe) << 7
624	\| (usb_pipeisoc (pipe)? 0x8000: 0)	624	\| (usb_pipeisoc (pipe)? 0x8000: 0)
625	\| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))	625	\| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
626	\| usb_pipeslow (pipe) << 13	626	\| usb_pipeslow (pipe) << 13
627	\| usb_maxpacket (usb_dev, pipe) << 16);	627	\| usb_maxpacket (usb_dev, pipe) << 16);
628		628
629	return ed_ret;	629	return ed_ret;
630	}	630	}
631		631
632	/-------------------------------------------------------------------------	632	/-------------------------------------------------------------------------
633	* TD handling functions	633	* TD handling functions
634	-------------------------------------------------------------------------/	634	-------------------------------------------------------------------------/
635		635
636	/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */	636	/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
637		637
638	static void td_fill (ohci_t *ohci, unsigned int info,	638	static void td_fill (ohci_t *ohci, unsigned int info,
639	void *data, int len,	639	void *data, int len,
640	struct usb_device dev, int index, urb_priv_t urb_priv)	640	struct usb_device dev, int index, urb_priv_t urb_priv)
641	{	641	{
642	volatile td_t td, td_pt;	642	volatile td_t td, td_pt;
643	#ifdef OHCI_FILL_TRACE	643	#ifdef OHCI_FILL_TRACE
644	int i;	644	int i;
645	#endif	645	#endif
646		646
647	if (index > urb_priv->length) {	647	if (index > urb_priv->length) {
648	err("index > length");	648	err("index > length");
649	return;	649	return;
650	}	650	}
651	/* use this td as the next dummy */	651	/* use this td as the next dummy */
652	td_pt = urb_priv->td [index];	652	td_pt = urb_priv->td [index];
653	td_pt->hwNextTD = 0;	653	td_pt->hwNextTD = 0;
654		654
655	/* fill the old dummy TD */	655	/* fill the old dummy TD */
656	td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);	656	td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
657		657
658	td->ed = urb_priv->ed;	658	td->ed = urb_priv->ed;
659	td->next_dl_td = NULL;	659	td->next_dl_td = NULL;
660	td->index = index;	660	td->index = index;
661	td->data = (__u32)data;	661	td->data = (__u32)data;
662	#ifdef OHCI_FILL_TRACE	662	#ifdef OHCI_FILL_TRACE
663	if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {	663	if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
664	for (i = 0; i < len; i++)	664	for (i = 0; i < len; i++)
665	printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);	665	printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
666	printf("\n");	666	printf("\n");
667	}	667	}
668	#endif	668	#endif
669	if (!len)	669	if (!len)
670	data = 0;	670	data = 0;
671		671
672	td->hwINFO = ohci_cpu_to_le32 (info);	672	td->hwINFO = ohci_cpu_to_le32 (info);
673	td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);	673	td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
674	if (data)	674	if (data)
675	td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));	675	td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
676	else	676	else
677	td->hwBE = 0;	677	td->hwBE = 0;
678	td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);	678	td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
679		679
680	/* append to queue */	680	/* append to queue */
681	td->ed->hwTailP = td->hwNextTD;	681	td->ed->hwTailP = td->hwNextTD;
682	}	682	}
683		683
684	/-------------------------------------------------------------------------/	684	/-------------------------------------------------------------------------/
685		685
686	/* prepare all TDs of a transfer */	686	/* prepare all TDs of a transfer */
687	static void td_submit_job (struct usb_device dev, unsigned long pipe, void buffer,	687	static void td_submit_job (struct usb_device dev, unsigned long pipe, void buffer,
688	int transfer_len, struct devrequest setup, urb_priv_t urb, int interval)	688	int transfer_len, struct devrequest setup, urb_priv_t urb, int interval)
689	{	689	{
690	ohci_t *ohci = &gohci;	690	ohci_t *ohci = &gohci;
691	int data_len = transfer_len;	691	int data_len = transfer_len;
692	void *data;	692	void *data;
693	int cnt = 0;	693	int cnt = 0;
694	__u32 info = 0;	694	__u32 info = 0;
695	unsigned int toggle = 0;	695	unsigned int toggle = 0;
696		696
697	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */	697	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
698	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {	698	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
699	toggle = TD_T_TOGGLE;	699	toggle = TD_T_TOGGLE;
700	} else {	700	} else {
701	toggle = TD_T_DATA0;	701	toggle = TD_T_DATA0;
702	usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);	702	usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
703	}	703	}
704	urb->td_cnt = 0;	704	urb->td_cnt = 0;
705	if (data_len)	705	if (data_len)
706	data = buffer;	706	data = buffer;
707	else	707	else
708	data = 0;	708	data = 0;
709		709
710	switch (usb_pipetype (pipe)) {	710	switch (usb_pipetype (pipe)) {
711	case PIPE_BULK:	711	case PIPE_BULK:
712	info = usb_pipeout (pipe)?	712	info = usb_pipeout (pipe)?
713	TD_CC \| TD_DP_OUT : TD_CC \| TD_DP_IN ;	713	TD_CC \| TD_DP_OUT : TD_CC \| TD_DP_IN ;
714	while(data_len > 4096) {	714	while(data_len > 4096) {
715	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);	715	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
716	data += 4096; data_len -= 4096; cnt++;	716	data += 4096; data_len -= 4096; cnt++;
717	}	717	}
718	info = usb_pipeout (pipe)?	718	info = usb_pipeout (pipe)?
719	TD_CC \| TD_DP_OUT : TD_CC \| TD_R \| TD_DP_IN ;	719	TD_CC \| TD_DP_OUT : TD_CC \| TD_R \| TD_DP_IN ;
720	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);	720	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
721	cnt++;	721	cnt++;
722		722
723	if (!ohci->sleeping)	723	if (!ohci->sleeping)
724	writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */	724	writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
725	break;	725	break;
726		726
727	case PIPE_CONTROL:	727	case PIPE_CONTROL:
728	info = TD_CC \| TD_DP_SETUP \| TD_T_DATA0;	728	info = TD_CC \| TD_DP_SETUP \| TD_T_DATA0;
729	td_fill (ohci, info, setup, 8, dev, cnt++, urb);	729	td_fill (ohci, info, setup, 8, dev, cnt++, urb);
730	if (data_len > 0) {	730	if (data_len > 0) {
731	info = usb_pipeout (pipe)?	731	info = usb_pipeout (pipe)?
732	TD_CC \| TD_R \| TD_DP_OUT \| TD_T_DATA1 : TD_CC \| TD_R \| TD_DP_IN \| TD_T_DATA1;	732	TD_CC \| TD_R \| TD_DP_OUT \| TD_T_DATA1 : TD_CC \| TD_R \| TD_DP_IN \| TD_T_DATA1;
733	/* NOTE: mishandles transfers >8K, some >4K */	733	/* NOTE: mishandles transfers >8K, some >4K */
734	td_fill (ohci, info, data, data_len, dev, cnt++, urb);	734	td_fill (ohci, info, data, data_len, dev, cnt++, urb);
735	}	735	}
736	info = usb_pipeout (pipe)?	736	info = usb_pipeout (pipe)?
737	TD_CC \| TD_DP_IN \| TD_T_DATA1: TD_CC \| TD_DP_OUT \| TD_T_DATA1;	737	TD_CC \| TD_DP_IN \| TD_T_DATA1: TD_CC \| TD_DP_OUT \| TD_T_DATA1;
738	td_fill (ohci, info, data, 0, dev, cnt++, urb);	738	td_fill (ohci, info, data, 0, dev, cnt++, urb);
739	if (!ohci->sleeping)	739	if (!ohci->sleeping)
740	writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */	740	writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
741	break;	741	break;
742	}	742	}
743	if (urb->length != cnt)	743	if (urb->length != cnt)
744	dbg("TD LENGTH %d != CNT %d", urb->length, cnt);	744	dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
745	}	745	}
746		746
747	/-------------------------------------------------------------------------	747	/-------------------------------------------------------------------------
748	* Done List handling functions	748	* Done List handling functions
749	-------------------------------------------------------------------------/	749	-------------------------------------------------------------------------/
750		750
751		751
752	/* calculate the transfer length and update the urb */	752	/* calculate the transfer length and update the urb */
753		753
754	static void dl_transfer_length(td_t * td)	754	static void dl_transfer_length(td_t * td)
755	{	755	{
756	__u32 tdINFO, tdBE, tdCBP;	756	__u32 tdINFO, tdBE, tdCBP;
757	urb_priv_t *lurb_priv = &urb_priv;	757	urb_priv_t *lurb_priv = &urb_priv;
758		758
759	tdINFO = ohci_cpu_to_le32 (td->hwINFO);	759	tdINFO = ohci_cpu_to_le32 (td->hwINFO);
760	tdBE = ohci_cpu_to_le32 (td->hwBE);	760	tdBE = ohci_cpu_to_le32 (td->hwBE);
761	tdCBP = ohci_cpu_to_le32 (td->hwCBP);	761	tdCBP = ohci_cpu_to_le32 (td->hwCBP);
762		762
763		763
764	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&	764	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
765	((td->index == 0) \|\| (td->index == lurb_priv->length - 1)))) {	765	((td->index == 0) \|\| (td->index == lurb_priv->length - 1)))) {
766	if (tdBE != 0) {	766	if (tdBE != 0) {
767	if (td->hwCBP == 0)	767	if (td->hwCBP == 0)
768	lurb_priv->actual_length += tdBE - td->data + 1;	768	lurb_priv->actual_length += tdBE - td->data + 1;
769	else	769	else
770	lurb_priv->actual_length += tdCBP - td->data;	770	lurb_priv->actual_length += tdCBP - td->data;
771	}	771	}
772	}	772	}
773	}	773	}
774		774
775	/-------------------------------------------------------------------------/	775	/-------------------------------------------------------------------------/
776		776
777	/* replies to the request have to be on a FIFO basis so	777	/* replies to the request have to be on a FIFO basis so
778	* we reverse the reversed done-list */	778	* we reverse the reversed done-list */
779		779
780	static td_t * dl_reverse_done_list (ohci_t *ohci)	780	static td_t * dl_reverse_done_list (ohci_t *ohci)
781	{	781	{
782	__u32 td_list_hc;	782	__u32 td_list_hc;
783	td_t *td_rev = NULL;	783	td_t *td_rev = NULL;
784	td_t *td_list = NULL;	784	td_t *td_list = NULL;
785	urb_priv_t *lurb_priv = NULL;	785	urb_priv_t *lurb_priv = NULL;
786		786
787	td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;	787	td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
788	ohci->hcca->done_head = 0;	788	ohci->hcca->done_head = 0;
789		789
790	while (td_list_hc) {	790	while (td_list_hc) {
791	td_list = (td_t *)td_list_hc;	791	td_list = (td_t *)td_list_hc;
792		792
793	if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {	793	if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
794	lurb_priv = &urb_priv;	794	lurb_priv = &urb_priv;
795	dbg(" USB-error/status: %x : %p",	795	dbg(" USB-error/status: %x : %p",
796	TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);	796	TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
797	if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {	797	if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
798	if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {	798	if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
799	td_list->ed->hwHeadP =	799	td_list->ed->hwHeadP =
800	(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) \|	800	(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) \|
801	(td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));	801	(td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
802	lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;	802	lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
803	} else	803	} else
804	td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);	804	td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
805	}	805	}
806	#ifdef CONFIG_MPC5200	806	#ifdef CONFIG_MPC5200
807	td_list->hwNextTD = 0;	807	td_list->hwNextTD = 0;
808	#endif	808	#endif
809	}	809	}
810		810
811	td_list->next_dl_td = td_rev;	811	td_list->next_dl_td = td_rev;
812	td_rev = td_list;	812	td_rev = td_list;
813	td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;	813	td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
814	}	814	}
815	return td_list;	815	return td_list;
816	}	816	}
817		817
818	/-------------------------------------------------------------------------/	818	/-------------------------------------------------------------------------/
819		819
820	/* td done list */	820	/* td done list */
821	static int dl_done_list (ohci_t ohci, td_t td_list)	821	static int dl_done_list (ohci_t ohci, td_t td_list)
822	{	822	{
823	td_t *td_list_next = NULL;	823	td_t *td_list_next = NULL;
824	ed_t *ed;	824	ed_t *ed;
825	int cc = 0;	825	int cc = 0;
826	int stat = 0;	826	int stat = 0;
827	/* urb_t urb; /	827	/* urb_t urb; /
828	urb_priv_t *lurb_priv;	828	urb_priv_t *lurb_priv;
829	__u32 tdINFO, edHeadP, edTailP;	829	__u32 tdINFO, edHeadP, edTailP;
830		830
831	while (td_list) {	831	while (td_list) {
832	td_list_next = td_list->next_dl_td;	832	td_list_next = td_list->next_dl_td;
833		833
834	lurb_priv = &urb_priv;	834	lurb_priv = &urb_priv;
835	tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);	835	tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
836		836
837	ed = td_list->ed;	837	ed = td_list->ed;
838		838
839	dl_transfer_length(td_list);	839	dl_transfer_length(td_list);
840		840
841	/* error code of transfer */	841	/* error code of transfer */
842	cc = TD_CC_GET (tdINFO);	842	cc = TD_CC_GET (tdINFO);
843	if (++(lurb_priv->td_cnt) == lurb_priv->length) {	843	if (++(lurb_priv->td_cnt) == lurb_priv->length) {
844	if ((ed->state & (ED_OPER \| ED_UNLINK))	844	if ((ed->state & (ED_OPER \| ED_UNLINK))
845	&& (lurb_priv->state != URB_DEL)) {	845	&& (lurb_priv->state != URB_DEL)) {
846	dbg("ConditionCode %#x", cc);	846	dbg("ConditionCode %#x", cc);
847	stat = cc_to_error[cc];	847	stat = cc_to_error[cc];
848	urb_finished = 1;	848	urb_finished = 1;
849	}	849	}
850	}	850	}
851		851
852	if (ed->state != ED_NEW) {	852	if (ed->state != ED_NEW) {
853	edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;	853	edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
854	edTailP = ohci_cpu_to_le32 (ed->hwTailP);	854	edTailP = ohci_cpu_to_le32 (ed->hwTailP);
855		855
856	/* unlink eds if they are not busy */	856	/* unlink eds if they are not busy */
857	if ((edHeadP == edTailP) && (ed->state == ED_OPER))	857	if ((edHeadP == edTailP) && (ed->state == ED_OPER))
858	ep_unlink (ohci, ed);	858	ep_unlink (ohci, ed);
859	}	859	}
860		860
861	td_list = td_list_next;	861	td_list = td_list_next;
862	}	862	}
863	return stat;	863	return stat;
864	}	864	}
865		865
866	/-------------------------------------------------------------------------	866	/-------------------------------------------------------------------------
867	* Virtual Root Hub	867	* Virtual Root Hub
868	-------------------------------------------------------------------------/	868	-------------------------------------------------------------------------/
869		869
870	/* Device descriptor */	870	/* Device descriptor */
871	static __u8 root_hub_dev_des[] =	871	static __u8 root_hub_dev_des[] =
872	{	872	{
873	0x12, /* __u8 bLength; */	873	0x12, /* __u8 bLength; */
874	0x01, /* __u8 bDescriptorType; Device */	874	0x01, /* __u8 bDescriptorType; Device */
875	0x10, /* __u16 bcdUSB; v1.1 */	875	0x10, /* __u16 bcdUSB; v1.1 */
876	0x01,	876	0x01,
877	0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */	877	0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
878	0x00, /* __u8 bDeviceSubClass; */	878	0x00, /* __u8 bDeviceSubClass; */
879	0x00, /* __u8 bDeviceProtocol; */	879	0x00, /* __u8 bDeviceProtocol; */
880	0x08, /* __u8 bMaxPacketSize0; 8 Bytes */	880	0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
881	0x00, /* __u16 idVendor; */	881	0x00, /* __u16 idVendor; */
882	0x00,	882	0x00,
883	0x00, /* __u16 idProduct; */	883	0x00, /* __u16 idProduct; */
884	0x00,	884	0x00,
885	0x00, /* __u16 bcdDevice; */	885	0x00, /* __u16 bcdDevice; */
886	0x00,	886	0x00,
887	0x00, /* __u8 iManufacturer; */	887	0x00, /* __u8 iManufacturer; */
888	0x01, /* __u8 iProduct; */	888	0x01, /* __u8 iProduct; */
889	0x00, /* __u8 iSerialNumber; */	889	0x00, /* __u8 iSerialNumber; */
890	0x01 /* __u8 bNumConfigurations; */	890	0x01 /* __u8 bNumConfigurations; */
891	};	891	};
892		892
893		893
894	/* Configuration descriptor */	894	/* Configuration descriptor */
895	static __u8 root_hub_config_des[] =	895	static __u8 root_hub_config_des[] =
896	{	896	{
897	0x09, /* __u8 bLength; */	897	0x09, /* __u8 bLength; */
898	0x02, /* __u8 bDescriptorType; Configuration */	898	0x02, /* __u8 bDescriptorType; Configuration */
899	0x19, /* __u16 wTotalLength; */	899	0x19, /* __u16 wTotalLength; */
900	0x00,	900	0x00,
901	0x01, /* __u8 bNumInterfaces; */	901	0x01, /* __u8 bNumInterfaces; */
902	0x01, /* __u8 bConfigurationValue; */	902	0x01, /* __u8 bConfigurationValue; */
903	0x00, /* __u8 iConfiguration; */	903	0x00, /* __u8 iConfiguration; */
904	0x40, /* __u8 bmAttributes;	904	0x40, /* __u8 bmAttributes;
905	Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */	905	Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
906	0x00, /* __u8 MaxPower; */	906	0x00, /* __u8 MaxPower; */
907		907
908	/* interface */	908	/* interface */
909	0x09, /* __u8 if_bLength; */	909	0x09, /* __u8 if_bLength; */
910	0x04, /* __u8 if_bDescriptorType; Interface */	910	0x04, /* __u8 if_bDescriptorType; Interface */
911	0x00, /* __u8 if_bInterfaceNumber; */	911	0x00, /* __u8 if_bInterfaceNumber; */
912	0x00, /* __u8 if_bAlternateSetting; */	912	0x00, /* __u8 if_bAlternateSetting; */
913	0x01, /* __u8 if_bNumEndpoints; */	913	0x01, /* __u8 if_bNumEndpoints; */
914	0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */	914	0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
915	0x00, /* __u8 if_bInterfaceSubClass; */	915	0x00, /* __u8 if_bInterfaceSubClass; */
916	0x00, /* __u8 if_bInterfaceProtocol; */	916	0x00, /* __u8 if_bInterfaceProtocol; */
917	0x00, /* __u8 if_iInterface; */	917	0x00, /* __u8 if_iInterface; */
918		918
919	/* endpoint */	919	/* endpoint */
920	0x07, /* __u8 ep_bLength; */	920	0x07, /* __u8 ep_bLength; */
921	0x05, /* __u8 ep_bDescriptorType; Endpoint */	921	0x05, /* __u8 ep_bDescriptorType; Endpoint */
922	0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */	922	0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
923	0x03, /* __u8 ep_bmAttributes; Interrupt */	923	0x03, /* __u8 ep_bmAttributes; Interrupt */
924	0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */	924	0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
925	0x00,	925	0x00,
926	0xff /* __u8 ep_bInterval; 255 ms */	926	0xff /* __u8 ep_bInterval; 255 ms */
927	};	927	};
928		928
929	static unsigned char root_hub_str_index0[] =	929	static unsigned char root_hub_str_index0[] =
930	{	930	{
931	0x04, /* __u8 bLength; */	931	0x04, /* __u8 bLength; */
932	0x03, /* __u8 bDescriptorType; String-descriptor */	932	0x03, /* __u8 bDescriptorType; String-descriptor */
933	0x09, /* __u8 lang ID */	933	0x09, /* __u8 lang ID */
934	0x04, /* __u8 lang ID */	934	0x04, /* __u8 lang ID */
935	};	935	};
936		936
937	static unsigned char root_hub_str_index1[] =	937	static unsigned char root_hub_str_index1[] =
938	{	938	{
939	28, /* __u8 bLength; */	939	28, /* __u8 bLength; */
940	0x03, /* __u8 bDescriptorType; String-descriptor */	940	0x03, /* __u8 bDescriptorType; String-descriptor */
941	'O', /* __u8 Unicode */	941	'O', /* __u8 Unicode */
942	0, /* __u8 Unicode */	942	0, /* __u8 Unicode */
943	'H', /* __u8 Unicode */	943	'H', /* __u8 Unicode */
944	0, /* __u8 Unicode */	944	0, /* __u8 Unicode */
945	'C', /* __u8 Unicode */	945	'C', /* __u8 Unicode */
946	0, /* __u8 Unicode */	946	0, /* __u8 Unicode */
947	'I', /* __u8 Unicode */	947	'I', /* __u8 Unicode */
948	0, /* __u8 Unicode */	948	0, /* __u8 Unicode */
949	' ', /* __u8 Unicode */	949	' ', /* __u8 Unicode */
950	0, /* __u8 Unicode */	950	0, /* __u8 Unicode */
951	'R', /* __u8 Unicode */	951	'R', /* __u8 Unicode */
952	0, /* __u8 Unicode */	952	0, /* __u8 Unicode */
953	'o', /* __u8 Unicode */	953	'o', /* __u8 Unicode */
954	0, /* __u8 Unicode */	954	0, /* __u8 Unicode */
955	'o', /* __u8 Unicode */	955	'o', /* __u8 Unicode */
956	0, /* __u8 Unicode */	956	0, /* __u8 Unicode */
957	't', /* __u8 Unicode */	957	't', /* __u8 Unicode */
958	0, /* __u8 Unicode */	958	0, /* __u8 Unicode */
959	' ', /* __u8 Unicode */	959	' ', /* __u8 Unicode */
960	0, /* __u8 Unicode */	960	0, /* __u8 Unicode */
961	'H', /* __u8 Unicode */	961	'H', /* __u8 Unicode */
962	0, /* __u8 Unicode */	962	0, /* __u8 Unicode */
963	'u', /* __u8 Unicode */	963	'u', /* __u8 Unicode */
964	0, /* __u8 Unicode */	964	0, /* __u8 Unicode */
965	'b', /* __u8 Unicode */	965	'b', /* __u8 Unicode */
966	0, /* __u8 Unicode */	966	0, /* __u8 Unicode */
967	};	967	};
968		968
969	/* Hub class-specific descriptor is constructed dynamically */	969	/* Hub class-specific descriptor is constructed dynamically */
970		970
971		971
972	/-------------------------------------------------------------------------/	972	/-------------------------------------------------------------------------/
973		973
974	#define OK(x) len = (x); break	974	#define OK(x) len = (x); break
975	#ifdef DEBUG	975	#ifdef DEBUG
976	#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}	976	#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
977	#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}	977	#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
978	#else	978	#else
979	#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)	979	#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
980	#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])	980	#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
981	#endif	981	#endif
982	#define RD_RH_STAT roothub_status(&gohci)	982	#define RD_RH_STAT roothub_status(&gohci)
983	#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)	983	#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
984		984
985	/* request to virtual root hub */	985	/* request to virtual root hub */
986		986
987	int rh_check_port_status(ohci_t *controller)	987	int rh_check_port_status(ohci_t *controller)
988	{	988	{
989	__u32 temp, ndp, i;	989	__u32 temp, ndp, i;
990	int res;	990	int res;
991		991
992	res = -1;	992	res = -1;
993	temp = roothub_a (controller);	993	temp = roothub_a (controller);
994	ndp = (temp & RH_A_NDP);	994	ndp = (temp & RH_A_NDP);
995	for (i = 0; i < ndp; i++) {	995	for (i = 0; i < ndp; i++) {
996	temp = roothub_portstatus (controller, i);	996	temp = roothub_portstatus (controller, i);
997	/* check for a device disconnect */	997	/* check for a device disconnect */
998	if (((temp & (RH_PS_PESC \| RH_PS_CSC)) ==	998	if (((temp & (RH_PS_PESC \| RH_PS_CSC)) ==
999	(RH_PS_PESC \| RH_PS_CSC)) &&	999	(RH_PS_PESC \| RH_PS_CSC)) &&
1000	((temp & RH_PS_CCS) == 0)) {	1000	((temp & RH_PS_CCS) == 0)) {
1001	res = i;	1001	res = i;
1002	break;	1002	break;
1003	}	1003	}
1004	}	1004	}
1005	return res;	1005	return res;
1006	}	1006	}
1007		1007
1008	static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,	1008	static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1009	void buffer, int transfer_len, struct devrequest cmd)	1009	void buffer, int transfer_len, struct devrequest cmd)
1010	{	1010	{
1011	void * data = buffer;	1011	void * data = buffer;
1012	int leni = transfer_len;	1012	int leni = transfer_len;
1013	int len = 0;	1013	int len = 0;
1014	int stat = 0;	1014	int stat = 0;
1015	__u32 datab[4];	1015	__u32 datab[4];
1016	__u8 data_buf = (__u8 )datab;	1016	__u8 data_buf = (__u8 )datab;
1017	__u16 bmRType_bReq;	1017	__u16 bmRType_bReq;
1018	__u16 wValue;	1018	__u16 wValue;
1019	__u16 wIndex;	1019	__u16 wIndex;
1020	__u16 wLength;	1020	__u16 wLength;
1021		1021
1022	#ifdef DEBUG	1022	#ifdef DEBUG
1023	urb_priv.actual_length = 0;	1023	urb_priv.actual_length = 0;
1024	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));	1024	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1025	#endif	1025	#endif
1026	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {	1026	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1027	info("Root-Hub submit IRQ: NOT implemented");	1027	info("Root-Hub submit IRQ: NOT implemented");
1028	return 0;	1028	return 0;
1029	}	1029	}
1030		1030
1031	bmRType_bReq = cmd->requesttype \| (cmd->request << 8);	1031	bmRType_bReq = cmd->requesttype \| (cmd->request << 8);
1032	wValue = m16_swap (cmd->value);	1032	wValue = m16_swap (cmd->value);
1033	wIndex = m16_swap (cmd->index);	1033	wIndex = m16_swap (cmd->index);
1034	wLength = m16_swap (cmd->length);	1034	wLength = m16_swap (cmd->length);
1035		1035
1036	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",	1036	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1037	dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);	1037	dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1038		1038
1039	switch (bmRType_bReq) {	1039	switch (bmRType_bReq) {
1040	/* Request Destination:	1040	/* Request Destination:
1041	without flags: Device,	1041	without flags: Device,
1042	RH_INTERFACE: interface,	1042	RH_INTERFACE: interface,
1043	RH_ENDPOINT: endpoint,	1043	RH_ENDPOINT: endpoint,
1044	RH_CLASS means HUB here,	1044	RH_CLASS means HUB here,
1045	RH_OTHER \| RH_CLASS almost ever means HUB_PORT here	1045	RH_OTHER \| RH_CLASS almost ever means HUB_PORT here
1046	*/	1046	*/
1047		1047
1048	case RH_GET_STATUS:	1048	case RH_GET_STATUS:
1049	(__u16 ) data_buf = m16_swap (1); OK (2);	1049	(__u16 ) data_buf = m16_swap (1); OK (2);
1050	case RH_GET_STATUS \| RH_INTERFACE:	1050	case RH_GET_STATUS \| RH_INTERFACE:
1051	(__u16 ) data_buf = m16_swap (0); OK (2);	1051	(__u16 ) data_buf = m16_swap (0); OK (2);
1052	case RH_GET_STATUS \| RH_ENDPOINT:	1052	case RH_GET_STATUS \| RH_ENDPOINT:
1053	(__u16 ) data_buf = m16_swap (0); OK (2);	1053	(__u16 ) data_buf = m16_swap (0); OK (2);
1054	case RH_GET_STATUS \| RH_CLASS:	1054	case RH_GET_STATUS \| RH_CLASS:
1055	(__u32 ) data_buf = m32_swap (	1055	(__u32 ) data_buf = m32_swap (
1056	RD_RH_STAT & ~(RH_HS_CRWE \| RH_HS_DRWE));	1056	RD_RH_STAT & ~(RH_HS_CRWE \| RH_HS_DRWE));
1057	OK (4);	1057	OK (4);
1058	case RH_GET_STATUS \| RH_OTHER \| RH_CLASS:	1058	case RH_GET_STATUS \| RH_OTHER \| RH_CLASS:
1059	(__u32 ) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);	1059	(__u32 ) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
1060		1060
1061	case RH_CLEAR_FEATURE \| RH_ENDPOINT:	1061	case RH_CLEAR_FEATURE \| RH_ENDPOINT:
1062	switch (wValue) {	1062	switch (wValue) {
1063	case (RH_ENDPOINT_STALL): OK (0);	1063	case (RH_ENDPOINT_STALL): OK (0);
1064	}	1064	}
1065	break;	1065	break;
1066		1066
1067	case RH_CLEAR_FEATURE \| RH_CLASS:	1067	case RH_CLEAR_FEATURE \| RH_CLASS:
1068	switch (wValue) {	1068	switch (wValue) {
1069	case RH_C_HUB_LOCAL_POWER:	1069	case RH_C_HUB_LOCAL_POWER:
1070	OK(0);	1070	OK(0);
1071	case (RH_C_HUB_OVER_CURRENT):	1071	case (RH_C_HUB_OVER_CURRENT):
1072	WR_RH_STAT(RH_HS_OCIC); OK (0);	1072	WR_RH_STAT(RH_HS_OCIC); OK (0);
1073	}	1073	}
1074	break;	1074	break;
1075		1075
1076	case RH_CLEAR_FEATURE \| RH_OTHER \| RH_CLASS:	1076	case RH_CLEAR_FEATURE \| RH_OTHER \| RH_CLASS:
1077	switch (wValue) {	1077	switch (wValue) {
1078	case (RH_PORT_ENABLE):	1078	case (RH_PORT_ENABLE):
1079	WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);	1079	WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1080	case (RH_PORT_SUSPEND):	1080	case (RH_PORT_SUSPEND):
1081	WR_RH_PORTSTAT (RH_PS_POCI); OK (0);	1081	WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1082	case (RH_PORT_POWER):	1082	case (RH_PORT_POWER):
1083	WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);	1083	WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1084	case (RH_C_PORT_CONNECTION):	1084	case (RH_C_PORT_CONNECTION):
1085	WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);	1085	WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1086	case (RH_C_PORT_ENABLE):	1086	case (RH_C_PORT_ENABLE):
1087	WR_RH_PORTSTAT (RH_PS_PESC); OK (0);	1087	WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1088	case (RH_C_PORT_SUSPEND):	1088	case (RH_C_PORT_SUSPEND):
1089	WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);	1089	WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1090	case (RH_C_PORT_OVER_CURRENT):	1090	case (RH_C_PORT_OVER_CURRENT):
1091	WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);	1091	WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1092	case (RH_C_PORT_RESET):	1092	case (RH_C_PORT_RESET):
1093	WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);	1093	WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1094	}	1094	}
1095	break;	1095	break;
1096		1096
1097	case RH_SET_FEATURE \| RH_OTHER \| RH_CLASS:	1097	case RH_SET_FEATURE \| RH_OTHER \| RH_CLASS:
1098	switch (wValue) {	1098	switch (wValue) {
1099	case (RH_PORT_SUSPEND):	1099	case (RH_PORT_SUSPEND):
1100	WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);	1100	WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1101	case (RH_PORT_RESET): /* BUG IN HUP CODE *********/	1101	case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1102	if (RD_RH_PORTSTAT & RH_PS_CCS)	1102	if (RD_RH_PORTSTAT & RH_PS_CCS)
1103	WR_RH_PORTSTAT (RH_PS_PRS);	1103	WR_RH_PORTSTAT (RH_PS_PRS);
1104	OK (0);	1104	OK (0);
1105	case (RH_PORT_POWER):	1105	case (RH_PORT_POWER):
1106	WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);	1106	WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
1107	case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/	1107	case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1108	if (RD_RH_PORTSTAT & RH_PS_CCS)	1108	if (RD_RH_PORTSTAT & RH_PS_CCS)
1109	WR_RH_PORTSTAT (RH_PS_PES );	1109	WR_RH_PORTSTAT (RH_PS_PES );
1110	OK (0);	1110	OK (0);
1111	}	1111	}
1112	break;	1112	break;
1113		1113
1114	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);	1114	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1115		1115
1116	case RH_GET_DESCRIPTOR:	1116	case RH_GET_DESCRIPTOR:
1117	switch ((wValue & 0xff00) >> 8) {	1117	switch ((wValue & 0xff00) >> 8) {
1118	case (0x01): /* device descriptor */	1118	case (0x01): /* device descriptor */
1119	len = min_t(unsigned int,	1119	len = min_t(unsigned int,
1120	leni,	1120	leni,
1121	min_t(unsigned int,	1121	min_t(unsigned int,
1122	sizeof (root_hub_dev_des),	1122	sizeof (root_hub_dev_des),
1123	wLength));	1123	wLength));
1124	data_buf = root_hub_dev_des; OK(len);	1124	data_buf = root_hub_dev_des; OK(len);
1125	case (0x02): /* configuration descriptor */	1125	case (0x02): /* configuration descriptor */
1126	len = min_t(unsigned int,	1126	len = min_t(unsigned int,
1127	leni,	1127	leni,
1128	min_t(unsigned int,	1128	min_t(unsigned int,
1129	sizeof (root_hub_config_des),	1129	sizeof (root_hub_config_des),
1130	wLength));	1130	wLength));
1131	data_buf = root_hub_config_des; OK(len);	1131	data_buf = root_hub_config_des; OK(len);
1132	case (0x03): /* string descriptors */	1132	case (0x03): /* string descriptors */
1133	if(wValue==0x0300) {	1133	if(wValue==0x0300) {
1134	len = min_t(unsigned int,	1134	len = min_t(unsigned int,
1135	leni,	1135	leni,
1136	min_t(unsigned int,	1136	min_t(unsigned int,
1137	sizeof (root_hub_str_index0),	1137	sizeof (root_hub_str_index0),
1138	wLength));	1138	wLength));
1139	data_buf = root_hub_str_index0;	1139	data_buf = root_hub_str_index0;
1140	OK(len);	1140	OK(len);
1141	}	1141	}
1142	if(wValue==0x0301) {	1142	if(wValue==0x0301) {
1143	len = min_t(unsigned int,	1143	len = min_t(unsigned int,
1144	leni,	1144	leni,
1145	min_t(unsigned int,	1145	min_t(unsigned int,
1146	sizeof (root_hub_str_index1),	1146	sizeof (root_hub_str_index1),
1147	wLength));	1147	wLength));
1148	data_buf = root_hub_str_index1;	1148	data_buf = root_hub_str_index1;
1149	OK(len);	1149	OK(len);
1150	}	1150	}
1151	default:	1151	default:
1152	stat = USB_ST_STALLED;	1152	stat = USB_ST_STALLED;
1153	}	1153	}
1154	break;	1154	break;
1155		1155
1156	case RH_GET_DESCRIPTOR \| RH_CLASS:	1156	case RH_GET_DESCRIPTOR \| RH_CLASS:
1157	{	1157	{
1158	__u32 temp = roothub_a (&gohci);	1158	__u32 temp = roothub_a (&gohci);
1159		1159
1160	data_buf [0] = 9; /* min length; */	1160	data_buf [0] = 9; /* min length; */
1161	data_buf [1] = 0x29;	1161	data_buf [1] = 0x29;
1162	data_buf [2] = temp & RH_A_NDP;	1162	data_buf [2] = temp & RH_A_NDP;
1163	data_buf [3] = 0;	1163	data_buf [3] = 0;
1164	if (temp & RH_A_PSM) /* per-port power switching? */	1164	if (temp & RH_A_PSM) /* per-port power switching? */
1165	data_buf [3] \|= 0x1;	1165	data_buf [3] \|= 0x1;
1166	if (temp & RH_A_NOCP) /* no overcurrent reporting? */	1166	if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1167	data_buf [3] \|= 0x10;	1167	data_buf [3] \|= 0x10;
1168	else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */	1168	else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1169	data_buf [3] \|= 0x8;	1169	data_buf [3] \|= 0x8;
1170		1170
1171	/* corresponds to data_buf[4-7] */	1171	/* corresponds to data_buf[4-7] */
1172	datab [1] = 0;	1172	datab [1] = 0;
1173	data_buf [5] = (temp & RH_A_POTPGT) >> 24;	1173	data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1174	temp = roothub_b (&gohci);	1174	temp = roothub_b (&gohci);
1175	data_buf [7] = temp & RH_B_DR;	1175	data_buf [7] = temp & RH_B_DR;
1176	if (data_buf [2] < 7) {	1176	if (data_buf [2] < 7) {
1177	data_buf [8] = 0xff;	1177	data_buf [8] = 0xff;
1178	} else {	1178	} else {
1179	data_buf [0] += 2;	1179	data_buf [0] += 2;
1180	data_buf [8] = (temp & RH_B_DR) >> 8;	1180	data_buf [8] = (temp & RH_B_DR) >> 8;
1181	data_buf [10] = data_buf [9] = 0xff;	1181	data_buf [10] = data_buf [9] = 0xff;
1182	}	1182	}
1183		1183
1184	len = min_t(unsigned int, leni,	1184	len = min_t(unsigned int, leni,
1185	min_t(unsigned int, data_buf [0], wLength));	1185	min_t(unsigned int, data_buf [0], wLength));
1186	OK (len);	1186	OK (len);
1187	}	1187	}
1188		1188
1189	case RH_GET_CONFIGURATION: (__u8 ) data_buf = 0x01; OK (1);	1189	case RH_GET_CONFIGURATION: (__u8 ) data_buf = 0x01; OK (1);
1190		1190
1191	case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);	1191	case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1192		1192
1193	default:	1193	default:
1194	dbg ("unsupported root hub command");	1194	dbg ("unsupported root hub command");
1195	stat = USB_ST_STALLED;	1195	stat = USB_ST_STALLED;
1196	}	1196	}
1197		1197
1198	#ifdef DEBUG	1198	#ifdef DEBUG
1199	ohci_dump_roothub (&gohci, 1);	1199	ohci_dump_roothub (&gohci, 1);
1200	#endif	1200	#endif
1201		1201
1202	len = min_t(int, len, leni);	1202	len = min_t(int, len, leni);
1203	if (data != data_buf)	1203	if (data != data_buf)
1204	memcpy (data, data_buf, len);	1204	memcpy (data, data_buf, len);
1205	dev->act_len = len;	1205	dev->act_len = len;
1206	dev->status = stat;	1206	dev->status = stat;
1207		1207
1208	#ifdef DEBUG	1208	#ifdef DEBUG
1209	if (transfer_len)	1209	if (transfer_len)
1210	urb_priv.actual_length = transfer_len;	1210	urb_priv.actual_length = transfer_len;
1211	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/usb_pipein(pipe)/);	1211	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/usb_pipein(pipe)/);
1212	#endif	1212	#endif
1213		1213
1214	return stat;	1214	return stat;
1215	}	1215	}
1216		1216
1217	/-------------------------------------------------------------------------/	1217	/-------------------------------------------------------------------------/
1218		1218
1219	/* common code for handling submit messages - used for all but root hub */	1219	/* common code for handling submit messages - used for all but root hub */
1220	/* accesses. */	1220	/* accesses. */
1221	int submit_common_msg(struct usb_device dev, unsigned long pipe, void buffer,	1221	int submit_common_msg(struct usb_device dev, unsigned long pipe, void buffer,
1222	int transfer_len, struct devrequest *setup, int interval)	1222	int transfer_len, struct devrequest *setup, int interval)
1223	{	1223	{
1224	int stat = 0;	1224	int stat = 0;
1225	int maxsize = usb_maxpacket(dev, pipe);	1225	int maxsize = usb_maxpacket(dev, pipe);
1226	int timeout;	1226	int timeout;
1227		1227
1228	/* device pulled? Shortcut the action. */	1228	/* device pulled? Shortcut the action. */
1229	if (devgone == dev) {	1229	if (devgone == dev) {
1230	dev->status = USB_ST_CRC_ERR;	1230	dev->status = USB_ST_CRC_ERR;
1231	return 0;	1231	return 0;
1232	}	1232	}
1233		1233
1234	#ifdef DEBUG	1234	#ifdef DEBUG
1235	urb_priv.actual_length = 0;	1235	urb_priv.actual_length = 0;
1236	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));	1236	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1237	#endif	1237	#endif
1238	if (!maxsize) {	1238	if (!maxsize) {
1239	err("submit_common_message: pipesize for pipe %lx is zero",	1239	err("submit_common_message: pipesize for pipe %lx is zero",
1240	pipe);	1240	pipe);
1241	return -1;	1241	return -1;
1242	}	1242	}
1243		1243
1244	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {	1244	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1245	err("sohci_submit_job failed");	1245	err("sohci_submit_job failed");
1246	return -1;	1246	return -1;
1247	}	1247	}
1248		1248
1249	/* allow more time for a BULK device to react - some are slow */	1249	/* allow more time for a BULK device to react - some are slow */
1250	#define BULK_TO 5000 /* timeout in milliseconds */	1250	#define BULK_TO 5000 /* timeout in milliseconds */
1251	if (usb_pipetype (pipe) == PIPE_BULK)	1251	if (usb_pipetype (pipe) == PIPE_BULK)
1252	timeout = BULK_TO;	1252	timeout = BULK_TO;
1253	else	1253	else
1254	timeout = 100;	1254	timeout = 100;
1255		1255
1256	/* wait for it to complete */	1256	/* wait for it to complete */
1257	for (;;) {	1257	for (;;) {
1258	/* check whether the controller is done */	1258	/* check whether the controller is done */
1259	stat = hc_interrupt();	1259	stat = hc_interrupt();
1260	if (stat < 0) {	1260	if (stat < 0) {
1261	stat = USB_ST_CRC_ERR;	1261	stat = USB_ST_CRC_ERR;
1262	break;	1262	break;
1263	}	1263	}
1264		1264
1265	/* NOTE: since we are not interrupt driven in U-Boot and always	1265	/* NOTE: since we are not interrupt driven in U-Boot and always
1266	* handle only one URB at a time, we cannot assume the	1266	* handle only one URB at a time, we cannot assume the
1267	* transaction finished on the first successful return from	1267	* transaction finished on the first successful return from
1268	* hc_interrupt().. unless the flag for current URB is set,	1268	* hc_interrupt().. unless the flag for current URB is set,
1269	* meaning that all TD's to/from device got actually	1269	* meaning that all TD's to/from device got actually
1270	* transferred and processed. If the current URB is not	1270	* transferred and processed. If the current URB is not
1271	* finished we need to re-iterate this loop so as	1271	* finished we need to re-iterate this loop so as
1272	* hc_interrupt() gets called again as there needs to be some	1272	* hc_interrupt() gets called again as there needs to be some
1273	* more TD's to process still */	1273	* more TD's to process still */
1274	if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {	1274	if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
1275	/* 0xff is returned for an SF-interrupt */	1275	/* 0xff is returned for an SF-interrupt */
1276	break;	1276	break;
1277	}	1277	}
1278		1278
1279	if (--timeout) {	1279	if (--timeout) {
1280	wait_ms(1);	1280	wait_ms(1);
1281	if (!urb_finished)	1281	if (!urb_finished)
1282	dbg("\%");	1282	dbg("\%");
1283		1283
1284	} else {	1284	} else {
1285	err("CTL:TIMEOUT ");	1285	err("CTL:TIMEOUT ");
1286	dbg("submit_common_msg: TO status %x\n", stat);	1286	dbg("submit_common_msg: TO status %x\n", stat);
1287	stat = USB_ST_CRC_ERR;	1287	stat = USB_ST_CRC_ERR;
1288	urb_finished = 1;	1288	urb_finished = 1;
1289	break;	1289	break;
1290	}	1290	}
1291	}	1291	}
1292	#if 0	1292	#if 0
1293	/* we got an Root Hub Status Change interrupt */	1293	/* we got an Root Hub Status Change interrupt */
1294	if (got_rhsc) {	1294	if (got_rhsc) {
1295	#ifdef DEBUG	1295	#ifdef DEBUG
1296	ohci_dump_roothub (&gohci, 1);	1296	ohci_dump_roothub (&gohci, 1);
1297	#endif	1297	#endif
1298	got_rhsc = 0;	1298	got_rhsc = 0;
1299	/* abuse timeout */	1299	/* abuse timeout */
1300	timeout = rh_check_port_status(&gohci);	1300	timeout = rh_check_port_status(&gohci);
1301	if (timeout >= 0) {	1301	if (timeout >= 0) {
1302	#if 0 /* this does nothing useful, but leave it here in case that changes */	1302	#if 0 /* this does nothing useful, but leave it here in case that changes */
1303	/* the called routine adds 1 to the passed value */	1303	/* the called routine adds 1 to the passed value */
1304	usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);	1304	usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1305	#endif	1305	#endif
1306	/*	1306	/*
1307	* XXX	1307	* XXX
1308	* This is potentially dangerous because it assumes	1308	* This is potentially dangerous because it assumes
1309	* that only one device is ever plugged in!	1309	* that only one device is ever plugged in!
1310	*/	1310	*/
1311	devgone = dev;	1311	devgone = dev;
1312	}	1312	}
1313	}	1313	}
1314	#endif	1314	#endif
1315		1315
1316	dev->status = stat;	1316	dev->status = stat;
1317	dev->act_len = transfer_len;	1317	dev->act_len = transfer_len;
1318		1318
1319	#ifdef DEBUG	1319	#ifdef DEBUG
1320	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));	1320	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1321	#endif	1321	#endif
1322		1322
1323	/* free TDs in urb_priv */	1323	/* free TDs in urb_priv */
1324	urb_free_priv (&urb_priv);	1324	urb_free_priv (&urb_priv);
1325	return 0;	1325	return 0;
1326	}	1326	}
1327		1327
1328	/* submit routines called from usb.c */	1328	/* submit routines called from usb.c */
1329	int submit_bulk_msg(struct usb_device dev, unsigned long pipe, void buffer,	1329	int submit_bulk_msg(struct usb_device dev, unsigned long pipe, void buffer,
1330	int transfer_len)	1330	int transfer_len)
1331	{	1331	{
1332	info("submit_bulk_msg");	1332	info("submit_bulk_msg");
1333	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);	1333	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1334	}	1334	}
1335		1335
1336	int submit_control_msg(struct usb_device dev, unsigned long pipe, void buffer,	1336	int submit_control_msg(struct usb_device dev, unsigned long pipe, void buffer,
1337	int transfer_len, struct devrequest *setup)	1337	int transfer_len, struct devrequest *setup)
1338	{	1338	{
1339	int maxsize = usb_maxpacket(dev, pipe);	1339	int maxsize = usb_maxpacket(dev, pipe);
1340		1340
1341	info("submit_control_msg");	1341	info("submit_control_msg");
1342	#ifdef DEBUG	1342	#ifdef DEBUG
1343	urb_priv.actual_length = 0;	1343	urb_priv.actual_length = 0;
1344	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));	1344	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1345	#endif	1345	#endif
1346	if (!maxsize) {	1346	if (!maxsize) {
1347	err("submit_control_message: pipesize for pipe %lx is zero",	1347	err("submit_control_message: pipesize for pipe %lx is zero",
1348	pipe);	1348	pipe);
1349	return -1;	1349	return -1;
1350	}	1350	}
1351	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {	1351	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1352	gohci.rh.dev = dev;	1352	gohci.rh.dev = dev;
1353	/* root hub - redirect */	1353	/* root hub - redirect */
1354	return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,	1354	return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1355	setup);	1355	setup);
1356	}	1356	}
1357		1357
1358	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);	1358	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1359	}	1359	}
1360		1360
1361	int submit_int_msg(struct usb_device dev, unsigned long pipe, void buffer,	1361	int submit_int_msg(struct usb_device dev, unsigned long pipe, void buffer,
1362	int transfer_len, int interval)	1362	int transfer_len, int interval)
1363	{	1363	{
1364	info("submit_int_msg");	1364	info("submit_int_msg");
1365	return -1;	1365	return -1;
1366	}	1366	}
1367		1367
1368	/-------------------------------------------------------------------------	1368	/-------------------------------------------------------------------------
1369	* HC functions	1369	* HC functions
1370	-------------------------------------------------------------------------/	1370	-------------------------------------------------------------------------/
1371		1371
1372	/* reset the HC and BUS */	1372	/* reset the HC and BUS */
1373		1373
1374	static int hc_reset (ohci_t *ohci)	1374	static int hc_reset (ohci_t *ohci)
1375	{	1375	{
1376	int timeout = 30;	1376	int timeout = 30;
1377	int smm_timeout = 50; /* 0,5 sec */	1377	int smm_timeout = 50; /* 0,5 sec */
1378		1378
1379	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */	1379	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1380	writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */	1380	writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1381	info("USB HC TakeOver from SMM");	1381	info("USB HC TakeOver from SMM");
1382	while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {	1382	while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1383	wait_ms (10);	1383	wait_ms (10);
1384	if (--smm_timeout == 0) {	1384	if (--smm_timeout == 0) {
1385	err("USB HC TakeOver failed!");	1385	err("USB HC TakeOver failed!");
1386	return -1;	1386	return -1;
1387	}	1387	}
1388	}	1388	}
1389	}	1389	}
1390		1390
1391	/* Disable HC interrupts */	1391	/* Disable HC interrupts */
1392	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);	1392	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1393		1393
1394	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",	1394	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1395	ohci->slot_name,	1395	ohci->slot_name,
1396	readl (&ohci->regs->control));	1396	readl (&ohci->regs->control));
1397		1397
1398	/* Reset USB (needed by some controllers) */	1398	/* Reset USB (needed by some controllers) */
1399	ohci->hc_control = 0;	1399	ohci->hc_control = 0;
1400	writel (ohci->hc_control, &ohci->regs->control);	1400	writel (ohci->hc_control, &ohci->regs->control);
1401		1401
1402	/* HC Reset requires max 10 us delay */	1402	/* HC Reset requires max 10 us delay */
1403	writel (OHCI_HCR, &ohci->regs->cmdstatus);	1403	writel (OHCI_HCR, &ohci->regs->cmdstatus);
1404	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {	1404	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1405	if (--timeout == 0) {	1405	if (--timeout == 0) {
1406	err("USB HC reset timed out!");	1406	err("USB HC reset timed out!");
1407	return -1;	1407	return -1;
1408	}	1408	}
1409	udelay (1);	1409	udelay (1);
1410	}	1410	}
1411	return 0;	1411	return 0;
1412	}	1412	}
1413		1413
1414	/-------------------------------------------------------------------------/	1414	/-------------------------------------------------------------------------/
1415		1415
1416	/* Start an OHCI controller, set the BUS operational	1416	/* Start an OHCI controller, set the BUS operational
1417	* enable interrupts	1417	* enable interrupts
1418	* connect the virtual root hub */	1418	* connect the virtual root hub */
1419		1419
1420	static int hc_start (ohci_t * ohci)	1420	static int hc_start (ohci_t * ohci)
1421	{	1421	{
1422	__u32 mask;	1422	__u32 mask;
1423	unsigned int fminterval;	1423	unsigned int fminterval;
1424		1424
1425	ohci->disabled = 1;	1425	ohci->disabled = 1;
1426		1426
1427	/* Tell the controller where the control and bulk lists are	1427	/* Tell the controller where the control and bulk lists are
1428	* The lists are empty now. */	1428	* The lists are empty now. */
1429		1429
1430	writel (0, &ohci->regs->ed_controlhead);	1430	writel (0, &ohci->regs->ed_controlhead);
1431	writel (0, &ohci->regs->ed_bulkhead);	1431	writel (0, &ohci->regs->ed_bulkhead);
1432		1432
1433	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */	1433	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1434		1434
1435	fminterval = 0x2edf;	1435	fminterval = 0x2edf;
1436	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);	1436	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1437	fminterval \|= ((((fminterval - 210) * 6) / 7) << 16);	1437	fminterval \|= ((((fminterval - 210) * 6) / 7) << 16);
1438	writel (fminterval, &ohci->regs->fminterval);	1438	writel (fminterval, &ohci->regs->fminterval);
1439	writel (0x628, &ohci->regs->lsthresh);	1439	writel (0x628, &ohci->regs->lsthresh);
1440		1440
1441	/* start controller operations */	1441	/* start controller operations */
1442	ohci->hc_control = OHCI_CONTROL_INIT \| OHCI_USB_OPER;	1442	ohci->hc_control = OHCI_CONTROL_INIT \| OHCI_USB_OPER;
1443	ohci->disabled = 0;	1443	ohci->disabled = 0;
1444	writel (ohci->hc_control, &ohci->regs->control);	1444	writel (ohci->hc_control, &ohci->regs->control);
1445		1445
1446	/* disable all interrupts */	1446	/* disable all interrupts */
1447	mask = (OHCI_INTR_SO \| OHCI_INTR_WDH \| OHCI_INTR_SF \| OHCI_INTR_RD \|	1447	mask = (OHCI_INTR_SO \| OHCI_INTR_WDH \| OHCI_INTR_SF \| OHCI_INTR_RD \|
1448	OHCI_INTR_UE \| OHCI_INTR_FNO \| OHCI_INTR_RHSC \|	1448	OHCI_INTR_UE \| OHCI_INTR_FNO \| OHCI_INTR_RHSC \|
1449	OHCI_INTR_OC \| OHCI_INTR_MIE);	1449	OHCI_INTR_OC \| OHCI_INTR_MIE);
1450	writel (mask, &ohci->regs->intrdisable);	1450	writel (mask, &ohci->regs->intrdisable);
1451	/* clear all interrupts */	1451	/* clear all interrupts */
1452	mask &= ~OHCI_INTR_MIE;	1452	mask &= ~OHCI_INTR_MIE;
1453	writel (mask, &ohci->regs->intrstatus);	1453	writel (mask, &ohci->regs->intrstatus);
1454	/* Choose the interrupts we care about now - but w/o MIE */	1454	/* Choose the interrupts we care about now - but w/o MIE */
1455	mask = OHCI_INTR_RHSC \| OHCI_INTR_UE \| OHCI_INTR_WDH \| OHCI_INTR_SO;	1455	mask = OHCI_INTR_RHSC \| OHCI_INTR_UE \| OHCI_INTR_WDH \| OHCI_INTR_SO;
1456	writel (mask, &ohci->regs->intrenable);	1456	writel (mask, &ohci->regs->intrenable);
1457		1457
1458	#ifdef OHCI_USE_NPS	1458	#ifdef OHCI_USE_NPS
1459	/* required for AMD-756 and some Mac platforms */	1459	/* required for AMD-756 and some Mac platforms */
1460	writel ((roothub_a (ohci) \| RH_A_NPS) & ~RH_A_PSM,	1460	writel ((roothub_a (ohci) \| RH_A_NPS) & ~RH_A_PSM,
1461	&ohci->regs->roothub.a);	1461	&ohci->regs->roothub.a);
1462	writel (RH_HS_LPSC, &ohci->regs->roothub.status);	1462	writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1463	#endif /* OHCI_USE_NPS */	1463	#endif /* OHCI_USE_NPS */
1464		1464
1465	#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})	1465	#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1466	/* POTPGT delay is bits 24-31, in 2 ms units. */	1466	/* POTPGT delay is bits 24-31, in 2 ms units. */
1467	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);	1467	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1468		1468
1469	/* connect the virtual root hub */	1469	/* connect the virtual root hub */
1470	ohci->rh.devnum = 0;	1470	ohci->rh.devnum = 0;
1471		1471
1472	return 0;	1472	return 0;
1473	}	1473	}
1474		1474
1475	/-------------------------------------------------------------------------/	1475	/-------------------------------------------------------------------------/
1476		1476
1477	/* an interrupt happens */	1477	/* an interrupt happens */
1478		1478
1479	static int	1479	static int
1480	hc_interrupt (void)	1480	hc_interrupt (void)
1481	{	1481	{
1482	ohci_t *ohci = &gohci;	1482	ohci_t *ohci = &gohci;
1483	struct ohci_regs *regs = ohci->regs;	1483	struct ohci_regs *regs = ohci->regs;
1484	int ints;	1484	int ints;
1485	int stat = -1;	1485	int stat = -1;
1486		1486
1487	if ((ohci->hcca->done_head != 0) &&	1487	if ((ohci->hcca->done_head != 0) &&
1488	!(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {	1488	!(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
1489		1489
1490	ints = OHCI_INTR_WDH;	1490	ints = OHCI_INTR_WDH;
1491		1491
1492	} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {	1492	} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
1493	ohci->disabled++;	1493	ohci->disabled++;
1494	err ("%s device removed!", ohci->slot_name);	1494	err ("%s device removed!", ohci->slot_name);
1495	return -1;	1495	return -1;
1496		1496
1497	} else if ((ints &= readl (&regs->intrenable)) == 0) {	1497	} else if ((ints &= readl (&regs->intrenable)) == 0) {
1498	dbg("hc_interrupt: returning..\n");	1498	dbg("hc_interrupt: returning..\n");
1499	return 0xff;	1499	return 0xff;
1500	}	1500	}
1501		1501
1502	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */	1502	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1503		1503
1504	if (ints & OHCI_INTR_RHSC) {	1504	if (ints & OHCI_INTR_RHSC) {
1505	got_rhsc = 1;	1505	got_rhsc = 1;
1506	stat = 0xff;	1506	stat = 0xff;
1507	}	1507	}
1508		1508
1509	if (ints & OHCI_INTR_UE) {	1509	if (ints & OHCI_INTR_UE) {
1510	ohci->disabled++;	1510	ohci->disabled++;
1511	err ("OHCI Unrecoverable Error, controller usb-%s disabled",	1511	err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1512	ohci->slot_name);	1512	ohci->slot_name);
1513	/* e.g. due to PCI Master/Target Abort */	1513	/* e.g. due to PCI Master/Target Abort */
1514		1514
1515	#ifdef DEBUG	1515	#ifdef DEBUG
1516	ohci_dump (ohci, 1);	1516	ohci_dump (ohci, 1);
1517	#endif	1517	#endif
1518	/* FIXME: be optimistic, hope that bug won't repeat often. */	1518	/* FIXME: be optimistic, hope that bug won't repeat often. */
1519	/* Make some non-interrupt context restart the controller. */	1519	/* Make some non-interrupt context restart the controller. */
1520	/* Count and limit the retries though; either hardware or */	1520	/* Count and limit the retries though; either hardware or */
1521	/* software errors can go forever... */	1521	/* software errors can go forever... */
1522	hc_reset (ohci);	1522	hc_reset (ohci);
1523	return -1;	1523	return -1;
1524	}	1524	}
1525		1525
1526	if (ints & OHCI_INTR_WDH) {	1526	if (ints & OHCI_INTR_WDH) {
1527	writel (OHCI_INTR_WDH, &regs->intrdisable);	1527	writel (OHCI_INTR_WDH, &regs->intrdisable);
1528	stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));	1528	stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1529	writel (OHCI_INTR_WDH, &regs->intrenable);	1529	writel (OHCI_INTR_WDH, &regs->intrenable);
1530	}	1530	}
1531		1531
1532	if (ints & OHCI_INTR_SO) {	1532	if (ints & OHCI_INTR_SO) {
1533	dbg("USB Schedule overrun\n");	1533	dbg("USB Schedule overrun\n");
1534	writel (OHCI_INTR_SO, &regs->intrenable);	1534	writel (OHCI_INTR_SO, &regs->intrenable);
1535	stat = -1;	1535	stat = -1;
1536	}	1536	}
1537		1537
1538	/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */	1538	/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1539	if (ints & OHCI_INTR_SF) {	1539	if (ints & OHCI_INTR_SF) {
1540	unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;	1540	unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
1541	wait_ms(1);	1541	wait_ms(1);
1542	writel (OHCI_INTR_SF, &regs->intrdisable);	1542	writel (OHCI_INTR_SF, &regs->intrdisable);
1543	if (ohci->ed_rm_list[frame] != NULL)	1543	if (ohci->ed_rm_list[frame] != NULL)
1544	writel (OHCI_INTR_SF, &regs->intrenable);	1544	writel (OHCI_INTR_SF, &regs->intrenable);
1545	stat = 0xff;	1545	stat = 0xff;
1546	}	1546	}
1547		1547
1548	writel (ints, &regs->intrstatus);	1548	writel (ints, &regs->intrstatus);
1549	return stat;	1549	return stat;
1550	}	1550	}
1551		1551
1552	/-------------------------------------------------------------------------/	1552	/-------------------------------------------------------------------------/
1553		1553
1554	/-------------------------------------------------------------------------/	1554	/-------------------------------------------------------------------------/
1555		1555
1556	/* De-allocate all resources.. */	1556	/* De-allocate all resources.. */
1557		1557
1558	static void hc_release_ohci (ohci_t *ohci)	1558	static void hc_release_ohci (ohci_t *ohci)
1559	{	1559	{
1560	dbg ("USB HC release ohci usb-%s", ohci->slot_name);	1560	dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1561		1561
1562	if (!ohci->disabled)	1562	if (!ohci->disabled)
1563	hc_reset (ohci);	1563	hc_reset (ohci);
1564	}	1564	}
1565		1565
1566	/-------------------------------------------------------------------------/	1566	/-------------------------------------------------------------------------/
1567		1567
1568	/*	1568	/*
1569	* low level initalisation routine, called from usb.c	1569	* low level initalisation routine, called from usb.c
1570	*/	1570	*/
1571	static char ohci_inited = 0;	1571	static char ohci_inited = 0;
1572		1572
1573	int usb_lowlevel_init(void)	1573	int usb_lowlevel_init(void)
1574	{	1574	{
1575		1575
1576	/* Set the USB Clock */	1576	/* Set the USB Clock */
1577	(vu_long )MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;	1577	(vu_long )MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
1578		1578
1579	/* remove all USB bits first before ORing in ours */	1579	/* remove all USB bits first before ORing in ours */
1580	(vu_long )MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;	1580	(vu_long )MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
1581		1581
1582	/* Activate USB port */	1582	/* Activate USB port */
1583	(vu_long )MPC5XXX_GPS_PORT_CONFIG \|= CONFIG_USB_CONFIG;	1583	(vu_long )MPC5XXX_GPS_PORT_CONFIG \|= CONFIG_USB_CONFIG;
1584		1584
1585	memset (&gohci, 0, sizeof (ohci_t));	1585	memset (&gohci, 0, sizeof (ohci_t));
1586	memset (&urb_priv, 0, sizeof (urb_priv_t));	1586	memset (&urb_priv, 0, sizeof (urb_priv_t));
1587		1587
1588	/* align the storage */	1588	/* align the storage */
1589	if ((__u32)&ghcca[0] & 0xff) {	1589	if ((__u32)&ghcca[0] & 0xff) {
1590	err("HCCA not aligned!!");	1590	err("HCCA not aligned!!");
1591	return -1;	1591	return -1;
1592	}	1592	}
1593	phcca = &ghcca[0];	1593	phcca = &ghcca[0];
1594	info("aligned ghcca %p", phcca);	1594	info("aligned ghcca %p", phcca);
1595	memset(&ohci_dev, 0, sizeof(struct ohci_device));	1595	memset(&ohci_dev, 0, sizeof(struct ohci_device));
1596	if ((__u32)&ohci_dev.ed[0] & 0x7) {	1596	if ((__u32)&ohci_dev.ed[0] & 0x7) {
1597	err("EDs not aligned!!");	1597	err("EDs not aligned!!");
1598	return -1;	1598	return -1;
1599	}	1599	}
1600	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));	1600	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1601	if ((__u32)gtd & 0x7) {	1601	if ((__u32)gtd & 0x7) {
1602	err("TDs not aligned!!");	1602	err("TDs not aligned!!");
1603	return -1;	1603	return -1;
1604	}	1604	}
1605	ptd = gtd;	1605	ptd = gtd;
1606	gohci.hcca = phcca;	1606	gohci.hcca = phcca;
1607	memset (phcca, 0, sizeof (struct ohci_hcca));	1607	memset (phcca, 0, sizeof (struct ohci_hcca));
1608		1608
1609	gohci.disabled = 1;	1609	gohci.disabled = 1;
1610	gohci.sleeping = 0;	1610	gohci.sleeping = 0;
1611	gohci.irq = -1;	1611	gohci.irq = -1;
1612	gohci.regs = (struct ohci_regs *)MPC5XXX_USB;	1612	gohci.regs = (struct ohci_regs *)MPC5XXX_USB;
1613		1613
1614	gohci.flags = 0;	1614	gohci.flags = 0;
1615	gohci.slot_name = "mpc5200";	1615	gohci.slot_name = "mpc5200";
1616		1616
1617	if (hc_reset (&gohci) < 0) {	1617	if (hc_reset (&gohci) < 0) {
1618	hc_release_ohci (&gohci);	1618	hc_release_ohci (&gohci);
1619	return -1;	1619	return -1;
1620	}	1620	}
1621		1621
1622	if (hc_start (&gohci) < 0) {	1622	if (hc_start (&gohci) < 0) {
1623	err ("can't start usb-%s", gohci.slot_name);	1623	err ("can't start usb-%s", gohci.slot_name);
1624	hc_release_ohci (&gohci);	1624	hc_release_ohci (&gohci);
1625	return -1;	1625	return -1;
1626	}	1626	}
1627		1627
1628	#ifdef DEBUG	1628	#ifdef DEBUG
1629	ohci_dump (&gohci, 1);	1629	ohci_dump (&gohci, 1);
1630	#endif	1630	#endif
1631	ohci_inited = 1;	1631	ohci_inited = 1;
1632	urb_finished = 1;	1632	urb_finished = 1;
1633		1633
1634	return 0;	1634	return 0;
1635	}	1635	}
1636		1636
1637	int usb_lowlevel_stop(void)	1637	int usb_lowlevel_stop(void)
1638	{	1638	{
1639	/* this gets called really early - before the controller has */	1639	/* this gets called really early - before the controller has */
1640	/* even been initialized! */	1640	/* even been initialized! */
1641	if (!ohci_inited)	1641	if (!ohci_inited)
1642	return 0;	1642	return 0;
1643	/* TODO release any interrupts, etc. */	1643	/* TODO release any interrupts, etc. */
1644	/* call hc_release_ohci() here ? */	1644	/* call hc_release_ohci() here ? */
1645	hc_reset (&gohci);	1645	hc_reset (&gohci);
1646	return 0;	1646	return 0;
1647	}	1647	}
1648		1648
1649	#endif /* CONFIG_USB_OHCI */	1649	#endif /* CONFIG_USB_OHCI */
1650		1650

cpu/ppc4xx/usb_ohci.c

Diff comments View file @ d00ce09

1	/*	1	/*
2	* URB OHCI HCD (Host Controller Driver) for USB on the PPC440EP.	2	* URB OHCI HCD (Host Controller Driver) for USB on the PPC440EP.
3	*	3	*
4	* (C) Copyright 2003-2004	4	* (C) Copyright 2003-2004
5	* Gary Jennejohn, DENX Software Engineering <gj@denx.de>	5	* Gary Jennejohn, DENX Software Engineering <gj@denx.de>
6	*	6	*
7	* (C) Copyright 2004	7	* (C) Copyright 2004
8	* Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>	8	* Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
9	*	9	*
10	* Note: Much of this code has been derived from Linux 2.4	10	* Note: Much of this code has been derived from Linux 2.4
11	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>	11	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
12	* (C) Copyright 2000-2002 David Brownell	12	* (C) Copyright 2000-2002 David Brownell
13	*	13	*
14	* See file CREDITS for list of people who contributed to this	14	* See file CREDITS for list of people who contributed to this
15	* project.	15	* project.
16	*	16	*
17	* This program is free software; you can redistribute it and/or	17	* This program is free software; you can redistribute it and/or
18	* modify it under the terms of the GNU General Public License as	18	* modify it under the terms of the GNU General Public License as
19	* published by the Free Software Foundation; either version 2 of	19	* published by the Free Software Foundation; either version 2 of
20	* the License, or (at your option) any later version.	20	* the License, or (at your option) any later version.
21	*	21	*
22	* This program is distributed in the hope that it will be useful,	22	* This program is distributed in the hope that it will be useful,
23	* but WITHOUT ANY WARRANTY; without even the implied warranty of	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25	* GNU General Public License for more details.	25	* GNU General Public License for more details.
26	*	26	*
27	* You should have received a copy of the GNU General Public License	27	* You should have received a copy of the GNU General Public License
28	* along with this program; if not, write to the Free Software	28	* along with this program; if not, write to the Free Software
29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30	* MA 02111-1307 USA	30	* MA 02111-1307 USA
31	*	31	*
32	*/	32	*/
33	/*	33	/*
34	* IMPORTANT NOTES	34	* IMPORTANT NOTES
35	* 1 - this driver is intended for use with USB Mass Storage Devices	35	* 1 - this driver is intended for use with USB Mass Storage Devices
36	* (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!	36	* (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
37	*/	37	*/
38		38
39	#include <common.h>	39	#include <common.h>
40		40
41	#ifdef CONFIG_USB_OHCI	41	#ifdef CONFIG_USB_OHCI
42		42
43	#include <malloc.h>	43	#include <malloc.h>
44	#include <usb.h>	44	#include <usb.h>
45	#include "usb_ohci.h"	45	#include "usb_ohci.h"
46		46
47	#include "usbdev.h"	47	#include "usbdev.h"
48		48
49	#define OHCI_USE_NPS /* force NoPowerSwitching mode */	49	#define OHCI_USE_NPS /* force NoPowerSwitching mode */
50	#undef OHCI_VERBOSE_DEBUG /* not always helpful */	50	#undef OHCI_VERBOSE_DEBUG /* not always helpful */
51	#undef DEBUG	51	#undef DEBUG
52	#undef SHOW_INFO	52	#undef SHOW_INFO
53	#undef OHCI_FILL_TRACE	53	#undef OHCI_FILL_TRACE
54		54
55	/* For initializing controller (mask in an HCFS mode too) */	55	/* For initializing controller (mask in an HCFS mode too) */
56	#define OHCI_CONTROL_INIT \	56	#define OHCI_CONTROL_INIT \
57	(OHCI_CTRL_CBSR & 0x3) \| OHCI_CTRL_IE \| OHCI_CTRL_PLE	57	(OHCI_CTRL_CBSR & 0x3) \| OHCI_CTRL_IE \| OHCI_CTRL_PLE
58		58
59	#define readl(a) (((vu_long )(a)))	59	#define readl(a) (((volatile u32 )(a)))
60	#define writel(a, b) (((vu_long )(b)) = ((vu_long)a))	60	#define writel(a, b) (((volatile u32 )(b)) = ((volatile u32)a))
61		61
62	#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })	62	#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
63		63
64	#ifdef DEBUG	64	#ifdef DEBUG
65	#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)	65	#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
66	#else	66	#else
67	#define dbg(format, arg...) do {} while(0)	67	#define dbg(format, arg...) do {} while(0)
68	#endif /* DEBUG */	68	#endif /* DEBUG */
69	#define err(format, arg...) printf("ERROR: " format "\n", ## arg)	69	#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
70	#ifdef SHOW_INFO	70	#ifdef SHOW_INFO
71	#define info(format, arg...) printf("INFO: " format "\n", ## arg)	71	#define info(format, arg...) printf("INFO: " format "\n", ## arg)
72	#else	72	#else
73	#define info(format, arg...) do {} while(0)	73	#define info(format, arg...) do {} while(0)
74	#endif	74	#endif
75		75
76	#define m16_swap(x) swap_16(x)	76	#define m16_swap(x) swap_16(x)
77	#define m32_swap(x) swap_32(x)	77	#define m32_swap(x) swap_32(x)
78		78
79	#if defined(CONFIG_405EZ) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440EPX)	79	#if defined(CONFIG_405EZ) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440EPX)
80	#define ohci_cpu_to_le16(x) (x)	80	#define ohci_cpu_to_le16(x) (x)
81	#define ohci_cpu_to_le32(x) (x)	81	#define ohci_cpu_to_le32(x) (x)
82	#else	82	#else
83	#define ohci_cpu_to_le16(x) swap_16(x)	83	#define ohci_cpu_to_le16(x) swap_16(x)
84	#define ohci_cpu_to_le32(x) swap_32(x)	84	#define ohci_cpu_to_le32(x) swap_32(x)
85	#endif	85	#endif
86		86
87	/* global ohci_t */	87	/* global ohci_t */
88	static ohci_t gohci;	88	static ohci_t gohci;
89	/* this must be aligned to a 256 byte boundary */	89	/* this must be aligned to a 256 byte boundary */
90	struct ohci_hcca ghcca[1];	90	struct ohci_hcca ghcca[1];
91	/* a pointer to the aligned storage */	91	/* a pointer to the aligned storage */
92	struct ohci_hcca *phcca;	92	struct ohci_hcca *phcca;
93	/* this allocates EDs for all possible endpoints */	93	/* this allocates EDs for all possible endpoints */
94	struct ohci_device ohci_dev;	94	struct ohci_device ohci_dev;
95	/* urb_priv */	95	/* urb_priv */
96	urb_priv_t urb_priv;	96	urb_priv_t urb_priv;
97	/* RHSC flag */	97	/* RHSC flag */
98	int got_rhsc;	98	int got_rhsc;
99	/* device which was disconnected */	99	/* device which was disconnected */
100	struct usb_device *devgone;	100	struct usb_device *devgone;
101	/* flag guarding URB transation */	101	/* flag guarding URB transation */
102	int urb_finished = 0;	102	int urb_finished = 0;
103		103
104	/-------------------------------------------------------------------------/	104	/-------------------------------------------------------------------------/
105		105
106	/* AMD-756 (D2 rev) reports corrupt register contents in some cases.	106	/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
107	* The erratum (#4) description is incorrect. AMD's workaround waits	107	* The erratum (#4) description is incorrect. AMD's workaround waits
108	* till some bits (mostly reserved) are clear; ok for all revs.	108	* till some bits (mostly reserved) are clear; ok for all revs.
109	*/	109	*/
110	#define OHCI_QUIRK_AMD756 0xabcd	110	#define OHCI_QUIRK_AMD756 0xabcd
111	#define read_roothub(hc, register, mask) ({ \	111	#define read_roothub(hc, register, mask) ({ \
112	u32 temp = readl (&hc->regs->roothub.register); \	112	u32 temp = readl (&hc->regs->roothub.register); \
113	if (hc->flags & OHCI_QUIRK_AMD756) \	113	if (hc->flags & OHCI_QUIRK_AMD756) \
114	while (temp & mask) \	114	while (temp & mask) \
115	temp = readl (&hc->regs->roothub.register); \	115	temp = readl (&hc->regs->roothub.register); \
116	temp; })	116	temp; })
117		117
118	static u32 roothub_a (struct ohci *hc)	118	static u32 roothub_a (struct ohci *hc)
119	{ return read_roothub (hc, a, 0xfc0fe000); }	119	{ return read_roothub (hc, a, 0xfc0fe000); }
120	static inline u32 roothub_b (struct ohci *hc)	120	static inline u32 roothub_b (struct ohci *hc)
121	{ return readl (&hc->regs->roothub.b); }	121	{ return readl (&hc->regs->roothub.b); }
122	static inline u32 roothub_status (struct ohci *hc)	122	static inline u32 roothub_status (struct ohci *hc)
123	{ return readl (&hc->regs->roothub.status); }	123	{ return readl (&hc->regs->roothub.status); }
124	static u32 roothub_portstatus (struct ohci *hc, int i)	124	static u32 roothub_portstatus (struct ohci *hc, int i)
125	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }	125	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
126		126
127		127
128	/* forward declaration */	128	/* forward declaration */
129	static int hc_interrupt (void);	129	static int hc_interrupt (void);
130	static void	130	static void
131	td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,	131	td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
132	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);	132	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
133		133
134	/-------------------------------------------------------------------------	134	/-------------------------------------------------------------------------
135	* URB support functions	135	* URB support functions
136	-------------------------------------------------------------------------/	136	-------------------------------------------------------------------------/
137		137
138	/* free HCD-private data associated with this URB */	138	/* free HCD-private data associated with this URB */
139		139
140	static void urb_free_priv (urb_priv_t * urb)	140	static void urb_free_priv (urb_priv_t * urb)
141	{	141	{
142	int i;	142	int i;
143	int last;	143	int last;
144	struct td * td;	144	struct td * td;
145		145
146	last = urb->length - 1;	146	last = urb->length - 1;
147	if (last >= 0) {	147	if (last >= 0) {
148	for (i = 0; i <= last; i++) {	148	for (i = 0; i <= last; i++) {
149	td = urb->td[i];	149	td = urb->td[i];
150	if (td) {	150	if (td) {
151	td->usb_dev = NULL;	151	td->usb_dev = NULL;
152	urb->td[i] = NULL;	152	urb->td[i] = NULL;
153	}	153	}
154	}	154	}
155	}	155	}
156	}	156	}
157		157
158	/-------------------------------------------------------------------------/	158	/-------------------------------------------------------------------------/
159		159
160	#ifdef DEBUG	160	#ifdef DEBUG
161	static int sohci_get_current_frame_number (struct usb_device * dev);	161	static int sohci_get_current_frame_number (struct usb_device * dev);
162		162
163	/* debug\| print the main components of an URB	163	/* debug\| print the main components of an URB
164	* small: 0) header + data packets 1) just header */	164	* small: 0) header + data packets 1) just header */
165		165
166	static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,	166	static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
167	int transfer_len, struct devrequest * setup, char * str, int small)	167	int transfer_len, struct devrequest * setup, char * str, int small)
168	{	168	{
169	urb_priv_t * purb = &urb_priv;	169	urb_priv_t * purb = &urb_priv;
170		170
171	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",	171	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
172	str,	172	str,
173	sohci_get_current_frame_number (dev),	173	sohci_get_current_frame_number (dev),
174	usb_pipedevice (pipe),	174	usb_pipedevice (pipe),
175	usb_pipeendpoint (pipe),	175	usb_pipeendpoint (pipe),
176	usb_pipeout (pipe)? 'O': 'I',	176	usb_pipeout (pipe)? 'O': 'I',
177	usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):	177	usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
178	(usb_pipecontrol (pipe)? "CTRL": "BULK"),	178	(usb_pipecontrol (pipe)? "CTRL": "BULK"),
179	purb->actual_length,	179	purb->actual_length,
180	transfer_len, dev->status);	180	transfer_len, dev->status);
181	#ifdef OHCI_VERBOSE_DEBUG	181	#ifdef OHCI_VERBOSE_DEBUG
182	if (!small) {	182	if (!small) {
183	int i, len;	183	int i, len;
184		184
185	if (usb_pipecontrol (pipe)) {	185	if (usb_pipecontrol (pipe)) {
186	printf (__FILE__ ": cmd(8):");	186	printf (__FILE__ ": cmd(8):");
187	for (i = 0; i < 8 ; i++)	187	for (i = 0; i < 8 ; i++)
188	printf (" %02x", ((__u8 *) setup) [i]);	188	printf (" %02x", ((__u8 *) setup) [i]);
189	printf ("\n");	189	printf ("\n");
190	}	190	}
191	if (transfer_len > 0 && buffer) {	191	if (transfer_len > 0 && buffer) {
192	printf (__FILE__ ": data(%d/%d):",	192	printf (__FILE__ ": data(%d/%d):",
193	purb->actual_length,	193	purb->actual_length,
194	transfer_len);	194	transfer_len);
195	len = usb_pipeout (pipe)?	195	len = usb_pipeout (pipe)?
196	transfer_len: purb->actual_length;	196	transfer_len: purb->actual_length;
197	for (i = 0; i < 16 && i < len; i++)	197	for (i = 0; i < 16 && i < len; i++)
198	printf (" %02x", ((__u8 *) buffer) [i]);	198	printf (" %02x", ((__u8 *) buffer) [i]);
199	printf ("%s\n", i < len? "...": "");	199	printf ("%s\n", i < len? "...": "");
200	}	200	}
201	}	201	}
202	#endif	202	#endif
203	}	203	}
204		204
205	/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/	205	/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
206	void ep_print_int_eds (ohci_t ohci, char str) {	206	void ep_print_int_eds (ohci_t ohci, char str) {
207	int i, j;	207	int i, j;
208	__u32 * ed_p;	208	__u32 * ed_p;
209	for (i= 0; i < 32; i++) {	209	for (i= 0; i < 32; i++) {
210	j = 5;	210	j = 5;
211	ed_p = &(ohci->hcca->int_table [i]);	211	ed_p = &(ohci->hcca->int_table [i]);
212	if (*ed_p == 0)	212	if (*ed_p == 0)
213	continue;	213	continue;
214	printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);	214	printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
215	while (*ed_p != 0 && j--) {	215	while (*ed_p != 0 && j--) {
216	ed_t ed = (ed_t )ohci_cpu_to_le32(ed_p);	216	ed_t ed = (ed_t )ohci_cpu_to_le32(ed_p);
217	printf (" ed: %4x;", ed->hwINFO);	217	printf (" ed: %4x;", ed->hwINFO);
218	ed_p = &ed->hwNextED;	218	ed_p = &ed->hwNextED;
219	}	219	}
220	printf ("\n");	220	printf ("\n");
221	}	221	}
222	}	222	}
223		223
224	static void ohci_dump_intr_mask (char *label, __u32 mask)	224	static void ohci_dump_intr_mask (char *label, __u32 mask)
225	{	225	{
226	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",	226	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
227	label,	227	label,
228	mask,	228	mask,
229	(mask & OHCI_INTR_MIE) ? " MIE" : "",	229	(mask & OHCI_INTR_MIE) ? " MIE" : "",
230	(mask & OHCI_INTR_OC) ? " OC" : "",	230	(mask & OHCI_INTR_OC) ? " OC" : "",
231	(mask & OHCI_INTR_RHSC) ? " RHSC" : "",	231	(mask & OHCI_INTR_RHSC) ? " RHSC" : "",
232	(mask & OHCI_INTR_FNO) ? " FNO" : "",	232	(mask & OHCI_INTR_FNO) ? " FNO" : "",
233	(mask & OHCI_INTR_UE) ? " UE" : "",	233	(mask & OHCI_INTR_UE) ? " UE" : "",
234	(mask & OHCI_INTR_RD) ? " RD" : "",	234	(mask & OHCI_INTR_RD) ? " RD" : "",
235	(mask & OHCI_INTR_SF) ? " SF" : "",	235	(mask & OHCI_INTR_SF) ? " SF" : "",
236	(mask & OHCI_INTR_WDH) ? " WDH" : "",	236	(mask & OHCI_INTR_WDH) ? " WDH" : "",
237	(mask & OHCI_INTR_SO) ? " SO" : ""	237	(mask & OHCI_INTR_SO) ? " SO" : ""
238	);	238	);
239	}	239	}
240		240
241	static void maybe_print_eds (char *label, __u32 value)	241	static void maybe_print_eds (char *label, __u32 value)
242	{	242	{
243	ed_t edp = (ed_t )value;	243	ed_t edp = (ed_t )value;
244		244
245	if (value) {	245	if (value) {
246	dbg ("%s %08x", label, value);	246	dbg ("%s %08x", label, value);
247	dbg ("%08x", edp->hwINFO);	247	dbg ("%08x", edp->hwINFO);
248	dbg ("%08x", edp->hwTailP);	248	dbg ("%08x", edp->hwTailP);
249	dbg ("%08x", edp->hwHeadP);	249	dbg ("%08x", edp->hwHeadP);
250	dbg ("%08x", edp->hwNextED);	250	dbg ("%08x", edp->hwNextED);
251	}	251	}
252	}	252	}
253		253
254	static char * hcfs2string (int state)	254	static char * hcfs2string (int state)
255	{	255	{
256	switch (state) {	256	switch (state) {
257	case OHCI_USB_RESET: return "reset";	257	case OHCI_USB_RESET: return "reset";
258	case OHCI_USB_RESUME: return "resume";	258	case OHCI_USB_RESUME: return "resume";
259	case OHCI_USB_OPER: return "operational";	259	case OHCI_USB_OPER: return "operational";
260	case OHCI_USB_SUSPEND: return "suspend";	260	case OHCI_USB_SUSPEND: return "suspend";
261	}	261	}
262	return "?";	262	return "?";
263	}	263	}
264		264
265	/* dump control and status registers */	265	/* dump control and status registers */
266	static void ohci_dump_status (ohci_t *controller)	266	static void ohci_dump_status (ohci_t *controller)
267	{	267	{
268	struct ohci_regs *regs = controller->regs;	268	struct ohci_regs *regs = controller->regs;
269	__u32 temp;	269	__u32 temp;
270		270
271	temp = readl (&regs->revision) & 0xff;	271	temp = readl (&regs->revision) & 0xff;
272	if (temp != 0x10)	272	if (temp != 0x10)
273	dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));	273	dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
274		274
275	temp = readl (&regs->control);	275	temp = readl (&regs->control);
276	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,	276	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
277	(temp & OHCI_CTRL_RWE) ? " RWE" : "",	277	(temp & OHCI_CTRL_RWE) ? " RWE" : "",
278	(temp & OHCI_CTRL_RWC) ? " RWC" : "",	278	(temp & OHCI_CTRL_RWC) ? " RWC" : "",
279	(temp & OHCI_CTRL_IR) ? " IR" : "",	279	(temp & OHCI_CTRL_IR) ? " IR" : "",
280	hcfs2string (temp & OHCI_CTRL_HCFS),	280	hcfs2string (temp & OHCI_CTRL_HCFS),
281	(temp & OHCI_CTRL_BLE) ? " BLE" : "",	281	(temp & OHCI_CTRL_BLE) ? " BLE" : "",
282	(temp & OHCI_CTRL_CLE) ? " CLE" : "",	282	(temp & OHCI_CTRL_CLE) ? " CLE" : "",
283	(temp & OHCI_CTRL_IE) ? " IE" : "",	283	(temp & OHCI_CTRL_IE) ? " IE" : "",
284	(temp & OHCI_CTRL_PLE) ? " PLE" : "",	284	(temp & OHCI_CTRL_PLE) ? " PLE" : "",
285	temp & OHCI_CTRL_CBSR	285	temp & OHCI_CTRL_CBSR
286	);	286	);
287		287
288	temp = readl (&regs->cmdstatus);	288	temp = readl (&regs->cmdstatus);
289	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,	289	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
290	(temp & OHCI_SOC) >> 16,	290	(temp & OHCI_SOC) >> 16,
291	(temp & OHCI_OCR) ? " OCR" : "",	291	(temp & OHCI_OCR) ? " OCR" : "",
292	(temp & OHCI_BLF) ? " BLF" : "",	292	(temp & OHCI_BLF) ? " BLF" : "",
293	(temp & OHCI_CLF) ? " CLF" : "",	293	(temp & OHCI_CLF) ? " CLF" : "",
294	(temp & OHCI_HCR) ? " HCR" : ""	294	(temp & OHCI_HCR) ? " HCR" : ""
295	);	295	);
296		296
297	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));	297	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
298	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));	298	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
299		299
300	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));	300	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
301		301
302	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));	302	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
303	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));	303	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
304		304
305	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));	305	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
306	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));	306	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
307		307
308	maybe_print_eds ("donehead", readl (&regs->donehead));	308	maybe_print_eds ("donehead", readl (&regs->donehead));
309	}	309	}
310		310
311	static void ohci_dump_roothub (ohci_t *controller, int verbose)	311	static void ohci_dump_roothub (ohci_t *controller, int verbose)
312	{	312	{
313	__u32 temp, ndp, i;	313	__u32 temp, ndp, i;
314		314
315	temp = roothub_a (controller);	315	temp = roothub_a (controller);
316	ndp = (temp & RH_A_NDP);	316	ndp = (temp & RH_A_NDP);
317		317
318	if (verbose) {	318	if (verbose) {
319	dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,	319	dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
320	((temp & RH_A_POTPGT) >> 24) & 0xff,	320	((temp & RH_A_POTPGT) >> 24) & 0xff,
321	(temp & RH_A_NOCP) ? " NOCP" : "",	321	(temp & RH_A_NOCP) ? " NOCP" : "",
322	(temp & RH_A_OCPM) ? " OCPM" : "",	322	(temp & RH_A_OCPM) ? " OCPM" : "",
323	(temp & RH_A_DT) ? " DT" : "",	323	(temp & RH_A_DT) ? " DT" : "",
324	(temp & RH_A_NPS) ? " NPS" : "",	324	(temp & RH_A_NPS) ? " NPS" : "",
325	(temp & RH_A_PSM) ? " PSM" : "",	325	(temp & RH_A_PSM) ? " PSM" : "",
326	ndp	326	ndp
327	);	327	);
328	temp = roothub_b (controller);	328	temp = roothub_b (controller);
329	dbg ("roothub.b: %08x PPCM=%04x DR=%04x",	329	dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
330	temp,	330	temp,
331	(temp & RH_B_PPCM) >> 16,	331	(temp & RH_B_PPCM) >> 16,
332	(temp & RH_B_DR)	332	(temp & RH_B_DR)
333	);	333	);
334	temp = roothub_status (controller);	334	temp = roothub_status (controller);
335	dbg ("roothub.status: %08x%s%s%s%s%s%s",	335	dbg ("roothub.status: %08x%s%s%s%s%s%s",
336	temp,	336	temp,
337	(temp & RH_HS_CRWE) ? " CRWE" : "",	337	(temp & RH_HS_CRWE) ? " CRWE" : "",
338	(temp & RH_HS_OCIC) ? " OCIC" : "",	338	(temp & RH_HS_OCIC) ? " OCIC" : "",
339	(temp & RH_HS_LPSC) ? " LPSC" : "",	339	(temp & RH_HS_LPSC) ? " LPSC" : "",
340	(temp & RH_HS_DRWE) ? " DRWE" : "",	340	(temp & RH_HS_DRWE) ? " DRWE" : "",
341	(temp & RH_HS_OCI) ? " OCI" : "",	341	(temp & RH_HS_OCI) ? " OCI" : "",
342	(temp & RH_HS_LPS) ? " LPS" : ""	342	(temp & RH_HS_LPS) ? " LPS" : ""
343	);	343	);
344	}	344	}
345		345
346	for (i = 0; i < ndp; i++) {	346	for (i = 0; i < ndp; i++) {
347	temp = roothub_portstatus (controller, i);	347	temp = roothub_portstatus (controller, i);
348	dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",	348	dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
349	i,	349	i,
350	temp,	350	temp,
351	(temp & RH_PS_PRSC) ? " PRSC" : "",	351	(temp & RH_PS_PRSC) ? " PRSC" : "",
352	(temp & RH_PS_OCIC) ? " OCIC" : "",	352	(temp & RH_PS_OCIC) ? " OCIC" : "",
353	(temp & RH_PS_PSSC) ? " PSSC" : "",	353	(temp & RH_PS_PSSC) ? " PSSC" : "",
354	(temp & RH_PS_PESC) ? " PESC" : "",	354	(temp & RH_PS_PESC) ? " PESC" : "",
355	(temp & RH_PS_CSC) ? " CSC" : "",	355	(temp & RH_PS_CSC) ? " CSC" : "",
356		356
357	(temp & RH_PS_LSDA) ? " LSDA" : "",	357	(temp & RH_PS_LSDA) ? " LSDA" : "",
358	(temp & RH_PS_PPS) ? " PPS" : "",	358	(temp & RH_PS_PPS) ? " PPS" : "",
359	(temp & RH_PS_PRS) ? " PRS" : "",	359	(temp & RH_PS_PRS) ? " PRS" : "",
360	(temp & RH_PS_POCI) ? " POCI" : "",	360	(temp & RH_PS_POCI) ? " POCI" : "",
361	(temp & RH_PS_PSS) ? " PSS" : "",	361	(temp & RH_PS_PSS) ? " PSS" : "",
362		362
363	(temp & RH_PS_PES) ? " PES" : "",	363	(temp & RH_PS_PES) ? " PES" : "",
364	(temp & RH_PS_CCS) ? " CCS" : ""	364	(temp & RH_PS_CCS) ? " CCS" : ""
365	);	365	);
366	}	366	}
367	}	367	}
368		368
369	static void ohci_dump (ohci_t *controller, int verbose)	369	static void ohci_dump (ohci_t *controller, int verbose)
370	{	370	{
371	dbg ("OHCI controller usb-%s state", controller->slot_name);	371	dbg ("OHCI controller usb-%s state", controller->slot_name);
372		372
373	/* dumps some of the state we know about */	373	/* dumps some of the state we know about */
374	ohci_dump_status (controller);	374	ohci_dump_status (controller);
375	if (verbose)	375	if (verbose)
376	ep_print_int_eds (controller, "hcca");	376	ep_print_int_eds (controller, "hcca");
377	dbg ("hcca frame #%04x", controller->hcca->frame_no);	377	dbg ("hcca frame #%04x", controller->hcca->frame_no);
378	ohci_dump_roothub (controller, 1);	378	ohci_dump_roothub (controller, 1);
379	}	379	}
380		380
381		381
382	#endif /* DEBUG */	382	#endif /* DEBUG */
383		383
384	/-------------------------------------------------------------------------	384	/-------------------------------------------------------------------------
385	* Interface functions (URB)	385	* Interface functions (URB)
386	-------------------------------------------------------------------------/	386	-------------------------------------------------------------------------/
387		387
388	/* get a transfer request */	388	/* get a transfer request */
389		389
390	int sohci_submit_job(struct usb_device dev, unsigned long pipe, void buffer,	390	int sohci_submit_job(struct usb_device dev, unsigned long pipe, void buffer,
391	int transfer_len, struct devrequest *setup, int interval)	391	int transfer_len, struct devrequest *setup, int interval)
392	{	392	{
393	ohci_t *ohci;	393	ohci_t *ohci;
394	ed_t * ed;	394	ed_t * ed;
395	urb_priv_t *purb_priv;	395	urb_priv_t *purb_priv;
396	int i, size = 0;	396	int i, size = 0;
397		397
398	ohci = &gohci;	398	ohci = &gohci;
399		399
400	/* when controller's hung, permit only roothub cleanup attempts	400	/* when controller's hung, permit only roothub cleanup attempts
401	* such as powering down ports */	401	* such as powering down ports */
402	if (ohci->disabled) {	402	if (ohci->disabled) {
403	err("sohci_submit_job: EPIPE");	403	err("sohci_submit_job: EPIPE");
404	return -1;	404	return -1;
405	}	405	}
406		406
407	/* if we have an unfinished URB from previous transaction let's	407	/* if we have an unfinished URB from previous transaction let's
408	* fail and scream as quickly as possible so as not to corrupt	408	* fail and scream as quickly as possible so as not to corrupt
409	* further communication */	409	* further communication */
410	if (!urb_finished) {	410	if (!urb_finished) {
411	err("sohci_submit_job: URB NOT FINISHED");	411	err("sohci_submit_job: URB NOT FINISHED");
412	return -1;	412	return -1;
413	}	413	}
414	/* we're about to begin a new transaction here so mark the URB unfinished */	414	/* we're about to begin a new transaction here so mark the URB unfinished */
415	urb_finished = 0;	415	urb_finished = 0;
416		416
417	/* every endpoint has a ed, locate and fill it */	417	/* every endpoint has a ed, locate and fill it */
418	if (!(ed = ep_add_ed (dev, pipe))) {	418	if (!(ed = ep_add_ed (dev, pipe))) {
419	err("sohci_submit_job: ENOMEM");	419	err("sohci_submit_job: ENOMEM");
420	return -1;	420	return -1;
421	}	421	}
422		422
423	/* for the private part of the URB we need the number of TDs (size) */	423	/* for the private part of the URB we need the number of TDs (size) */
424	switch (usb_pipetype (pipe)) {	424	switch (usb_pipetype (pipe)) {
425	case PIPE_BULK: /* one TD for every 4096 Byte */	425	case PIPE_BULK: /* one TD for every 4096 Byte */
426	size = (transfer_len - 1) / 4096 + 1;	426	size = (transfer_len - 1) / 4096 + 1;
427	break;	427	break;
428	case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */	428	case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
429	size = (transfer_len == 0)? 2:	429	size = (transfer_len == 0)? 2:
430	(transfer_len - 1) / 4096 + 3;	430	(transfer_len - 1) / 4096 + 3;
431	break;	431	break;
432	}	432	}
433		433
434	if (size >= (N_URB_TD - 1)) {	434	if (size >= (N_URB_TD - 1)) {
435	err("need %d TDs, only have %d", size, N_URB_TD);	435	err("need %d TDs, only have %d", size, N_URB_TD);
436	return -1;	436	return -1;
437	}	437	}
438	purb_priv = &urb_priv;	438	purb_priv = &urb_priv;
439	purb_priv->pipe = pipe;	439	purb_priv->pipe = pipe;
440		440
441	/* fill the private part of the URB */	441	/* fill the private part of the URB */
442	purb_priv->length = size;	442	purb_priv->length = size;
443	purb_priv->ed = ed;	443	purb_priv->ed = ed;
444	purb_priv->actual_length = 0;	444	purb_priv->actual_length = 0;
445		445
446	/* allocate the TDs */	446	/* allocate the TDs */
447	/* note that td[0] was allocated in ep_add_ed */	447	/* note that td[0] was allocated in ep_add_ed */
448	for (i = 0; i < size; i++) {	448	for (i = 0; i < size; i++) {
449	purb_priv->td[i] = td_alloc (dev);	449	purb_priv->td[i] = td_alloc (dev);
450	if (!purb_priv->td[i]) {	450	if (!purb_priv->td[i]) {
451	purb_priv->length = i;	451	purb_priv->length = i;
452	urb_free_priv (purb_priv);	452	urb_free_priv (purb_priv);
453	err("sohci_submit_job: ENOMEM");	453	err("sohci_submit_job: ENOMEM");
454	return -1;	454	return -1;
455	}	455	}
456	}	456	}
457		457
458	if (ed->state == ED_NEW \|\| (ed->state & ED_DEL)) {	458	if (ed->state == ED_NEW \|\| (ed->state & ED_DEL)) {
459	urb_free_priv (purb_priv);	459	urb_free_priv (purb_priv);
460	err("sohci_submit_job: EINVAL");	460	err("sohci_submit_job: EINVAL");
461	return -1;	461	return -1;
462	}	462	}
463		463
464	/* link the ed into a chain if is not already */	464	/* link the ed into a chain if is not already */
465	if (ed->state != ED_OPER)	465	if (ed->state != ED_OPER)
466	ep_link (ohci, ed);	466	ep_link (ohci, ed);
467		467
468	/* fill the TDs and link it to the ed */	468	/* fill the TDs and link it to the ed */
469	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);	469	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
470		470
471	return 0;	471	return 0;
472	}	472	}
473		473
474	/-------------------------------------------------------------------------/	474	/-------------------------------------------------------------------------/
475		475
476	#ifdef DEBUG	476	#ifdef DEBUG
477	/* tell us the current USB frame number */	477	/* tell us the current USB frame number */
478		478
479	static int sohci_get_current_frame_number (struct usb_device *usb_dev)	479	static int sohci_get_current_frame_number (struct usb_device *usb_dev)
480	{	480	{
481	ohci_t *ohci = &gohci;	481	ohci_t *ohci = &gohci;
482		482
483	return ohci_cpu_to_le16 (ohci->hcca->frame_no);	483	return ohci_cpu_to_le16 (ohci->hcca->frame_no);
484	}	484	}
485	#endif	485	#endif
486		486
487	/-------------------------------------------------------------------------	487	/-------------------------------------------------------------------------
488	* ED handling functions	488	* ED handling functions
489	-------------------------------------------------------------------------/	489	-------------------------------------------------------------------------/
490		490
491	/* link an ed into one of the HC chains */	491	/* link an ed into one of the HC chains */
492		492
493	static int ep_link (ohci_t ohci, ed_t edi)	493	static int ep_link (ohci_t ohci, ed_t edi)
494	{	494	{
495	volatile ed_t *ed = edi;	495	volatile ed_t *ed = edi;
496		496
497	ed->state = ED_OPER;	497	ed->state = ED_OPER;
498		498
499	switch (ed->type) {	499	switch (ed->type) {
500	case PIPE_CONTROL:	500	case PIPE_CONTROL:
501	ed->hwNextED = 0;	501	ed->hwNextED = 0;
502	if (ohci->ed_controltail == NULL) {	502	if (ohci->ed_controltail == NULL) {
503	writel (ed, &ohci->regs->ed_controlhead);	503	writel (ed, &ohci->regs->ed_controlhead);
504	} else {	504	} else {
505	ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);	505	ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
506	}	506	}
507	ed->ed_prev = ohci->ed_controltail;	507	ed->ed_prev = ohci->ed_controltail;
508	if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&	508	if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
509	!ohci->ed_rm_list[1] && !ohci->sleeping) {	509	!ohci->ed_rm_list[1] && !ohci->sleeping) {
510	ohci->hc_control \|= OHCI_CTRL_CLE;	510	ohci->hc_control \|= OHCI_CTRL_CLE;
511	writel (ohci->hc_control, &ohci->regs->control);	511	writel (ohci->hc_control, &ohci->regs->control);
512	}	512	}
513	ohci->ed_controltail = edi;	513	ohci->ed_controltail = edi;
514	break;	514	break;
515		515
516	case PIPE_BULK:	516	case PIPE_BULK:
517	ed->hwNextED = 0;	517	ed->hwNextED = 0;
518	if (ohci->ed_bulktail == NULL) {	518	if (ohci->ed_bulktail == NULL) {
519	writel (ed, &ohci->regs->ed_bulkhead);	519	writel (ed, &ohci->regs->ed_bulkhead);
520	} else {	520	} else {
521	ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);	521	ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
522	}	522	}
523	ed->ed_prev = ohci->ed_bulktail;	523	ed->ed_prev = ohci->ed_bulktail;
524	if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&	524	if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
525	!ohci->ed_rm_list[1] && !ohci->sleeping) {	525	!ohci->ed_rm_list[1] && !ohci->sleeping) {
526	ohci->hc_control \|= OHCI_CTRL_BLE;	526	ohci->hc_control \|= OHCI_CTRL_BLE;
527	writel (ohci->hc_control, &ohci->regs->control);	527	writel (ohci->hc_control, &ohci->regs->control);
528	}	528	}
529	ohci->ed_bulktail = edi;	529	ohci->ed_bulktail = edi;
530	break;	530	break;
531	}	531	}
532	return 0;	532	return 0;
533	}	533	}
534		534
535	/-------------------------------------------------------------------------/	535	/-------------------------------------------------------------------------/
536		536
537	/* unlink an ed from one of the HC chains.	537	/* unlink an ed from one of the HC chains.
538	* just the link to the ed is unlinked.	538	* just the link to the ed is unlinked.
539	* the link from the ed still points to another operational ed or 0	539	* the link from the ed still points to another operational ed or 0
540	* so the HC can eventually finish the processing of the unlinked ed */	540	* so the HC can eventually finish the processing of the unlinked ed */
541		541
542	static int ep_unlink (ohci_t ohci, ed_t edi)	542	static int ep_unlink (ohci_t ohci, ed_t edi)
543	{	543	{
544	volatile ed_t *ed = edi;	544	volatile ed_t *ed = edi;
545		545
546	ed->hwINFO \|= ohci_cpu_to_le32 (OHCI_ED_SKIP);	546	ed->hwINFO \|= ohci_cpu_to_le32 (OHCI_ED_SKIP);
547		547
548	switch (ed->type) {	548	switch (ed->type) {
549	case PIPE_CONTROL:	549	case PIPE_CONTROL:
550	if (ed->ed_prev == NULL) {	550	if (ed->ed_prev == NULL) {
551	if (!ed->hwNextED) {	551	if (!ed->hwNextED) {
552	ohci->hc_control &= ~OHCI_CTRL_CLE;	552	ohci->hc_control &= ~OHCI_CTRL_CLE;
553	writel (ohci->hc_control, &ohci->regs->control);	553	writel (ohci->hc_control, &ohci->regs->control);
554	}	554	}
555	writel (ohci_cpu_to_le32 (((__u32 )&ed->hwNextED)), &ohci->regs->ed_controlhead);	555	writel (ohci_cpu_to_le32 (((__u32 )&ed->hwNextED)), &ohci->regs->ed_controlhead);
556	} else {	556	} else {
557	ed->ed_prev->hwNextED = ed->hwNextED;	557	ed->ed_prev->hwNextED = ed->hwNextED;
558	}	558	}
559	if (ohci->ed_controltail == ed) {	559	if (ohci->ed_controltail == ed) {
560	ohci->ed_controltail = ed->ed_prev;	560	ohci->ed_controltail = ed->ed_prev;
561	} else {	561	} else {
562	((ed_t )ohci_cpu_to_le32 (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;	562	((ed_t )ohci_cpu_to_le32 (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
563	}	563	}
564	break;	564	break;
565		565
566	case PIPE_BULK:	566	case PIPE_BULK:
567	if (ed->ed_prev == NULL) {	567	if (ed->ed_prev == NULL) {
568	if (!ed->hwNextED) {	568	if (!ed->hwNextED) {
569	ohci->hc_control &= ~OHCI_CTRL_BLE;	569	ohci->hc_control &= ~OHCI_CTRL_BLE;
570	writel (ohci->hc_control, &ohci->regs->control);	570	writel (ohci->hc_control, &ohci->regs->control);
571	}	571	}
572	writel (ohci_cpu_to_le32 (((__u32 )&ed->hwNextED)), &ohci->regs->ed_bulkhead);	572	writel (ohci_cpu_to_le32 (((__u32 )&ed->hwNextED)), &ohci->regs->ed_bulkhead);
573	} else {	573	} else {
574	ed->ed_prev->hwNextED = ed->hwNextED;	574	ed->ed_prev->hwNextED = ed->hwNextED;
575	}	575	}
576	if (ohci->ed_bulktail == ed) {	576	if (ohci->ed_bulktail == ed) {
577	ohci->ed_bulktail = ed->ed_prev;	577	ohci->ed_bulktail = ed->ed_prev;
578	} else {	578	} else {
579	((ed_t )ohci_cpu_to_le32 (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;	579	((ed_t )ohci_cpu_to_le32 (((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
580	}	580	}
581	break;	581	break;
582	}	582	}
583	ed->state = ED_UNLINK;	583	ed->state = ED_UNLINK;
584	return 0;	584	return 0;
585	}	585	}
586		586
587		587
588	/-------------------------------------------------------------------------/	588	/-------------------------------------------------------------------------/
589		589
590	/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,	590	/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
591	* but the USB stack is a little bit stateless so we do it at every transaction	591	* but the USB stack is a little bit stateless so we do it at every transaction
592	* if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK	592	* if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
593	* in all other cases the state is left unchanged	593	* in all other cases the state is left unchanged
594	* the ed info fields are setted anyway even though most of them should not change */	594	* the ed info fields are setted anyway even though most of them should not change */
595		595
596	static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)	596	static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
597	{	597	{
598	td_t *td;	598	td_t *td;
599	ed_t *ed_ret;	599	ed_t *ed_ret;
600	volatile ed_t *ed;	600	volatile ed_t *ed;
601		601
602	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) \|	602	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) \|
603	(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];	603	(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
604		604
605	if ((ed->state & ED_DEL) \|\| (ed->state & ED_URB_DEL)) {	605	if ((ed->state & ED_DEL) \|\| (ed->state & ED_URB_DEL)) {
606	err("ep_add_ed: pending delete");	606	err("ep_add_ed: pending delete");
607	/* pending delete request */	607	/* pending delete request */
608	return NULL;	608	return NULL;
609	}	609	}
610		610
611	if (ed->state == ED_NEW) {	611	if (ed->state == ED_NEW) {
612	ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */	612	ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
613	/* dummy td; end of td list for ed */	613	/* dummy td; end of td list for ed */
614	td = td_alloc (usb_dev);	614	td = td_alloc (usb_dev);
615	ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);	615	ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
616	ed->hwHeadP = ed->hwTailP;	616	ed->hwHeadP = ed->hwTailP;
617	ed->state = ED_UNLINK;	617	ed->state = ED_UNLINK;
618	ed->type = usb_pipetype (pipe);	618	ed->type = usb_pipetype (pipe);
619	ohci_dev.ed_cnt++;	619	ohci_dev.ed_cnt++;
620	}	620	}
621		621
622	ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)	622	ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
623	\| usb_pipeendpoint (pipe) << 7	623	\| usb_pipeendpoint (pipe) << 7
624	\| (usb_pipeisoc (pipe)? 0x8000: 0)	624	\| (usb_pipeisoc (pipe)? 0x8000: 0)
625	\| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))	625	\| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
626	\| usb_pipeslow (pipe) << 13	626	\| usb_pipeslow (pipe) << 13
627	\| usb_maxpacket (usb_dev, pipe) << 16);	627	\| usb_maxpacket (usb_dev, pipe) << 16);
628		628
629	return ed_ret;	629	return ed_ret;
630	}	630	}
631		631
632	/-------------------------------------------------------------------------	632	/-------------------------------------------------------------------------
633	* TD handling functions	633	* TD handling functions
634	-------------------------------------------------------------------------/	634	-------------------------------------------------------------------------/
635		635
636	/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */	636	/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
637		637
638	static void td_fill (ohci_t *ohci, unsigned int info,	638	static void td_fill (ohci_t *ohci, unsigned int info,
639	void *data, int len,	639	void *data, int len,
640	struct usb_device dev, int index, urb_priv_t urb_priv)	640	struct usb_device dev, int index, urb_priv_t urb_priv)
641	{	641	{
642	volatile td_t td, td_pt;	642	volatile td_t td, td_pt;
643	#ifdef OHCI_FILL_TRACE	643	#ifdef OHCI_FILL_TRACE
644	int i;	644	int i;
645	#endif	645	#endif
646		646
647	if (index > urb_priv->length) {	647	if (index > urb_priv->length) {
648	err("index > length");	648	err("index > length");
649	return;	649	return;
650	}	650	}
651	/* use this td as the next dummy */	651	/* use this td as the next dummy */
652	td_pt = urb_priv->td [index];	652	td_pt = urb_priv->td [index];
653	td_pt->hwNextTD = 0;	653	td_pt->hwNextTD = 0;
654		654
655	/* fill the old dummy TD */	655	/* fill the old dummy TD */
656	td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);	656	td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
657		657
658	td->ed = urb_priv->ed;	658	td->ed = urb_priv->ed;
659	td->next_dl_td = NULL;	659	td->next_dl_td = NULL;
660	td->index = index;	660	td->index = index;
661	td->data = (__u32)data;	661	td->data = (__u32)data;
662	#ifdef OHCI_FILL_TRACE	662	#ifdef OHCI_FILL_TRACE
663	if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {	663	if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
664	for (i = 0; i < len; i++)	664	for (i = 0; i < len; i++)
665	printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);	665	printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
666	printf("\n");	666	printf("\n");
667	}	667	}
668	#endif	668	#endif
669	if (!len)	669	if (!len)
670	data = 0;	670	data = 0;
671		671
672	td->hwINFO = ohci_cpu_to_le32 (info);	672	td->hwINFO = ohci_cpu_to_le32 (info);
673	td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);	673	td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
674	if (data)	674	if (data)
675	td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));	675	td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
676	else	676	else
677	td->hwBE = 0;	677	td->hwBE = 0;
678	td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);	678	td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
679		679
680	/* append to queue */	680	/* append to queue */
681	td->ed->hwTailP = td->hwNextTD;	681	td->ed->hwTailP = td->hwNextTD;
682	}	682	}
683		683
684	/-------------------------------------------------------------------------/	684	/-------------------------------------------------------------------------/
685		685
686	/* prepare all TDs of a transfer */	686	/* prepare all TDs of a transfer */
687	static void td_submit_job (struct usb_device dev, unsigned long pipe, void buffer,	687	static void td_submit_job (struct usb_device dev, unsigned long pipe, void buffer,
688	int transfer_len, struct devrequest setup, urb_priv_t urb, int interval)	688	int transfer_len, struct devrequest setup, urb_priv_t urb, int interval)
689	{	689	{
690	ohci_t *ohci = &gohci;	690	ohci_t *ohci = &gohci;
691	int data_len = transfer_len;	691	int data_len = transfer_len;
692	void *data;	692	void *data;
693	int cnt = 0;	693	int cnt = 0;
694	__u32 info = 0;	694	__u32 info = 0;
695	unsigned int toggle = 0;	695	unsigned int toggle = 0;
696		696
697	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */	697	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
698	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {	698	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
699	toggle = TD_T_TOGGLE;	699	toggle = TD_T_TOGGLE;
700	} else {	700	} else {
701	toggle = TD_T_DATA0;	701	toggle = TD_T_DATA0;
702	usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);	702	usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
703	}	703	}
704	urb->td_cnt = 0;	704	urb->td_cnt = 0;
705	if (data_len)	705	if (data_len)
706	data = buffer;	706	data = buffer;
707	else	707	else
708	data = 0;	708	data = 0;
709		709
710	switch (usb_pipetype (pipe)) {	710	switch (usb_pipetype (pipe)) {
711	case PIPE_BULK:	711	case PIPE_BULK:
712	info = usb_pipeout (pipe)?	712	info = usb_pipeout (pipe)?
713	TD_CC \| TD_DP_OUT : TD_CC \| TD_DP_IN ;	713	TD_CC \| TD_DP_OUT : TD_CC \| TD_DP_IN ;
714	while(data_len > 4096) {	714	while(data_len > 4096) {
715	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);	715	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
716	data += 4096; data_len -= 4096; cnt++;	716	data += 4096; data_len -= 4096; cnt++;
717	}	717	}
718	info = usb_pipeout (pipe)?	718	info = usb_pipeout (pipe)?
719	TD_CC \| TD_DP_OUT : TD_CC \| TD_R \| TD_DP_IN ;	719	TD_CC \| TD_DP_OUT : TD_CC \| TD_R \| TD_DP_IN ;
720	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);	720	td_fill (ohci, info \| (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
721	cnt++;	721	cnt++;
722		722
723	if (!ohci->sleeping)	723	if (!ohci->sleeping)
724	writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */	724	writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
725	break;	725	break;
726		726
727	case PIPE_CONTROL:	727	case PIPE_CONTROL:
728	info = TD_CC \| TD_DP_SETUP \| TD_T_DATA0;	728	info = TD_CC \| TD_DP_SETUP \| TD_T_DATA0;
729	td_fill (ohci, info, setup, 8, dev, cnt++, urb);	729	td_fill (ohci, info, setup, 8, dev, cnt++, urb);
730	if (data_len > 0) {	730	if (data_len > 0) {
731	info = usb_pipeout (pipe)?	731	info = usb_pipeout (pipe)?
732	TD_CC \| TD_R \| TD_DP_OUT \| TD_T_DATA1 : TD_CC \| TD_R \| TD_DP_IN \| TD_T_DATA1;	732	TD_CC \| TD_R \| TD_DP_OUT \| TD_T_DATA1 : TD_CC \| TD_R \| TD_DP_IN \| TD_T_DATA1;
733	/* NOTE: mishandles transfers >8K, some >4K */	733	/* NOTE: mishandles transfers >8K, some >4K */
734	td_fill (ohci, info, data, data_len, dev, cnt++, urb);	734	td_fill (ohci, info, data, data_len, dev, cnt++, urb);
735	}	735	}
736	info = usb_pipeout (pipe)?	736	info = usb_pipeout (pipe)?
737	TD_CC \| TD_DP_IN \| TD_T_DATA1: TD_CC \| TD_DP_OUT \| TD_T_DATA1;	737	TD_CC \| TD_DP_IN \| TD_T_DATA1: TD_CC \| TD_DP_OUT \| TD_T_DATA1;
738	td_fill (ohci, info, data, 0, dev, cnt++, urb);	738	td_fill (ohci, info, data, 0, dev, cnt++, urb);
739	if (!ohci->sleeping)	739	if (!ohci->sleeping)
740	writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */	740	writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
741	break;	741	break;
742	}	742	}
743	if (urb->length != cnt)	743	if (urb->length != cnt)
744	dbg("TD LENGTH %d != CNT %d", urb->length, cnt);	744	dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
745	}	745	}
746		746
747	/-------------------------------------------------------------------------	747	/-------------------------------------------------------------------------
748	* Done List handling functions	748	* Done List handling functions
749	-------------------------------------------------------------------------/	749	-------------------------------------------------------------------------/
750		750
751		751
752	/* calculate the transfer length and update the urb */	752	/* calculate the transfer length and update the urb */
753		753
754	static void dl_transfer_length(td_t * td)	754	static void dl_transfer_length(td_t * td)
755	{	755	{
756	__u32 tdINFO, tdBE, tdCBP;	756	__u32 tdINFO, tdBE, tdCBP;
757	urb_priv_t *lurb_priv = &urb_priv;	757	urb_priv_t *lurb_priv = &urb_priv;
758		758
759	tdINFO = ohci_cpu_to_le32 (td->hwINFO);	759	tdINFO = ohci_cpu_to_le32 (td->hwINFO);
760	tdBE = ohci_cpu_to_le32 (td->hwBE);	760	tdBE = ohci_cpu_to_le32 (td->hwBE);
761	tdCBP = ohci_cpu_to_le32 (td->hwCBP);	761	tdCBP = ohci_cpu_to_le32 (td->hwCBP);
762		762
763		763
764	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&	764	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
765	((td->index == 0) \|\| (td->index == lurb_priv->length - 1)))) {	765	((td->index == 0) \|\| (td->index == lurb_priv->length - 1)))) {
766	if (tdBE != 0) {	766	if (tdBE != 0) {
767	if (td->hwCBP == 0)	767	if (td->hwCBP == 0)
768	lurb_priv->actual_length += tdBE - td->data + 1;	768	lurb_priv->actual_length += tdBE - td->data + 1;
769	else	769	else
770	lurb_priv->actual_length += tdCBP - td->data;	770	lurb_priv->actual_length += tdCBP - td->data;
771	}	771	}
772	}	772	}
773	}	773	}
774		774
775	/-------------------------------------------------------------------------/	775	/-------------------------------------------------------------------------/
776		776
777	/* replies to the request have to be on a FIFO basis so	777	/* replies to the request have to be on a FIFO basis so
778	* we reverse the reversed done-list */	778	* we reverse the reversed done-list */
779		779
780	static td_t * dl_reverse_done_list (ohci_t *ohci)	780	static td_t * dl_reverse_done_list (ohci_t *ohci)
781	{	781	{
782	__u32 td_list_hc;	782	__u32 td_list_hc;
783	td_t *td_rev = NULL;	783	td_t *td_rev = NULL;
784	td_t *td_list = NULL;	784	td_t *td_list = NULL;
785	urb_priv_t *lurb_priv = NULL;	785	urb_priv_t *lurb_priv = NULL;
786		786
787	td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;	787	td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
788	ohci->hcca->done_head = 0;	788	ohci->hcca->done_head = 0;
789		789
790	while (td_list_hc) {	790	while (td_list_hc) {
791	td_list = (td_t *)td_list_hc;	791	td_list = (td_t *)td_list_hc;
792		792
793	if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {	793	if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
794	lurb_priv = &urb_priv;	794	lurb_priv = &urb_priv;
795	dbg(" USB-error/status: %x : %p",	795	dbg(" USB-error/status: %x : %p",
796	TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);	796	TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
797	if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {	797	if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
798	if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {	798	if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
799	td_list->ed->hwHeadP =	799	td_list->ed->hwHeadP =
800	(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) \|	800	(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) \|
801	(td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));	801	(td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
802	lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;	802	lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
803	} else	803	} else
804	td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);	804	td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
805	}	805	}
806	#ifdef CONFIG_MPC5200	806	#ifdef CONFIG_MPC5200
807	td_list->hwNextTD = 0;	807	td_list->hwNextTD = 0;
808	#endif	808	#endif
809	}	809	}
810		810
811	td_list->next_dl_td = td_rev;	811	td_list->next_dl_td = td_rev;
812	td_rev = td_list;	812	td_rev = td_list;
813	td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;	813	td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
814	}	814	}
815	return td_list;	815	return td_list;
816	}	816	}
817		817
818	/-------------------------------------------------------------------------/	818	/-------------------------------------------------------------------------/
819		819
820	/* td done list */	820	/* td done list */
821	static int dl_done_list (ohci_t ohci, td_t td_list)	821	static int dl_done_list (ohci_t ohci, td_t td_list)
822	{	822	{
823	td_t *td_list_next = NULL;	823	td_t *td_list_next = NULL;
824	ed_t *ed;	824	ed_t *ed;
825	int cc = 0;	825	int cc = 0;
826	int stat = 0;	826	int stat = 0;
827	/* urb_t urb; /	827	/* urb_t urb; /
828	urb_priv_t *lurb_priv;	828	urb_priv_t *lurb_priv;
829	__u32 tdINFO, edHeadP, edTailP;	829	__u32 tdINFO, edHeadP, edTailP;
830		830
831	while (td_list) {	831	while (td_list) {
832	td_list_next = td_list->next_dl_td;	832	td_list_next = td_list->next_dl_td;
833		833
834	lurb_priv = &urb_priv;	834	lurb_priv = &urb_priv;
835	tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);	835	tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
836		836
837	ed = td_list->ed;	837	ed = td_list->ed;
838		838
839	dl_transfer_length(td_list);	839	dl_transfer_length(td_list);
840		840
841	/* error code of transfer */	841	/* error code of transfer */
842	cc = TD_CC_GET (tdINFO);	842	cc = TD_CC_GET (tdINFO);
843	if (++(lurb_priv->td_cnt) == lurb_priv->length) {	843	if (++(lurb_priv->td_cnt) == lurb_priv->length) {
844	if ((ed->state & (ED_OPER \| ED_UNLINK))	844	if ((ed->state & (ED_OPER \| ED_UNLINK))
845	&& (lurb_priv->state != URB_DEL)) {	845	&& (lurb_priv->state != URB_DEL)) {
846	dbg("ConditionCode %#x", cc);	846	dbg("ConditionCode %#x", cc);
847	stat = cc_to_error[cc];	847	stat = cc_to_error[cc];
848	urb_finished = 1;	848	urb_finished = 1;
849	}	849	}
850	}	850	}
851		851
852	if (ed->state != ED_NEW) {	852	if (ed->state != ED_NEW) {
853	edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;	853	edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
854	edTailP = ohci_cpu_to_le32 (ed->hwTailP);	854	edTailP = ohci_cpu_to_le32 (ed->hwTailP);
855		855
856	/* unlink eds if they are not busy */	856	/* unlink eds if they are not busy */
857	if ((edHeadP == edTailP) && (ed->state == ED_OPER))	857	if ((edHeadP == edTailP) && (ed->state == ED_OPER))
858	ep_unlink (ohci, ed);	858	ep_unlink (ohci, ed);
859	}	859	}
860		860
861	td_list = td_list_next;	861	td_list = td_list_next;
862	}	862	}
863	return stat;	863	return stat;
864	}	864	}
865		865
866	/-------------------------------------------------------------------------	866	/-------------------------------------------------------------------------
867	* Virtual Root Hub	867	* Virtual Root Hub
868	-------------------------------------------------------------------------/	868	-------------------------------------------------------------------------/
869		869
870	/* Device descriptor */	870	/* Device descriptor */
871	static __u8 root_hub_dev_des[] =	871	static __u8 root_hub_dev_des[] =
872	{	872	{
873	0x12, /* __u8 bLength; */	873	0x12, /* __u8 bLength; */
874	0x01, /* __u8 bDescriptorType; Device */	874	0x01, /* __u8 bDescriptorType; Device */
875	0x10, /* __u16 bcdUSB; v1.1 */	875	0x10, /* __u16 bcdUSB; v1.1 */
876	0x01,	876	0x01,
877	0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */	877	0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
878	0x00, /* __u8 bDeviceSubClass; */	878	0x00, /* __u8 bDeviceSubClass; */
879	0x00, /* __u8 bDeviceProtocol; */	879	0x00, /* __u8 bDeviceProtocol; */
880	0x08, /* __u8 bMaxPacketSize0; 8 Bytes */	880	0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
881	0x00, /* __u16 idVendor; */	881	0x00, /* __u16 idVendor; */
882	0x00,	882	0x00,
883	0x00, /* __u16 idProduct; */	883	0x00, /* __u16 idProduct; */
884	0x00,	884	0x00,
885	0x00, /* __u16 bcdDevice; */	885	0x00, /* __u16 bcdDevice; */
886	0x00,	886	0x00,
887	0x00, /* __u8 iManufacturer; */	887	0x00, /* __u8 iManufacturer; */
888	0x01, /* __u8 iProduct; */	888	0x01, /* __u8 iProduct; */
889	0x00, /* __u8 iSerialNumber; */	889	0x00, /* __u8 iSerialNumber; */
890	0x01 /* __u8 bNumConfigurations; */	890	0x01 /* __u8 bNumConfigurations; */
891	};	891	};
892		892
893		893
894	/* Configuration descriptor */	894	/* Configuration descriptor */
895	static __u8 root_hub_config_des[] =	895	static __u8 root_hub_config_des[] =
896	{	896	{
897	0x09, /* __u8 bLength; */	897	0x09, /* __u8 bLength; */
898	0x02, /* __u8 bDescriptorType; Configuration */	898	0x02, /* __u8 bDescriptorType; Configuration */
899	0x19, /* __u16 wTotalLength; */	899	0x19, /* __u16 wTotalLength; */
900	0x00,	900	0x00,
901	0x01, /* __u8 bNumInterfaces; */	901	0x01, /* __u8 bNumInterfaces; */
902	0x01, /* __u8 bConfigurationValue; */	902	0x01, /* __u8 bConfigurationValue; */
903	0x00, /* __u8 iConfiguration; */	903	0x00, /* __u8 iConfiguration; */
904	0x40, /* __u8 bmAttributes;	904	0x40, /* __u8 bmAttributes;
905	Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */	905	Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
906	0x00, /* __u8 MaxPower; */	906	0x00, /* __u8 MaxPower; */
907		907
908	/* interface */	908	/* interface */
909	0x09, /* __u8 if_bLength; */	909	0x09, /* __u8 if_bLength; */
910	0x04, /* __u8 if_bDescriptorType; Interface */	910	0x04, /* __u8 if_bDescriptorType; Interface */
911	0x00, /* __u8 if_bInterfaceNumber; */	911	0x00, /* __u8 if_bInterfaceNumber; */
912	0x00, /* __u8 if_bAlternateSetting; */	912	0x00, /* __u8 if_bAlternateSetting; */
913	0x01, /* __u8 if_bNumEndpoints; */	913	0x01, /* __u8 if_bNumEndpoints; */
914	0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */	914	0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
915	0x00, /* __u8 if_bInterfaceSubClass; */	915	0x00, /* __u8 if_bInterfaceSubClass; */
916	0x00, /* __u8 if_bInterfaceProtocol; */	916	0x00, /* __u8 if_bInterfaceProtocol; */
917	0x00, /* __u8 if_iInterface; */	917	0x00, /* __u8 if_iInterface; */
918		918
919	/* endpoint */	919	/* endpoint */
920	0x07, /* __u8 ep_bLength; */	920	0x07, /* __u8 ep_bLength; */
921	0x05, /* __u8 ep_bDescriptorType; Endpoint */	921	0x05, /* __u8 ep_bDescriptorType; Endpoint */
922	0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */	922	0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
923	0x03, /* __u8 ep_bmAttributes; Interrupt */	923	0x03, /* __u8 ep_bmAttributes; Interrupt */
924	0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */	924	0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
925	0x00,	925	0x00,
926	0xff /* __u8 ep_bInterval; 255 ms */	926	0xff /* __u8 ep_bInterval; 255 ms */
927	};	927	};
928		928
929	static unsigned char root_hub_str_index0[] =	929	static unsigned char root_hub_str_index0[] =
930	{	930	{
931	0x04, /* __u8 bLength; */	931	0x04, /* __u8 bLength; */
932	0x03, /* __u8 bDescriptorType; String-descriptor */	932	0x03, /* __u8 bDescriptorType; String-descriptor */
933	0x09, /* __u8 lang ID */	933	0x09, /* __u8 lang ID */
934	0x04, /* __u8 lang ID */	934	0x04, /* __u8 lang ID */
935	};	935	};
936		936
937	static unsigned char root_hub_str_index1[] =	937	static unsigned char root_hub_str_index1[] =
938	{	938	{
939	28, /* __u8 bLength; */	939	28, /* __u8 bLength; */
940	0x03, /* __u8 bDescriptorType; String-descriptor */	940	0x03, /* __u8 bDescriptorType; String-descriptor */
941	'O', /* __u8 Unicode */	941	'O', /* __u8 Unicode */
942	0, /* __u8 Unicode */	942	0, /* __u8 Unicode */
943	'H', /* __u8 Unicode */	943	'H', /* __u8 Unicode */
944	0, /* __u8 Unicode */	944	0, /* __u8 Unicode */
945	'C', /* __u8 Unicode */	945	'C', /* __u8 Unicode */
946	0, /* __u8 Unicode */	946	0, /* __u8 Unicode */
947	'I', /* __u8 Unicode */	947	'I', /* __u8 Unicode */
948	0, /* __u8 Unicode */	948	0, /* __u8 Unicode */
949	' ', /* __u8 Unicode */	949	' ', /* __u8 Unicode */
950	0, /* __u8 Unicode */	950	0, /* __u8 Unicode */
951	'R', /* __u8 Unicode */	951	'R', /* __u8 Unicode */
952	0, /* __u8 Unicode */	952	0, /* __u8 Unicode */
953	'o', /* __u8 Unicode */	953	'o', /* __u8 Unicode */
954	0, /* __u8 Unicode */	954	0, /* __u8 Unicode */
955	'o', /* __u8 Unicode */	955	'o', /* __u8 Unicode */
956	0, /* __u8 Unicode */	956	0, /* __u8 Unicode */
957	't', /* __u8 Unicode */	957	't', /* __u8 Unicode */
958	0, /* __u8 Unicode */	958	0, /* __u8 Unicode */
959	' ', /* __u8 Unicode */	959	' ', /* __u8 Unicode */
960	0, /* __u8 Unicode */	960	0, /* __u8 Unicode */
961	'H', /* __u8 Unicode */	961	'H', /* __u8 Unicode */
962	0, /* __u8 Unicode */	962	0, /* __u8 Unicode */
963	'u', /* __u8 Unicode */	963	'u', /* __u8 Unicode */
964	0, /* __u8 Unicode */	964	0, /* __u8 Unicode */
965	'b', /* __u8 Unicode */	965	'b', /* __u8 Unicode */
966	0, /* __u8 Unicode */	966	0, /* __u8 Unicode */
967	};	967	};
968		968
969	/* Hub class-specific descriptor is constructed dynamically */	969	/* Hub class-specific descriptor is constructed dynamically */
970		970
971		971
972	/-------------------------------------------------------------------------/	972	/-------------------------------------------------------------------------/
973		973
974	#define OK(x) len = (x); break	974	#define OK(x) len = (x); break
975	#ifdef DEBUG	975	#ifdef DEBUG
976	#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}	976	#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
977	#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}	977	#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
978	#else	978	#else
979	#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)	979	#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
980	#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])	980	#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
981	#endif	981	#endif
982	#define RD_RH_STAT roothub_status(&gohci)	982	#define RD_RH_STAT roothub_status(&gohci)
983	#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)	983	#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
984		984
985	/* request to virtual root hub */	985	/* request to virtual root hub */
986		986
987	int rh_check_port_status(ohci_t *controller)	987	int rh_check_port_status(ohci_t *controller)
988	{	988	{
989	__u32 temp, ndp, i;	989	__u32 temp, ndp, i;
990	int res;	990	int res;
991		991
992	res = -1;	992	res = -1;
993	temp = roothub_a (controller);	993	temp = roothub_a (controller);
994	ndp = (temp & RH_A_NDP);	994	ndp = (temp & RH_A_NDP);
995	for (i = 0; i < ndp; i++) {	995	for (i = 0; i < ndp; i++) {
996	temp = roothub_portstatus (controller, i);	996	temp = roothub_portstatus (controller, i);
997	/* check for a device disconnect */	997	/* check for a device disconnect */
998	if (((temp & (RH_PS_PESC \| RH_PS_CSC)) ==	998	if (((temp & (RH_PS_PESC \| RH_PS_CSC)) ==
999	(RH_PS_PESC \| RH_PS_CSC)) &&	999	(RH_PS_PESC \| RH_PS_CSC)) &&
1000	((temp & RH_PS_CCS) == 0)) {	1000	((temp & RH_PS_CCS) == 0)) {
1001	res = i;	1001	res = i;
1002	break;	1002	break;
1003	}	1003	}
1004	}	1004	}
1005	return res;	1005	return res;
1006	}	1006	}
1007		1007
1008	static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,	1008	static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1009	void buffer, int transfer_len, struct devrequest cmd)	1009	void buffer, int transfer_len, struct devrequest cmd)
1010	{	1010	{
1011	void * data = buffer;	1011	void * data = buffer;
1012	int leni = transfer_len;	1012	int leni = transfer_len;
1013	int len = 0;	1013	int len = 0;
1014	int stat = 0;	1014	int stat = 0;
1015	__u32 datab[4];	1015	__u32 datab[4];
1016	__u8 data_buf = (__u8 )datab;	1016	__u8 data_buf = (__u8 )datab;
1017	__u16 bmRType_bReq;	1017	__u16 bmRType_bReq;
1018	__u16 wValue;	1018	__u16 wValue;
1019	__u16 wIndex;	1019	__u16 wIndex;
1020	__u16 wLength;	1020	__u16 wLength;
1021		1021
1022	#ifdef DEBUG	1022	#ifdef DEBUG
1023	urb_priv.actual_length = 0;	1023	urb_priv.actual_length = 0;
1024	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));	1024	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1025	#endif	1025	#endif
1026	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {	1026	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1027	info("Root-Hub submit IRQ: NOT implemented");	1027	info("Root-Hub submit IRQ: NOT implemented");
1028	return 0;	1028	return 0;
1029	}	1029	}
1030		1030
1031	bmRType_bReq = cmd->requesttype \| (cmd->request << 8);	1031	bmRType_bReq = cmd->requesttype \| (cmd->request << 8);
1032	wValue = m16_swap (cmd->value);	1032	wValue = m16_swap (cmd->value);
1033	wIndex = m16_swap (cmd->index);	1033	wIndex = m16_swap (cmd->index);
1034	wLength = m16_swap (cmd->length);	1034	wLength = m16_swap (cmd->length);
1035		1035
1036	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",	1036	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1037	dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);	1037	dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1038		1038
1039	switch (bmRType_bReq) {	1039	switch (bmRType_bReq) {
1040	/* Request Destination:	1040	/* Request Destination:
1041	without flags: Device,	1041	without flags: Device,
1042	RH_INTERFACE: interface,	1042	RH_INTERFACE: interface,
1043	RH_ENDPOINT: endpoint,	1043	RH_ENDPOINT: endpoint,
1044	RH_CLASS means HUB here,	1044	RH_CLASS means HUB here,
1045	RH_OTHER \| RH_CLASS almost ever means HUB_PORT here	1045	RH_OTHER \| RH_CLASS almost ever means HUB_PORT here
1046	*/	1046	*/
1047		1047
1048	case RH_GET_STATUS:	1048	case RH_GET_STATUS:
1049	(__u16 ) data_buf = m16_swap (1); OK (2);	1049	(__u16 ) data_buf = m16_swap (1); OK (2);
1050	case RH_GET_STATUS \| RH_INTERFACE:	1050	case RH_GET_STATUS \| RH_INTERFACE:
1051	(__u16 ) data_buf = m16_swap (0); OK (2);	1051	(__u16 ) data_buf = m16_swap (0); OK (2);
1052	case RH_GET_STATUS \| RH_ENDPOINT:	1052	case RH_GET_STATUS \| RH_ENDPOINT:
1053	(__u16 ) data_buf = m16_swap (0); OK (2);	1053	(__u16 ) data_buf = m16_swap (0); OK (2);
1054	case RH_GET_STATUS \| RH_CLASS:	1054	case RH_GET_STATUS \| RH_CLASS:
1055	(__u32 ) data_buf = m32_swap (	1055	(__u32 ) data_buf = m32_swap (
1056	RD_RH_STAT & ~(RH_HS_CRWE \| RH_HS_DRWE));	1056	RD_RH_STAT & ~(RH_HS_CRWE \| RH_HS_DRWE));
1057	OK (4);	1057	OK (4);
1058	case RH_GET_STATUS \| RH_OTHER \| RH_CLASS:	1058	case RH_GET_STATUS \| RH_OTHER \| RH_CLASS:
1059	(__u32 ) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);	1059	(__u32 ) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
1060		1060
1061	case RH_CLEAR_FEATURE \| RH_ENDPOINT:	1061	case RH_CLEAR_FEATURE \| RH_ENDPOINT:
1062	switch (wValue) {	1062	switch (wValue) {
1063	case (RH_ENDPOINT_STALL): OK (0);	1063	case (RH_ENDPOINT_STALL): OK (0);
1064	}	1064	}
1065	break;	1065	break;
1066		1066
1067	case RH_CLEAR_FEATURE \| RH_CLASS:	1067	case RH_CLEAR_FEATURE \| RH_CLASS:
1068	switch (wValue) {	1068	switch (wValue) {
1069	case RH_C_HUB_LOCAL_POWER:	1069	case RH_C_HUB_LOCAL_POWER:
1070	OK(0);	1070	OK(0);
1071	case (RH_C_HUB_OVER_CURRENT):	1071	case (RH_C_HUB_OVER_CURRENT):
1072	WR_RH_STAT(RH_HS_OCIC); OK (0);	1072	WR_RH_STAT(RH_HS_OCIC); OK (0);
1073	}	1073	}
1074	break;	1074	break;
1075		1075
1076	case RH_CLEAR_FEATURE \| RH_OTHER \| RH_CLASS:	1076	case RH_CLEAR_FEATURE \| RH_OTHER \| RH_CLASS:
1077	switch (wValue) {	1077	switch (wValue) {
1078	case (RH_PORT_ENABLE):	1078	case (RH_PORT_ENABLE):
1079	WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);	1079	WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1080	case (RH_PORT_SUSPEND):	1080	case (RH_PORT_SUSPEND):
1081	WR_RH_PORTSTAT (RH_PS_POCI); OK (0);	1081	WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1082	case (RH_PORT_POWER):	1082	case (RH_PORT_POWER):
1083	WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);	1083	WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1084	case (RH_C_PORT_CONNECTION):	1084	case (RH_C_PORT_CONNECTION):
1085	WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);	1085	WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1086	case (RH_C_PORT_ENABLE):	1086	case (RH_C_PORT_ENABLE):
1087	WR_RH_PORTSTAT (RH_PS_PESC); OK (0);	1087	WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1088	case (RH_C_PORT_SUSPEND):	1088	case (RH_C_PORT_SUSPEND):
1089	WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);	1089	WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1090	case (RH_C_PORT_OVER_CURRENT):	1090	case (RH_C_PORT_OVER_CURRENT):
1091	WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);	1091	WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1092	case (RH_C_PORT_RESET):	1092	case (RH_C_PORT_RESET):
1093	WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);	1093	WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1094	}	1094	}
1095	break;	1095	break;
1096		1096
1097	case RH_SET_FEATURE \| RH_OTHER \| RH_CLASS:	1097	case RH_SET_FEATURE \| RH_OTHER \| RH_CLASS:
1098	switch (wValue) {	1098	switch (wValue) {
1099	case (RH_PORT_SUSPEND):	1099	case (RH_PORT_SUSPEND):
1100	WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);	1100	WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1101	case (RH_PORT_RESET): /* BUG IN HUP CODE *********/	1101	case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1102	if (RD_RH_PORTSTAT & RH_PS_CCS)	1102	if (RD_RH_PORTSTAT & RH_PS_CCS)
1103	WR_RH_PORTSTAT (RH_PS_PRS);	1103	WR_RH_PORTSTAT (RH_PS_PRS);
1104	OK (0);	1104	OK (0);
1105	case (RH_PORT_POWER):	1105	case (RH_PORT_POWER):
1106	WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);	1106	WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
1107	case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/	1107	case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1108	if (RD_RH_PORTSTAT & RH_PS_CCS)	1108	if (RD_RH_PORTSTAT & RH_PS_CCS)
1109	WR_RH_PORTSTAT (RH_PS_PES );	1109	WR_RH_PORTSTAT (RH_PS_PES );
1110	OK (0);	1110	OK (0);
1111	}	1111	}
1112	break;	1112	break;
1113		1113
1114	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);	1114	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1115		1115
1116	case RH_GET_DESCRIPTOR:	1116	case RH_GET_DESCRIPTOR:
1117	switch ((wValue & 0xff00) >> 8) {	1117	switch ((wValue & 0xff00) >> 8) {
1118	case (0x01): /* device descriptor */	1118	case (0x01): /* device descriptor */
1119	len = min_t(unsigned int,	1119	len = min_t(unsigned int,
1120	leni,	1120	leni,
1121	min_t(unsigned int,	1121	min_t(unsigned int,
1122	sizeof (root_hub_dev_des),	1122	sizeof (root_hub_dev_des),
1123	wLength));	1123	wLength));
1124	data_buf = root_hub_dev_des; OK(len);	1124	data_buf = root_hub_dev_des; OK(len);
1125	case (0x02): /* configuration descriptor */	1125	case (0x02): /* configuration descriptor */
1126	len = min_t(unsigned int,	1126	len = min_t(unsigned int,
1127	leni,	1127	leni,
1128	min_t(unsigned int,	1128	min_t(unsigned int,
1129	sizeof (root_hub_config_des),	1129	sizeof (root_hub_config_des),
1130	wLength));	1130	wLength));
1131	data_buf = root_hub_config_des; OK(len);	1131	data_buf = root_hub_config_des; OK(len);
1132	case (0x03): /* string descriptors */	1132	case (0x03): /* string descriptors */
1133	if(wValue==0x0300) {	1133	if(wValue==0x0300) {
1134	len = min_t(unsigned int,	1134	len = min_t(unsigned int,
1135	leni,	1135	leni,
1136	min_t(unsigned int,	1136	min_t(unsigned int,
1137	sizeof (root_hub_str_index0),	1137	sizeof (root_hub_str_index0),
1138	wLength));	1138	wLength));
1139	data_buf = root_hub_str_index0;	1139	data_buf = root_hub_str_index0;
1140	OK(len);	1140	OK(len);
1141	}	1141	}
1142	if(wValue==0x0301) {	1142	if(wValue==0x0301) {
1143	len = min_t(unsigned int,	1143	len = min_t(unsigned int,
1144	leni,	1144	leni,
1145	min_t(unsigned int,	1145	min_t(unsigned int,
1146	sizeof (root_hub_str_index1),	1146	sizeof (root_hub_str_index1),
1147	wLength));	1147	wLength));
1148	data_buf = root_hub_str_index1;	1148	data_buf = root_hub_str_index1;
1149	OK(len);	1149	OK(len);
1150	}	1150	}
1151	default:	1151	default:
1152	stat = USB_ST_STALLED;	1152	stat = USB_ST_STALLED;
1153	}	1153	}
1154	break;	1154	break;
1155		1155
1156	case RH_GET_DESCRIPTOR \| RH_CLASS:	1156	case RH_GET_DESCRIPTOR \| RH_CLASS:
1157	{	1157	{
1158	__u32 temp = roothub_a (&gohci);	1158	__u32 temp = roothub_a (&gohci);
1159		1159
1160	data_buf [0] = 9; /* min length; */	1160	data_buf [0] = 9; /* min length; */
1161	data_buf [1] = 0x29;	1161	data_buf [1] = 0x29;
1162	data_buf [2] = temp & RH_A_NDP;	1162	data_buf [2] = temp & RH_A_NDP;
1163	data_buf [3] = 0;	1163	data_buf [3] = 0;
1164	if (temp & RH_A_PSM) /* per-port power switching? */	1164	if (temp & RH_A_PSM) /* per-port power switching? */
1165	data_buf [3] \|= 0x1;	1165	data_buf [3] \|= 0x1;
1166	if (temp & RH_A_NOCP) /* no overcurrent reporting? */	1166	if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1167	data_buf [3] \|= 0x10;	1167	data_buf [3] \|= 0x10;
1168	else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */	1168	else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1169	data_buf [3] \|= 0x8;	1169	data_buf [3] \|= 0x8;
1170		1170
1171	/* corresponds to data_buf[4-7] */	1171	/* corresponds to data_buf[4-7] */
1172	datab [1] = 0;	1172	datab [1] = 0;
1173	data_buf [5] = (temp & RH_A_POTPGT) >> 24;	1173	data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1174	temp = roothub_b (&gohci);	1174	temp = roothub_b (&gohci);
1175	data_buf [7] = temp & RH_B_DR;	1175	data_buf [7] = temp & RH_B_DR;
1176	if (data_buf [2] < 7) {	1176	if (data_buf [2] < 7) {
1177	data_buf [8] = 0xff;	1177	data_buf [8] = 0xff;
1178	} else {	1178	} else {
1179	data_buf [0] += 2;	1179	data_buf [0] += 2;
1180	data_buf [8] = (temp & RH_B_DR) >> 8;	1180	data_buf [8] = (temp & RH_B_DR) >> 8;
1181	data_buf [10] = data_buf [9] = 0xff;	1181	data_buf [10] = data_buf [9] = 0xff;
1182	}	1182	}
1183		1183
1184	len = min_t(unsigned int, leni,	1184	len = min_t(unsigned int, leni,
1185	min_t(unsigned int, data_buf [0], wLength));	1185	min_t(unsigned int, data_buf [0], wLength));
1186	OK (len);	1186	OK (len);
1187	}	1187	}
1188		1188
1189	case RH_GET_CONFIGURATION: (__u8 ) data_buf = 0x01; OK (1);	1189	case RH_GET_CONFIGURATION: (__u8 ) data_buf = 0x01; OK (1);
1190		1190
1191	case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);	1191	case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1192		1192
1193	default:	1193	default:
1194	dbg ("unsupported root hub command");	1194	dbg ("unsupported root hub command");
1195	stat = USB_ST_STALLED;	1195	stat = USB_ST_STALLED;
1196	}	1196	}
1197		1197
1198	#ifdef DEBUG	1198	#ifdef DEBUG
1199	ohci_dump_roothub (&gohci, 1);	1199	ohci_dump_roothub (&gohci, 1);
1200	#endif	1200	#endif
1201		1201
1202	len = min_t(int, len, leni);	1202	len = min_t(int, len, leni);
1203	if (data != data_buf)	1203	if (data != data_buf)
1204	memcpy (data, data_buf, len);	1204	memcpy (data, data_buf, len);
1205	dev->act_len = len;	1205	dev->act_len = len;
1206	dev->status = stat;	1206	dev->status = stat;
1207		1207
1208	#ifdef DEBUG	1208	#ifdef DEBUG
1209	if (transfer_len)	1209	if (transfer_len)
1210	urb_priv.actual_length = transfer_len;	1210	urb_priv.actual_length = transfer_len;
1211	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/usb_pipein(pipe)/);	1211	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/usb_pipein(pipe)/);
1212	#endif	1212	#endif
1213		1213
1214	return stat;	1214	return stat;
1215	}	1215	}
1216		1216
1217	/-------------------------------------------------------------------------/	1217	/-------------------------------------------------------------------------/
1218		1218
1219	/* common code for handling submit messages - used for all but root hub */	1219	/* common code for handling submit messages - used for all but root hub */
1220	/* accesses. */	1220	/* accesses. */
1221	int submit_common_msg(struct usb_device dev, unsigned long pipe, void buffer,	1221	int submit_common_msg(struct usb_device dev, unsigned long pipe, void buffer,
1222	int transfer_len, struct devrequest *setup, int interval)	1222	int transfer_len, struct devrequest *setup, int interval)
1223	{	1223	{
1224	int stat = 0;	1224	int stat = 0;
1225	int maxsize = usb_maxpacket(dev, pipe);	1225	int maxsize = usb_maxpacket(dev, pipe);
1226	int timeout;	1226	int timeout;
1227		1227
1228	/* device pulled? Shortcut the action. */	1228	/* device pulled? Shortcut the action. */
1229	if (devgone == dev) {	1229	if (devgone == dev) {
1230	dev->status = USB_ST_CRC_ERR;	1230	dev->status = USB_ST_CRC_ERR;
1231	return 0;	1231	return 0;
1232	}	1232	}
1233		1233
1234	#ifdef DEBUG	1234	#ifdef DEBUG
1235	urb_priv.actual_length = 0;	1235	urb_priv.actual_length = 0;
1236	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));	1236	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1237	#endif	1237	#endif
1238	if (!maxsize) {	1238	if (!maxsize) {
1239	err("submit_common_message: pipesize for pipe %lx is zero",	1239	err("submit_common_message: pipesize for pipe %lx is zero",
1240	pipe);	1240	pipe);
1241	return -1;	1241	return -1;
1242	}	1242	}
1243		1243
1244	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {	1244	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1245	err("sohci_submit_job failed");	1245	err("sohci_submit_job failed");
1246	return -1;	1246	return -1;
1247	}	1247	}
1248		1248
1249	/* allow more time for a BULK device to react - some are slow */	1249	/* allow more time for a BULK device to react - some are slow */
1250	#define BULK_TO 5000 /* timeout in milliseconds */	1250	#define BULK_TO 5000 /* timeout in milliseconds */
1251	if (usb_pipetype (pipe) == PIPE_BULK)	1251	if (usb_pipetype (pipe) == PIPE_BULK)
1252	timeout = BULK_TO;	1252	timeout = BULK_TO;
1253	else	1253	else
1254	timeout = 100;	1254	timeout = 100;
1255		1255
1256	/* wait for it to complete */	1256	/* wait for it to complete */
1257	for (;;) {	1257	for (;;) {
1258	/* check whether the controller is done */	1258	/* check whether the controller is done */
1259	stat = hc_interrupt();	1259	stat = hc_interrupt();
1260	if (stat < 0) {	1260	if (stat < 0) {
1261	stat = USB_ST_CRC_ERR;	1261	stat = USB_ST_CRC_ERR;
1262	break;	1262	break;
1263	}	1263	}
1264		1264
1265	/* NOTE: since we are not interrupt driven in U-Boot and always	1265	/* NOTE: since we are not interrupt driven in U-Boot and always
1266	* handle only one URB at a time, we cannot assume the	1266	* handle only one URB at a time, we cannot assume the
1267	* transaction finished on the first successful return from	1267	* transaction finished on the first successful return from
1268	* hc_interrupt().. unless the flag for current URB is set,	1268	* hc_interrupt().. unless the flag for current URB is set,
1269	* meaning that all TD's to/from device got actually	1269	* meaning that all TD's to/from device got actually
1270	* transferred and processed. If the current URB is not	1270	* transferred and processed. If the current URB is not
1271	* finished we need to re-iterate this loop so as	1271	* finished we need to re-iterate this loop so as
1272	* hc_interrupt() gets called again as there needs to be some	1272	* hc_interrupt() gets called again as there needs to be some
1273	* more TD's to process still */	1273	* more TD's to process still */
1274	if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {	1274	if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
1275	/* 0xff is returned for an SF-interrupt */	1275	/* 0xff is returned for an SF-interrupt */
1276	break;	1276	break;
1277	}	1277	}
1278		1278
1279	if (--timeout) {	1279	if (--timeout) {
1280	wait_ms(1);	1280	wait_ms(1);
1281	if (!urb_finished)	1281	if (!urb_finished)
1282	dbg("\%");	1282	dbg("\%");
1283		1283
1284	} else {	1284	} else {
1285	err("CTL:TIMEOUT ");	1285	err("CTL:TIMEOUT ");
1286	dbg("submit_common_msg: TO status %x\n", stat);	1286	dbg("submit_common_msg: TO status %x\n", stat);
1287	stat = USB_ST_CRC_ERR;	1287	stat = USB_ST_CRC_ERR;
1288	urb_finished = 1;	1288	urb_finished = 1;
1289	break;	1289	break;
1290	}	1290	}
1291	}	1291	}
1292	#if 0	1292	#if 0
1293	/* we got an Root Hub Status Change interrupt */	1293	/* we got an Root Hub Status Change interrupt */
1294	if (got_rhsc) {	1294	if (got_rhsc) {
1295	#ifdef DEBUG	1295	#ifdef DEBUG
1296	ohci_dump_roothub (&gohci, 1);	1296	ohci_dump_roothub (&gohci, 1);
1297	#endif	1297	#endif
1298	got_rhsc = 0;	1298	got_rhsc = 0;
1299	/* abuse timeout */	1299	/* abuse timeout */
1300	timeout = rh_check_port_status(&gohci);	1300	timeout = rh_check_port_status(&gohci);
1301	if (timeout >= 0) {	1301	if (timeout >= 0) {
1302	#if 0 /* this does nothing useful, but leave it here in case that changes */	1302	#if 0 /* this does nothing useful, but leave it here in case that changes */
1303	/* the called routine adds 1 to the passed value */	1303	/* the called routine adds 1 to the passed value */
1304	usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);	1304	usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1305	#endif	1305	#endif
1306	/*	1306	/*
1307	* XXX	1307	* XXX
1308	* This is potentially dangerous because it assumes	1308	* This is potentially dangerous because it assumes
1309	* that only one device is ever plugged in!	1309	* that only one device is ever plugged in!
1310	*/	1310	*/
1311	devgone = dev;	1311	devgone = dev;
1312	}	1312	}
1313	}	1313	}
1314	#endif	1314	#endif
1315		1315
1316	dev->status = stat;	1316	dev->status = stat;
1317	dev->act_len = transfer_len;	1317	dev->act_len = transfer_len;
1318		1318
1319	#ifdef DEBUG	1319	#ifdef DEBUG
1320	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));	1320	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1321	#endif	1321	#endif
1322		1322
1323	/* free TDs in urb_priv */	1323	/* free TDs in urb_priv */
1324	urb_free_priv (&urb_priv);	1324	urb_free_priv (&urb_priv);
1325	return 0;	1325	return 0;
1326	}	1326	}
1327		1327
1328	/* submit routines called from usb.c */	1328	/* submit routines called from usb.c */
1329	int submit_bulk_msg(struct usb_device dev, unsigned long pipe, void buffer,	1329	int submit_bulk_msg(struct usb_device dev, unsigned long pipe, void buffer,
1330	int transfer_len)	1330	int transfer_len)
1331	{	1331	{
1332	info("submit_bulk_msg");	1332	info("submit_bulk_msg");
1333	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);	1333	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1334	}	1334	}
1335		1335
1336	int submit_control_msg(struct usb_device dev, unsigned long pipe, void buffer,	1336	int submit_control_msg(struct usb_device dev, unsigned long pipe, void buffer,
1337	int transfer_len, struct devrequest *setup)	1337	int transfer_len, struct devrequest *setup)
1338	{	1338	{
1339	int maxsize = usb_maxpacket(dev, pipe);	1339	int maxsize = usb_maxpacket(dev, pipe);
1340		1340
1341	info("submit_control_msg");	1341	info("submit_control_msg");
1342	#ifdef DEBUG	1342	#ifdef DEBUG
1343	urb_priv.actual_length = 0;	1343	urb_priv.actual_length = 0;
1344	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));	1344	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1345	#endif	1345	#endif
1346	if (!maxsize) {	1346	if (!maxsize) {
1347	err("submit_control_message: pipesize for pipe %lx is zero",	1347	err("submit_control_message: pipesize for pipe %lx is zero",
1348	pipe);	1348	pipe);
1349	return -1;	1349	return -1;
1350	}	1350	}
1351	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {	1351	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1352	gohci.rh.dev = dev;	1352	gohci.rh.dev = dev;
1353	/* root hub - redirect */	1353	/* root hub - redirect */
1354	return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,	1354	return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1355	setup);	1355	setup);
1356	}	1356	}
1357		1357
1358	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);	1358	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1359	}	1359	}
1360		1360
1361	int submit_int_msg(struct usb_device dev, unsigned long pipe, void buffer,	1361	int submit_int_msg(struct usb_device dev, unsigned long pipe, void buffer,
1362	int transfer_len, int interval)	1362	int transfer_len, int interval)
1363	{	1363	{
1364	info("submit_int_msg");	1364	info("submit_int_msg");
1365	return -1;	1365	return -1;
1366	}	1366	}
1367		1367
1368	/-------------------------------------------------------------------------	1368	/-------------------------------------------------------------------------
1369	* HC functions	1369	* HC functions
1370	-------------------------------------------------------------------------/	1370	-------------------------------------------------------------------------/
1371		1371
1372	/* reset the HC and BUS */	1372	/* reset the HC and BUS */
1373		1373
1374	static int hc_reset (ohci_t *ohci)	1374	static int hc_reset (ohci_t *ohci)
1375	{	1375	{
1376	int timeout = 30;	1376	int timeout = 30;
1377	int smm_timeout = 50; /* 0,5 sec */	1377	int smm_timeout = 50; /* 0,5 sec */
1378		1378
1379	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */	1379	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1380	writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */	1380	writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1381	info("USB HC TakeOver from SMM");	1381	info("USB HC TakeOver from SMM");
1382	while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {	1382	while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1383	wait_ms (10);	1383	wait_ms (10);
1384	if (--smm_timeout == 0) {	1384	if (--smm_timeout == 0) {
1385	err("USB HC TakeOver failed!");	1385	err("USB HC TakeOver failed!");
1386	return -1;	1386	return -1;
1387	}	1387	}
1388	}	1388	}
1389	}	1389	}
1390		1390
1391	/* Disable HC interrupts */	1391	/* Disable HC interrupts */
1392	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);	1392	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1393		1393
1394	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",	1394	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1395	ohci->slot_name,	1395	ohci->slot_name,
1396	readl (&ohci->regs->control));	1396	readl (&ohci->regs->control));
1397		1397
1398	/* Reset USB (needed by some controllers) */	1398	/* Reset USB (needed by some controllers) */
1399	ohci->hc_control = 0;	1399	ohci->hc_control = 0;
1400	writel (ohci->hc_control, &ohci->regs->control);	1400	writel (ohci->hc_control, &ohci->regs->control);
1401		1401
1402	/* HC Reset requires max 10 us delay */	1402	/* HC Reset requires max 10 us delay */
1403	writel (OHCI_HCR, &ohci->regs->cmdstatus);	1403	writel (OHCI_HCR, &ohci->regs->cmdstatus);
1404	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {	1404	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1405	if (--timeout == 0) {	1405	if (--timeout == 0) {
1406	err("USB HC reset timed out!");	1406	err("USB HC reset timed out!");
1407	return -1;	1407	return -1;
1408	}	1408	}
1409	udelay (1);	1409	udelay (1);
1410	}	1410	}
1411	return 0;	1411	return 0;
1412	}	1412	}
1413		1413
1414	/-------------------------------------------------------------------------/	1414	/-------------------------------------------------------------------------/
1415		1415
1416	/* Start an OHCI controller, set the BUS operational	1416	/* Start an OHCI controller, set the BUS operational
1417	* enable interrupts	1417	* enable interrupts
1418	* connect the virtual root hub */	1418	* connect the virtual root hub */
1419		1419
1420	static int hc_start (ohci_t * ohci)	1420	static int hc_start (ohci_t * ohci)
1421	{	1421	{
1422	__u32 mask;	1422	__u32 mask;
1423	unsigned int fminterval;	1423	unsigned int fminterval;
1424		1424
1425	ohci->disabled = 1;	1425	ohci->disabled = 1;
1426		1426
1427	/* Tell the controller where the control and bulk lists are	1427	/* Tell the controller where the control and bulk lists are
1428	* The lists are empty now. */	1428	* The lists are empty now. */
1429		1429
1430	writel (0, &ohci->regs->ed_controlhead);	1430	writel (0, &ohci->regs->ed_controlhead);
1431	writel (0, &ohci->regs->ed_bulkhead);	1431	writel (0, &ohci->regs->ed_bulkhead);
1432		1432
1433	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */	1433	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1434		1434
1435	fminterval = 0x2edf;	1435	fminterval = 0x2edf;
1436	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);	1436	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1437	fminterval \|= ((((fminterval - 210) * 6) / 7) << 16);	1437	fminterval \|= ((((fminterval - 210) * 6) / 7) << 16);
1438	writel (fminterval, &ohci->regs->fminterval);	1438	writel (fminterval, &ohci->regs->fminterval);
1439	writel (0x628, &ohci->regs->lsthresh);	1439	writel (0x628, &ohci->regs->lsthresh);
1440		1440
1441	/* start controller operations */	1441	/* start controller operations */
1442	ohci->hc_control = OHCI_CONTROL_INIT \| OHCI_USB_OPER;	1442	ohci->hc_control = OHCI_CONTROL_INIT \| OHCI_USB_OPER;
1443	ohci->disabled = 0;	1443	ohci->disabled = 0;
1444	writel (ohci->hc_control, &ohci->regs->control);	1444	writel (ohci->hc_control, &ohci->regs->control);
1445		1445
1446	/* disable all interrupts */	1446	/* disable all interrupts */
1447	mask = (OHCI_INTR_SO \| OHCI_INTR_WDH \| OHCI_INTR_SF \| OHCI_INTR_RD \|	1447	mask = (OHCI_INTR_SO \| OHCI_INTR_WDH \| OHCI_INTR_SF \| OHCI_INTR_RD \|
1448	OHCI_INTR_UE \| OHCI_INTR_FNO \| OHCI_INTR_RHSC \|	1448	OHCI_INTR_UE \| OHCI_INTR_FNO \| OHCI_INTR_RHSC \|
1449	OHCI_INTR_OC \| OHCI_INTR_MIE);	1449	OHCI_INTR_OC \| OHCI_INTR_MIE);
1450	writel (mask, &ohci->regs->intrdisable);	1450	writel (mask, &ohci->regs->intrdisable);
1451	/* clear all interrupts */	1451	/* clear all interrupts */
1452	mask &= ~OHCI_INTR_MIE;	1452	mask &= ~OHCI_INTR_MIE;
1453	writel (mask, &ohci->regs->intrstatus);	1453	writel (mask, &ohci->regs->intrstatus);
1454	/* Choose the interrupts we care about now - but w/o MIE */	1454	/* Choose the interrupts we care about now - but w/o MIE */
1455	mask = OHCI_INTR_RHSC \| OHCI_INTR_UE \| OHCI_INTR_WDH \| OHCI_INTR_SO;	1455	mask = OHCI_INTR_RHSC \| OHCI_INTR_UE \| OHCI_INTR_WDH \| OHCI_INTR_SO;
1456	writel (mask, &ohci->regs->intrenable);	1456	writel (mask, &ohci->regs->intrenable);
1457		1457
1458	#ifdef OHCI_USE_NPS	1458	#ifdef OHCI_USE_NPS
1459	/* required for AMD-756 and some Mac platforms */	1459	/* required for AMD-756 and some Mac platforms */
1460	writel ((roothub_a (ohci) \| RH_A_NPS) & ~RH_A_PSM,	1460	writel ((roothub_a (ohci) \| RH_A_NPS) & ~RH_A_PSM,
1461	&ohci->regs->roothub.a);	1461	&ohci->regs->roothub.a);
1462	writel (RH_HS_LPSC, &ohci->regs->roothub.status);	1462	writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1463	#endif /* OHCI_USE_NPS */	1463	#endif /* OHCI_USE_NPS */
1464		1464
1465	#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})	1465	#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1466	/* POTPGT delay is bits 24-31, in 2 ms units. */	1466	/* POTPGT delay is bits 24-31, in 2 ms units. */
1467	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);	1467	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1468		1468
1469	/* connect the virtual root hub */	1469	/* connect the virtual root hub */
1470	ohci->rh.devnum = 0;	1470	ohci->rh.devnum = 0;
1471		1471
1472	return 0;	1472	return 0;
1473	}	1473	}
1474		1474
1475	/-------------------------------------------------------------------------/	1475	/-------------------------------------------------------------------------/
1476		1476
1477	/* an interrupt happens */	1477	/* an interrupt happens */
1478		1478
1479	static int	1479	static int
1480	hc_interrupt (void)	1480	hc_interrupt (void)
1481	{	1481	{
1482	ohci_t *ohci = &gohci;	1482	ohci_t *ohci = &gohci;
1483	struct ohci_regs *regs = ohci->regs;	1483	struct ohci_regs *regs = ohci->regs;
1484	int ints;	1484	int ints;
1485	int stat = -1;	1485	int stat = -1;
1486		1486
1487	if ((ohci->hcca->done_head != 0) &&	1487	if ((ohci->hcca->done_head != 0) &&
1488	!(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {	1488	!(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
1489		1489
1490	ints = OHCI_INTR_WDH;	1490	ints = OHCI_INTR_WDH;
1491		1491
1492	} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {	1492	} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
1493	ohci->disabled++;	1493	ohci->disabled++;
1494	err ("%s device removed!", ohci->slot_name);	1494	err ("%s device removed!", ohci->slot_name);
1495	return -1;	1495	return -1;
1496		1496
1497	} else if ((ints &= readl (&regs->intrenable)) == 0) {	1497	} else if ((ints &= readl (&regs->intrenable)) == 0) {
1498	dbg("hc_interrupt: returning..\n");	1498	dbg("hc_interrupt: returning..\n");
1499	return 0xff;	1499	return 0xff;
1500	}	1500	}
1501		1501
1502	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */	1502	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1503		1503
1504	if (ints & OHCI_INTR_RHSC) {	1504	if (ints & OHCI_INTR_RHSC) {
1505	got_rhsc = 1;	1505	got_rhsc = 1;
1506	stat = 0xff;	1506	stat = 0xff;
1507	}	1507	}
1508		1508
1509	if (ints & OHCI_INTR_UE) {	1509	if (ints & OHCI_INTR_UE) {
1510	ohci->disabled++;	1510	ohci->disabled++;
1511	err ("OHCI Unrecoverable Error, controller usb-%s disabled",	1511	err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1512	ohci->slot_name);	1512	ohci->slot_name);
1513	/* e.g. due to PCI Master/Target Abort */	1513	/* e.g. due to PCI Master/Target Abort */
1514		1514
1515	#ifdef DEBUG	1515	#ifdef DEBUG
1516	ohci_dump (ohci, 1);	1516	ohci_dump (ohci, 1);
1517	#endif	1517	#endif
1518	/* FIXME: be optimistic, hope that bug won't repeat often. */	1518	/* FIXME: be optimistic, hope that bug won't repeat often. */
1519	/* Make some non-interrupt context restart the controller. */	1519	/* Make some non-interrupt context restart the controller. */
1520	/* Count and limit the retries though; either hardware or */	1520	/* Count and limit the retries though; either hardware or */
1521	/* software errors can go forever... */	1521	/* software errors can go forever... */
1522	hc_reset (ohci);	1522	hc_reset (ohci);
1523	return -1;	1523	return -1;
1524	}	1524	}
1525		1525
1526	if (ints & OHCI_INTR_WDH) {	1526	if (ints & OHCI_INTR_WDH) {
1527	writel (OHCI_INTR_WDH, &regs->intrdisable);	1527	writel (OHCI_INTR_WDH, &regs->intrdisable);
1528	stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));	1528	stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1529	writel (OHCI_INTR_WDH, &regs->intrenable);	1529	writel (OHCI_INTR_WDH, &regs->intrenable);
1530	}	1530	}
1531		1531
1532	if (ints & OHCI_INTR_SO) {	1532	if (ints & OHCI_INTR_SO) {
1533	dbg("USB Schedule overrun\n");	1533	dbg("USB Schedule overrun\n");
1534	writel (OHCI_INTR_SO, &regs->intrenable);	1534	writel (OHCI_INTR_SO, &regs->intrenable);
1535	stat = -1;	1535	stat = -1;
1536	}	1536	}
1537		1537
1538	/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */	1538	/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1539	if (ints & OHCI_INTR_SF) {	1539	if (ints & OHCI_INTR_SF) {
1540	unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;	1540	unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
1541	wait_ms(1);	1541	wait_ms(1);
1542	writel (OHCI_INTR_SF, &regs->intrdisable);	1542	writel (OHCI_INTR_SF, &regs->intrdisable);
1543	if (ohci->ed_rm_list[frame] != NULL)	1543	if (ohci->ed_rm_list[frame] != NULL)
1544	writel (OHCI_INTR_SF, &regs->intrenable);	1544	writel (OHCI_INTR_SF, &regs->intrenable);
1545	stat = 0xff;	1545	stat = 0xff;
1546	}	1546	}
1547		1547
1548	writel (ints, &regs->intrstatus);	1548	writel (ints, &regs->intrstatus);
1549	return stat;	1549	return stat;
1550	}	1550	}
1551		1551
1552	/-------------------------------------------------------------------------/	1552	/-------------------------------------------------------------------------/
1553		1553
1554	/-------------------------------------------------------------------------/	1554	/-------------------------------------------------------------------------/
1555		1555
1556	/* De-allocate all resources.. */	1556	/* De-allocate all resources.. */
1557		1557
1558	static void hc_release_ohci (ohci_t *ohci)	1558	static void hc_release_ohci (ohci_t *ohci)
1559	{	1559	{
1560	dbg ("USB HC release ohci usb-%s", ohci->slot_name);	1560	dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1561		1561
1562	if (!ohci->disabled)	1562	if (!ohci->disabled)
1563	hc_reset (ohci);	1563	hc_reset (ohci);
1564	}	1564	}
1565		1565
1566	/-------------------------------------------------------------------------/	1566	/-------------------------------------------------------------------------/
1567		1567
1568	/*	1568	/*
1569	* low level initalisation routine, called from usb.c	1569	* low level initalisation routine, called from usb.c
1570	*/	1570	*/
1571	static char ohci_inited = 0;	1571	static char ohci_inited = 0;
1572		1572
1573	int usb_lowlevel_init(void)	1573	int usb_lowlevel_init(void)
1574	{	1574	{
1575	memset (&gohci, 0, sizeof (ohci_t));	1575	memset (&gohci, 0, sizeof (ohci_t));
1576	memset (&urb_priv, 0, sizeof (urb_priv_t));	1576	memset (&urb_priv, 0, sizeof (urb_priv_t));
1577		1577
1578	/* align the storage */	1578	/* align the storage */
1579	if ((__u32)&ghcca[0] & 0xff) {	1579	if ((__u32)&ghcca[0] & 0xff) {
1580	err("HCCA not aligned!!");	1580	err("HCCA not aligned!!");
1581	return -1;	1581	return -1;
1582	}	1582	}
1583	phcca = &ghcca[0];	1583	phcca = &ghcca[0];
1584	info("aligned ghcca %p", phcca);	1584	info("aligned ghcca %p", phcca);
1585	memset(&ohci_dev, 0, sizeof(struct ohci_device));	1585	memset(&ohci_dev, 0, sizeof(struct ohci_device));
1586	if ((__u32)&ohci_dev.ed[0] & 0x7) {	1586	if ((__u32)&ohci_dev.ed[0] & 0x7) {
1587	err("EDs not aligned!!");	1587	err("EDs not aligned!!");
1588	return -1;	1588	return -1;
1589	}	1589	}
1590	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));	1590	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1591	if ((__u32)gtd & 0x7) {	1591	if ((__u32)gtd & 0x7) {
1592	err("TDs not aligned!!");	1592	err("TDs not aligned!!");
1593	return -1;	1593	return -1;
1594	}	1594	}
1595	ptd = gtd;	1595	ptd = gtd;
1596	gohci.hcca = phcca;	1596	gohci.hcca = phcca;
1597	memset (phcca, 0, sizeof (struct ohci_hcca));	1597	memset (phcca, 0, sizeof (struct ohci_hcca));
1598		1598
1599	gohci.disabled = 1;	1599	gohci.disabled = 1;
1600	gohci.sleeping = 0;	1600	gohci.sleeping = 0;
1601	gohci.irq = -1;	1601	gohci.irq = -1;
1602	#if defined(CONFIG_440EP)	1602	#if defined(CONFIG_440EP)
1603	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE \| 0x1000);	1603	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE \| 0x1000);
1604	#elif defined(CONFIG_440EPX) \|\| defined(CFG_USB_HOST)	1604	#elif defined(CONFIG_440EPX) \|\| defined(CFG_USB_HOST)
1605	gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);	1605	gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
1606	#endif	1606	#endif
1607		1607
1608	gohci.flags = 0;	1608	gohci.flags = 0;
1609	gohci.slot_name = "ppc440";	1609	gohci.slot_name = "ppc440";
1610		1610
1611	if (hc_reset (&gohci) < 0) {	1611	if (hc_reset (&gohci) < 0) {
1612	hc_release_ohci (&gohci);	1612	hc_release_ohci (&gohci);
1613	return -1;	1613	return -1;
1614	}	1614	}
1615		1615
1616	if (hc_start (&gohci) < 0) {	1616	if (hc_start (&gohci) < 0) {
1617	err ("can't start usb-%s", gohci.slot_name);	1617	err ("can't start usb-%s", gohci.slot_name);
1618	hc_release_ohci (&gohci);	1618	hc_release_ohci (&gohci);
1619	return -1;	1619	return -1;
1620	}	1620	}
1621		1621
1622	#ifdef DEBUG	1622	#ifdef DEBUG
1623	ohci_dump (&gohci, 1);	1623	ohci_dump (&gohci, 1);
1624	#endif	1624	#endif
1625	ohci_inited = 1;	1625	ohci_inited = 1;
1626	urb_finished = 1;	1626	urb_finished = 1;
1627		1627
1628	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440EPX)	1628	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440EPX)
1629	/* init the device driver */	1629	/* init the device driver */
1630	usb_dev_init();	1630	usb_dev_init();
1631	#endif	1631	#endif
1632		1632
1633	return 0;	1633	return 0;
1634	}	1634	}
1635		1635
1636	int usb_lowlevel_stop(void)	1636	int usb_lowlevel_stop(void)
1637	{	1637	{
1638	/* this gets called really early - before the controller has */	1638	/* this gets called really early - before the controller has */
1639	/* even been initialized! */	1639	/* even been initialized! */
1640	if (!ohci_inited)	1640	if (!ohci_inited)
1641	return 0;	1641	return 0;
1642	/* TODO release any interrupts, etc. */	1642	/* TODO release any interrupts, etc. */
1643	/* call hc_release_ohci() here ? */	1643	/* call hc_release_ohci() here ? */
1644	hc_reset (&gohci);	1644	hc_reset (&gohci);
1645	return 0;	1645	return 0;
1646	}	1646	}
1647		1647
1648	#endif /* CONFIG_USB_OHCI */	1648	#endif /* CONFIG_USB_OHCI */
1649		1649