Eric Lee / smarc-uboot | Embedian Git Server

Commit d48eb5131d287f52bb85b4c58c8680a2e8e3b641

Authored by Peter Tyser 2009-04-19 11:34:02 +0800

Committed by Wolfgang Denk 2009-06-13 02:39:46 +0800

Exists in master and in 54 other branches

i2c: Remove deprecated individual i2c commands

The following individual I2C commands have been removed: imd, imm, inm,
imw, icrc32, iprobe, iloop, isdram.

The functionality of the individual commands is still available via
the 'i2c' command.

This change only has an impact on those boards which did not have
CONFIG_I2C_CMD_TREE defined.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Showing 26 changed files with 0 additions and 98 deletions Inline Diff

README
common/cmd_i2c.c
doc/feature-removal-schedule.txt
include/configs/DU405.h
include/configs/DU440.h
include/configs/MPC8313ERDB.h
include/configs/MPC8349EMDS.h
include/configs/MPC8349ITX.h
include/configs/MPC8360ERDK.h
include/configs/MPC8536DS.h
include/configs/MPC8568MDS.h
include/configs/MPC8569MDS.h
include/configs/MPC8572DS.h
include/configs/MVBLM7.h
include/configs/PMC440.h
include/configs/SIMPC8313.h
include/configs/XPEDITE5200.h
include/configs/XPEDITE5370.h
include/configs/ads5121.h
include/configs/at91rm9200ek.h
include/configs/katmai.h
include/configs/keymile-common.h
include/configs/kmeter1.h
include/configs/korat.h
include/configs/sbc8349.h
include/configs/socrates.h

README

Diff comments View file @ d48eb51

 #
 # (C) Copyright 2000 - 2008
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
 # published by the Free Software Foundation; either version 2 of
 # the License, or (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
 Summary:
 ========
 This directory contains the source code for U-Boot, a boot loader for
 Embedded boards based on PowerPC, ARM, MIPS and several other
 processors, which can be installed in a boot ROM and used to
 initialize and test the hardware or to download and run application
 code.
 The development of U-Boot is closely related to Linux: some parts of
 the source code originate in the Linux source tree, we have some
 header files in common, and special provision has been made to
 support booting of Linux images.
 Some attention has been paid to make this software easily
 configurable and extendable. For instance, all monitor commands are
 implemented with the same call interface, so that it's very easy to
 add new commands. Also, instead of permanently adding rarely used
 code (for instance hardware test utilities) to the monitor, you can
 load and run it dynamically.
 Status:
 =======
 In general, all boards for which a configuration option exists in the
 Makefile have been tested to some extent and can be considered
 "working". In fact, many of them are used in production systems.
 In case of problems see the CHANGELOG and CREDITS files to find out
 who contributed the specific port. The MAINTAINERS file lists board
 maintainers.
 Where to get help:
 ==================
 In case you have questions about, problems with or contributions for
 U-Boot you should send a message to the U-Boot mailing list at
 <u-boot@lists.denx.de>. There is also an archive of previous traffic
 on the mailing list - please search the archive before asking FAQ's.
 Please see http://lists.denx.de/pipermail/u-boot and
 http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
 Where to get source code:
 =========================
 The U-Boot source code is maintained in the git repository at
 git://www.denx.de/git/u-boot.git ; you can browse it online at
 http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
 The "snapshot" links on this page allow you to download tarballs of
 any version you might be interested in. Official releases are also
 available for FTP download from the ftp://ftp.denx.de/pub/u-boot/
 directory.
 Pre-built (and tested) images are available from
 ftp://ftp.denx.de/pub/u-boot/images/
 Where we come from:
 ===================
 - start from 8xxrom sources
 - create PPCBoot project (http://sourceforge.net/projects/ppcboot)
 - clean up code
 - make it easier to add custom boards
 - make it possible to add other [PowerPC] CPUs
 - extend functions, especially:
   * Provide extended interface to Linux boot loader
   * S-Record download
   * network boot
   * PCMCIA / CompactFlash / ATA disk / SCSI ... boot
 - create ARMBoot project (http://sourceforge.net/projects/armboot)
 - add other CPU families (starting with ARM)
 - create U-Boot project (http://sourceforge.net/projects/u-boot)
 - current project page: see http://www.denx.de/wiki/U-Boot
 Names and Spelling:
 ===================
 The "official" name of this project is "Das U-Boot". The spelling
 "U-Boot" shall be used in all written text (documentation, comments
 in source files etc.). Example:
 	This is the README file for the U-Boot project.
 File names etc. shall be based on the string "u-boot". Examples:
 	include/asm-ppc/u-boot.h
 	#include <asm/u-boot.h>
 Variable names, preprocessor constants etc. shall be either based on
 the string "u_boot" or on "U_BOOT". Example:
 	U_BOOT_VERSION		u_boot_logo
 	IH_OS_U_BOOT		u_boot_hush_start
 Versioning:
 ===========
 U-Boot uses a 3 level version number containing a version, a
 sub-version, and a patchlevel: "U-Boot-2.34.5" means version "2",
 sub-version "34", and patchlevel "4".
 The patchlevel is used to indicate certain stages of development
 between released versions, i. e. officially released versions of
 U-Boot will always have a patchlevel of "0".
 Directory Hierarchy:
 ====================
 - board		Board dependent files
 - common	Misc architecture independent functions
 - cpu		CPU specific files
   - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
   - arm720t	Files specific to ARM 720 CPUs
   - arm920t	Files specific to ARM 920 CPUs
     - at91rm9200 Files specific to Atmel AT91RM9200 CPU
     - imx	Files specific to Freescale MC9328 i.MX CPUs
     - s3c24x0	Files specific to Samsung S3C24X0 CPUs
   - arm925t	Files specific to ARM 925 CPUs
   - arm926ejs	Files specific to ARM 926 CPUs
   - arm1136	Files specific to ARM 1136 CPUs
   - at32ap	Files specific to Atmel AVR32 AP CPUs
   - blackfin	Files specific to Analog Devices Blackfin CPUs
   - i386	Files specific to i386 CPUs
   - ixp		Files specific to Intel XScale IXP CPUs
   - leon2	Files specific to Gaisler LEON2 SPARC CPU
   - leon3	Files specific to Gaisler LEON3 SPARC CPU
   - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
   - mcf5227x	Files specific to Freescale ColdFire MCF5227x CPUs
   - mcf532x	Files specific to Freescale ColdFire MCF5329 CPUs
   - mcf5445x	Files specific to Freescale ColdFire MCF5445x CPUs
   - mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
   - mips	Files specific to MIPS CPUs
   - mpc5xx	Files specific to Freescale MPC5xx  CPUs
   - mpc5xxx	Files specific to Freescale MPC5xxx CPUs
   - mpc8xx	Files specific to Freescale MPC8xx  CPUs
   - mpc8220	Files specific to Freescale MPC8220 CPUs
   - mpc824x	Files specific to Freescale MPC824x CPUs
   - mpc8260	Files specific to Freescale MPC8260 CPUs
   - mpc85xx	Files specific to Freescale MPC85xx CPUs
   - nios	Files specific to Altera NIOS CPUs
   - nios2	Files specific to Altera Nios-II CPUs
   - ppc4xx	Files specific to AMCC PowerPC 4xx CPUs
   - pxa		Files specific to Intel XScale PXA CPUs
   - s3c44b0	Files specific to Samsung S3C44B0 CPUs
   - sa1100	Files specific to Intel StrongARM SA1100 CPUs
 - disk		Code for disk drive partition handling
 - doc		Documentation (don't expect too much)
 - drivers	Commonly used device drivers
 - dtt		Digital Thermometer and Thermostat drivers
 - examples	Example code for standalone applications, etc.
 - include	Header Files
 - lib_arm	Files generic to ARM	 architecture
 - lib_avr32	Files generic to AVR32	 architecture
 - lib_blackfin	Files generic to Blackfin architecture
 - lib_generic	Files generic to all	 architectures
 - lib_i386	Files generic to i386	 architecture
 - lib_m68k	Files generic to m68k	 architecture
 - lib_mips	Files generic to MIPS	 architecture
 - lib_nios	Files generic to NIOS	 architecture
 - lib_ppc	Files generic to PowerPC architecture
 - lib_sparc	Files generic to SPARC	 architecture
 - libfdt	Library files to support flattened device trees
 - net		Networking code
 - post		Power On Self Test
 - rtc		Real Time Clock drivers
 - tools		Tools to build S-Record or U-Boot images, etc.
 Software Configuration:
 =======================
 Configuration is usually done using C preprocessor defines; the
 rationale behind that is to avoid dead code whenever possible.
 There are two classes of configuration variables:
 * Configuration _OPTIONS_:
   These are selectable by the user and have names beginning with
   "CONFIG_".
 * Configuration _SETTINGS_:
   These depend on the hardware etc. and should not be meddled with if
   you don't know what you're doing; they have names beginning with
   "CONFIG_SYS_".
 Later we will add a configuration tool - probably similar to or even
 identical to what's used for the Linux kernel. Right now, we have to
 do the configuration by hand, which means creating some symbolic
 links and editing some configuration files. We use the TQM8xxL boards
 as an example here.
 Selection of Processor Architecture and Board Type:
 ---------------------------------------------------
 For all supported boards there are ready-to-use default
 configurations available; just type "make <board_name>_config".
 Example: For a TQM823L module type:
 	cd u-boot
 	make TQM823L_config
 For the Cogent platform, you need to specify the CPU type as well;
 e.g. "make cogent_mpc8xx_config". And also configure the cogent
 directory according to the instructions in cogent/README.
 Configuration Options:
 ----------------------
 Configuration depends on the combination of board and CPU type; all
 such information is kept in a configuration file
 "include/configs/<board_name>.h".
 Example: For a TQM823L module, all configuration settings are in
 "include/configs/TQM823L.h".
 Many of the options are named exactly as the corresponding Linux
 kernel configuration options. The intention is to make it easier to
 build a config tool - later.
 The following options need to be configured:
 - CPU Type:	Define exactly one, e.g. CONFIG_MPC85XX.
 - Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
 		Define exactly one, e.g. CONFIG_ATSTK1002
 - CPU Module Type: (if CONFIG_COGENT is defined)
 		Define exactly one of
 		CONFIG_CMA286_60_OLD
 --- FIXME --- not tested yet:
 		CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P,
 		CONFIG_CMA287_23, CONFIG_CMA287_50
 - Motherboard Type: (if CONFIG_COGENT is defined)
 		Define exactly one of
 		CONFIG_CMA101, CONFIG_CMA102
 - Motherboard I/O Modules: (if CONFIG_COGENT is defined)
 		Define one or more of
 		CONFIG_CMA302
 - Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
 		Define one or more of
 		CONFIG_LCD_HEARTBEAT	- update a character position on
 					  the LCD display every second with
 					  a "rotator" |\-/|\-/
 - Board flavour: (if CONFIG_MPC8260ADS is defined)
 		CONFIG_ADSTYPE
 		Possible values are:
 			CONFIG_SYS_8260ADS	- original MPC8260ADS
 			CONFIG_SYS_8266ADS	- MPC8266ADS
 			CONFIG_SYS_PQ2FADS	- PQ2FADS-ZU or PQ2FADS-VR
 			CONFIG_SYS_8272ADS	- MPC8272ADS
 - MPC824X Family Member (if CONFIG_MPC824X is defined)
 		Define exactly one of
 		CONFIG_MPC8240, CONFIG_MPC8245
 - 8xx CPU Options: (if using an MPC8xx CPU)
 		CONFIG_8xx_GCLK_FREQ	- deprecated: CPU clock if
 					  get_gclk_freq() cannot work
 					  e.g. if there is no 32KHz
 					  reference PIT/RTC clock
 		CONFIG_8xx_OSCLK	- PLL input clock (either EXTCLK
 					  or XTAL/EXTAL)
 - 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
 		CONFIG_SYS_8xx_CPUCLK_MIN
 		CONFIG_SYS_8xx_CPUCLK_MAX
 		CONFIG_8xx_CPUCLK_DEFAULT
 			See doc/README.MPC866
 		CONFIG_SYS_MEASURE_CPUCLK
 		Define this to measure the actual CPU clock instead
 		of relying on the correctness of the configured
 		values. Mostly useful for board bringup to make sure
 		the PLL is locked at the intended frequency. Note
 		that this requires a (stable) reference clock (32 kHz
 		RTC clock or CONFIG_SYS_8XX_XIN)
 		CONFIG_SYS_DELAYED_ICACHE
 		Define this option if you want to enable the
 		ICache only when Code runs from RAM.
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 		Defines the Monahans run mode to oscillator
 		ratio. Valid values are 8, 16, 24, 31. The core
 		frequency is this value multiplied by 13 MHz.
 		CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
 		Defines the Monahans turbo mode to oscillator
 		ratio. Valid values are 1 (default if undefined) and
 		2. The core frequency as calculated above is multiplied
 		by this value.
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 		U-Boot stores all clock information in Hz
 		internally. For binary compatibility with older Linux
 		kernels (which expect the clocks passed in the
 		bd_info data to be in MHz) the environment variable
 		"clocks_in_mhz" can be defined so that U-Boot
 		converts clock data to MHZ before passing it to the
 		Linux kernel.
 		When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
 		"clocks_in_mhz=1" is automatically included in the
 		default environment.
 		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
 		When transferring memsize parameter to linux, some versions
 		expect it to be in bytes, others in MB.
 		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
 		CONFIG_OF_LIBFDT
 		New kernel versions are expecting firmware settings to be
 		passed using flattened device trees (based on open firmware
 		concepts).
 		CONFIG_OF_LIBFDT
 		 * New libfdt-based support
 		 * Adds the "fdt" command
 		 * The bootm command automatically updates the fdt
 		OF_CPU - The proper name of the cpus node.
 		OF_SOC - The proper name of the soc node.
 		OF_TBCLK - The timebase frequency.
 		OF_STDOUT_PATH - The path to the console device
 		boards with QUICC Engines require OF_QE to set UCC MAC
 		addresses
 		CONFIG_OF_BOARD_SETUP
 		Board code has addition modification that it wants to make
 		to the flat device tree before handing it off to the kernel
 		CONFIG_OF_BOOT_CPU
 		This define fills in the correct boot CPU in the boot
 		param header, the default value is zero if undefined.
 - vxWorks boot parameters:
 		bootvx constructs a valid bootline using the following
 		environments variables: bootfile, ipaddr, serverip, hostname.
 		It loads the vxWorks image pointed bootfile.
 		CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name
 		CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address
 		CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server
 		CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters
 		CONFIG_SYS_VXWORKS_ADD_PARAMS
 		Add it at the end of the bootline. E.g "u=username pw=secret"
 		Note: If a "bootargs" environment is defined, it will overwride
 		the defaults discussed just above.
 - Serial Ports:
 		CONFIG_PL010_SERIAL
 		Define this if you want support for Amba PrimeCell PL010 UARTs.
 		CONFIG_PL011_SERIAL
 		Define this if you want support for Amba PrimeCell PL011 UARTs.
 		CONFIG_PL011_CLOCK
 		If you have Amba PrimeCell PL011 UARTs, set this variable to
 		the clock speed of the UARTs.
 		CONFIG_PL01x_PORTS
 		If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
 		define this to a list of base addresses for each (supported)
 		port. See e.g. include/configs/versatile.h
 - Console Interface:
 		Depending on board, define exactly one serial port
 		(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
 		CONFIG_8xx_CONS_SCC1, ...), or switch off the serial
 		console by defining CONFIG_8xx_CONS_NONE
 		Note: if CONFIG_8xx_CONS_NONE is defined, the serial
 		port routines must be defined elsewhere
 		(i.e. serial_init(), serial_getc(), ...)
 		CONFIG_CFB_CONSOLE
 		Enables console device for a color framebuffer. Needs following
 		defines (cf. smiLynxEM, i8042, board/eltec/bab7xx)
 			VIDEO_FB_LITTLE_ENDIAN	graphic memory organisation
 						(default big endian)
 			VIDEO_HW_RECTFILL	graphic chip supports
 						rectangle fill
 						(cf. smiLynxEM)
 			VIDEO_HW_BITBLT		graphic chip supports
 						bit-blit (cf. smiLynxEM)
 			VIDEO_VISIBLE_COLS	visible pixel columns
 						(cols=pitch)
 			VIDEO_VISIBLE_ROWS	visible pixel rows
 			VIDEO_PIXEL_SIZE	bytes per pixel
 			VIDEO_DATA_FORMAT	graphic data format
 						(0-5, cf. cfb_console.c)
 			VIDEO_FB_ADRS		framebuffer address
 			VIDEO_KBD_INIT_FCT	keyboard int fct
 						(i.e. i8042_kbd_init())
 			VIDEO_TSTC_FCT		test char fct
 						(i.e. i8042_tstc)
 			VIDEO_GETC_FCT		get char fct
 						(i.e. i8042_getc)
 			CONFIG_CONSOLE_CURSOR	cursor drawing on/off
 						(requires blink timer
 						cf. i8042.c)
 			CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
 			CONFIG_CONSOLE_TIME	display time/date info in
 						upper right corner
 						(requires CONFIG_CMD_DATE)
 			CONFIG_VIDEO_LOGO	display Linux logo in
 						upper left corner
 			CONFIG_VIDEO_BMP_LOGO	use bmp_logo.h instead of
 						linux_logo.h for logo.
 						Requires CONFIG_VIDEO_LOGO
 			CONFIG_CONSOLE_EXTRA_INFO
 						additional board info beside
 						the logo
 		When CONFIG_CFB_CONSOLE is defined, video console is
 		default i/o. Serial console can be forced with
 		environment 'console=serial'.
 		When CONFIG_SILENT_CONSOLE is defined, all console
 		messages (by U-Boot and Linux!) can be silenced with
 		the "silent" environment variable. See
 		doc/README.silent for more information.
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
 		CONFIG_SYS_BAUDRATE_TABLE, see below.
 		CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
 - Console Rx buffer length
 		With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
 		the maximum receive buffer length for the SMC.
 		This option is actual only for 82xx and 8xx possible.
 		If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
 		must be defined, to setup the maximum idle timeout for
 		the SMC.
 - Interrupt driven serial port input:
 		CONFIG_SERIAL_SOFTWARE_FIFO
 		PPC405GP only.
 		Use an interrupt handler for receiving data on the
 		serial port. It also enables using hardware handshake
 		(RTS/CTS) and UART's built-in FIFO. Set the number of
 		bytes the interrupt driven input buffer should have.
 		Leave undefined to disable this feature, including
 		disable the buffer and hardware handshake.
 - Console UART Number:
 		CONFIG_UART1_CONSOLE
 		AMCC PPC4xx only.
 		If defined internal UART1 (and not UART0) is used
 		as default U-Boot console.
 - Boot Delay:	CONFIG_BOOTDELAY - in seconds
 		Delay before automatically booting the default image;
 		set to -1 to disable autoboot.
 		See doc/README.autoboot for these options that
 		work with CONFIG_BOOTDELAY. None are required.
 		CONFIG_BOOT_RETRY_TIME
 		CONFIG_BOOT_RETRY_MIN
 		CONFIG_AUTOBOOT_KEYED
 		CONFIG_AUTOBOOT_PROMPT
 		CONFIG_AUTOBOOT_DELAY_STR
 		CONFIG_AUTOBOOT_STOP_STR
 		CONFIG_AUTOBOOT_DELAY_STR2
 		CONFIG_AUTOBOOT_STOP_STR2
 		CONFIG_ZERO_BOOTDELAY_CHECK
 		CONFIG_RESET_TO_RETRY
 - Autoboot Command:
 		CONFIG_BOOTCOMMAND
 		Only needed when CONFIG_BOOTDELAY is enabled;
 		define a command string that is automatically executed
 		when no character is read on the console interface
 		within "Boot Delay" after reset.
 		CONFIG_BOOTARGS
 		This can be used to pass arguments to the bootm
 		command. The value of CONFIG_BOOTARGS goes into the
 		environment value "bootargs".
 		CONFIG_RAMBOOT and CONFIG_NFSBOOT
 		The value of these goes into the environment as
 		"ramboot" and "nfsboot" respectively, and can be used
 		as a convenience, when switching between booting from
 		RAM and NFS.
 - Pre-Boot Commands:
 		CONFIG_PREBOOT
 		When this option is #defined, the existence of the
 		environment variable "preboot" will be checked
 		immediately before starting the CONFIG_BOOTDELAY
 		countdown and/or running the auto-boot command resp.
 		entering interactive mode.
 		This feature is especially useful when "preboot" is
 		automatically generated or modified. For an example
 		see the LWMON board specific code: here "preboot" is
 		modified when the user holds down a certain
 		combination of keys on the (special) keyboard when
 		booting the systems
 - Serial Download Echo Mode:
 		CONFIG_LOADS_ECHO
 		If defined to 1, all characters received during a
 		serial download (using the "loads" command) are
 		echoed back. This might be needed by some terminal
 		emulations (like "cu"), but may as well just take
 		time on others. This setting #define's the initial
 		value of the "loads_echo" environment variable.
 - Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
 		CONFIG_KGDB_BAUDRATE
 		Select one of the baudrates listed in
 		CONFIG_SYS_BAUDRATE_TABLE, see below.
 - Monitor Functions:
 		Monitor commands can be included or excluded
 		from the build by using the #include files
 		"config_cmd_all.h" and #undef'ing unwanted
 		commands, or using "config_cmd_default.h"
 		and augmenting with additional #define's
 		for wanted commands.
 		The default command configuration includes all commands
 		except those marked below with a "*".
 		CONFIG_CMD_ASKENV	* ask for env variable
 		CONFIG_CMD_BDI		  bdinfo
 		CONFIG_CMD_BEDBUG	* Include BedBug Debugger
 		CONFIG_CMD_BMP		* BMP support
 		CONFIG_CMD_BSP		* Board specific commands
 		CONFIG_CMD_BOOTD	  bootd
 		CONFIG_CMD_CACHE	* icache, dcache
 		CONFIG_CMD_CONSOLE	  coninfo
 		CONFIG_CMD_DATE		* support for RTC, date/time...
 		CONFIG_CMD_DHCP		* DHCP support
 		CONFIG_CMD_DIAG		* Diagnostics
 		CONFIG_CMD_DOC		* Disk-On-Chip Support
 		CONFIG_CMD_DS4510	* ds4510 I2C gpio commands
 		CONFIG_CMD_DS4510_INFO	* ds4510 I2C info command
 		CONFIG_CMD_DS4510_MEM	* ds4510 I2C eeprom/sram commansd
 		CONFIG_CMD_DS4510_RST	* ds4510 I2C rst command
 		CONFIG_CMD_DTT		* Digital Therm and Thermostat
 		CONFIG_CMD_ECHO		  echo arguments
 		CONFIG_CMD_EEPROM	* EEPROM read/write support
 		CONFIG_CMD_ELF		* bootelf, bootvx
 		CONFIG_CMD_SAVEENV	  saveenv
 		CONFIG_CMD_FDC		* Floppy Disk Support
 		CONFIG_CMD_FAT		* FAT partition support
 		CONFIG_CMD_FDOS		* Dos diskette Support
 		CONFIG_CMD_FLASH	  flinfo, erase, protect
 		CONFIG_CMD_FPGA		  FPGA device initialization support
 		CONFIG_CMD_HWFLOW	* RTS/CTS hw flow control
 		CONFIG_CMD_I2C		* I2C serial bus support
 		CONFIG_CMD_IDE		* IDE harddisk support
 		CONFIG_CMD_IMI		  iminfo
 		CONFIG_CMD_IMLS		  List all found images
 		CONFIG_CMD_IMMAP	* IMMR dump support
 		CONFIG_CMD_IRQ		* irqinfo
 		CONFIG_CMD_ITEST	  Integer/string test of 2 values
 		CONFIG_CMD_JFFS2	* JFFS2 Support
 		CONFIG_CMD_KGDB		* kgdb
 		CONFIG_CMD_LOADB	  loadb
 		CONFIG_CMD_LOADS	  loads
 		CONFIG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 					  loop, loopw, mtest
 		CONFIG_CMD_MISC		  Misc functions like sleep etc
 		CONFIG_CMD_MMC		* MMC memory mapped support
 		CONFIG_CMD_MII		* MII utility commands
 		CONFIG_CMD_MTDPARTS	* MTD partition support
 		CONFIG_CMD_NAND		* NAND support
 		CONFIG_CMD_NET		  bootp, tftpboot, rarpboot
 		CONFIG_CMD_PCA953X	* PCA953x I2C gpio commands
 		CONFIG_CMD_PCA953X_INFO	* PCA953x I2C gpio info command
 		CONFIG_CMD_PCI		* pciinfo
 		CONFIG_CMD_PCMCIA		* PCMCIA support
 		CONFIG_CMD_PING		* send ICMP ECHO_REQUEST to network
 					  host
 		CONFIG_CMD_PORTIO	* Port I/O
 		CONFIG_CMD_REGINFO	* Register dump
 		CONFIG_CMD_RUN		  run command in env variable
 		CONFIG_CMD_SAVES	* save S record dump
 		CONFIG_CMD_SCSI		* SCSI Support
 		CONFIG_CMD_SDRAM	* print SDRAM configuration information
 					  (requires CONFIG_CMD_I2C)
 		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
 					  (4xx only)
 		CONFIG_CMD_SOURCE	  "source" command Support
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_USB		* USB support
 		CONFIG_CMD_VFD		* VFD support (TRAB)
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_FSL		* Microblaze FSL support
 		EXAMPLE: If you want all functions except of network
 		support you can write:
 		#include "config_cmd_all.h"
 		#undef CONFIG_CMD_NET
 	Other Commands:
 		fdt (flattened device tree) command: CONFIG_OF_LIBFDT
 	Note:	Don't enable the "icache" and "dcache" commands
 		(configuration option CONFIG_CMD_CACHE) unless you know
 		what you (and your U-Boot users) are doing. Data
 		cache cannot be enabled on systems like the 8xx or
 		8260 (where accesses to the IMMR region must be
 		uncached), and it cannot be disabled on all other
 		systems where we (mis-) use the data cache to hold an
 		initial stack and some data.
 		XXX - this list needs to get updated!
 - Watchdog:
 		CONFIG_WATCHDOG
 		If this variable is defined, it enables watchdog
 		support. There must be support in the platform specific
 		code for a watchdog. For the 8xx and 8260 CPUs, the
 		SIU Watchdog feature is enabled in the SYPCR
 		register.
 - U-Boot Version:
 		CONFIG_VERSION_VARIABLE
 		If this variable is defined, an environment variable
 		named "ver" is created by U-Boot showing the U-Boot
 		version as printed by the "version" command.
 		This variable is readonly.
 - Real-Time Clock:
 		When CONFIG_CMD_DATE is selected, the type of the RTC
 		has to be selected, too. Define exactly one of the
 		following options:
 		CONFIG_RTC_MPC8xx	- use internal RTC of MPC8xx
 		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
 		CONFIG_RTC_MC13783	- use MC13783 RTC
 		CONFIG_RTC_MC146818	- use MC146818 RTC
 		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
 		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
 		CONFIG_RTC_ISL1208	- use Intersil ISL1208 RTC
 		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC
 		CONFIG_SYS_RTC_DS1337_NOOSC	- Turn off the OSC output for DS1337
 		Note that if the RTC uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 - GPIO Support:
 		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
 		CONFIG_PCA953X_INFO	- enable pca953x info command
 		Note that if the GPIO device uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 - Timestamp Support:
 		When CONFIG_TIMESTAMP is selected, the timestamp
 		(date and time) of an image is printed by image
 		commands like bootm or iminfo. This option is
 		automatically enabled when you select CONFIG_CMD_DATE .
 - Partition Support:
 		CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION
 		and/or CONFIG_ISO_PARTITION and/or CONFIG_EFI_PARTITION
 		If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
 		CONFIG_CMD_SCSI) you must configure support for at
 		least one partition type as well.
 - IDE Reset method:
 		CONFIG_IDE_RESET_ROUTINE - this is defined in several
 		board configurations files but used nowhere!
 		CONFIG_IDE_RESET - is this is defined, IDE Reset will
 		be performed by calling the function
 			ide_set_reset(int reset)
 		which has to be defined in a board specific file
 - ATAPI Support:
 		CONFIG_ATAPI
 		Set this to enable ATAPI support.
 - LBA48 Support
 		CONFIG_LBA48
 		Set this to enable support for disks larger than 137GB
 		Also look at CONFIG_SYS_64BIT_LBA ,CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
 		Whithout these , LBA48 support uses 32bit variables and will 'only'
 		support disks up to 2.1TB.
 		CONFIG_SYS_64BIT_LBA:
 			When enabled, makes the IDE subsystem use 64bit sector addresses.
 			Default is 32bit.
 - SCSI Support:
 		At the moment only there is only support for the
 		SYM53C8XX SCSI controller; define
 		CONFIG_SCSI_SYM53C8XX to enable it.
 		CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
 		CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
 		CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
 		maximum numbers of LUNs, SCSI ID's and target
 		devices.
 		CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
 - NETWORK Support (PCI):
 		CONFIG_E1000
 		Support for Intel 8254x gigabit chips.
 		CONFIG_E1000_FALLBACK_MAC
 		default MAC for empty EEPROM after production.
 		CONFIG_EEPRO100
 		Support for Intel 82557/82559/82559ER chips.
 		Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
 		write routine for first time initialisation.
 		CONFIG_TULIP
 		Support for Digital 2114x chips.
 		Optional CONFIG_TULIP_SELECT_MEDIA for board specific
 		modem chip initialisation (KS8761/QS6611).
 		CONFIG_NATSEMI
 		Support for National dp83815 chips.
 		CONFIG_NS8382X
 		Support for National dp8382[01] gigabit chips.
 - NETWORK Support (other):
 		CONFIG_DRIVER_LAN91C96
 		Support for SMSC's LAN91C96 chips.
 			CONFIG_LAN91C96_BASE
 			Define this to hold the physical address
 			of the LAN91C96's I/O space
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 		CONFIG_DRIVER_SMC91111
 		Support for SMSC's LAN91C111 chip
 			CONFIG_SMC91111_BASE
 			Define this to hold the physical address
 			of the device (I/O space)
 			CONFIG_SMC_USE_32_BIT
 			Define this if data bus is 32 bits
 			CONFIG_SMC_USE_IOFUNCS
 			Define this to use i/o functions instead of macros
 			(some hardware wont work with macros)
 		CONFIG_DRIVER_SMC911X
 		Support for SMSC's LAN911x and LAN921x chips
 			CONFIG_DRIVER_SMC911X_BASE
 			Define this to hold the physical address
 			of the device (I/O space)
 			CONFIG_DRIVER_SMC911X_32_BIT
 			Define this if data bus is 32 bits
 			CONFIG_DRIVER_SMC911X_16_BIT
 			Define this if data bus is 16 bits. If your processor
 			automatically converts one 32 bit word to two 16 bit
 			words you may also try CONFIG_DRIVER_SMC911X_32_BIT.
 - USB Support:
 		At the moment only the UHCI host controller is
 		supported (PIP405, MIP405, MPC5200); define
 		CONFIG_USB_UHCI to enable it.
 		define CONFIG_USB_KEYBOARD to enable the USB Keyboard
 		and define CONFIG_USB_STORAGE to enable the USB
 		storage devices.
 		Note:
 		Supported are USB Keyboards and USB Floppy drives
 		(TEAC FD-05PUB).
 		MPC5200 USB requires additional defines:
 			CONFIG_USB_CLOCK
 				for 528 MHz Clock: 0x0001bbbb
 			CONFIG_USB_CONFIG
 				for differential drivers: 0x00001000
 				for single ended drivers: 0x00005000
 			CONFIG_SYS_USB_EVENT_POLL
 				May be defined to allow interrupt polling
 				instead of using asynchronous interrupts
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the
 		command "setenv stdin usbtty; setenv stdout usbtty" and
 		attach your USB cable. The Unix command "dmesg" should print
 		it has found a new device. The environment variable usbtty
 		can be set to gserial or cdc_acm to enable your device to
 		appear to a USB host as a Linux gserial device or a
 		Common Device Class Abstract Control Model serial device.
 		If you select usbtty = gserial you should be able to enumerate
 		a Linux host by
 		# modprobe usbserial vendor=0xVendorID product=0xProductID
 		else if using cdc_acm, simply setting the environment
 		variable usbtty to be cdc_acm should suffice. The following
 		might be defined in YourBoardName.h
 			CONFIG_USB_DEVICE
 			Define this to build a UDC device
 			CONFIG_USB_TTY
 			Define this to have a tty type of device available to
 			talk to the UDC device
 			CONFIG_SYS_CONSOLE_IS_IN_ENV
 			Define this if you want stdin, stdout &/or stderr to
 			be set to usbtty.
 			mpc8xx:
 				CONFIG_SYS_USB_EXTC_CLK 0xBLAH
 				Derive USB clock from external clock "blah"
 				- CONFIG_SYS_USB_EXTC_CLK 0x02
 				CONFIG_SYS_USB_BRG_CLK 0xBLAH
 				Derive USB clock from brgclk
 				- CONFIG_SYS_USB_BRG_CLK 0x04
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
 		CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME,
 		CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot
 		should pretend to be a Linux device to it's target host.
 			CONFIG_USBD_MANUFACTURER
 			Define this string as the name of your company for
 			- CONFIG_USBD_MANUFACTURER "my company"
 			CONFIG_USBD_PRODUCT_NAME
 			Define this string as the name of your product
 			- CONFIG_USBD_PRODUCT_NAME "acme usb device"
 			CONFIG_USBD_VENDORID
 			Define this as your assigned Vendor ID from the USB
 			Implementors Forum. This *must* be a genuine Vendor ID
 			to avoid polluting the USB namespace.
 			- CONFIG_USBD_VENDORID 0xFFFF
 			CONFIG_USBD_PRODUCTID
 			Define this as the unique Product ID
 			for your device
 			- CONFIG_USBD_PRODUCTID 0xFFFF
 - MMC Support:
 		The MMC controller on the Intel PXA is supported. To
 		enable this define CONFIG_MMC. The MMC can be
 		accessed from the boot prompt by mapping the device
 		to physical memory similar to flash. Command line is
 		enabled with CONFIG_CMD_MMC. The MMC driver also works with
 		the FAT fs. This is enabled with CONFIG_CMD_FAT.
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
 		CONFIG_JFFS2_NAND_DEV
 		Define these for a default partition on a NAND device
 		CONFIG_SYS_JFFS2_FIRST_SECTOR,
 		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
 		Define these for a default partition on a NOR device
 		CONFIG_SYS_JFFS_CUSTOM_PART
 		Define this to create an own partition. You have to provide a
 		function struct part_info* jffs2_part_info(int part_num)
 		If you define only one JFFS2 partition you may also want to
 		#define CONFIG_SYS_JFFS_SINGLE_PART	1
 		to disable the command chpart. This is the default when you
 		have not defined a custom partition
 - Keyboard Support:
 		CONFIG_ISA_KEYBOARD
 		Define this to enable standard (PC-Style) keyboard
 		support
 		CONFIG_I8042_KBD
 		Standard PC keyboard driver with US (is default) and
 		GERMAN key layout (switch via environment 'keymap=de') support.
 		Export function i8042_kbd_init, i8042_tstc and i8042_getc
 		for cfb_console. Supports cursor blinking.
 - Video support:
 		CONFIG_VIDEO
 		Define this to enable video support (for output to
 		video).
 		CONFIG_VIDEO_CT69000
 		Enable Chips & Technologies 69000 Video chip
 		CONFIG_VIDEO_SMI_LYNXEM
 		Enable Silicon Motion SMI 712/710/810 Video chip. The
 		video output is selected via environment 'videoout'
 		(1 = LCD and 2 = CRT). If videoout is undefined, CRT is
 		assumed.
 		For the CT69000 and SMI_LYNXEM drivers, videomode is
 		selected via environment 'videomode'. Two different ways
 		are possible:
 		- "videomode=num"   'num' is a standard LiLo mode numbers.
 		Following standard modes are supported	(* is default):
 		      Colors	640x480 800x600 1024x768 1152x864 1280x1024
 		-------------+---------------------------------------------
 		      8 bits |	0x301*	0x303	 0x305	  0x161	    0x307
 		     15 bits |	0x310	0x313	 0x316	  0x162	    0x319
 		     16 bits |	0x311	0x314	 0x317	  0x163	    0x31A
 		     24 bits |	0x312	0x315	 0x318	    ?	    0x31B
 		-------------+---------------------------------------------
 		(i.e. setenv videomode 317; saveenv; reset;)
 		- "videomode=bootargs" all the video parameters are parsed
 		from the bootargs. (See drivers/video/videomodes.c)
 		CONFIG_VIDEO_SED13806
 		Enable Epson SED13806 driver. This driver supports 8bpp
 		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
 		or CONFIG_VIDEO_SED13806_16BPP
 - Keyboard Support:
 		CONFIG_KEYBOARD
 		Define this to enable a custom keyboard support.
 		This simply calls drv_keyboard_init() which must be
 		defined in your board-specific files.
 		The only board using this so far is RBC823.
 - LCD Support:	CONFIG_LCD
 		Define this to enable LCD support (for output to LCD
 		display); also select one of the supported displays
 		by defining one of these:
 		CONFIG_ATMEL_LCD:
 			HITACHI TX09D70VM1CCA, 3.5", 240x320.
 		CONFIG_NEC_NL6448AC33:
 			NEC NL6448AC33-18. Active, color, single scan.
 		CONFIG_NEC_NL6448BC20
 			NEC NL6448BC20-08. 6.5", 640x480.
 			Active, color, single scan.
 		CONFIG_NEC_NL6448BC33_54
 			NEC NL6448BC33-54. 10.4", 640x480.
 			Active, color, single scan.
 		CONFIG_SHARP_16x9
 			Sharp 320x240. Active, color, single scan.
 			It isn't 16x9, and I am not sure what it is.
 		CONFIG_SHARP_LQ64D341
 			Sharp LQ64D341 display, 640x480.
 			Active, color, single scan.
 		CONFIG_HLD1045
 			HLD1045 display, 640x480.
 			Active, color, single scan.
 		CONFIG_OPTREX_BW
 			Optrex	 CBL50840-2 NF-FW 99 22 M5
 			or
 			Hitachi	 LMG6912RPFC-00T
 			or
 			Hitachi	 SP14Q002
 			320x240. Black & white.
 		Normally display is black on white background; define
 		CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
 - Splash Screen Support: CONFIG_SPLASH_SCREEN
 		If this option is set, the environment is checked for
 		a variable "splashimage". If found, the usual display
 		of logo, copyright and system information on the LCD
 		is suppressed and the BMP image at the address
 		specified in "splashimage" is loaded instead. The
 		console is redirected to the "nulldev", too. This
 		allows for a "silent" boot where a splash screen is
 		loaded very quickly after power-on.
 - Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
 		If this option is set, additionally to standard BMP
 		images, gzipped BMP images can be displayed via the
 		splashscreen support or the bmp command.
 - Compression support:
 		CONFIG_BZIP2
 		If this option is set, support for bzip2 compressed
 		images is included. If not, only uncompressed and gzip
 		compressed images are supported.
 		NOTE: the bzip2 algorithm requires a lot of RAM, so
 		the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
 		be at least 4MB.
 		CONFIG_LZMA
 		If this option is set, support for lzma compressed
 		images is included.
 		Note: The LZMA algorithm adds between 2 and 4KB of code and it
 		requires an amount of dynamic memory that is given by the
 		formula:
 			(1846 + 768 << (lc + lp)) * sizeof(uint16)
 		Where lc and lp stand for, respectively, Literal context bits
 		and Literal pos bits.
 		This value is upper-bounded by 14MB in the worst case. Anyway,
 		for a ~4MB large kernel image, we have lc=3 and lp=0 for a
 		total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is
 		a very small buffer.
 		Use the lzmainfo tool to determinate the lc and lp values and
 		then calculate the amount of needed dynamic memory (ensuring
 		the appropriate CONFIG_SYS_MALLOC_LEN value).
 - MII/PHY support:
 		CONFIG_PHY_ADDR
 		The address of PHY on MII bus.
 		CONFIG_PHY_CLOCK_FREQ (ppc4xx)
 		The clock frequency of the MII bus
 		CONFIG_PHY_GIGE
 		If this option is set, support for speed/duplex
 		detection of gigabit PHY is included.
 		CONFIG_PHY_RESET_DELAY
 		Some PHY like Intel LXT971A need extra delay after
 		reset before any MII register access is possible.
 		For such PHY, set this option to the usec delay
 		required. (minimum 300usec for LXT971A)
 		CONFIG_PHY_CMD_DELAY (ppc4xx)
 		Some PHY like Intel LXT971A need extra delay after
 		command issued before MII status register can be read
 - Ethernet address:
 		CONFIG_ETHADDR
 		CONFIG_ETH1ADDR
 		CONFIG_ETH2ADDR
 		CONFIG_ETH3ADDR
 		CONFIG_ETH4ADDR
 		CONFIG_ETH5ADDR
 		Define a default value for Ethernet address to use
 		for the respective Ethernet interface, in case this
 		is not determined automatically.
 - IP address:
 		CONFIG_IPADDR
 		Define a default value for the IP address to use for
 		the default Ethernet interface, in case this is not
 		determined through e.g. bootp.
 - Server IP address:
 		CONFIG_SERVERIP
 		Defines a default value for the IP address of a TFTP
 		server to contact when using the "tftboot" command.
 - Multicast TFTP Mode:
 		CONFIG_MCAST_TFTP
 		Defines whether you want to support multicast TFTP as per
 		rfc-2090; for example to work with atftp.  Lets lots of targets
 		tftp down the same boot image concurrently.  Note: the Ethernet
 		driver in use must provide a function: mcast() to join/leave a
 		multicast group.
 		CONFIG_BOOTP_RANDOM_DELAY
 - BOOTP Recovery Mode:
 		CONFIG_BOOTP_RANDOM_DELAY
 		If you have many targets in a network that try to
 		boot using BOOTP, you may want to avoid that all
 		systems send out BOOTP requests at precisely the same
 		moment (which would happen for instance at recovery
 		from a power failure, when all systems will try to
 		boot, thus flooding the BOOTP server. Defining
 		CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
 		inserted before sending out BOOTP requests. The
 		following delays are inserted then:
 		1st BOOTP request:	delay 0 ... 1 sec
 		2nd BOOTP request:	delay 0 ... 2 sec
 		3rd BOOTP request:	delay 0 ... 4 sec
 		4th and following
 		BOOTP requests:		delay 0 ... 8 sec
 - DHCP Advanced Options:
 		You can fine tune the DHCP functionality by defining
 		CONFIG_BOOTP_* symbols:
 		CONFIG_BOOTP_SUBNETMASK
 		CONFIG_BOOTP_GATEWAY
 		CONFIG_BOOTP_HOSTNAME
 		CONFIG_BOOTP_NISDOMAIN
 		CONFIG_BOOTP_BOOTPATH
 		CONFIG_BOOTP_BOOTFILESIZE
 		CONFIG_BOOTP_DNS
 		CONFIG_BOOTP_DNS2
 		CONFIG_BOOTP_SEND_HOSTNAME
 		CONFIG_BOOTP_NTPSERVER
 		CONFIG_BOOTP_TIMEOFFSET
 		CONFIG_BOOTP_VENDOREX
 		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
 		environment variable, not the BOOTP server.
 		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
 		serverip from a DHCP server, it is possible that more
 		than one DNS serverip is offered to the client.
 		If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
 		serverip will be stored in the additional environment
 		variable "dnsip2". The first DNS serverip is always
 		stored in the variable "dnsip", when CONFIG_BOOTP_DNS
 		is defined.
 		CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
 		to do a dynamic update of a DNS server. To do this, they
 		need the hostname of the DHCP requester.
 		If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
 		of the "hostname" environment variable is passed as
 		option 12 to the DHCP server.
 		CONFIG_BOOTP_DHCP_REQUEST_DELAY
 		A 32bit value in microseconds for a delay between
 		receiving a "DHCP Offer" and sending the "DHCP Request".
 		This fixes a problem with certain DHCP servers that don't
 		respond 100% of the time to a "DHCP request". E.g. On an
 		AT91RM9200 processor running at 180MHz, this delay needed
 		to be *at least* 15,000 usec before a Windows Server 2003
 		DHCP server would reply 100% of the time. I recommend at
 		least 50,000 usec to be safe. The alternative is to hope
 		that one of the retries will be successful but note that
 		the DHCP timeout and retry process takes a longer than
 		this delay.
  - CDP Options:
 		CONFIG_CDP_DEVICE_ID
 		The device id used in CDP trigger frames.
 		CONFIG_CDP_DEVICE_ID_PREFIX
 		A two character string which is prefixed to the MAC address
 		of the device.
 		CONFIG_CDP_PORT_ID
 		A printf format string which contains the ascii name of
 		the port. Normally is set to "eth%d" which sets
 		eth0 for the first Ethernet, eth1 for the second etc.
 		CONFIG_CDP_CAPABILITIES
 		A 32bit integer which indicates the device capabilities;
 		0x00000010 for a normal host which does not forwards.
 		CONFIG_CDP_VERSION
 		An ascii string containing the version of the software.
 		CONFIG_CDP_PLATFORM
 		An ascii string containing the name of the platform.
 		CONFIG_CDP_TRIGGER
 		A 32bit integer sent on the trigger.
 		CONFIG_CDP_POWER_CONSUMPTION
 		A 16bit integer containing the power consumption of the
 		device in .1 of milliwatts.
 		CONFIG_CDP_APPLIANCE_VLAN_TYPE
 		A byte containing the id of the VLAN.
 - Status LED:	CONFIG_STATUS_LED
 		Several configurations allow to display the current
 		status using a LED. For instance, the LED will blink
 		fast while running U-Boot code, stop blinking as
 		soon as a reply to a BOOTP request was received, and
 		start blinking slow once the Linux kernel is running
 		(supported by a status LED driver in the Linux
 		kernel). Defining CONFIG_STATUS_LED enables this
 		feature in U-Boot.
 - CAN Support:	CONFIG_CAN_DRIVER
 		Defining CONFIG_CAN_DRIVER enables CAN driver support
 		on those systems that support this (optional)
 		feature, like the TQM8xxL modules.
 - I2C Support:	CONFIG_HARD_I2C | CONFIG_SOFT_I2C
 		These enable I2C serial bus commands. Defining either of
 		(but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will
 		include the appropriate I2C driver for the selected CPU.
 		This will allow you to use i2c commands at the u-boot
 		command line (as long as you set CONFIG_CMD_I2C in
 		CONFIG_COMMANDS) and communicate with i2c based realtime
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
-		CONFIG_I2C_CMD_TREE is a recommended option that places
-		all I2C commands under a single 'i2c' root command.  The
-		older 'imm', 'imd', 'iprobe' etc. commands are considered
-		deprecated and may disappear in the future.
 		CONFIG_HARD_I2C selects a hardware I2C controller.
 		CONFIG_SOFT_I2C configures u-boot to use a software (aka
 		bit-banging) driver instead of CPM or similar hardware
 		support for I2C.
 		There are several other quantities that must also be
 		defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C.
 		In both cases you will need to define CONFIG_SYS_I2C_SPEED
 		to be the frequency (in Hz) at which you wish your i2c bus
 		to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
 		the CPU's i2c node address).
 		Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
 		sets the CPU up as a master node and so its address should
 		therefore be cleared to 0 (See, eg, MPC823e User's Manual
 		p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0.
 		That's all that's required for CONFIG_HARD_I2C.
 		If you use the software i2c interface (CONFIG_SOFT_I2C)
 		then the following macros need to be defined (examples are
 		from include/configs/lwmon.h):
 		I2C_INIT
 		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.
 		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
 		I2C_PORT
 		(Only for MPC8260 CPU). The I/O port to use (the code
 		assumes both bits are on the same port). Valid values
 		are 0..3 for ports A..D.
 		I2C_ACTIVE
 		The code necessary to make the I2C data line active
 		(driven).  If the data line is open collector, this
 		define can be null.
 		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)
 		I2C_TRISTATE
 		The code necessary to make the I2C data line tri-stated
 		(inactive).  If the data line is open collector, this
 		define can be null.
 		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 		I2C_READ
 		Code that returns TRUE if the I2C data line is high,
 		FALSE if it is low.
 		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 		I2C_SDA(bit)
 		If <bit> is TRUE, sets the I2C data line high. If it
 		is FALSE, it clears it (low).
 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
 		I2C_SCL(bit)
 		If <bit> is TRUE, sets the I2C clock line high. If it
 		is FALSE, it clears it (low).
 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 		I2C_DELAY
 		This delay is invoked four times per clock cycle so this
 		controls the rate of data transfer.  The data rate thus
 		is 1 / (I2C_DELAY * 4). Often defined to be something
 		like:
 		#define I2C_DELAY  udelay(2)
 		CONFIG_SYS_I2C_INIT_BOARD
 		When a board is reset during an i2c bus transfer
 		chips might think that the current transfer is still
 		in progress. On some boards it is possible to access
 		the i2c SCLK line directly, either by using the
 		processor pin as a GPIO or by having a second pin
 		connected to the bus. If this option is defined a
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.
 		CONFIG_I2CFAST (PPC405GP|PPC405EP only)
 		This option enables configuration of bi_iic_fast[] flags
 		in u-boot bd_info structure based on u-boot environment
 		variable "i2cfast". (see also i2cfast)
 		CONFIG_I2C_MULTI_BUS
 		This option allows the use of multiple I2C buses, each of which
 		must have a controller.  At any point in time, only one bus is
 		active.  To switch to a different bus, use the 'i2c dev' command.
 		Note that bus numbering is zero-based.
 		CONFIG_SYS_I2C_NOPROBES
 		This option specifies a list of I2C devices that will be skipped
 		when the 'i2c probe' command is issued (or 'iprobe' using the legacy
 		command).  If CONFIG_I2C_MULTI_BUS is set, specify a list of bus-device
 		pairs.	Otherwise, specify a 1D array of device addresses
 		e.g.
 			#undef	CONFIG_I2C_MULTI_BUS
 			#define CONFIG_SYS_I2C_NOPROBES	{0x50,0x68}
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 			#define	CONFIG_I2C_MULTI_BUS
 			#define CONFIG_SYS_I2C_MULTI_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 		CONFIG_SYS_SPD_BUS_NUM
 		If defined, then this indicates the I2C bus number for DDR SPD.
 		If not defined, then U-Boot assumes that SPD is on I2C bus 0.
 		CONFIG_SYS_RTC_BUS_NUM
 		If defined, then this indicates the I2C bus number for the RTC.
 		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
 		CONFIG_SYS_DTT_BUS_NUM
 		If defined, then this indicates the I2C bus number for the DTT.
 		If not defined, then U-Boot assumes that DTT is on I2C bus 0.
 		CONFIG_SYS_I2C_DTT_ADDR:
 		If defined, specifies the I2C address of the DTT device.
 		If not defined, then U-Boot uses predefined value for
 		specified DTT device.
 		CONFIG_FSL_I2C
 		Define this option if you want to use Freescale's I2C driver in
 		drivers/i2c/fsl_i2c.c.
 		CONFIG_I2C_MUX
 		Define this option if you have I2C devices reached over 1 .. n
 		I2C Muxes like the pca9544a. This option addes a new I2C
 		Command "i2c bus [muxtype:muxaddr:muxchannel]" which adds a
 		new I2C Bus to the existing I2C Busses. If you select the
 		new Bus with "i2c dev", u-bbot sends first the commandos for
 		the muxes to activate this new "bus".
 		CONFIG_I2C_MULTI_BUS must be also defined, to use this
 		feature!
 		Example:
 		Adding a new I2C Bus reached over 2 pca9544a muxes
 			The First mux with address 70 and channel 6
 			The Second mux with address 71 and channel 4
 		=> i2c bus pca9544a:70:6:pca9544a:71:4
 		Use the "i2c bus" command without parameter, to get a list
 		of I2C Busses with muxes:
 		=> i2c bus
 		Busses reached over muxes:
 		Bus ID: 2
 		  reached over Mux(es):
 		    pca9544a@70 ch: 4
 		Bus ID: 3
 		  reached over Mux(es):
 		    pca9544a@70 ch: 6
 		    pca9544a@71 ch: 4
 		=>
 		If you now switch to the new I2C Bus 3 with "i2c dev 3"
 		u-boot sends First the Commando to the mux@70 to enable
 		channel 6, and then the Commando to the mux@71 to enable
 		the channel 4.
 		After that, you can use the "normal" i2c commands as
 		usual, to communicate with your I2C devices behind
 		the 2 muxes.
 		This option is actually implemented for the bitbanging
 		algorithm in common/soft_i2c.c and for the Hardware I2C
 		Bus on the MPC8260. But it should be not so difficult
 		to add this option to other architectures.
 		CONFIG_SOFT_I2C_READ_REPEATED_START
 		defining this will force the i2c_read() function in
 		the soft_i2c driver to perform an I2C repeated start
 		between writing the address pointer and reading the
 		data.  If this define is omitted the default behaviour
 		of doing a stop-start sequence will be used.  Most I2C
 		devices can use either method, but some require one or
 		the other.
 - SPI Support:	CONFIG_SPI
 		Enables SPI driver (so far only tested with
 		SPI EEPROM, also an instance works with Crystal A/D and
 		D/As on the SACSng board)
 		CONFIG_SPI_X
 		Enables extended (16-bit) SPI EEPROM addressing.
 		(symmetrical to CONFIG_I2C_X)
 		CONFIG_SOFT_SPI
 		Enables a software (bit-bang) SPI driver rather than
 		using hardware support. This is a general purpose
 		driver that only requires three general I/O port pins
 		(two outputs, one input) to function. If this is
 		defined, the board configuration must define several
 		SPI configuration items (port pins to use, etc). For
 		an example, see include/configs/sacsng.h.
 		CONFIG_HARD_SPI
 		Enables a hardware SPI driver for general-purpose reads
 		and writes.  As with CONFIG_SOFT_SPI, the board configuration
 		must define a list of chip-select function pointers.
 		Currently supported on some MPC8xxx processors.  For an
 		example, see include/configs/mpc8349emds.h.
 		CONFIG_MXC_SPI
 		Enables the driver for the SPI controllers on i.MX and MXC
 		SoCs. Currently only i.MX31 is supported.
 - FPGA Support: CONFIG_FPGA
 		Enables FPGA subsystem.
 		CONFIG_FPGA_<vendor>
 		Enables support for specific chip vendors.
 		(ALTERA, XILINX)
 		CONFIG_FPGA_<family>
 		Enables support for FPGA family.
 		(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
 		CONFIG_FPGA_COUNT
 		Specify the number of FPGA devices to support.
 		CONFIG_SYS_FPGA_PROG_FEEDBACK
 		Enable printing of hash marks during FPGA configuration.
 		CONFIG_SYS_FPGA_CHECK_BUSY
 		Enable checks on FPGA configuration interface busy
 		status by the configuration function. This option
 		will require a board or device specific function to
 		be written.
 		CONFIG_FPGA_DELAY
 		If defined, a function that provides delays in the FPGA
 		configuration driver.
 		CONFIG_SYS_FPGA_CHECK_CTRLC
 		Allow Control-C to interrupt FPGA configuration
 		CONFIG_SYS_FPGA_CHECK_ERROR
 		Check for configuration errors during FPGA bitfile
 		loading. For example, abort during Virtex II
 		configuration if the INIT_B line goes low (which
 		indicated a CRC error).
 		CONFIG_SYS_FPGA_WAIT_INIT
 		Maximum time to wait for the INIT_B line to deassert
 		after PROB_B has been deasserted during a Virtex II
 		FPGA configuration sequence. The default time is 500
 		ms.
 		CONFIG_SYS_FPGA_WAIT_BUSY
 		Maximum time to wait for BUSY to deassert during
 		Virtex II FPGA configuration. The default is 5 ms.
 		CONFIG_SYS_FPGA_WAIT_CONFIG
 		Time to wait after FPGA configuration. The default is
 		200 ms.
 - Configuration Management:
 		CONFIG_IDENT_STRING
 		If defined, this string will be added to the U-Boot
 		version information (U_BOOT_VERSION)
 - Vendor Parameter Protection:
 		U-Boot considers the values of the environment
 		variables "serial#" (Board Serial Number) and
 		"ethaddr" (Ethernet Address) to be parameters that
 		are set once by the board vendor / manufacturer, and
 		protects these variables from casual modification by
 		the user. Once set, these variables are read-only,
 		and write or delete attempts are rejected. You can
 		change this behaviour:
 		If CONFIG_ENV_OVERWRITE is #defined in your config
 		file, the write protection for vendor parameters is
 		completely disabled. Anybody can change or delete
 		these parameters.
 		Alternatively, if you #define _both_ CONFIG_ETHADDR
 		_and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
 		Ethernet address is installed in the environment,
 		which can be changed exactly ONCE by the user. [The
 		serial# is unaffected by this, i. e. it remains
 		read-only.]
 - Protected RAM:
 		CONFIG_PRAM
 		Define this variable to enable the reservation of
 		"protected RAM", i. e. RAM which is not overwritten
 		by U-Boot. Define CONFIG_PRAM to hold the number of
 		kB you want to reserve for pRAM. You can overwrite
 		this default value by defining an environment
 		variable "pram" to the number of kB you want to
 		reserve. Note that the board info structure will
 		still show the full amount of RAM. If pRAM is
 		reserved, a new environment variable "mem" will
 		automatically be defined to hold the amount of
 		remaining RAM in a form that can be passed as boot
 		argument to Linux, for instance like that:
 			setenv bootargs ... mem=\${mem}
 			saveenv
 		This way you can tell Linux not to use this memory,
 		either, which results in a memory region that will
 		not be affected by reboots.
 		*WARNING* If your board configuration uses automatic
 		detection of the RAM size, you must make sure that
 		this memory test is non-destructive. So far, the
 		following board configurations are known to be
 		"pRAM-clean":
 			ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
 			HERMES, IP860, RPXlite, LWMON, LANTEC,
 			PCU_E, FLAGADM, TQM8260
 - Error Recovery:
 		CONFIG_PANIC_HANG
 		Define this variable to stop the system in case of a
 		fatal error, so that you have to reset it manually.
 		This is probably NOT a good idea for an embedded
 		system where you want the system to reboot
 		automatically as fast as possible, but it may be
 		useful during development since you can try to debug
 		the conditions that lead to the situation.
 		CONFIG_NET_RETRY_COUNT
 		This variable defines the number of retries for
 		network operations like ARP, RARP, TFTP, or BOOTP
 		before giving up the operation. If not defined, a
 		default value of 5 is used.
 		CONFIG_ARP_TIMEOUT
 		Timeout waiting for an ARP reply in milliseconds.
 - Command Interpreter:
 		CONFIG_AUTO_COMPLETE
 		Enable auto completion of commands using TAB.
 		Note that this feature has NOT been implemented yet
 		for the "hush" shell.
 		CONFIG_SYS_HUSH_PARSER
 		Define this variable to enable the "hush" shell (from
 		Busybox) as command line interpreter, thus enabling
 		powerful command line syntax like
 		if...then...else...fi conditionals or `&&' and '||'
 		constructs ("shell scripts").
 		If undefined, you get the old, much simpler behaviour
 		with a somewhat smaller memory footprint.
 		CONFIG_SYS_PROMPT_HUSH_PS2
 		This defines the secondary prompt string, which is
 		printed when the command interpreter needs more input
 		to complete a command. Usually "> ".
 	Note:
 		In the current implementation, the local variables
 		space and global environment variables space are
 		separated. Local variables are those you define by
 		simply typing `name=value'. To access a local
 		variable later on, you have write `$name' or
 		`${name}'; to execute the contents of a variable
 		directly type `$name' at the command prompt.
 		Global environment variables are those you use
 		setenv/printenv to work with. To run a command stored
 		in such a variable, you need to use the run command,
 		and you must not use the '$' sign to access them.
 		To store commands and special characters in a
 		variable, please use double quotation marks
 		surrounding the whole text of the variable, instead
 		of the backslashes before semicolons and special
 		symbols.
 - Commandline Editing and History:
 		CONFIG_CMDLINE_EDITING
 		Enable editing and History functions for interactive
 		commandline input operations
 - Default Environment:
 		CONFIG_EXTRA_ENV_SETTINGS
 		Define this to contain any number of null terminated
 		strings (variable = value pairs) that will be part of
 		the default environment compiled into the boot image.
 		For example, place something like this in your
 		board's config file:
 		#define CONFIG_EXTRA_ENV_SETTINGS \
 			"myvar1=value1\0" \
 			"myvar2=value2\0"
 		Warning: This method is based on knowledge about the
 		internal format how the environment is stored by the
 		U-Boot code. This is NOT an official, exported
 		interface! Although it is unlikely that this format
 		will change soon, there is no guarantee either.
 		You better know what you are doing here.
 		Note: overly (ab)use of the default environment is
 		discouraged. Make sure to check other ways to preset
 		the environment like the "source" command or the
 		boot command first.
 - DataFlash Support:
 		CONFIG_HAS_DATAFLASH
 		Defining this option enables DataFlash features and
 		allows to read/write in Dataflash via the standard
 		commands cp, md...
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 		Adding this option adds support for Xilinx SystemACE
 		chips attached via some sort of local bus. The address
 		of the chip must also be defined in the
 		CONFIG_SYS_SYSTEMACE_BASE macro. For example:
 		#define CONFIG_SYSTEMACE
 		#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
 		When SystemACE support is added, the "ace" device type
 		becomes available to the fat commands, i.e. fatls.
 - TFTP Fixed UDP Port:
 		CONFIG_TFTP_PORT
 		If this is defined, the environment variable tftpsrcp
 		is used to supply the TFTP UDP source port value.
 		If tftpsrcp isn't defined, the normal pseudo-random port
 		number generator is used.
 		Also, the environment variable tftpdstp is used to supply
 		the TFTP UDP destination port value.  If tftpdstp isn't
 		defined, the normal port 69 is used.
 		The purpose for tftpsrcp is to allow a TFTP server to
 		blindly start the TFTP transfer using the pre-configured
 		target IP address and UDP port. This has the effect of
 		"punching through" the (Windows XP) firewall, allowing
 		the remainder of the TFTP transfer to proceed normally.
 		A better solution is to properly configure the firewall,
 		but sometimes that is not allowed.
 - Show boot progress:
 		CONFIG_SHOW_BOOT_PROGRESS
 		Defining this option allows to add some board-
 		specific code (calling a user-provided function
 		"show_boot_progress(int)") that enables you to show
 		the system's boot progress on some display (for
 		example, some LED's) on your board. At the moment,
 		the following checkpoints are implemented:
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
 		CONFIG_UPDATE_TFTP_MSEC_MAX
 		These options enable and control the auto-update feature;
 		for a more detailed description refer to doc/README.update.
 Legacy uImage format:
   Arg	Where			When
     1	common/cmd_bootm.c	before attempting to boot an image
    -1	common/cmd_bootm.c	Image header has bad	 magic number
     2	common/cmd_bootm.c	Image header has correct magic number
    -2	common/cmd_bootm.c	Image header has bad	 checksum
     3	common/cmd_bootm.c	Image header has correct checksum
    -3	common/cmd_bootm.c	Image data   has bad	 checksum
     4	common/cmd_bootm.c	Image data   has correct checksum
    -4	common/cmd_bootm.c	Image is for unsupported architecture
     5	common/cmd_bootm.c	Architecture check OK
    -5	common/cmd_bootm.c	Wrong Image Type (not kernel, multi)
     6	common/cmd_bootm.c	Image Type check OK
    -6	common/cmd_bootm.c	gunzip uncompression error
    -7	common/cmd_bootm.c	Unimplemented compression type
     7	common/cmd_bootm.c	Uncompression OK
     8	common/cmd_bootm.c	No uncompress/copy overwrite error
    -9	common/cmd_bootm.c	Unsupported OS (not Linux, BSD, VxWorks, QNX)
     9	common/image.c		Start initial ramdisk verification
   -10	common/image.c		Ramdisk header has bad	   magic number
   -11	common/image.c		Ramdisk header has bad	   checksum
    10	common/image.c		Ramdisk header is OK
   -12	common/image.c		Ramdisk data   has bad	   checksum
    11	common/image.c		Ramdisk data   has correct checksum
    12	common/image.c		Ramdisk verification complete, start loading
   -13	common/image.c		Wrong Image Type (not PPC Linux ramdisk)
    13	common/image.c		Start multifile image verification
    14	common/image.c		No initial ramdisk, no multifile, continue.
    15	lib_<arch>/bootm.c	All preparation done, transferring control to OS
   -30	lib_ppc/board.c		Fatal error, hang the system
   -31	post/post.c		POST test failed, detected by post_output_backlog()
   -32	post/post.c		POST test failed, detected by post_run_single()
    34	common/cmd_doc.c	before loading a Image from a DOC device
   -35	common/cmd_doc.c	Bad usage of "doc" command
    35	common/cmd_doc.c	correct usage of "doc" command
   -36	common/cmd_doc.c	No boot device
    36	common/cmd_doc.c	correct boot device
   -37	common/cmd_doc.c	Unknown Chip ID on boot device
    37	common/cmd_doc.c	correct chip ID found, device available
   -38	common/cmd_doc.c	Read Error on boot device
    38	common/cmd_doc.c	reading Image header from DOC device OK
   -39	common/cmd_doc.c	Image header has bad magic number
    39	common/cmd_doc.c	Image header has correct magic number
   -40	common/cmd_doc.c	Error reading Image from DOC device
    40	common/cmd_doc.c	Image header has correct magic number
    41	common/cmd_ide.c	before loading a Image from a IDE device
   -42	common/cmd_ide.c	Bad usage of "ide" command
    42	common/cmd_ide.c	correct usage of "ide" command
   -43	common/cmd_ide.c	No boot device
    43	common/cmd_ide.c	boot device found
   -44	common/cmd_ide.c	Device not available
    44	common/cmd_ide.c	Device available
   -45	common/cmd_ide.c	wrong partition selected
    45	common/cmd_ide.c	partition selected
   -46	common/cmd_ide.c	Unknown partition table
    46	common/cmd_ide.c	valid partition table found
   -47	common/cmd_ide.c	Invalid partition type
    47	common/cmd_ide.c	correct partition type
   -48	common/cmd_ide.c	Error reading Image Header on boot device
    48	common/cmd_ide.c	reading Image Header from IDE device OK
   -49	common/cmd_ide.c	Image header has bad magic number
    49	common/cmd_ide.c	Image header has correct magic number
   -50	common/cmd_ide.c	Image header has bad	 checksum
    50	common/cmd_ide.c	Image header has correct checksum
   -51	common/cmd_ide.c	Error reading Image from IDE device
    51	common/cmd_ide.c	reading Image from IDE device OK
    52	common/cmd_nand.c	before loading a Image from a NAND device
   -53	common/cmd_nand.c	Bad usage of "nand" command
    53	common/cmd_nand.c	correct usage of "nand" command
   -54	common/cmd_nand.c	No boot device
    54	common/cmd_nand.c	boot device found
   -55	common/cmd_nand.c	Unknown Chip ID on boot device
    55	common/cmd_nand.c	correct chip ID found, device available
   -56	common/cmd_nand.c	Error reading Image Header on boot device
    56	common/cmd_nand.c	reading Image Header from NAND device OK
   -57	common/cmd_nand.c	Image header has bad magic number
    57	common/cmd_nand.c	Image header has correct magic number
   -58	common/cmd_nand.c	Error reading Image from NAND device
    58	common/cmd_nand.c	reading Image from NAND device OK
   -60	common/env_common.c	Environment has a bad CRC, using default
    64	net/eth.c		starting with Ethernet configuration.
   -64	net/eth.c		no Ethernet found.
    65	net/eth.c		Ethernet found.
   -80	common/cmd_net.c	usage wrong
    80	common/cmd_net.c	before calling NetLoop()
   -81	common/cmd_net.c	some error in NetLoop() occurred
    81	common/cmd_net.c	NetLoop() back without error
   -82	common/cmd_net.c	size == 0 (File with size 0 loaded)
    82	common/cmd_net.c	trying automatic boot
    83	common/cmd_net.c	running "source" command
   -83	common/cmd_net.c	some error in automatic boot or "source" command
    84	common/cmd_net.c	end without errors
 FIT uImage format:
   Arg	Where			When
   100	common/cmd_bootm.c	Kernel FIT Image has correct format
  -100	common/cmd_bootm.c	Kernel FIT Image has incorrect format
   101	common/cmd_bootm.c	No Kernel subimage unit name, using configuration
  -101	common/cmd_bootm.c	Can't get configuration for kernel subimage
   102	common/cmd_bootm.c	Kernel unit name specified
  -103	common/cmd_bootm.c	Can't get kernel subimage node offset
   103	common/cmd_bootm.c	Found configuration node
   104	common/cmd_bootm.c	Got kernel subimage node offset
  -104	common/cmd_bootm.c	Kernel subimage hash verification failed
   105	common/cmd_bootm.c	Kernel subimage hash verification OK
  -105	common/cmd_bootm.c	Kernel subimage is for unsupported architecture
   106	common/cmd_bootm.c	Architecture check OK
  -106	common/cmd_bootm.c	Kernel subimage has wrong type
   107	common/cmd_bootm.c	Kernel subimage type OK
  -107	common/cmd_bootm.c	Can't get kernel subimage data/size
   108	common/cmd_bootm.c	Got kernel subimage data/size
  -108	common/cmd_bootm.c	Wrong image type (not legacy, FIT)
  -109	common/cmd_bootm.c	Can't get kernel subimage type
  -110	common/cmd_bootm.c	Can't get kernel subimage comp
  -111	common/cmd_bootm.c	Can't get kernel subimage os
  -112	common/cmd_bootm.c	Can't get kernel subimage load address
  -113	common/cmd_bootm.c	Image uncompress/copy overwrite error
   120	common/image.c		Start initial ramdisk verification
  -120	common/image.c		Ramdisk FIT image has incorrect format
   121	common/image.c		Ramdisk FIT image has correct format
   122	common/image.c		No ramdisk subimage unit name, using configuration
  -122	common/image.c		Can't get configuration for ramdisk subimage
   123	common/image.c		Ramdisk unit name specified
  -124	common/image.c		Can't get ramdisk subimage node offset
   125	common/image.c		Got ramdisk subimage node offset
  -125	common/image.c		Ramdisk subimage hash verification failed
   126	common/image.c		Ramdisk subimage hash verification OK
  -126	common/image.c		Ramdisk subimage for unsupported architecture
   127	common/image.c		Architecture check OK
  -127	common/image.c		Can't get ramdisk subimage data/size
   128	common/image.c		Got ramdisk subimage data/size
   129	common/image.c		Can't get ramdisk load address
  -129	common/image.c		Got ramdisk load address
  -130	common/cmd_doc.c	Incorrect FIT image format
   131	common/cmd_doc.c	FIT image format OK
  -140	common/cmd_ide.c	Incorrect FIT image format
   141	common/cmd_ide.c	FIT image format OK
  -150	common/cmd_nand.c	Incorrect FIT image format
   151	common/cmd_nand.c	FIT image format OK
 Modem Support:
 --------------
 [so far only for SMDK2400 and TRAB boards]
 - Modem support enable:
 		CONFIG_MODEM_SUPPORT
 - RTS/CTS Flow control enable:
 		CONFIG_HWFLOW
 - Modem debug support:
 		CONFIG_MODEM_SUPPORT_DEBUG
 		Enables debugging stuff (char screen[1024], dbg())
 		for modem support. Useful only with BDI2000.
 - Interrupt support (PPC):
 		There are common interrupt_init() and timer_interrupt()
 		for all PPC archs. interrupt_init() calls interrupt_init_cpu()
 		for CPU specific initialization. interrupt_init_cpu()
 		should set decrementer_count to appropriate value. If
 		CPU resets decrementer automatically after interrupt
 		(ppc4xx) it should set decrementer_count to zero.
 		timer_interrupt() calls timer_interrupt_cpu() for CPU
 		specific handling. If board has watchdog / status_led
 		/ other_activity_monitor it works automatically from
 		general timer_interrupt().
 - General:
 		In the target system modem support is enabled when a
 		specific key (key combination) is pressed during
 		power-on. Otherwise U-Boot will boot normally
 		(autoboot). The key_pressed() function is called from
 		board_init(). Currently key_pressed() is a dummy
 		function, returning 1 and thus enabling modem
 		initialization.
 		If there are no modem init strings in the
 		environment, U-Boot proceed to autoboot; the
 		previous output (banner, info printfs) will be
 		suppressed, though.
 		See also: doc/README.Modem
 Configuration Settings:
 -----------------------
 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
 		undefine this when you're short of memory.
 - CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
 		width of the commands listed in the 'help' command output.
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
 		prompt for user input.
 - CONFIG_SYS_CBSIZE:	Buffer size for input from the Console
 - CONFIG_SYS_PBSIZE:	Buffer size for Console output
 - CONFIG_SYS_MAXARGS:	max. Number of arguments accepted for monitor commands
 - CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
 		the application (usually a Linux kernel) when it is
 		booted
 - CONFIG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 - CONFIG_SYS_CONSOLE_INFO_QUIET
 		Suppress display of console information at boot.
 - CONFIG_SYS_CONSOLE_IS_IN_ENV
 		If the board specific function
 			extern int overwrite_console (void);
 		returns 1, the stdin, stderr and stdout are switched to the
 		serial port, else the settings in the environment are used.
 - CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 		Enable the call to overwrite_console().
 - CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 		Enable overwrite of previous console environment settings.
 - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
 		Begin and End addresses of the area used by the
 		simple memory test.
 - CONFIG_SYS_ALT_MEMTEST:
 		Enable an alternate, more extensive memory test.
 - CONFIG_SYS_MEMTEST_SCRATCH:
 		Scratch address used by the alternate memory test
 		You only need to set this if address zero isn't writeable
 - CONFIG_SYS_MEM_TOP_HIDE (PPC only):
 		If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
 		this specified memory area will get subtracted from the top
 		(end) of RAM and won't get "touched" at all by U-Boot. By
 		fixing up gd->ram_size the Linux kernel should gets passed
 		the now "corrected" memory size and won't touch it either.
 		This should work for arch/ppc and arch/powerpc. Only Linux
 		board ports in arch/powerpc with bootwrapper support that
 		recalculate the memory size from the SDRAM controller setup
 		will have to get fixed in Linux additionally.
 		This option can be used as a workaround for the 440EPx/GRx
 		CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
 		be touched.
 		WARNING: Please make sure that this value is a multiple of
 		the Linux page size (normally 4k). If this is not the case,
 		then the end address of the Linux memory will be located at a
 		non page size aligned address and this could cause major
 		problems.
 - CONFIG_SYS_TFTP_LOADADDR:
 		Default load address for network file downloads
 - CONFIG_SYS_LOADS_BAUD_CHANGE:
 		Enable temporary baudrate change while serial download
 - CONFIG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 - CONFIG_SYS_MBIO_BASE:
 		Physical start address of Motherboard I/O (if using a
 		Cogent motherboard)
 - CONFIG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 - CONFIG_SYS_MONITOR_BASE:
 		Physical start address of boot monitor code (set by
 		make config files to be same as the text base address
 		(TEXT_BASE) used when linking) - same as
 		CONFIG_SYS_FLASH_BASE when booting from flash.
 - CONFIG_SYS_MONITOR_LEN:
 		Size of memory reserved for monitor code, used to
 		determine _at_compile_time_ (!) if the environment is
 		embedded within the U-Boot image, or in a separate
 		flash sector.
 - CONFIG_SYS_MALLOC_LEN:
 		Size of DRAM reserved for malloc() use.
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,
 		you can define CONFIG_SYS_BOOTM_LEN in your board config file
 		to adjust this setting to your needs.
 - CONFIG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
 		the Linux kernel (bd_info, boot arguments, FDT blob if
 		used) must be put below this limit, unless "bootm_low"
 		enviroment variable is defined and non-zero. In such case
 		all data for the Linux kernel must be between "bootm_low"
 		and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.
 - CONFIG_SYS_MAX_FLASH_BANKS:
 		Max number of Flash memory banks
 - CONFIG_SYS_MAX_FLASH_SECT:
 		Max number of sectors on a Flash chip
 - CONFIG_SYS_FLASH_ERASE_TOUT:
 		Timeout for Flash erase operations (in ms)
 - CONFIG_SYS_FLASH_WRITE_TOUT:
 		Timeout for Flash write operations (in ms)
 - CONFIG_SYS_FLASH_LOCK_TOUT
 		Timeout for Flash set sector lock bit operation (in ms)
 - CONFIG_SYS_FLASH_UNLOCK_TOUT
 		Timeout for Flash clear lock bits operation (in ms)
 - CONFIG_SYS_FLASH_PROTECTION
 		If defined, hardware flash sectors protection is used
 		instead of U-Boot software protection.
 - CONFIG_SYS_DIRECT_FLASH_TFTP:
 		Enable TFTP transfers directly to flash memory;
 		without this option such a download has to be
 		performed in two steps: (1) download to RAM, and (2)
 		copy from RAM to flash.
 		The two-step approach is usually more reliable, since
 		you can check if the download worked before you erase
 		the flash, but in some situations (when system RAM is
 		too limited to allow for a temporary copy of the
 		downloaded image) this option may be very useful.
 - CONFIG_SYS_FLASH_CFI:
 		Define if the flash driver uses extra elements in the
 		common flash structure for storing flash geometry.
 - CONFIG_FLASH_CFI_DRIVER
 		This option also enables the building of the cfi_flash driver
 		in the drivers directory
 - CONFIG_FLASH_CFI_MTD
 		This option enables the building of the cfi_mtd driver
 		in the drivers directory. The driver exports CFI flash
 		to the MTD layer.
 - CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 		Use buffered writes to flash.
 - CONFIG_FLASH_SPANSION_S29WS_N
 		s29ws-n MirrorBit flash has non-standard addresses for buffered
 		write commands.
 - CONFIG_SYS_FLASH_QUIET_TEST
 		If this option is defined, the common CFI flash doesn't
 		print it's warning upon not recognized FLASH banks. This
 		is useful, if some of the configured banks are only
 		optionally available.
 - CONFIG_FLASH_SHOW_PROGRESS
 		If defined (must be an integer), print out countdown
 		digits and dots.  Recommended value: 45 (9..1) for 80
 		column displays, 15 (3..1) for 40 column displays.
 - CONFIG_SYS_RX_ETH_BUFFER:
 		Defines the number of Ethernet receive buffers. On some
 		Ethernet controllers it is recommended to set this value
 		to 8 or even higher (EEPRO100 or 405 EMAC), since all
 		buffers can be full shortly after enabling the interface
 		on high Ethernet traffic.
 		Defaults to 4 if not defined.
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
 - CONFIG_ENV_IS_IN_FLASH:
 	Define this if the environment is in flash memory.
 	a) The environment occupies one whole flash sector, which is
 	   "embedded" in the text segment with the U-Boot code. This
 	   happens usually with "bottom boot sector" or "top boot
 	   sector" type flash chips, which have several smaller
 	   sectors at the start or the end. For instance, such a
 	   layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
 	   such a case you would place the environment in one of the
 	   4 kB sectors - with U-Boot code before and after it. With
 	   "top boot sector" type flash chips, you would put the
 	   environment in one of the last sectors, leaving a gap
 	   between U-Boot and the environment.
 	- CONFIG_ENV_OFFSET:
 	   Offset of environment data (variable area) to the
 	   beginning of flash memory; for instance, with bottom boot
 	   type flash chips the second sector can be used: the offset
 	   for this sector is given here.
 	   CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
 	- CONFIG_ENV_ADDR:
 	   This is just another way to specify the start address of
 	   the flash sector containing the environment (instead of
 	   CONFIG_ENV_OFFSET).
 	- CONFIG_ENV_SECT_SIZE:
 	   Size of the sector containing the environment.
 	b) Sometimes flash chips have few, equal sized, BIG sectors.
 	   In such a case you don't want to spend a whole sector for
 	   the environment.
 	- CONFIG_ENV_SIZE:
 	   If you use this in combination with CONFIG_ENV_IS_IN_FLASH
 	   and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
 	   of this flash sector for the environment. This saves
 	   memory for the RAM copy of the environment.
 	   It may also save flash memory if you decide to use this
 	   when your environment is "embedded" within U-Boot code,
 	   since then the remainder of the flash sector could be used
 	   for U-Boot code. It should be pointed out that this is
 	   STRONGLY DISCOURAGED from a robustness point of view:
 	   updating the environment in flash makes it always
 	   necessary to erase the WHOLE sector. If something goes
 	   wrong before the contents has been restored from a copy in
 	   RAM, your target system will be dead.
 	- CONFIG_ENV_ADDR_REDUND
 	  CONFIG_ENV_SIZE_REDUND
 	   These settings describe a second storage area used to hold
 	   a redundant copy of the environment data, so that there is
 	   a valid backup copy in case there is a power failure during
 	   a "saveenv" operation.
 BE CAREFUL! Any changes to the flash layout, and some changes to the
 source code will make it necessary to adapt <board>/u-boot.lds*
 accordingly!
 - CONFIG_ENV_IS_IN_NVRAM:
 	Define this if you have some non-volatile memory device
 	(NVRAM, battery buffered SRAM) which you want to use for the
 	environment.
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These two #defines are used to determine the memory area you
 	  want to use for environment. It is assumed that this memory
 	  can just be read and written to, without any special
 	  provision.
 BE CAREFUL! The first access to the environment happens quite early
 in U-Boot initalization (when we try to get the setting of for the
 console baudrate). You *MUST* have mapped your NVRAM area then, or
 U-Boot will hang.
 Please note that even with NVRAM we still use a copy of the
 environment in RAM: we could work on NVRAM directly, but we want to
 keep settings there always unmodified except somebody uses "saveenv"
 to save the current settings.
 - CONFIG_ENV_IS_IN_EEPROM:
 	Use this if you have an EEPROM or similar serial access
 	device and a driver for it.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the
 	  environment area within the total memory of your EEPROM.
 	- CONFIG_SYS_I2C_EEPROM_ADDR:
 	  If defined, specified the chip address of the EEPROM device.
 	  The default address is zero.
 	- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
 	  If defined, the number of bits used to address bytes in a
 	  single page in the EEPROM device.  A 64 byte page, for example
 	  would require six bits.
 	- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
 	  If defined, the number of milliseconds to delay between
 	  page writes.	The default is zero milliseconds.
 	- CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
 	  The length in bytes of the EEPROM memory array address.  Note
 	  that this is NOT the chip address length!
 	- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
 	  EEPROM chips that implement "address overflow" are ones
 	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 	  address and the extra bits end up in the "chip address" bit
 	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
 	  byte chips.
 	  Note that we consider the length of the address field to
 	  still be one byte because the extra address bits are hidden
 	  in the chip address.
 	- CONFIG_SYS_EEPROM_SIZE:
 	  The size in bytes of the EEPROM device.
 - CONFIG_ENV_IS_IN_DATAFLASH:
 	Define this if you have a DataFlash memory device which you
 	want to use for the environment.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_ADDR:
 	- CONFIG_ENV_SIZE:
 	  These three #defines specify the offset and size of the
 	  environment area within the total memory of your DataFlash placed
 	  at the specified address.
 - CONFIG_ENV_IS_IN_NAND:
 	Define this if you have a NAND device which you want to use
 	for the environment.
 	- CONFIG_ENV_OFFSET:
 	- CONFIG_ENV_SIZE:
 	  These two #defines specify the offset and size of the environment
 	  area within the first NAND device.
 	- CONFIG_ENV_OFFSET_REDUND
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data,
 	  so that there is a valid backup copy in case there is a
 	  power failure during a "saveenv" operation.
 	Note: CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND must be aligned
 	to a block boundary, and CONFIG_ENV_SIZE must be a multiple of
 	the NAND devices block size.
 - CONFIG_SYS_SPI_INIT_OFFSET
 	Defines offset to the initial SPI buffer area in DPRAM. The
 	area is used at an early stage (ROM part) if the environment
 	is configured to reside in the SPI EEPROM: We need a 520 byte
 	scratch DPRAM area. It is used between the two initialization
 	calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
 	to be a good choice since it makes it far enough from the
 	start of the data area as well as from the stack pointer.
 Please note that the environment is read-only until the monitor
 has been relocated to RAM and a RAM copy of the environment has been
 created; also, when using EEPROM you will have to use getenv_r()
 until then to read environment variables.
 The environment is protected by a CRC32 checksum. Before the monitor
 is relocated into RAM, as a result of a bad CRC you will be working
 with the compiled-in default environment - *silently*!!! [This is
 necessary, because the first environment variable we need is the
 "baudrate" setting for the console - if we have a bad CRC, we don't
 have any device yet where we could complain.]
 Note: once the monitor has been relocated, then it will complain if
 the default environment is used; a new CRC is computed as soon as you
 use the "saveenv" command to store a valid environment.
 - CONFIG_SYS_FAULT_ECHO_LINK_DOWN:
 		Echo the inverted Ethernet link state to the fault LED.
 		Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR
 		      also needs to be defined.
 - CONFIG_SYS_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.
 - CONFIG_SYS_64BIT_VSPRINTF:
 		Makes vsprintf (and all *printf functions) support printing
 		of 64bit values by using the L quantifier
 - CONFIG_SYS_64BIT_STRTOUL:
 		Adds simple_strtoull that returns a 64bit value
 - CONFIG_NS16550_MIN_FUNCTIONS:
 		Define this if you desire to only have use of the NS16550_init
 		and NS16550_putc functions for the serial driver located at
 		drivers/serial/ns16550.c.  This option is useful for saving
 		space for already greatly restricted images, including but not
 		limited to NAND_SPL configurations.
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 - CONFIG_SYS_CACHELINE_SIZE:
 		Cache Line Size of the CPU.
 - CONFIG_SYS_DEFAULT_IMMR:
 		Default address of the IMMR after system reset.
 		Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
 		and RPXsuper) to be able to adjust the position of
 		the IMMR register after a reset.
 - Floppy Disk Support:
 		CONFIG_SYS_FDC_DRIVE_NUMBER
 		the default drive number (default value 0)
 		CONFIG_SYS_ISA_IO_STRIDE
 		defines the spacing between FDC chipset registers
 		(default value 1)
 		CONFIG_SYS_ISA_IO_OFFSET
 		defines the offset of register from address. It
 		depends on which part of the data bus is connected to
 		the FDC chipset. (default value 0)
 		If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and
 		CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their
 		default value.
 		if CONFIG_SYS_FDC_HW_INIT is defined, then the function
 		fdc_hw_init() is called at the beginning of the FDC
 		setup. fdc_hw_init() must be provided by the board
 		source code. It is used to make hardware dependant
 		initializations.
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx/82xx systems only]
 - CONFIG_SYS_INIT_RAM_ADDR:
 		Start address of memory area that can be used for
 		initial data and stack; please note that this must be
 		writable memory that is working WITHOUT special
 		initialization, i. e. you CANNOT use normal RAM which
 		will become available only after programming the
 		memory controller and running certain initialization
 		sequences.
 		U-Boot uses the following memory types:
 		- MPC8xx and MPC8260: IMMR (internal memory of the CPU)
 		- MPC824X: data cache
 		- PPC4xx:  data cache
 - CONFIG_SYS_GBL_DATA_OFFSET:
 		Offset of the initial data structure in the memory
 		area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
 		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
 		data is located at the end of the available space
 		(sometimes written as (CONFIG_SYS_INIT_RAM_END -
 		CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
 		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
 		CONFIG_SYS_GBL_DATA_OFFSET) downward.
 	Note:
 		On the MPC824X (or other systems that use the data
 		cache for initial memory) the address chosen for
 		CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
 		point to an otherwise UNUSED address space between
 		the top of RAM and the start of the PCI space.
 - CONFIG_SYS_SIUMCR:	SIU Module Configuration (11-6)
 - CONFIG_SYS_SYPCR:	System Protection Control (11-9)
 - CONFIG_SYS_TBSCR:	Time Base Status and Control (11-26)
 - CONFIG_SYS_PISCR:	Periodic Interrupt Status and Control (11-31)
 - CONFIG_SYS_PLPRCR:	PLL, Low-Power, and Reset Control Register (15-30)
 - CONFIG_SYS_SCCR:	System Clock and reset Control Register (15-27)
 - CONFIG_SYS_OR_TIMING_SDRAM:
 		SDRAM timing
 - CONFIG_SYS_MAMR_PTA:
 		periodic timer for refresh
 - CONFIG_SYS_DER:	Debug Event Register (37-47)
 - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
   CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
   CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
   CONFIG_SYS_BR1_PRELIM:
 		Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
 - SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
   CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
   CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
 		Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
 - CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
   CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
 		Machine Mode Register and Memory Periodic Timer
 		Prescaler definitions (SDRAM timing)
 - CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]:
 		enable I2C microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [DSP2]
 - CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]:
 		enable SMC microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SMC1]
 - CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]:
 		enable SPI microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SCC4]
 - CONFIG_SYS_USE_OSCCLK:
 		Use OSCM clock mode on MBX8xx board. Be careful,
 		wrong setting might damage your board. Read
 		doc/README.MBX before setting this variable!
 - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
 		Offset of the bootmode word in DPRAM used by post
 		(Power On Self Tests). This definition overrides
 		#define'd default value in commproc.h resp.
 		cpm_8260.h.
 - CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
   CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
   CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
   CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
   CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
   CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
   CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
   CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
 		Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
 - CONFIG_PCI_DISABLE_PCIE:
 		Disable PCI-Express on systems where it is supported but not
 		required.
 - CONFIG_SPD_EEPROM
 		Get DDR timing information from an I2C EEPROM. Common
 		with pluggable memory modules such as SODIMMs
   SPD_EEPROM_ADDRESS
 		I2C address of the SPD EEPROM
 - CONFIG_SYS_SPD_BUS_NUM
 		If SPD EEPROM is on an I2C bus other than the first
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 - CONFIG_SYS_83XX_DDR_USES_CS0
 		Only for 83xx systems. If specified, then DDR should
 		be configured using CS0 and CS1 instead of CS2 and CS3.
 - CONFIG_ETHER_ON_FEC[12]
 		Define to enable FEC[12] on a 8xx series processor.
 - CONFIG_FEC[12]_PHY
 		Define to the hardcoded PHY address which corresponds
 		to the given FEC; i. e.
 			#define CONFIG_FEC1_PHY 4
 		means that the PHY with address 4 is connected to FEC1
 		When set to -1, means to probe for first available.
 - CONFIG_FEC[12]_PHY_NORXERR
 		The PHY does not have a RXERR line (RMII only).
 		(so program the FEC to ignore it).
 - CONFIG_RMII
 		Enable RMII mode for all FECs.
 		Note that this is a global option, we can't
 		have one FEC in standard MII mode and another in RMII mode.
 - CONFIG_CRC32_VERIFY
 		Add a verify option to the crc32 command.
 		The syntax is:
 		=> crc32 -v <address> <count> <crc32>
 		Where address/count indicate a memory area
 		and crc32 is the correct crc32 which the
 		area should have.
 - CONFIG_LOOPW
 		Add the "loopw" memory command. This only takes effect if
 		the memory commands are activated globally (CONFIG_CMD_MEM).
 - CONFIG_MX_CYCLIC
 		Add the "mdc" and "mwc" memory commands. These are cyclic
 		"md/mw" commands.
 		Examples:
 		=> mdc.b 10 4 500
 		This command will print 4 bytes (10,11,12,13) each 500 ms.
 		=> mwc.l 100 12345678 10
 		This command will write 12345678 to address 100 all 10 ms.
 		This only takes effect if the memory commands are activated
 		globally (CONFIG_CMD_MEM).
 - CONFIG_SKIP_LOWLEVEL_INIT
 - CONFIG_SKIP_RELOCATE_UBOOT
 		[ARM only] If these variables are defined, then
 		certain low level initializations (like setting up
 		the memory controller) are omitted and/or U-Boot does
 		not relocate itself into RAM.
 		Normally these variables MUST NOT be defined. The
 		only exception is when U-Boot is loaded (to RAM) by
 		some other boot loader or by a debugger which
 		performs these initializations itself.
 Building the Software:
 ======================
 Building U-Boot has been tested in several native build environments
 and in many different cross environments. Of course we cannot support
 all possibly existing versions of cross development tools in all
 (potentially obsolete) versions. In case of tool chain problems we
 recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK)
 which is extensively used to build and test U-Boot.
 If you are not using a native environment, it is assumed that you
 have GNU cross compiling tools available in your path. In this case,
 you must set the environment variable CROSS_COMPILE in your shell.
 Note that no changes to the Makefile or any other source files are
 necessary. For example using the ELDK on a 4xx CPU, please enter:
 	$ CROSS_COMPILE=ppc_4xx-
 	$ export CROSS_COMPILE
 Note: If you wish to generate Windows versions of the utilities in
       the tools directory you can use the MinGW toolchain
       (http://www.mingw.org).  Set your HOST tools to the MinGW
       toolchain and execute 'make tools'.  For example:
        $ make HOSTCC=i586-mingw32msvc-gcc HOSTSTRIP=i586-mingw32msvc-strip tools
       Binaries such as tools/mkimage.exe will be created which can
       be executed on computers running Windows.
 U-Boot is intended to be simple to build. After installing the
 sources you must configure U-Boot for one specific board type. This
 is done by typing:
 	make NAME_config
 where "NAME_config" is the name of one of the existing configu-
 rations; see the main Makefile for supported names.
 Note: for some board special configuration names may exist; check if
       additional information is available from the board vendor; for
       instance, the TQM823L systems are available without (standard)
       or with LCD support. You can select such additional "features"
       when choosing the configuration, i. e.
       make TQM823L_config
 	- will configure for a plain TQM823L, i. e. no LCD support
       make TQM823L_LCD_config
 	- will configure for a TQM823L with U-Boot console on LCD
       etc.
 Finally, type "make all", and you should get some working U-Boot
 images ready for download to / installation on your system:
 - "u-boot.bin" is a raw binary image
 - "u-boot" is an image in ELF binary format
 - "u-boot.srec" is in Motorola S-Record format
 By default the build is performed locally and the objects are saved
 in the source directory. One of the two methods can be used to change
 this behavior and build U-Boot to some external directory:
 1. Add O= to the make command line invocations:
 	make O=/tmp/build distclean
 	make O=/tmp/build NAME_config
 	make O=/tmp/build all
 2. Set environment variable BUILD_DIR to point to the desired location:
 	export BUILD_DIR=/tmp/build
 	make distclean
 	make NAME_config
 	make all
 Note that the command line "O=" setting overrides the BUILD_DIR environment
 variable.
 Please be aware that the Makefiles assume you are using GNU make, so
 for instance on NetBSD you might need to use "gmake" instead of
 native "make".
 If the system board that you have is not listed, then you will need
 to port U-Boot to your hardware platform. To do this, follow these
 steps:
 1.  Add a new configuration option for your board to the toplevel
     "Makefile" and to the "MAKEALL" script, using the existing
     entries as examples. Note that here and at many other places
     boards and other names are listed in alphabetical sort order. Please
     keep this order.
 2.  Create a new directory to hold your board specific code. Add any
     files you need. In your board directory, you will need at least
     the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
 3.  Create a new configuration file "include/configs/<board>.h" for
     your board
 3.  If you're porting U-Boot to a new CPU, then also create a new
     directory to hold your CPU specific code. Add any files you need.
 4.  Run "make <board>_config" with your new name.
 5.  Type "make", and you should get a working "u-boot.srec" file
     to be installed on your target system.
 6.  Debug and solve any problems that might arise.
     [Of course, this last step is much harder than it sounds.]
 Testing of U-Boot Modifications, Ports to New Hardware, etc.:
 ==============================================================
 If you have modified U-Boot sources (for instance added a new board
 or support for new devices, a new CPU, etc.) you are expected to
 provide feedback to the other developers. The feedback normally takes
 the form of a "patch", i. e. a context diff against a certain (latest
 official or latest in the git repository) version of U-Boot sources.
 But before you submit such a patch, please verify that your modifi-
 cation did not break existing code. At least make sure that *ALL* of
 the supported boards compile WITHOUT ANY compiler warnings. To do so,
 just run the "MAKEALL" script, which will configure and build U-Boot
 for ALL supported system. Be warned, this will take a while. You can
 select which (cross) compiler to use by passing a `CROSS_COMPILE'
 environment variable to the script, i. e. to use the ELDK cross tools
 you can type
 	CROSS_COMPILE=ppc_8xx- MAKEALL
 or to build on a native PowerPC system you can type
 	CROSS_COMPILE=' ' MAKEALL
 When using the MAKEALL script, the default behaviour is to build
 U-Boot in the source directory. This location can be changed by
 setting the BUILD_DIR environment variable. Also, for each target
 built, the MAKEALL script saves two log files (<target>.ERR and
 <target>.MAKEALL) in the <source dir>/LOG directory. This default
 location can be changed by setting the MAKEALL_LOGDIR environment
 variable. For example:
 	export BUILD_DIR=/tmp/build
 	export MAKEALL_LOGDIR=/tmp/log
 	CROSS_COMPILE=ppc_8xx- MAKEALL
 With the above settings build objects are saved in the /tmp/build,
 log files are saved in the /tmp/log and the source tree remains clean
 during the whole build process.
 See also "U-Boot Porting Guide" below.
 Monitor Commands - Overview:
 ============================
 go	- start application at address 'addr'
 run	- run commands in an environment variable
 bootm	- boot application image from memory
 bootp	- boot image via network using BootP/TFTP protocol
 tftpboot- boot image via network using TFTP protocol
 	       and env variables "ipaddr" and "serverip"
 	       (and eventually "gatewayip")
 rarpboot- boot image via network using RARP/TFTP protocol
 diskboot- boot from IDE devicebootd   - boot default, i.e., run 'bootcmd'
 loads	- load S-Record file over serial line
 loadb	- load binary file over serial line (kermit mode)
 md	- memory display
 mm	- memory modify (auto-incrementing)
 nm	- memory modify (constant address)
 mw	- memory write (fill)
 cp	- memory copy
 cmp	- memory compare
 crc32	- checksum calculation
 imd	- i2c memory display
 imm	- i2c memory modify (auto-incrementing)
 inm	- i2c memory modify (constant address)
 imw	- i2c memory write (fill)
 icrc32	- i2c checksum calculation
 iprobe	- probe to discover valid I2C chip addresses
 iloop	- infinite loop on address range
 isdram	- print SDRAM configuration information
 sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
 setenv	- set environment variables
 saveenv - save environment variables to persistent storage
 protect - enable or disable FLASH write protection
 erase	- erase FLASH memory
 flinfo	- print FLASH memory information
 bdinfo	- print Board Info structure
 iminfo	- print header information for application image
 coninfo - print console devices and informations
 ide	- IDE sub-system
 loop	- infinite loop on address range
 loopw	- infinite write loop on address range
 mtest	- simple RAM test
 icache	- enable or disable instruction cache
 dcache	- enable or disable data cache
 reset	- Perform RESET of the CPU
 echo	- echo args to console
 version - print monitor version
 help	- print online help
 ?	- alias for 'help'
 Monitor Commands - Detailed Description:
 ========================================
 TODO.
 For now: just type "help <command>".
 Environment Variables:
 ======================
 U-Boot supports user configuration using Environment Variables which
 can be made persistent by saving to Flash memory.
 Environment Variables are set using "setenv", printed using
 "printenv", and saved to Flash using "saveenv". Using "setenv"
 without a value can be used to delete a variable from the
 environment. As long as you don't save the environment you are
 working with an in-memory copy. In case the Flash area containing the
 environment is erased by accident, a default environment is provided.
 Some configuration options can be set using Environment Variables:
   baudrate	- see CONFIG_BAUDRATE
   bootdelay	- see CONFIG_BOOTDELAY
   bootcmd	- see CONFIG_BOOTCOMMAND
   bootargs	- Boot arguments when booting an RTOS image
   bootfile	- Name of the image to load with TFTP
   bootm_low	- Memory range available for image processing in the bootm
 		  command can be restricted. This variable is given as
 		  a hexadecimal number and defines lowest address allowed
 		  for use by the bootm command. See also "bootm_size"
 		  environment variable. Address defined by "bootm_low" is
 		  also the base of the initial memory mapping for the Linux
 		  kernel -- see the description of CONFIG_SYS_BOOTMAPSZ.
   bootm_size	- Memory range available for image processing in the bootm
 		  command can be restricted. This variable is given as
 		  a hexadecimal number and defines the size of the region
 		  allowed for use by the bootm command. See also "bootm_low"
 		  environment variable.
   updatefile	- Location of the software update file on a TFTP server, used
 		  by the automatic software update feature. Please refer to
 		  documentation in doc/README.update for more details.
   autoload	- if set to "no" (any string beginning with 'n'),
 		  "bootp" will just load perform a lookup of the
 		  configuration from the BOOTP server, but not try to
 		  load any image using TFTP
   autoscript	- if set to "yes" commands like "loadb", "loady",
 		  "bootp", "tftpb", "rarpboot" and "nfs" will attempt
 		  to automatically run script images (by internally
 		  calling "source").
   autoscript_uname - if script image is in a format (FIT) this
 		     variable is used to get script subimage unit name.
   autostart	- if set to "yes", an image loaded using the "bootp",
 		  "rarpboot", "tftpboot" or "diskboot" commands will
 		  be automatically started (by internally calling
 		  "bootm")
 		  If set to "no", a standalone image passed to the
 		  "bootm" command will be copied to the load address
 		  (and eventually uncompressed), but NOT be started.
 		  This can be used to load and uncompress arbitrary
 		  data.
   i2cfast	- (PPC405GP|PPC405EP only)
 		  if set to 'y' configures Linux I2C driver for fast
 		  mode (400kHZ). This environment variable is used in
 		  initialization code. So, for changes to be effective
 		  it must be saved and board must be reset.
   initrd_high	- restrict positioning of initrd images:
 		  If this variable is not set, initrd images will be
 		  copied to the highest possible address in RAM; this
 		  is usually what you want since it allows for
 		  maximum initrd size. If for some reason you want to
 		  make sure that the initrd image is loaded below the
 		  CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
 		  variable to a value of "no" or "off" or "0".
 		  Alternatively, you can set it to a maximum upper
 		  address to use (U-Boot will still check that it
 		  does not overwrite the U-Boot stack and data).
 		  For instance, when you have a system with 16 MB
 		  RAM, and want to reserve 4 MB from use by Linux,
 		  you can do this by adding "mem=12M" to the value of
 		  the "bootargs" variable. However, now you must make
 		  sure that the initrd image is placed in the first
 		  12 MB as well - this can be done with
 		  setenv initrd_high 00c00000
 		  If you set initrd_high to 0xFFFFFFFF, this is an
 		  indication to U-Boot that all addresses are legal
 		  for the Linux kernel, including addresses in flash
 		  memory. In this case U-Boot will NOT COPY the
 		  ramdisk at all. This may be useful to reduce the
 		  boot time on your system, but requires that this
 		  feature is supported by your Linux kernel.
   ipaddr	- IP address; needed for tftpboot command
   loadaddr	- Default load address for commands like "bootp",
 		  "rarpboot", "tftpboot", "loadb" or "diskboot"
   loads_echo	- see CONFIG_LOADS_ECHO
   serverip	- TFTP server IP address; needed for tftpboot command
   bootretry	- see CONFIG_BOOT_RETRY_TIME
   bootdelaykey	- see CONFIG_AUTOBOOT_DELAY_STR
   bootstopkey	- see CONFIG_AUTOBOOT_STOP_STR
   ethprime	- When CONFIG_NET_MULTI is enabled controls which
 		  interface is used first.
   ethact	- When CONFIG_NET_MULTI is enabled controls which
 		  interface is currently active. For example you
 		  can do the following
 		  => setenv ethact FEC ETHERNET
 		  => ping 192.168.0.1 # traffic sent on FEC ETHERNET
 		  => setenv ethact SCC ETHERNET
 		  => ping 10.0.0.1 # traffic sent on SCC ETHERNET
   ethrotate	- When set to "no" U-Boot does not go through all
 		  available network interfaces.
 		  It just stays at the currently selected interface.
    netretry	- When set to "no" each network operation will
 		  either succeed or fail without retrying.
 		  When set to "once" the network operation will
 		  fail when all the available network interfaces
 		  are tried once without success.
 		  Useful on scripts which control the retry operation
 		  themselves.
   npe_ucode	- set load address for the NPE microcode
   tftpsrcport	- If this is set, the value is used for TFTP's
 		  UDP source port.
   tftpdstport	- If this is set, the value is used for TFTP's UDP
 		  destination port instead of the Well Know Port 69.
    vlan		- When set to a value < 4095 the traffic over
 		  Ethernet is encapsulated/received over 802.1q
 		  VLAN tagged frames.
 The following environment variables may be used and automatically
 updated by the network boot commands ("bootp" and "rarpboot"),
 depending the information provided by your boot server:
   bootfile	- see above
   dnsip		- IP address of your Domain Name Server
   dnsip2	- IP address of your secondary Domain Name Server
   gatewayip	- IP address of the Gateway (Router) to use
   hostname	- Target hostname
   ipaddr	- see above
   netmask	- Subnet Mask
   rootpath	- Pathname of the root filesystem on the NFS server
   serverip	- see above
 There are two special Environment Variables:
   serial#	- contains hardware identification information such
 		  as type string and/or serial number
   ethaddr	- Ethernet address
 These variables can be set only once (usually during manufacturing of
 the board). U-Boot refuses to delete or overwrite these variables
 once they have been set once.
 Further special Environment Variables:
   ver		- Contains the U-Boot version string as printed
 		  with the "version" command. This variable is
 		  readonly (see CONFIG_VERSION_VARIABLE).
 Please note that changes to some configuration parameters may take
 only effect after the next boot (yes, that's just like Windoze :-).
 Command Line Parsing:
 =====================
 There are two different command line parsers available with U-Boot:
 the old "simple" one, and the much more powerful "hush" shell:
 Old, simple command line parser:
 --------------------------------
 - supports environment variables (through setenv / saveenv commands)
 - several commands on one line, separated by ';'
 - variable substitution using "... ${name} ..." syntax
 - special characters ('$', ';') can be escaped by prefixing with '\',
   for example:
 	setenv bootcmd bootm \${address}
 - You can also escape text by enclosing in single apostrophes, for example:
 	setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off'
 Hush shell:
 -----------
 - similar to Bourne shell, with control structures like
   if...then...else...fi, for...do...done; while...do...done,
   until...do...done, ...
 - supports environment ("global") variables (through setenv / saveenv
   commands) and local shell variables (through standard shell syntax
   "name=value"); only environment variables can be used with "run"
   command
 General rules:
 --------------
 (1) If a command line (or an environment variable executed by a "run"
     command) contains several commands separated by semicolon, and
     one of these commands fails, then the remaining commands will be
     executed anyway.
 (2) If you execute several variables with one call to run (i. e.
     calling run with a list of variables as arguments), any failing
     command will cause "run" to terminate, i. e. the remaining
     variables are not executed.
 Note for Redundant Ethernet Interfaces:
 =======================================
 Some boards come with redundant Ethernet interfaces; U-Boot supports
 such configurations and is capable of automatic selection of a
 "working" interface when needed. MAC assignment works as follows:
 Network interfaces are numbered eth0, eth1, eth2, ... Corresponding
 MAC addresses can be stored in the environment as "ethaddr" (=>eth0),
 "eth1addr" (=>eth1), "eth2addr", ...
 If the network interface stores some valid MAC address (for instance
 in SROM), this is used as default address if there is NO correspon-
 ding setting in the environment; if the corresponding environment
 variable is set, this overrides the settings in the card; that means:
 o If the SROM has a valid MAC address, and there is no address in the
   environment, the SROM's address is used.
 o If there is no valid address in the SROM, and a definition in the
   environment exists, then the value from the environment variable is
   used.
 o If both the SROM and the environment contain a MAC address, and
   both addresses are the same, this MAC address is used.
 o If both the SROM and the environment contain a MAC address, and the
   addresses differ, the value from the environment is used and a
   warning is printed.
 o If neither SROM nor the environment contain a MAC address, an error
   is raised.
 Image Formats:
 ==============
 U-Boot is capable of booting (and performing other auxiliary operations on)
 images in two formats:
 New uImage format (FIT)
 -----------------------
 Flexible and powerful format based on Flattened Image Tree -- FIT (similar
 to Flattened Device Tree). It allows the use of images with multiple
 components (several kernels, ramdisks, etc.), with contents protected by
 SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
 Old uImage format
 -----------------
 Old image format is based on binary files which can be basically anything,
 preceded by a special header; see the definitions in include/image.h for
 details; basically, the header defines the following image properties:
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
   LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
   IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
 * Image Name
 * Image Timestamp
 The header is marked by a special Magic Number, and both the header
 and the data portions of the image are secured against corruption by
 CRC32 checksums.
 Linux Support:
 ==============
 Although U-Boot should support any OS or standalone application
 easily, the main focus has always been on Linux during the design of
 U-Boot.
 U-Boot includes many features that so far have been part of some
 special "boot loader" code within the Linux kernel. Also, any
 "initrd" images to be used are no longer part of one big Linux image;
 instead, kernel and "initrd" are separate images. This implementation
 serves several purposes:
 - the same features can be used for other OS or standalone
   applications (for instance: using compressed images to reduce the
   Flash memory footprint)
 - it becomes much easier to port new Linux kernel versions because
   lots of low-level, hardware dependent stuff are done by U-Boot
 - the same Linux kernel image can now be used with different "initrd"
   images; of course this also means that different kernel images can
   be run with the same "initrd". This makes testing easier (you don't
   have to build a new "zImage.initrd" Linux image when you just
   change a file in your "initrd"). Also, a field-upgrade of the
   software is easier now.
 Linux HOWTO:
 ============
 Porting Linux to U-Boot based systems:
 ---------------------------------------
 U-Boot cannot save you from doing all the necessary modifications to
 configure the Linux device drivers for use with your target hardware
 (no, we don't intend to provide a full virtual machine interface to
 Linux :-).
 But now you can ignore ALL boot loader code (in arch/ppc/mbxboot).
 Just make sure your machine specific header file (for instance
 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
 Information structure as we define in include/asm-<arch>/u-boot.h,
 and make sure that your definition of IMAP_ADDR uses the same value
 as your U-Boot configuration in CONFIG_SYS_IMMR.
 Configuring the Linux kernel:
 -----------------------------
 No specific requirements for U-Boot. Make sure you have some root
 device (initial ramdisk, NFS) for your target system.
 Building a Linux Image:
 -----------------------
 With U-Boot, "normal" build targets like "zImage" or "bzImage" are
 not used. If you use recent kernel source, a new build target
 "uImage" will exist which automatically builds an image usable by
 U-Boot. Most older kernels also have support for a "pImage" target,
 which was introduced for our predecessor project PPCBoot and uses a
 100% compatible format.
 Example:
 	make TQM850L_config
 	make oldconfig
 	make dep
 	make uImage
 The "uImage" build target uses a special tool (in 'tools/mkimage') to
 encapsulate a compressed Linux kernel image with header	 information,
 CRC32 checksum etc. for use with U-Boot. This is what we are doing:
 * build a standard "vmlinux" kernel image (in ELF binary format):
 * convert the kernel into a raw binary image:
 	${CROSS_COMPILE}-objcopy -O binary \
 				 -R .note -R .comment \
 				 -S vmlinux linux.bin
 * compress the binary image:
 	gzip -9 linux.bin
 * package compressed binary image for U-Boot:
 	mkimage -A ppc -O linux -T kernel -C gzip \
 		-a 0 -e 0 -n "Linux Kernel Image" \
 		-d linux.bin.gz uImage
 The "mkimage" tool can also be used to create ramdisk images for use
 with U-Boot, either separated from the Linux kernel image, or
 combined into one file. "mkimage" encapsulates the images with a 64
 byte header containing information about target architecture,
 operating system, image type, compression method, entry points, time
 stamp, CRC32 checksums, etc.
 "mkimage" can be called in two ways: to verify existing images and
 print the header information, or to build new images.
 In the first form (with "-l" option) mkimage lists the information
 contained in the header of an existing U-Boot image; this includes
 checksum verification:
 	tools/mkimage -l image
 	  -l ==> list image header information
 The second form (with "-d" option) is used to build a U-Boot image
 from a "data file" which is used as image payload:
 	tools/mkimage -A arch -O os -T type -C comp -a addr -e ep \
 		      -n name -d data_file image
 	  -A ==> set architecture to 'arch'
 	  -O ==> set operating system to 'os'
 	  -T ==> set image type to 'type'
 	  -C ==> set compression type 'comp'
 	  -a ==> set load address to 'addr' (hex)
 	  -e ==> set entry point to 'ep' (hex)
 	  -n ==> set image name to 'name'
 	  -d ==> use image data from 'datafile'
 Right now, all Linux kernels for PowerPC systems use the same load
 address (0x00000000), but the entry point address depends on the
 kernel version:
 - 2.2.x kernels have the entry point at 0x0000000C,
 - 2.3.x and later kernels have the entry point at 0x00000000.
 So a typical call to build a U-Boot image would read:
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
 	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz \
 	> examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (gzip compressed)
 	Data Size:    335725 Bytes = 327.86 kB = 0.32 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 To verify the contents of the image (or check for corruption):
 	-> tools/mkimage -l examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (gzip compressed)
 	Data Size:    335725 Bytes = 327.86 kB = 0.32 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 NOTE: for embedded systems where boot time is critical you can trade
 speed for memory and install an UNCOMPRESSED image instead: this
 needs more space in Flash, but boots much faster since it does not
 need to be uncompressed:
 	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C none -a 0 -e 0 \
 	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux \
 	> examples/uImage.TQM850L-uncompressed
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
 	Image Type:   PowerPC Linux Kernel Image (uncompressed)
 	Data Size:    792160 Bytes = 773.59 kB = 0.76 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 Similar you can build U-Boot images from a 'ramdisk.image.gz' file
 when your kernel is intended to use an initial ramdisk:
 	-> tools/mkimage -n 'Simple Ramdisk Image' \
 	> -A ppc -O linux -T ramdisk -C gzip \
 	> -d /LinuxPPC/images/SIMPLE-ramdisk.image.gz examples/simple-initrd
 	Image Name:   Simple Ramdisk Image
 	Created:      Wed Jan 12 14:01:50 2000
 	Image Type:   PowerPC Linux RAMDisk Image (gzip compressed)
 	Data Size:    566530 Bytes = 553.25 kB = 0.54 MB
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 Installing a Linux Image:
 -------------------------
 To downloading a U-Boot image over the serial (console) interface,
 you must convert the image to S-Record format:
 	objcopy -I binary -O srec examples/image examples/image.srec
 The 'objcopy' does not understand the information in the U-Boot
 image header, so the resulting S-Record file will be relative to
 address 0x00000000. To load it to a given address, you need to
 specify the target address as 'offset' parameter with the 'loads'
 command.
 Example: install the image to address 0x40100000 (which on the
 TQM8xxL is in the first Flash bank):
 	=> erase 40100000 401FFFFF
 	.......... done
 	Erased 8 sectors
 	=> loads 40100000
 	## Ready for S-Record download ...
 	~>examples/image.srec
 	1 2 3 4 5 6 7 8 9 10 11 12 13 ...
 	...
 	15989 15990 15991 15992
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00000000
 You can check the success of the download using the 'iminfo' command;
 this includes a checksum verification so you can be sure no data
 corruption happened:
 	=> imi 40100000
 	## Checking Image at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 Boot Linux:
 -----------
 The "bootm" command is used to boot an application that is stored in
 memory (RAM or Flash). In case of a Linux kernel image, the contents
 of the "bootargs" environment variable is passed to the kernel as
 parameters. You can check and modify this variable using the
 "printenv" and "setenv" commands:
 	=> printenv bootargs
 	bootargs=root=/dev/ram
 	=> setenv bootargs root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	=> printenv bootargs
 	bootargs=root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	=> bootm 40020000
 	## Booting Linux kernel at 40020000 ...
 	   Image Name:	 2.2.13 for NFS on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 381681 Bytes = 372 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	   Uncompressing Kernel Image ... OK
 	Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:35:17 MEST 2000
 	Boot arguments: root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2
 	time_init: decrementer frequency = 187500000/60
 	Calibrating delay loop... 49.77 BogoMIPS
 	Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000]
 	...
 If you want to boot a Linux kernel with initial RAM disk, you pass
 the memory addresses of both the kernel and the initrd image (PPBCOOT
 format!) to the "bootm" command:
 	=> imi 40100000 40200000
 	## Checking Image at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	## Checking Image at 40200000 ...
 	   Image Name:	 Simple Ramdisk Image
 	   Image Type:	 PowerPC Linux RAMDisk Image (gzip compressed)
 	   Data Size:	 566530 Bytes = 553 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 00000000
 	   Verifying Checksum ... OK
 	=> bootm 40100000 40200000
 	## Booting Linux kernel at 40100000 ...
 	   Image Name:	 2.2.13 for initrd on TQM850L
 	   Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
 	   Data Size:	 335725 Bytes = 327 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 0000000c
 	   Verifying Checksum ... OK
 	   Uncompressing Kernel Image ... OK
 	## Loading RAMDisk Image at 40200000 ...
 	   Image Name:	 Simple Ramdisk Image
 	   Image Type:	 PowerPC Linux RAMDisk Image (gzip compressed)
 	   Data Size:	 566530 Bytes = 553 kB = 0 MB
 	   Load Address: 00000000
 	   Entry Point:	 00000000
 	   Verifying Checksum ... OK
 	   Loading Ramdisk ... OK
 	Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:32:08 MEST 2000
 	Boot arguments: root=/dev/ram
 	time_init: decrementer frequency = 187500000/60
 	Calibrating delay loop... 49.77 BogoMIPS
 	...
 	RAMDISK: Compressed image found at block 0
 	VFS: Mounted root (ext2 filesystem).
 	bash#
 Boot Linux and pass a flat device tree:
 -----------
 First, U-Boot must be compiled with the appropriate defines. See the section
 titled "Linux Kernel Interface" above for a more in depth explanation. The
 following is an example of how to start a kernel and pass an updated
 flat device tree:
 => print oftaddr
 oftaddr=0x300000
 => print oft
 oft=oftrees/mpc8540ads.dtb
 => tftp $oftaddr $oft
 Speed: 1000, full duplex
 Using TSEC0 device
 TFTP from server 192.168.1.1; our IP address is 192.168.1.101
 Filename 'oftrees/mpc8540ads.dtb'.
 Load address: 0x300000
 Loading: #
 done
 Bytes transferred = 4106 (100a hex)
 => tftp $loadaddr $bootfile
 Speed: 1000, full duplex
 Using TSEC0 device
 TFTP from server 192.168.1.1; our IP address is 192.168.1.2
 Filename 'uImage'.
 Load address: 0x200000
 Loading:############
 done
 Bytes transferred = 1029407 (fb51f hex)
 => print loadaddr
 loadaddr=200000
 => print oftaddr
 oftaddr=0x300000
 => bootm $loadaddr - $oftaddr
 ## Booting image at 00200000 ...
    Image Name:	 Linux-2.6.17-dirty
    Image Type:	 PowerPC Linux Kernel Image (gzip compressed)
    Data Size:	 1029343 Bytes = 1005.2 kB
    Load Address: 00000000
    Entry Point:	 00000000
    Verifying Checksum ... OK
    Uncompressing Kernel Image ... OK
 Booting using flat device tree at 0x300000
 Using MPC85xx ADS machine description
 Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
 [snip]
 More About U-Boot Image Types:
 ------------------------------
 U-Boot supports the following image types:
    "Standalone Programs" are directly runnable in the environment
 	provided by U-Boot; it is expected that (if they behave
 	well) you can continue to work in U-Boot after return from
 	the Standalone Program.
    "OS Kernel Images" are usually images of some Embedded OS which
 	will take over control completely. Usually these programs
 	will install their own set of exception handlers, device
 	drivers, set up the MMU, etc. - this means, that you cannot
 	expect to re-enter U-Boot except by resetting the CPU.
    "RAMDisk Images" are more or less just data blocks, and their
 	parameters (address, size) are passed to an OS kernel that is
 	being started.
    "Multi-File Images" contain several images, typically an OS
 	(Linux) kernel image and one or more data images like
 	RAMDisks. This construct is useful for instance when you want
 	to boot over the network using BOOTP etc., where the boot
 	server provides just a single image file, but you want to get
 	for instance an OS kernel and a RAMDisk image.
 	"Multi-File Images" start with a list of image sizes, each
 	image size (in bytes) specified by an "uint32_t" in network
 	byte order. This list is terminated by an "(uint32_t)0".
 	Immediately after the terminating 0 follow the images, one by
 	one, all aligned on "uint32_t" boundaries (size rounded up to
 	a multiple of 4 bytes).
    "Firmware Images" are binary images containing firmware (like
 	U-Boot or FPGA images) which usually will be programmed to
 	flash memory.
    "Script files" are command sequences that will be executed by
 	U-Boot's command interpreter; this feature is especially
 	useful when you configure U-Boot to use a real shell (hush)
 	as command interpreter.
 Standalone HOWTO:
 =================
 One of the features of U-Boot is that you can dynamically load and
 run "standalone" applications, which can use some resources of
 U-Boot like console I/O functions or interrupt services.
 Two simple examples are included with the sources:
 "Hello World" Demo:
 -------------------
 'examples/hello_world.c' contains a small "Hello World" Demo
 application; it is automatically compiled when you build U-Boot.
 It's configured to run at address 0x00040004, so you can play with it
 like that:
 	=> loads
 	## Ready for S-Record download ...
 	~>examples/hello_world.srec
 	1 2 3 4 5 6 7 8 9 10 11 ...
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00040004
 	=> go 40004 Hello World! This is a test.
 	## Starting application at 0x00040004 ...
 	Hello World
 	argc = 7
 	argv[0] = "40004"
 	argv[1] = "Hello"
 	argv[2] = "World!"
 	argv[3] = "This"
 	argv[4] = "is"
 	argv[5] = "a"
 	argv[6] = "test."
 	argv[7] = "<NULL>"
 	Hit any key to exit ...
 	## Application terminated, rc = 0x0
 Another example, which demonstrates how to register a CPM interrupt
 handler with the U-Boot code, can be found in 'examples/timer.c'.
 Here, a CPM timer is set up to generate an interrupt every second.
 The interrupt service routine is trivial, just printing a '.'
 character, but this is just a demo program. The application can be
 controlled by the following keys:
 	? - print current values og the CPM Timer registers
 	b - enable interrupts and start timer
 	e - stop timer and disable interrupts
 	q - quit application
 	=> loads
 	## Ready for S-Record download ...
 	~>examples/timer.srec
 	1 2 3 4 5 6 7 8 9 10 11 ...
 	[file transfer complete]
 	[connected]
 	## Start Addr = 0x00040004
 	=> go 40004
 	## Starting application at 0x00040004 ...
 	TIMERS=0xfff00980
 	Using timer 1
 	  tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0xfff009b0
 Hit 'b':
 	[q, b, e, ?] Set interval 1000000 us
 	Enabling timer
 Hit '?':
 	[q, b, e, ?] ........
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0
 Hit '?':
 	[q, b, e, ?] .
 	tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0
 Hit 'e':
 	[q, b, e, ?] ...Stopping timer
 Hit 'q':
 	[q, b, e, ?] ## Application terminated, rc = 0x0
 Minicom warning:
 ================
 Over time, many people have reported problems when trying to use the
 "minicom" terminal emulation program for serial download. I (wd)
 consider minicom to be broken, and recommend not to use it. Under
 Unix, I recommend to use C-Kermit for general purpose use (and
 especially for kermit binary protocol download ("loadb" command), and
 use "cu" for S-Record download ("loads" command).
 Nevertheless, if you absolutely want to use it try adding this
 configuration to your "File transfer protocols" section:
 	   Name	   Program			Name U/D FullScr IO-Red. Multi
 	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
 	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N
 NetBSD Notes:
 =============
 Starting at version 0.9.2, U-Boot supports NetBSD both as host
 (build U-Boot) and target system (boots NetBSD/mpc8xx).
 Building requires a cross environment; it is known to work on
 NetBSD/i386 with the cross-powerpc-netbsd-1.3 package (you will also
 need gmake since the Makefiles are not compatible with BSD make).
 Note that the cross-powerpc package does not install include files;
 attempting to build U-Boot will fail because <machine/ansi.h> is
 missing.  This file has to be installed and patched manually:
 	# cd /usr/pkg/cross/powerpc-netbsd/include
 	# mkdir powerpc
 	# ln -s powerpc machine
 	# cp /usr/src/sys/arch/powerpc/include/ansi.h powerpc/ansi.h
 	# ${EDIT} powerpc/ansi.h	## must remove __va_list, _BSD_VA_LIST
 Native builds *don't* work due to incompatibilities between native
 and U-Boot include files.
 Booting assumes that (the first part of) the image booted is a
 stage-2 loader which in turn loads and then invokes the kernel
 proper. Loader sources will eventually appear in the NetBSD source
 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the
 meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz
 Implementation Internals:
 =========================
 The following is not intended to be a complete description of every
 implementation detail. However, it should help to understand the
 inner workings of U-Boot and make it easier to port it to custom
 hardware.
 Initial Stack, Global Data:
 ---------------------------
 The implementation of U-Boot is complicated by the fact that U-Boot
 starts running out of ROM (flash memory), usually without access to
 system RAM (because the memory controller is not initialized yet).
 This means that we don't have writable Data or BSS segments, and BSS
 is not initialized as zero. To be able to get a C environment working
 at all, we have to allocate at least a minimal stack. Implementation
 options for this are defined and restricted by the CPU used: Some CPU
 models provide on-chip memory (like the IMMR area on MPC8xx and
 MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.
 	Chris Hallinan posted a good summary of these issues to the
 	U-Boot mailing list:
 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
 	From: "Chris Hallinan" <clh@net1plus.com>
 	Date: Mon, 10 Feb 2003 16:43:46 -0500 (22:43 MET)
 	...
 	Correct me if I'm wrong, folks, but the way I understand it
 	is this: Using DCACHE as initial RAM for Stack, etc, does not
 	require any physical RAM backing up the cache. The cleverness
 	is that the cache is being used as a temporary supply of
 	necessary storage before the SDRAM controller is setup. It's
 	beyond the scope of this list to explain the details, but you
 	can see how this works by studying the cache architecture and
 	operation in the architecture and processor-specific manuals.
 	OCM is On Chip Memory, which I believe the 405GP has 4K. It
 	is another option for the system designer to use as an
 	initial stack/RAM area prior to SDRAM being available. Either
 	option should work for you. Using CS 4 should be fine if your
 	board designers haven't used it for something that would
 	cause you grief during the initial boot! It is frequently not
 	used.
 	CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
 	with your processor/board/system design. The default value
 	you will find in any recent u-boot distribution in
 	walnut.h should work for you. I'd set it to a value larger
 	than your SDRAM module. If you have a 64MB SDRAM module, set
 	it above 400_0000. Just make sure your board has no resources
 	that are supposed to respond to that address! That code in
 	start.S has been around a while and should work as is when
 	you get the config right.
 	-Chris Hallinan
 	DS4.COM, Inc.
 It is essential to remember this, since it has some impact on the C
 code for the initialization procedures:
 * Initialized global data (data segment) is read-only. Do not attempt
   to write it.
 * Do not use any uninitialized global data (or implicitely initialized
   as zero data - BSS segment) at all - this is undefined, initiali-
   zation is performed later (when relocating to RAM).
 * Stack space is very limited. Avoid big data buffers or things like
   that.
 Having only the stack as writable memory limits means we cannot use
 normal global data to share information beween the code. But it
 turned out that the implementation of U-Boot can be greatly
 simplified by making a global data structure (gd_t) available to all
 functions. We could pass a pointer to this data as argument to _all_
 functions, but this would bloat the code. Instead we use a feature of
 the GCC compiler (Global Register Variables) to share the data: we
 place a pointer (gd) to the global data into a register which we
 reserve for this purpose.
 When choosing a register for such a purpose we are restricted by the
 relevant  (E)ABI  specifications for the current architecture, and by
 GCC's implementation.
 For PowerPC, the following registers have specific use:
 	R1:	stack pointer
 	R2:	reserved for system use
 	R3-R4:	parameter passing and return values
 	R5-R10: parameter passing
 	R13:	small data area pointer
 	R30:	GOT pointer
 	R31:	frame pointer
 	(U-Boot also uses R14 as internal GOT pointer.)
     ==> U-Boot will use R2 to hold a pointer to the global data
     Note: on PPC, we could use a static initializer (since the
     address of the global data structure is known at compile time),
     but it turned out that reserving a register results in somewhat
     smaller code - although the code savings are not that big (on
     average for all boards 752 bytes for the whole U-Boot image,
     624 text + 127 data).
 On Blackfin, the normal C ABI (except for P5) is followed as documented here:
 	http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
     ==> U-Boot will use P5 to hold a pointer to the global data
 On ARM, the following registers are used:
 	R0:	function argument word/integer result
 	R1-R3:	function argument word
 	R9:	GOT pointer
 	R10:	stack limit (used only if stack checking if enabled)
 	R11:	argument (frame) pointer
 	R12:	temporary workspace
 	R13:	stack pointer
 	R14:	link register
 	R15:	program counter
     ==> U-Boot will use R8 to hold a pointer to the global data
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 Memory Management:
 ------------------
 U-Boot runs in system state and uses physical addresses, i.e. the
 MMU is not used either for address mapping nor for memory protection.
 The available memory is mapped to fixed addresses using the memory
 controller. In this process, a contiguous block is formed for each
 memory type (Flash, SDRAM, SRAM), even when it consists of several
 physical memory banks.
 U-Boot is installed in the first 128 kB of the first Flash bank (on
 TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After
 booting and sizing and initializing DRAM, the code relocates itself
 to the upper end of DRAM. Immediately below the U-Boot code some
 memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN
 configuration setting]. Below that, a structure with global Board
 Info data is placed, followed by the stack (growing downward).
 Additionally, some exception handler code is copied to the low 8 kB
 of DRAM (0x00000000 ... 0x00001FFF).
 So a typical memory configuration with 16 MB of DRAM could look like
 this:
 	0x0000 0000	Exception Vector code
 	      :
 	0x0000 1FFF
 	0x0000 2000	Free for Application Use
 	      :
 	      :
 	      :
 	      :
 	0x00FB FF20	Monitor Stack (Growing downward)
 	0x00FB FFAC	Board Info Data and permanent copy of global data
 	0x00FC 0000	Malloc Arena
 	      :
 	0x00FD FFFF
 	0x00FE 0000	RAM Copy of Monitor Code
 	...		eventually: LCD or video framebuffer
 	...		eventually: pRAM (Protected RAM - unchanged by reset)
 	0x00FF FFFF	[End of RAM]
 System Initialization:
 ----------------------
 In the reset configuration, U-Boot starts at the reset entry point
 (on most PowerPC systems at address 0x00000100). Because of the reset
 configuration for CS0# this is a mirror of the onboard Flash memory.
 To be able to re-map memory U-Boot then jumps to its link address.
 To be able to implement the initialization code in C, a (small!)
 initial stack is set up in the internal Dual Ported RAM (in case CPUs
 which provide such a feature like MPC8xx or MPC8260), or in a locked
 part of the data cache. After that, U-Boot initializes the CPU core,
 the caches and the SIU.
 Next, all (potentially) available memory banks are mapped using a
 preliminary mapping. For example, we put them on 512 MB boundaries
 (multiples of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash
 on 0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is
 programmed for SDRAM access. Using the temporary configuration, a
 simple memory test is run that determines the size of the SDRAM
 banks.
 When there is more than one SDRAM bank, and the banks are of
 different size, the largest is mapped first. For equal size, the first
 bank (CS2#) is mapped first. The first mapping is always for address
 0x00000000, with any additional banks following immediately to create
 contiguous memory starting from 0.
 Then, the monitor installs itself at the upper end of the SDRAM area
 and allocates memory for use by malloc() and for the global Board
 Info data; also, the exception vector code is copied to the low RAM
 pages, and the final stack is set up.
 Only after this relocation will you have a "normal" C environment;
 until that you are restricted in several ways, mostly because you are
 running from ROM, and because the code will have to be relocated to a
 new address in RAM.
 U-Boot Porting Guide:
 ----------------------
 [Based on messages by Jerry Van Baren in the U-Boot-Users mailing
 list, October 2002]
 int main (int argc, char *argv[])
 {
 	sighandler_t no_more_time;
 	signal (SIGALRM, no_more_time);
 	alarm (PROJECT_DEADLINE - toSec (3 * WEEK));
 	if (available_money > available_manpower) {
 		pay consultant to port U-Boot;
 		return 0;
 	}
 	Download latest U-Boot source;
 	Subscribe to u-boot mailing list;
 	if (clueless) {
 		email ("Hi, I am new to U-Boot, how do I get started?");
 	}
 	while (learning) {
 		Read the README file in the top level directory;
 		Read http://www.denx.de/twiki/bin/view/DULG/Manual ;
 		Read the source, Luke;
 	}
 	if (available_money > toLocalCurrency ($2500)) {
 		Buy a BDI2000;
 	} else {
 		Add a lot of aggravation and time;
 	}
 	Create your own board support subdirectory;
 	Create your own board config file;
 	while (!running) {
 		do {
 			Add / modify source code;
 		} until (compiles);
 		Debug;
 		if (clueless)
 			email ("Hi, I am having problems...");
 	}
 	Send patch file to Wolfgang;
 	return 0;
 }
 void no_more_time (int sig)
 {
       hire_a_guru();
 }
 Coding Standards:
 -----------------
 All contributions to U-Boot should conform to the Linux kernel
 coding style; see the file "Documentation/CodingStyle" and the script
 "scripts/Lindent" in your Linux kernel source directory.  In sources
 originating from U-Boot a style corresponding to "Lindent -pcs" (adding
 spaces before parameters to function calls) is actually used.
 Source files originating from a different project (for example the
 MTD subsystem) are generally exempt from these guidelines and are not
 reformated to ease subsequent migration to newer versions of those
 sources.
 Please note that U-Boot is implemented in C (and to some small parts in
 Assembler); no C++ is used, so please do not use C++ style comments (//)
 in your code.
 Please also stick to the following formatting rules:
 - remove any trailing white space
 - use TAB characters for indentation, not spaces
 - make sure NOT to use DOS '\r\n' line feeds
 - do not add more than 2 empty lines to source files
 - do not add trailing empty lines to source files
 Submissions which do not conform to the standards may be returned
 with a request to reformat the changes.
 Submitting Patches:
 -------------------
 Since the number of patches for U-Boot is growing, we need to
 establish some rules. Submissions which do not conform to these rules
 may be rejected, even when they contain important and valuable stuff.
 Please see http://www.denx.de/wiki/U-Boot/Patches for details.
 Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
 see http://lists.denx.de/mailman/listinfo/u-boot
 When you send a patch, please include the following information with
 it:
 * For bug fixes: a description of the bug and how your patch fixes
   this bug. Please try to include a way of demonstrating that the
   patch actually fixes something.
 * For new features: a description of the feature and your
   implementation.
 * A CHANGELOG entry as plaintext (separate from the patch)
 * For major contributions, your entry to the CREDITS file
 * When you add support for a new board, don't forget to add this
   board to the MAKEALL script, too.
 * If your patch adds new configuration options, don't forget to
   document these in the README file.
 * The patch itself. If you are using git (which is *strongly*
   recommended) you can easily generate the patch using the
   "git-format-patch". If you then use "git-send-email" to send it to
   the U-Boot mailing list, you will avoid most of the common problems
   with some other mail clients.
   If you cannot use git, use "diff -purN OLD NEW". If your version of
   diff does not support these options, then get the latest version of
   GNU diff.
   The current directory when running this command shall be the parent
   directory of the U-Boot source tree (i. e. please make sure that
   your patch includes sufficient directory information for the
   affected files).
   We prefer patches as plain text. MIME attachments are discouraged,
   and compressed attachments must not be used.
 * If one logical set of modifications affects or creates several
   files, all these changes shall be submitted in a SINGLE patch file.
 * Changesets that contain different, unrelated modifications shall be
   submitted as SEPARATE patches, one patch per changeset.
 Notes:
 * Before sending the patch, run the MAKEALL script on your patched
   source tree and make sure that no errors or warnings are reported
   for any of the boards.
 * Keep your modifications to the necessary minimum: A patch
   containing several unrelated changes or arbitrary reformats will be
   returned with a request to re-formatting / split it.
 * If you modify existing code, make sure that your new code does not
   add to the memory footprint of the code ;-) Small is beautiful!
   When adding new features, these should compile conditionally only
   (using #ifdef), and the resulting code with the new feature
   disabled must not need more memory than the old code without your
   modification.
 * Remember that there is a size limit of 100 kB per message on the
   u-boot mailing list. Bigger patches will be moderated. If they are
   reasonable and not too big, they will be acknowledged. But patches
   bigger than the size limit should be avoided.

common/cmd_i2c.c

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2001
  * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * I2C Functions similar to the standard memory functions.
  *
  * There are several parameters in many of the commands that bear further
  * explanations:
  *
  * Two of the commands (imm and imw) take a byte/word/long modifier
  * (e.g. imm.w specifies the word-length modifier).  This was done to
  * allow manipulating word-length registers.  It was not done on any other
  * commands because it was not deemed useful.
  *
  * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
  *   Each I2C chip on the bus has a unique address.  On the I2C data bus,
  *   the address is the upper seven bits and the LSB is the "read/write"
  *   bit.  Note that the {i2c_chip} address specified on the command
  *   line is not shifted up: e.g. a typical EEPROM memory chip may have
  *   an I2C address of 0x50, but the data put on the bus will be 0xA0
  *   for write and 0xA1 for read.  This "non shifted" address notation
  *   matches at least half of the data sheets :-/.
  *
  * {addr} is the address (or offset) within the chip.  Small memory
  *   chips have 8 bit addresses.  Large memory chips have 16 bit
  *   addresses.  Other memory chips have 9, 10, or 11 bit addresses.
  *   Many non-memory chips have multiple registers and {addr} is used
  *   as the register index.  Some non-memory chips have only one register
  *   and therefore don't need any {addr} parameter.
  *
  *   The default {addr} parameter is one byte (.1) which works well for
  *   memories and registers with 8 bits of address space.
  *
  *   You can specify the length of the {addr} field with the optional .0,
  *   .1, or .2 modifier (similar to the .b, .w, .l modifier).  If you are
  *   manipulating a single register device which doesn't use an address
  *   field, use "0.0" for the address and the ".0" length field will
  *   suppress the address in the I2C data stream.  This also works for
  *   successive reads using the I2C auto-incrementing memory pointer.
  *
  *   If you are manipulating a large memory with 2-byte addresses, use
  *   the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
  *
  *   Then there are the unfortunate memory chips that spill the most
  *   significant 1, 2, or 3 bits of address into the chip address byte.
  *   This effectively makes one chip (logically) look like 2, 4, or
  *   8 chips.  This is handled (awkwardly) by #defining
  *   CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
  *   {addr} field (since .1 is the default, it doesn't actually have to
  *   be specified).  Examples: given a memory chip at I2C chip address
  *   0x50, the following would happen...
  *     imd 50 0 10      display 16 bytes starting at 0x000
  *                      On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
  *     imd 50 100 10    display 16 bytes starting at 0x100
  *                      On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
  *     imd 50 210 10    display 16 bytes starting at 0x210
  *                      On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
  *   This is awfully ugly.  It would be nice if someone would think up
  *   a better way of handling this.
  *
  * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
  */
 #include <common.h>
 #include <command.h>
 #include <environment.h>
 #include <i2c.h>
 #include <malloc.h>
 #include <asm/byteorder.h>
 /* Display values from last command.
  * Memory modify remembered values are different from display memory.
  */
 static uchar	i2c_dp_last_chip;
 static uint	i2c_dp_last_addr;
 static uint	i2c_dp_last_alen;
 static uint	i2c_dp_last_length = 0x10;
 static uchar	i2c_mm_last_chip;
 static uint	i2c_mm_last_addr;
 static uint	i2c_mm_last_alen;
 /* If only one I2C bus is present, the list of devices to ignore when
  * the probe command is issued is represented by a 1D array of addresses.
  * When multiple buses are present, the list is an array of bus-address
  * pairs.  The following macros take care of this */
 #if defined(CONFIG_SYS_I2C_NOPROBES)
 #if defined(CONFIG_I2C_MULTI_BUS)
 static struct
 {
 	uchar	bus;
 	uchar	addr;
 } i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
 #define GET_BUS_NUM	i2c_get_bus_num()
 #define COMPARE_BUS(b,i)	(i2c_no_probes[(i)].bus == (b))
 #define COMPARE_ADDR(a,i)	(i2c_no_probes[(i)].addr == (a))
 #define NO_PROBE_ADDR(i)	i2c_no_probes[(i)].addr
 #else		/* single bus */
 static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
 #define GET_BUS_NUM	0
 #define COMPARE_BUS(b,i)	((b) == 0)	/* Make compiler happy */
 #define COMPARE_ADDR(a,i)	(i2c_no_probes[(i)] == (a))
 #define NO_PROBE_ADDR(i)	i2c_no_probes[(i)]
 #endif	/* CONFIG_MULTI_BUS */
 #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
 #endif
 #if defined(CONFIG_I2C_MUX)
 static I2C_MUX_DEVICE	*i2c_mux_devices = NULL;
 static	int	i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS;
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 static int
 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]);
 /* TODO: Implement architecture-specific get/set functions */
 unsigned int __def_i2c_get_bus_speed(void)
 {
 	return CONFIG_SYS_I2C_SPEED;
 }
 unsigned int i2c_get_bus_speed(void)
 	__attribute__((weak, alias("__def_i2c_get_bus_speed")));
 int __def_i2c_set_bus_speed(unsigned int speed)
 {
 	if (speed != CONFIG_SYS_I2C_SPEED)
 		return -1;
 	return 0;
 }
 int i2c_set_bus_speed(unsigned int)
 	__attribute__((weak, alias("__def_i2c_set_bus_speed")));
 /*
  * Syntax:
  *	imd {i2c_chip} {addr}{.0, .1, .2} {len}
  */
 #define DISP_LINE_LEN	16
 int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	u_char	chip;
 	uint	addr, alen, length;
 	int	j, nbytes, linebytes;
 	/* We use the last specified parameters, unless new ones are
 	 * entered.
 	 */
 	chip   = i2c_dp_last_chip;
 	addr   = i2c_dp_last_addr;
 	alen   = i2c_dp_last_alen;
 	length = i2c_dp_last_length;
 	if (argc < 3) {
 		cmd_usage(cmdtp);
 		return 1;
 	}
 	if ((flag & CMD_FLAG_REPEAT) == 0) {
 		/*
 		 * New command specified.
 		 */
 		alen = 1;
 		/*
 		 * I2C chip address
 		 */
 		chip = simple_strtoul(argv[1], NULL, 16);
 		/*
 		 * I2C data address within the chip.  This can be 1 or
 		 * 2 bytes long.  Some day it might be 3 bytes long :-).
 		 */
 		addr = simple_strtoul(argv[2], NULL, 16);
 		alen = 1;
 		for (j = 0; j < 8; j++) {
 			if (argv[2][j] == '.') {
 				alen = argv[2][j+1] - '0';
 				if (alen > 4) {
 					cmd_usage(cmdtp);
 					return 1;
 				}
 				break;
 			} else if (argv[2][j] == '\0')
 				break;
 		}
 		/*
 		 * If another parameter, it is the length to display.
 		 * Length is the number of objects, not number of bytes.
 		 */
 		if (argc > 3)
 			length = simple_strtoul(argv[3], NULL, 16);
 	}
 	/*
 	 * Print the lines.
 	 *
 	 * We buffer all read data, so we can make sure data is read only
 	 * once.
 	 */
 	nbytes = length;
 	do {
 		unsigned char	linebuf[DISP_LINE_LEN];
 		unsigned char	*cp;
 		linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
 		if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
 			puts ("Error reading the chip.\n");
 		else {
 			printf("%04x:", addr);
 			cp = linebuf;
 			for (j=0; j<linebytes; j++) {
 				printf(" %02x", *cp++);
 				addr++;
 			}
 			puts ("    ");
 			cp = linebuf;
 			for (j=0; j<linebytes; j++) {
 				if ((*cp < 0x20) || (*cp > 0x7e))
 					puts (".");
 				else
 					printf("%c", *cp);
 				cp++;
 			}
 			putc ('\n');
 		}
 		nbytes -= linebytes;
 	} while (nbytes > 0);
 	i2c_dp_last_chip   = chip;
 	i2c_dp_last_addr   = addr;
 	i2c_dp_last_alen   = alen;
 	i2c_dp_last_length = length;
 	return 0;
 }
 int do_i2c_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
 }
 int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
 }
 /* Write (fill) memory
  *
  * Syntax:
  *	imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
  */
 int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	uchar	chip;
 	ulong	addr;
 	uint	alen;
 	uchar	byte;
 	int	count;
 	int	j;
 	if ((argc < 4) || (argc > 5)) {
 		cmd_usage(cmdtp);
 		return 1;
 	}
 	/*
 	 * Chip is always specified.
 	 */
 	chip = simple_strtoul(argv[1], NULL, 16);
 	/*
 	 * Address is always specified.
 	 */
 	addr = simple_strtoul(argv[2], NULL, 16);
 	alen = 1;
 	for (j = 0; j < 8; j++) {
 		if (argv[2][j] == '.') {
 			alen = argv[2][j+1] - '0';
 			if (alen > 4) {
 				cmd_usage(cmdtp);
 				return 1;
 			}
 			break;
 		} else if (argv[2][j] == '\0')
 			break;
 	}
 	/*
 	 * Value to write is always specified.
 	 */
 	byte = simple_strtoul(argv[3], NULL, 16);
 	/*
 	 * Optional count
 	 */
 	if (argc == 5)
 		count = simple_strtoul(argv[4], NULL, 16);
 	else
 		count = 1;
 	while (count-- > 0) {
 		if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
 			puts ("Error writing the chip.\n");
 		/*
 		 * Wait for the write to complete.  The write can take
 		 * up to 10mSec (we allow a little more time).
 		 *
 		 * On some chips, while the write is in progress, the
 		 * chip doesn't respond.  This apparently isn't a
 		 * universal feature so we don't take advantage of it.
 		 */
 /*
  * No write delay with FRAM devices.
  */
 #if !defined(CONFIG_SYS_I2C_FRAM)
 		udelay(11000);
 #endif
 #if 0
 		for (timeout = 0; timeout < 10; timeout++) {
 			udelay(2000);
 			if (i2c_probe(chip) == 0)
 				break;
 		}
 #endif
 	}
 	return (0);
 }
 /* Calculate a CRC on memory
  *
  * Syntax:
  *	icrc32 {i2c_chip} {addr}{.0, .1, .2} {count}
  */
 int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	uchar	chip;
 	ulong	addr;
 	uint	alen;
 	int	count;
 	uchar	byte;
 	ulong	crc;
 	ulong	err;
 	int	j;
 	if (argc < 4) {
 		cmd_usage(cmdtp);
 		return 1;
 	}
 	/*
 	 * Chip is always specified.
 	 */
 	chip = simple_strtoul(argv[1], NULL, 16);
 	/*
 	 * Address is always specified.
 	 */
 	addr = simple_strtoul(argv[2], NULL, 16);
 	alen = 1;
 	for (j = 0; j < 8; j++) {
 		if (argv[2][j] == '.') {
 			alen = argv[2][j+1] - '0';
 			if (alen > 4) {
 				cmd_usage(cmdtp);
 				return 1;
 			}
 			break;
 		} else if (argv[2][j] == '\0')
 			break;
 	}
 	/*
 	 * Count is always specified
 	 */
 	count = simple_strtoul(argv[3], NULL, 16);
 	printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
 	/*
 	 * CRC a byte at a time.  This is going to be slooow, but hey, the
 	 * memories are small and slow too so hopefully nobody notices.
 	 */
 	crc = 0;
 	err = 0;
 	while (count-- > 0) {
 		if (i2c_read(chip, addr, alen, &byte, 1) != 0)
 			err++;
 		crc = crc32 (crc, &byte, 1);
 		addr++;
 	}
 	if (err > 0)
 		puts ("Error reading the chip,\n");
 	else
 		printf ("%08lx\n", crc);
 	return 0;
 }
 /* Modify memory.
  *
  * Syntax:
  *	imm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
  *	inm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
  */
 static int
 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 {
 	uchar	chip;
 	ulong	addr;
 	uint	alen;
 	ulong	data;
 	int	size = 1;
 	int	nbytes;
 	int	j;
 	extern char console_buffer[];
 	if (argc != 3) {
 		cmd_usage(cmdtp);
 		return 1;
 	}
 #ifdef CONFIG_BOOT_RETRY_TIME
 	reset_cmd_timeout();	/* got a good command to get here */
 #endif
 	/*
 	 * We use the last specified parameters, unless new ones are
 	 * entered.
 	 */
 	chip = i2c_mm_last_chip;
 	addr = i2c_mm_last_addr;
 	alen = i2c_mm_last_alen;
 	if ((flag & CMD_FLAG_REPEAT) == 0) {
 		/*
 		 * New command specified.  Check for a size specification.
 		 * Defaults to byte if no or incorrect specification.
 		 */
 		size = cmd_get_data_size(argv[0], 1);
 		/*
 		 * Chip is always specified.
 		 */
 		chip = simple_strtoul(argv[1], NULL, 16);
 		/*
 		 * Address is always specified.
 		 */
 		addr = simple_strtoul(argv[2], NULL, 16);
 		alen = 1;
 		for (j = 0; j < 8; j++) {
 			if (argv[2][j] == '.') {
 				alen = argv[2][j+1] - '0';
 				if (alen > 4) {
 					cmd_usage(cmdtp);
 					return 1;
 				}
 				break;
 			} else if (argv[2][j] == '\0')
 				break;
 		}
 	}
 	/*
 	 * Print the address, followed by value.  Then accept input for
 	 * the next value.  A non-converted value exits.
 	 */
 	do {
 		printf("%08lx:", addr);
 		if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
 			puts ("\nError reading the chip,\n");
 		else {
 			data = cpu_to_be32(data);
 			if (size == 1)
 				printf(" %02lx", (data >> 24) & 0x000000FF);
 			else if (size == 2)
 				printf(" %04lx", (data >> 16) & 0x0000FFFF);
 			else
 				printf(" %08lx", data);
 		}
 		nbytes = readline (" ? ");
 		if (nbytes == 0) {
 			/*
 			 * <CR> pressed as only input, don't modify current
 			 * location and move to next.
 			 */
 			if (incrflag)
 				addr += size;
 			nbytes = size;
 #ifdef CONFIG_BOOT_RETRY_TIME
 			reset_cmd_timeout(); /* good enough to not time out */
 #endif
 		}
 #ifdef CONFIG_BOOT_RETRY_TIME
 		else if (nbytes == -2)
 			break;	/* timed out, exit the command	*/
 #endif
 		else {
 			char *endp;
 			data = simple_strtoul(console_buffer, &endp, 16);
 			if (size == 1)
 				data = data << 24;
 			else if (size == 2)
 				data = data << 16;
 			data = be32_to_cpu(data);
 			nbytes = endp - console_buffer;
 			if (nbytes) {
 #ifdef CONFIG_BOOT_RETRY_TIME
 				/*
 				 * good enough to not time out
 				 */
 				reset_cmd_timeout();
 #endif
 				if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
 					puts ("Error writing the chip.\n");
 #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
 				udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 #endif
 				if (incrflag)
 					addr += size;
 			}
 		}
 	} while (nbytes);
 	i2c_mm_last_chip = chip;
 	i2c_mm_last_addr = addr;
 	i2c_mm_last_alen = alen;
 	return 0;
 }
 /*
  * Syntax:
  *	iprobe {addr}{.0, .1, .2}
  */
 int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int j;
 #if defined(CONFIG_SYS_I2C_NOPROBES)
 	int k, skip;
 	uchar bus = GET_BUS_NUM;
 #endif	/* NOPROBES */
 	puts ("Valid chip addresses:");
 	for (j = 0; j < 128; j++) {
 #if defined(CONFIG_SYS_I2C_NOPROBES)
 		skip = 0;
 		for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
 			if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
 				skip = 1;
 				break;
 			}
 		}
 		if (skip)
 			continue;
 #endif
 		if (i2c_probe(j) == 0)
 			printf(" %02X", j);
 	}
 	putc ('\n');
 #if defined(CONFIG_SYS_I2C_NOPROBES)
 	puts ("Excluded chip addresses:");
 	for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
 		if (COMPARE_BUS(bus,k))
 			printf(" %02X", NO_PROBE_ADDR(k));
 	}
 	putc ('\n');
 #endif
 	return 0;
 }
 /*
  * Syntax:
  *	iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
  *	{length} - Number of bytes to read
  *	{delay}  - A DECIMAL number and defaults to 1000 uSec
  */
 int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	u_char	chip;
 	ulong	alen;
 	uint	addr;
 	uint	length;
 	u_char	bytes[16];
 	int	delay;
 	int	j;
 	if (argc < 3) {
 		cmd_usage(cmdtp);
 		return 1;
 	}
 	/*
 	 * Chip is always specified.
 	 */
 	chip = simple_strtoul(argv[1], NULL, 16);
 	/*
 	 * Address is always specified.
 	 */
 	addr = simple_strtoul(argv[2], NULL, 16);
 	alen = 1;
 	for (j = 0; j < 8; j++) {
 		if (argv[2][j] == '.') {
 			alen = argv[2][j+1] - '0';
 			if (alen > 4) {
 				cmd_usage(cmdtp);
 				return 1;
 			}
 			break;
 		} else if (argv[2][j] == '\0')
 			break;
 	}
 	/*
 	 * Length is the number of objects, not number of bytes.
 	 */
 	length = 1;
 	length = simple_strtoul(argv[3], NULL, 16);
 	if (length > sizeof(bytes))
 		length = sizeof(bytes);
 	/*
 	 * The delay time (uSec) is optional.
 	 */
 	delay = 1000;
 	if (argc > 3)
 		delay = simple_strtoul(argv[4], NULL, 10);
 	/*
 	 * Run the loop...
 	 */
 	while (1) {
 		if (i2c_read(chip, addr, alen, bytes, length) != 0)
 			puts ("Error reading the chip.\n");
 		udelay(delay);
 	}
 	/* NOTREACHED */
 	return 0;
 }
 /*
  * The SDRAM command is separately configured because many
  * (most?) embedded boards don't use SDRAM DIMMs.
  */
 #if defined(CONFIG_CMD_SDRAM)
 static void print_ddr2_tcyc (u_char const b)
 {
 	printf ("%d.", (b >> 4) & 0x0F);
 	switch (b & 0x0F) {
 	case 0x0:
 	case 0x1:
 	case 0x2:
 	case 0x3:
 	case 0x4:
 	case 0x5:
 	case 0x6:
 	case 0x7:
 	case 0x8:
 	case 0x9:
 		printf ("%d ns\n", b & 0x0F);
 		break;
 	case 0xA:
 		puts ("25 ns\n");
 		break;
 	case 0xB:
 		puts ("33 ns\n");
 		break;
 	case 0xC:
 		puts ("66 ns\n");
 		break;
 	case 0xD:
 		puts ("75 ns\n");
 		break;
 	default:
 		puts ("?? ns\n");
 		break;
 	}
 }
 static void decode_bits (u_char const b, char const *str[], int const do_once)
 {
 	u_char mask;
 	for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
 		if (b & mask) {
 			puts (*str);
 			if (do_once)
 				return;
 		}
 	}
 }
 /*
  * Syntax:
  *	sdram {i2c_chip}
  */
 int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	enum { unknown, EDO, SDRAM, DDR2 } type;
 	u_char	chip;
 	u_char	data[128];
 	u_char	cksum;
 	int	j;
 	static const char *decode_CAS_DDR2[] = {
 		" TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
 	};
 	static const char *decode_CAS_default[] = {
 		" TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
 	};
 	static const char *decode_CS_WE_default[] = {
 		" TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
 	};
 	static const char *decode_byte21_default[] = {
 		"  TBD (bit 7)\n",
 		"  Redundant row address\n",
 		"  Differential clock input\n",
 		"  Registerd DQMB inputs\n",
 		"  Buffered DQMB inputs\n",
 		"  On-card PLL\n",
 		"  Registered address/control lines\n",
 		"  Buffered address/control lines\n"
 	};
 	static const char *decode_byte22_DDR2[] = {
 		"  TBD (bit 7)\n",
 		"  TBD (bit 6)\n",
 		"  TBD (bit 5)\n",
 		"  TBD (bit 4)\n",
 		"  TBD (bit 3)\n",
 		"  Supports partial array self refresh\n",
 		"  Supports 50 ohm ODT\n",
 		"  Supports weak driver\n"
 	};
 	static const char *decode_row_density_DDR2[] = {
 		"512 MiB", "256 MiB", "128 MiB", "16 GiB",
 		"8 GiB", "4 GiB", "2 GiB", "1 GiB"
 	};
 	static const char *decode_row_density_default[] = {
 		"512 MiB", "256 MiB", "128 MiB", "64 MiB",
 		"32 MiB", "16 MiB", "8 MiB", "4 MiB"
 	};
 	if (argc < 2) {
 		cmd_usage(cmdtp);
 		return 1;
 	}
 	/*
 	 * Chip is always specified.
 	 */
 	chip = simple_strtoul (argv[1], NULL, 16);
 	if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
 		puts ("No SDRAM Serial Presence Detect found.\n");
 		return 1;
 	}
 	cksum = 0;
 	for (j = 0; j < 63; j++) {
 		cksum += data[j];
 	}
 	if (cksum != data[63]) {
 		printf ("WARNING: Configuration data checksum failure:\n"
 			"  is 0x%02x, calculated 0x%02x\n", data[63], cksum);
 	}
 	printf ("SPD data revision            %d.%d\n",
 		(data[62] >> 4) & 0x0F, data[62] & 0x0F);
 	printf ("Bytes used                   0x%02X\n", data[0]);
 	printf ("Serial memory size           0x%02X\n", 1 << data[1]);
 	puts ("Memory type                  ");
 	switch (data[2]) {
 	case 2:
 		type = EDO;
 		puts ("EDO\n");
 		break;
 	case 4:
 		type = SDRAM;
 		puts ("SDRAM\n");
 		break;
 	case 8:
 		type = DDR2;
 		puts ("DDR2\n");
 		break;
 	default:
 		type = unknown;
 		puts ("unknown\n");
 		break;
 	}
 	puts ("Row address bits             ");
 	if ((data[3] & 0x00F0) == 0)
 		printf ("%d\n", data[3] & 0x0F);
 	else
 		printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
 	puts ("Column address bits          ");
 	if ((data[4] & 0x00F0) == 0)
 		printf ("%d\n", data[4] & 0x0F);
 	else
 		printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
 	switch (type) {
 	case DDR2:
 		printf ("Number of ranks              %d\n",
 			(data[5] & 0x07) + 1);
 		break;
 	default:
 		printf ("Module rows                  %d\n", data[5]);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("Module data width            %d bits\n", data[6]);
 		break;
 	default:
 		printf ("Module data width            %d bits\n",
 			(data[7] << 8) | data[6]);
 		break;
 	}
 	puts ("Interface signal levels      ");
 	switch(data[8]) {
 		case 0:  puts ("TTL 5.0 V\n");	break;
 		case 1:  puts ("LVTTL\n");	break;
 		case 2:  puts ("HSTL 1.5 V\n");	break;
 		case 3:  puts ("SSTL 3.3 V\n");	break;
 		case 4:  puts ("SSTL 2.5 V\n");	break;
 		case 5:  puts ("SSTL 1.8 V\n");	break;
 		default: puts ("unknown\n");	break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("SDRAM cycle time             ");
 		print_ddr2_tcyc (data[9]);
 		break;
 	default:
 		printf ("SDRAM cycle time             %d.%d ns\n",
 			(data[9] >> 4) & 0x0F, data[9] & 0x0F);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("SDRAM access time            0.%d%d ns\n",
 			(data[10] >> 4) & 0x0F, data[10] & 0x0F);
 		break;
 	default:
 		printf ("SDRAM access time            %d.%d ns\n",
 			(data[10] >> 4) & 0x0F, data[10] & 0x0F);
 		break;
 	}
 	puts ("EDC configuration            ");
 	switch (data[11]) {
 		case 0:  puts ("None\n");	break;
 		case 1:  puts ("Parity\n");	break;
 		case 2:  puts ("ECC\n");	break;
 		default: puts ("unknown\n");	break;
 	}
 	if ((data[12] & 0x80) == 0)
 		puts ("No self refresh, rate        ");
 	else
 		puts ("Self refresh, rate           ");
 	switch(data[12] & 0x7F) {
 		case 0:  puts ("15.625 us\n");	break;
 		case 1:  puts ("3.9 us\n");	break;
 		case 2:  puts ("7.8 us\n");	break;
 		case 3:  puts ("31.3 us\n");	break;
 		case 4:  puts ("62.5 us\n");	break;
 		case 5:  puts ("125 us\n");	break;
 		default: puts ("unknown\n");	break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("SDRAM width (primary)        %d\n", data[13]);
 		break;
 	default:
 		printf ("SDRAM width (primary)        %d\n", data[13] & 0x7F);
 		if ((data[13] & 0x80) != 0) {
 			printf ("  (second bank)              %d\n",
 				2 * (data[13] & 0x7F));
 		}
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		if (data[14] != 0)
 			printf ("EDC width                    %d\n", data[14]);
 		break;
 	default:
 		if (data[14] != 0) {
 			printf ("EDC width                    %d\n",
 				data[14] & 0x7F);
 			if ((data[14] & 0x80) != 0) {
 				printf ("  (second bank)              %d\n",
 					2 * (data[14] & 0x7F));
 			}
 		}
 		break;
 	}
 	if (DDR2 != type) {
 		printf ("Min clock delay, back-to-back random column addresses "
 			"%d\n", data[15]);
 	}
 	puts ("Burst length(s)             ");
 	if (data[16] & 0x80) puts (" Page");
 	if (data[16] & 0x08) puts (" 8");
 	if (data[16] & 0x04) puts (" 4");
 	if (data[16] & 0x02) puts (" 2");
 	if (data[16] & 0x01) puts (" 1");
 	putc ('\n');
 	printf ("Number of banks              %d\n", data[17]);
 	switch (type) {
 	case DDR2:
 		puts ("CAS latency(s)              ");
 		decode_bits (data[18], decode_CAS_DDR2, 0);
 		putc ('\n');
 		break;
 	default:
 		puts ("CAS latency(s)              ");
 		decode_bits (data[18], decode_CAS_default, 0);
 		putc ('\n');
 		break;
 	}
 	if (DDR2 != type) {
 		puts ("CS latency(s)               ");
 		decode_bits (data[19], decode_CS_WE_default, 0);
 		putc ('\n');
 	}
 	if (DDR2 != type) {
 		puts ("WE latency(s)               ");
 		decode_bits (data[20], decode_CS_WE_default, 0);
 		putc ('\n');
 	}
 	switch (type) {
 	case DDR2:
 		puts ("Module attributes:\n");
 		if (data[21] & 0x80)
 			puts ("  TBD (bit 7)\n");
 		if (data[21] & 0x40)
 			puts ("  Analysis probe installed\n");
 		if (data[21] & 0x20)
 			puts ("  TBD (bit 5)\n");
 		if (data[21] & 0x10)
 			puts ("  FET switch external enable\n");
 		printf ("  %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
 		if (data[20] & 0x11) {
 			printf ("  %d active registers on DIMM\n",
 				(data[21] & 0x03) + 1);
 		}
 		break;
 	default:
 		puts ("Module attributes:\n");
 		if (!data[21])
 			puts ("  (none)\n");
 		else
 			decode_bits (data[21], decode_byte21_default, 0);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		decode_bits (data[22], decode_byte22_DDR2, 0);
 		break;
 	default:
 		puts ("Device attributes:\n");
 		if (data[22] & 0x80) puts ("  TBD (bit 7)\n");
 		if (data[22] & 0x40) puts ("  TBD (bit 6)\n");
 		if (data[22] & 0x20) puts ("  Upper Vcc tolerance 5%\n");
 		else                 puts ("  Upper Vcc tolerance 10%\n");
 		if (data[22] & 0x10) puts ("  Lower Vcc tolerance 5%\n");
 		else                 puts ("  Lower Vcc tolerance 10%\n");
 		if (data[22] & 0x08) puts ("  Supports write1/read burst\n");
 		if (data[22] & 0x04) puts ("  Supports precharge all\n");
 		if (data[22] & 0x02) puts ("  Supports auto precharge\n");
 		if (data[22] & 0x01) puts ("  Supports early RAS# precharge\n");
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("SDRAM cycle time (2nd highest CAS latency)        ");
 		print_ddr2_tcyc (data[23]);
 		break;
 	default:
 		printf ("SDRAM cycle time (2nd highest CAS latency)        %d."
 			"%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("SDRAM access from clock (2nd highest CAS latency) 0."
 			"%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
 		break;
 	default:
 		printf ("SDRAM access from clock (2nd highest CAS latency) %d."
 			"%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("SDRAM cycle time (3rd highest CAS latency)        ");
 		print_ddr2_tcyc (data[25]);
 		break;
 	default:
 		printf ("SDRAM cycle time (3rd highest CAS latency)        %d."
 			"%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("SDRAM access from clock (3rd highest CAS latency) 0."
 			"%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
 		break;
 	default:
 		printf ("SDRAM access from clock (3rd highest CAS latency) %d."
 			"%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("Minimum row precharge        %d.%02d ns\n",
 			(data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
 		break;
 	default:
 		printf ("Minimum row precharge        %d ns\n", data[27]);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("Row active to row active min %d.%02d ns\n",
 			(data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
 		break;
 	default:
 		printf ("Row active to row active min %d ns\n", data[28]);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("RAS to CAS delay min         %d.%02d ns\n",
 			(data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
 		break;
 	default:
 		printf ("RAS to CAS delay min         %d ns\n", data[29]);
 		break;
 	}
 	printf ("Minimum RAS pulse width      %d ns\n", data[30]);
 	switch (type) {
 	case DDR2:
 		puts ("Density of each row          ");
 		decode_bits (data[31], decode_row_density_DDR2, 1);
 		putc ('\n');
 		break;
 	default:
 		puts ("Density of each row          ");
 		decode_bits (data[31], decode_row_density_default, 1);
 		putc ('\n');
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		puts ("Command and Address setup    ");
 		if (data[32] >= 0xA0) {
 			printf ("1.%d%d ns\n",
 				((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
 		} else {
 			printf ("0.%d%d ns\n",
 				((data[32] >> 4) & 0x0F), data[32] & 0x0F);
 		}
 		break;
 	default:
 		printf ("Command and Address setup    %c%d.%d ns\n",
 			(data[32] & 0x80) ? '-' : '+',
 			(data[32] >> 4) & 0x07, data[32] & 0x0F);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		puts ("Command and Address hold     ");
 		if (data[33] >= 0xA0) {
 			printf ("1.%d%d ns\n",
 				((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
 		} else {
 			printf ("0.%d%d ns\n",
 				((data[33] >> 4) & 0x0F), data[33] & 0x0F);
 		}
 		break;
 	default:
 		printf ("Command and Address hold     %c%d.%d ns\n",
 			(data[33] & 0x80) ? '-' : '+',
 			(data[33] >> 4) & 0x07, data[33] & 0x0F);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("Data signal input setup      0.%d%d ns\n",
 			(data[34] >> 4) & 0x0F, data[34] & 0x0F);
 		break;
 	default:
 		printf ("Data signal input setup      %c%d.%d ns\n",
 			(data[34] & 0x80) ? '-' : '+',
 			(data[34] >> 4) & 0x07, data[34] & 0x0F);
 		break;
 	}
 	switch (type) {
 	case DDR2:
 		printf ("Data signal input hold       0.%d%d ns\n",
 			(data[35] >> 4) & 0x0F, data[35] & 0x0F);
 		break;
 	default:
 		printf ("Data signal input hold       %c%d.%d ns\n",
 			(data[35] & 0x80) ? '-' : '+',
 			(data[35] >> 4) & 0x07, data[35] & 0x0F);
 		break;
 	}
 	puts ("Manufacturer's JEDEC ID      ");
 	for (j = 64; j <= 71; j++)
 		printf ("%02X ", data[j]);
 	putc ('\n');
 	printf ("Manufacturing Location       %02X\n", data[72]);
 	puts ("Manufacturer's Part Number   ");
 	for (j = 73; j <= 90; j++)
 		printf ("%02X ", data[j]);
 	putc ('\n');
 	printf ("Revision Code                %02X %02X\n", data[91], data[92]);
 	printf ("Manufacturing Date           %02X %02X\n", data[93], data[94]);
 	puts ("Assembly Serial Number       ");
 	for (j = 95; j <= 98; j++)
 		printf ("%02X ", data[j]);
 	putc ('\n');
 	if (DDR2 != type) {
 		printf ("Speed rating                 PC%d\n",
 			data[126] == 0x66 ? 66 : data[126]);
 	}
 	return 0;
 }
 #endif
-#if defined(CONFIG_I2C_CMD_TREE)
 int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	return 0;
 }
 #if defined(CONFIG_I2C_MUX)
 int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	int ret=0;
 	if (argc == 1) {
 		/* show all busses */
 		I2C_MUX		*mux;
 		I2C_MUX_DEVICE	*device = i2c_mux_devices;
 		printf ("Busses reached over muxes:\n");
 		while (device != NULL) {
 			printf ("Bus ID: %x\n", device->busid);
 			printf ("  reached over Mux(es):\n");
 			mux = device->mux;
 			while (mux != NULL) {
 				printf ("    %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
 				mux = mux->next;
 			}
 			device = device->next;
 		}
 	} else {
 		I2C_MUX_DEVICE *dev;
 		dev = i2c_mux_ident_muxstring ((uchar *)argv[1]);
 		ret = 0;
 	}
 	return ret;
 }
 #endif  /* CONFIG_I2C_MUX */
 #if defined(CONFIG_I2C_MULTI_BUS)
 int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	int bus_idx, ret=0;
 	if (argc == 1)
 		/* querying current setting */
 		printf("Current bus is %d\n", i2c_get_bus_num());
 	else {
 		bus_idx = simple_strtoul(argv[1], NULL, 10);
 		printf("Setting bus to %d\n", bus_idx);
 		ret = i2c_set_bus_num(bus_idx);
 		if (ret)
 			printf("Failure changing bus number (%d)\n", ret);
 	}
 	return ret;
 }
 #endif  /* CONFIG_I2C_MULTI_BUS */
 int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	int speed, ret=0;
 	if (argc == 1)
 		/* querying current speed */
 		printf("Current bus speed=%d\n", i2c_get_bus_speed());
 	else {
 		speed = simple_strtoul(argv[1], NULL, 10);
 		printf("Setting bus speed to %d Hz\n", speed);
 		ret = i2c_set_bus_speed(speed);
 		if (ret)
 			printf("Failure changing bus speed (%d)\n", ret);
 	}
 	return ret;
 }
 int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 #if defined(CONFIG_I2C_MUX)
 	if (!strncmp(argv[1], "bu", 2))
 		return do_i2c_add_bus(cmdtp, flag, --argc, ++argv);
 #endif  /* CONFIG_I2C_MUX */
 	if (!strncmp(argv[1], "sp", 2))
 		return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
 #if defined(CONFIG_I2C_MULTI_BUS)
 	if (!strncmp(argv[1], "de", 2))
 		return do_i2c_bus_num(cmdtp, flag, --argc, ++argv);
 #endif  /* CONFIG_I2C_MULTI_BUS */
 	if (!strncmp(argv[1], "md", 2))
 		return do_i2c_md(cmdtp, flag, --argc, ++argv);
 	if (!strncmp(argv[1], "mm", 2))
 		return do_i2c_mm(cmdtp, flag, --argc, ++argv);
 	if (!strncmp(argv[1], "mw", 2))
 		return do_i2c_mw(cmdtp, flag, --argc, ++argv);
 	if (!strncmp(argv[1], "nm", 2))
 		return do_i2c_nm(cmdtp, flag, --argc, ++argv);
 	if (!strncmp(argv[1], "cr", 2))
 		return do_i2c_crc(cmdtp, flag, --argc, ++argv);
 	if (!strncmp(argv[1], "pr", 2))
 		return do_i2c_probe(cmdtp, flag, --argc, ++argv);
 	if (!strncmp(argv[1], "re", 2))
 		return do_i2c_reset(cmdtp, flag, --argc, ++argv);
 	if (!strncmp(argv[1], "lo", 2))
 		return do_i2c_loop(cmdtp, flag, --argc, ++argv);
 #if defined(CONFIG_CMD_SDRAM)
 	if (!strncmp(argv[1], "sd", 2))
 		return do_sdram(cmdtp, flag, --argc, ++argv);
 #endif
 	else
 		cmd_usage(cmdtp);
 	return 0;
 }
-#endif  /* CONFIG_I2C_CMD_TREE */
 /***************************************************/
-#if defined(CONFIG_I2C_CMD_TREE)
 U_BOOT_CMD(
 	i2c, 6, 1, do_i2c,
 	"I2C sub-system",
 #if defined(CONFIG_I2C_MUX)
 	"bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes.\n"
 #endif  /* CONFIG_I2C_MUX */
 	"speed [speed] - show or set I2C bus speed\n"
 #if defined(CONFIG_I2C_MULTI_BUS)
 	"i2c dev [dev] - show or set current I2C bus\n"
 #endif  /* CONFIG_I2C_MULTI_BUS */
 	"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
 	"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
 	"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
 	"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
 	"i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
 	"i2c probe - show devices on the I2C bus\n"
 	"i2c reset - re-init the I2C Controller\n"
 	"i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
 #if defined(CONFIG_CMD_SDRAM)
 	"i2c sdram chip - print SDRAM configuration information\n"
 #endif
 );
-#endif /* CONFIG_I2C_CMD_TREE */
-U_BOOT_CMD(
-	imd,	4,	1,	do_i2c_md,		\
-	"i2c memory display",				\
-	"chip address[.0, .1, .2] [# of objects]\n    - i2c memory display\n" \
-);
-U_BOOT_CMD(
-	imm,	3,	1,	do_i2c_mm,
-	"i2c memory modify (auto-incrementing)",
-	"chip address[.0, .1, .2]\n"
-	"    - memory modify, auto increment address\n"
-);
-U_BOOT_CMD(
-	inm,	3,	1,	do_i2c_nm,
-	"memory modify (constant address)",
-	"chip address[.0, .1, .2]\n    - memory modify, read and keep address\n"
-);
-U_BOOT_CMD(
-	imw,	5,	1,	do_i2c_mw,
-	"memory write (fill)",
-	"chip address[.0, .1, .2] value [count]\n    - memory write (fill)\n"
-);
-U_BOOT_CMD(
-	icrc32,	5,	1,	do_i2c_crc,
-	"checksum calculation",
-	"chip address[.0, .1, .2] count\n    - compute CRC32 checksum\n"
-);
-U_BOOT_CMD(
-	iprobe,	1,	1,	do_i2c_probe,
-	"probe to discover valid I2C chip addresses",
-	"\n    -discover valid I2C chip addresses\n"
-);
-/*
- * Require full name for "iloop" because it is an infinite loop!
- */
-U_BOOT_CMD(
-	iloop,	5,	1,	do_i2c_loop,
-	"infinite loop on address range",
-	"chip address[.0, .1, .2] [# of objects]\n"
-	"    - loop, reading a set of addresses\n"
-);
-#if defined(CONFIG_CMD_SDRAM)
-U_BOOT_CMD(
-	isdram,	2,	1,	do_sdram,
-	"print SDRAM configuration information",
-	"chip\n    - print SDRAM configuration information\n"
-	"      (valid chip values 50..57)\n"
-);
-#endif
 #if defined(CONFIG_I2C_MUX)
 int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
 {
 	I2C_MUX_DEVICE	*devtmp = i2c_mux_devices;
 	if (i2c_mux_devices == NULL) {
 		i2c_mux_devices = dev;
 		return 0;
 	}
 	while (devtmp->next != NULL)
 		devtmp = devtmp->next;
 	devtmp->next = dev;
 	return 0;
 }
 I2C_MUX_DEVICE	*i2c_mux_search_device(int id)
 {
 	I2C_MUX_DEVICE	*device = i2c_mux_devices;
 	while (device != NULL) {
 		if (device->busid == id)
 			return device;
 		device = device->next;
 	}
 	return NULL;
 }
 /* searches in the buf from *pos the next ':'.
  * returns:
  *     0 if found (with *pos = where)
  *   < 0 if an error occured
  *   > 0 if the end of buf is reached
  */
 static int i2c_mux_search_next (int *pos, uchar	*buf, int len)
 {
 	while ((buf[*pos] != ':') && (*pos < len)) {
 		*pos += 1;
 	}
 	if (*pos >= len)
 		return 1;
 	if (buf[*pos] != ':')
 		return -1;
 	return 0;
 }
 static int i2c_mux_get_busid (void)
 {
 	int	tmp = i2c_mux_busid;
 	i2c_mux_busid ++;
 	return tmp;
 }
 /* Analyses a Muxstring and sends immediately the
    Commands to the Muxes. Runs from Flash.
  */
 int i2c_mux_ident_muxstring_f (uchar *buf)
 {
 	int	pos = 0;
 	int	oldpos;
 	int	ret = 0;
 	int	len = strlen((char *)buf);
 	int	chip;
 	uchar	channel;
 	int	was = 0;
 	while (ret == 0) {
 		oldpos = pos;
 		/* search name */
 		ret = i2c_mux_search_next(&pos, buf, len);
 		if (ret != 0)
 			printf ("ERROR\n");
 		/* search address */
 		pos ++;
 		oldpos = pos;
 		ret = i2c_mux_search_next(&pos, buf, len);
 		if (ret != 0)
 			printf ("ERROR\n");
 		buf[pos] = 0;
 		chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
 		buf[pos] = ':';
 		/* search channel */
 		pos ++;
 		oldpos = pos;
 		ret = i2c_mux_search_next(&pos, buf, len);
 		if (ret < 0)
 			printf ("ERROR\n");
 		was = 0;
 		if (buf[pos] != 0) {
 			buf[pos] = 0;
 			was = 1;
 		}
 		channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
 		if (was)
 			buf[pos] = ':';
 		if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
 			printf ("Error setting Mux: chip:%x channel: \
 				%x\n", chip, channel);
 			return -1;
 		}
 		pos ++;
 		oldpos = pos;
 	}
 	return 0;
 }
 /* Analyses a Muxstring and if this String is correct
  * adds a new I2C Bus.
  */
 I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
 {
 	I2C_MUX_DEVICE	*device;
 	I2C_MUX		*mux;
 	int	pos = 0;
 	int	oldpos;
 	int	ret = 0;
 	int	len = strlen((char *)buf);
 	int	was = 0;
 	device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
 	device->mux = NULL;
 	device->busid = i2c_mux_get_busid ();
 	device->next = NULL;
 	while (ret == 0) {
 		mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
 		mux->next = NULL;
 		/* search name of mux */
 		oldpos = pos;
 		ret = i2c_mux_search_next(&pos, buf, len);
 		if (ret != 0)
 			printf ("%s no name.\n", __FUNCTION__);
 		mux->name = (char *)malloc (pos - oldpos + 1);
 		memcpy (mux->name, &buf[oldpos], pos - oldpos);
 		mux->name[pos - oldpos] = 0;
 		/* search address */
 		pos ++;
 		oldpos = pos;
 		ret = i2c_mux_search_next(&pos, buf, len);
 		if (ret != 0)
 			printf ("%s no mux address.\n", __FUNCTION__);
 		buf[pos] = 0;
 		mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
 		buf[pos] = ':';
 		/* search channel */
 		pos ++;
 		oldpos = pos;
 		ret = i2c_mux_search_next(&pos, buf, len);
 		if (ret < 0)
 			printf ("%s no mux channel.\n", __FUNCTION__);
 		was = 0;
 		if (buf[pos] != 0) {
 			buf[pos] = 0;
 			was = 1;
 		}
 		mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
 		if (was)
 			buf[pos] = ':';
 		if (device->mux == NULL)
 			device->mux = mux;
 		else {
 			I2C_MUX		*muxtmp = device->mux;
 			while (muxtmp->next != NULL) {
 				muxtmp = muxtmp->next;
 			}
 			muxtmp->next = mux;
 		}
 		pos ++;
 		oldpos = pos;
 	}
 	if (ret > 0) {
 		/* Add Device */
 		i2c_mux_add_device (device);
 		return device;
 	}
 	return NULL;
 }
 int i2x_mux_select_mux(int bus)
 {
 	I2C_MUX_DEVICE  *dev;
 	I2C_MUX		*mux;
 	if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
 		/* select Default Mux Bus */
 #if defined(CONFIG_SYS_I2C_IVM_BUS)
 		i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
 #else
 		{
 		unsigned char *buf;
 		buf = (unsigned char *) getenv("EEprom_ivm");
 		if (buf != NULL)
 			i2c_mux_ident_muxstring_f (buf);
 		}
 #endif
 		return 0;
 	}
 	dev = i2c_mux_search_device(bus);
 	if (dev == NULL)
 		return -1;
 	mux = dev->mux;
 	while (mux != NULL) {
 		if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
 			printf ("Error setting Mux: chip:%x channel: \
 				%x\n", mux->chip, mux->channel);
 			return -1;
 		}
 		mux = mux->next;
 	}
 	return 0;
 }
 #endif /* CONFIG_I2C_MUX */

doc/feature-removal-schedule.txt

Diff comments View file @ d48eb51

 The following is a list of files and features that are going to be
 removed from the U-Boot source tree.  Every entry should contain what
 exactly is going away, when it will be gone, why it is being removed,
 and who is going to be doing the work.  When the feature is removed
 from U-Boot, its corresponding entry should also be removed from this
 file.
 ---------------------------
 What:	CONFIG_NET_MULTI option
 When:	Release 2009-11
 Why:	U-boot currently implements two network driver APIs.  New drivers with
 	the older-style implementation have not been accepted for a while, and
 	this parallel system makes the code confusing and hard to augment.
 	All existing in-tree boards will be converted to use CONFIG_NET_MULTI
 	over the span of two releases (2009-07 and 2009-09).
 	In the 2009-11 release, all code that is compiled when CONFIG_NET_MULTI
 	is not set will be removed, and all references to CONFIG_NET_MULTI
 	will be removed, effectively making it the only API.  This should
 	provide ample time for out-of-tree users to adjust, and for tools on
 	all architectures to be made to work with weak functions.
 Who:	Ben Warren <biggerbadderben@gmail.com>
 ---------------------------
 What:	"autoscr" command
 When:	Release 2009-09
 Why:	"autosrc" is an ugly and completely non-standard name.
 	The "autoscr" command is deprecated and will be replaced by
 	the "source" command as used by other shells such as bash.
 	Starting with March 2009, both commands will be supported for
 	a transition period of 6 months after which "autoscr" will be
 	removed. During the transition period existing scripts and
 	environment variable names remain untouched for maximum
 	compatibiltiy; thse will be changed when support for the
 	"autoscr" command get's finally dropped.
 Who:	Peter Tyser <ptyser@xes-inc.com>
 ---------------------------
 What:	GPL cleanup
 When:	August 2009
 Why:	Over time, a couple of files have sneaked in into the U-Boot
 	source code that are either missing a valid GPL license
 	header or that carry a license that is incompatible with the
 	GPL.
 	Such files shall be removed from the U-Boot source tree.
 	See http://www.denx.de/wiki/pub/U-Boot/TaskGplCleanup/u-boot-1.1.2-files
 	for an old and probably incomplete list of such files.
 Who:	Wolfgang Denk <wd@denx.de> and board maintainers
 ---------------------------
-What:	Individual I2C commands
-When:	April 2009
-Why:	Per the U-Boot README, individual I2C commands such as "imd", "imm",
-	"imw", etc are deprecated.  The single "i2c" command which is
-	currently enabled via CONFIG_I2C_CMD_TREE contains the same
-	functionality as the individual I2C commands.  The individual
-	I2C commands should be removed as well as any references to
-	CONFIG_I2C_CMD_TREE.
-Who:	Peter Tyser <ptyser@xes-inc.com>
----------------------------
 What:	Legacy NAND code
 When:	April 2009
 Why:	Legacy NAND code is deprecated.  Similar functionality exists in
 	more recent NAND code ported from the Linux kernel.
 Who:	Scott Wood <scottwood@freescale.com>

include/configs/DU405.h

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2001
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * board/config.h - configuration options, board specific
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  * (easy to change)
  */
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_DU405		1	/* ...on a DU405 board		*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
 #define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND	"bootm fff00000"
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_NFS
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 #define CONFIG_RTC_MC146818		/* BQ3285 is MC146818 compatible*/
 #define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 #define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 #define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/
 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
 #define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
 #define PCI_HOST_FORCE	1		/* configure as pci host	*/
 #define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
 #define CONFIG_PCI			/* include pci support		*/
 #define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 					/* resource configuration	*/
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 #define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
 #define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
 #define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
 #define CONFIG_SYS_PCI_PTM2LA	0xffe00000	/* point to flash		*/
 #define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
 #undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
 #define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
 #define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 #define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 #define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
 #define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 #define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_FLASH_BASE		0xFFFD0000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 #define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
 #define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
 #define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
 #define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
 #define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
 #define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
  */
-#define CONFIG_I2C_CMD_TREE     1
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 /*
  * Init Memory Controller:
  *
  * BR0/1 and OR0/1 (FLASH)
  */
 #define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
 #define FLASH0_BA	0xFFC00000	    /* FLASH 0 Base Address		*/
 #define FLASH1_BA	0xFF800000	    /* FLASH 1 Base Address		*/
 #define CAN_BA		0xF0000000	    /* CAN Base Address			*/
 #define DUART_BA	0xF0300000	    /* DUART Base Address		*/
 #define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
 #define SRAM_BA		0xF0200000	    /* SRAM Base Address		*/
 #define DURAG_IO_BA	0xF0400000	    /* DURAG Bus IO Base Address	*/
 #define DURAG_MEM_BA	0xF0500000	    /* DURAG Bus Mem Base Address	*/
 #define FPGA_MODE_REG	(DUART_BA+0x80)	    /* FPGA Mode Register		*/
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
 #define CONFIG_SYS_EBC_PB0AP	0x92015480
 #define CONFIG_SYS_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 /* Memory Bank 1 (Flash Bank 1) initialization					*/
 #define CONFIG_SYS_EBC_PB1AP	0x92015480
 #define CONFIG_SYS_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 /* Memory Bank 2 (CAN0) initialization						*/
 #define CONFIG_SYS_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CONFIG_SYS_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 /* Memory Bank 3 (DUART) initialization						*/
 #define CONFIG_SYS_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CONFIG_SYS_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 /* Memory Bank 4 (CompactFlash IDE) initialization				*/
 #define CONFIG_SYS_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CONFIG_SYS_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 /* Memory Bank 5 (SRAM) initialization						*/
 #define CONFIG_SYS_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CONFIG_SYS_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 /* Memory Bank 6 (DURAG Bus IO Space) initialization				*/
 #define CONFIG_SYS_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CONFIG_SYS_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
 /* Memory Bank 7 (DURAG Bus Mem Space) initialization				*/
 #define CONFIG_SYS_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CONFIG_SYS_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 #define CONFIG_SYS_TEMP_STACK_OCM	  1
 /* On Chip Memory location */
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
 #define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 #define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 #endif	/* __CONFIG_H */

include/configs/DU440.h

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2008
  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
  *
  * based on the Sequoia board configuration by
  * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  **********************************************************************
  * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
  **********************************************************************
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_DU440		1		/* Board is esd DU440	*/
 #define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_SYS_CLK_FREQ	33333400	/* external freq to pll	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
 #define CONFIG_LAST_STAGE_INIT  1               /* last_stage_init      */
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor */
 #define CONFIG_SYS_MALLOC_LEN		(8 << 20)	/* Reserve 8 MB for malloc()  */
 #define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
 #define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 #define CONFIG_SYS_NAND0_ADDR		0xd0000000      /* NAND Flash		*/
 #define CONFIG_SYS_NAND1_ADDR		0xd0100000      /* NAND Flash		*/
 #define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
 #define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
 #define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
 #define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
 #define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
 #define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
 #define CONFIG_SYS_PCI_IOBASE          0xe8000000
 /* Don't change either of these */
 #define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
 #define CONFIG_SYS_USB2D0_BASE		0xe0000100
 #define CONFIG_SYS_USB_DEVICE		0xe0000000
 #define CONFIG_SYS_USB_HOST		0xe0000400
 /*
  * Initial RAM & stack pointer
  */
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
 #define CONFIG_SYS_INIT_RAM_OCM	1		/* OCM as init ram	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
 #define CONFIG_SYS_INIT_RAM_END	(4 << 10)
 #define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /*
  * Serial Port
  */
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI     1
 #undef CONFIG_UART1_CONSOLE
 #define CONFIG_SYS_BAUDRATE_TABLE						\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 /*
  * Video Port
  */
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_SMI_LYNXEM
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_VIDEO_BMP_GZIP              /* gzip compressed bmp images */
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_EEPROM    1	/* use FLASH for environment vars */
 /*
  * FLASH related
  */
 #define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible */
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver       */
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
 /* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
 #define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector        */
 #define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif
 #ifdef CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_OFFSET		0	/* environment starts at */
 					/* the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x1000 /* 4096 bytes may be used for env vars */
 #endif
 /*
  * DDR SDRAM
  */
 #define CONFIG_SYS_MBYTES_SDRAM        (1024)	/* 512 MiB      TODO: remove    */
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization        */
 #define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
 					/* 440EPx errata CHIP 11        */
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup     */
 #define CONFIG_DDR_ECC			/* Use ECC when available       */
 #define SPD_EEPROM_ADDRESS	{0x50}
 #define CONFIG_PROG_SDRAM_TLB
 /*
  * I2C
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support    */
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged	        */
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address  */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
-#define CONFIG_I2C_CMD_TREE     1
 #define CONFIG_I2C_MULTI_BUS    1
 #define CONFIG_SYS_SPD_BUS_NUM         0
 #define IIC1_MCP3021_ADDR	0x4d
 #define IIC1_USB2507_ADDR	0x2c
 #ifdef CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_I2C_NOPROBES        {{1, IIC1_USB2507_ADDR}}
 #endif
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x54
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
 #define CONFIG_SYS_EEPROM_WREN         1
 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 /*
  * standard dtt sensor configuration - bottom bit will determine local or
  * remote sensor of the TMP401
  */
 #define CONFIG_DTT_SENSORS		{ 0, 1 }
 /*
  * The PMC440 uses a TI TMP401 temperature sensor. This part
  * is basically compatible to the ADM1021 that is supported
  * by U-Boot.
  *
  * - i2c addr 0x4c
  * - conversion rate 0x02 = 0.25 conversions/second
  * - ALERT ouput disabled
  * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
  */
 #define CONFIG_DTT_ADM1021
 #define CONFIG_SYS_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 /*
  * RTC stuff
  */
 #define CONFIG_RTC_DS1338
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 #undef	CONFIG_BOOTARGS
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"ethrotate=no\0"						\
 	"hostname=du440\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 	"flash_self=run ramargs addip addtty optargs;"			\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;"	\
 	        "bootm\0"						\
 	"rootpath=/tftpboot/du440/target_root_du440\0"			\
 	"img=/tftpboot/du440/uImage\0"					\
 	"kernel_addr=FFC00000\0"					\
 	"ramdisk_addr=FFE00000\0"					\
 	"initrd_high=30000000\0"					\
 	"load=tftp 100000 /tftpboot/du440/u-boot.bin\0"			\
 	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
 		"cp.b 100000 FFFA0000 60000\0"				\
 	""
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 #define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 #ifndef __ASSEMBLY__
 int du440_phy_addr(int devnum);
 #endif
 #define CONFIG_PPC4xx_EMAC
 #define	CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		du440_phy_addr(0) /* PHY address	*/
 #define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
 #undef CONFIG_PHY_GIGE			/* no GbE detection		*/
 #define CONFIG_HAS_ETH0
 #define CONFIG_SYS_RX_ETH_BUFFER	128
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_PHY1_ADDR	du440_phy_addr(1)
 /*
  * USB
  */
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 #define CONFIG_SYS_USB_OHCI_CPU_INIT	1
 #define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME	"du440"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BMP
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SOURCE
 #define CONFIG_CMD_USB
 #define CONFIG_SUPPORT_VFAT
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 #define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
 #define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_MEMTEST_START	0x00400000 /* memtest works on		*/
 #define CONFIG_SYS_MEMTEST_END		0x3f000000 /* 4 ... < 1GB DRAM	*/
 #define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 #define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 #define CONFIG_AUTOBOOT_KEYED	1
 #define CONFIG_AUTOBOOT_PROMPT	\
 	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
 #define CONFIG_AUTOBOOT_DELAY_STR "d"
 #define CONFIG_AUTOBOOT_STOP_STR " "
 /*
  * PCI stuff
  */
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
 #define CONFIG_SYS_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 /* Board-specific PCI */
 #define CONFIG_SYS_PCI_TARGET_INIT
 #define CONFIG_SYS_PCI_MASTER_INIT
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)     /* Initial Memory map for Linux */
 /*
  * External Bus Controller (EBC) Setup
  */
 #define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_CPLD_BASE		0xC0000000
 #define CONFIG_SYS_CPLD_RANGE	        0x00000010
 #define CONFIG_SYS_DUMEM_BASE		0xC0100000
 #define CONFIG_SYS_DUMEM_RANGE		0x00100000
 #define CONFIG_SYS_DUIO_BASE		0xC0200000
 #define CONFIG_SYS_DUIO_RANGE	        0x00010000
 #define CONFIG_SYS_NAND0_CS		2		/* NAND chip connected to CSx */
 #define CONFIG_SYS_NAND1_CS		3		/* NAND chip connected to CSx */
 /* Memory Bank 0 (NOR-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB0AP		0x04017200
 #define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 /* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
 #define CONFIG_SYS_EBC_PB1AP		0x018003c0
 #define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_CPLD_BASE | 0x18000)
 /* Memory Bank 2 (NAND-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB2AP		0x018003c0
 #define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND0_ADDR | 0x1c000)
 /* Memory Bank 3 (NAND-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB3AP		0x018003c0
 #define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND1_ADDR | 0x1c000)
 /* Memory Bank 4 (DUMEM, 1MB) initialization */
 #define CONFIG_SYS_EBC_PB4AP		0x018053c0
 #define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_DUMEM_BASE | 0x18000)
 /* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
 #define CONFIG_SYS_EBC_PB5AP		0x018053c0
 #define CONFIG_SYS_EBC_PB5CR		(CONFIG_SYS_DUIO_BASE | 0x18000)
 /*
  * NAND FLASH
  */
 #define CONFIG_SYS_MAX_NAND_DEVICE	2
 #define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
 				 CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 #define CONFIG_SOURCE		1
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
 #endif	/* __CONFIG_H */

include/configs/MPC8313ERDB.h

Diff comments View file @ d48eb51

 /*
  * Copyright (C) Freescale Semiconductor, Inc. 2006.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * mpc8313epb board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300		1
 #define CONFIG_MPC83XX		1
 #define CONFIG_MPC831X		1
 #define CONFIG_MPC8313		1
 #define CONFIG_MPC8313ERDB	1
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI
 #define CONFIG_MISC_INIT_R
 /*
  * On-board devices
  *
  * TSEC1 is VSC switch
  * TSEC2 is SoC TSEC
  */
 #define CONFIG_VSC7385_ENET
 #define CONFIG_TSEC2
 #ifdef CONFIG_SYS_66MHZ
 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
 #elif defined(CONFIG_SYS_33MHZ)
 #define CONFIG_83XX_CLKIN	33333333	/* in Hz */
 #else
 #error Unknown oscillator frequency.
 #endif
 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 #define CONFIG_SYS_IMMR		0xE0000000
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
 #endif
 #define CONFIG_SYS_MEMTEST_START	0x00001000
 #define CONFIG_SYS_MEMTEST_END		0x07f00000
 /* Early revs of this board will lock up hard when attempting
  * to access the PMC registers, unless a JTAG debugger is
  * connected, or some resistor modifications are made.
  */
 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 /*
  * Device configurations
  */
 /* Vitesse 7385 */
 #ifdef CONFIG_VSC7385_ENET
 #define CONFIG_TSEC1
 /* The flash address and size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
 #define CONFIG_VSC7385_IMAGE_SIZE	8192
 #endif
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 /*
  * Manually set up DDR parameters, as this board does not
  * seem to have the SPD connected to I2C.
  */
 #define CONFIG_SYS_DDR_SIZE		128		/* MB */
 #define CONFIG_SYS_DDR_CONFIG		( CSCONFIG_EN \
 				| 0x00010000 /* TODO */ \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
 				/* 0x80010102 */
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 #define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
 				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
 				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
 				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 				/* 0x00220802 */
 #define CONFIG_SYS_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
 				| ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 				| (10 << TIMING_CFG1_REFREC_SHIFT ) \
 				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 				/* 0x3835a322 */
 #define CONFIG_SYS_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 				| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 				| ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 				/* 0x129048c6 */ /* P9-45,may need tuning */
 #define CONFIG_SYS_DDR_INTERVAL	( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 				| ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 				/* 0x05100500 */
 #if defined(CONFIG_DDR_2T_TIMING)
 #define CONFIG_SYS_SDRAM_CFG		( SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 				| SDRAM_CFG_2T_EN \
 				| SDRAM_CFG_DBW_32 )
 #else
 #define CONFIG_SYS_SDRAM_CFG		( SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 				| SDRAM_CFG_32_BE )
 				/* 0x43080000 */
 #endif
 #define CONFIG_SYS_SDRAM_CFG2		0x00401000
 /* set burst length to 8 for 32-bit data path */
 #define CONFIG_SYS_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
 				| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
 				/* 0x44480632 */
 #define CONFIG_SYS_DDR_MODE_2		0x8000C000
 #define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 				/*0x02000000*/
 #define CONFIG_SYS_DDRCDR_VALUE	( DDRCDR_EN \
 				| DDRCDR_PZ_NOMZ \
 				| DDRCDR_NZ_NOMZ \
 				| DDRCDR_M_ODR )
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		8		/* flash size in MB */
 #define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 #define CONFIG_SYS_FLASH_EMPTY_INFO			/* display empty sectors */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE |	/* flash Base address */ \
 				(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
 				BR_V)			/* valid */
 #define CONFIG_SYS_NOR_OR_PRELIM	( 0xFF800000		/* 8 MByte */ \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_9 \
 				| OR_GPCM_EHTR \
 				| OR_GPCM_EAD )
 				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* window base at flash base */
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000017	/* 16 MB window size */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	135		/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 #define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
 /*
  * Local Bus LCRR and LBCR regs
  */
 #define CONFIG_SYS_LCRR	LCRR_EADC_1 | LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	( 0x00040000 /* TODO */ \
 			| (0xFF << LBCR_BMT_SHIFT) \
 			| 0xF )	/* 0x0004ff0f */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */	/* LB refresh timer prescal, 266MHz/32 */
 /* drivers/mtd/nand/nand.c */
 #ifdef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE		0xFFF00000
 #else
 #define CONFIG_SYS_NAND_BASE		0xE2800000
 #endif
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND 1
 #define CONFIG_NAND_FSL_ELBC 1
 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 #define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 				| BR_PS_8		/* Port Size = 8 bit */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
 				| BR_V )		/* valid */
 #define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFF8000		/* length 32K */ \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
 				| OR_FCM_SCY_1 \
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR )
 				/* 0xFFFF8396 */
 #ifdef CONFIG_NAND_U_BOOT
 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 #else
 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 #endif
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 /* local bus read write buffer mapping */
 #define CONFIG_SYS_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
 #define CONFIG_SYS_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
 #define CONFIG_SYS_LBLAWBAR3_PRELIM	0xFA000000
 #define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
 /* Vitesse 7385 */
 #define CONFIG_SYS_VSC7385_BASE	0xF0000000
 #ifdef CONFIG_VSC7385_ENET
 #define CONFIG_SYS_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
 #define CONFIG_SYS_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */
 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
 #endif
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}} /* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 /*
  * TSEC
  */
 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
 #define CONFIG_NET_MULTI
 #define CONFIG_GMII			/* MII PHY management */
 #ifdef CONFIG_TSEC1
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
 #define TSEC1_PHY_ADDR		0x1c
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC1_PHYIDX		0
 #endif
 #ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME	"TSEC1"
 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
 #define TSEC2_PHY_ADDR		4
 #define TSEC2_FLAGS		TSEC_GIGABIT
 #define TSEC2_PHYIDX		0
 #endif
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC1"
 /*
  * Configure on-board RTC
  */
 #define CONFIG_RTC_DS1337
 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
 /*
  * Environment
  */
 #if defined(CONFIG_NAND_U_BOOT)
 	#define CONFIG_ENV_IS_IN_NAND	1
 	#define CONFIG_ENV_OFFSET		(512 * 1024)
 	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
 	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
 	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 #elif !defined(CONFIG_SYS_RAMBOOT)
 	#define CONFIG_ENV_IS_IN_FLASH	1
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 /* Address and size of Redundant Environment Sector */
 #else
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
     #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 #define CONFIG_CMDLINE_EDITING 1
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
 #ifdef CONFIG_SYS_66MHZ
 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 /* 0x62040000 */
 #define CONFIG_SYS_HRCW_LOW (\
 	0x20000000 /* reserved, must be set */ |\
 	HRCWL_DDRCM |\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
 	HRCWL_CSB_TO_CLKIN_2X1 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 #elif defined(CONFIG_SYS_33MHZ)
 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 /* 0x65040000 */
 #define CONFIG_SYS_HRCW_LOW (\
 	0x20000000 /* reserved, must be set */ |\
 	HRCWL_DDRCM |\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
 	HRCWL_CSB_TO_CLKIN_5X1 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 #endif
 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_TSEC1M_IN_RGMII |\
 	HRCWH_TSEC2M_IN_RGMII |\
 	HRCWH_BIG_ENDIAN)
 #ifdef CONFIG_NAND_SPL
 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 		       HRCWH_FROM_0XFFF00100 |\
 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
 		       HRCWH_RL_EXT_NAND)
 #else
 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 		       HRCWH_FROM_0X00000100 |\
 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
 		       HRCWH_RL_EXT_LEGACY)
 #endif
 /* System IO Config */
 #define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
 #define CONFIG_SYS_SICRL	SICRL_USBDR			/* Enable Internal USB Phy  */
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
 			 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 #define CONFIG_SYS_HID2 HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR @ 0x00000000 */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 /* PCI @ 0x80000000 */
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 /* PCI2 not supported on 8313 */
 #define CONFIG_SYS_IBAT3L	(0)
 #define CONFIG_SYS_IBAT3U	(0)
 #define CONFIG_SYS_IBAT4L	(0)
 #define CONFIG_SYS_IBAT4U	(0)
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT7L	(0)
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02	/* Software reboot */
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_ETHADDR		00:E0:0C:00:95:01
 #define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
 #define CONFIG_IPADDR		10.0.0.2
 #define CONFIG_SERVERIP		10.0.0.1
 #define CONFIG_GATEWAYIP	10.0.0.1
 #define CONFIG_NETMASK		255.0.0.0
 #define CONFIG_NETDEV		eth1
 #define CONFIG_HOSTNAME		mpc8313erdb
 #define CONFIG_ROOTPATH		/nfs/root/path
 #define CONFIG_BOOTFILE		uImage
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 #define CONFIG_FDTFILE		mpc8313erdb.dtb
 #define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
 	"ethprime=TSEC1\0"						\
 	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
 	"tftpflash=tftpboot $loadaddr $uboot; "				\
 		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
 		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
 		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
 	"fdtaddr=400000\0"						\
 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
 	"console=ttyS0\0"						\
 	"setbootargs=setenv bootargs "					\
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv rootdev /dev/nfs;"					\
 	"run setbootargs;"						\
 	"run setipargs;"						\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"setenv rootdev /dev/ram;"					\
 	"run setbootargs;"						\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #undef MK_STR
 #undef XMK_STR
 #endif	/* __CONFIG_H */

include/configs/MPC8349EMDS.h

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * mpc8349emds board configuration file
  *
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC83XX		1	/* MPC83XX family */
 #define CONFIG_MPC834X		1	/* MPC834X family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
 #undef CONFIG_PCI
 #undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
 #define PCI_66M
 #ifdef PCI_66M
 #define CONFIG_83XX_CLKIN	66000000	/* in Hz */
 #else
 #define CONFIG_83XX_CLKIN	33000000	/* in Hz */
 #endif
 #ifdef CONFIG_PCISLAVE
 #define CONFIG_PCI
 #define CONFIG_83XX_PCICLK	66666666	/* in Hz */
 #endif /* CONFIG_PCISLAVE */
 #ifndef CONFIG_SYS_CLK_FREQ
 #ifdef PCI_66M
 #define CONFIG_SYS_CLK_FREQ	66000000
 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
 #else
 #define CONFIG_SYS_CLK_FREQ	33000000
 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
 #endif
 #endif
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 #define CONFIG_SYS_IMMR		0xE0000000
 #undef CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START	0x00000000      /* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x00100000
 /*
  * DDR Setup
  */
 #define CONFIG_DDR_ECC			/* support DDR ECC function */
 #define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 /*
  * 32-bit data path mode.
  *
  * Please note that using this mode for devices with the real density of 64-bit
  * effectively reduces the amount of available memory due to the effect of
  * wrapping around while translating address to row/columns, for example in the
  * 256MB module the upper 128MB get aliased with contents of the lower
  * 128MB); normally this define should be used for devices with real 32-bit
  * data path.
  */
 #undef CONFIG_DDR_32BIT
 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING
 /*
  * DDRCDR - DDR Control Driver Register
  */
 #define CONFIG_SYS_DDRCDR_VALUE	0x80080001
 #if defined(CONFIG_SPD_EEPROM)
 /*
  * Determine DDR configuration from I2C interface.
  */
 #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
 #else
 /*
  * Manually set up DDR parameters
  */
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
 #if defined(CONFIG_DDR_II)
 #define CONFIG_SYS_DDRCDR		0x80080001
 #define CONFIG_SYS_DDR_CS2_BNDS	0x0000000f
 #define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
 #define CONFIG_SYS_DDR_TIMING_0	0x00220802
 #define CONFIG_SYS_DDR_TIMING_1	0x38357322
 #define CONFIG_SYS_DDR_TIMING_2	0x2f9048c8
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 #define CONFIG_SYS_DDR_CLK_CNTL	0x02000000
 #define CONFIG_SYS_DDR_MODE		0x47d00432
 #define CONFIG_SYS_DDR_MODE2		0x8000c000
 #define CONFIG_SYS_DDR_INTERVAL	0x03cf0080
 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #else
 #define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_1	0x36332321
 #define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
 #define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
 #define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
 #if defined(CONFIG_DDR_32BIT)
 /* set burst length to 8 for 32-bit data path */
 #define CONFIG_SYS_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
 #else
 /* the default burst length is 4 - for 64-bit data path */
 #define CONFIG_SYS_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
 #endif
 #endif
 #endif
 /*
  * SDRAM on the Local Bus
  */
 #define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
 #define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		32		/* max flash size in MB */
 #define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE |	/* flash Base address */ \
 				(2 << BR_PS_SHIFT) |	/* 16 bit port size */	 \
 				BR_V)			/* valid */
 #define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* window base at flash base */
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018	/* 32 MB window size */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MID_FLASH_JUMP	0x7F000000
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef  CONFIG_SYS_RAMBOOT
 #endif
 /*
  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
  */
 #define CONFIG_SYS_BCSR		0xE2400000
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR		/* Access window base at BCSR base */
 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E		/* Access window size 32K */
 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801)	/* Port-size=8bit, MSEL=GPCM */
 #define CONFIG_SYS_OR1_PRELIM		0xFFFFE8F0		/* length 32K */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000			/* End of used area in RAM*/
 #define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
 /*
  * Local Bus LCRR and LBCR regs
  *    LCRR:  DLL bypass, Clock divider is 4
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
 #define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 /*
  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
  */
 #undef CONFIG_SYS_LB_SDRAM
 #ifdef CONFIG_SYS_LB_SDRAM
 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  *    port-size = 32-bits = BR2[19:20] = 11
  *    no parity checking = BR2[21:22] = 00
  *    SDRAM for MSEL = BR2[24:26] = 011
  *    Valid = BR[31] = 1
  *
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  *
  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 #define CONFIG_SYS_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 #define CONFIG_SYS_LBLAWBAR2_PRELIM	0xF0000000
 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019 /* 64M */
 /*
  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
  *                 XAM, OR2[17:18] = 11
  *    9 columns OR2[19-21] = 010
  *    13 rows   OR2[23-25] = 100
  *    EAD set for extra time OR[31] = 1
  *
  * 0    4    8    12   16   20   24   28
  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  */
 #define CONFIG_SYS_OR2_PRELIM	0xFC006901
 #define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 #define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
 				| LSDMR_BSMA1516	\
 				| LSDMR_RFCR8		\
 				| LSDMR_PRETOACT6	\
 				| LSDMR_ACTTORW3	\
 				| LSDMR_BL8		\
 				| LSDMR_WRC3		\
 				| LSDMR_CL3		\
 				)
 /*
  * SDRAM Controller configuration sequence.
  */
 #define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 #define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 #define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 #define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 #define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 #endif
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX     1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 /* SPI */
 #define CONFIG_MPC8XXX_SPI
 #undef CONFIG_SOFT_SPI			/* SPI bit-banged */
 /* GPIOs.  Used as SPI chip selects */
 #define CONFIG_SYS_GPIO1_PRELIM
 #define CONFIG_SYS_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
 #define CONFIG_SYS_GPIO1_DAT		0xC0000000  /* Both are active LOW */
 /* TSEC */
 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 /* USB */
 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 #define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
 #define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
 #define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS	0xE2100000
 #define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
 #if defined(CONFIG_PCI)
 #define PCI_ONE_PCI1
 #if defined(PCI_64BIT)
 #undef PCI_ALL_PCI1
 #undef PCI_TWO_PCI1
 #undef PCI_ONE_PCI1
 #endif
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 #define CONFIG_83XX_GENERIC_PCI
 #define CONFIG_83XX_PCI_STREAMING
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 #if !defined(CONFIG_PCI_PNP)
 	#define PCI_ENET0_IOADDR	0xFIXME
 	#define PCI_ENET0_MEMADDR	0xFIXME
 	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 #endif	/* CONFIG_PCI */
 /*
  * TSEC configuration
  */
 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
 #if defined(CONFIG_TSEC_ENET)
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
 #endif
 #define CONFIG_GMII		1	/* MII PHY management */
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC2_FLAGS		TSEC_GIGABIT
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"TSEC0"
 #endif	/* CONFIG_TSEC_ENET */
 /*
  * Configure on-board RTC
  */
 #define CONFIG_RTC_DS1374			/* use ds1374 rtc via i2c	*/
 #define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
 /*
  * Environment
  */
 #ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #else
 	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_MII
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
 #endif
 #if defined(CONFIG_SYS_RAMBOOT)
     #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
 	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 #if 1 /*528/264*/
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X2 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*396/132*/
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_3X1)
 #elif 0 /*264/132*/
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*132/132*/
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_1X1)
 #elif 0 /*264/264 */
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_1X1)
 #endif
 #ifdef CONFIG_PCISLAVE
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_AGENT |\
 	HRCWH_64_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_DISABLE |\
 	HRCWH_PCI2_ARBITER_DISABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
 #if defined(PCI_64BIT)
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_64_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCI2_ARBITER_DISABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCI2_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #endif /* PCI_64BIT */
 #endif /* CONFIG_PCISLAVE */
 /*
  * System performance
  */
 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 #define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
 #define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
 /* System IO Config */
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
 /* #define CONFIG_SYS_HID0_FINAL		(\
 	HID0_ENABLE_INSTRUCTION_CACHE |\
 	HID0_ENABLE_M_BIT |\
 	HID0_ENABLE_ADDRESS_BROADCAST ) */
 #define CONFIG_SYS_HID2 HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR @ 0x00000000 */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 /* PCI @ 0x80000000 */
 #ifdef CONFIG_PCI
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT1L	(0)
 #define CONFIG_SYS_IBAT1U	(0)
 #define CONFIG_SYS_IBAT2L	(0)
 #define CONFIG_SYS_IBAT2U	(0)
 #endif
 #ifdef CONFIG_MPC83XX_PCI2
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT3L	(0)
 #define CONFIG_SYS_IBAT3U	(0)
 #define CONFIG_SYS_IBAT4L	(0)
 #define CONFIG_SYS_IBAT4U	(0)
 #endif
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 				 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT7L	(0)
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02	/* Software reboot */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_ETHADDR		00:04:9f:ef:23:33
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH0
 #define CONFIG_ETH1ADDR		00:E0:0C:00:7E:21
 #endif
 #define CONFIG_IPADDR		192.168.1.253
 #define CONFIG_HOSTNAME		mpc8349emds
 #define CONFIG_ROOTPATH		/nfsroot/rootfs
 #define CONFIG_BOOTFILE		uImage
 #define CONFIG_SERVERIP		192.168.1.1
 #define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
 #define CONFIG_BAUDRATE	 115200
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"hostname=mpc8349emds\0"					\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 	"flash_nfs=run nfsargs addip addtty;"				\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip addtty;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
 		"bootm\0"						\
 	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
 	"update=protect off fe000000 fe03ffff; "			\
 		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"	\
 	"upd=run load update\0"						\
 	"fdtaddr=400000\0"						\
 	"fdtfile=mpc8349emds.dtb\0"					\
 	""
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
       "nfsroot=$serverip:$rootpath "                                    \
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
    "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
    "setenv bootargs root=/dev/ram rw "                                  \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $ramdiskaddr $ramdiskfile;"                                    \
    "tftp $loadaddr $bootfile;"                                          \
    "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 #endif	/* __CONFIG_H */

include/configs/MPC8349ITX.h

Diff comments View file @ d48eb51

 /*
  * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
  Memory map:
  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  0xF001_0000-0xF001_FFFF Local bus expansion slot
  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  I2C address list:
 						Align.	Board
  Bus	Addr	Part No.	Description	Length	Location
  ----------------------------------------------------------------
  I2C0	0x50	M24256-BWMN6P	Board EEPROM	2	U64
  I2C1	0x20	PCF8574		I2C Expander	0	U8
  I2C1	0x21	PCF8574		I2C Expander	0	U10
  I2C1	0x38	PCF8574A	I2C Expander	0	U8
  I2C1	0x39	PCF8574A	I2C Expander	0	U10
  I2C1	0x51	(DDR)		DDR EEPROM	1	U1
  I2C1	0x68	DS1339		RTC		1	U68
  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
 */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #if (TEXT_BASE == 0xFE000000)
 #define CONFIG_SYS_LOWBOOT
 #endif
 /*
  * High Level Configuration Options
  */
 #define CONFIG_MPC834X		/* MPC834x family (8343, 8347, 8349) */
 #define CONFIG_MPC8349		/* MPC8349 specific */
 #define CONFIG_SYS_IMMR		0xE0000000	/* The IMMR is relocated to here */
 #define CONFIG_MISC_INIT_F
 #define CONFIG_MISC_INIT_R
 /*
  * On-board devices
  */
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_COMPACT_FLASH	/* The CF card interface on the back of the board */
 #define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
 #define CONFIG_SATA_SIL3114	/* SIL3114 SATA controller */
 #endif
 #define CONFIG_PCI
 #define CONFIG_RTC_DS1337
 #define CONFIG_HARD_I2C
 #define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
 /*
  * Device configurations
  */
 /* I2C */
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 #define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
 #define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC */
 #define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
 #define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
 #define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
 #define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* I2C1, DS1339 RTC*/
 #define SPD_EEPROM_ADDRESS	0x51	/* I2C1, DDR */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 /* Don't probe these addresses: */
 #define CONFIG_SYS_I2C_NOPROBES	{{1, CONFIG_SYS_I2C_8574_ADDR1}, \
 				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
 				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
 				 {1, CONFIG_SYS_I2C_8574A_ADDR2}}
 /* Bit definitions for the 8574[A] I2C expander */
 #define I2C_8574_REVISION	0x03	/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
 #define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
 #define I2C_8574_MPCICLKRN	0x10	/* MiniPCI Clk Run */
 #define I2C_8574_PCI66		0x20	/* 0=33MHz PCI, 1=66MHz PCI */
 #define I2C_8574_FLASHSIDE	0x40	/* 0=Reset vector from U4, 1=from U7*/
 #undef CONFIG_SOFT_I2C
 #endif
 /* Compact Flash */
 #ifdef CONFIG_COMPACT_FLASH
 #define CONFIG_SYS_IDE_MAXBUS		1
 #define CONFIG_SYS_IDE_MAXDEVICE	1
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 #define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
 #define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
 #define CONFIG_SYS_ATA_REG_OFFSET	0
 #define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
 #define CONFIG_SYS_ATA_STRIDE		2
 #define ATA_RESET_TIME	1	/* If a CF card is not inserted, time out quickly */
 #endif
 /*
  * SATA
  */
 #ifdef CONFIG_SATA_SIL3114
 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 #define CONFIG_LIBATA
 #define CONFIG_LBA48
 #endif
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_MEMTEST_START	0x1000		/* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x2000
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 #endif
 #ifndef CONFIG_SPD_EEPROM	/* No SPD? Then manually set up DDR parameters */
     #define CONFIG_SYS_DDR_SIZE	256		/* Mb */
     #define CONFIG_SYS_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
     #define CONFIG_SYS_DDR_TIMING_1	0x26242321
     #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
 #endif
 /*
  *Flash on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_MAX_FLASH_SECT	135	/* 127 64KB sectors + 8 8KB sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 #define CONFIG_SYS_FLASH_SIZE		16		/* FLASH size in MB */
 #define CONFIG_SYS_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
 #define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 /* Vitesse 7385 */
 #ifdef CONFIG_VSC7385_ENET
 #define CONFIG_TSEC2
 /* The flash address and size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE		0xFEFFE000
 #define CONFIG_VSC7385_IMAGE_SIZE	8192
 #endif
 /*
  * BRx, ORx, LBLAWBARx, and LBLAWARx
  */
 /* Flash */
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
 /* Vitesse 7385 */
 #define CONFIG_SYS_VSC7385_BASE	0xF8000000
 #ifdef CONFIG_VSC7385_ENET
 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 				OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_VSC7385_BASE
 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
 #endif
 /* LED */
 #define CONFIG_SYS_LED_BASE		0xF9000000
 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
 				OR_GPCM_EHTR | OR_GPCM_EAD)
 /* Compact Flash */
 #ifdef CONFIG_COMPACT_FLASH
 #define CONFIG_SYS_CF_BASE		0xF0000000
 #define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		(OR_UPM_AM | OR_UPM_BI)
 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_CF_BASE
 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
 #endif
 /*
  * U-Boot memory configuration
  */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 #define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 /*
  * Local Bus LCRR and LBCR regs
  *    LCRR:  DLL bypass, Clock divider is 4
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
 #define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 #define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 #define CONFIG_CONSOLE		ttyS0
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 /*
  * PCI
  */
 #ifdef CONFIG_PCI
 #define CONFIG_MPC83XX_PCI2
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_MMIO_BASE	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M */
 #ifdef CONFIG_MPC83XX_PCI2
 #define CONFIG_SYS_PCI2_MEM_BASE	(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 #define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI2_MMIO_BASE	(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 #define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
 #define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS	(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 #define CONFIG_SYS_PCI2_IO_SIZE	0x01000000	/* 16M */
 #endif
 #define _IO_BASE		0x00000000	/* points to PCI I/O space */
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #ifdef CONFIG_RTL8139
 /* This macro is used by RTL8139 but not defined in PPC architecture */
 #define KSEG1ADDR(x)	    (x)
 #endif
 #ifndef CONFIG_PCI_PNP
     #define PCI_ENET0_IOADDR	0x00000000
     #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
     #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
 #endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif
 #define PCI_66M
 #ifdef PCI_66M
 #define CONFIG_83XX_CLKIN	66666666	/* in Hz */
 #else
 #define CONFIG_83XX_CLKIN	33333333	/* in Hz */
 #endif
 /* TSEC */
 #ifdef CONFIG_TSEC_ENET
 #define CONFIG_NET_MULTI
 #define CONFIG_MII
 #define CONFIG_PHY_GIGE		/* In case CONFIG_CMD_MII is specified */
 #define CONFIG_TSEC1
 #ifdef CONFIG_TSEC1
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME  "TSEC0"
 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
 #define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
 #define TSEC1_PHYIDX		0
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #endif
 #ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  "TSEC1"
 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
 #define TSEC2_PHY_ADDR		4
 #define TSEC2_PHYIDX		0
 #define TSEC2_FLAGS		TSEC_GIGABIT
 #endif
 #define CONFIG_ETHPRIME		"Freescale TSEC"
 #endif
 /*
  * Environment
  */
 #define CONFIG_ENV_OVERWRITE
 #ifndef CONFIG_SYS_RAMBOOT
   #define CONFIG_ENV_IS_IN_FLASH
   #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
   #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
   #define CONFIG_ENV_SIZE		0x2000
 #else
   #define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
   #undef  CONFIG_FLASH_CFI_DRIVER
   #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
   #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 #define CONFIG_LOADS_ECHO	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_SDRAM
 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114)
     #define CONFIG_DOS_PARTITION
     #define CONFIG_CMD_FAT
 #endif
 #ifdef CONFIG_COMPACT_FLASH
     #define CONFIG_CMD_IDE
 #endif
 #ifdef CONFIG_SATA_SIL3114
     #define CONFIG_CMD_SATA
     #define CONFIG_CMD_EXT2
 #endif
 #ifdef CONFIG_PCI
     #define CONFIG_CMD_PCI
 #endif
 #ifdef CONFIG_HARD_I2C
     #define CONFIG_CMD_I2C
 #endif
 /* Watchdog */
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_LOADADDR	500000	/* default location for tftp and bootm */
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_SYS_PROMPT	"MPC8349E-mITX> "	/* Monitor Command Prompt */
 #else
 #define CONFIG_SYS_PROMPT	"MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
 #endif
 #if defined(CONFIG_CMD_KGDB)
     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
     #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN_4X1 |\
 	HRCWL_VCO_1X2 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #ifdef CONFIG_SYS_LOWBOOT
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCI2_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCI2_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0XFFF00100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #endif
 /*
  * System performance
  */
 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 #define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
 #define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
 /*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH SICRH_TSOBI1	/* Needed for gigabit to work on TSEC 1 */
 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	CONFIG_SYS_HID0_INIT
 #define CONFIG_SYS_HID2	HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR  */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 /* PCI  */
 #ifdef CONFIG_PCI
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT1L	0
 #define CONFIG_SYS_IBAT1U	0
 #define CONFIG_SYS_IBAT2L	0
 #define CONFIG_SYS_IBAT2U	0
 #endif
 #ifdef CONFIG_MPC83XX_PCI2
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT3L	0
 #define CONFIG_SYS_IBAT3U	0
 #define CONFIG_SYS_IBAT4L	0
 #define CONFIG_SYS_IBAT4U	0
 #endif
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 				 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT7L	0
 #define CONFIG_SYS_IBAT7U	0
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02	/* Software reboot */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR		00:E0:0C:00:8C:01
 #endif
 #ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
 #endif
 #define CONFIG_IPADDR		192.168.1.253
 #define CONFIG_SERVERIP		192.168.1.1
 #define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.252.0
 #define CONFIG_NETDEV		eth0
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_HOSTNAME		mpc8349emitx
 #else
 #define CONFIG_HOSTNAME		mpc8349emitxgp
 #endif
 /* Default path and filenames */
 #define CONFIG_ROOTPATH		/nfsroot/rootfs
 #define CONFIG_BOOTFILE		uImage
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_FDTFILE		mpc8349emitx.dtb
 #else
 #define CONFIG_FDTFILE		mpc8349emitxgp.dtb
 #endif
 #define CONFIG_BOOTDELAY	0
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
 #define CONFIG_BOOTARGS \
 	"root=/dev/nfs rw" \
 	" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
 	" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":"	\
 		MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
 		MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
 	" console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"console=" MK_STR(CONFIG_CONSOLE) "\0"				\
 	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
 	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
 	"tftpflash=tftpboot $loadaddr $uboot; "				\
 		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
 		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
 		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
 	"fdtaddr=400000\0"						\
 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
 	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	" console=$console,$baudrate $othbootargs; "			\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"setenv bootargs root=/dev/ram rw"				\
 	" console=$console,$baudrate $othbootargs; "			\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #undef MK_STR
 #undef XMK_STR
 #endif

include/configs/MPC8360ERDK.h

Diff comments View file @ d48eb51

 /*
  * Copyright (C) 2006 Freescale Semiconductor, Inc.
  *                    Dave Liu <daveliu@freescale.com>
  *
  * Copyright (C) 2007 Logic Product Development, Inc.
  *                    Peter Barada <peterb@logicpd.com>
  *
  * Copyright (C) 2007 MontaVista Software, Inc.
  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_QE		1 /* Has QE */
 #define CONFIG_MPC83XX		1 /* MPC83XX family */
 #define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
 #define CONFIG_MPC8360ERDK	1 /* MPC8360ERDK board specific */
 /*
  * System Clock Setup
  */
 #ifdef CONFIG_CLKIN_33MHZ
 #define CONFIG_83XX_CLKIN		33333333
 #define CONFIG_SYS_CLK_FREQ		33333333
 #define PCI_33M				1
 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK	HRCWL_CSB_TO_CLKIN_10X1
 #else
 #define CONFIG_83XX_CLKIN		66000000
 #define CONFIG_SYS_CLK_FREQ		66000000
 #define PCI_66M				1
 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK	HRCWL_CSB_TO_CLKIN_5X1
 #endif /* CONFIG_CLKIN_33MHZ */
 /*
  * Hardware Reset Configuration Word
  */
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
 	HRCWL_CORE_TO_CSB_2X1 |\
 	HRCWL_CE_TO_PLL_1X15)
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCICKDRV_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_SECONDARY_DDR_DISABLE |\
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LALE_EARLY)
 /*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH		0x00000000
 #define CONFIG_SYS_SICRL		0x40000000
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 #define CONFIG_BOARD_EARLY_INIT_R
 /*
  * IMMR new address
  */
 #define CONFIG_SYS_IMMR		0xE0000000
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_DDR_ECC		/* support DDR ECC function */
 #define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
 /*
  * DDRCDR - DDR Control Driver Register
  */
 #define CONFIG_SYS_DDRCDR_VALUE	0x80080001
 #undef CONFIG_SPD_EEPROM	/* Do not use SPD EEPROM for DDR setup */
 /*
  * Manually set up DDR parameters
  */
 #define CONFIG_DDR_II
 #define CONFIG_SYS_DDR_SIZE		256 /* MB */
 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
 				 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000
 #define CONFIG_SYS_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #define CONFIG_SYS_DDR_INTERVAL	((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 				 (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
 #define CONFIG_SYS_DDR_MODE		0x47800432
 #define CONFIG_SYS_DDR_MODE2		0x8000c000
 #define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 				 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 				 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 				 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 				 (0 << TIMING_CFG0_WWT_SHIFT) | \
 				 (0 << TIMING_CFG0_RRT_SHIFT) | \
 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
 				 (0 << TIMING_CFG0_RWT_SHIFT))
 #define CONFIG_SYS_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_30) | \
 				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 				 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
 				 (10 << TIMING_CFG1_REFREC_SHIFT) | \
 				 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 				 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 				 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 #define CONFIG_SYS_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 				 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 				 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 				 (0 << TIMING_CFG2_CPO_SHIFT))
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 /*
  * Memory test
  */
 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START	0x00000000 /* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x00100000
 /*
  * The reserved memory
  */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
 #define CONFIG_SYS_FLASH_BASE		0xFF800000 /* FLASH base address */
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 /*
  * Initial RAM Base Address Setup
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 /*
  * Local Bus Configuration & Clock Setup
  */
 #define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
 #define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
 #define CONFIG_SYS_FLASH_PROTECTION	1 /* Use intel Flash protection. */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
 			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 			BR_V)	/* valid */
 #define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 /*
  * NAND flash on the local bus
  */
 #define CONFIG_SYS_NAND_BASE		0x60000000
 #define CONFIG_CMD_NAND		1
 #define CONFIG_NAND_FSL_UPM	1
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000001b /* Access window size 4K */
 /* Port size 8 bit, UPMA */
 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_NAND_BASE | 0x00000881)
 #define CONFIG_SYS_OR1_PRELIM		0xfc000001
 /*
  * Fujitsu MB86277 (MINT) graphics controller
  */
 #define CONFIG_SYS_VIDEO_BASE		0x70000000
 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VIDEO_BASE
 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019 /* Access window size 64MB */
 /* Port size 32 bit, UPMB */
 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
 #define CONFIG_SYS_OR2_PRELIM		0xfc000001 /* (64MB, EAD=1) */
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE	0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0x52}} /* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET	0x3000
 #define CONFIG_SYS_I2C2_OFFSET 0x3100
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI	1
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCI1_IO_BASE	0xE0300000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xE0300000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x100000 /* 1M */
 #ifdef CONFIG_PCI
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 #undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif	/* CONFIG_PCI */
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
 #endif
 /*
  * QE UEC ethernet configuration
  */
 #define CONFIG_UEC_ETH
 #define CONFIG_ETHPRIME		"FSL UEC0"
 #define CONFIG_UEC_ETH1		/* GETH1 */
 #ifdef CONFIG_UEC_ETH1
 #define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
 #define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	2
 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 #define CONFIG_UEC_ETH2		/* GETH2 */
 #ifdef CONFIG_UEC_ETH2
 #define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
 #define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
 #define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	4
 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 /*
  * Environment
  */
 #ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x20000
 #else /* CONFIG_SYS_RAMBOOT */
 #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
 #endif /* CONFIG_SYS_RAMBOOT */
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DHCP
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #endif
 #if defined(CONFIG_SYS_RAMBOOT)
 #undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_LOADS
 #endif
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 #else
 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 /*
  * Core HID Setup
  */
 #define CONFIG_SYS_HID0_INIT		0x000000000
 #define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
 #define CONFIG_SYS_HID2		HID2_HBE
 /*
  * MMU Setup
  */
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR: cache cacheable */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 /* NAND: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
 			 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 /* Stack in dcache: cacheable, no memory coherence */
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
 			 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
 			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else /* CONFIG_PCI */
 #define CONFIG_SYS_IBAT6L	(0)
 #define CONFIG_SYS_IBAT6U	(0)
 #define CONFIG_SYS_IBAT7L	(0)
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif /* CONFIG_PCI */
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02 /* Software reboot */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #if defined(CONFIG_UEC_ETH)
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
 #define CONFIG_HAS_ETH3
 #define CONFIG_ETHADDR	00:04:9f:ef:01:01
 #define CONFIG_ETH1ADDR	00:04:9f:ef:01:02
 #define CONFIG_ETH2ADDR	00:04:9f:ef:01:03
 #define CONFIG_ETH3ADDR	00:04:9f:ef:01:04
 #endif
 #define CONFIG_BAUDRATE 115200
 #define CONFIG_LOADADDR	a00000
 #define CONFIG_HOSTNAME	mpc8360erdk
 #define CONFIG_BOOTFILE	uImage
 #define CONFIG_IPADDR		10.0.0.99
 #define CONFIG_SERVERIP		10.0.0.2
 #define CONFIG_GATEWAYIP	10.0.0.2
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_ROOTPATH		/nfsroot/
 #define	CONFIG_BOOTDELAY 2	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 #define CONFIG_EXTRA_ENV_SETTINGS \
    "netdev=eth0\0"\
    "consoledev=ttyS0\0"\
    "loadaddr=a00000\0"\
    "fdtaddr=900000\0"\
    "fdtfile=dtb\0"\
    "fsfile=fs\0"\
    "ubootfile=u-boot.bin\0"\
    "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
    "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
 		"$mtdparts panic=1\0"\
    "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
    "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
 		"$gatewayip:$netmask:$hostname:$netdev:off "\
 		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
    "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
 		"rootfstype=jffs2 rw\0"\
    "tftp_get_uboot=tftp 100000 $ubootfile\0"\
    "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
    "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
    "tftp_get_fs=tftp c00000 $fsfile\0"\
    "nand_erase_kernel=nand erase 0 400000\0"\
    "nand_erase_dtb=nand erase 400000 20000\0"\
    "nand_erase_fs=nand erase 420000 3be0000\0"\
    "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
    "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
    "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
    "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
    "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
    "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
 		"cp.b 100000 ff800000 $filesize\0"\
    "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
 		"nand_write_kernel\0"\
    "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
    "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
    "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
 		"nand_reflash_fs\0"\
    "boot_m=bootm $loadaddr - $fdtaddr\0"\
    "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
    "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
 		"boot_m\0"\
    "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
 		"boot_m\0"\
    ""
 #define CONFIG_BOOTCOMMAND "run dhcpboot"
 #endif /* __CONFIG_H */

include/configs/MPC8536DS.h

Diff comments View file @ d48eb51

 /*
  * Copyright 2008 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * mpc8536ds board configuration file
  *
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8536		1
 #define CONFIG_MPC8536DS	1
 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* Enable PCI controller 1 */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
  * This allows booting from a promjet.
  */
 #define CONFIG_ASSUME_AMD_FLASH
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0)
 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
 #define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
 					     from ICS307 instead of switches */
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x7fffffff
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
 #define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
 #define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR+0xb000)
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 #define CONFIG_SYS_SPD_BUS_NUM		1
 /* These are used when DDR doesn't use SPD. */
 #define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
 #define CONFIG_SYS_DDR_TIMING_1	0x3935d322
 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
 #define CONFIG_SYS_DDR_MODE_1		0x00480432
 #define CONFIG_SYS_DDR_MODE_2		0x00000000
 #define CONFIG_SYS_DDR_INTERVAL	0x06180100
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
 #define CONFIG_SYS_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
 #define CONFIG_SYS_DDR_CONTROL2	0x04400010
 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
 #define CONFIG_SYS_DDR_SBE		0x00010000
 /* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif
 #undef CONFIG_CLOCKS_IN_MHZ
 /*
  * Memory map -- xxx -this is wrong, needs updating
  *
  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
  *
  * Localbus cacheable (TBD)
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
  * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
  * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 /*
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
 #define PIXIS_BASE_PHYS	PIXIS_BASE
 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
 #define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
 #define PIXIS_PWR		0x5	/* PIXIS Power status register */
 #define PIXIS_AUX		0x6	/* Auxiliary 1 register */
 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
 #define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
 #define PIXIS_VCTL		0x10	/* VELA Control Register */
 #define PIXIS_VSTAT		0x11	/* VELA Status Register */
 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
 #define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
 #define PIXIS_VSYSCLK0		0x1A	/* VELA SYSCLK0 Register */
 #define PIXIS_VSYSCLK1		0x1B	/* VELA SYSCLK1 Register */
 #define PIXIS_VSYSCLK2		0x1C	/* VELA SYSCLK2 Register */
 #define PIXIS_VDDRCLK0		0x1D	/* VELA DDRCLK0 Register */
 #define PIXIS_VDDRCLK1		0x1E	/* VELA DDRCLK1 Register */
 #define PIXIS_VDDRCLK2		0x1F	/* VELA DDRCLK2 Register */
 #define PIXIS_VWATCH		0x24    /* Watchdog Register */
 #define PIXIS_LED		0x25    /* LED Register */
 /* old pixis referenced names */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 #define CONFIG_SYS_NAND_BASE           0xffa00000
 #define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 				CONFIG_SYS_NAND_BASE + 0x40000, \
 				CONFIG_SYS_NAND_BASE + 0x80000, \
 				CONFIG_SYS_NAND_BASE + 0xC0000}
 #define CONFIG_SYS_MAX_NAND_DEVICE	4
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND		1
 #define CONFIG_NAND_FSL_ELBC	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 /* NAND flash config */
 #define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 				| BR_PS_8              /* Port Size = 8 bit */ \
 				| BR_MS_FCM             /* MSEL = FCM */ \
 				| BR_V)                 /* valid */
 #define CONFIG_NAND_OR_PRELIM	(0xFFFC0000            /* length 256K */ \
 				| OR_FCM_PGS            /* Large Page*/ \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
 				| OR_FCM_SCY_1 \
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR)
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
 				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 				| BR_PS_8              /* Port Size = 8 bit */ \
 				| BR_MS_FCM             /* MSEL = FCM */ \
 				| BR_V)                 /* valid */
 #define CONFIG_SYS_OR4_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
 				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 				| BR_PS_8              /* Port Size = 8 bit */ \
 				| BR_MS_FCM             /* MSEL = FCM */ \
 				| BR_V)                 /* valid */
 #define CONFIG_SYS_OR5_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
 				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 				| BR_PS_8              /* Port Size = 8 bit */ \
 				| BR_MS_FCM             /* MSEL = FCM */ \
 				| BR_V)                 /* valid */
 #define CONFIG_SYS_OR6_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 /*
  * Pass open firmware flat tree
  */
 #define CONFIG_OF_LIBFDT		1
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 #define CONFIG_SYS_64BIT_STRTOUL		1
 #define CONFIG_SYS_64BIT_VSPRINTF		1
 /*
  * I2C
  */
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0, 0x29}}	/* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 /*
  * I2C2 EEPROM
  */
 #define CONFIG_ID_EEPROM
 #ifdef CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #endif
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_BUS_NUM	1
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_IO_VIRT	0xffc00000
 #define CONFIG_SYS_PCI1_IO_BUS	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xffc00000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x08000000	/* 128M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc10000
 #define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc10000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x98000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0x98000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0x98000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x08000000	/* 128M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
 #define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc30000
 #define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc30000
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 #if defined(CONFIG_PCI)
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 /*PCIE video card used*/
 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE3_IO_VIRT
 /*PCI video card used*/
 /*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
 /* video */
 #define CONFIG_VIDEO
 #if defined(CONFIG_VIDEO)
 #define CONFIG_BIOSEMU
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 #endif
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 #undef CONFIG_RTL8139
 #ifdef CONFIG_RTL8139
 /* This macro is used by RTL8139 but not defined in PPC architecture */
 #define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 #define _IO_BASE	0x00000000
 #endif
 #ifndef CONFIG_PCI_PNP
 	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
 	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
 #endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_EXT2
 #endif
 #if defined(CONFIG_TSEC_ENET)
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
 #endif
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC3"
 #define CONFIG_FSL_SGMII_RISER	1
 #define SGMII_RISER_PHY_OFFSET	0x1c
 #define TSEC1_PHY_ADDR		1	/* TSEC1 -> PHY1 */
 #define TSEC3_PHY_ADDR		0	/* TSEC3 -> PHY0 */
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define CONFIG_ETHPRIME		"eTSEC1"
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #endif	/* CONFIG_TSEC_ENET */
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR		0xfff80000
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_BEDBUG
 #define CONFIG_CMD_NET
 #endif
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 #define CONFIG_MMC     1
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR	00:E0:0C:02:00:FD
 #define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
 #define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
 #define CONFIG_HAS_ETH3
 #define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
 #endif
 #define CONFIG_IPADDR		192.168.1.254
 #define CONFIG_HOSTNAME		unknown
 #define CONFIG_ROOTPATH		/opt/nfsroot
 #define CONFIG_BOOTFILE		uImage
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 #define CONFIG_SERVERIP		192.168.1.1
 #define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.255.0
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 #define CONFIG_BAUDRATE	115200
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
  "netdev=eth0\0"						\
  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
  "tftpflash=tftpboot $loadaddr $uboot; "			\
 	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
 	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
 	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
 	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
 	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
  "consoledev=ttyS0\0"				\
  "ramdiskaddr=2000000\0"			\
  "ramdiskfile=8536ds/ramdisk.uboot\0"		\
  "fdtaddr=c00000\0"				\
  "fdtfile=8536ds/mpc8536ds.dtb\0"		\
  "bdev=sda3\0"
 #define CONFIG_HDBOOT				\
  "setenv bootargs root=/dev/$bdev rw "		\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "tftp $loadaddr $bootfile;"			\
  "tftp $fdtaddr $fdtfile;"			\
  "bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND		\
  "setenv bootargs root=/dev/nfs rw "	\
  "nfsroot=$serverip:$rootpath "		\
  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  "console=$consoledev,$baudrate $othbootargs;"	\
  "tftp $loadaddr $bootfile;"		\
  "tftp $fdtaddr $fdtfile;"		\
  "bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND		\
  "setenv bootargs root=/dev/ram rw "	\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "tftp $ramdiskaddr $ramdiskfile;"	\
  "tftp $loadaddr $bootfile;"		\
  "tftp $fdtaddr $fdtfile;"		\
  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 #endif	/* __CONFIG_H */

include/configs/MPC8568MDS.h

Diff comments View file @ d48eb51

 /*
  * Copyright 2004-2007 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * mpc8568mds board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
 #define CONFIG_MPC8568		1	/* MPC8568 specific */
 #define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* PCI controller */
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the MDS board.
  * This allows booting from a promjet.
  */
 #define CONFIG_ASSUME_AMD_FLASH
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
 #define CONFIG_SYS_CLK_FREQ	66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
 #define CONFIG_BTB				/* toggle branch predition */
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 /* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif
 #undef CONFIG_CLOCKS_IN_MHZ
 /*
  * Local Bus Definitions
  */
 /*
  * FLASH on the Local Bus
  * Two banks, 8M each, using the CFI driver.
  * Boot from BR0/OR0 bank at 0xff00_0000
  * Alternate BR1/OR1 bank at 0xff80_0000
  *
  * BR0, BR1:
  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  *    Port Size = 16 bits = BRx[19:20] = 10
  *    Use GPCM = BRx[24:26] = 000
  *    Valid = BRx[31] = 1
  *
  * 0    4    8    12   16   20   24   28
  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
  *
  * OR0, OR1:
  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  *    Reserved ORx[17:18] = 11, confusion here?
  *    CSNT = ORx[20] = 1
  *    ACS = half cycle delay = ORx[21:22] = 11
  *    SCY = 6 = ORx[24:27] = 0110
  *    TRLX = use relaxed timing = ORx[29] = 1
  *    EAD = use external address latch delay = OR[31] = 1
  *
  * 0    4    8    12   16   20   24   28
  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
  */
 #define CONFIG_SYS_BCSR_BASE		0xf8000000
 #define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
 /*Chip select 0 - Flash*/
 #define CONFIG_SYS_BR0_PRELIM		0xfe001001
 #define	CONFIG_SYS_OR0_PRELIM		0xfe006ff7
 /*Chip slelect 1 - BCSR*/
 #define CONFIG_SYS_BR1_PRELIM		0xf8000801
 #define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
 /*#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE} */
 #define CONFIG_SYS_MAX_FLASH_BANKS		1		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT		512		/* sectors per device */
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 /*
  * SDRAM on the LocalBus
  */
 #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
 #define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */
 /*Chip select 2 - SDRAM*/
 #define CONFIG_SYS_BR2_PRELIM      0xf0001861
 #define CONFIG_SYS_OR2_PRELIM		0xfc006901
 #define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
 #define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
 #define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
 #define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
 				| LSDMR_PRETOACT7	\
 				| LSDMR_ACTTORW7	\
 				| LSDMR_BL8		\
 				| LSDMR_WRC4		\
 				| LSDMR_CL3		\
 				| LSDMR_RFEN		\
 				)
 /*
  * The bcsr registers are connected to CS3 on MDS.
  * The new memory map places bcsr at 0xf8000000.
  *
  * For BR3, need:
  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  *    port-size = 8-bits  = BR[19:20] = 01
  *    no parity checking  = BR[21:22] = 00
  *    GPMC for MSEL       = BR[24:26] = 000
  *    Valid               = BR[31]    = 1
  *
  * 0    4    8    12   16   20   24   28
  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  *
  * For OR3, need:
  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
  *    disable buffer ctrl OR[19]    = 0
  *    CSNT                OR[20]    = 1
  *    ACS                 OR[21:22] = 11
  *    XACS                OR[23]    = 1
  *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
  *    SETA                OR[28]    = 0
  *    TRLX                OR[29]    = 1
  *    EHTR                OR[30]    = 1
  *    EAD extra time      OR[31]    = 1
  *
  * 0    4    8    12   16   20   24   28
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 #define CONFIG_SYS_BCSR (0xf8000000)
 /*Chip slelect 4 - PIB*/
 #define CONFIG_SYS_BR4_PRELIM   0xf8008801
 #define CONFIG_SYS_OR4_PRELIM   0xffffe9f7
 /*Chip select 5 - PIB*/
 #define CONFIG_SYS_BR5_PRELIM	 0xf8010801
 #define CONFIG_SYS_OR5_PRELIM	 0xffff69f7
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_SIZE	128	    /* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 /* Serial Port */
 #define CONFIG_CONS_INDEX		1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 /* Use the HUSH parser*/
 #define CONFIG_SYS_HUSH_PARSER
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT		1
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 #define CONFIG_SYS_64BIT_VSPRINTF	1
 #define CONFIG_SYS_64BIT_STRTOUL	1
 /*
  * I2C
  */
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES        {{0,0x69}}	/* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 /*
  * General PCI
  * Memory Addresses are mapped 1-1. I/O is mapped from 0
  */
 #define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
 #define CONFIG_SYS_PCI1_IO_BUS	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
 #define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 #define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
 #define CONFIG_SYS_SRIO_MEM_BUS	0xc0000000
 #define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
 #ifdef CONFIG_QE
 /*
  * QE UEC ethernet configuration
  */
 #define CONFIG_UEC_ETH
 #ifndef CONFIG_TSEC_ENET
 #define CONFIG_ETHPRIME         "FSL UEC0"
 #endif
 #define CONFIG_PHY_MODE_NEED_CHANGE
 #define CONFIG_eTSEC_MDIO_BUS
 #ifdef CONFIG_eTSEC_MDIO_BUS
 #define CONFIG_MIIM_ADDRESS	0xE0024520
 #endif
 #define CONFIG_UEC_ETH1         /* GETH1 */
 #ifdef CONFIG_UEC_ETH1
 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 #define CONFIG_UEC_ETH2         /* GETH2 */
 #ifdef CONFIG_UEC_ETH2
 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 #endif /* CONFIG_QE */
 #if defined(CONFIG_PCI)
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 #endif	/* CONFIG_PCI */
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
 #endif
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"eTSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"eTSEC1"
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		3
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC2_FLAGS		TSEC_GIGABIT
 /* Options are: eTSEC[0-1] */
 #define CONFIG_ETHPRIME		"eTSEC0"
 #endif	/* CONFIG_TSEC_ENET */
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
 #endif
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
 #define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
 #define CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 #define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 #define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 #define CONFIG_HAS_ETH3
 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 #endif
 #define CONFIG_IPADDR    192.168.1.253
 #define CONFIG_HOSTNAME  unknown
 #define CONFIG_ROOTPATH  /nfsroot
 #define CONFIG_BOOTFILE  your.uImage
 #define CONFIG_SERVERIP  192.168.1.1
 #define CONFIG_GATEWAYIP 192.168.1.1
 #define CONFIG_NETMASK   255.255.255.0
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 #define CONFIG_BAUDRATE	115200
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS0\0"                                                 \
    "ramdiskaddr=600000\0"                                               \
    "ramdiskfile=your.ramdisk.u-boot\0"					\
    "fdtaddr=400000\0"							\
    "fdtfile=your.fdt.dtb\0"						\
    "nfsargs=setenv bootargs root=/dev/nfs rw "				\
       "nfsroot=$serverip:$rootpath "					\
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs\0"			\
    "ramargs=setenv bootargs root=/dev/ram rw "				\
       "console=$consoledev,$baudrate $othbootargs\0"			\
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "run nfsargs;"							\
    "tftp $loadaddr $bootfile;"                                          \
    "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND \
    "run ramargs;"							\
    "tftp $ramdiskaddr $ramdiskfile;"                                    \
    "tftp $loadaddr $bootfile;"                                          \
    "bootm $loadaddr $ramdiskaddr"
 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 #endif	/* __CONFIG_H */

include/configs/MPC8569MDS.h

Diff comments View file @ d48eb51

 /*
  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * mpc8569mds board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
 #define CONFIG_MPC8569		1	/* MPC8569 specific */
 #define CONFIG_MPC8569MDS	1	/* MPC8569MDS board specific */
 #define CONFIG_FSL_ELBC		1	/* Has Enhance localbus controller */
 #define CONFIG_PCI		1	/* Disable PCI/PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the MDS board.
  * This allows booting from a promjet.
  */
 #define CONFIG_ASSUME_AMD_FLASH
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif
 /* Replace a call to get_clock_freq (after it is implemented)*/
 #define CONFIG_SYS_CLK_FREQ	66666666
 #define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
 #define CONFIG_BTB				/* toggle branch predition */
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
 						/* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
 						/* PQII uses CONFIG_SYS_IMMR */
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 /* DDR Setup */
 #define CONFIG_FSL_DDR3
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 					/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
 #define SPD_EEPROM_ADDRESS2    0x52    /* CTLR 1 DIMM 0 */
 /* These are used when DDR doesn't use SPD.  */
 #define CONFIG_SYS_SDRAM_SIZE           1024		/* DDR is 1024MB */
 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 #define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
 #define CONFIG_SYS_DDR_TIMING_2         0x002888D0
 #define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
 #define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
 #define CONFIG_SYS_DDR_SDRAM_MODE	0x40401521
 #define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
 #define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x03E00000
 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x01000000
 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 #define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
 #define CONFIG_SYS_DDR_WRLVL_CNTL	0x0655A604
 #define CONFIG_SYS_DDR_CDR_1		0x80040000
 #define CONFIG_SYS_DDR_CDR_2		0x00000000
 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 #define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 #define CONFIG_SYS_DDR_SBE              0x00010000
 #undef CONFIG_CLOCKS_IN_MHZ
 /*
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BCSR_BASE		0xf8000000
 #define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
 /*Chip select 0 - Flash*/
 #define CONFIG_SYS_BR0_PRELIM		0xfe000801
 #define	CONFIG_SYS_OR0_PRELIM		0xfe000ff7
 /*Chip select 1 - BCSR*/
 #define CONFIG_SYS_BR1_PRELIM		0xf8000801
 #define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
 /*Chip select 4 - PIB*/
 #define CONFIG_SYS_BR4_PRELIM		0xf8008801
 #define CONFIG_SYS_OR4_PRELIM		0xffffe9f7
 /*Chip select 5 - PIB*/
 #define CONFIG_SYS_BR5_PRELIM		0xf8010801
 #define CONFIG_SYS_OR5_PRELIM		0xffffe9f7
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 /*
  * SDRAM on the LocalBus
  */
 #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
 #define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 #define CONFIG_SYS_LBC_LCRR	0x00000004	/* LB clock ratio reg */
 #define CONFIG_SYS_LBC_LBCR	0x00040000	/* LB config reg */
 #define CONFIG_SYS_LBC_LSRT	0x20000000	/* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR	0x00000000	/* LB refresh timer prescal*/
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 			(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
 /* Serial Port */
 #define CONFIG_CONS_INDEX		1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 /* Use the HUSH parser*/
 #define CONFIG_SYS_HUSH_PARSER
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT		1
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 #define CONFIG_SYS_64BIT_VSPRINTF	1
 #define CONFIG_SYS_64BIT_STRTOUL	1
 /*
  * I2C
  */
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE	0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET	0x3000
 #define CONFIG_SYS_I2C2_OFFSET	0x3100
 /*
  * I2C2 EEPROM
  */
 #define CONFIG_ID_EEPROM
 #ifdef CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #endif
 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 #define PLPPAR1_I2C_BIT_MASK		0x0000000F
 #define PLPPAR1_I2C2_VAL		0x00000000
 #define PLPDIR1_I2C_BIT_MASK		0x0000000F
 #define PLPDIR1_I2C2_VAL		0x0000000F
 /*
  * General PCI
  * Memory Addresses are mapped 1-1. I/O is mapped from 0
  */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 #define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
 #define CONFIG_SYS_SRIO_MEM_BUS		0xc0000000
 #define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
 #ifdef CONFIG_QE
 /*
  * QE UEC ethernet configuration
  */
 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
 #define CONFIG_UEC_ETH
 #define CONFIG_ETHPRIME         "FSL UEC0"
 #define CONFIG_PHY_MODE_NEED_CHANGE
 #define CONFIG_UEC_ETH1         /* GETH1 */
 #define CONFIG_HAS_ETH0
 #ifdef CONFIG_UEC_ETH1
 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 #define CONFIG_UEC_ETH2         /* GETH2 */
 #define CONFIG_HAS_ETH1
 #ifdef CONFIG_UEC_ETH2
 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 #endif /* CONFIG_QE */
 #if defined(CONFIG_PCI)
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
 #endif
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /* QE microcode/firmware address */
 #define CONFIG_SYS_QE_FW_ADDR	0xfff00000
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
 #endif
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
 #else
 #define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 						/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	32		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 						/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ	1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)
 					/* Initial Memory map for Linux*/
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_HOSTNAME mpc8569mds
 #define CONFIG_ROOTPATH  /nfsroot
 #define CONFIG_BOOTFILE  your.uImage
 #define CONFIG_SERVERIP  192.168.1.1
 #define CONFIG_GATEWAYIP 192.168.1.1
 #define CONFIG_NETMASK   255.255.255.0
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 #define CONFIG_BAUDRATE	115200
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"consoledev=ttyS0\0"						\
 	"ramdiskaddr=600000\0"						\
 	"ramdiskfile=your.ramdisk.u-boot\0"				\
 	"fdtaddr=400000\0"						\
 	"fdtfile=your.fdt.dtb\0"					\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 	"nfsroot=$serverip:$rootpath "					\
 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 	"console=$consoledev,$baudrate $othbootargs\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw "			\
 	"console=$consoledev,$baudrate $othbootargs\0"			\
 #define CONFIG_NFSBOOTCOMMAND						\
 	"run nfsargs;"							\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"run ramargs;"							\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"bootm $loadaddr $ramdiskaddr"
 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 #endif	/* __CONFIG_H */

include/configs/MPC8572DS.h

Diff comments View file @ d48eb51

 /*
  * Copyright 2007-2008 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * mpc8572ds board configuration file
  *
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8572		1
 #define CONFIG_MPC8572DS	1
 #define CONFIG_MP		1	/* support multiple processors */
 #define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
  * This allows booting from a promjet.
  */
 #define CONFIG_ASSUME_AMD_FLASH
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
 #define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
 					     from ICS307 instead of switches */
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ADDR_MAP			1
 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
 #endif
 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x7fffffff
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_CCSRBAR_PHYS		0xfffe00000ull	/* physical addr of CCSRBAR */
 #else
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
 #endif
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 #define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
 /* DDR Setup */
 #define CONFIG_SYS_DDR_TLB_START 9
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 /* I2C addresses of SPD EEPROMs */
 #define CONFIG_SYS_SPD_BUS_NUM		1	/* SPD EEPROMS locate on I2C bus 1 */
 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
 /* These are used when DDR doesn't use SPD.  */
 #define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
 #define CONFIG_SYS_DDR_TIMING_3		0x00020000
 #define CONFIG_SYS_DDR_TIMING_0		0x00260802
 #define CONFIG_SYS_DDR_TIMING_1		0x626b2634
 #define CONFIG_SYS_DDR_TIMING_2		0x062874cf
 #define CONFIG_SYS_DDR_MODE_1		0x00440462
 #define CONFIG_SYS_DDR_MODE_2		0x00000000
 #define CONFIG_SYS_DDR_INTERVAL		0x0c300100
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
 #define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
 #define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
 #define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
 #define CONFIG_SYS_DDR_CONTROL2		0x24400000
 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
 #define CONFIG_SYS_DDR_SBE		0x00010000
 /*
  * Make sure required options are set
  */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif
 #undef CONFIG_CLOCKS_IN_MHZ
 /*
  * Memory map
  *
  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
  *
  * Localbus cacheable (TBD)
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
  * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
  * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 /*
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
 #else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 #define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS	0xfffdf0000ull
 #else
 #define PIXIS_BASE_PHYS	PIXIS_BASE
 #endif
 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
 #define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
 #define PIXIS_PWR		0x5	/* PIXIS Power status register */
 #define PIXIS_AUX		0x6	/* Auxiliary 1 register */
 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
 #define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
 #define PIXIS_VCTL		0x10	/* VELA Control Register */
 #define PIXIS_VSTAT		0x11	/* VELA Status Register */
 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
 #define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
 #define PIXIS_VSYSCLK0		0x1C	/* VELA SYSCLK0 Register */
 #define PIXIS_VSYSCLK1		0x1D	/* VELA SYSCLK1 Register */
 #define PIXIS_VSYSCLK2		0x1E	/* VELA SYSCLK2 Register */
 #define PIXIS_VDDRCLK0		0x1F	/* VELA DDRCLK0 Register */
 #define PIXIS_VDDRCLK1		0x20	/* VELA DDRCLK1 Register */
 #define PIXIS_VDDRCLK2		0x21	/* VELA DDRCLK2 Register */
 #define PIXIS_VWATCH		0x24    /* Watchdog Register */
 #define PIXIS_LED		0x25    /* LED Register */
 /* old pixis referenced names */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
 #define PIXIS_VSPEED2_TSEC1SER	0x8
 #define PIXIS_VSPEED2_TSEC2SER	0x4
 #define PIXIS_VSPEED2_TSEC3SER	0x2
 #define PIXIS_VSPEED2_TSEC4SER	0x1
 #define PIXIS_VCFGEN1_TSEC1SER	0x20
 #define PIXIS_VCFGEN1_TSEC2SER	0x20
 #define PIXIS_VCFGEN1_TSEC3SER	0x20
 #define PIXIS_VCFGEN1_TSEC4SER	0x20
 #define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
 					| PIXIS_VSPEED2_TSEC2SER \
 					| PIXIS_VSPEED2_TSEC3SER \
 					| PIXIS_VSPEED2_TSEC4SER)
 #define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
 					| PIXIS_VCFGEN1_TSEC2SER \
 					| PIXIS_VCFGEN1_TSEC3SER \
 					| PIXIS_VCFGEN1_TSEC4SER)
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 #define CONFIG_SYS_NAND_BASE		0xffa00000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 				CONFIG_SYS_NAND_BASE + 0x40000, \
 				CONFIG_SYS_NAND_BASE + 0x80000,\
 				CONFIG_SYS_NAND_BASE + 0xC0000}
 #define CONFIG_SYS_MAX_NAND_DEVICE    4
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND		1
 #define CONFIG_NAND_FSL_ELBC	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 /* NAND flash config */
 #define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
 #define CONFIG_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
 			       | OR_FCM_PGS	       /* Large Page*/ \
 			       | OR_FCM_CSCT \
 			       | OR_FCM_CST \
 			       | OR_FCM_CHT \
 			       | OR_FCM_SCY_1 \
 			       | OR_FCM_TRLX \
 			       | OR_FCM_EHTR)
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
 #define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM	 /* NAND Options */
 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
 #define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM	 /* NAND Options */
 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
 #define CONFIG_SYS_OR6_PRELIM  CONFIG_NAND_OR_PRELIM	 /* NAND Options */
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 /*
  * Pass open firmware flat tree
  */
 #define CONFIG_OF_LIBFDT		1
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 #define CONFIG_SYS_64BIT_VSPRINTF	1
 #define CONFIG_SYS_64BIT_STRTOUL	1
 /* new uImage format support */
 #define CONFIG_FIT		1
 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
 /* I2C */
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x29}}/* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 /*
  * I2C2 EEPROM
  */
 #define CONFIG_ID_EEPROM
 #ifdef CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #endif
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_SYS_EEPROM_BUS_NUM	1
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
 #endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
 #define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
 #else
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
 #define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
 #endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
 #define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 #if defined(CONFIG_PCI)
 /*PCIE video card used*/
 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
 /* video */
 #define CONFIG_VIDEO
 #if defined(CONFIG_VIDEO)
 #define CONFIG_BIOSEMU
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 #endif
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 #undef CONFIG_RTL8139
 #ifdef CONFIG_RTL8139
 /* This macro is used by RTL8139 but not defined in PPC architecture */
 #define KSEG1ADDR(x)		(x)
 #define _IO_BASE	0x00000000
 #endif
 #ifndef CONFIG_PCI_PNP
 	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCIE3_IO_BUS
 	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCIE3_IO_BUS
 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
 #endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SCSI_AHCI
 #ifdef CONFIG_SCSI_AHCI
 #define CONFIG_SATA_ULI5288
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
 #define CONFIG_SYS_SCSI_MAX_LUN	1
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
 #endif /* SCSI */
 #endif	/* CONFIG_PCI */
 #if defined(CONFIG_TSEC_ENET)
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
 #endif
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"eTSEC2"
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC3"
 #define CONFIG_TSEC4	1
 #define CONFIG_TSEC4_NAME	"eTSEC4"
 #define CONFIG_PIXIS_SGMII_CMD
 #define CONFIG_FSL_SGMII_RISER	1
 #define SGMII_RISER_PHY_OFFSET	0x1c
 #ifdef CONFIG_FSL_SGMII_RISER
 #define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
 #endif
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC3_PHY_ADDR		2
 #define TSEC4_PHY_ADDR		3
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define TSEC4_PHYIDX		0
 #define CONFIG_ETHPRIME		"eTSEC1"
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #endif	/* CONFIG_TSEC_ENET */
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR		0xfff80000
 #else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_BEDBUG
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_SCSI
 #define CONFIG_CMD_EXT2
 #endif
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR	00:E0:0C:02:00:FD
 #define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
 #define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
 #define CONFIG_HAS_ETH3
 #define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
 #endif
 #define CONFIG_IPADDR		192.168.1.254
 #define CONFIG_HOSTNAME		unknown
 #define CONFIG_ROOTPATH		/opt/nfsroot
 #define CONFIG_BOOTFILE		uImage
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 #define CONFIG_SERVERIP		192.168.1.1
 #define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.255.0
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 #define CONFIG_BAUDRATE	115200
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
  "memctl_intlv_ctl=2\0"						\
  "netdev=eth0\0"						\
  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
  "tftpflash=tftpboot $loadaddr $uboot; "			\
 	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
 	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
 	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
 	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
 	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
  "consoledev=ttyS0\0"				\
  "ramdiskaddr=2000000\0"			\
  "ramdiskfile=8572ds/ramdisk.uboot\0"		\
  "fdtaddr=c00000\0"				\
  "fdtfile=8572ds/mpc8572ds.dtb\0"		\
  "bdev=sda3\0"
 #define CONFIG_HDBOOT				\
  "setenv bootargs root=/dev/$bdev rw "		\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "tftp $loadaddr $bootfile;"			\
  "tftp $fdtaddr $fdtfile;"			\
  "bootm $loadaddr - $fdtaddr"
 #define CONFIG_NFSBOOTCOMMAND		\
  "setenv bootargs root=/dev/nfs rw "	\
  "nfsroot=$serverip:$rootpath "		\
  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  "console=$consoledev,$baudrate $othbootargs;"	\
  "tftp $loadaddr $bootfile;"		\
  "tftp $fdtaddr $fdtfile;"		\
  "bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND		\
  "setenv bootargs root=/dev/ram rw "	\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "tftp $ramdiskaddr $ramdiskfile;"	\
  "tftp $loadaddr $bootfile;"		\
  "tftp $fdtaddr $fdtfile;"		\
  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 #endif	/* __CONFIG_H */

include/configs/MVBLM7.h

Diff comments View file @ d48eb51

 /*
  * Copyright (C) Matrix Vision GmbH 2008
  *
  * Matrix Vision mvBlueLYNX-M7 configuration file
  * based on Freescale's MPC8349ITX.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <version.h>
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300	1
 #define CONFIG_MPC83XX	1
 #define CONFIG_MPC834X	1
 #define CONFIG_MPC8343	1
 #define CONFIG_SYS_IMMR		0xE0000000
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI
 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 #define CONFIG_HARD_I2C
 #define CONFIG_TSEC_ENET
 #define CONFIG_MPC8XXX_SPI
 #define CONFIG_HARD_SPI
 #define MVBLM7_MMC_CS   0x04000000
 /* I2C */
 #undef CONFIG_SOFT_I2C
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_83XX_DDR_USES_CS0	1
 #define CONFIG_SYS_MEMTEST_START	(60<<20)
 #define CONFIG_SYS_MEMTEST_END		(70<<20)
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDR_SIZE		256
 /* HC, 75Ohm, DDR-II, DRQ */
 #define CONFIG_SYS_DDRCDR		0x80000001
 /* EN, ODT_WR, 3BA, 14row, 10col */
 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014102
 #define CONFIG_SYS_DDR_CS1_CONFIG	0x0
 #define CONFIG_SYS_DDR_CS2_CONFIG	0x0
 #define CONFIG_SYS_DDR_CS3_CONFIG	0x0
 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
 #define CONFIG_SYS_DDR_CS1_BNDS	0x0
 #define CONFIG_SYS_DDR_CS2_BNDS	0x0
 #define CONFIG_SYS_DDR_CS3_BNDS	0x0
 #define CONFIG_SYS_DDR_CLK_CNTL	0x02000000
 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
 #define CONFIG_SYS_DDR_TIMING_1	0x2625b221
 #define CONFIG_SYS_DDR_TIMING_2	0x1f9820c7
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 /* ~MEM_EN, SREN, DDR-II, 32_BE */
 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43080000
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #define CONFIG_SYS_DDR_INTERVAL	0x04060100
 #define CONFIG_SYS_DDR_MODE		0x078e0232
 /* Flash */
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_FLASH_BASE		0xFF800000
 #define CONFIG_SYS_FLASH_SIZE		8
 #define CONFIG_SYS_FLASH_SIZE_SHIFT	3
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	256
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM |  \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
 				OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 				OR_GPCM_EAD)
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
 /*
  * U-Boot memory configuration
  */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 #undef	CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 #define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
 /*
  * Local Bus LCRR and LBCR regs
  *  LCRR:  DLL bypass, Clock divider is 4
  * External Local Bus rate is
  *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
 #define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_LSRT	0x32000000
 /* LB refresh timer prescal, 266MHz/32*/
 #define CONFIG_SYS_LBC_MRTPR	0x20000000
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 #define CONFIG_CONSOLE		ttyS0
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT		1
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 #define MV_DTB_NAME	"mvblm7.dtb"
 /*
  * PCI
  */
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000
 #define CONFIG_SYS_PCI1_MMIO_BASE	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x01000000
 #define _IO_BASE		0x00000000
 #define CONFIG_NET_MULTI	1
 #define CONFIG_NET_RETRY_COUNT	3
 #define PCI_66M
 #define CONFIG_83XX_CLKIN	66666667
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
 /* TSEC */
 #define CONFIG_GMII
 #define CONFIG_SYS_VSC8601_SKEWFIX
 #define	CONFIG_SYS_VSC8601_SKEW_TX	3
 #define	CONFIG_SYS_VSC8601_SKEW_RX	3
 #define CONFIG_TSEC1
 #define CONFIG_TSEC2
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_FEC1_PHY_NORXERR
 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
 #define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 #define TSEC1_PHY_ADDR		0x10
 #define TSEC1_PHYIDX		0
 #define TSEC1_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  	"TSEC1"
 #define CONFIG_FEC2_PHY_NORXERR
 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
 #define CONFIG_SYS_TSEC2 		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 #define TSEC2_PHY_ADDR		0x11
 #define TSEC2_PHYIDX		0
 #define TSEC2_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
 #define CONFIG_ETHPRIME		"TSEC0"
 #define CONFIG_BOOTP_VENDOREX
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_NTPSERVER
 #define CONFIG_BOOTP_RANDOM_DELAY
 #define CONFIG_BOOTP_SEND_HOSTNAME
 /* USB */
 #define CONFIG_HAS_FSL_DR_USB
 /*
  * Environment
  */
 #undef  CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0xFF800000
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND 	CONFIG_ENV_SIZE
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_FPGA
 #undef CONFIG_WATCHDOG
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR	0x200000
 #define CONFIG_SYS_PROMPT	"mvBL-M7> "
 #define CONFIG_SYS_CBSIZE	256
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS	16
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_HZ		1000
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_HRCW_LOW	0x0
 #define CONFIG_SYS_HRCW_HIGH	0x0
 /*
  * System performance
  */
 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 #define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
 #define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
 /* clocking */
 #define CONFIG_SYS_SCCR_ENCCM		0
 #define CONFIG_SYS_SCCR_USBMPHCM	0
 #define	CONFIG_SYS_SCCR_USBDRCM	2
 #define CONFIG_SYS_SCCR_TSEC1CM	1
 #define CONFIG_SYS_SCCR_TSEC2CM	1
 #define CONFIG_SYS_SICRH	0x1fff8003
 #define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	CONFIG_SYS_HID0_INIT
 #define CONFIG_SYS_HID2	HID2_HBE
 #define CONFIG_HIGH_BATS	1
 /* DDR  */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 /* PCI  */
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
 				BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 /* no PCI2 */
 #define CONFIG_SYS_IBAT3L	0
 #define CONFIG_SYS_IBAT3U	0
 #define CONFIG_SYS_IBAT4L	0
 #define CONFIG_SYS_IBAT4U	0
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
 				BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 				 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT7L	0
 #define CONFIG_SYS_IBAT7U	0
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02	/* Software reboot */
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_NETDEV		eth0
 /* Default path and filenames */
 #define CONFIG_BOOTDELAY		5
 #define CONFIG_AUTOBOOT_KEYED
 #define CONFIG_AUTOBOOT_STOP_STR	"s"
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 #define CONFIG_RESET_TO_RETRY		1000
 #define MV_CI			mvBL-M7
 #define MV_VCI			mvBL-M7
 #define MV_FPGA_DATA		0xfff80000
 #define MV_FPGA_SIZE		0x00076ca2
 #define MV_KERNEL_ADDR		0xff810000
 #define MV_INITRD_ADDR		0xffb00000
 #define MV_SOURCE_ADDR		0xff804000
 #define MV_SOURCE_ADDR2		0xff806000
 #define MV_DTB_ADDR		0xff808000
 #define MV_INITRD_LENGTH	0x00400000
 #define CONFIG_SHOW_BOOT_PROGRESS 1
 #define MV_KERNEL_ADDR_RAM	0x00100000
 #define MV_DTB_ADDR_RAM		0x00600000
 #define MV_INITRD_ADDR_RAM	0x01000000
 #define CONFIG_BOOTCOMMAND	"if imi ${autoscr_addr}; \
 					then source ${autoscr_addr};  \
 					else source ${autoscr_addr2}; \
 				fi;"
 #define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
 #define CONFIG_EXTRA_ENV_SETTINGS				\
 	"console_nr=0\0"					\
 	"baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" 		\
 	"stdin=serial\0"					\
 	"stdout=serial\0"					\
 	"stderr=serial\0"					\
 	"fpga=0\0"						\
 	"fpgadata=" MK_STR(MV_FPGA_DATA) "\0"			\
 	"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"		\
 	"autoscr_addr=" MK_STR(MV_SOURCE_ADDR) "\0"		\
 	"autoscr_addr2=" MK_STR(MV_SOURCE_ADDR2) "\0"		\
 	"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0"		\
 	"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"	\
 	"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0"		\
 	"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"	\
 	"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0"	\
 	"mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0"			\
 	"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"		\
 	"dtb_name=" MK_STR(MV_DTB_NAME) "\0"			\
 	"mv_version=" U_BOOT_VERSION "\0"			\
 	"dhcp_client_id=" MK_STR(MV_CI) "\0"			\
 	"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"	\
 	"netretry=no\0"						\
 	"use_static_ipaddr=no\0"				\
 	"static_ipaddr=192.168.90.10\0"				\
 	"static_netmask=255.255.255.0\0"			\
 	"static_gateway=0.0.0.0\0"				\
 	"initrd_name=uInitrd.mvblm7-xenorfs\0"			\
 	"zcip=no\0"						\
 	"netboot=yes\0"						\
 	"mvtest=Ff\0"						\
 	"tried_bootfromflash=no\0"				\
 	"tried_bootfromnet=no\0"				\
 	"bootfile=mvblm72625.boot\0"				\
 	"use_dhcp=yes\0"					\
 	"gev_start=yes\0"					\
 	"mvbcdma_debug=0\0"					\
 	"mvbcia_debug=0\0"					\
 	"propdev_debug=0\0"					\
 	"gevss_debug=0\0"					\
 	"watchdog=0\0"						\
 	"usb_dr_mode=host\0"					\
 	"sensor_cnt=2\0"					\
 	""
 #define CONFIG_FPGA_COUNT	1
 #define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #endif

include/configs/PMC440.h

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2007-2008
  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
  * Based on the sequoia configuration file.
  *
  * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2006
  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /************************************************************************
  * PMC440.h - configuration for esd PMC440 boards
  ***********************************************************************/
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_440EPX		1	/* Specific PPC440EPx   */
 #define CONFIG_440		1	/* ... PPC440 family    */
 #define CONFIG_4xx		1	/* ... PPC4xx family    */
 #define CONFIG_SYS_CLK_FREQ	33333400
 #if 0 /* temporary disabled because OS/9 does not like dcache on startup */
 #define CONFIG_4xx_DCACHE		/* enable dcache        */
 #endif
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_F	1
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r     */
 #define CONFIG_BOARD_TYPES	1	/* support board types  */
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_MONITOR_LEN		(384  * 1024)	/* Reserve 384 kB for Monitor   */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 256 kB for malloc()  */
 #define CONFIG_PRAM		0	/* use pram variable to overwrite */
 #define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
 #define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0          */
 #define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH       */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 #define CONFIG_SYS_NAND_ADDR		0xd0000000	/* NAND Flash           */
 #define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm                  */
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
 #define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs    */
 #define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory    */
 #define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
 #define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
 #define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
 #define CONFIG_SYS_PCI_MEMSIZE		0x80000000	/* 2GB! */
 /* Don't change either of these */
 #define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals */
 #define CONFIG_SYS_USB2D0_BASE		0xe0000100
 #define CONFIG_SYS_USB_DEVICE		0xe0000000
 #define CONFIG_SYS_USB_HOST		0xe0000400
 #define CONFIG_SYS_FPGA_BASE0		0xef000000	/* 32 bit */
 #define CONFIG_SYS_FPGA_BASE1		0xef100000	/* 16 bit */
 #define CONFIG_SYS_RESET_BASE		0xef200000
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM                  */
 #define CONFIG_SYS_INIT_RAM_END	(4 << 10)
 #define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI	1
 #undef CONFIG_UART1_CONSOLE	/* console on front panel */
 #define CONFIG_SYS_BAUDRATE_TABLE						\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use FLASH for environment vars */
 #else
 #define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars */
 #define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
 #endif
 /*-----------------------------------------------------------------------
  * RTC
  *----------------------------------------------------------------------*/
 #define CONFIG_RTC_RX8025
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks           */
 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip    */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)      */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)      */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)     */
 #define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection        */
 #define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash        */
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector          */
 #define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector     */
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif
 #ifdef CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_OFFSET		0	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x1000	/* 4096 bytes may be used for env vars */
 #endif
 /*
  * IPL (Initial Program Loader, integrated inside CPU)
  * Will load first 4k from NAND (SPL) into cache and execute it from there.
  *
  * SPL (Secondary Program Loader)
  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
  * controller and the NAND controller so that the special U-Boot image can be
  * loaded from NAND to SDRAM.
  *
  * NUB (NAND U-Boot)
  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
  *
  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
  * set up. While still running from cache, I experienced problems accessing
  * the NAND controller.	sr - 2006-08-25
  */
 #if defined (CONFIG_NAND_U_BOOT)
 #define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location                 */
 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size                     */
 #define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here    */
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr        */
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 /*
  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  */
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image   */
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image     */
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
 #define CONFIG_SYS_NAND_PAGE_SIZE	512	/* NAND chip page size          */
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10) /* NAND chip block size      */
 #define CONFIG_SYS_NAND_PAGE_COUNT	32	/* NAND chip page count         */
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	5	/* Location of bad block marker */
 #undef CONFIG_SYS_NAND_4_ADDR_CYCLE		/* No fourth addr used (<=32MB) */
 #define CONFIG_SYS_NAND_ECCSIZE	256
 #define CONFIG_SYS_NAND_ECCBYTES	3
 #define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 #define CONFIG_SYS_NAND_OOBSIZE	16
 #define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 #define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 #endif
 #ifdef CONFIG_ENV_IS_IN_NAND
 /*
  * For NAND booting the environment is embedded in the U-Boot image. Please take
  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
  */
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #endif
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_MBYTES_SDRAM	(256)	/* 256MB                        */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE	/* use DDR2 optimization        */
 #endif
 #define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes */
 						  /* 440EPx errata CHIP 11 */
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support    */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address  */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
-#define CONFIG_I2C_CMD_TREE	1
 #define CONFIG_I2C_MULTI_BUS	1
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
 #define CONFIG_SYS_EEPROM_WREN			1
 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR	0x52
 /*
  * standard dtt sensor configuration - bottom bit will determine local or
  * remote sensor of the TMP401
  */
 #define CONFIG_DTT_SENSORS		{ 0, 1 }
 /*
  * The PMC440 uses a TI TMP401 temperature sensor. This part
  * is basically compatible to the ADM1021 that is supported
  * by U-Boot.
  *
  * - i2c addr 0x4c
  * - conversion rate 0x02 = 0.25 conversions/second
  * - ALERT ouput disabled
  * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
  */
 #define CONFIG_DTT_ADM1021
 #define CONFIG_SYS_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 #define CONFIG_PREBOOT		"echo Add \\\"run fpga\\\" and "	\
 				"\\\"painit\\\" to preboot command"
 #undef	CONFIG_BOOTARGS
 /* Setup some board specific values for the default environment variables */
 #define CONFIG_HOSTNAME		pmc440
 #define CONFIG_SYS_BOOTFILE	"bootfile=/tftpboot/pmc440/uImage\0"
 #define CONFIG_SYS_ROOTPATH	"rootpath=/opt/eldk/ppc_4xxFP\0"
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_SYS_BOOTFILE						\
 	CONFIG_SYS_ROOTPATH						\
 	"fdt_file=/tftpboot/pmc440/pmc440.dtb\0"			\
 	"netdev=eth0\0"							\
 	"ethrotate=no\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 	"nfsroot=${serverip}:${rootpath}\0"				\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 	"addmisc=setenv bootargs ${bootargs} mem=${mem}\0"		\
 	"nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
 	"nand_boot=run nandargs addip addtty addmisc;bootm ${kernel_addr}\0" \
 	"nand_boot_fdt=run nandargs addip addtty addmisc;"		\
 		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
 	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
 		"run nfsargs addip addtty addmisc;"			\
 		"bootm\0"						\
 	"net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"		\
 		"tftp  ${fdt_addr_r} ${fdt_file};"			\
 		"run nfsargs addip addtty addmisc;"			\
 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
 	"kernel_addr=ffc00000\0"					\
 	"kernel_addr_r=200000\0"					\
 	"fpga_addr=fff00000\0"						\
 	"fdt_addr=fff80000\0"						\
 	"fdt_addr_r=800000\0"						\
 	"fpga=fpga loadb 0 ${fpga_addr}\0"				\
 	"load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"		\
 	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
 		"cp.b 200000 fffa0000 60000\0"				\
 	""
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds     */
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download  */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change        */
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_MII		1	/* MII PHY management           */
 #define CONFIG_PHY_ADDR		0	/* PHY address, See schematics  */
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_HAS_ETH0
 #define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
 #define CONFIG_PHY1_ADDR	1
 #define CONFIG_RESET_PHY_R	1
 /* USB */
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
 #define CONFIG_SYS_USB_OHCI_CPU_INIT	1
 #define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 #include <config_cmd_default.h>
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 /* POST support */
 #define CONFIG_POST		(CONFIG_SYS_POST_MEMORY |	\
 				 CONFIG_SYS_POST_CPU    |	\
 				 CONFIG_SYS_POST_UART   |	\
 				 CONFIG_SYS_POST_I2C    |	\
 				 CONFIG_SYS_POST_CACHE  |	\
 				 CONFIG_SYS_POST_FPU    |	\
 				 CONFIG_SYS_POST_ETHER  |	\
 				 CONFIG_SYS_POST_SPR)
 #define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #define CONFIG_LOGBUFFER
 #define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000	/* free virtual address     */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
 #define CONFIG_SUPPORT_VFAT
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_LONGHELP			/* undef to save memory         */
 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt       */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
 #else
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
 #endif
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on          */
 #define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM       */
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address      */
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 #define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
 #define CONFIG_LOOPW		1	/* enable loopw command         */
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 #define CONFIG_AUTOBOOT_KEYED	1
 #define CONFIG_AUTOBOOT_PROMPT	\
 	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
 #undef CONFIG_AUTOBOOT_DELAY_STR
 #define CONFIG_AUTOBOOT_STOP_STR " "
 /*-----------------------------------------------------------------------
  * PCI stuff
  *----------------------------------------------------------------------*/
 /* General PCI */
 #define CONFIG_PCI		/* include pci support          */
 #define CONFIG_PCI_PNP		/* do (not) pci plug-and-play   */
 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP   */
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup  */
 #define CONFIG_SYS_PCI_TARGBASE	0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 /* Board-specific PCI */
 #define CONFIG_SYS_PCI_TARGET_INIT
 #define CONFIG_SYS_PCI_MASTER_INIT
 /* PCI identification */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh      */
 #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441	/* PCI Device ID: Non-Monarch */
 #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440	/* PCI Device ID: Monarch */
 #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH	PCI_CLASS_PROCESSOR_POWERPC
 #define CONFIG_SYS_PCI_CLASSCODE_MONARCH	PCI_CLASS_BRIDGE_HOST
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FPGA stuff
  *----------------------------------------------------------------------*/
 #define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN2
 #define CONFIG_FPGA_SPARTAN3
 #define CONFIG_FPGA_COUNT	2
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
 /*
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_NAND_CS		2	/* NAND chip connected to CSx   */
 /* Memory Bank 0 (NOR-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB0AP		0x03017200
 #define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 /* Memory Bank 2 (NAND-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB2AP		0x018003c0
 #define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
 #else
 #define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx   */
 /* Memory Bank 2 (NOR-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB2AP		0x03017200
 #define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 /* Memory Bank 0 (NAND-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB0AP		0x018003c0
 #define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
 #endif
 /* Memory Bank 1 (RESET) initialization */
 #define CONFIG_SYS_EBC_PB1AP		0x7f817200 /* 0x03017200 */
 #define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_RESET_BASE | 0x1c000)
 /* Memory Bank 4 (FPGA / 32Bit) initialization */
 #define CONFIG_SYS_EBC_PB4AP		0x03840f40	/* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
 #define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_FPGA_BASE0 | 0x1c000)	/* BS=1M,BU=R/W,BW=32bit */
 /* Memory Bank 5 (FPGA / 16Bit) initialization */
 #define CONFIG_SYS_EBC_PB5AP		0x03840f40	/* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
 #define CONFIG_SYS_EBC_PB5CR		(CONFIG_SYS_FPGA_BASE1 | 0x1a000)	/* BS=1M,BU=R/W,BW=16bit */
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 #define CONFIG_SYS_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl. chips */
 #define CONFIG_SYS_NAND_QUIET_TEST	1
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH     */
 #define BOOTFLAG_WARM	0x02	/* Software reboot                      */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_API		1
 #endif /* __CONFIG_H */

include/configs/SIMPC8313.h

Diff comments View file @ d48eb51

 /*
  * Copyright (C) Sheldon Instruments, Inc. 2008
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * simpc8313 board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_NAND_U_BOOT
 #define CONFIG_E300			1
 #define CONFIG_MPC83XX			1
 #define CONFIG_MPC831X			1
 #define CONFIG_MPC8313			1
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI
 #define CONFIG_MISC_INIT_R
 /*
  * On-board devices
  *
  * TSEC1 is Marvell PHY 88E1118
  */
 #define CONFIG_SYS_33MHZ
 #define CONFIG_83XX_CLKIN		33333333	/* in Hz */
 #define CONFIG_SYS_CLK_FREQ		CONFIG_83XX_CLKIN
 #define CONFIG_SYS_IMMR			0xE0000000
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DEFAULT_IMMR		CONFIG_SYS_IMMR
 #endif
 #define CONFIG_SYS_MEMTEST_START	0x00001000
 #define CONFIG_SYS_MEMTEST_END		0x07f00000
 #define CONFIG_SYS_ACR_PIPE_DEP		3	/* Arbiter pipeline depth (0-3) */
 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 /*
  * Device configurations
  */
 #define CONFIG_TSEC1
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_MAX_MEM_MAPPED		(512 << 20)
 #define CONFIG_SYS_DDRCDR		( DDRCDR_EN \
 					| DDRCDR_PZ_NOMZ \
 					| DDRCDR_NZ_NOMZ \
 					| DDRCDR_M_ODR )
 					/* 0x73000002 TODO ODR & DRN ? */
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 #if !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END		0x1000		/* End of used area in RAM*/
 #define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
 /*
  * Local Bus LCRR and LBCR regs
  */
 #define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
 #define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
 				| (0xFF << LBCR_BMT_SHIFT) \
 				| 0xF )	/* 0x0004ff0f */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
 /* drivers/mtd/nand/nand.c */
 #ifdef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE		0xFFF00000
 #else
 #define CONFIG_SYS_NAND_BASE		0xE2800000
 #endif
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS			1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND 		1
 #define CONFIG_NAND_FSL_ELBC		1
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00100100
 #define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
 #define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
 					| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 					| BR_PS_8		/* Port Size = 8 bit */ \
 					| BR_MS_FCM		/* MSEL = FCM */ \
 					| BR_V )		/* valid */
 #ifdef CONFIG_NAND_SP
 #define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFF8000	/* length 32K */ \
 					| OR_FCM_CSCT \
 					| OR_FCM_CST \
 					| OR_FCM_CHT \
 					| OR_FCM_SCY_1 \
 					| OR_FCM_TRLX \
 					| OR_FCM_EHTR )
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000000E	/* 32KB */
 #define CONFIG_SYS_NAND_PAGE_SIZE	(512)		/* NAND chip page size */
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size */
 #define NAND_CACHE_PAGES		32
 #elif defined(CONFIG_NAND_LP)
 #define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFC0000	/* length 256K */ \
 					| OR_FCM_PGS \
 					| OR_FCM_CSCT \
 					| OR_FCM_CST \
 					| OR_FCM_CHT \
 					| OR_FCM_SCY_1 \
 					| OR_FCM_TRLX \
 					| OR_FCM_EHTR )
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000011	/* 256KB */
 #define CONFIG_SYS_NAND_PAGE_SIZE	(2048)		/* NAND chip page size */
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip block size */
 #define NAND_CACHE_PAGES		64
 #else
 #error Page size of NAND not defined.
 #endif /* CONFIG_NAND_SP */
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_NAND_BR_PRELIM
 #define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_NAND_OR_PRELIM
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM	CONFIG_SYS_LBLAWBAR0_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR0_PRELIM
 /*
  * JFFS2 configuration
  */
 #define CONFIG_JFFS2_NAND
 #define CONFIG_JFFS2_DEV	"nand0"
 /* mtdparts command line support */
 #define CONFIG_CMD_MTDPARTS
 #define MTDIDS_DEFAULT		"nand0=nand0"
 #define MTDPARTS_DEFAULT	"mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT		1
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #ifdef CONFIG_NAND_SPL
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 #define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR+0x4600)
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES		{{0,0x69}} /* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_IO_BASE		0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
 #define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1057	/* Motorola */
 /*
  * TSEC
  */
 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
 #define CONFIG_NET_MULTI
 #define CONFIG_GMII			/* MII PHY management */
 #ifdef CONFIG_TSEC1
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME		"TSEC0"
 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
 #define TSEC1_PHY_ADDR			0x0
 #define TSEC1_FLAGS			TSEC_GIGABIT
 #define TSEC1_PHYIDX			0
 #endif
 #ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME		"TSEC1"
 #define CONFIG_SYS_TSEC2_OFFSET		0x25000
 #define TSEC2_PHY_ADDR			4
 #define TSEC2_FLAGS			TSEC_GIGABIT
 #define TSEC2_PHYIDX			0
 #endif
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC1"
 /*
  * Configure on-board RTC
  */
 #define CONFIG_RTC_DS1337
 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
 /*
  * Environment
  */
 #if defined(CONFIG_NAND_U_BOOT)
 	#define CONFIG_ENV_IS_IN_NAND		1
 	#define CONFIG_ENV_OFFSET		(768 * 1024)
 	#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 	#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
 	#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
 	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
 	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 #elif !defined(CONFIG_SYS_RAMBOOT)
 	#define CONFIG_ENV_IS_IN_FLASH		1
 	#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
 	#define CONFIG_ENV_SIZE			0x2000
 /* Address and size of Redundant Environment Sector */
 #else
 	#define CONFIG_ENV_IS_NOWHERE		1	/* Store ENV in memory only */
 	#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE			0x2000
 #endif
 #define CONFIG_LOADS_ECHO			1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_IMLS
 #undef CONFIG_CMD_FLASH
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_JFFS2
 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 	#undef CONFIG_CMD_SAVEENV
 	#undef CONFIG_CMD_LOADS
 #endif
 #define CONFIG_CMDLINE_EDITING		1
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP				/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		( CONFIG_SYS_CBSIZE		\
 					+ sizeof(CONFIG_SYS_PROMPT)	\
 					+ 16 )	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ			1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_RCWH_PCIHOST		0x80000000	/* PCIHOST */
 #define CONFIG_SYS_HRCW_LOW		( HRCWL_LCL_BUS_TO_SCB_CLK_1X1	\
 					| 0x20000000 /* reserved */	\
 					| HRCWL_DDR_TO_SCB_CLK_2X1	\
 					| HRCWL_CSB_TO_CLKIN_4X1	\
 					| HRCWL_CORE_TO_CSB_2_5X1 )
 #define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 4)
 #define CONFIG_SYS_HRCW_HIGH_BASE	( HRCWH_PCI_HOST		\
 					| HRCWH_PCI1_ARBITER_ENABLE	\
 					| HRCWH_CORE_ENABLE		\
 					| HRCWH_BOOTSEQ_DISABLE		\
 					| HRCWH_SW_WATCHDOG_DISABLE	\
 					| HRCWH_TSEC1M_IN_RGMII		\
 					| HRCWH_TSEC2M_IN_RGMII		\
 					| HRCWH_BIG_ENDIAN		\
 					| HRCWH_LALE_NORMAL )
 #ifdef CONFIG_NAND_LP
 #define CONFIG_SYS_HRCW_HIGH	( CONFIG_SYS_HRCW_HIGH_BASE		\
 				| HRCWH_FROM_0XFFF00100			\
 				| HRCWH_ROM_LOC_NAND_LP_8BIT		\
 				| HRCWH_RL_EXT_NAND)
 #else
 #define CONFIG_SYS_HRCW_HIGH	( CONFIG_SYS_HRCW_HIGH_BASE		\
 				| HRCWH_FROM_0XFFF00100			\
 				| HRCWH_ROM_LOC_NAND_SP_8BIT		\
 				| HRCWH_RL_EXT_NAND )
 #endif
 /* System IO Config */
 #define CONFIG_SYS_SICRH	( SICRH_ETSEC2_B	\
 				| SICRH_ETSEC2_C	\
 				| SICRH_ETSEC2_D	\
 				| SICRH_ETSEC2_E	\
 				| SICRH_ETSEC2_F	\
 				| SICRH_ETSEC2_G	\
 				| SICRH_TSOBI1		\
 				| SICRH_TSOBI2 )
 #define CONFIG_SYS_SICRL	(SICRL_USBDR		\
 				| SICRL_ETSEC2_A )
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK	\
 				| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
 #define CONFIG_SYS_HID2		HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR @ 0x00000000 */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT1L	((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
 #define CONFIG_SYS_IBAT1U	((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
 /* PCI @ 0x80000000 */
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 /* PCI2 not supported on 8313 */
 #define CONFIG_SYS_IBAT4L	(0)
 #define CONFIG_SYS_IBAT4U	(0)
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT7L	(0)
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02	/* Software reboot */
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_NETDEV		eth1
 #define CONFIG_HOSTNAME		simpc8313
 #define CONFIG_ROOTPATH		/tftpboot/
 #define CONFIG_BOOTFILE		/tftpboot/uImage
 #define CONFIG_UBOOTPATH	u-boot-nand.bin	/* U-Boot image on TFTP server */
 #define CONFIG_FDTFILE		simpc8313.dtb
 #define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	5	/* 5 second delay */
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTCOMMAND	"nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
 	"ethprime=TSEC1\0"						\
 	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
 	"tftpflash=tftpboot $loadaddr $uboot; "				\
 		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
 		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
 		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
 	"fdtaddr=ae0000\0"						\
 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
 	"console=ttyS0\0"						\
 	"setbootargs=setenv bootargs "					\
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"	\
 	"load_uboot=tftp 100000 u-boot-nand.bin\0"			\
 	"burn_uboot=nand erase u-boot 80000; "				\
 		"nand write 100000 u-boot $filesize\0"			\
 	"update_uboot=run load_uboot;run burn_uboot\0"			\
 	"mtdids=nand0=nand0\0"						\
 	"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"	\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
 	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "		\
 		"console=ttyS0,115200\0"				\
 	""
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv rootdev /dev/nfs;"					\
 	"run setbootargs;"						\
 	"run setipargs;"						\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
 	"setenv rootdev /dev/ram;"					\
 	"run setbootargs;"						\
 	"tftp $ramdiskaddr $ramdiskfile;"				\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 #undef MK_STR
 #undef XMK_STR
 #endif	/* __CONFIG_H */

include/configs/XPEDITE5200.h

Diff comments View file @ d48eb51

 /*
  * Copyright 2008 Extreme Engineering Solutions, Inc.
  * Copyright 2004-2008 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * xpedite5200 board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8548		1
 #define CONFIG_XPEDITE5200	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite5200"
 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
 #define CONFIG_RELOC_FIXUP_WORKS	/* Fully relocate to SDRAM */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
 #define CONFIG_PCI1		1	/* PCI controller 1 */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 /*
  * DDR config
  */
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #define SPD_EEPROM_ADDRESS		0x54
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 #define CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_CLK_FREQ	66666666
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 #define CONFIG_SYS_PCI1_ADDR	(CONFIG_SYS_CCSRBAR + 0x8000)
 /*
  * Diagnostics
  */
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
 /*
  * Memory map
  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
  * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
  * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
  * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
  * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
  */
 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
 /*
  * NAND flash configuration
  */
 #define CONFIG_SYS_NAND_BASE		0xef800000
 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_NAND_ACTL
 #define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
 #define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
 #define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
 #define CONFIG_SYS_NAND_ACTL_DELAY	25
 /*
  * NOR flash configuration
  */
 #define CONFIG_SYS_FLASH_BASE		0xfc000000
 #define CONFIG_SYS_FLASH_BASE2		0xf8000000
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
 						  {0xfbf40000, 0xc0000} }
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 /*
  * Chip select configuration
  */
 /* NOR Flash 0 on CS0 */
 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
 				 BR_PS_16		| \
 				 BR_V)
 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
 				 OR_GPCM_ACS_DIV4	| \
 				 OR_GPCM_SCY_8)
 /* NOR Flash 1 on CS1 */
 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
 				 BR_PS_16		| \
 				 BR_V)
 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
 /* NAND flash on CS2 */
 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
 				 BR_PS_8		| \
 				 BR_V)
 /* NAND flash on CS2 */
 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
 				 OR_GPCM_BCTLD		| \
 				 OR_GPCM_CSNT		| \
 				 OR_GPCM_ACS_DIV4	| \
 				 OR_GPCM_SCY_4		| \
 				 OR_GPCM_TRLX		| \
 				 OR_GPCM_EHTR)
 /* NAND flash on CS3 */
 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
 				 BR_PS_8		| \
 				 BR_V)
 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
 /*
  * Use L1 as initial stack
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
 #define CONFIG_SYS_INIT_RAM_END		0x4000
 #define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * Use the HUSH parser
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 /*
  * Pass open firmware flat tree
  */
 #define CONFIG_OF_LIBFDT		1
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 #define CONFIG_SYS_64BIT_VSPRINTF	1
 #define CONFIG_SYS_64BIT_STRTOUL	1
 /*
  * I2C
  */
 #define CONFIG_FSL_I2C				/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C				/* I2C with hardware support */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 /* I2C EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
 /* I2C RTC */
 #define CONFIG_RTC_M41T11			1
 #define CONFIG_SYS_I2C_RTC_ADDR			0x68
 #define CONFIG_SYS_M41T11_BASE_YEAR		2000
 /* GPIO */
 #define CONFIG_PCA953X
 #define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
 #define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
 #define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
 /* PCA957 @ 0x18 */
 #define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
 #define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
 #define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
 #define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
 #define CONFIG_SYS_PCA953X_FLASH_WP		0x20
 #define CONFIG_SYS_PCA953X_MONARCH		0x40
 #define CONFIG_SYS_PCA953X_EREADY		0x80
 /* PCA957 @ 0x19 */
 #define CONFIG_SYS_PCA953X_P14_IO0		0x01
 #define CONFIG_SYS_PCA953X_P14_IO1		0x02
 #define CONFIG_SYS_PCA953X_P14_IO2		0x04
 #define CONFIG_SYS_PCA953X_P14_IO3		0x08
 #define CONFIG_SYS_PCA953X_P14_IO4		0x10
 #define CONFIG_SYS_PCA953X_P14_IO5		0x20
 #define CONFIG_SYS_PCA953X_P14_IO6		0x40
 #define CONFIG_SYS_PCA953X_P14_IO7		0x80
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
 #define CONFIG_SYS_PCI1_IO_BASE		0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
 #define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
 /*
  * Networking options
  */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_ETHPRIME		"eTSEC1"
 #define CONFIG_TSEC1		1
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC1_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC2		1
 #define CONFIG_TSEC2_NAME	"eTSEC2"
 #define TSEC2_FLAGS		TSEC_GIGABIT
 #define TSEC2_PHY_ADDR		2
 #define TSEC2_PHYIDX		0
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC3"
 #define TSEC3_FLAGS		TSEC_GIGABIT
 #define TSEC3_PHY_ADDR		3
 #define TSEC3_PHYIDX		0
 #define CONFIG_HAS_ETH2
 #define CONFIG_TSEC4	1
 #define CONFIG_TSEC4_NAME	"eTSEC4"
 #define TSEC4_FLAGS		TSEC_GIGABIT
 #define TSEC4_PHY_ADDR		4
 #define TSEC4_PHYIDX		0
 #define CONFIG_HAS_ETH3
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 /*
  * Command configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_FIT		1
 #define CONFIG_FIT_VERBOSE	1
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 /*
  * Boot Flags
  */
 #define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02		/* Software reboot */
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
 #define CONFIG_ENV_SIZE		0x8000
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
 /*
  * Flash memory map:
  * fff80000 - ffffffff     Pri U-Boot (512 KB)
  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
  * fff00000 - fff3ffff     Pri FDT (256KB)
  * fef00000 - ffefffff     Pri OS image (16MB)
  * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
  *
  * fbf80000 - fbffffff     Sec U-Boot (512 KB)
  * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
  * fbf00000 - fbf3ffff     Sec FDT (256KB)
  * faf00000 - fbefffff     Sec OS image (16MB)
  * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
  */
 #define CONFIG_UBOOT1_ENV_ADDR	MK_STR(0xfff80000)
 #define CONFIG_UBOOT2_ENV_ADDR	MK_STR(0xfbf80000)
 #define CONFIG_FDT1_ENV_ADDR	MK_STR(0xfff00000)
 #define CONFIG_FDT2_ENV_ADDR	MK_STR(0xfbf00000)
 #define CONFIG_OS1_ENV_ADDR	MK_STR(0xfef00000)
 #define CONFIG_OS2_ENV_ADDR	MK_STR(0xfaf00000)
 #define CONFIG_PROG_UBOOT1						\
 	"$download_cmd $loadaddr $ubootfile; "				\
 	"if test $? -eq 0; then "					\
 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
 		"if test $? -ne 0; then "				\
 			"echo PROGRAM FAILED; "				\
 		"else; "						\
 			"echo PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_UBOOT2						\
 	"$download_cmd $loadaddr $ubootfile; "				\
 	"if test $? -eq 0; then "					\
 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
 		"if test $? -ne 0; then "				\
 			"echo PROGRAM FAILED; "				\
 		"else; "						\
 			"echo PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_BOOT_OS_NET						\
 	"$download_cmd $osaddr $osfile; "				\
 	"if test $? -eq 0; then "					\
 		"if test -n $fdtaddr; then "				\
 			"$download_cmd $fdtaddr $fdtfile; "		\
 			"if test $? -eq 0; then "			\
 				"bootm $osaddr - $fdtaddr; "		\
 			"else; "					\
 				"echo FDT DOWNLOAD FAILED; "		\
 			"fi; "						\
 		"else; "						\
 			"bootm $osaddr; "				\
 		"fi; "							\
 	"else; "							\
 		"echo OS DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_OS1							\
 	"$download_cmd $osaddr $osfile; "				\
 	"if test $? -eq 0; then "					\
 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
 		"if test $? -ne 0; then "				\
 			"echo OS PROGRAM FAILED; "			\
 		"else; "						\
 			"echo OS PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo OS DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_OS2							\
 	"$download_cmd $osaddr $osfile; "				\
 	"if test $? -eq 0; then "					\
 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
 		"if test $? -ne 0; then "				\
 			"echo OS PROGRAM FAILED; "			\
 		"else; "						\
 			"echo OS PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo OS DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_FDT1						\
 	"$download_cmd $fdtaddr $fdtfile; "				\
 	"if test $? -eq 0; then "					\
 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
 		"if test $? -ne 0; then "				\
 			"echo FDT PROGRAM FAILED; "			\
 		"else; "						\
 			"echo FDT PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo FDT DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_FDT2						\
 	"$download_cmd $fdtaddr $fdtfile; "				\
 	"if test $? -eq 0; then "					\
 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
 		"if test $? -ne 0; then "				\
 			"echo FDT PROGRAM FAILED; "			\
 		"else; "						\
 			"echo FDT PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo FDT DOWNLOAD FAILED; "				\
 	"fi;"
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"autoload=yes\0"						\
 	"download_cmd=tftp\0"						\
 	"console_args=console=ttyS0,115200\0"				\
 	"root_args=root=/dev/nfs rw\0"					\
 	"misc_args=ip=on\0"						\
 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 	"bootfile=/home/user/file\0"					\
 	"osfile=/home/user/uImage-XPedite5200\0"			\
 	"fdtfile=/home/user/xpedite5200.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
 	"fdtaddr=c00000\0"						\
 	"osaddr=0x1000000\0"						\
 	"loadaddr=0x1000000\0"						\
 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
 	"prog_os1="CONFIG_PROG_OS1"\0"					\
 	"prog_os2="CONFIG_PROG_OS2"\0"					\
 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
 	"bootcmd_flash1=run set_bootargs; "				\
 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 	"bootcmd_flash2=run set_bootargs; "				\
 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 	"bootcmd=run bootcmd_flash1\0"
 #endif	/* __CONFIG_H */

include/configs/XPEDITE5370.h

Diff comments View file @ d48eb51

 /*
  * Copyright 2008 Extreme Engineering Solutions, Inc.
  * Copyright 2007-2008 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * xpedite5370 board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8572		1
 #define CONFIG_XPEDITE5370	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite5370"
 #define CONFIG_NUM_CPUS		2	/* 2 Cores */
 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
 #define CONFIG_RELOC_FIXUP_WORKS	/* Fully relocate to SDRAM */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 /*
  * DDR config
  */
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
 #define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
 #define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
 #define CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR + 0xa000)
 #define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR + 0x9000)
 /*
  * Diagnostics
  */
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
 /*
  * Memory map
  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
  * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
  * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
  * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
  * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
  * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
  */
 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
 /*
  * NAND flash configuration
  */
 #define CONFIG_SYS_NAND_BASE		0xef800000
 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
 /*
  * NOR flash configuration
  */
 #define CONFIG_SYS_FLASH_BASE		0xf8000000
 #define CONFIG_SYS_FLASH_BASE2		0xf0000000
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
 						  {0xf7f40000, 0xc0000} }
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 /*
  * Chip select configuration
  */
 /* NOR Flash 0 on CS0 */
 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
 				 BR_PS_16		| \
 				 BR_V)
 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
 				 OR_GPCM_CSNT		| \
 				 OR_GPCM_XACS		| \
 				 OR_GPCM_ACS_DIV2	| \
 				 OR_GPCM_SCY_8		| \
 				 OR_GPCM_TRLX		| \
 				 OR_GPCM_EHTR		| \
 				 OR_GPCM_EAD)
 /* NOR Flash 1 on CS1 */
 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
 				 BR_PS_16		| \
 				 BR_V)
 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
 /* NAND flash on CS2 */
 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
 				 (2<<BR_DECC_SHIFT)	| \
 				 BR_PS_8		| \
 				 BR_MS_FCM		| \
 				 BR_V)
 /* NAND flash on CS2 */
 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
 				 OR_FCM_PGS	| \
 				 OR_FCM_CSCT	| \
 				 OR_FCM_CST	| \
 				 OR_FCM_CHT	| \
 				 OR_FCM_SCY_1	| \
 				 OR_FCM_TRLX	| \
 				 OR_FCM_EHTR)
 /* NAND flash on CS3 */
 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
 				 (2<<BR_DECC_SHIFT)	| \
 				 BR_PS_8		| \
 				 BR_MS_FCM		| \
 				 BR_V)
 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
 /*
  * Use L1 as initial stack
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
 #define CONFIG_SYS_INIT_RAM_END		0x00004000
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * Use the HUSH parser
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 /*
  * Pass open firmware flat tree
  */
 #define CONFIG_OF_LIBFDT		1
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 #define CONFIG_SYS_64BIT_VSPRINTF	1
 #define CONFIG_SYS_64BIT_STRTOUL	1
 /*
  * I2C
  */
 #define CONFIG_FSL_I2C				/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C				/* I2C with hardware support */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 /* PEX8518 slave I2C interface */
 #define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
 /* I2C DS1631 temperature sensor */
 #define CONFIG_SYS_I2C_DS1621_ADDR	0x48
 #define CONFIG_DTT_DS1621
 #define CONFIG_DTT_SENSORS		{ 0 }
 /* I2C EEPROM - AT24C128B */
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
 /* I2C RTC */
 #define CONFIG_RTC_M41T11		1
 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
 #define CONFIG_SYS_M41T11_BASE_YEAR	2000
 /* GPIO/EEPROM/SRAM */
 #define CONFIG_DS4510
 #define CONFIG_SYS_I2C_DS4510_ADDR	0x51
 /* GPIO */
 #define CONFIG_PCA953X
 #define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
 #define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
 #define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
 #define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
 #define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
 /*
  * PU = pulled high, PD = pulled low
  * I = input, O = output, IO = input/output
  */
 /* PCA9557 @ 0x18*/
 #define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
 #define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
 #define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
 #define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
 #define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
 /* PCA9557 @ 0x1c*/
 #define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
 #define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
 #define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
 #define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
 #define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
 #define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
 #define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
 #define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
 /* PCA9557 @ 0x1e*/
 #define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
 #define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
 #define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
 #define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
 #define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
 #define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
 #define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
 /* PCA9557 @ 0x1f */
 #define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
 #define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
 #define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
 #define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* PCIE1 - VPX P1 */
 #define CONFIG_SYS_PCIE1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 /* PCIE2 - PEX8518 */
 #define CONFIG_SYS_PCIE2_MEM_BASE	0xc0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
 /*
  * Networking options
  */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_NET_MULTI	1
 #define CONFIG_TSEC_TBI
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
 #define CONFIG_ETHPRIME		"eTSEC2"
 #define CONFIG_TSEC1		1
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC2		1
 #define CONFIG_TSEC2_NAME	"eTSEC2"
 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_PHY_ADDR		2
 #define TSEC2_PHYIDX		0
 #define CONFIG_HAS_ETH1
 /*
  * Command configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DS4510
 #define CONFIG_CMD_DS4510_INFO
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_FIT		1
 #define CONFIG_FIT_VERBOSE	1
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 /*
  * Boot Flags
  */
 #define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02		/* Software reboot */
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
 #define CONFIG_ENV_SIZE		0x8000
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
 /*
  * Flash memory map:
  * fff80000 - ffffffff     Pri U-Boot (512 KB)
  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
  * fff00000 - fff3ffff     Pri FDT (256KB)
  * fef00000 - ffefffff     Pri OS image (16MB)
  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
  *
  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
  * f7f00000 - f7f3ffff     Sec FDT (256KB)
  * f6f00000 - f7efffff     Sec OS image (16MB)
  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
  */
 #define CONFIG_UBOOT1_ENV_ADDR	MK_STR(0xfff80000)
 #define CONFIG_UBOOT2_ENV_ADDR	MK_STR(0xf7f80000)
 #define CONFIG_FDT1_ENV_ADDR	MK_STR(0xfff00000)
 #define CONFIG_FDT2_ENV_ADDR	MK_STR(0xf7f00000)
 #define CONFIG_OS1_ENV_ADDR	MK_STR(0xfef00000)
 #define CONFIG_OS2_ENV_ADDR	MK_STR(0xf6f00000)
 #define CONFIG_PROG_UBOOT1						\
 	"$download_cmd $loadaddr $ubootfile; "				\
 	"if test $? -eq 0; then "					\
 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
 		"if test $? -ne 0; then "				\
 			"echo PROGRAM FAILED; "				\
 		"else; "						\
 			"echo PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_UBOOT2						\
 	"$download_cmd $loadaddr $ubootfile; "				\
 	"if test $? -eq 0; then "					\
 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
 		"if test $? -ne 0; then "				\
 			"echo PROGRAM FAILED; "				\
 		"else; "						\
 			"echo PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_BOOT_OS_NET						\
 	"$download_cmd $osaddr $osfile; "				\
 	"if test $? -eq 0; then "					\
 		"if test -n $fdtaddr; then "				\
 			"$download_cmd $fdtaddr $fdtfile; "		\
 			"if test $? -eq 0; then "			\
 				"bootm $osaddr - $fdtaddr; "		\
 			"else; "					\
 				"echo FDT DOWNLOAD FAILED; "		\
 			"fi; "						\
 		"else; "						\
 			"bootm $osaddr; "				\
 		"fi; "							\
 	"else; "							\
 		"echo OS DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_OS1							\
 	"$download_cmd $osaddr $osfile; "				\
 	"if test $? -eq 0; then "					\
 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
 		"if test $? -ne 0; then "				\
 			"echo OS PROGRAM FAILED; "			\
 		"else; "						\
 			"echo OS PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo OS DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_OS2							\
 	"$download_cmd $osaddr $osfile; "				\
 	"if test $? -eq 0; then "					\
 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
 		"if test $? -ne 0; then "				\
 			"echo OS PROGRAM FAILED; "			\
 		"else; "						\
 			"echo OS PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo OS DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_FDT1						\
 	"$download_cmd $fdtaddr $fdtfile; "				\
 	"if test $? -eq 0; then "					\
 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
 		"if test $? -ne 0; then "				\
 			"echo FDT PROGRAM FAILED; "			\
 		"else; "						\
 			"echo FDT PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo FDT DOWNLOAD FAILED; "				\
 	"fi;"
 #define CONFIG_PROG_FDT2						\
 	"$download_cmd $fdtaddr $fdtfile; "				\
 	"if test $? -eq 0; then "					\
 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
 		"if test $? -ne 0; then "				\
 			"echo FDT PROGRAM FAILED; "			\
 		"else; "						\
 			"echo FDT PROGRAM SUCCEEDED; "			\
 		"fi; "							\
 	"else; "							\
 		"echo FDT DOWNLOAD FAILED; "				\
 	"fi;"
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"autoload=yes\0"						\
 	"download_cmd=tftp\0"						\
 	"console_args=console=ttyS0,115200\0"				\
 	"root_args=root=/dev/nfs rw\0"					\
 	"misc_args=ip=on\0"						\
 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 	"bootfile=/home/user/file\0"					\
 	"osfile=/home/user/uImage-XPedite5370\0"			\
 	"fdtfile=/home/user/xpedite5370.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
 	"fdtaddr=c00000\0"						\
 	"osaddr=0x1000000\0"						\
 	"loadaddr=0x1000000\0"						\
 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
 	"prog_os1="CONFIG_PROG_OS1"\0"					\
 	"prog_os2="CONFIG_PROG_OS2"\0"					\
 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
 	"bootcmd_flash1=run set_bootargs; "				\
 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 	"bootcmd_flash2=run set_bootargs; "				\
 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 	"bootcmd=run bootcmd_flash1\0"
 #endif	/* __CONFIG_H */

include/configs/ads5121.h

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2007, 2008 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * ADS5121 board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #define CONFIG_ADS5121 1
 /*
  * Memory map for the ADS5121 board:
  *
  * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
  * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
  * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
  * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
  * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
  * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
  * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
  * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
  */
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
 #define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
 #undef CONFIG_FSL_DIU_LOGO_BMP		/* Don't include FSL DIU binary bmp */
 /* video */
 #undef CONFIG_VIDEO
 #if defined(CONFIG_VIDEO)
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #endif
 /* CONFIG_PCI is defined at config time */
 #ifdef CONFIG_ADS5121_REV2
 #define CONFIG_SYS_MPC512X_CLKIN	66000000	/* in Hz */
 #else
 #define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
 #define CONFIG_PCI
 #endif
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SYS_IMMR		0x80000000
 #define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
 #define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 /*
  * DDR Setup - manually set all parameters as there's no SPD etc.
  */
 #ifdef CONFIG_ADS5121_REV2
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
 #else
 #define CONFIG_SYS_DDR_SIZE		512		/* MB */
 #endif
 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 /* DDR Controller Configuration
  *
  * SYS_CFG:
  *	[31:31]	MDDRC Soft Reset:	Diabled
  *	[30:30]	DRAM CKE pin:		Enabled
  *	[29:29]	DRAM CLK:		Enabled
  *	[28:28]	Command Mode:		Enabled (For initialization only)
  *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
  *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
  *	[20:19]	Read Test:		DON'T USE
  *	[18:18]	Self Refresh:		Enabled
  *	[17:17]	16bit Mode:		Disabled
  *	[16:13] Ready Delay:		2
  *	[12:12]	Half DQS Delay:		Disabled
  *	[11:11]	Quarter DQS Delay:	Disabled
  *	[10:08]	Write Delay:		2
  *	[07:07]	Early ODT:		Disabled
  *	[06:06]	On DIE Termination:	Disabled
  *	[05:05]	FIFO Overflow Clear:	DON'T USE here
  *	[04:04]	FIFO Underflow Clear:	DON'T USE here
  *	[03:03]	FIFO Overflow Pending:	DON'T USE here
  *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
  *	[01:01]	FIFO Overlfow Enabled:	Enabled
  *	[00:00]	FIFO Underflow Enabled:	Enabled
  * TIME_CFG0
  *	[31:16]	DRAM Refresh Time:	0 CSB clocks
  *	[15:8]	DRAM Command Time:	0 CSB clocks
  *	[07:00]	DRAM Precharge Time:	0 CSB clocks
  * TIME_CFG1
  *	[31:26]	DRAM tRFC:
  *	[25:21]	DRAM tWR1:
  *	[20:17]	DRAM tWRT1:
  *	[16:11]	DRAM tDRR:
  *	[10:05]	DRAM tRC:
  *	[04:00]	DRAM tRAS:
  * TIME_CFG2
  *	[31:28]	DRAM tRCD:
  *	[27:23]	DRAM tFAW:
  *	[22:19]	DRAM tRTW1:
  *	[18:15]	DRAM tCCD:
  *	[14:10] DRAM tRTP:
  *	[09:05]	DRAM tRP:
  *	[04:00] DRAM tRPA
  */
 #ifdef CONFIG_ADS5121_REV2
 #define CONFIG_SYS_MDDRC_SYS_CFG	0xF8604A00
 #define CONFIG_SYS_MDDRC_SYS_CFG_RUN	0xE8604A00
 #define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
 #define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
 #else
 #define CONFIG_SYS_MDDRC_SYS_CFG	 0xFA804A00
 #define CONFIG_SYS_MDDRC_SYS_CFG_RUN	 0xEA804A00
 #define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
 #define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
 #endif
 #define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
 #define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
 #define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x06183D2E
 #define CONFIG_SYS_MICRON_NOP		0x01380000
 #define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
 #define CONFIG_SYS_MICRON_EM2		0x01020000
 #define CONFIG_SYS_MICRON_EM3		0x01030000
 #define CONFIG_SYS_MICRON_EN_DLL	0x01010000
 #define CONFIG_SYS_MICRON_RFSH		0x01080000
 #define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
 #define CONFIG_SYS_MICRON_OCD_DEFAULT	0x01010780
 /* DDR Priority Manager Configuration */
 #define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
 #define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
 #define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
 #define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
 #define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
 #define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
 #define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
 #define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
 #define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
 #define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
 #define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
 #define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
 #define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
 #define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
 #define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
 #define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
 #define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
 #define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
 #define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
 #define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
 #define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
 #define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
 /*
  * NOR FLASH on the Local Bus
  */
 #undef CONFIG_BKUP_FLASH
 #define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #ifdef CONFIG_BKUP_FLASH
 #define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		0x00800000	/* max flash size in bytes */
 #else
 #define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size in bytes */
 #endif
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
 #define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
 #undef CONFIG_SYS_FLASH_CHECKSUM
 /*
  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
  * window is 64KB
  */
 #define CONFIG_SYS_CPLD_BASE		0x82000000
 #define CONFIG_SYS_CPLD_SIZE		0x00010000	/* 64 KB */
 #define CONFIG_SYS_SRAM_BASE		0x30000000
 #define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
 #define CONFIG_SYS_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
 #define CONFIG_SYS_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */
 #define CONFIG_SYS_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */
 /* Use SRAM for initial stack */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_SRAM_SIZE		/* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
 #ifdef	CONFIG_FSL_DIU_FB
 #define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
 #else
 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
 #endif
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX     1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 /*
  * Serial console configuration
  */
 #define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
 #if CONFIG_PSC_CONSOLE != 3
 #error CONFIG_PSC_CONSOLE must be 3
 #endif
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 #define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
 #define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
 #define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
 #define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 /*
  * PCI
  */
 #ifdef CONFIG_PCI
 /*
  * General PCI
  */
 #define CONFIG_SYS_PCI_MEM_BASE	0xA0000000
 #define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
 #define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
 #define CONFIG_SYS_PCI_IO_PHYS		0x84000000
 #define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #if 0
 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
 #endif
 /*
  * IIM - IC Identification Module
  */
 #undef CONFIG_IIM
 /*
  * EEPROM configuration
  */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC512x_FEC	1
 #define CONFIG_NET_MULTI
 #define CONFIG_PHY_ADDR		0x1
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_FEC_AN_TIMEOUT	1
 #define CONFIG_HAS_ETH0
 /*
  * Configure on-board RTC
  */
 #define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
 #define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 /* This has to be a multiple of the Flash sector size */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SIZE		0x2000
 #ifdef CONFIG_BKUP_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (256K) for env */
 #else
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* one sector (256K) for env */
 #endif
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DATE
 #undef CONFIG_CMD_FUSE
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_EXT2
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #endif
 #if defined(CONFIG_CMD_IDE)
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 #define CONFIG_ISO_PARTITION
 #endif /* defined(CONFIG_CMD_IDE) */
 /*
  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
  * to chapter 36 of the MPC5121e Reference Manual.
  */
 /* #define CONFIG_WATCHDOG */		/* enable watchdog */
 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
  /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
 	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 /* Cache Configuration */
 #define CONFIG_SYS_DCACHE_SIZE		32768
 #define CONFIG_SYS_CACHELINE_SIZE	32
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
 #endif
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 #define CONFIG_SYS_HID2	HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_TIMESTAMP
 #define CONFIG_HOSTNAME		ads5121
 #define CONFIG_BOOTFILE		ads5121/uImage
 #define CONFIG_ROOTPATH		/opt/eldk/ppc_6xx
 #define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"u-boot_addr_r=200000\0"					\
 	"kernel_addr_r=600000\0"					\
 	"fdt_addr_r=880000\0"						\
 	"ramdisk_addr_r=900000\0"					\
 	"u-boot_addr=FFF00000\0"					\
 	"kernel_addr=FFC40000\0"					\
 	"fdt_addr=FFEC0000\0"						\
 	"ramdisk_addr=FC040000\0"					\
 	"ramdiskfile=ads5121/uRamdisk\0"				\
 	"u-boot=ads5121/u-boot.bin\0"					\
 	"bootfile=ads5121/uImage\0"					\
 	"fdtfile=ads5121/ads5121.dtb\0"					\
 	"rootpath=/opt/eldk/ppc_6xx\n"					\
 	"netdev=eth0\0"							\
 	"consdev=ttyPSC0\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} "				\
 		"console=${consdev},${baudrate}\0"			\
 	"flash_nfs=run nfsargs addip addtty;"				\
 		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
 	"flash_self=run ramargs addip addtty;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
 	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
 		"tftp ${fdt_addr_r} ${fdtfile};"			\
 		"run nfsargs addip addtty;"				\
 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
 	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
 		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
 		"tftp ${fdt_addr_r} ${fdtfile};"			\
 		"run ramargs addip addtty;"				\
 		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
 	"update=protect off ${u-boot_addr} +${filesize};"		\
 		"era ${u-boot_addr} +${filesize};"			\
 		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
 	"upd=run load update\0"						\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
 #define OF_CPU			"PowerPC,5121@0"
 #define OF_SOC_COMPAT		"fsl,mpc5121-immr"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
 #undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
 #undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
 #undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
 #define CONFIG_IDE_RESET		/* reset for IDE supported	*/
 #define CONFIG_IDE_PREINIT
 #define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
 #define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 #define CONFIG_SYS_ATA_BASE_ADDR	MPC512X_PATA
 /* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
 #define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
 /* Offset for normal register accesses	*/
 #define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 /* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
 #define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
 /* Interval between registers	*/
 #define CONFIG_SYS_ATA_STRIDE		4
 #define ATA_BASE_ADDR		MPC512X_PATA
 /*
  * Control register bit definitions
  */
 #define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
 #define FSL_ATA_CTRL_ATA_RST_B		0x40000000
 #define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
 #define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
 #define FSL_ATA_CTRL_DMA_PENDING	0x08000000
 #define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
 #define FSL_ATA_CTRL_DMA_WRITE		0x02000000
 #define FSL_ATA_CTRL_IORDY_EN		0x01000000
 #endif	/* __CONFIG_H */

include/configs/at91rm9200ek.h

Diff comments View file @ d48eb51

 /*
  * Ulf Samuelsson <ulf@atmel.com>
  * Rick Bronson <rick@efn.org>
  *
  * Configuration settings for the AT91RM9200EK board.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /* ARM asynchronous clock */
 /*
  * from 18.432 MHz crystal
  * (18432000 / 4 * 39)
  */
 #define AT91C_MAIN_CLOCK	179712000
 /*
  * peripheral clock
  * (AT91C_MASTER_CLOCK / 3)
  */
 #define AT91C_MASTER_CLOCK	59904000
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 #define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
 #define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
 #define CONFIG_AT91RM9200EK	1	/* on an AT91RM9200EK Board	*/
 #undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 #define USE_920T_MMU		1
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	1
 /*
  * LowLevel Init
  */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
 /* flash */
 #define CONFIG_SYS_MC_PUIA_VAL	0x00000000
 #define CONFIG_SYS_MC_PUP_VAL	0x00000000
 #define CONFIG_SYS_MC_PUER_VAL	0x00000000
 #define CONFIG_SYS_MC_ASR_VAL	0x00000000
 #define CONFIG_SYS_MC_AASR_VAL	0x00000000
 #define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
 #define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 /* clocks */
 #define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
 #define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
 #define CONFIG_SYS_MCKR_VAL	0x00000202
 /* sdram */
 #define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
 #define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
 #define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
 #define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
 #define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
 #define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
 #define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
 #define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
 #define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
 #define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
 #else
 #define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
 #define CONFIG_SYS_AT91C_BRGR_DIVISOR	33
 /*
  * Memory Configuration
  */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			0x20000000
 #define PHYS_SDRAM_SIZE			0x02000000	/* 32 megs */
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END		\
 		(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144)
 /*
  * Hardware drivers
  */
 /*
  * UART Configuration
  *
  * define one of these to choose the DBGU,
  * USART0 or USART1 as console
  */
 #define CONFIG_AT91RM9200_USART
 #define CONFIG_DBGU
 #undef CONFIG_USART0
 #undef CONFIG_USART1
 /* don't include RTS/CTS flow control support	*/
 #undef	CONFIG_HWFLOW
 /* disable modem initialization stuff */
 #undef	CONFIG_MODEM_SUPPORT
 #define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 #define CONFIG_BAUDRATE			115200
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_IMI
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_MISC
 #undef CONFIG_CMD_LOADS
 #include <asm/arch/AT91RM9200.h>	/* needed for port definitions */
 /* Options for MMC/SD Card */
 #define CONFIG_DOS_PARTITION	1
 #undef CONFIG_MMC
 #define CONFIG_SYS_MMC_BASE		0xFFFB4000
 #define CONFIG_SYS_MMC_BLOCKSIZE	512
 /*
  * Network Driver Setting
  */
 #define CONFIG_DRIVER_ETHER
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_AT91C_USE_RMII
 /*
  * AC Characteristics
  * DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns
  */
 #define DATAFLASH_TCSS	(0xC << 16)
 #define DATAFLASH_TCHS	(0x1 << 24)
 #if defined(CONFIG_HAS_DATAFLASH)
 #define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
 #define CONFIG_SYS_MAX_DATAFLASH_PAGES		16384
 /* Logical adress for CS0 */
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
 /* Logical adress for CS3 */
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000
 #define	CONFIG_SYS_SUPPORT_BLOCK_ERASE		1
 #define	CONFIG_SYS_DATAFLASH_MMC_PIO		AT91C_PIO_PB22
 #endif
 /*
  * NOR Flash
  */
 #define CONFIG_SYS_FLASH_BASE			0x10000000
 #define PHYS_FLASH_SIZE				0x800000	/* 8MB */
 #define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER			1
 #define CONFIG_SYS_MAX_FLASH_BANKS		1
 #define CONFIG_SYS_MAX_FLASH_SECT		256
 #define CONFIG_SYS_FLASH_PROTECTION
 /*
  * Environment Settings
  */
 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
 /*
  * Datasflash Environment Settings
  */
 #define CONFIG_ENV_OFFSET			0x4200
 #define CONFIG_ENV_ADDR			\
 		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 /* 8 * 1056 really , but start.s is not OK with this*/
 #define CONFIG_ENV_SIZE			0x2000
 #else
 /*
  * NOR Flash Environment Settings
  */
 #define CONFIG_ENV_IS_IN_FLASH		1
 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 /*
  * between boot.bin and u-boot.bin.gz
  */
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0xe000)
 #define CONFIG_ENV_SIZE			0x10000 /* sectors are 64K here */
 #else
 /*
  * after u-boot.bin
  */
 #define CONFIG_ENV_ADDR			\
 		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SIZE			0x10000 /* sectors are 64K here */
 /* The following #defines are needed to get flash environment right */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_MONITOR_LEN		\
 		(CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE)
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 #endif	/* CONFIG_ENV_IS_IN_DATAFLASH */
 /*
  * Boot option
  */
 #define CONFIG_BOOTDELAY		3
 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 /* boot.bin, env, u-boot.bin.gz */
 #define CONFIG_SYS_BOOT_SIZE		0x6000 /* 24 KBytes */
 #define CONFIG_SYS_U_BOOT_BASE		(CONFIG_SYS_FLASH_BASE + 0x10000)
 #define CONFIG_SYS_U_BOOT_SIZE		0x10000 /* 64 KBytes */
 #else
 /* u-boot.bin */
 #define CONFIG_SYS_BOOT_SIZE		0x0 /* 0 KBytes */
 #define CONFIG_SYS_U_BOOT_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_U_BOOT_SIZE		0x40000 /* 128 KBytes */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 #define CONFIG_SYS_LOAD_ADDR		0x21000000 /* default load address */
 #define CONFIG_ENV_OVERWRITE	1
 /*
  * USB Config
  */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_OHCI_NEW	1
 #define CONFIG_USB_KEYBOARD	1
 #define CONFIG_USB_STORAGE	1
 #define CONFIG_DOS_PARTITION	1
 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
 #define CONFIG_SYS_USB_OHCI_REGS_BASE		AT91_USB_HOST_BASE
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 /*
  * I2C
  */
 #define CONFIG_HARD_I2C
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		0	/* not used */
 #define CONFIG_SYS_I2C_SLAVE		0	/* not used */
 #endif
 /*
  * Shell Settings
  */
 #define CONFIG_CMDLINE_EDITING		1
 #define CONFIG_SYS_LONGHELP		1
 #define CONFIG_AUTO_COMPLETE		1
 #define CONFIG_SYS_HUSH_PARSER		1
 #define CONFIG_SYS_PROMPT		"U-Boot> "
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		\
 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #ifndef __ASSEMBLY__
 /*-----------------------------------------------------------------------
  * Board specific extension for bd_info
  *
  * This structure is embedded in the global bd_info (bd_t) structure
  * and can be used by the board specific code (eg board/...)
  */
 struct bd_info_ext {
 	/* helper variable for board environment handling
 	 *
 	 * env_crc_valid == 0	=>	uninitialised
 	 * env_crc_valid > 0	=>	environment crc in flash is valid
 	 * env_crc_valid < 0	=>	environment crc in flash is invalid
 	 */
 	int env_crc_valid;
 };
 #endif
 #define CONFIG_SYS_HZ 1000
 /*
  * AT91C_TC0_CMR is implicitly set to
  * AT91C_TC_TIMER_DIV1_CLOCK
  */
 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
 #define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \
 					     , 0x1000)
 /* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
 #define CONFIG_STACKSIZE_IRQ		(4 * 1024) /* Unsure if to big or to small*/
 #define CONFIG_STACKSIZE_FIQ		(4 * 1024) /* Unsure if to big or to small*/
 #endif

include/configs/katmai.h

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /************************************************************************
  * katmai.h - configuration for AMCC Katmai (440SPe)
  ***********************************************************************/
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_KATMAI			1	/* Board is Katmai	*/
 #define CONFIG_4xx			1	/* ... PPC4xx family	*/
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 #define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
 /*
  * Enable this board for more than 2GB of SDRAM
  */
 #define CONFIG_PHYS_64BIT
 #define	CONFIG_VERY_BIG_RAM
 /*
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		katmai
 #include "amcc-common.h"
 /*
  * For booting 256K-paged Linux we should have 16MB of memory
  * for Linux initial memory map
  */
 #undef CONFIG_SYS_BOOTMAPSZ
 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH	*/
 #define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
 #define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
 #define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
 #define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
 #define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
 #define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
 #define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
 #define CONFIG_SYS_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
 #define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
 #define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
 #define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
 #define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
 #define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
 #define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000
 /* base address of inbound PCIe window */
 #define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
 /* System RAM mapped to PCI space */
 #define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
 #define CONFIG_SYS_ACE_BASE		0xfe000000	/* Xilinx ACE controller - Compact Flash */
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
 #define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #undef CONFIG_UART1_CONSOLE
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
 #define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
 #define SPD_EEPROM_ADDRESS	{0x51, 0x52}	/* SPD i2c spd addresses*/
 #define CONFIG_DDR_ECC		1	/* with ECC support		*/
 #define CONFIG_DDR_RQDC_FIXED	0x80000038 /* optimal value found by GDA*/
 #undef  CONFIG_STRESS
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_SPD_BUS_NUM		0	/* The I2C bus for SPD		*/
 #define IIC0_BOOTPROM_ADDR	0x50
 #define IIC0_ALT_BOOTPROM_ADDR	0x54
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 #define CONFIG_SYS_I2C_EEPROM_ADDR	(0x50)
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 /* I2C RTC */
 #define CONFIG_RTC_M41T11	1
 #define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC		*/
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 #define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/
 /* I2C DTT */
 #define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support	*/
 #define CONFIG_SYS_DTT_BUS_NUM		1	/* The I2C bus for DTT		*/
 /*
  * standard dtt sensor configuration - bottom bit will determine local or
  * remote sensor of the ADM1021, the rest determines index into
  * CONFIG_SYS_DTT_ADM1021 array below.
  */
 #define CONFIG_DTT_SENSORS	{ 0, 1 }
 /*
  * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
  * there will be one entry in this array for each two (dummy) sensors in
  * CONFIG_DTT_SENSORS.
  *
  * For Katmai board:
  * - only one ADM1021
  * - i2c addr 0x18
  * - conversion rate 0x02 = 0.25 conversions/second
  * - ALERT ouput disabled
  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
  * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
  */
 #define CONFIG_SYS_DTT_ADM1021		{ { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
 #define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
 /*
  * Default environment variables
  */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_AMCC_DEF_ENV						\
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=fff10000\0"					\
 	"ramdisk_addr=fff20000\0"					\
 	"kozio=bootm ffc60000\0"					\
 	"pciconfighost=1\0"						\
 	"pcie_mode=RP:RP:RP\0"						\
 	""
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
 #define	CONFIG_IBM_EMAC4_V4	1	/* 440SPe has this EMAC version	*/
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
 #define CONFIG_HAS_ETH0
 #define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
 #define CONFIG_PHY_RESET_DELAY	1000
 #define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 #define CONFIG_SYS_MAX_FLASH_BANKS     1		    /* number of banks	    */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024		    /* sectors per device   */
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector	*/
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
 /* General PCI */
 #define CONFIG_PCI			/* include pci support		*/
 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 /* Board-specific PCI */
 #define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
 #undef	CONFIG_SYS_PCI_MASTER_INIT
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
 /* #define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 /*
  *  NETWORK Support (PCI):
  */
 /* Support for Intel 82557/82559/82559ER chips. */
 #define CONFIG_EEPRO100
 /*-----------------------------------------------------------------------
  * Xilinx System ACE support
  *----------------------------------------------------------------------*/
 #define CONFIG_SYSTEMACE	1	/* Enable SystemACE support	*/
 #define CONFIG_SYS_SYSTEMACE_WIDTH	16	/* Data bus width is 16		*/
 #define CONFIG_SYS_SYSTEMACE_BASE	CONFIG_SYS_ACE_BASE
 #define CONFIG_DOS_PARTITION	1
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
 /* Memory Bank 0 (Flash) initialization					*/
 #define CONFIG_SYS_EBC_PB0AP		(EBC_BXAP_BME_DISABLED      |		\
 				 EBC_BXAP_TWT_ENCODE(7)     |		\
 				 EBC_BXAP_BCE_DISABLE       |		\
 				 EBC_BXAP_BCT_2TRANS        |		\
 				 EBC_BXAP_CSN_ENCODE(0)     |		\
 				 EBC_BXAP_OEN_ENCODE(0)     |		\
 				 EBC_BXAP_WBN_ENCODE(0)     |		\
 				 EBC_BXAP_WBF_ENCODE(0)     |		\
 				 EBC_BXAP_TH_ENCODE(0)      |		\
 				 EBC_BXAP_RE_DISABLED       |		\
 				 EBC_BXAP_SOR_DELAYED       |		\
 				 EBC_BXAP_BEM_WRITEONLY     |		\
 				 EBC_BXAP_PEN_DISABLED)
 #define CONFIG_SYS_EBC_PB0CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |	\
 				 EBC_BXCR_BS_16MB                    |	\
 				 EBC_BXCR_BU_RW                      |	\
 				 EBC_BXCR_BW_16BIT)
 /* Memory Bank 1 (Xilinx System ACE controller) initialization		*/
 #define CONFIG_SYS_EBC_PB1AP		(EBC_BXAP_BME_DISABLED      |		\
 				 EBC_BXAP_TWT_ENCODE(4)     |		\
 				 EBC_BXAP_BCE_DISABLE       |		\
 				 EBC_BXAP_BCT_2TRANS        |		\
 				 EBC_BXAP_CSN_ENCODE(0)     |		\
 				 EBC_BXAP_OEN_ENCODE(0)     |		\
 				 EBC_BXAP_WBN_ENCODE(0)     |		\
 				 EBC_BXAP_WBF_ENCODE(0)     |		\
 				 EBC_BXAP_TH_ENCODE(0)      |		\
 				 EBC_BXAP_RE_DISABLED       |		\
 				 EBC_BXAP_SOR_NONDELAYED    |		\
 				 EBC_BXAP_BEM_WRITEONLY     |		\
 				 EBC_BXAP_PEN_DISABLED)
 #define CONFIG_SYS_EBC_PB1CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |	\
 				 EBC_BXCR_BS_1MB                    |	\
 				 EBC_BXCR_BU_RW                     |	\
 				 EBC_BXCR_BW_16BIT)
 /*-------------------------------------------------------------------------
  * Initialize EBC CONFIG -
  * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
  * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
  *-------------------------------------------------------------------------*/
 #define CONFIG_SYS_EBC_CFG		(EBC_CFG_LE_UNLOCK    |	\
 				 EBC_CFG_PTD_ENABLE   |	\
 				 EBC_CFG_RTC_16PERCLK | \
 				 EBC_CFG_ATC_PREVIOUS | \
 				 EBC_CFG_DTC_PREVIOUS | \
 				 EBC_CFG_CTC_PREVIOUS | \
 				 EBC_CFG_OEO_PREVIOUS | \
 				 EBC_CFG_EMC_DEFAULT  |	\
 				 EBC_CFG_PME_DISABLE  |	\
 				 EBC_CFG_PR_16)
 /*-----------------------------------------------------------------------
  * GPIO Setup
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_GPIO_PCIE_PRESENT0	17
 #define CONFIG_SYS_GPIO_PCIE_PRESENT1	21
 #define CONFIG_SYS_GPIO_PCIE_PRESENT2	23
 #define CONFIG_SYS_GPIO_RS232_FORCEOFF	30
 #define CONFIG_SYS_PFC0		(GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
 				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
 				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
 				 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
 #define CONFIG_SYS_GPIO_OR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 #define CONFIG_SYS_GPIO_TCR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 #define CONFIG_SYS_GPIO_ODR		0
 #endif	/* __CONFIG_H */

include/configs/keymile-common.h

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2008
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_KEYMILE_H
 #define __CONFIG_KEYMILE_H
 /* Do boardspecific init for all boards */
 #define CONFIG_BOARD_EARLY_INIT_R       1
 #define CONFIG_BOOTCOUNT_LIMIT
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ECHO
 #define CONFIG_CMD_IMMAP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_JFFS2_CMDLINE
 #undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 #undef	CONFIG_BOOTARGS			/* the boot command will set bootargs */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
 #define CONFIG_CMDLINE_EDITING		1	/* add command line history     */
 #define CONFIG_COMMAND_HISTORY		1
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
 #define CONFIG_HUSH_INIT_VAR	1
 #define CONFIG_SYS_ALT_MEMTEST		/* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 #define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * How to get access to the slot ID.  Put this here to make it easy
  * to modify in a centralized location.  This is used in the HDLC
  * driver to set the MAC.
 */
 #define CONFIG_CHECK_ETHERNET_PRESENT	1
 #define CONFIG_SYS_SLOT_ID_BASE		CONFIG_SYS_PIGGY_BASE
 #define CONFIG_SYS_SLOT_ID_OFF		(0x07)	/* register offset */
 #define CONFIG_SYS_SLOT_ID_MASK		(0x3f)	/* mask for slot ID bits */
 #define CONFIG_I2C_MULTI_BUS	1
-#define CONFIG_I2C_CMD_TREE	1
 #define CONFIG_SYS_MAX_I2C_BUS		2
 #define CONFIG_SYS_I2C_INIT_BOARD	1
 #define CONFIG_I2C_MUX		1
 /* EEprom support */
 #define CONFIG_SYS_I2C_MULTI_EEPROMS	1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 /* Support the IVM EEprom */
 #define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
 #define	CONFIG_SYS_FLASH_PROTECTION 1
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /* define this to use the keymile's io muxing feature */
 /*#define CONFIG_IO_MUXING */
 #ifdef CONFIG_IO_MUXING
 #define	CONFIG_KM_DEF_ENV_IOMUX \
 	"nc=setenv ethact HDLC ETHERNET \0" \
 	"nce=setenv ethact SCC ETHERNET \0"	\
 	"stderr=serial,nc \0"	\
 	"stdin=serial,nc \0" \
 	"stdout=serial,nc \0" \
 	"tftpsrcp=69 \0" \
 	"tftpdstp=69 \0"
 #else
 #define	CONFIG_KM_DEF_ENV_IOMUX \
 	"stderr=serial \0" \
 	"stdin=serial \0"	 \
 	"stdout=serial \0"
 #endif
 #ifndef CONFIG_KM_DEF_ENV_PRIVATE
 #define	CONFIG_KM_DEF_ENV_PRIVATE \
 	"kmprivate=empty\0"
 #endif
 #define xstr(s)	str(s)
 #define str(s)	#s
 #ifndef CONFIG_KM_DEF_ENV
 #define CONFIG_KM_DEF_ENV	\
 	"netdev=eth0\0"							\
 	"u-boot_addr_r=100000\0"					\
 	"kernel_addr_r=200000\0"					\
 	"fdt_addr_r=600000\0"						\
 	"ram_ws=800000 \0"						\
 	"autoscr_ws=780000 \0"						\
 	"fdt_file=" xstr(CONFIG_HOSTNAME) "/" 				\
 		xstr(CONFIG_HOSTNAME) ".dtb\0"				\
 	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" 		\
 	"kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" 		\
 	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
 	"update=protect off " xstr(BOOTFLASH_START) " +${filesize};"	\
 		"erase " xstr(BOOTFLASH_START) "  +${filesize};"	\
 		"cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) 		\
 		"  ${filesize};"					\
 		"protect on " xstr(BOOTFLASH_START) "  +${filesize}\0"	\
 	"load_fdt=tftp ${fdt_addr_r} ${fdt_file}; "			\
 		"setenv actual_fdt_addr ${fdt_addr_r} \0" 		\
 	"load_kernel=tftp ${kernel_addr_r} ${kernel_file}; " 		\
 		"setenv actual_kernel_addr ${kernel_addr_r} \0" 	\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"mtdargs=setenv bootargs root=${actual_rootfs} rw "		\
 		"rootfstype=jffs2 \0" 					\
 	"altmtdargs=setenv bootargs root=${backup_rootfs} rw "		\
 		"rootfstype=jffs2 \0" 					\
 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addboardid=setenv bootargs ${bootargs} " 			\
 		"hwKey=${IVM_HWKey} boardId=0x${IVM_BoardId} \0" 	\
 	"addpram=setenv bootargs ${bootargs} "				\
 		"mem=${mem} pram=${pram}\0"				\
 	"pram=" xstr(CONFIG_PRAM) "k\0"					\
 	"net_nfs=tftp ${kernel_addr_r} ${kernel_file}; "		\
 		"tftp ${fdt_addr_r} ${fdt_file}; "			\
 		"run nfsargs addip addcon addboardid addpram;"		\
 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
 	"net_self=tftp ${kernel_addr_r} ${kernel_file}; "		\
 		"tftp ${fdt_addr_r} ${fdt_file}; "			\
 		"tftp ${ramdisk_addr} ${ramdisk_file}; "		\
 		"run ramargs addip addboardid addpram; "		\
 		"bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"\
 	"flash_nfs=run nfsargs addip addcon;"				\
 		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
 	"flash_self=run ramargs addip addcon addboardid addpram;"	\
 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
 	"bootcmd=run mtdargs addip addcon addboardid addpram; "		\
 		"bootm ${actual_kernel_addr} - ${actual_fdt_addr} \0"	\
 	"altbootcmd=run altmtdargs addip addcon addboardid addpram; "	\
 		"bootm ${backup_kernel_addr} - ${backup_fdt_addr} \0"	\
 	"actual0=setenv actual_bank 0; setenv actual_kernel_addr "	\
 		"${bank0_kernel_addr}; "				\
 		"setenv actual_fdt_addr ${bank0_fdt_addr}; "		\
 		"setenv actual_rootfs ${bank0_rootfs} \0" 		\
 	"actual1=setenv actual_bank 1; setenv actual_kernel_addr "	\
 		"${bank1_kernel_addr}; "				\
 		"setenv actual_fdt_addr ${bank1_fdt_addr}; "		\
 		"setenv actual_rootfs ${bank1_rootfs} \0" 		\
 	"backup0=setenv backup_bank 0; setenv backup_kernel_addr " 	\
 		"${bank0_kernel_addr}; "				\
 		"setenv backup_fdt_addr ${bank0_fdt_addr}; "		\
 		"setenv backup_rootfs ${bank0_rootfs} \0"		\
 	"backup1=setenv backup_bank 1; setenv backup_kernel_addr "	\
 		"${bank1_kernel_addr}; "				\
 		"setenv backup_fdt_addr ${bank1_fdt_addr}; " 		\
 		"setenv backup_rootfs ${bank1_rootfs} \0" 		\
 	"setbank0=run actual0 backup1 \0" 				\
 	"setbank1=run actual1 backup0 \0" 				\
 	"release=setenv bootcmd "					\
 		"\'run mtdargs addip addcon addboardid addpram;" 	\
 		"bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; "	\
 		"saveenv \0"						\
 	"develop=setenv bootcmd "					\
 		"\'run nfsargs addip addcon addboardid addpram;" 	\
 		"bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; "	\
 		"saveenv \0"						\
 	"developall=setenv bootcmd "					\
 		"\'run load_fdt load_kernel nfsargs "			\
 		"addip addcon addboardid addpram; "			\
 		"bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; "	\
 		"saveenv \0"						\
 	"set_new_esw_script=setenv new_esw_script "			\
 		"new_esw_0x${IVM_BoardId}_0x${IVM_HWKey}.scr \0"	\
 	"new_esw=run set_new_esw_script; "				\
 		"tftp ${autoscr_ws} ${new_esw_script}; "		\
 		"iminfo ${autoscr_ws}; source ${autoscr_ws} \0"	\
 	"bootlimit=0 \0" 						\
 	CONFIG_KM_DEF_ENV_IOMUX						\
 	CONFIG_KM_DEF_ENV_PRIVATE					\
 	""
 #endif /* CONFIG_KM_DEF_ENV */
 #define CONFIG_VERSION_VARIABLE 	/* include version env variable */
 #endif /* __CONFIG_KEYMILE_H */

include/configs/kmeter1.h

Diff comments View file @ d48eb51

 /*
  * Copyright (C) 2006 Freescale Semiconductor, Inc.
  *                    Dave Liu <daveliu@freescale.com>
  *
  * Copyright (C) 2007 Logic Product Development, Inc.
  *                    Peter Barada <peterb@logicpd.com>
  *
  * Copyright (C) 2007 MontaVista Software, Inc.
  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  *
  * (C) Copyright 2008
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_QE		1 /* Has QE */
 #define CONFIG_MPC83XX		1 /* MPC83XX family */
 #define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
 #define CONFIG_KMETER1		1 /* KMETER1 board specific */
 #define CONFIG_HOSTNAME		kmeter1
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"
 #undef CONFIG_SYS_I2C_INIT_BOARD
 #define CONFIG_MISC_INIT_R	1
 /*
  * System Clock Setup
  */
 #define CONFIG_83XX_CLKIN		66000000
 #define CONFIG_SYS_CLK_FREQ		66000000
 #define CONFIG_83XX_PCICLK		66000000
 /*
  * Hardware Reset Configuration Word
  */
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_CSB_TO_CLKIN_4X1 | \
 	HRCWL_CORE_TO_CSB_2X1 | \
 	HRCWL_CE_PLL_VCO_DIV_2 | \
 	HRCWL_CE_TO_PLL_1X6 )
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_CORE_ENABLE | \
 	HRCWH_FROM_0X00000100 | \
 	HRCWH_BOOTSEQ_DISABLE | \
 	HRCWH_SW_WATCHDOG_DISABLE | \
 	HRCWH_ROM_LOC_LOCAL_16BIT | \
 	HRCWH_BIG_ENDIAN | \
 	HRCWH_LALE_EARLY | \
 	HRCWH_LDP_CLEAR )
 /*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH		0x00000006
 #define CONFIG_SYS_SICRL		0x00000000
 /*
  * IMMR new address
  */
 #define CONFIG_SYS_IMMR		0xE0000000
 /*
  * DDR Setup
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #define CFG_83XX_DDR_USES_CS0
 #undef CONFIG_DDR_ECC
 /*
  * DDRCDR - DDR Control Driver Register
  */
 #undef CONFIG_SPD_EEPROM	/* Do not use SPD EEPROM for DDR setup */
 /*
  * Manually set up DDR parameters
  */
 #define CONFIG_DDR_II
 #define CONFIG_SYS_DDR_SIZE		2048 /* MB */
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
 					 CSCONFIG_ROW_BIT_13 | \
 					 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 					 SDRAM_CFG_SREN)
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #define CONFIG_SYS_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #define CONFIG_SYS_DDR_INTERVAL	((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 				 (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
 #define	CONFIG_SYS_DDRCDR		0x40000001
 #define CONFIG_SYS_DDR_MODE		0x47860452
 #define CONFIG_SYS_DDR_MODE2		0x8080c000
 #define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 				 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 				 (0 << TIMING_CFG0_WWT_SHIFT) | \
 				 (0 << TIMING_CFG0_RRT_SHIFT) | \
 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
 				 (0 << TIMING_CFG0_RWT_SHIFT))
 #define CONFIG_SYS_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_50) | \
 				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 				 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
 				 ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
 				 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 				 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 				 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 #define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 				 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 				 (5 << TIMING_CFG2_CPO_SHIFT))
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 /*
  * The reserved memory
  */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
 #define CONFIG_SYS_FLASH_BASE		0xF0000000
 #define CONFIG_SYS_FLASH_BASE_1		0xF2000000
 #define CONFIG_SYS_PIGGY_BASE		0xE8000000
 #define	CONFIG_SYS_PIGGY_SIZE		128
 #define CONFIG_SYS_PAXE_BASE		0xA0000000
 #define	CONFIG_SYS_PAXE_SIZE		512
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 /*
  * Initial RAM Base Address Setup
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 /*
  * Local Bus Configuration & Clock Setup
  */
 #define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
 /*
  * Init Local Bus Memory Controller:
  *
  * Bank Bus     Machine PortSz  Size  Device
  * ---- ---     ------- ------  -----  ------
  *  0   Local   GPCM    16 bit  256MB FLASH
  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
  *  3   Local   GPCM     8 bit  512MB PAXE
  *
  */
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
 #define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
 #define CONFIG_SYS_FLASH_PROTECTION	1
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001b /* 256MB window size */
 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | \
 				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 				BR_V)
 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_SCY_5 | \
 				OR_GPCM_TRLX | OR_GPCM_EAD)
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000001A /* 128MB window size */
 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_PIGGY_BASE | \
 				(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 				BR_V)
 #define CONFIG_SYS_OR1_PRELIM		(MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_SCY_2 | \
 				OR_GPCM_TRLX | OR_GPCM_EAD)
 /*
  * PAXE on the local bus CS3
  */
 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PAXE_BASE /* Window base at flash base */
 #define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000001C /* 512MB window size */
 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_PAXE_BASE | \
 				(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 				BR_V)
 #define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_SCY_2 | \
 				OR_GPCM_TRLX | OR_GPCM_EAD)
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #undef CONFIG_PCI		/* No PCI */
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
 #endif
 /*
  * QE UEC ethernet configuration
  */
 #define CONFIG_UEC_ETH
 #define CONFIG_ETHPRIME		"FSL UEC0"
 #define CONFIG_UEC_ETH1		/* GETH1 */
 #define UEC_VERBOSE_DEBUG	1
 #ifdef CONFIG_UEC_ETH1
 #define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE	/* not used in RMII Mode */
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	0
 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
 #endif
 /*
  * Environment
  */
 #ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x20000
 #define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #else /* CFG_RAMBOOT */
 #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
 #endif /* CFG_RAMBOOT */
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_FSL_I2C
 #define CONFIG_SYS_I2C_SPEED	200000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE	0x7F
 #define CONFIG_SYS_I2C_OFFSET	0x3000
 #define CONFIG_I2C_MULTI_BUS	1
-#define CONFIG_I2C_CMD_TREE	1
 #define CONFIG_SYS_MAX_I2C_BUS		2
 #define CONFIG_I2C_MUX		1
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
 #define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
 #define CONFIG_DTT_SENSORS	{0, 1, 2, 3}	/* Sensor addresses		*/
 #define CONFIG_SYS_DTT_MAX_TEMP	70
 #define CONFIG_SYS_DTT_LOW_TEMP	-30
 #define CONFIG_SYS_DTT_HYSTERESIS	3
 #define CONFIG_SYS_DTT_BUS_NUM		(2)
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #endif
 #if defined(CFG_RAMBOOT)
 #undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_LOADS
 #endif
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 /*
  * Core HID Setup
  */
 #define CONFIG_SYS_HID0_INIT		0x000000000
 #define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
 #define CONFIG_SYS_HID2			HID2_HBE
 /*
  * MMU Setup
  */
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR: cache cacheable */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 /* Stack in dcache: cacheable, no memory coherence */
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
 #define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CFG_DBAT6L	CFG_IBAT6L
 #define CFG_DBAT6U	CFG_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
 #define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CFG_DBAT7L	CFG_IBAT7L
 #define CFG_DBAT7U	CFG_IBAT7U
 #else /* CONFIG_PCI */
 #define CONFIG_SYS_IBAT6L	(0)
 #define CONFIG_SYS_IBAT6U	(0)
 #define CONFIG_SYS_IBAT7L	(0)
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif /* CONFIG_PCI */
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02 /* Software reboot */
 #define BOOTFLASH_START	F0000000
 #define CONFIG_PRAM	512	/* protected RAM [KBytes] */
 #define MTDIDS_DEFAULT		"nor0=app"
 #define MTDPARTS_DEFAULT \
 	"mtdparts=app:256k(u-boot),128k(env),128k(envred),"	\
 	"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 #endif
 #define CONFIG_EXTRA_ENV_SETTINGS \
        CONFIG_KM_DEF_ENV						\
 	"rootpath=/opt/eldk/ppc_82xx\0"					\
 	"addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 	"ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"			\
 	"loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"		\
 	"loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"			\
 	"loadkernel=tftp ${kernel_addr_r} ${bootfile}\0"		\
 	"unlock=yes\0"							\
 	"fdt_addr=F0080000\0"						\
 	"kernel_addr=F00a0000\0"					\
 	"ramdisk_addr=F03a0000\0"					\
 	"ramdisk_addr_r=F10000\0"					\
 	"EEprom_ivm=pca9547:70:9\0"					\
 	"dtt_bus=pca9547:70:a\0"					\
 	"mtdids=nor0=app \0"						\
 	"mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"			\
    ""
 #if defined(CONFIG_UEC_ETH)
 #define CONFIG_HAS_ETH0
 #endif
 #endif /* __CONFIG_H */

include/configs/korat.h

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2007-2009
  * Larry Johnson, lrj@acm.org
  *
  * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2006
  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * korat.h - configuration for Korat board
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_440EPX		1	/* Specific PPC440EPx		*/
 #define CONFIG_4xx		1	/* ... PPC4xx family		*/
 #define CONFIG_SYS_CLK_FREQ	33333333
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
 /*
  * Manufacturer's information serial EEPROM parameters
  */
 #define MAN_DATA_EEPROM_ADDR	0x53	/* EEPROM I2C address		*/
 #define MAN_INFO_FIELD		2
 #define MAN_INFO_LENGTH		9
 #define MAN_MAC_ADDR_FIELD	3
 #define MAN_MAC_ADDR_LENGTH	12
 /*
  * Base addresses -- Note these are effective addresses where the actual
  * resources get mapped (not physical addresses).
  */
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kiB for Monitor  */
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kiB for malloc() */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CONFIG_SYS_FLASH0_SIZE		0x01000000
 #define CONFIG_SYS_FLASH0_ADDR		(-CONFIG_SYS_FLASH0_SIZE)
 #define CONFIG_SYS_FLASH1_TOP		0xF8000000
 #define CONFIG_SYS_FLASH1_MAX_SIZE	0x08000000
 #define CONFIG_SYS_FLASH1_ADDR		(CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH1_ADDR	/* start of FLASH	*/
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 #define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm			*/
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
 #define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
 #define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
 /* Don't change either of these */
 #define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
 #define CONFIG_SYS_USB2D0_BASE		0xe0000100
 #define CONFIG_SYS_USB_DEVICE		0xe0000000
 #define CONFIG_SYS_USB_HOST		0xe0000400
 #define CONFIG_SYS_CPLD_BASE		0xc0000000
 /*
  * Initial RAM & stack pointer
  */
 /* 440EPx has 16KB of internal SRAM, so no need for D-Cache		*/
 #undef CONFIG_SYS_INIT_RAM_DCACHE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
 #define CONFIG_SYS_INIT_RAM_END	(4 << 10)
 #define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data	*/
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 /*
  * Serial Port
  */
 #define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI	1
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 #define CONFIG_SYS_BAUDRATE_TABLE						\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environ vars	*/
 /*
  * FLASH related
  */
 #define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	      */
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	      */
 #define CONFIG_FLASH_CFI_LEGACY		/* Allow hard-coded config for FLASH0 */
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	      */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* max number of sectors on one chip  */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
 #define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
 #define CONFIG_SYS_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	      */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
 /* Address and size of Redundant Environment Sector */
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 /*
  * DDR SDRAM
  */
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
 #define CONFIG_ZERO_SDRAM		/* Zero SDRAM after setup	*/
 #define CONFIG_DDR_ECC			/* Use ECC when available	*/
 #define SPD_EEPROM_ADDRESS	{0x50}
 #define CONFIG_PROG_SDRAM_TLB
 #define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4 KiB as	*/
 					/* per 440EPx Errata CHIP_11	*/
 /*
  * I2C
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 #define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 /* I2C RTC */
 #define CONFIG_RTC_M41T60	1
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 /* I2C SYSMON (LM73)							*/
 #define CONFIG_DTT_LM73		1	/* National Semi's LM73		*/
 #define CONFIG_DTT_SENSORS	{2}	/* Sensor addresses		*/
 #define CONFIG_SYS_DTT_MAX_TEMP	70
 #define CONFIG_SYS_DTT_MIN_TEMP	-30
 #define CONFIG_PREBOOT	"echo;"						\
 	"echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
 	"echo"
 #undef	CONFIG_BOOTARGS
 /* Setup some board specific values for the default environment variables */
 #define CONFIG_HOSTNAME		korat
 /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"u_boot=korat/u-boot.bin\0"					\
 	"load=tftp 200000 ${u_boot}\0"					\
 	"update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;"	\
 		"cp.b ${fileaddr} F7F60000 ${filesize};protect on "	\
 		"F7F60000 F7FBFFFF\0"					\
 	"upd=run load update\0"						\
 	"bootfile=korat/uImage\0"					\
 	"dtb=korat/korat.dtb\0"						\
 	"kernel_addr=F4000000\0"					\
 	"ramdisk_addr=F4400000\0"					\
 	"dtb_addr=F41E0000\0"						\
 	"udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; "	\
 		"cp.b ${fileaddr} F4000000 ${filesize}\0"		\
 	"udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; "		\
 		"cp.b ${fileaddr} F41E0000 ${filesize}\0"		\
 	"ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; "	\
 		"tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} "	\
 		"${dtb}\0"						\
 	"rd_size=73728\0"						\
 	"ramargs=setenv bootargs root=/dev/ram rw "			\
 		"ramdisk_size=${rd_size}\0"				\
 	"usbdev=sda1\0"							\
 	"usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0"	\
 	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
 	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"pciclk=33\0"							\
 	"addide=setenv bootargs ${bootargs} ide=reverse "		\
 		"idebus=${pciclk}\0"					\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 	"flash_cf=run usbargs addide addip addtty; "			\
 		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
 	"flash_nfs=run nfsargs addide addip addtty; "			\
 		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
 	"flash_self=run ramargs addip addtty; "				\
 		"bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0"	\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_cf"
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		2	/* PHY address, See schematics	*/
 #define CONFIG_PHY_DYNAMIC_ANEG	1
 #undef CONFIG_PHY_RESET			/* Don't do software PHY reset	*/
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_HAS_ETH0
 #define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx	*/
 					/*   buffers & descriptors	*/
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_PHY1_ADDR	3
 /* USB */
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_SUBNETMASK
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_I2C
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_USB
 /* POST support */
 #define CONFIG_POST		(CONFIG_SYS_POST_CACHE	| \
 				 CONFIG_SYS_POST_CPU	| \
 				 CONFIG_SYS_POST_ECC	| \
 				 CONFIG_SYS_POST_ETHER	| \
 				 CONFIG_SYS_POST_FPU	| \
 				 CONFIG_SYS_POST_I2C	| \
 				 CONFIG_SYS_POST_MEMORY	| \
 				 CONFIG_SYS_POST_RTC	| \
 				 CONFIG_SYS_POST_SPR	| \
 				 CONFIG_SYS_POST_UART)
 #define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #define CONFIG_LOGBUFFER
 #define CONFIG_SYS_POST_CACHE_ADDR	0xC8000000	/* free virtual address     */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
 #define CONFIG_SUPPORT_VFAT
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 #define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
 #define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 					/* Print Buffer Size		*/
 #define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
 #define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 #define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO		1  /* To use extended board_into (bd_t)	*/
 #define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW		1	/* enable loopw command		*/
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable	*/
 /*
  * Korat-specific options
  */
 #define CONFIG_SYS_KORAT_MAN_RESET_MS	10000	/* timeout for manufacturer reset */
 /*
  * PCI stuff
  */
 /* General PCI */
 #define CONFIG_PCI			/* include pci support		*/
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
 #define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
 						/*   CONFIG_SYS_PCI_MEMBASE	*/
 /* Board-specific PCI */
 #define CONFIG_SYS_PCI_TARGET_INIT
 #define CONFIG_SYS_PCI_MASTER_INIT
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
 #define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
 /*
  * For booting Linux, the board info and command line data have to be in the
  * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
  * during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 /*
  * External Bus Controller (EBC) Setup
  */
 /* Memory Bank 0 (NOR-FLASH) initialization				*/
 #if CONFIG_SYS_FLASH0_SIZE == 0x01000000
 #define CONFIG_SYS_EBC_PB0AP		0x04017300
 #define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
 #elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
 #define CONFIG_SYS_EBC_PB0AP		0x04017300
 #define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
 #else
 #error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
 #endif
 /* Memory Bank 1 (NOR-FLASH) initialization				*/
 #if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
 #define CONFIG_SYS_EBC_PB1AP		0x04017300
 #define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
 #else
 #error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
 #endif
 /* Memory Bank 2 (CPLD) initialization					*/
 #define CONFIG_SYS_EBC_PB2AP		0x04017300
 #define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_CPLD_BASE | 0x00038000)
 /*
  * GPIO Setup
  *
  * Korat GPIO usage:
  *
  *                   Init.
  * Pin    Source I/O value Function
  * ------ ------ --- ----- ---------------------------------
  * GPIO00  Alt1  I/O   x   PerAddr07
  * GPIO01  Alt1  I/O   x   PerAddr06
  * GPIO02  Alt1  I/O   x   PerAddr05
  * GPIO03  GPIO   x    x   GPIO03 to expansion bus connector
  * GPIO04  GPIO   x    x   GPIO04 to expansion bus connector
  * GPIO05  GPIO   x    x   GPIO05 to expansion bus connector
  * GPIO06  Alt1   O    x   PerCS1 (2nd NOR flash)
  * GPIO07  Alt1   O    x   PerCS2 (CPLD)
  * GPIO08  Alt1   O    x   PerCS3 to expansion bus connector
  * GPIO09  Alt1   O    x   PerCS4 to expansion bus connector
  * GPIO10  Alt1   O    x   PerCS5 to expansion bus connector
  * GPIO11  Alt1   I    x   PerErr
  * GPIO12  GPIO   O    0   ATMega !Reset
  * GPIO13  GPIO   x    x   Test Point 2 (TP2)
  * GPIO14  GPIO   O    1   Write protect EEPROM #1 (0xA8)
  * GPIO15  GPIO   O    0   CPU Run LED !On
  * GPIO16  Alt1   O    x   GMC1TxD0
  * GPIO17  Alt1   O    x   GMC1TxD1
  * GPIO18  Alt1   O    x   GMC1TxD2
  * GPIO19  Alt1   O    x   GMC1TxD3
  * GPIO20  Alt1   I    x   RejectPkt0
  * GPIO21  Alt1   I    x   RejectPkt1
  * GPIO22  GPIO   I    x   PGOOD_DDR
  * GPIO23  Alt1   O    x   SCPD0
  * GPIO24  Alt1   O    x   GMC0TxD2
  * GPIO25  Alt1   O    x   GMC0TxD3
  * GPIO26  GPIO? I/O   x   IIC0SDA (selected in SDR0_PFC4)
  * GPIO27  GPIO   O    0   PHY #0 1000BASE-X select
  * GPIO28  GPIO   O    0   PHY #1 1000BASE-X select
  * GPIO29  GPIO   I    x   Test jumper !Present
  * GPIO30  GPIO   I    x   SFP module #0 !Present
  * GPIO31  GPIO   I    x   SFP module #1 !Present
  *
  * GPIO32  GPIO   O    1   SFP module #0 Tx !Enable
  * GPIO33  GPIO   O    1   SFP module #1 Tx !Enable
  * GPIO34  Alt2   I    x   !UART1_CTS
  * GPIO35  Alt2   O    x   !UART1_RTS
  * GPIO36  Alt1   I    x   !UART0_CTS
  * GPIO37  Alt1   O    x   !UART0_RTS
  * GPIO38  Alt2   O    x   UART1_Tx
  * GPIO39  Alt2   I    x   UART1_Rx
  * GPIO40  Alt1   I    x   IRQ0 (Ethernet 0)
  * GPIO41  Alt1   I    x   IRQ1 (Ethernet 1)
  * GPIO42  Alt1   I    x   IRQ2 (PCI interrupt)
  * GPIO43  Alt1   I    x   IRQ3 (System Alert from CPLD)
  * GPIO44  xxxx   x    x   (grounded through pulldown)
  * GPIO45  GPIO   O    0   PHY #0 Enable
  * GPIO46  GPIO   O    0   PHY #1 Enable
  * GPIO47  GPIO   I    x   Reset switch !Pressed
  * GPIO48  GPIO   I    x   Shutdown switch !Pressed
  * GPIO49  xxxx   x    x   (reserved for trace port)
  *   .      .     .    .               .
  *   .      .     .    .               .
  *   .      .     .    .               .
  * GPIO63  xxxx   x    x   (reserved for trace port)
  */
 #define CONFIG_SYS_GPIO_ATMEGA_RESET_	12
 #define CONFIG_SYS_GPIO_ATMEGA_SS_	13
 #define CONFIG_SYS_GPIO_PHY0_FIBER_SEL	27
 #define CONFIG_SYS_GPIO_PHY1_FIBER_SEL	28
 #define CONFIG_SYS_GPIO_SFP0_PRESENT_	30
 #define CONFIG_SYS_GPIO_SFP1_PRESENT_	31
 #define CONFIG_SYS_GPIO_SFP0_TX_EN_	32
 #define CONFIG_SYS_GPIO_SFP1_TX_EN_	33
 #define CONFIG_SYS_GPIO_PHY0_EN	45
 #define CONFIG_SYS_GPIO_PHY1_EN	46
 #define CONFIG_SYS_GPIO_RESET_PRESSED_	47
 /*
  * PPC440 GPIO Configuration
  */
 #define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)			*/	\
 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)			*/	\
 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28		USB2D_TXVALID	*/	\
 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
 },											\
 {											\
 /* GPIO Core 1 */									\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \
 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
 }											\
 }
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02	/* Software reboot			*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400 /* speed to run kgdb serial port	*/
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
 #endif
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #endif /* __CONFIG_H */

include/configs/sbc8349.h

Diff comments View file @ d48eb51

 /*
  * WindRiver SBC8349 U-Boot configuration file.
  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
  *
  * Paul Gortmaker <paul.gortmaker@windriver.com>
  * Based on the MPC8349EMDS config.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * sbc8349 board configuration file.
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC83XX		1	/* MPC83XX family */
 #define CONFIG_MPC834X		1	/* MPC834X family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_SBC8349		1	/* WRS SBC8349 board specific */
 #undef CONFIG_PCI
 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
 #define PCI_66M
 #ifdef PCI_66M
 #define CONFIG_83XX_CLKIN	66000000	/* in Hz */
 #else
 #define CONFIG_83XX_CLKIN	33000000	/* in Hz */
 #endif
 #ifndef CONFIG_SYS_CLK_FREQ
 #ifdef PCI_66M
 #define CONFIG_SYS_CLK_FREQ	66000000
 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
 #else
 #define CONFIG_SYS_CLK_FREQ	33000000
 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
 #endif
 #endif
 #undef CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 #define CONFIG_SYS_IMMR		0xE0000000
 #undef CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x00100000
 /*
  * DDR Setup
  */
 #undef CONFIG_DDR_ECC			/* only for ECC DDR module */
 #undef CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 #define CONFIG_SYS_83XX_DDR_USES_CS0		/* WRS; Fsl board uses CS2/CS3 */
 /*
  * 32-bit data path mode.
  *
  * Please note that using this mode for devices with the real density of 64-bit
  * effectively reduces the amount of available memory due to the effect of
  * wrapping around while translating address to row/columns, for example in the
  * 256MB module the upper 128MB get aliased with contents of the lower
  * 128MB); normally this define should be used for devices with real 32-bit
  * data path.
  */
 #undef CONFIG_DDR_32BIT
 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING
 #if defined(CONFIG_SPD_EEPROM)
 /*
  * Determine DDR configuration from I2C interface.
  */
 #define SPD_EEPROM_ADDRESS	0x52		/* DDR DIMM */
 #else
 /*
  * Manually set up DDR parameters
  * NB: manual DDR setup untested on sbc834x
  */
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
 #define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_1	0x36332321
 #define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
 #define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
 #define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
 #if defined(CONFIG_DDR_32BIT)
 /* set burst length to 8 for 32-bit data path */
 #define CONFIG_SYS_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
 #else
 /* the default burst length is 4 - for 64-bit data path */
 #define CONFIG_SYS_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
 #endif
 #endif
 /*
  * SDRAM on the Local Bus
  */
 #define CONFIG_SYS_LBC_SDRAM_BASE	0x10000000	/* Localbus SDRAM */
 #define CONFIG_SYS_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		8		/* flash size in MB */
 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE |	/* flash Base address */ \
 				(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
 				BR_V)			/* valid */
 #define CONFIG_SYS_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* window base at flash base */
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MID_FLASH_JUMP	0x7F000000
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef  CONFIG_SYS_RAMBOOT
 #endif
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000			/* End of used area in RAM*/
 #define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
 /*
  * Local Bus LCRR and LBCR regs
  *    LCRR:  DLL bypass, Clock divider is 4
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
 #define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
 #ifdef CONFIG_SYS_LB_SDRAM
 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  *    port-size = 32-bits = BR2[19:20] = 11
  *    no parity checking = BR2[21:22] = 00
  *    SDRAM for MSEL = BR2[24:26] = 011
  *    Valid = BR[31] = 1
  *
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  *
  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 #define CONFIG_SYS_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 #define CONFIG_SYS_LBLAWBAR2_PRELIM	0xF0000000
 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019 /* 64M */
 /*
  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
  *                 XAM, OR2[17:18] = 11
  *    9 columns OR2[19-21] = 010
  *    13 rows   OR2[23-25] = 100
  *    EAD set for extra time OR[31] = 1
  *
  * 0    4    8    12   16   20   24   28
  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  */
 #define CONFIG_SYS_OR2_PRELIM	0xFC006901
 #define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 #define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
 				| LSDMR_BSMA1516	\
 				| LSDMR_RFCR8		\
 				| LSDMR_PRETOACT6	\
 				| LSDMR_ACTTORW3	\
 				| LSDMR_BL8		\
 				| LSDMR_WRC3		\
 				| LSDMR_CL3		\
 				)
 /*
  * SDRAM Controller configuration sequence.
  */
 #define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 #define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 #define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 #define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 #define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 #endif
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX     1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CONFIG_FSL_I2C
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
 #define CONFIG_SYS_I2C1_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 #define CONFIG_SYS_I2C_OFFSET		CONFIG_SYS_I2C2_OFFSET
 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
 /* TSEC */
 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 #define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
 #define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
 #define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS	0xE2100000
 #define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
 #if defined(CONFIG_PCI)
 #define PCI_64BIT
 #define PCI_ONE_PCI1
 #if defined(PCI_64BIT)
 #undef PCI_ALL_PCI1
 #undef PCI_TWO_PCI1
 #undef PCI_ONE_PCI1
 #endif
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 #if !defined(CONFIG_PCI_PNP)
 	#define PCI_ENET0_IOADDR	0xFIXME
 	#define PCI_ENET0_MEMADDR	0xFIXME
 	#define PCI_IDSEL_NUMBER	0xFIXME
 #endif
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 #endif	/* CONFIG_PCI */
 /*
  * TSEC configuration
  */
 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
 #if defined(CONFIG_TSEC_ENET)
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
 #endif
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"TSEC1"
 #define CONFIG_PHY_BCM5421S	1
 #define TSEC1_PHY_ADDR		0x19
 #define TSEC2_PHY_ADDR		0x1a
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC2_FLAGS		TSEC_GIGABIT
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"TSEC0"
 #endif	/* CONFIG_TSEC_ENET */
 /*
  * Environment
  */
 #ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #else
 	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
 #endif
 #if defined(CONFIG_SYS_RAMBOOT)
     #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
 	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 #if 1 /*528/264*/
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X2 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*396/132*/
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_3X1)
 #elif 0 /*264/132*/
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*132/132*/
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_1X1)
 #elif 0 /*264/264 */
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_1X1)
 #endif
 #if defined(PCI_64BIT)
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_64_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCI2_ARBITER_DISABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCI2_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT |\
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #endif
 /* System IO Config */
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
 /* #define CONFIG_SYS_HID0_FINAL		(\
 	HID0_ENABLE_INSTRUCTION_CACHE |\
 	HID0_ENABLE_M_BIT |\
 	HID0_ENABLE_ADDRESS_BROADCAST ) */
 #define CONFIG_SYS_HID2 HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /* DDR @ 0x00000000 */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 /* PCI @ 0x80000000 */
 #ifdef CONFIG_PCI
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT1L	(0)
 #define CONFIG_SYS_IBAT1U	(0)
 #define CONFIG_SYS_IBAT2L	(0)
 #define CONFIG_SYS_IBAT2U	(0)
 #endif
 #ifdef CONFIG_MPC83XX_PCI2
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT3L	(0)
 #define CONFIG_SYS_IBAT3U	(0)
 #define CONFIG_SYS_IBAT4L	(0)
 #define CONFIG_SYS_IBAT4U	(0)
 #endif
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 				 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT7L	(0)
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02	/* Software reboot */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR		00:a0:1e:a0:13:8d
 #define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:a0:1e:a0:13:8e
 #endif
 #define CONFIG_IPADDR		192.168.1.234
 #define CONFIG_HOSTNAME		SBC8349
 #define CONFIG_ROOTPATH		/tftpboot/rootfs
 #define CONFIG_BOOTFILE		uImage
 #define CONFIG_SERVERIP		192.168.1.1
 #define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
 #define CONFIG_BAUDRATE	 115200
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"hostname=sbc8349\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 	"flash_nfs=run nfsargs addip addtty;"				\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip addtty;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
 		"bootm\0"						\
 	"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"		\
 	"update=protect off fff00000 fff3ffff; "			\
 		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0"	\
 	"upd=run load update\0"						\
 	"fdtaddr=400000\0"						\
 	"fdtfile=sbc8349.dtb\0"						\
 	""
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
       "nfsroot=$serverip:$rootpath "                                    \
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
    "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr - $fdtaddr"
 #define CONFIG_RAMBOOTCOMMAND						\
    "setenv bootargs root=/dev/ram rw "                                  \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $ramdiskaddr $ramdiskfile;"                                    \
    "tftp $loadaddr $bootfile;"                                          \
    "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 #endif	/* __CONFIG_H */

include/configs/socrates.h

Diff comments View file @ d48eb51

 /*
  * (C) Copyright 2008
  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  *
  * Wolfgang Denk <wd@denx.de>
  * Copyright 2004 Freescale Semiconductor.
  * (C) Copyright 2002,2003 Motorola,Inc.
  * Xianghua Xiao <X.Xiao@motorola.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * Socrates
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /* new uImage format support */
 #define CONFIG_FIT		1
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE			*/
 #define CONFIG_E500		1	/* BOOKE e500 family		*/
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
 #define CONFIG_MPC8544		1
 #define CONFIG_SOCRATES		1
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
 #define CONFIG_BOARD_EARLY_INIT_R 1	/* Call board_early_init_r	*/
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 /*
  * sysclk for MPC85xx
  *
  * Two valid values are:
  *    33000000
  *    66000000
  *
  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  * is likely the desired value here, so that is now the default.
  * The board, however, can run at 66MHz.  In any event, this value
  * must match the settings of some switches.  Details can be found
  * in the README.mpc85xxads.
  */
 #ifndef CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_CLK_FREQ	66666666
 #endif
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache		*/
 #define CONFIG_BTB			/* toggle branch predition	*/
 #define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
 #undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time	*/
 #define CONFIG_SYS_MEMTEST_START	0x00400000
 #define CONFIG_SYS_MEMTEST_END		0x00C00000
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
 #define CONFIG_SYS_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x50	/* CTLR 0 DIMM 0 */
 #define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
 /* Hardcoded values, to use instead of SPD */
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
 #define CONFIG_SYS_DDR_CS0_CONFIG		0x80010102
 #define CONFIG_SYS_DDR_TIMING_0		0x00260802
 #define CONFIG_SYS_DDR_TIMING_1		0x3935D322
 #define CONFIG_SYS_DDR_TIMING_2		0x14904CC8
 #define CONFIG_SYS_DDR_MODE			0x00480432
 #define CONFIG_SYS_DDR_INTERVAL		0x030C0100
 #define CONFIG_SYS_DDR_CONFIG_2		0x04400000
 #define CONFIG_SYS_DDR_CONFIG			0xC3008000
 #define CONFIG_SYS_DDR_CLK_CONTROL		0x03800000
 #define CONFIG_SYS_SDRAM_SIZE			256 /* in Megs */
 /*
  * Flash on the LocalBus
  */
 #define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
 #define CONFIG_SYS_FLASH0		0xFE000000
 #define CONFIG_SYS_FLASH1		0xFC000000
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 #define CONFIG_SYS_LBC_FLASH_BASE	CONFIG_SYS_FLASH1	/* Localbus flash start	*/
 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH	*/
 #define CONFIG_SYS_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
 #define CONFIG_SYS_OR0_PRELIM		0xfe000030	/* 32MB Flash		*/
 #define CONFIG_SYS_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
 #define CONFIG_SYS_OR1_PRELIM		0xfe000030	/* 32MB Flash		*/
 #define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks	*/
 #define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device	*/
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 #define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
 #define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg		*/
 #define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
 #define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End used area in RAM	*/
 #define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data*/
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */
 /* FPGA and NAND */
 #define CONFIG_SYS_FPGA_BASE		0xc0000000
 #define CONFIG_SYS_FPGA_SIZE		0x00100000	/* 1 MB		*/
 #define CONFIG_SYS_HMI_BASE		0xc0010000
 #define CONFIG_SYS_BR3_PRELIM		0xc0001881	/* UPMA, 32-bit */
 #define CONFIG_SYS_OR3_PRELIM		0xfff00000	/* 1 MB 	*/
 #define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_FPGA_BASE + 0x70)
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_CMD_NAND
 /* LIME GDC */
 #define CONFIG_SYS_LIME_BASE		0xc8000000
 #define CONFIG_SYS_LIME_SIZE		0x04000000	/* 64 MB	*/
 #define CONFIG_SYS_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
 #define CONFIG_SYS_OR2_PRELIM		0xfc000000	/* 64 MB	*/
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_MB862xx
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define VIDEO_FB_16BPP_PIXEL_SWAP
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 #define CONFIG_BAUDRATE         115200
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 /*
  * I2C
  */
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CONFIG_SYS_I2C_SPEED		102124	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 /* I2C RTC */
 #define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
 #define CONFIG_SYS_I2C_RTC_ADDR	0x32	/* at address 0x32		*/
 /* I2C W83782G HW-Monitoring IC */
 #define CONFIG_SYS_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/
 /* I2C temp sensor */
 /* Socrates uses Maxim's	DS75, which is compatible with LM75 */
 #define CONFIG_DTT_LM75		1
 #define CONFIG_DTT_SENSORS	{4}		/* Sensor addresses	*/
 #define CONFIG_SYS_DTT_MAX_TEMP	125
 #define CONFIG_SYS_DTT_LOW_TEMP	-55
 #define CONFIG_SYS_DTT_HYSTERESIS	3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
 /*
  * General PCI
  * Memory space is mapped 1-1.
  */
 #define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
 /* PCI is clocked by the external source at 33 MHz */
 #define CONFIG_PCI_CLK_FREQ	33000000
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
 #define CONFIG_SYS_PCI1_IO_BASE	0xE2000000
 #define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
 #define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M			*/
 #if defined(CONFIG_PCI)
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
 #endif	/* CONFIG_PCI */
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC3_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC3_FLAGS		TSEC_GIGABIT
 /* Options are: TSEC[0,1] */
 #define CONFIG_ETHPRIME		"TSEC0"
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x4000
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 #define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_BMP
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
 #endif
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address		*/
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
     #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size	*/
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks	*/
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01		/* Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02		/* Software reboot		*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
 #endif
 #define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
 #define CONFIG_BOOTDELAY 1		/* -1 disables auto-boot	*/
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Welcome on the ABB Socrates Board;" \
 	"echo"
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"consdev=ttyS0\0"						\
 	"uboot_file=/home/tftp/syscon3/u-boot.bin\0"			\
 	"bootfile=/home/tftp/syscon3/uImage\0"				\
 	"fdt_file=/home/tftp/syscon3/socrates.dtb\0"			\
 	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0"			\
 	"uboot_addr=FFFA0000\0"						\
 	"kernel_addr=FE000000\0"					\
 	"fdt_addr=FE1E0000\0"						\
 	"ramdisk_addr=FE200000\0"					\
 	"fdt_addr_r=B00000\0"						\
 	"kernel_addr_r=200000\0"					\
 	"ramdisk_addr_r=400000\0"					\
 	"rootpath=/opt/eldk/ppc_85xxDP\0"				\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=$serverip:$rootpath\0"				\
 	"addcons=setenv bootargs $bootargs "				\
 		"console=$consdev,$baudrate\0"				\
 	"addip=setenv bootargs $bootargs "				\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
 		":$hostname:$netdev:off panic=1\0"			\
 	"boot_nor=run ramargs addcons;"					\
 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
 	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
 		"tftp ${fdt_addr_r} ${fdt_file}; "			\
 		"run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
 	"update_uboot=tftp 100000 ${uboot_file};"			\
 		"protect off fffa0000 ffffffff;"			\
 		"era fffa0000 ffffffff;"				\
 		"cp.b 100000 fffa0000 ${filesize};"			\
 		"setenv filesize;saveenv\0"				\
 	"update_kernel=tftp 100000 ${bootfile};"			\
 		"era fe000000 fe1dffff;"				\
 		"cp.b 100000 fe000000 ${filesize};"			\
 		"setenv filesize;saveenv\0"				\
 	"update_fdt=tftp 100000 ${fdt_file};" 				\
 		"era fe1e0000 fe1fffff;"				\
 		"cp.b 100000 fe1e0000 ${filesize};"			\
 		"setenv filesize;saveenv\0"				\
 	"update_initrd=tftp 100000 ${initrd_file};" 			\
 		"era fe200000 fe9fffff;"				\
 		"cp.b 100000 fe200000 ${filesize};"			\
 		"setenv filesize;saveenv\0"				\
 	"clean_data=era fea00000 fff5ffff\0"				\
 	"usbargs=setenv bootargs root=/dev/sda1 rw\0" 			\
 	"load_usb=usb start;" 						\
 		"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"	\
 	"boot_usb=run load_usb usbargs addcons;"			\
 		"bootm ${kernel_addr_r} - ${fdt_addr};"			\
 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
 	""
 #define CONFIG_BOOTCOMMAND	"run boot_nor"
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 /* USB support */
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_PCI_OHCI			1
 #define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
 #define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
 #define CONFIG_DOS_PARTITION		1
 #define CONFIG_USB_STORAGE		1
 #endif	/* __CONFIG_H */