Eric Lee / smarc-uboot | Embedian Git Server

Commit d5243359e1afc957acd373dbbde1cf6c70ee5485

Authored by Hannes Petermaier 2014-02-04 04:22:18 +0800

Committed by Heiko Schocher 2014-02-20 13:48:23 +0800

Exists in master and in 49 other branches

OMAP24xx I2C: Add support for set-speed

Adds support for set-speed on the OMAP24xx I2C Adapter.

Changes to omap24_i2c_write(...) for polling ARDY Bit from IRQ-Status.
Otherwise on a subsequent call the transfer of last byte from the
predecessor is aborted and therefore lost. For exmaple when
i2c_write(...) is followed by a i2c_setspeed(...) (which has to
deactivate and activate master for changing psc,...).

Minor cosmetical changes.

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Heiko Schocher <hs@denx.de>

Showing 2 changed files with 98 additions and 50 deletions Inline Diff

drivers/i2c/omap24xx_i2c.c
include/i2c.h

drivers/i2c/omap24xx_i2c.c

Diff comments View file @ d524335

1	/*	1	/*
2	* Basic I2C functions	2	* Basic I2C functions
3	*	3	*
4	* Copyright (c) 2004 Texas Instruments	4	* Copyright (c) 2004 Texas Instruments
5	*	5	*
6	* This package is free software; you can redistribute it and/or	6	* This package is free software; you can redistribute it and/or
7	* modify it under the terms of the license found in the file	7	* modify it under the terms of the license found in the file
8	* named COPYING that should have accompanied this file.	8	* named COPYING that should have accompanied this file.
9	*	9	*
10	* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR	10	* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11	* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED	11	* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12	* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.	12	* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13	*	13	*
14	* Author: Jian Zhang jzhang@ti.com, Texas Instruments	14	* Author: Jian Zhang jzhang@ti.com, Texas Instruments
15	*	15	*
16	* Copyright (c) 2003 Wolfgang Denk, wd@denx.de	16	* Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17	* Rewritten to fit into the current U-Boot framework	17	* Rewritten to fit into the current U-Boot framework
18	*	18	*
19	* Adapted for OMAP2420 I2C, r-woodruff2@ti.com	19	* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20	*	20	*
21	* Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions	21	* Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22	* New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4	22	* New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23	* (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older	23	* (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24	* OMAPs and derivatives as well. The only anticipated exception would	24	* OMAPs and derivatives as well. The only anticipated exception would
25	* be the OMAP2420, which shall require driver modification.	25	* be the OMAP2420, which shall require driver modification.
26	* - Rewritten i2c_read to operate correctly with all types of chips	26	* - Rewritten i2c_read to operate correctly with all types of chips
27	* (old function could not read consistent data from some I2C slaves).	27	* (old function could not read consistent data from some I2C slaves).
28	* - Optimized i2c_write.	28	* - Optimized i2c_write.
29	* - New i2c_probe, performs write access vs read. The old probe could	29	* - New i2c_probe, performs write access vs read. The old probe could
30	* hang the system under certain conditions (e.g. unconfigured pads).	30	* hang the system under certain conditions (e.g. unconfigured pads).
31	* - The read/write/probe functions try to identify unconfigured bus.	31	* - The read/write/probe functions try to identify unconfigured bus.
32	* - Status functions now read irqstatus_raw as per TRM guidelines	32	* - Status functions now read irqstatus_raw as per TRM guidelines
33	* (except for OMAP243X and OMAP34XX).	33	* (except for OMAP243X and OMAP34XX).
34	* - Driver now supports up to I2C5 (OMAP5).	34	* - Driver now supports up to I2C5 (OMAP5).
		35	*
		36	* Copyright (c) 2014 Hannes Petermaier <oe5hpm@oevsv.at>, B&R
		37	* - Added support for set_speed
		38	*
35	*/	39	*/
36		40
37	#include <common.h>	41	#include <common.h>
38	#include <i2c.h>	42	#include <i2c.h>
39		43
40	#include <asm/arch/i2c.h>	44	#include <asm/arch/i2c.h>
41	#include <asm/io.h>	45	#include <asm/io.h>
42		46
43	#include "omap24xx_i2c.h"	47	#include "omap24xx_i2c.h"
44		48
45	DECLARE_GLOBAL_DATA_PTR;	49	DECLARE_GLOBAL_DATA_PTR;
46		50
47	#define I2C_TIMEOUT 1000	51	#define I2C_TIMEOUT 1000
48		52
49	/* Absolutely safe for status update at 100 kHz I2C: */	53	/* Absolutely safe for status update at 100 kHz I2C: */
50	#define I2C_WAIT 200	54	#define I2C_WAIT 200
51		55
52	static int wait_for_bb(struct i2c_adapter *adap);	56	static int wait_for_bb(struct i2c_adapter *adap);
53	static struct i2c omap24_get_base(struct i2c_adapter adap);	57	static struct i2c omap24_get_base(struct i2c_adapter adap);
54	static u16 wait_for_event(struct i2c_adapter *adap);	58	static u16 wait_for_event(struct i2c_adapter *adap);
55	static void flush_fifo(struct i2c_adapter *adap);	59	static void flush_fifo(struct i2c_adapter *adap);
		60	static int omap24_i2c_findpsc(u32 pscl, u32 psch, uint speed)
		61	{
		62	unsigned int sampleclk, prescaler;
		63	int fsscll, fssclh;
56		64
57	static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)	65	speed <<= 1;
		66	prescaler = 0;
		67	/*
		68	* some divisors may cause a precission loss, but shouldn't
		69	* be a big thing, because i2c_clk is then allready very slow.
		70	*/
		71	while (prescaler <= 0xFF) {
		72	sampleclk = I2C_IP_CLK / (prescaler+1);
		73
		74	fsscll = sampleclk / speed;
		75	fssclh = fsscll;
		76	fsscll -= I2C_FASTSPEED_SCLL_TRIM;
		77	fssclh -= I2C_FASTSPEED_SCLH_TRIM;
		78
		79	if (((fsscll > 0) && (fssclh > 0)) &&
		80	((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
		81	(fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) {
		82	if (pscl)
		83	*pscl = fsscll;
		84	if (psch)
		85	*psch = fssclh;
		86
		87	return prescaler;
		88	}
		89	prescaler++;
		90	}
		91	return -1;
		92	}
		93	static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
58	{	94	{
59	struct i2c *i2c_base = omap24_get_base(adap);	95	struct i2c *i2c_base = omap24_get_base(adap);
60	int psc, fsscll, fssclh;	96	int psc, fsscll = 0, fssclh = 0;
61	int hsscll = 0, hssclh = 0;	97	int hsscll = 0, hssclh = 0;
62	u32 scll, sclh;	98	u32 scll = 0, sclh = 0;
63	int timeout = I2C_TIMEOUT;
64		99
65	/* Only handle standard, fast and high speeds */	100	if (speed >= OMAP_I2C_HIGH_SPEED) {
66	if ((speed != OMAP_I2C_STANDARD) &&
67	(speed != OMAP_I2C_FAST_MODE) &&
68	(speed != OMAP_I2C_HIGH_SPEED)) {
69	printf("Error : I2C unsupported speed %d\n", speed);
70	return;
71	}
72
73	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
74	psc -= 1;
75	if (psc < I2C_PSC_MIN) {
76	printf("Error : I2C unsupported prescalar %d\n", psc);
77	return;
78	}
79
80	if (speed == OMAP_I2C_HIGH_SPEED) {
81	/* High speed */	101	/* High speed */
		102	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
		103	psc -= 1;
		104	if (psc < I2C_PSC_MIN) {
		105	printf("Error : I2C unsupported prescaler %d\n", psc);
		106	return -1;
		107	}
82		108
83	/* For first phase of HS mode */	109	/* For first phase of HS mode */
84	fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /	110	fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
85	(2 * OMAP_I2C_FAST_MODE);
86		111
		112	fssclh = fsscll;
		113
87	fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;	114	fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
88	fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;	115	fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
89	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|	116	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
90	((fsscll > 255) \|\| (fssclh > 255))) {	117	((fsscll > 255) \|\| (fssclh > 255))) {
91	puts("Error : I2C initializing first phase clock\n");	118	puts("Error : I2C initializing first phase clock\n");
92	return;	119	return -1;
93	}	120	}
94		121
95	/* For second phase of HS mode */	122	/* For second phase of HS mode */
96	hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);	123	hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
97		124
98	hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;	125	hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
99	hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;	126	hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
100	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|	127	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
101	((fsscll > 255) \|\| (fssclh > 255))) {	128	((fsscll > 255) \|\| (fssclh > 255))) {
102	puts("Error : I2C initializing second phase clock\n");	129	puts("Error : I2C initializing second phase clock\n");
103	return;	130	return -1;
104	}	131	}
105		132
106	scll = (unsigned int)hsscll << 8 \| (unsigned int)fsscll;	133	scll = (unsigned int)hsscll << 8 \| (unsigned int)fsscll;
107	sclh = (unsigned int)hssclh << 8 \| (unsigned int)fssclh;	134	sclh = (unsigned int)hssclh << 8 \| (unsigned int)fssclh;
108		135
109	} else {	136	} else {
110	/* Standard and fast speed */	137	/* Standard and fast speed */
111	fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);	138	psc = omap24_i2c_findpsc(&scll, &sclh, speed);
112		139	if (0 > psc) {
113	fsscll -= I2C_FASTSPEED_SCLL_TRIM;
114	fssclh -= I2C_FASTSPEED_SCLH_TRIM;
115	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
116	((fsscll > 255) \|\| (fssclh > 255))) {
117	puts("Error : I2C initializing clock\n");	140	puts("Error : I2C initializing clock\n");
118	return;	141	return -1;
119	}	142	}
120
121	scll = (unsigned int)fsscll;
122	sclh = (unsigned int)fssclh;
123	}	143	}
124		144
		145	adap->speed = speed;
		146	adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
		147	writew(0, &i2c_base->con);
		148	writew(psc, &i2c_base->psc);
		149	writew(scll, &i2c_base->scll);
		150	writew(sclh, &i2c_base->sclh);
		151	writew(I2C_CON_EN, &i2c_base->con);
		152	writew(0xFFFF, &i2c_base->stat); /* clear all pending status */
		153
		154	return 0;
		155	}
		156	static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
		157	{
		158	struct i2c *i2c_base = omap24_get_base(adap);
		159	int timeout = I2C_TIMEOUT;
		160
125	if (readw(&i2c_base->con) & I2C_CON_EN) {	161	if (readw(&i2c_base->con) & I2C_CON_EN) {
126	writew(0, &i2c_base->con);	162	writew(0, &i2c_base->con);
127	udelay(50000);	163	udelay(50000);
128	}	164	}
129		165
130	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */	166	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
131	udelay(1000);	167	udelay(1000);
132		168
133	writew(I2C_CON_EN, &i2c_base->con);	169	writew(I2C_CON_EN, &i2c_base->con);
134	while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {	170	while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
135	if (timeout <= 0) {	171	if (timeout <= 0) {
136	puts("ERROR: Timeout in soft-reset\n");	172	puts("ERROR: Timeout in soft-reset\n");
137	return;	173	return;
138	}	174	}
139	udelay(1000);	175	udelay(1000);
140	}	176	}
141		177
142	writew(0, &i2c_base->con);	178	if (0 != omap24_i2c_setspeed(adap, speed)) {
143	writew(psc, &i2c_base->psc);	179	printf("ERROR: failed to setup I2C bus-speed!\n");
144	writew(scll, &i2c_base->scll);	180	return;
145	writew(sclh, &i2c_base->sclh);	181	}
146		182
147	/* own address */	183	/* own address */
148	writew(slaveadd, &i2c_base->oa);	184	writew(slaveadd, &i2c_base->oa);
149	writew(I2C_CON_EN, &i2c_base->con);	185
150	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX)	186	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX)
151	/*	187	/*
152	* Have to enable interrupts for OMAP2/3, these IPs don't have	188	* Have to enable interrupts for OMAP2/3, these IPs don't have
153	* an 'irqstatus_raw' register and we shall have to poll 'stat'	189	* an 'irqstatus_raw' register and we shall have to poll 'stat'
154	*/	190	*/
155	writew(I2C_IE_XRDY_IE \| I2C_IE_RRDY_IE \| I2C_IE_ARDY_IE \|	191	writew(I2C_IE_XRDY_IE \| I2C_IE_RRDY_IE \| I2C_IE_ARDY_IE \|
156	I2C_IE_NACK_IE \| I2C_IE_AL_IE, &i2c_base->ie);	192	I2C_IE_NACK_IE \| I2C_IE_AL_IE, &i2c_base->ie);
157	#endif	193	#endif
158	udelay(1000);	194	udelay(1000);
159	flush_fifo(adap);	195	flush_fifo(adap);
160	writew(0xFFFF, &i2c_base->stat);	196	writew(0xFFFF, &i2c_base->stat);
161	}	197	}
162		198
163	static void flush_fifo(struct i2c_adapter *adap)	199	static void flush_fifo(struct i2c_adapter *adap)
164	{	200	{
165	struct i2c *i2c_base = omap24_get_base(adap);	201	struct i2c *i2c_base = omap24_get_base(adap);
166	u16 stat;	202	u16 stat;
167		203
168	/* note: if you try and read data when its not there or ready	204	/*
		205	* note: if you try and read data when its not there or ready
169	* you get a bus error	206	* you get a bus error
170	*/	207	*/
171	while (1) {	208	while (1) {
172	stat = readw(&i2c_base->stat);	209	stat = readw(&i2c_base->stat);
173	if (stat == I2C_STAT_RRDY) {	210	if (stat == I2C_STAT_RRDY) {
174	readb(&i2c_base->data);	211	readb(&i2c_base->data);
175	writew(I2C_STAT_RRDY, &i2c_base->stat);	212	writew(I2C_STAT_RRDY, &i2c_base->stat);
176	udelay(1000);	213	udelay(1000);
177	} else	214	} else
178	break;	215	break;
179	}	216	}
180	}	217	}
181		218
182	/*	219	/*
183	* i2c_probe: Use write access. Allows to identify addresses that are	220	* i2c_probe: Use write access. Allows to identify addresses that are
184	* write-only (like the config register of dual-port EEPROMs)	221	* write-only (like the config register of dual-port EEPROMs)
185	*/	222	*/
186	static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)	223	static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
187	{	224	{
188	struct i2c *i2c_base = omap24_get_base(adap);	225	struct i2c *i2c_base = omap24_get_base(adap);
189	u16 status;	226	u16 status;
190	int res = 1; /* default = fail */	227	int res = 1; /* default = fail */
191		228
192	if (chip == readw(&i2c_base->oa))	229	if (chip == readw(&i2c_base->oa))
193	return res;	230	return res;
194		231
195	/* Wait until bus is free */	232	/* Wait until bus is free */
196	if (wait_for_bb(adap))	233	if (wait_for_bb(adap))
197	return res;	234	return res;
198		235
199	/* No data transfer, slave addr only */	236	/* No data transfer, slave addr only */
200	writew(chip, &i2c_base->sa);	237	writew(chip, &i2c_base->sa);
201	/* Stop bit needed here */	238	/* Stop bit needed here */
202	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX \|	239	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX \|
203	I2C_CON_STP, &i2c_base->con);	240	I2C_CON_STP, &i2c_base->con);
204		241
205	status = wait_for_event(adap);	242	status = wait_for_event(adap);
206		243
207	if ((status & ~I2C_STAT_XRDY) == 0 \|\| (status & I2C_STAT_AL)) {	244	if ((status & ~I2C_STAT_XRDY) == 0 \|\| (status & I2C_STAT_AL)) {
208	/*	245	/*
209	* With current high-level command implementation, notifying	246	* With current high-level command implementation, notifying
210	* the user shall flood the console with 127 messages. If	247	* the user shall flood the console with 127 messages. If
211	* silent exit is desired upon unconfigured bus, remove the	248	* silent exit is desired upon unconfigured bus, remove the
212	* following 'if' section:	249	* following 'if' section:
213	*/	250	*/
214	if (status == I2C_STAT_XRDY)	251	if (status == I2C_STAT_XRDY)
215	printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",	252	printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
216	adap->hwadapnr, status);	253	adap->hwadapnr, status);
217		254
218	goto pr_exit;	255	goto pr_exit;
219	}	256	}
220		257
221	/* Check for ACK (!NAK) */	258	/* Check for ACK (!NAK) */
222	if (!(status & I2C_STAT_NACK)) {	259	if (!(status & I2C_STAT_NACK)) {
223	res = 0; /* Device found */	260	res = 0; /* Device found */
224	udelay(I2C_WAIT); /* Required by AM335X in SPL */	261	udelay(adap->waitdelay);/* Required by AM335X in SPL */
225	/* Abort transfer (force idle state) */	262	/* Abort transfer (force idle state) */
226	writew(I2C_CON_MST \| I2C_CON_TRX, &i2c_base->con); /* Reset */	263	writew(I2C_CON_MST \| I2C_CON_TRX, &i2c_base->con); /* Reset */
227	udelay(1000);	264	udelay(1000);
228	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_TRX \|	265	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_TRX \|
229	I2C_CON_STP, &i2c_base->con); /* STP */	266	I2C_CON_STP, &i2c_base->con); /* STP */
230	}	267	}
231	pr_exit:	268	pr_exit:
232	flush_fifo(adap);	269	flush_fifo(adap);
233	writew(0xFFFF, &i2c_base->stat);	270	writew(0xFFFF, &i2c_base->stat);
234	return res;	271	return res;
235	}	272	}
236		273
237	/*	274	/*
238	* i2c_read: Function now uses a single I2C read transaction with bulk transfer	275	* i2c_read: Function now uses a single I2C read transaction with bulk transfer
239	* of the requested number of bytes (note that the 'i2c md' command	276	* of the requested number of bytes (note that the 'i2c md' command
240	* limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is	277	* limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
241	* defined in the board config header, this transaction shall be with	278	* defined in the board config header, this transaction shall be with
242	* Repeated Start (Sr) between the address and data phases; otherwise	279	* Repeated Start (Sr) between the address and data phases; otherwise
243	* Stop-Start (P-S) shall be used (some I2C chips do require a P-S).	280	* Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
244	* The address (reg offset) may be 0, 1 or 2 bytes long.	281	* The address (reg offset) may be 0, 1 or 2 bytes long.
245	* Function now reads correctly from chips that return more than one	282	* Function now reads correctly from chips that return more than one
246	* byte of data per addressed register (like TI temperature sensors),	283	* byte of data per addressed register (like TI temperature sensors),
247	* or that do not need a register address at all (such as some clock	284	* or that do not need a register address at all (such as some clock
248	* distributors).	285	* distributors).
249	*/	286	*/
250	static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,	287	static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
251	int alen, uchar *buffer, int len)	288	int alen, uchar *buffer, int len)
252	{	289	{
253	struct i2c *i2c_base = omap24_get_base(adap);	290	struct i2c *i2c_base = omap24_get_base(adap);
254	int i2c_error = 0;	291	int i2c_error = 0;
255	u16 status;	292	u16 status;
256		293
257	if (alen < 0) {	294	if (alen < 0) {
258	puts("I2C read: addr len < 0\n");	295	puts("I2C read: addr len < 0\n");
259	return 1;	296	return 1;
260	}	297	}
261	if (len < 0) {	298	if (len < 0) {
262	puts("I2C read: data len < 0\n");	299	puts("I2C read: data len < 0\n");
263	return 1;	300	return 1;
264	}	301	}
265	if (buffer == NULL) {	302	if (buffer == NULL) {
266	puts("I2C read: NULL pointer passed\n");	303	puts("I2C read: NULL pointer passed\n");
267	return 1;	304	return 1;
268	}	305	}
269		306
270	if (alen > 2) {	307	if (alen > 2) {
271	printf("I2C read: addr len %d not supported\n", alen);	308	printf("I2C read: addr len %d not supported\n", alen);
272	return 1;	309	return 1;
273	}	310	}
274		311
275	if (addr + len > (1 << 16)) {	312	if (addr + len > (1 << 16)) {
276	puts("I2C read: address out of range\n");	313	puts("I2C read: address out of range\n");
277	return 1;	314	return 1;
278	}	315	}
279		316
280	/* Wait until bus not busy */	317	/* Wait until bus not busy */
281	if (wait_for_bb(adap))	318	if (wait_for_bb(adap))
282	return 1;	319	return 1;
283		320
284	/* Zero, one or two bytes reg address (offset) */	321	/* Zero, one or two bytes reg address (offset) */
285	writew(alen, &i2c_base->cnt);	322	writew(alen, &i2c_base->cnt);
286	/* Set slave address */	323	/* Set slave address */
287	writew(chip, &i2c_base->sa);	324	writew(chip, &i2c_base->sa);
288		325
289	if (alen) {	326	if (alen) {
290	/* Must write reg offset first */	327	/* Must write reg offset first */
291	#ifdef CONFIG_I2C_REPEATED_START	328	#ifdef CONFIG_I2C_REPEATED_START
292	/* No stop bit, use Repeated Start (Sr) */	329	/* No stop bit, use Repeated Start (Sr) */
293	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \|	330	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \|
294	I2C_CON_TRX, &i2c_base->con);	331	I2C_CON_TRX, &i2c_base->con);
295	#else	332	#else
296	/* Stop - Start (P-S) */	333	/* Stop - Start (P-S) */
297	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_STP \|	334	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_STP \|
298	I2C_CON_TRX, &i2c_base->con);	335	I2C_CON_TRX, &i2c_base->con);
299	#endif	336	#endif
300	/* Send register offset */	337	/* Send register offset */
301	while (1) {	338	while (1) {
302	status = wait_for_event(adap);	339	status = wait_for_event(adap);
303	/* Try to identify bus that is not padconf'd for I2C */	340	/* Try to identify bus that is not padconf'd for I2C */
304	if (status == I2C_STAT_XRDY) {	341	if (status == I2C_STAT_XRDY) {
305	i2c_error = 2;	342	i2c_error = 2;
306	printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",	343	printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
307	adap->hwadapnr, status);	344	adap->hwadapnr, status);
308	goto rd_exit;	345	goto rd_exit;
309	}	346	}
310	if (status == 0 \|\| status & I2C_STAT_NACK) {	347	if (status == 0 \|\| (status & I2C_STAT_NACK)) {
311	i2c_error = 1;	348	i2c_error = 1;
312	printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",	349	printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
313	status);	350	status);
314	goto rd_exit;	351	goto rd_exit;
315	}	352	}
316	if (alen) {	353	if (alen) {
317	if (status & I2C_STAT_XRDY) {	354	if (status & I2C_STAT_XRDY) {
318	alen--;	355	alen--;
319	/* Do we have to use byte access? */	356	/* Do we have to use byte access? */
320	writeb((addr >> (8 * alen)) & 0xff,	357	writeb((addr >> (8 * alen)) & 0xff,
321	&i2c_base->data);	358	&i2c_base->data);
322	writew(I2C_STAT_XRDY, &i2c_base->stat);	359	writew(I2C_STAT_XRDY, &i2c_base->stat);
323	}	360	}
324	}	361	}
325	if (status & I2C_STAT_ARDY) {	362	if (status & I2C_STAT_ARDY) {
326	writew(I2C_STAT_ARDY, &i2c_base->stat);	363	writew(I2C_STAT_ARDY, &i2c_base->stat);
327	break;	364	break;
328	}	365	}
329	}	366	}
330	}	367	}
331	/* Set slave address */	368	/* Set slave address */
332	writew(chip, &i2c_base->sa);	369	writew(chip, &i2c_base->sa);
333	/* Read len bytes from slave */	370	/* Read len bytes from slave */
334	writew(len, &i2c_base->cnt);	371	writew(len, &i2c_base->cnt);
335	/* Need stop bit here */	372	/* Need stop bit here */
336	writew(I2C_CON_EN \| I2C_CON_MST \|	373	writew(I2C_CON_EN \| I2C_CON_MST \|
337	I2C_CON_STT \| I2C_CON_STP,	374	I2C_CON_STT \| I2C_CON_STP,
338	&i2c_base->con);	375	&i2c_base->con);
339		376
340	/* Receive data */	377	/* Receive data */
341	while (1) {	378	while (1) {
342	status = wait_for_event(adap);	379	status = wait_for_event(adap);
343	/*	380	/*
344	* Try to identify bus that is not padconf'd for I2C. This	381	* Try to identify bus that is not padconf'd for I2C. This
345	* state could be left over from previous transactions if	382	* state could be left over from previous transactions if
346	* the address phase is skipped due to alen=0.	383	* the address phase is skipped due to alen=0.
347	*/	384	*/
348	if (status == I2C_STAT_XRDY) {	385	if (status == I2C_STAT_XRDY) {
349	i2c_error = 2;	386	i2c_error = 2;
350	printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",	387	printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
351	adap->hwadapnr, status);	388	adap->hwadapnr, status);
352	goto rd_exit;	389	goto rd_exit;
353	}	390	}
354	if (status == 0 \|\| status & I2C_STAT_NACK) {	391	if (status == 0 \|\| (status & I2C_STAT_NACK)) {
355	i2c_error = 1;	392	i2c_error = 1;
356	goto rd_exit;	393	goto rd_exit;
357	}	394	}
358	if (status & I2C_STAT_RRDY) {	395	if (status & I2C_STAT_RRDY) {
359	*buffer++ = readb(&i2c_base->data);	396	*buffer++ = readb(&i2c_base->data);
360	writew(I2C_STAT_RRDY, &i2c_base->stat);	397	writew(I2C_STAT_RRDY, &i2c_base->stat);
361	}	398	}
362	if (status & I2C_STAT_ARDY) {	399	if (status & I2C_STAT_ARDY) {
363	writew(I2C_STAT_ARDY, &i2c_base->stat);	400	writew(I2C_STAT_ARDY, &i2c_base->stat);
364	break;	401	break;
365	}	402	}
366	}	403	}
367		404
368	rd_exit:	405	rd_exit:
369	flush_fifo(adap);	406	flush_fifo(adap);
370	writew(0xFFFF, &i2c_base->stat);	407	writew(0xFFFF, &i2c_base->stat);
371	return i2c_error;	408	return i2c_error;
372	}	409	}
373		410
374	/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */	411	/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
375	static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,	412	static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
376	int alen, uchar *buffer, int len)	413	int alen, uchar *buffer, int len)
377	{	414	{
378	struct i2c *i2c_base = omap24_get_base(adap);	415	struct i2c *i2c_base = omap24_get_base(adap);
379	int i;	416	int i;
380	u16 status;	417	u16 status;
381	int i2c_error = 0;	418	int i2c_error = 0;
		419	int timeout = I2C_TIMEOUT;
382		420
383	if (alen < 0) {	421	if (alen < 0) {
384	puts("I2C write: addr len < 0\n");	422	puts("I2C write: addr len < 0\n");
385	return 1;	423	return 1;
386	}	424	}
387		425
388	if (len < 0) {	426	if (len < 0) {
389	puts("I2C write: data len < 0\n");	427	puts("I2C write: data len < 0\n");
390	return 1;	428	return 1;
391	}	429	}
392		430
393	if (buffer == NULL) {	431	if (buffer == NULL) {
394	puts("I2C write: NULL pointer passed\n");	432	puts("I2C write: NULL pointer passed\n");
395	return 1;	433	return 1;
396	}	434	}
397		435
398	if (alen > 2) {	436	if (alen > 2) {
399	printf("I2C write: addr len %d not supported\n", alen);	437	printf("I2C write: addr len %d not supported\n", alen);
400	return 1;	438	return 1;
401	}	439	}
402		440
403	if (addr + len > (1 << 16)) {	441	if (addr + len > (1 << 16)) {
404	printf("I2C write: address 0x%x + 0x%x out of range\n",	442	printf("I2C write: address 0x%x + 0x%x out of range\n",
405	addr, len);	443	addr, len);
406	return 1;	444	return 1;
407	}	445	}
408		446
409	/* Wait until bus not busy */	447	/* Wait until bus not busy */
410	if (wait_for_bb(adap))	448	if (wait_for_bb(adap))
411	return 1;	449	return 1;
412		450
413	/* Start address phase - will write regoffset + len bytes data */	451	/* Start address phase - will write regoffset + len bytes data */
414	writew(alen + len, &i2c_base->cnt);	452	writew(alen + len, &i2c_base->cnt);
415	/* Set slave address */	453	/* Set slave address */
416	writew(chip, &i2c_base->sa);	454	writew(chip, &i2c_base->sa);
417	/* Stop bit needed here */	455	/* Stop bit needed here */
418	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX \|	456	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX \|
419	I2C_CON_STP, &i2c_base->con);	457	I2C_CON_STP, &i2c_base->con);
420		458
421	while (alen) {	459	while (alen) {
422	/* Must write reg offset (one or two bytes) */	460	/* Must write reg offset (one or two bytes) */
423	status = wait_for_event(adap);	461	status = wait_for_event(adap);
424	/* Try to identify bus that is not padconf'd for I2C */	462	/* Try to identify bus that is not padconf'd for I2C */
425	if (status == I2C_STAT_XRDY) {	463	if (status == I2C_STAT_XRDY) {
426	i2c_error = 2;	464	i2c_error = 2;
427	printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",	465	printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
428	adap->hwadapnr, status);	466	adap->hwadapnr, status);
429	goto wr_exit;	467	goto wr_exit;
430	}	468	}
431	if (status == 0 \|\| status & I2C_STAT_NACK) {	469	if (status == 0 \|\| (status & I2C_STAT_NACK)) {
432	i2c_error = 1;	470	i2c_error = 1;
433	printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",	471	printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
434	status);	472	status);
435	goto wr_exit;	473	goto wr_exit;
436	}	474	}
437	if (status & I2C_STAT_XRDY) {	475	if (status & I2C_STAT_XRDY) {
438	alen--;	476	alen--;
439	writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);	477	writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
440	writew(I2C_STAT_XRDY, &i2c_base->stat);	478	writew(I2C_STAT_XRDY, &i2c_base->stat);
441	} else {	479	} else {
442	i2c_error = 1;	480	i2c_error = 1;
443	printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",	481	printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
444	status);	482	status);
445	goto wr_exit;	483	goto wr_exit;
446	}	484	}
447	}	485	}
448	/* Address phase is over, now write data */	486	/* Address phase is over, now write data */
449	for (i = 0; i < len; i++) {	487	for (i = 0; i < len; i++) {
450	status = wait_for_event(adap);	488	status = wait_for_event(adap);
451	if (status == 0 \|\| status & I2C_STAT_NACK) {	489	if (status == 0 \|\| (status & I2C_STAT_NACK)) {
452	i2c_error = 1;	490	i2c_error = 1;
453	printf("i2c_write: error waiting for data ACK (status=0x%x)\n",	491	printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
454	status);	492	status);
455	goto wr_exit;	493	goto wr_exit;
456	}	494	}
457	if (status & I2C_STAT_XRDY) {	495	if (status & I2C_STAT_XRDY) {
458	writeb(buffer[i], &i2c_base->data);	496	writeb(buffer[i], &i2c_base->data);
459	writew(I2C_STAT_XRDY, &i2c_base->stat);	497	writew(I2C_STAT_XRDY, &i2c_base->stat);
460	} else {	498	} else {
461	i2c_error = 1;	499	i2c_error = 1;
462	printf("i2c_write: bus not ready for data Tx (i=%d)\n",	500	printf("i2c_write: bus not ready for data Tx (i=%d)\n",
463	i);	501	i);
464	goto wr_exit;	502	goto wr_exit;
465	}	503	}
466	}	504	}
		505	/*
		506	* poll ARDY bit for making sure that last byte really has been
		507	* transferred on the bus.
		508	*/
		509	do {
		510	status = wait_for_event(adap);
		511	} while (!(status & I2C_STAT_ARDY) && timeout--);
		512	if (timeout <= 0)
		513	printf("i2c_write: timed out writig last byte!\n");
467		514
468	wr_exit:	515	wr_exit:
469	flush_fifo(adap);	516	flush_fifo(adap);
470	writew(0xFFFF, &i2c_base->stat);	517	writew(0xFFFF, &i2c_base->stat);
471	return i2c_error;	518	return i2c_error;
472	}	519	}
473		520
474	/*	521	/*
475	* Wait for the bus to be free by checking the Bus Busy (BB)	522	* Wait for the bus to be free by checking the Bus Busy (BB)
476	* bit to become clear	523	* bit to become clear
477	*/	524	*/
478	static int wait_for_bb(struct i2c_adapter *adap)	525	static int wait_for_bb(struct i2c_adapter *adap)
479	{	526	{
480	struct i2c *i2c_base = omap24_get_base(adap);	527	struct i2c *i2c_base = omap24_get_base(adap);
481	int timeout = I2C_TIMEOUT;	528	int timeout = I2C_TIMEOUT;
482	u16 stat;	529	u16 stat;
483		530
484	writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/	531	writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
485	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX)	532	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX)
486	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {	533	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
487	#else	534	#else
488	/* Read RAW status */	535	/* Read RAW status */
489	while ((stat = readw(&i2c_base->irqstatus_raw) &	536	while ((stat = readw(&i2c_base->irqstatus_raw) &
490	I2C_STAT_BB) && timeout--) {	537	I2C_STAT_BB) && timeout--) {
491	#endif	538	#endif
492	writew(stat, &i2c_base->stat);	539	writew(stat, &i2c_base->stat);
493	udelay(I2C_WAIT);	540	udelay(adap->waitdelay);
494	}	541	}
495		542
496	if (timeout <= 0) {	543	if (timeout <= 0) {
497	printf("Timed out in wait_for_bb: status=%04x\n",	544	printf("Timed out in wait_for_bb: status=%04x\n",
498	stat);	545	stat);
499	return 1;	546	return 1;
500	}	547	}
501	writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/	548	writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
502	return 0;	549	return 0;
503	}	550	}
504		551
505	/*	552	/*
506	* Wait for the I2C controller to complete current action	553	* Wait for the I2C controller to complete current action
507	* and update status	554	* and update status
508	*/	555	*/
509	static u16 wait_for_event(struct i2c_adapter *adap)	556	static u16 wait_for_event(struct i2c_adapter *adap)
510	{	557	{
511	struct i2c *i2c_base = omap24_get_base(adap);	558	struct i2c *i2c_base = omap24_get_base(adap);
512	u16 status;	559	u16 status;
513	int timeout = I2C_TIMEOUT;	560	int timeout = I2C_TIMEOUT;
514		561
515	do {	562	do {
516	udelay(I2C_WAIT);	563	udelay(adap->waitdelay);
517	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX)	564	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX)
518	status = readw(&i2c_base->stat);	565	status = readw(&i2c_base->stat);
519	#else	566	#else
520	/* Read RAW status */	567	/* Read RAW status */
521	status = readw(&i2c_base->irqstatus_raw);	568	status = readw(&i2c_base->irqstatus_raw);
522	#endif	569	#endif
523	} while (!(status &	570	} while (!(status &
524	(I2C_STAT_ROVR \| I2C_STAT_XUDF \| I2C_STAT_XRDY \|	571	(I2C_STAT_ROVR \| I2C_STAT_XUDF \| I2C_STAT_XRDY \|
525	I2C_STAT_RRDY \| I2C_STAT_ARDY \| I2C_STAT_NACK \|	572	I2C_STAT_RRDY \| I2C_STAT_ARDY \| I2C_STAT_NACK \|
526	I2C_STAT_AL)) && timeout--);	573	I2C_STAT_AL)) && timeout--);
527		574
528	if (timeout <= 0) {	575	if (timeout <= 0) {
529	printf("Timed out in wait_for_event: status=%04x\n",	576	printf("Timed out in wait_for_event: status=%04x\n",
530	status);	577	status);
531	/*	578	/*
532	* If status is still 0 here, probably the bus pads have	579	* If status is still 0 here, probably the bus pads have
533	* not been configured for I2C, and/or pull-ups are missing.	580	* not been configured for I2C, and/or pull-ups are missing.
534	*/	581	*/
535	printf("Check if pads/pull-ups of bus %d are properly configured\n",	582	printf("Check if pads/pull-ups of bus %d are properly configured\n",
536	adap->hwadapnr);	583	adap->hwadapnr);
537	writew(0xFFFF, &i2c_base->stat);	584	writew(0xFFFF, &i2c_base->stat);
538	status = 0;	585	status = 0;
539	}	586	}
540		587
541	return status;	588	return status;
542	}	589	}
543		590
544	static struct i2c omap24_get_base(struct i2c_adapter adap)	591	static struct i2c omap24_get_base(struct i2c_adapter adap)
545	{	592	{
546	switch (adap->hwadapnr) {	593	switch (adap->hwadapnr) {
547	case 0:	594	case 0:
548	return (struct i2c *)I2C_BASE1;	595	return (struct i2c *)I2C_BASE1;
549	break;	596	break;
550	case 1:	597	case 1:
551	return (struct i2c *)I2C_BASE2;	598	return (struct i2c *)I2C_BASE2;
552	break;	599	break;
553	#if (I2C_BUS_MAX > 2)	600	#if (I2C_BUS_MAX > 2)
554	case 2:	601	case 2:
555	return (struct i2c *)I2C_BASE3;	602	return (struct i2c *)I2C_BASE3;
556	break;	603	break;
557	#if (I2C_BUS_MAX > 3)	604	#if (I2C_BUS_MAX > 3)
558	case 3:	605	case 3:
559	return (struct i2c *)I2C_BASE4;	606	return (struct i2c *)I2C_BASE4;
560	break;	607	break;
561	#if (I2C_BUS_MAX > 4)	608	#if (I2C_BUS_MAX > 4)
562	case 4:	609	case 4:
563	return (struct i2c *)I2C_BASE5;	610	return (struct i2c *)I2C_BASE5;
564	break;	611	break;
565	#endif	612	#endif
566	#endif	613	#endif
567	#endif	614	#endif
568	default:	615	default:
569	printf("wrong hwadapnr: %d\n", adap->hwadapnr);	616	printf("wrong hwadapnr: %d\n", adap->hwadapnr);
570	break;	617	break;
571	}	618	}
572	return NULL;	619	return NULL;
573	}	620	}
574		621
575	#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)	622	#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
576	#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED	623	#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
577	#endif	624	#endif
578	#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)	625	#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
579	#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE	626	#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
580	#endif	627	#endif
581		628
582	U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,	629	U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
583	omap24_i2c_read, omap24_i2c_write, NULL,	630	omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
584	CONFIG_SYS_OMAP24_I2C_SPEED,	631	CONFIG_SYS_OMAP24_I2C_SPEED,
585	CONFIG_SYS_OMAP24_I2C_SLAVE,	632	CONFIG_SYS_OMAP24_I2C_SLAVE,
586	0)	633	0)
587	U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,	634	U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
588	omap24_i2c_read, omap24_i2c_write, NULL,	635	omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
589	CONFIG_SYS_OMAP24_I2C_SPEED1,	636	CONFIG_SYS_OMAP24_I2C_SPEED1,
590	CONFIG_SYS_OMAP24_I2C_SLAVE1,	637	CONFIG_SYS_OMAP24_I2C_SLAVE1,
591	1)	638	1)
592	#if (I2C_BUS_MAX > 2)	639	#if (I2C_BUS_MAX > 2)
593	#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)	640	#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
594	#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED	641	#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
595	#endif	642	#endif
596	#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)	643	#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
597	#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE	644	#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
598	#endif	645	#endif
599		646
600	U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,	647	U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
601	omap24_i2c_read, omap24_i2c_write, NULL,	648	omap24_i2c_read, omap24_i2c_write, NULL,
602	CONFIG_SYS_OMAP24_I2C_SPEED2,	649	CONFIG_SYS_OMAP24_I2C_SPEED2,
603	CONFIG_SYS_OMAP24_I2C_SLAVE2,	650	CONFIG_SYS_OMAP24_I2C_SLAVE2,
604	2)	651	2)
605	#if (I2C_BUS_MAX > 3)	652	#if (I2C_BUS_MAX > 3)
606	#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)	653	#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
607	#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED	654	#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
608	#endif	655	#endif
609	#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)	656	#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
610	#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE	657	#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE

include/i2c.h

Diff comments View file @ d524335

 /*
  * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net>
  * Copyright (C) 2009 - 2013 Heiko Schocher <hs@denx.de>
  * Changes for multibus/multiadapter I2C support.
  *
  * (C) Copyright 2001
  * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
  * The original I2C interface was
  *   (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
  *   AIRVENT SAM s.p.a - RIMINI(ITALY)
  * but has been changed substantially.
  */
 #ifndef _I2C_H_
 #define _I2C_H_
 /*
  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
  *
  * The implementation MUST NOT use static or global variables if the
  * I2C routines are used to read SDRAM configuration information
  * because this is done before the memories are initialized. Limited
  * use of stack-based variables are OK (the initial stack size is
  * limited).
  *
  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
  */
 /*
  * Configuration items.
  */
 #define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */
 #if !defined(CONFIG_SYS_I2C_MAX_HOPS)
 /* no muxes used bus = i2c adapters */
 #define CONFIG_SYS_I2C_DIRECT_BUS	1
 #define CONFIG_SYS_I2C_MAX_HOPS		0
 #define CONFIG_SYS_NUM_I2C_BUSES	ll_entry_count(struct i2c_adapter, i2c)
 #else
 /* we use i2c muxes */
 #undef CONFIG_SYS_I2C_DIRECT_BUS
 #endif
 /* define the I2C bus number for RTC and DTT if not already done */
 #if !defined(CONFIG_SYS_RTC_BUS_NUM)
 #define CONFIG_SYS_RTC_BUS_NUM		0
 #endif
 #if !defined(CONFIG_SYS_DTT_BUS_NUM)
 #define CONFIG_SYS_DTT_BUS_NUM		0
 #endif
 #if !defined(CONFIG_SYS_SPD_BUS_NUM)
 #define CONFIG_SYS_SPD_BUS_NUM		0
 #endif
 struct i2c_adapter {
 	void		(*init)(struct i2c_adapter *adap, int speed,
 				int slaveaddr);
 	int		(*probe)(struct i2c_adapter *adap, uint8_t chip);
 	int		(*read)(struct i2c_adapter *adap, uint8_t chip,
 				uint addr, int alen, uint8_t *buffer,
 				int len);
 	int		(*write)(struct i2c_adapter *adap, uint8_t chip,
 				uint addr, int alen, uint8_t *buffer,
 				int len);
 	uint		(*set_bus_speed)(struct i2c_adapter *adap,
 				uint speed);
 	int		speed;
+	int		waitdelay;
 	int		slaveaddr;
 	int		init_done;
 	int		hwadapnr;
 	char		*name;
 };
 #define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
 		_set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
 	{ \
 		.init		=	_init, \
 		.probe		=	_probe, \
 		.read		=	_read, \
 		.write		=	_write, \
 		.set_bus_speed	=	_set_speed, \
 		.speed		=	_speed, \
 		.slaveaddr	=	_slaveaddr, \
 		.init_done	=	0, \
 		.hwadapnr	=	_hwadapnr, \
 		.name		=	#_name \
 };
 #define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
 			_set_speed, _speed, _slaveaddr, _hwadapnr) \
 	ll_entry_declare(struct i2c_adapter, _name, i2c) = \
 	U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
 		 _set_speed, _speed, _slaveaddr, _hwadapnr, _name);
 struct i2c_adapter *i2c_get_adapter(int index);
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 struct i2c_mux {
 	int	id;
 	char	name[16];
 };
 struct i2c_next_hop {
 	struct i2c_mux		mux;
 	uint8_t		chip;
 	uint8_t		channel;
 };
 struct i2c_bus_hose {
 	int	adapter;
 	struct i2c_next_hop	next_hop[CONFIG_SYS_I2C_MAX_HOPS];
 };
 #define I2C_NULL_HOP	{{-1, ""}, 0, 0}
 extern struct i2c_bus_hose	i2c_bus[];
 #define I2C_ADAPTER(bus)	i2c_bus[bus].adapter
 #else
 #define I2C_ADAPTER(bus)	bus
 #endif
 #define	I2C_BUS			gd->cur_i2c_bus
 #define	I2C_ADAP_NR(bus)	i2c_get_adapter(I2C_ADAPTER(bus))
 #define	I2C_ADAP		I2C_ADAP_NR(gd->cur_i2c_bus)
 #define I2C_ADAP_HWNR		(I2C_ADAP->hwadapnr)
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 #define I2C_MUX_PCA9540_ID	1
 #define I2C_MUX_PCA9540		{I2C_MUX_PCA9540_ID, "PCA9540B"}
 #define I2C_MUX_PCA9542_ID	2
 #define I2C_MUX_PCA9542		{I2C_MUX_PCA9542_ID, "PCA9542A"}
 #define I2C_MUX_PCA9544_ID	3
 #define I2C_MUX_PCA9544		{I2C_MUX_PCA9544_ID, "PCA9544A"}
 #define I2C_MUX_PCA9547_ID	4
 #define I2C_MUX_PCA9547		{I2C_MUX_PCA9547_ID, "PCA9547A"}
 #define I2C_MUX_PCA9548_ID	5
 #define I2C_MUX_PCA9548		{I2C_MUX_PCA9548_ID, "PCA9548"}
 #endif
 #ifndef I2C_SOFT_DECLARATIONS
 # if defined(CONFIG_MPC8260)
 #  define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
 # elif defined(CONFIG_8xx)
 #  define I2C_SOFT_DECLARATIONS	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 # elif (defined(CONFIG_AT91RM9200) || \
 	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
 	defined(CONFIG_AT91SAM9263))
 #  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIOA;
 # else
 #  define I2C_SOFT_DECLARATIONS
 # endif
 #endif
 #ifdef CONFIG_8xx
 /* Set default value for the I2C bus speed on 8xx. In the
  * future, we'll define these in all 8xx board config files.
  */
 #ifndef	CONFIG_SYS_I2C_SPEED
 #define	CONFIG_SYS_I2C_SPEED	50000
 #endif
 #endif
 /*
  * Many boards/controllers/drivers don't support an I2C slave interface so
  * provide a default slave address for them for use in common code.  A real
  * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
  * support a slave interface.
  */
 #ifndef	CONFIG_SYS_I2C_SLAVE
 #define	CONFIG_SYS_I2C_SLAVE	0xfe
 #endif
 /*
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
 void i2c_board_late_init(void);
 #endif
 #ifdef CONFIG_SYS_I2C
 /*
  * i2c_get_bus_num:
  *
  *  Returns index of currently active I2C bus.  Zero-based.
  */
 unsigned int i2c_get_bus_num(void);
 /*
  * i2c_set_bus_num:
  *
  *  Change the active I2C bus.  Subsequent read/write calls will
  *  go to this one.
  *
  *	bus - bus index, zero based
  *
  *	Returns: 0 on success, not 0 on failure
  *
  */
 int i2c_set_bus_num(unsigned int bus);
 /*
  * i2c_init_all():
  *
  * Initializes all I2C adapters in the system. All i2c_adap structures must
  * be initialized beforehead with function pointers and data, including
  * speed and slaveaddr. Returns 0 on success, non-0 on failure.
  */
 void i2c_init_all(void);
 /*
  * Probe the given I2C chip address.  Returns 0 if a chip responded,
  * not 0 on failure.
  */
 int i2c_probe(uint8_t chip);
 /*
  * Read/Write interface:
  *   chip:    I2C chip address, range 0..127
  *   addr:    Memory (register) address within the chip
  *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
  *              memories, 0 for register type devices with only one
  *              register)
  *   buffer:  Where to read/write the data
  *   len:     How many bytes to read/write
  *
  *   Returns: 0 on success, not 0 on failure
  */
 int i2c_read(uint8_t chip, unsigned int addr, int alen,
 				uint8_t *buffer, int len);
 int i2c_write(uint8_t chip, unsigned int addr, int alen,
 				uint8_t *buffer, int len);
 /*
  * Utility routines to read/write registers.
  */
 uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
 void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
 /*
  * i2c_set_bus_speed:
  *
  *  Change the speed of the active I2C bus
  *
  *	speed - bus speed in Hz
  *
  *	Returns: new bus speed
  *
  */
 unsigned int i2c_set_bus_speed(unsigned int speed);
 /*
  * i2c_get_bus_speed:
  *
  *  Returns speed of currently active I2C bus in Hz
  */
 unsigned int i2c_get_bus_speed(void);
 /*
  * i2c_reloc_fixup:
  *
  * Adjusts I2C pointers after U-Boot is relocated to DRAM
  */
 void i2c_reloc_fixup(void);
 #if defined(CONFIG_SYS_I2C_SOFT)
 void i2c_soft_init(void);
 void i2c_soft_active(void);
 void i2c_soft_tristate(void);
 int i2c_soft_read(void);
 void i2c_soft_sda(int bit);
 void i2c_soft_scl(int bit);
 void i2c_soft_delay(void);
 #endif
 #else
 /*
  * Probe the given I2C chip address.  Returns 0 if a chip responded,
  * not 0 on failure.
  */
 int i2c_probe(uchar chip);
 /*
  * Read/Write interface:
  *   chip:    I2C chip address, range 0..127
  *   addr:    Memory (register) address within the chip
  *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
  *              memories, 0 for register type devices with only one
  *              register)
  *   buffer:  Where to read/write the data
  *   len:     How many bytes to read/write
  *
  *   Returns: 0 on success, not 0 on failure
  */
 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
 /*
  * Utility routines to read/write registers.
  */
 static inline u8 i2c_reg_read(u8 addr, u8 reg)
 {
 	u8 buf;
 #ifdef CONFIG_8xx
 	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 #ifdef DEBUG
 	printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
 #endif
 	i2c_read(addr, reg, 1, &buf, 1);
 	return buf;
 }
 static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
 {
 #ifdef CONFIG_8xx
 	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 #ifdef DEBUG
 	printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
 	       __func__, addr, reg, val);
 #endif
 	i2c_write(addr, reg, 1, &val, 1);
 }
 /*
  * Functions for setting the current I2C bus and its speed
  */
 /*
  * i2c_set_bus_num:
  *
  *  Change the active I2C bus.  Subsequent read/write calls will
  *  go to this one.
  *
  *	bus - bus index, zero based
  *
  *	Returns: 0 on success, not 0 on failure
  *
  */
 int i2c_set_bus_num(unsigned int bus);
 /*
  * i2c_get_bus_num:
  *
  *  Returns index of currently active I2C bus.  Zero-based.
  */
 unsigned int i2c_get_bus_num(void);
 /*
  * i2c_set_bus_speed:
  *
  *  Change the speed of the active I2C bus
  *
  *	speed - bus speed in Hz
  *
  *	Returns: 0 on success, not 0 on failure
  *
  */
 int i2c_set_bus_speed(unsigned int);
 /*
  * i2c_get_bus_speed:
  *
  *  Returns speed of currently active I2C bus in Hz
  */
 unsigned int i2c_get_bus_speed(void);
 #endif /* CONFIG_SYS_I2C */
 /*
  * only for backwardcompatibility, should go away if we switched
  * completely to new multibus support.
  */
 #if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
 # if !defined(CONFIG_SYS_MAX_I2C_BUS)
 #  define CONFIG_SYS_MAX_I2C_BUS		2
 # endif
 # define I2C_MULTI_BUS				1
 #else
 # define CONFIG_SYS_MAX_I2C_BUS		1
 # define I2C_MULTI_BUS				0
 #endif
 /* NOTE: These two functions MUST be always_inline to avoid code growth! */
 static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
 static inline unsigned int I2C_GET_BUS(void)
 {
 	return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
 }
 static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
 static inline void I2C_SET_BUS(unsigned int bus)
 {
 	if (I2C_MULTI_BUS)
 		i2c_set_bus_num(bus);
 }
 /* Multi I2C definitions */
 enum {
 	I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
 	I2C_8, I2C_9, I2C_10,
 };
 /* Multi I2C busses handling */
 #ifdef CONFIG_SOFT_I2C_MULTI_BUS
 extern int get_multi_scl_pin(void);
 extern int get_multi_sda_pin(void);
 extern int multi_i2c_init(void);
 #endif
 /**
  * Get FDT values for i2c bus.
  *
  * @param blob  Device tree blbo
  * @return the number of I2C bus
  */
 void board_i2c_init(const void *blob);
 /**
  * Find the I2C bus number by given a FDT I2C node.
  *
  * @param blob  Device tree blbo
  * @param node  FDT I2C node to find
  * @return the number of I2C bus (zero based), or -1 on error
  */
 int i2c_get_bus_num_fdt(int node);
 /**
  * Reset the I2C bus represented by the given a FDT I2C node.
  *
  * @param blob  Device tree blbo
  * @param node  FDT I2C node to find
  * @return 0 if port was reset, -1 if not found
  */
 int i2c_reset_port_fdt(const void *blob, int node);
 #endif	/* _I2C_H_ */

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Eric Lee 2023-05-08 10:09:23 UTC

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