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Commit d59baeb76f911d0391e73e5f6068e55ea48514f8

Authored by Roger Quadros
Committed by Tom Rini
1 parent 3160b1b986
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: OMAP5+: sata: Move scsi_scan() to the right place 

scsi_scan() must be called as part of scsi_init() and not
as part of sata_init().

Signed-off-by: Roger Quadros <rogerq@ti.com>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

arch/arm/cpu/armv7/omap-common/sata.c
Diff comments   View file @ d59baeb
1 /* 1 /*
2 * TI SATA platform driver 2 * TI SATA platform driver
3 * 3 *
4 * (C) Copyright 2013 4 * (C) Copyright 2013
5 * Texas Instruments, <www.ti.com> 5 * Texas Instruments, <www.ti.com>
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <ahci.h> 11 #include <ahci.h>
12 #include <scsi.h> 12 #include <scsi.h>
13 #include <asm/arch/clock.h> 13 #include <asm/arch/clock.h>
14 #include <asm/arch/sata.h> 14 #include <asm/arch/sata.h>
15 #include <sata.h> 15 #include <sata.h>
16 #include <asm/io.h> 16 #include <asm/io.h>
17 #include "pipe3-phy.h" 17 #include "pipe3-phy.h"
18 18
19 static struct pipe3_dpll_map dpll_map_sata[] = { 19 static struct pipe3_dpll_map dpll_map_sata[] = {
20 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ 20 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
21 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ 21 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
22 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ 22 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
23 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ 23 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
24 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ 24 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
25 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ 25 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
26 { }, /* Terminator */ 26 { }, /* Terminator */
27 }; 27 };
28 28
29 struct omap_pipe3 sata_phy = { 29 struct omap_pipe3 sata_phy = {
30 .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, 30 .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
31 /* .power_reg is updated at runtime */ 31 /* .power_reg is updated at runtime */
32 .dpll_map = dpll_map_sata, 32 .dpll_map = dpll_map_sata,
33 }; 33 };
34 34
35 int init_sata(int dev) 35 int init_sata(int dev)
36 { 36 {
37 int ret; 37 int ret;
38 u32 val; 38 u32 val;
39 39
40 u32 const clk_domains_sata[] = { 40 u32 const clk_domains_sata[] = {
41 0 41 0
42 }; 42 };
43 43
44 u32 const clk_modules_hw_auto_sata[] = { 44 u32 const clk_modules_hw_auto_sata[] = {
45 (*prcm)->cm_l3init_ocp2scp3_clkctrl, 45 (*prcm)->cm_l3init_ocp2scp3_clkctrl,
46 0 46 0
47 }; 47 };
48 48
49 u32 const clk_modules_explicit_en_sata[] = { 49 u32 const clk_modules_explicit_en_sata[] = {
50 (*prcm)->cm_l3init_sata_clkctrl, 50 (*prcm)->cm_l3init_sata_clkctrl,
51 0 51 0
52 }; 52 };
53 53
54 do_enable_clocks(clk_domains_sata, 54 do_enable_clocks(clk_domains_sata,
55 clk_modules_hw_auto_sata, 55 clk_modules_hw_auto_sata,
56 clk_modules_explicit_en_sata, 56 clk_modules_explicit_en_sata,
57 0); 57 0);
58 58
59 /* Enable optional functional clock for SATA */ 59 /* Enable optional functional clock for SATA */
60 setbits_le32((*prcm)->cm_l3init_sata_clkctrl, 60 setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
61 SATA_CLKCTRL_OPTFCLKEN_MASK); 61 SATA_CLKCTRL_OPTFCLKEN_MASK);
62 62
63 sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; 63 sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
64 64
65 /* Power up the PHY */ 65 /* Power up the PHY */
66 phy_pipe3_power_on(&sata_phy); 66 phy_pipe3_power_on(&sata_phy);
67 67
68 /* Enable SATA module, No Idle, No Standby */ 68 /* Enable SATA module, No Idle, No Standby */
69 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; 69 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
70 writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); 70 writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
71 71
72 ret = ahci_init(DWC_AHSATA_BASE); 72 ret = ahci_init(DWC_AHSATA_BASE);
73 scsi_scan(1);
74 73
75 return ret; 74 return ret;
76 } 75 }
77 76
78 /* On OMAP platforms SATA provides the SCSI subsystem */ 77 /* On OMAP platforms SATA provides the SCSI subsystem */
79 void scsi_init(void) 78 void scsi_init(void)
80 { 79 {
81 init_sata(0); 80 init_sata(0);
81 scsi_scan(1);
82 } 82 }