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Commit d85879938d3fc3557f6ff74a60f95e0975a314ce

Authored by Thomas Chou
1 parent b375219e73
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

dm: implement a MTD uclass 

Implement a Memory Technology Device (MTD) uclass. It should
include most flash drivers in the future. Though no uclass ops
are defined yet, the MTD ops could be used.

The NAND flash driver is based on MTD. The CFI flash and SPI
flash support MTD, too. It should make sense to convert them
to MTD uclass.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>

Showing 7 changed files with 63 additions and 0 deletions Inline Diff

1 menu "MTD Support"
2
3 config MTD
4 bool "Enable Driver Model for MTD drivers"
5 depends on DM
6 help
7 Enable driver model for Memory Technology Devices (MTD), such as
8 flash, RAM and similar chips, often used for solid state file
9 systems on embedded devices.
10
11 endmenu
12
1 source "drivers/mtd/nand/Kconfig" 13 source "drivers/mtd/nand/Kconfig"
2 14
3 source "drivers/mtd/spi/Kconfig" 15 source "drivers/mtd/spi/Kconfig"
4 16
drivers/mtd/Makefile
Diff comments   View file @ d858799
1 # 1 #
2 # (C) Copyright 2000-2007 2 # (C) Copyright 2000-2007
3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 # 4 #
5 # SPDX-License-Identifier: GPL-2.0+ 5 # SPDX-License-Identifier: GPL-2.0+
6 # 6 #
7 7
8 ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)$(CONFIG_CMD_SF))) 8 ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)$(CONFIG_CMD_SF)))
9 obj-y += mtdcore.o mtd_uboot.o 9 obj-y += mtdcore.o mtd_uboot.o
10 endif 10 endif
11 obj-$(CONFIG_MTD) += mtd-uclass.o
11 obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o 12 obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
12 obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o 13 obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
13 obj-$(CONFIG_HAS_DATAFLASH) += at45.o 14 obj-$(CONFIG_HAS_DATAFLASH) += at45.o
14 obj-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o 15 obj-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
15 obj-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o 16 obj-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
16 obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o 17 obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
17 obj-$(CONFIG_FTSMC020) += ftsmc020.o 18 obj-$(CONFIG_FTSMC020) += ftsmc020.o
18 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o 19 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
19 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o 20 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
20 obj-$(CONFIG_ST_SMI) += st_smi.o 21 obj-$(CONFIG_ST_SMI) += st_smi.o
21 22
drivers/mtd/mtd-uclass.c
Diff comments   View file @ d858799
File was created 1 /*
2 * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <mtd.h>
11
12 /*
13 * Implement a MTD uclass which should include most flash drivers.
14 * The uclass private is pointed to mtd_info.
15 */
16
17 UCLASS_DRIVER(mtd) = {
18 .id = UCLASS_MTD,
19 .name = "mtd",
20 .per_device_auto_alloc_size = sizeof(struct mtd_info),
21 };
22
include/dm/uclass-id.h
Diff comments   View file @ d858799
1 /* 1 /*
2 * Copyright (c) 2013 Google, Inc 2 * Copyright (c) 2013 Google, Inc
3 * 3 *
4 * (C) Copyright 2012 4 * (C) Copyright 2012
5 * Pavel Herrmann <morpheus.ibis@gmail.com> 5 * Pavel Herrmann <morpheus.ibis@gmail.com>
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #ifndef _DM_UCLASS_ID_H 10 #ifndef _DM_UCLASS_ID_H
11 #define _DM_UCLASS_ID_H 11 #define _DM_UCLASS_ID_H
12 12
13 /* TODO(sjg@chromium.org): this could be compile-time generated */ 13 /* TODO(sjg@chromium.org): this could be compile-time generated */
14 enum uclass_id { 14 enum uclass_id {
15 /* These are used internally by driver model */ 15 /* These are used internally by driver model */
16 UCLASS_ROOT = 0, 16 UCLASS_ROOT = 0,
17 UCLASS_DEMO, 17 UCLASS_DEMO,
18 UCLASS_TEST, 18 UCLASS_TEST,
19 UCLASS_TEST_FDT, 19 UCLASS_TEST_FDT,
20 UCLASS_TEST_BUS, 20 UCLASS_TEST_BUS,
21 UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ 21 UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
22 UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ 22 UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
23 UCLASS_PCI_EMUL, /* sandbox PCI device emulator */ 23 UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
24 UCLASS_USB_EMUL, /* sandbox USB bus device emulator */ 24 UCLASS_USB_EMUL, /* sandbox USB bus device emulator */
25 UCLASS_SIMPLE_BUS, /* bus with child devices */ 25 UCLASS_SIMPLE_BUS, /* bus with child devices */
26 26
27 /* U-Boot uclasses start here - in alphabetical order */ 27 /* U-Boot uclasses start here - in alphabetical order */
28 UCLASS_ADC, /* Analog-to-digital converter */ 28 UCLASS_ADC, /* Analog-to-digital converter */
29 UCLASS_CLK, /* Clock source, e.g. used by peripherals */ 29 UCLASS_CLK, /* Clock source, e.g. used by peripherals */
30 UCLASS_CPU, /* CPU, typically part of an SoC */ 30 UCLASS_CPU, /* CPU, typically part of an SoC */
31 UCLASS_CROS_EC, /* Chrome OS EC */ 31 UCLASS_CROS_EC, /* Chrome OS EC */
32 UCLASS_DISPLAY_PORT, /* Display port video */ 32 UCLASS_DISPLAY_PORT, /* Display port video */
33 UCLASS_RAM, /* RAM controller */ 33 UCLASS_RAM, /* RAM controller */
34 UCLASS_ETH, /* Ethernet device */ 34 UCLASS_ETH, /* Ethernet device */
35 UCLASS_GPIO, /* Bank of general-purpose I/O pins */ 35 UCLASS_GPIO, /* Bank of general-purpose I/O pins */
36 UCLASS_I2C, /* I2C bus */ 36 UCLASS_I2C, /* I2C bus */
37 UCLASS_I2C_EEPROM, /* I2C EEPROM device */ 37 UCLASS_I2C_EEPROM, /* I2C EEPROM device */
38 UCLASS_I2C_GENERIC, /* Generic I2C device */ 38 UCLASS_I2C_GENERIC, /* Generic I2C device */
39 UCLASS_I2C_MUX, /* I2C multiplexer */ 39 UCLASS_I2C_MUX, /* I2C multiplexer */
40 UCLASS_LED, /* Light-emitting diode (LED) */ 40 UCLASS_LED, /* Light-emitting diode (LED) */
41 UCLASS_LPC, /* x86 'low pin count' interface */ 41 UCLASS_LPC, /* x86 'low pin count' interface */
42 UCLASS_MASS_STORAGE, /* Mass storage device */ 42 UCLASS_MASS_STORAGE, /* Mass storage device */
43 UCLASS_MISC, /* Miscellaneous device */ 43 UCLASS_MISC, /* Miscellaneous device */
44 UCLASS_MMC, /* SD / MMC card or chip */ 44 UCLASS_MMC, /* SD / MMC card or chip */
45 UCLASS_MOD_EXP, /* RSA Mod Exp device */ 45 UCLASS_MOD_EXP, /* RSA Mod Exp device */
46 UCLASS_MTD, /* Memory Technology Device (MTD) device */
46 UCLASS_PCH, /* x86 platform controller hub */ 47 UCLASS_PCH, /* x86 platform controller hub */
47 UCLASS_PCI, /* PCI bus */ 48 UCLASS_PCI, /* PCI bus */
48 UCLASS_PCI_GENERIC, /* Generic PCI bus device */ 49 UCLASS_PCI_GENERIC, /* Generic PCI bus device */
49 UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ 50 UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
50 UCLASS_PINCONFIG, /* Pin configuration node device */ 51 UCLASS_PINCONFIG, /* Pin configuration node device */
51 UCLASS_PMIC, /* PMIC I/O device */ 52 UCLASS_PMIC, /* PMIC I/O device */
52 UCLASS_REGULATOR, /* Regulator device */ 53 UCLASS_REGULATOR, /* Regulator device */
53 UCLASS_RESET, /* Reset device */ 54 UCLASS_RESET, /* Reset device */
54 UCLASS_REMOTEPROC, /* Remote Processor device */ 55 UCLASS_REMOTEPROC, /* Remote Processor device */
55 UCLASS_RTC, /* Real time clock device */ 56 UCLASS_RTC, /* Real time clock device */
56 UCLASS_SERIAL, /* Serial UART */ 57 UCLASS_SERIAL, /* Serial UART */
57 UCLASS_SPI, /* SPI bus */ 58 UCLASS_SPI, /* SPI bus */
58 UCLASS_SPI_FLASH, /* SPI flash */ 59 UCLASS_SPI_FLASH, /* SPI flash */
59 UCLASS_SPI_GENERIC, /* Generic SPI flash target */ 60 UCLASS_SPI_GENERIC, /* Generic SPI flash target */
60 UCLASS_SYSCON, /* System configuration device */ 61 UCLASS_SYSCON, /* System configuration device */
61 UCLASS_THERMAL, /* Thermal sensor */ 62 UCLASS_THERMAL, /* Thermal sensor */
62 UCLASS_TIMER, /* Timer device */ 63 UCLASS_TIMER, /* Timer device */
63 UCLASS_TPM, /* Trusted Platform Module TIS interface */ 64 UCLASS_TPM, /* Trusted Platform Module TIS interface */
64 UCLASS_USB, /* USB bus */ 65 UCLASS_USB, /* USB bus */
65 UCLASS_USB_DEV_GENERIC, /* USB generic device */ 66 UCLASS_USB_DEV_GENERIC, /* USB generic device */
66 UCLASS_USB_HUB, /* USB hub */ 67 UCLASS_USB_HUB, /* USB hub */
67 UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */ 68 UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */
68 69
69 UCLASS_COUNT, 70 UCLASS_COUNT,
70 UCLASS_INVALID = -1, 71 UCLASS_INVALID = -1,
71 }; 72 };
72 73
73 #endif 74 #endif
74 75
1 /* 1 /*
2 * (C) Copyright 2000-2005 2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef _FLASH_H_ 8 #ifndef _FLASH_H_
9 #define _FLASH_H_ 9 #define _FLASH_H_
10 10
11 #ifndef CONFIG_SYS_NO_FLASH 11 #ifndef CONFIG_SYS_NO_FLASH
12 /*----------------------------------------------------------------------- 12 /*-----------------------------------------------------------------------
13 * FLASH Info: contains chip specific data, per FLASH bank 13 * FLASH Info: contains chip specific data, per FLASH bank
14 */ 14 */
15 15
16 typedef struct { 16 typedef struct {
17 ulong size; /* total bank size in bytes */ 17 ulong size; /* total bank size in bytes */
18 ushort sector_count; /* number of erase units */ 18 ushort sector_count; /* number of erase units */
19 ulong flash_id; /* combined device & manufacturer code */ 19 ulong flash_id; /* combined device & manufacturer code */
20 ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* virtual sector start address */ 20 ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* virtual sector start address */
21 uchar protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status */ 21 uchar protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status */
22 #ifdef CONFIG_SYS_FLASH_CFI 22 #ifdef CONFIG_SYS_FLASH_CFI
23 uchar portwidth; /* the width of the port */ 23 uchar portwidth; /* the width of the port */
24 uchar chipwidth; /* the width of the chip */ 24 uchar chipwidth; /* the width of the chip */
25 ushort buffer_size; /* # of bytes in write buffer */ 25 ushort buffer_size; /* # of bytes in write buffer */
26 ulong erase_blk_tout; /* maximum block erase timeout */ 26 ulong erase_blk_tout; /* maximum block erase timeout */
27 ulong write_tout; /* maximum write timeout */ 27 ulong write_tout; /* maximum write timeout */
28 ulong buffer_write_tout; /* maximum buffer write timeout */ 28 ulong buffer_write_tout; /* maximum buffer write timeout */
29 ushort vendor; /* the primary vendor id */ 29 ushort vendor; /* the primary vendor id */
30 ushort cmd_reset; /* vendor specific reset command */ 30 ushort cmd_reset; /* vendor specific reset command */
31 uchar cmd_erase_sector; /* vendor specific erase sect. command */ 31 uchar cmd_erase_sector; /* vendor specific erase sect. command */
32 ushort interface; /* used for x8/x16 adjustments */ 32 ushort interface; /* used for x8/x16 adjustments */
33 ushort legacy_unlock; /* support Intel legacy (un)locking */ 33 ushort legacy_unlock; /* support Intel legacy (un)locking */
34 ushort manufacturer_id; /* manufacturer id */ 34 ushort manufacturer_id; /* manufacturer id */
35 ushort device_id; /* device id */ 35 ushort device_id; /* device id */
36 ushort device_id2; /* extended device id */ 36 ushort device_id2; /* extended device id */
37 ushort ext_addr; /* extended query table address */ 37 ushort ext_addr; /* extended query table address */
38 ushort cfi_version; /* cfi version */ 38 ushort cfi_version; /* cfi version */
39 ushort cfi_offset; /* offset for cfi query */ 39 ushort cfi_offset; /* offset for cfi query */
40 ulong addr_unlock1; /* unlock address 1 for AMD flash roms */ 40 ulong addr_unlock1; /* unlock address 1 for AMD flash roms */
41 ulong addr_unlock2; /* unlock address 2 for AMD flash roms */ 41 ulong addr_unlock2; /* unlock address 2 for AMD flash roms */
42 const char *name; /* human-readable name */ 42 const char *name; /* human-readable name */
43 #endif 43 #endif
44 #ifdef CONFIG_MTD
45 struct mtd_info *mtd;
46 #endif
44 } flash_info_t; 47 } flash_info_t;
45 48
46 extern flash_info_t flash_info[]; /* info for FLASH chips */ 49 extern flash_info_t flash_info[]; /* info for FLASH chips */
47 50
48 typedef unsigned long flash_sect_t; 51 typedef unsigned long flash_sect_t;
49 52
50 /* 53 /*
51 * Values for the width of the port 54 * Values for the width of the port
52 */ 55 */
53 #define FLASH_CFI_8BIT 0x01 56 #define FLASH_CFI_8BIT 0x01
54 #define FLASH_CFI_16BIT 0x02 57 #define FLASH_CFI_16BIT 0x02
55 #define FLASH_CFI_32BIT 0x04 58 #define FLASH_CFI_32BIT 0x04
56 #define FLASH_CFI_64BIT 0x08 59 #define FLASH_CFI_64BIT 0x08
57 /* 60 /*
58 * Values for the width of the chip 61 * Values for the width of the chip
59 */ 62 */
60 #define FLASH_CFI_BY8 0x01 63 #define FLASH_CFI_BY8 0x01
61 #define FLASH_CFI_BY16 0x02 64 #define FLASH_CFI_BY16 0x02
62 #define FLASH_CFI_BY32 0x04 65 #define FLASH_CFI_BY32 0x04
63 #define FLASH_CFI_BY64 0x08 66 #define FLASH_CFI_BY64 0x08
64 /* convert between bit value and numeric value */ 67 /* convert between bit value and numeric value */
65 #define CFI_FLASH_SHIFT_WIDTH 3 68 #define CFI_FLASH_SHIFT_WIDTH 3
66 /* 69 /*
67 * Values for the flash device interface 70 * Values for the flash device interface
68 */ 71 */
69 #define FLASH_CFI_X8 0x00 72 #define FLASH_CFI_X8 0x00
70 #define FLASH_CFI_X16 0x01 73 #define FLASH_CFI_X16 0x01
71 #define FLASH_CFI_X8X16 0x02 74 #define FLASH_CFI_X8X16 0x02
72 #define FLASH_CFI_X16X32 0x05 75 #define FLASH_CFI_X16X32 0x05
73 76
74 /* convert between bit value and numeric value */ 77 /* convert between bit value and numeric value */
75 #define CFI_FLASH_SHIFT_WIDTH 3 78 #define CFI_FLASH_SHIFT_WIDTH 3
76 79
77 /* Prototypes */ 80 /* Prototypes */
78 81
79 extern unsigned long flash_init (void); 82 extern unsigned long flash_init (void);
80 extern void flash_protect_default(void); 83 extern void flash_protect_default(void);
81 extern void flash_print_info (flash_info_t *); 84 extern void flash_print_info (flash_info_t *);
82 extern int flash_erase (flash_info_t *, int, int); 85 extern int flash_erase (flash_info_t *, int, int);
83 extern int flash_sect_erase (ulong addr_first, ulong addr_last); 86 extern int flash_sect_erase (ulong addr_first, ulong addr_last);
84 extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last); 87 extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
85 extern int flash_sect_roundb (ulong *addr); 88 extern int flash_sect_roundb (ulong *addr);
86 extern unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect); 89 extern unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect);
87 extern void flash_set_verbose(uint); 90 extern void flash_set_verbose(uint);
88 91
89 /* common/flash.c */ 92 /* common/flash.c */
90 extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info); 93 extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
91 extern int flash_write (char *, ulong, ulong); 94 extern int flash_write (char *, ulong, ulong);
92 extern flash_info_t *addr2info (ulong); 95 extern flash_info_t *addr2info (ulong);
93 extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); 96 extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
94 97
95 /* drivers/mtd/cfi_mtd.c */ 98 /* drivers/mtd/cfi_mtd.c */
96 #ifdef CONFIG_FLASH_CFI_MTD 99 #ifdef CONFIG_FLASH_CFI_MTD
97 extern int cfi_mtd_init(void); 100 extern int cfi_mtd_init(void);
98 #endif 101 #endif
99 102
100 /* board/?/flash.c */ 103 /* board/?/flash.c */
101 #if defined(CONFIG_SYS_FLASH_PROTECTION) 104 #if defined(CONFIG_SYS_FLASH_PROTECTION)
102 extern int flash_real_protect(flash_info_t *info, long sector, int prot); 105 extern int flash_real_protect(flash_info_t *info, long sector, int prot);
103 extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len); 106 extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len);
104 extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len); 107 extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
105 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 108 #endif /* CONFIG_SYS_FLASH_PROTECTION */
106 109
107 #ifdef CONFIG_FLASH_CFI_LEGACY 110 #ifdef CONFIG_FLASH_CFI_LEGACY
108 extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info); 111 extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info);
109 extern int jedec_flash_match(flash_info_t *info, ulong base); 112 extern int jedec_flash_match(flash_info_t *info, ulong base);
110 #define CFI_CMDSET_AMD_LEGACY 0xFFF0 113 #define CFI_CMDSET_AMD_LEGACY 0xFFF0
111 #endif 114 #endif
112 115
113 #if defined(CONFIG_SYS_FLASH_CFI) 116 #if defined(CONFIG_SYS_FLASH_CFI)
114 extern flash_info_t *flash_get_info(ulong base); 117 extern flash_info_t *flash_get_info(ulong base);
115 #endif 118 #endif
116 119
117 /*----------------------------------------------------------------------- 120 /*-----------------------------------------------------------------------
118 * return codes from flash_write(): 121 * return codes from flash_write():
119 */ 122 */
120 #define ERR_OK 0 123 #define ERR_OK 0
121 #define ERR_TIMOUT 1 124 #define ERR_TIMOUT 1
122 #define ERR_NOT_ERASED 2 125 #define ERR_NOT_ERASED 2
123 #define ERR_PROTECTED 4 126 #define ERR_PROTECTED 4
124 #define ERR_INVAL 8 127 #define ERR_INVAL 8
125 #define ERR_ALIGN 16 128 #define ERR_ALIGN 16
126 #define ERR_UNKNOWN_FLASH_VENDOR 32 129 #define ERR_UNKNOWN_FLASH_VENDOR 32
127 #define ERR_UNKNOWN_FLASH_TYPE 64 130 #define ERR_UNKNOWN_FLASH_TYPE 64
128 #define ERR_PROG_ERROR 128 131 #define ERR_PROG_ERROR 128
129 #define ERR_ABORTED 256 132 #define ERR_ABORTED 256
130 133
131 /*----------------------------------------------------------------------- 134 /*-----------------------------------------------------------------------
132 * Protection Flags for flash_protect(): 135 * Protection Flags for flash_protect():
133 */ 136 */
134 #define FLAG_PROTECT_SET 0x01 137 #define FLAG_PROTECT_SET 0x01
135 #define FLAG_PROTECT_CLEAR 0x02 138 #define FLAG_PROTECT_CLEAR 0x02
136 #define FLAG_PROTECT_INVALID 0x03 139 #define FLAG_PROTECT_INVALID 0x03
137 /*----------------------------------------------------------------------- 140 /*-----------------------------------------------------------------------
138 * Set Environment according to label: 141 * Set Environment according to label:
139 */ 142 */
140 #define FLAG_SETENV 0x80 143 #define FLAG_SETENV 0x80
141 144
142 /*----------------------------------------------------------------------- 145 /*-----------------------------------------------------------------------
143 * Device IDs 146 * Device IDs
144 */ 147 */
145 148
146 /* Manufacturers inside bank 0 have ids like 0x00xx00xx */ 149 /* Manufacturers inside bank 0 have ids like 0x00xx00xx */
147 #define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */ 150 #define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */
148 #define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ 151 #define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */
149 #define ATM_MANUFACT 0x001F001F /* ATMEL */ 152 #define ATM_MANUFACT 0x001F001F /* ATMEL */
150 #define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */ 153 #define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
151 #define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */ 154 #define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
152 #define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */ 155 #define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
153 #define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */ 156 #define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */
154 #define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */ 157 #define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */
155 #define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */ 158 #define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
156 #define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ 159 #define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */
157 #define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ 160 #define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/
158 #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ 161 #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */
159 #define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ 162 #define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */
160 #define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ 163 #define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */
161 #define EON_ALT_MANU 0x001C001C /* EON manuf. ID in D23..D16, D7..D0 */ 164 #define EON_ALT_MANU 0x001C001C /* EON manuf. ID in D23..D16, D7..D0 */
162 165
163 /* Manufacturers inside bank 1 have ids like 0x01xx01xx */ 166 /* Manufacturers inside bank 1 have ids like 0x01xx01xx */
164 #define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ 167 #define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */
165 168
166 /* Manufacturers inside bank 2 have ids like 0x02xx02xx */ 169 /* Manufacturers inside bank 2 have ids like 0x02xx02xx */
167 170
168 /* Micron Technologies (INTEL compat.) */ 171 /* Micron Technologies (INTEL compat.) */
169 #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ 172 #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
170 #define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */ 173 #define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
171 174
172 #define AMD_ID_LV040B 0x4F /* 29LV040B ID */ 175 #define AMD_ID_LV040B 0x4F /* 29LV040B ID */
173 /* 4 Mbit, 512K x 8, */ 176 /* 4 Mbit, 512K x 8, */
174 /* 8 64K x 8 uniform sectors */ 177 /* 8 64K x 8 uniform sectors */
175 #define AMD_ID_F033C 0xA3 /* 29LV033C ID */ 178 #define AMD_ID_F033C 0xA3 /* 29LV033C ID */
176 /* 32 Mbit, 4Mbits x 8, */ 179 /* 32 Mbit, 4Mbits x 8, */
177 /* 64 64K x 8 uniform sectors */ 180 /* 64 64K x 8 uniform sectors */
178 #define AMD_ID_F065D 0x93 /* 29LV065D ID */ 181 #define AMD_ID_F065D 0x93 /* 29LV065D ID */
179 /* 64 Mbit, 8Mbits x 8, */ 182 /* 64 Mbit, 8Mbits x 8, */
180 /* 126 64K x 8 uniform sectors */ 183 /* 126 64K x 8 uniform sectors */
181 #define ATM_ID_LV040 0x13 /* 29LV040B ID */ 184 #define ATM_ID_LV040 0x13 /* 29LV040B ID */
182 /* 4 Mbit, 512K x 8, */ 185 /* 4 Mbit, 512K x 8, */
183 /* 8 64K x 8 uniform sectors */ 186 /* 8 64K x 8 uniform sectors */
184 #define AMD_ID_F040B 0xA4 /* 29F040B ID */ 187 #define AMD_ID_F040B 0xA4 /* 29F040B ID */
185 /* 4 Mbit, 512K x 8, */ 188 /* 4 Mbit, 512K x 8, */
186 /* 8 64K x 8 uniform sectors */ 189 /* 8 64K x 8 uniform sectors */
187 #define STM_ID_M29W040B 0xE3 /* M29W040B ID */ 190 #define STM_ID_M29W040B 0xE3 /* M29W040B ID */
188 /* 4 Mbit, 512K x 8, */ 191 /* 4 Mbit, 512K x 8, */
189 /* 8 64K x 8 uniform sectors */ 192 /* 8 64K x 8 uniform sectors */
190 #define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */ 193 #define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */
191 /* 8 Mbit, 512K x 16, */ 194 /* 8 Mbit, 512K x 16, */
192 /* 8 64K x 16 uniform sectors */ 195 /* 8 64K x 16 uniform sectors */
193 #define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */ 196 #define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
194 #define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */ 197 #define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
195 #define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */ 198 #define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
196 #define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */ 199 #define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */
197 #define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */ 200 #define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
198 201
199 #define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */ 202 #define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
200 203
201 #define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */ 204 #define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
202 #define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */ 205 #define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
203 206
204 #define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */ 207 #define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */
205 #define AMD_ID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */ 208 #define AMD_ID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */
206 209
207 #define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */ 210 #define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */
208 #define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */ 211 #define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */
209 212
210 #define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */ 213 #define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */
211 #define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */ 214 #define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
212 215
213 #define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */ 216 #define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */
214 #define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */ 217 #define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
215 218
216 #define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */ 219 #define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
217 #define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */ 220 #define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */
218 #define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */ 221 #define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
219 #define MX_ID_LV320B 0x22A822A8 /* 29LV320B by Macronix, AMD compatible */ 222 #define MX_ID_LV320B 0x22A822A8 /* 29LV320B by Macronix, AMD compatible */
220 223
221 #define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */ 224 #define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
222 #define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */ 225 #define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
223 #define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */ 226 #define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */
224 #define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */ 227 #define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */
225 #define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */ 228 #define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */
226 #define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */ 229 #define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */
227 230
228 #define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/ 231 #define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
229 #define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */ 232 #define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */
230 #define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */ 233 #define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */
231 #define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */ 234 #define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */
232 #define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */ 235 #define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */
233 #define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */ 236 #define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */
234 #define AMD_ID_LV640MT_2 0x22102210 /* 2nd ID word for AM29LV640MT at 0x38 */ 237 #define AMD_ID_LV640MT_2 0x22102210 /* 2nd ID word for AM29LV640MT at 0x38 */
235 #define AMD_ID_LV640MT_3 0x22012201 /* 3rd ID word for AM29LV640MT at 0x3c */ 238 #define AMD_ID_LV640MT_3 0x22012201 /* 3rd ID word for AM29LV640MT at 0x3c */
236 #define AMD_ID_LV640MB_2 0x22102210 /* 2nd ID word for AM29LV640MB at 0x38 */ 239 #define AMD_ID_LV640MB_2 0x22102210 /* 2nd ID word for AM29LV640MB at 0x38 */
237 #define AMD_ID_LV640MB_3 0x22002200 /* 3rd ID word for AM29LV640MB at 0x3c */ 240 #define AMD_ID_LV640MB_3 0x22002200 /* 3rd ID word for AM29LV640MB at 0x3c */
238 #define AMD_ID_LV128U_2 0x22122212 /* 2nd ID word for AM29LV128M at 0x38 */ 241 #define AMD_ID_LV128U_2 0x22122212 /* 2nd ID word for AM29LV128M at 0x38 */
239 #define AMD_ID_LV128U_3 0x22002200 /* 3rd ID word for AM29LV128M at 0x3c */ 242 #define AMD_ID_LV128U_3 0x22002200 /* 3rd ID word for AM29LV128M at 0x3c */
240 #define AMD_ID_LV256U_2 0x22122212 /* 2nd ID word for AM29LV256M at 0x38 */ 243 #define AMD_ID_LV256U_2 0x22122212 /* 2nd ID word for AM29LV256M at 0x38 */
241 #define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */ 244 #define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */
242 #define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */ 245 #define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */
243 #define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */ 246 #define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */
244 #define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */ 247 #define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */
245 #define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */ 248 #define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */
246 #define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */ 249 #define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */
247 #define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */ 250 #define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */
248 251
249 252
250 #define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */ 253 #define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
251 #define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */ 254 #define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */
252 255
253 #define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */ 256 #define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
254 #define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */ 257 #define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */
255 258
256 #define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */ 259 #define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
257 #define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */ 260 #define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */
258 #define ATM_ID_BV6416 0x000000D6 /* 49BV6416 ID */ 261 #define ATM_ID_BV6416 0x000000D6 /* 49BV6416 ID */
259 262
260 #define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */ 263 #define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
261 #define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */ 264 #define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
262 #define FUJI_ID_29LV650UE 0x22d722d7 /* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */ 265 #define FUJI_ID_29LV650UE 0x22d722d7 /* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
263 266
264 #define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */ 267 #define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
265 #define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */ 268 #define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
266 #define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */ 269 #define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
267 #define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */ 270 #define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */
268 #define SST_ID_xF1601 0x234B234B /* 39xF1601 ID (16M = 1M x 16 ) */ 271 #define SST_ID_xF1601 0x234B234B /* 39xF1601 ID (16M = 1M x 16 ) */
269 #define SST_ID_xF1602 0x234A234A /* 39xF1602 ID (16M = 1M x 16 ) */ 272 #define SST_ID_xF1602 0x234A234A /* 39xF1602 ID (16M = 1M x 16 ) */
270 #define SST_ID_xF3201 0x235B235B /* 39xF3201 ID (32M = 2M x 16 ) */ 273 #define SST_ID_xF3201 0x235B235B /* 39xF3201 ID (32M = 2M x 16 ) */
271 #define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */ 274 #define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */
272 #define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */ 275 #define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */
273 #define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */ 276 #define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */
274 #define SST_ID_xF020 0xBFD6BFD6 /* 39xF020 ID (256KB = 2Mbit x 8) */ 277 #define SST_ID_xF020 0xBFD6BFD6 /* 39xF020 ID (256KB = 2Mbit x 8) */
275 #define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */ 278 #define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */
276 279
277 #define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */ 280 #define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */
278 /* 8 64K x 8 uniform sectors */ 281 /* 8 64K x 8 uniform sectors */
279 282
280 #define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */ 283 #define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
281 #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */ 284 #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
282 #define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */ 285 #define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
283 #define STM_ID_29W320ET 0x22562256 /* M29W320ET ID (32 M, top boot sector) */ 286 #define STM_ID_29W320ET 0x22562256 /* M29W320ET ID (32 M, top boot sector) */
284 #define STM_ID_29W320EB 0x22572257 /* M29W320EB ID (32 M, bottom boot sect)*/ 287 #define STM_ID_29W320EB 0x22572257 /* M29W320EB ID (32 M, bottom boot sect)*/
285 #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */ 288 #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
286 #define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */ 289 #define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */
287 290
288 #define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ 291 #define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
289 #define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */ 292 #define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */
290 #define INTEL_ID_28F800B3B 0x88938893 /* 8M = 512K x 16 bottom boot sector */ 293 #define INTEL_ID_28F800B3B 0x88938893 /* 8M = 512K x 16 bottom boot sector */
291 #define INTEL_ID_28F160B3T 0x88908890 /* 16M = 1M x 16 top boot sector */ 294 #define INTEL_ID_28F160B3T 0x88908890 /* 16M = 1M x 16 top boot sector */
292 #define INTEL_ID_28F160B3B 0x88918891 /* 16M = 1M x 16 bottom boot sector */ 295 #define INTEL_ID_28F160B3B 0x88918891 /* 16M = 1M x 16 bottom boot sector */
293 #define INTEL_ID_28F320B3T 0x88968896 /* 32M = 2M x 16 top boot sector */ 296 #define INTEL_ID_28F320B3T 0x88968896 /* 32M = 2M x 16 top boot sector */
294 #define INTEL_ID_28F320B3B 0x88978897 /* 32M = 2M x 16 bottom boot sector */ 297 #define INTEL_ID_28F320B3B 0x88978897 /* 32M = 2M x 16 bottom boot sector */
295 #define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */ 298 #define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */
296 #define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */ 299 #define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */
297 #define INTEL_ID_28F160F3B 0x88F488F4 /* 16M = 1M x 16 bottom boot sector */ 300 #define INTEL_ID_28F160F3B 0x88F488F4 /* 16M = 1M x 16 bottom boot sector */
298 301
299 #define INTEL_ID_28F800C3T 0x88C088C0 /* 8M = 512K x 16 top boot sector */ 302 #define INTEL_ID_28F800C3T 0x88C088C0 /* 8M = 512K x 16 top boot sector */
300 #define INTEL_ID_28F800C3B 0x88C188C1 /* 8M = 512K x 16 bottom boot sector */ 303 #define INTEL_ID_28F800C3B 0x88C188C1 /* 8M = 512K x 16 bottom boot sector */
301 #define INTEL_ID_28F160C3T 0x88C288C2 /* 16M = 1M x 16 top boot sector */ 304 #define INTEL_ID_28F160C3T 0x88C288C2 /* 16M = 1M x 16 top boot sector */
302 #define INTEL_ID_28F160C3B 0x88C388C3 /* 16M = 1M x 16 bottom boot sector */ 305 #define INTEL_ID_28F160C3B 0x88C388C3 /* 16M = 1M x 16 bottom boot sector */
303 #define INTEL_ID_28F320C3T 0x88C488C4 /* 32M = 2M x 16 top boot sector */ 306 #define INTEL_ID_28F320C3T 0x88C488C4 /* 32M = 2M x 16 top boot sector */
304 #define INTEL_ID_28F320C3B 0x88C588C5 /* 32M = 2M x 16 bottom boot sector */ 307 #define INTEL_ID_28F320C3B 0x88C588C5 /* 32M = 2M x 16 bottom boot sector */
305 #define INTEL_ID_28F640C3T 0x88CC88CC /* 64M = 4M x 16 top boot sector */ 308 #define INTEL_ID_28F640C3T 0x88CC88CC /* 64M = 4M x 16 top boot sector */
306 #define INTEL_ID_28F640C3B 0x88CD88CD /* 64M = 4M x 16 bottom boot sector */ 309 #define INTEL_ID_28F640C3B 0x88CD88CD /* 64M = 4M x 16 bottom boot sector */
307 310
308 #define INTEL_ID_28F128J3 0x89188918 /* 16M = 8M x 16 x 128 */ 311 #define INTEL_ID_28F128J3 0x89188918 /* 16M = 8M x 16 x 128 */
309 #define INTEL_ID_28F320J5 0x00140014 /* 32M = 128K x 32 */ 312 #define INTEL_ID_28F320J5 0x00140014 /* 32M = 128K x 32 */
310 #define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */ 313 #define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */
311 #define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */ 314 #define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */
312 #define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */ 315 #define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */
313 #define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */ 316 #define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */
314 #define INTEL_ID_28F256J3A 0x001D001D /* 256M = 128K x 256 */ 317 #define INTEL_ID_28F256J3A 0x001D001D /* 256M = 128K x 256 */
315 #define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */ 318 #define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */
316 #define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */ 319 #define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */
317 #define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */ 320 #define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */
318 #define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */ 321 #define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */
319 #define INTEL_ID_28F64P30T 0x88178817 /* 64M = 32K x 255 + 32k x 4 */ 322 #define INTEL_ID_28F64P30T 0x88178817 /* 64M = 32K x 255 + 32k x 4 */
320 #define INTEL_ID_28F64P30B 0x881A881A /* 64M = 32K x 255 + 32k x 4 */ 323 #define INTEL_ID_28F64P30B 0x881A881A /* 64M = 32K x 255 + 32k x 4 */
321 #define INTEL_ID_28F128P30T 0x88188818 /* 128M = 64K x 255 + 32k x 4 */ 324 #define INTEL_ID_28F128P30T 0x88188818 /* 128M = 64K x 255 + 32k x 4 */
322 #define INTEL_ID_28F128P30B 0x881B881B /* 128M = 64K x 255 + 32k x 4 */ 325 #define INTEL_ID_28F128P30B 0x881B881B /* 128M = 64K x 255 + 32k x 4 */
323 #define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */ 326 #define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */
324 #define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */ 327 #define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */
325 328
326 #define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ 329 #define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */
327 #define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */ 330 #define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */
328 331
329 /* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */ 332 /* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
330 #define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */ 333 #define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */
331 #define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */ 334 #define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */
332 #define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */ 335 #define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */
333 /* LH28F008SCR-L85 1Mx8, 16 64k blocks */ 336 /* LH28F008SCR-L85 1Mx8, 16 64k blocks */
334 337
335 #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ 338 #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */
336 #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ 339 #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */
337 #define NUMONYX_256MBIT 0x8922 /* Numonyx P33/30 256MBit 65nm */ 340 #define NUMONYX_256MBIT 0x8922 /* Numonyx P33/30 256MBit 65nm */
338 341
339 /*----------------------------------------------------------------------- 342 /*-----------------------------------------------------------------------
340 * Internal FLASH identification codes 343 * Internal FLASH identification codes
341 * 344 *
342 * Be careful when adding new type! Odd numbers are "bottom boot sector" types! 345 * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
343 */ 346 */
344 347
345 #define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */ 348 #define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */
346 /* Bright Micro BM29F040 */ 349 /* Bright Micro BM29F040 */
347 /* Fujitsu MBM29F040A */ 350 /* Fujitsu MBM29F040A */
348 /* STM M29W040B */ 351 /* STM M29W040B */
349 /* SGS Thomson M29F040B */ 352 /* SGS Thomson M29F040B */
350 /* 8 64K x 8 uniform sectors */ 353 /* 8 64K x 8 uniform sectors */
351 #define FLASH_AM400T 0x0002 /* AMD AM29LV400 */ 354 #define FLASH_AM400T 0x0002 /* AMD AM29LV400 */
352 #define FLASH_AM400B 0x0003 355 #define FLASH_AM400B 0x0003
353 #define FLASH_AM800T 0x0004 /* AMD AM29LV800 */ 356 #define FLASH_AM800T 0x0004 /* AMD AM29LV800 */
354 #define FLASH_AM800B 0x0005 357 #define FLASH_AM800B 0x0005
355 #define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */ 358 #define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */
356 #define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */ 359 #define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */
357 #define FLASH_AM160T 0x0006 /* AMD AM29LV160 */ 360 #define FLASH_AM160T 0x0006 /* AMD AM29LV160 */
358 #define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */ 361 #define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
359 #define FLASH_AM160B 0x0007 362 #define FLASH_AM160B 0x0007
360 #define FLASH_AM320T 0x0008 /* AMD AM29LV320 */ 363 #define FLASH_AM320T 0x0008 /* AMD AM29LV320 */
361 #define FLASH_AM320B 0x0009 364 #define FLASH_AM320B 0x0009
362 365
363 #define FLASH_AM080 0x000A /* AMD Am29F080B */ 366 #define FLASH_AM080 0x000A /* AMD Am29F080B */
364 /* 16 64K x 8 uniform sectors */ 367 /* 16 64K x 8 uniform sectors */
365 368
366 #define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */ 369 #define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */
367 #define FLASH_AMDL322B 0x0011 370 #define FLASH_AMDL322B 0x0011
368 #define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */ 371 #define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */
369 #define FLASH_AMDL323B 0x0013 372 #define FLASH_AMDL323B 0x0013
370 #define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */ 373 #define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
371 #define FLASH_AMDL324B 0x0015 374 #define FLASH_AMDL324B 0x0015
372 375
373 #define FLASH_AMDLV033C 0x0018 376 #define FLASH_AMDLV033C 0x0018
374 #define FLASH_AMDLV065D 0x001A 377 #define FLASH_AMDLV065D 0x001A
375 378
376 #define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */ 379 #define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
377 #define FLASH_AMD016 0x0018 /* AMD AM29F016D */ 380 #define FLASH_AMD016 0x0018 /* AMD AM29F016D */
378 #define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/ 381 #define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/
379 #define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */ 382 #define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */
380 383
381 #define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */ 384 #define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
382 #define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */ 385 #define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
383 #define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */ 386 #define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */
384 #define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ 387 #define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
385 #define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ 388 #define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
386 #define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */ 389 #define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */
387 #define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */ 390 #define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */
388 #define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */ 391 #define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */
389 392
390 #define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */ 393 #define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
391 #define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */ 394 #define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */
392 #define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/ 395 #define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/
393 #define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/ 396 #define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/
394 #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ 397 #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
395 #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/ 398 #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
396 399
397 #define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ 400 #define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
398 #define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ 401 #define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
399 402
400 #define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */ 403 #define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */
401 #define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */ 404 #define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */
402 #define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */ 405 #define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */
403 #define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */ 406 #define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */
404 #define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */ 407 #define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */
405 #define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */ 408 #define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */
406 #define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */ 409 #define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */
407 #define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */ 410 #define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */
408 411
409 #define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ 412 #define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
410 #define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */ 413 #define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */
411 #define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */ 414 #define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */
412 #define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */ 415 #define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */
413 #define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */ 416 #define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */
414 #define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */ 417 #define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */
415 #define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */ 418 #define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */
416 #define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */ 419 #define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */
417 #define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */ 420 #define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */
418 #define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */ 421 #define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
419 #define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */ 422 #define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */
420 #define FLASH_AM065D 0x0093 423 #define FLASH_AM065D 0x0093
421 424
422 #define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */ 425 #define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
423 426
424 #define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */ 427 #define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */
425 #define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */ 428 #define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */
426 #define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */ 429 #define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */
427 #define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */ 430 #define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */
428 #define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */ 431 #define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */
429 #define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */ 432 #define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
430 #define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */ 433 #define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
431 #define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */ 434 #define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
432 #define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */ 435 #define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */
433 436
434 #define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */ 437 #define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */
435 #define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */ 438 #define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */
436 #define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */ 439 #define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */
437 440
438 #define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */ 441 #define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
439 #define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */ 442 #define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
440 #define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */ 443 #define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
441 #define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */ 444 #define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */
442 #define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */ 445 #define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
443 #define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */ 446 #define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
444 #define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */ 447 #define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */
445 #define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */ 448 #define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
446 #define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */ 449 #define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
447 #define FLASH_AMDL163B 0x00B3 450 #define FLASH_AMDL163B 0x00B3
448 #define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */ 451 #define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */
449 #define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */ 452 #define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */
450 #define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */ 453 #define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */
451 454
452 #define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */ 455 #define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */
453 #define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */ 456 #define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */
454 #define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */ 457 #define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */
455 #define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */ 458 #define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */
456 459
457 #define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ 460 #define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */
458 #define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ 461 #define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
459 #define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ 462 #define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
460 #define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */ 463 #define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
461 464
462 #define FLASH_STM32F4 0x00F2 /* STM32F4 Embedded Flash */ 465 #define FLASH_STM32F4 0x00F2 /* STM32F4 Embedded Flash */
463 #define FLASH_STM32F1 0x00F3 /* STM32F1 Embedded Flash */ 466 #define FLASH_STM32F1 0x00F3 /* STM32F1 Embedded Flash */
464 467
465 #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ 468 #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
466 469
467 470
468 /* manufacturer offsets 471 /* manufacturer offsets
469 */ 472 */
470 #define FLASH_MAN_AMD 0x00000000 /* AMD */ 473 #define FLASH_MAN_AMD 0x00000000 /* AMD */
471 #define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */ 474 #define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */
472 #define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */ 475 #define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */
473 #define FLASH_MAN_MX 0x00030000 /* MXIC */ 476 #define FLASH_MAN_MX 0x00030000 /* MXIC */
474 #define FLASH_MAN_STM 0x00040000 477 #define FLASH_MAN_STM 0x00040000
475 #define FLASH_MAN_TOSH 0x00050000 /* Toshiba */ 478 #define FLASH_MAN_TOSH 0x00050000 /* Toshiba */
476 #define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */ 479 #define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */
477 #define FLASH_MAN_SST 0x00100000 480 #define FLASH_MAN_SST 0x00100000
478 #define FLASH_MAN_INTEL 0x00300000 481 #define FLASH_MAN_INTEL 0x00300000
479 #define FLASH_MAN_MT 0x00400000 482 #define FLASH_MAN_MT 0x00400000
480 #define FLASH_MAN_SHARP 0x00500000 483 #define FLASH_MAN_SHARP 0x00500000
481 #define FLASH_MAN_ATM 0x00600000 484 #define FLASH_MAN_ATM 0x00600000
482 #define FLASH_MAN_CFI 0x01000000 485 #define FLASH_MAN_CFI 0x01000000
483 486
484 487
485 #define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ 488 #define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
486 #define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */ 489 #define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
487 490
488 #define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */ 491 #define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */
489 /* with AMD, Fujitsu and SST */ 492 /* with AMD, Fujitsu and SST */
490 /* (JEDEC standard commands ?) */ 493 /* (JEDEC standard commands ?) */
491 494
492 #define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */ 495 #define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */
493 496
494 /*----------------------------------------------------------------------- 497 /*-----------------------------------------------------------------------
495 * Timeout constants: 498 * Timeout constants:
496 * 499 *
497 * We can't find any specifications for maximum chip erase times, 500 * We can't find any specifications for maximum chip erase times,
498 * so these values are guestimates. 501 * so these values are guestimates.
499 */ 502 */
500 #define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */ 503 #define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */
501 #define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */ 504 #define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */
502 505
503 #endif /* !CONFIG_SYS_NO_FLASH */ 506 #endif /* !CONFIG_SYS_NO_FLASH */
504 507
505 #endif /* _FLASH_H_ */ 508 #endif /* _FLASH_H_ */
506 509
include/linux/mtd/mtd.h
Diff comments   View file @ d858799
1 /* 1 /*
2 * Copyright ยฉ 1999-2010 David Woodhouse <dwmw2@infradead.org> et al. 2 * Copyright ยฉ 1999-2010 David Woodhouse <dwmw2@infradead.org> et al.
3 * 3 *
4 * Released under GPL 4 * Released under GPL
5 * 5 *
6 */ 6 */
7 7
8 #ifndef __MTD_MTD_H__ 8 #ifndef __MTD_MTD_H__
9 #define __MTD_MTD_H__ 9 #define __MTD_MTD_H__
10 10
11 #ifndef __UBOOT__ 11 #ifndef __UBOOT__
12 #include <linux/types.h> 12 #include <linux/types.h>
13 #include <linux/uio.h> 13 #include <linux/uio.h>
14 #include <linux/notifier.h> 14 #include <linux/notifier.h>
15 #include <linux/device.h> 15 #include <linux/device.h>
16 16
17 #include <mtd/mtd-abi.h> 17 #include <mtd/mtd-abi.h>
18 18
19 #include <asm/div64.h> 19 #include <asm/div64.h>
20 #else 20 #else
21 #include <linux/compat.h> 21 #include <linux/compat.h>
22 #include <mtd/mtd-abi.h> 22 #include <mtd/mtd-abi.h>
23 #include <asm/errno.h> 23 #include <asm/errno.h>
24 #include <div64.h> 24 #include <div64.h>
25 25
26 #define MAX_MTD_DEVICES 32 26 #define MAX_MTD_DEVICES 32
27 #endif 27 #endif
28 28
29 #define MTD_ERASE_PENDING 0x01 29 #define MTD_ERASE_PENDING 0x01
30 #define MTD_ERASING 0x02 30 #define MTD_ERASING 0x02
31 #define MTD_ERASE_SUSPEND 0x04 31 #define MTD_ERASE_SUSPEND 0x04
32 #define MTD_ERASE_DONE 0x08 32 #define MTD_ERASE_DONE 0x08
33 #define MTD_ERASE_FAILED 0x10 33 #define MTD_ERASE_FAILED 0x10
34 34
35 #define MTD_FAIL_ADDR_UNKNOWN -1LL 35 #define MTD_FAIL_ADDR_UNKNOWN -1LL
36 36
37 /* 37 /*
38 * If the erase fails, fail_addr might indicate exactly which block failed. If 38 * If the erase fails, fail_addr might indicate exactly which block failed. If
39 * fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level 39 * fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level
40 * or was not specific to any particular block. 40 * or was not specific to any particular block.
41 */ 41 */
42 struct erase_info { 42 struct erase_info {
43 struct mtd_info *mtd; 43 struct mtd_info *mtd;
44 uint64_t addr; 44 uint64_t addr;
45 uint64_t len; 45 uint64_t len;
46 uint64_t fail_addr; 46 uint64_t fail_addr;
47 u_long time; 47 u_long time;
48 u_long retries; 48 u_long retries;
49 unsigned dev; 49 unsigned dev;
50 unsigned cell; 50 unsigned cell;
51 void (*callback) (struct erase_info *self); 51 void (*callback) (struct erase_info *self);
52 u_long priv; 52 u_long priv;
53 u_char state; 53 u_char state;
54 struct erase_info *next; 54 struct erase_info *next;
55 int scrub; 55 int scrub;
56 }; 56 };
57 57
58 struct mtd_erase_region_info { 58 struct mtd_erase_region_info {
59 uint64_t offset; /* At which this region starts, from the beginning of the MTD */ 59 uint64_t offset; /* At which this region starts, from the beginning of the MTD */
60 uint32_t erasesize; /* For this region */ 60 uint32_t erasesize; /* For this region */
61 uint32_t numblocks; /* Number of blocks of erasesize in this region */ 61 uint32_t numblocks; /* Number of blocks of erasesize in this region */
62 unsigned long *lockmap; /* If keeping bitmap of locks */ 62 unsigned long *lockmap; /* If keeping bitmap of locks */
63 }; 63 };
64 64
65 /** 65 /**
66 * struct mtd_oob_ops - oob operation operands 66 * struct mtd_oob_ops - oob operation operands
67 * @mode: operation mode 67 * @mode: operation mode
68 * 68 *
69 * @len: number of data bytes to write/read 69 * @len: number of data bytes to write/read
70 * 70 *
71 * @retlen: number of data bytes written/read 71 * @retlen: number of data bytes written/read
72 * 72 *
73 * @ooblen: number of oob bytes to write/read 73 * @ooblen: number of oob bytes to write/read
74 * @oobretlen: number of oob bytes written/read 74 * @oobretlen: number of oob bytes written/read
75 * @ooboffs: offset of oob data in the oob area (only relevant when 75 * @ooboffs: offset of oob data in the oob area (only relevant when
76 * mode = MTD_OPS_PLACE_OOB or MTD_OPS_RAW) 76 * mode = MTD_OPS_PLACE_OOB or MTD_OPS_RAW)
77 * @datbuf: data buffer - if NULL only oob data are read/written 77 * @datbuf: data buffer - if NULL only oob data are read/written
78 * @oobbuf: oob data buffer 78 * @oobbuf: oob data buffer
79 * 79 *
80 * Note, it is allowed to read more than one OOB area at one go, but not write. 80 * Note, it is allowed to read more than one OOB area at one go, but not write.
81 * The interface assumes that the OOB write requests program only one page's 81 * The interface assumes that the OOB write requests program only one page's
82 * OOB area. 82 * OOB area.
83 */ 83 */
84 struct mtd_oob_ops { 84 struct mtd_oob_ops {
85 unsigned int mode; 85 unsigned int mode;
86 size_t len; 86 size_t len;
87 size_t retlen; 87 size_t retlen;
88 size_t ooblen; 88 size_t ooblen;
89 size_t oobretlen; 89 size_t oobretlen;
90 uint32_t ooboffs; 90 uint32_t ooboffs;
91 uint8_t *datbuf; 91 uint8_t *datbuf;
92 uint8_t *oobbuf; 92 uint8_t *oobbuf;
93 }; 93 };
94 94
95 #ifdef CONFIG_SYS_NAND_MAX_OOBFREE 95 #ifdef CONFIG_SYS_NAND_MAX_OOBFREE
96 #define MTD_MAX_OOBFREE_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_OOBFREE 96 #define MTD_MAX_OOBFREE_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_OOBFREE
97 #else 97 #else
98 #define MTD_MAX_OOBFREE_ENTRIES_LARGE 32 98 #define MTD_MAX_OOBFREE_ENTRIES_LARGE 32
99 #endif 99 #endif
100 100
101 #ifdef CONFIG_SYS_NAND_MAX_ECCPOS 101 #ifdef CONFIG_SYS_NAND_MAX_ECCPOS
102 #define MTD_MAX_ECCPOS_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_ECCPOS 102 #define MTD_MAX_ECCPOS_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_ECCPOS
103 #else 103 #else
104 #define MTD_MAX_ECCPOS_ENTRIES_LARGE 680 104 #define MTD_MAX_ECCPOS_ENTRIES_LARGE 680
105 #endif 105 #endif
106 106
107 /* 107 /*
108 * Internal ECC layout control structure. For historical reasons, there is a 108 * Internal ECC layout control structure. For historical reasons, there is a
109 * similar, smaller struct nand_ecclayout_user (in mtd-abi.h) that is retained 109 * similar, smaller struct nand_ecclayout_user (in mtd-abi.h) that is retained
110 * for export to user-space via the ECCGETLAYOUT ioctl. 110 * for export to user-space via the ECCGETLAYOUT ioctl.
111 * nand_ecclayout should be expandable in the future simply by the above macros. 111 * nand_ecclayout should be expandable in the future simply by the above macros.
112 */ 112 */
113 struct nand_ecclayout { 113 struct nand_ecclayout {
114 __u32 eccbytes; 114 __u32 eccbytes;
115 __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE]; 115 __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
116 __u32 oobavail; 116 __u32 oobavail;
117 struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE]; 117 struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
118 }; 118 };
119 119
120 struct module; /* only needed for owner field in mtd_info */ 120 struct module; /* only needed for owner field in mtd_info */
121 121
122 struct mtd_info { 122 struct mtd_info {
123 u_char type; 123 u_char type;
124 uint32_t flags; 124 uint32_t flags;
125 uint64_t size; // Total size of the MTD 125 uint64_t size; // Total size of the MTD
126 126
127 /* "Major" erase size for the device. Naรฏve users may take this 127 /* "Major" erase size for the device. Naรฏve users may take this
128 * to be the only erase size available, or may use the more detailed 128 * to be the only erase size available, or may use the more detailed
129 * information below if they desire 129 * information below if they desire
130 */ 130 */
131 uint32_t erasesize; 131 uint32_t erasesize;
132 /* Minimal writable flash unit size. In case of NOR flash it is 1 (even 132 /* Minimal writable flash unit size. In case of NOR flash it is 1 (even
133 * though individual bits can be cleared), in case of NAND flash it is 133 * though individual bits can be cleared), in case of NAND flash it is
134 * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR 134 * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR
135 * it is of ECC block size, etc. It is illegal to have writesize = 0. 135 * it is of ECC block size, etc. It is illegal to have writesize = 0.
136 * Any driver registering a struct mtd_info must ensure a writesize of 136 * Any driver registering a struct mtd_info must ensure a writesize of
137 * 1 or larger. 137 * 1 or larger.
138 */ 138 */
139 uint32_t writesize; 139 uint32_t writesize;
140 140
141 /* 141 /*
142 * Size of the write buffer used by the MTD. MTD devices having a write 142 * Size of the write buffer used by the MTD. MTD devices having a write
143 * buffer can write multiple writesize chunks at a time. E.g. while 143 * buffer can write multiple writesize chunks at a time. E.g. while
144 * writing 4 * writesize bytes to a device with 2 * writesize bytes 144 * writing 4 * writesize bytes to a device with 2 * writesize bytes
145 * buffer the MTD driver can (but doesn't have to) do 2 writesize 145 * buffer the MTD driver can (but doesn't have to) do 2 writesize
146 * operations, but not 4. Currently, all NANDs have writebufsize 146 * operations, but not 4. Currently, all NANDs have writebufsize
147 * equivalent to writesize (NAND page size). Some NOR flashes do have 147 * equivalent to writesize (NAND page size). Some NOR flashes do have
148 * writebufsize greater than writesize. 148 * writebufsize greater than writesize.
149 */ 149 */
150 uint32_t writebufsize; 150 uint32_t writebufsize;
151 151
152 uint32_t oobsize; // Amount of OOB data per block (e.g. 16) 152 uint32_t oobsize; // Amount of OOB data per block (e.g. 16)
153 uint32_t oobavail; // Available OOB bytes per block 153 uint32_t oobavail; // Available OOB bytes per block
154 154
155 /* 155 /*
156 * If erasesize is a power of 2 then the shift is stored in 156 * If erasesize is a power of 2 then the shift is stored in
157 * erasesize_shift otherwise erasesize_shift is zero. Ditto writesize. 157 * erasesize_shift otherwise erasesize_shift is zero. Ditto writesize.
158 */ 158 */
159 unsigned int erasesize_shift; 159 unsigned int erasesize_shift;
160 unsigned int writesize_shift; 160 unsigned int writesize_shift;
161 /* Masks based on erasesize_shift and writesize_shift */ 161 /* Masks based on erasesize_shift and writesize_shift */
162 unsigned int erasesize_mask; 162 unsigned int erasesize_mask;
163 unsigned int writesize_mask; 163 unsigned int writesize_mask;
164 164
165 /* 165 /*
166 * read ops return -EUCLEAN if max number of bitflips corrected on any 166 * read ops return -EUCLEAN if max number of bitflips corrected on any
167 * one region comprising an ecc step equals or exceeds this value. 167 * one region comprising an ecc step equals or exceeds this value.
168 * Settable by driver, else defaults to ecc_strength. User can override 168 * Settable by driver, else defaults to ecc_strength. User can override
169 * in sysfs. N.B. The meaning of the -EUCLEAN return code has changed; 169 * in sysfs. N.B. The meaning of the -EUCLEAN return code has changed;
170 * see Documentation/ABI/testing/sysfs-class-mtd for more detail. 170 * see Documentation/ABI/testing/sysfs-class-mtd for more detail.
171 */ 171 */
172 unsigned int bitflip_threshold; 172 unsigned int bitflip_threshold;
173 173
174 // Kernel-only stuff starts here. 174 // Kernel-only stuff starts here.
175 #ifndef __UBOOT__ 175 #ifndef __UBOOT__
176 const char *name; 176 const char *name;
177 #else 177 #else
178 char *name; 178 char *name;
179 #endif 179 #endif
180 int index; 180 int index;
181 181
182 /* ECC layout structure pointer - read only! */ 182 /* ECC layout structure pointer - read only! */
183 struct nand_ecclayout *ecclayout; 183 struct nand_ecclayout *ecclayout;
184 184
185 /* the ecc step size. */ 185 /* the ecc step size. */
186 unsigned int ecc_step_size; 186 unsigned int ecc_step_size;
187 187
188 /* max number of correctible bit errors per ecc step */ 188 /* max number of correctible bit errors per ecc step */
189 unsigned int ecc_strength; 189 unsigned int ecc_strength;
190 190
191 /* Data for variable erase regions. If numeraseregions is zero, 191 /* Data for variable erase regions. If numeraseregions is zero,
192 * it means that the whole device has erasesize as given above. 192 * it means that the whole device has erasesize as given above.
193 */ 193 */
194 int numeraseregions; 194 int numeraseregions;
195 struct mtd_erase_region_info *eraseregions; 195 struct mtd_erase_region_info *eraseregions;
196 196
197 /* 197 /*
198 * Do not call via these pointers, use corresponding mtd_*() 198 * Do not call via these pointers, use corresponding mtd_*()
199 * wrappers instead. 199 * wrappers instead.
200 */ 200 */
201 int (*_erase) (struct mtd_info *mtd, struct erase_info *instr); 201 int (*_erase) (struct mtd_info *mtd, struct erase_info *instr);
202 #ifndef __UBOOT__ 202 #ifndef __UBOOT__
203 int (*_point) (struct mtd_info *mtd, loff_t from, size_t len, 203 int (*_point) (struct mtd_info *mtd, loff_t from, size_t len,
204 size_t *retlen, void **virt, resource_size_t *phys); 204 size_t *retlen, void **virt, resource_size_t *phys);
205 int (*_unpoint) (struct mtd_info *mtd, loff_t from, size_t len); 205 int (*_unpoint) (struct mtd_info *mtd, loff_t from, size_t len);
206 #endif 206 #endif
207 unsigned long (*_get_unmapped_area) (struct mtd_info *mtd, 207 unsigned long (*_get_unmapped_area) (struct mtd_info *mtd,
208 unsigned long len, 208 unsigned long len,
209 unsigned long offset, 209 unsigned long offset,
210 unsigned long flags); 210 unsigned long flags);
211 int (*_read) (struct mtd_info *mtd, loff_t from, size_t len, 211 int (*_read) (struct mtd_info *mtd, loff_t from, size_t len,
212 size_t *retlen, u_char *buf); 212 size_t *retlen, u_char *buf);
213 int (*_write) (struct mtd_info *mtd, loff_t to, size_t len, 213 int (*_write) (struct mtd_info *mtd, loff_t to, size_t len,
214 size_t *retlen, const u_char *buf); 214 size_t *retlen, const u_char *buf);
215 int (*_panic_write) (struct mtd_info *mtd, loff_t to, size_t len, 215 int (*_panic_write) (struct mtd_info *mtd, loff_t to, size_t len,
216 size_t *retlen, const u_char *buf); 216 size_t *retlen, const u_char *buf);
217 int (*_read_oob) (struct mtd_info *mtd, loff_t from, 217 int (*_read_oob) (struct mtd_info *mtd, loff_t from,
218 struct mtd_oob_ops *ops); 218 struct mtd_oob_ops *ops);
219 int (*_write_oob) (struct mtd_info *mtd, loff_t to, 219 int (*_write_oob) (struct mtd_info *mtd, loff_t to,
220 struct mtd_oob_ops *ops); 220 struct mtd_oob_ops *ops);
221 int (*_get_fact_prot_info) (struct mtd_info *mtd, size_t len, 221 int (*_get_fact_prot_info) (struct mtd_info *mtd, size_t len,
222 size_t *retlen, struct otp_info *buf); 222 size_t *retlen, struct otp_info *buf);
223 int (*_read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, 223 int (*_read_fact_prot_reg) (struct mtd_info *mtd, loff_t from,
224 size_t len, size_t *retlen, u_char *buf); 224 size_t len, size_t *retlen, u_char *buf);
225 int (*_get_user_prot_info) (struct mtd_info *mtd, size_t len, 225 int (*_get_user_prot_info) (struct mtd_info *mtd, size_t len,
226 size_t *retlen, struct otp_info *buf); 226 size_t *retlen, struct otp_info *buf);
227 int (*_read_user_prot_reg) (struct mtd_info *mtd, loff_t from, 227 int (*_read_user_prot_reg) (struct mtd_info *mtd, loff_t from,
228 size_t len, size_t *retlen, u_char *buf); 228 size_t len, size_t *retlen, u_char *buf);
229 int (*_write_user_prot_reg) (struct mtd_info *mtd, loff_t to, 229 int (*_write_user_prot_reg) (struct mtd_info *mtd, loff_t to,
230 size_t len, size_t *retlen, u_char *buf); 230 size_t len, size_t *retlen, u_char *buf);
231 int (*_lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, 231 int (*_lock_user_prot_reg) (struct mtd_info *mtd, loff_t from,
232 size_t len); 232 size_t len);
233 #ifndef __UBOOT__ 233 #ifndef __UBOOT__
234 int (*_writev) (struct mtd_info *mtd, const struct kvec *vecs, 234 int (*_writev) (struct mtd_info *mtd, const struct kvec *vecs,
235 unsigned long count, loff_t to, size_t *retlen); 235 unsigned long count, loff_t to, size_t *retlen);
236 #endif 236 #endif
237 void (*_sync) (struct mtd_info *mtd); 237 void (*_sync) (struct mtd_info *mtd);
238 int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); 238 int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
239 int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); 239 int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
240 int (*_is_locked) (struct mtd_info *mtd, loff_t ofs, uint64_t len); 240 int (*_is_locked) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
241 int (*_block_isreserved) (struct mtd_info *mtd, loff_t ofs); 241 int (*_block_isreserved) (struct mtd_info *mtd, loff_t ofs);
242 int (*_block_isbad) (struct mtd_info *mtd, loff_t ofs); 242 int (*_block_isbad) (struct mtd_info *mtd, loff_t ofs);
243 int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs); 243 int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
244 #ifndef __UBOOT__ 244 #ifndef __UBOOT__
245 int (*_suspend) (struct mtd_info *mtd); 245 int (*_suspend) (struct mtd_info *mtd);
246 void (*_resume) (struct mtd_info *mtd); 246 void (*_resume) (struct mtd_info *mtd);
247 void (*_reboot) (struct mtd_info *mtd); 247 void (*_reboot) (struct mtd_info *mtd);
248 #endif 248 #endif
249 /* 249 /*
250 * If the driver is something smart, like UBI, it may need to maintain 250 * If the driver is something smart, like UBI, it may need to maintain
251 * its own reference counting. The below functions are only for driver. 251 * its own reference counting. The below functions are only for driver.
252 */ 252 */
253 int (*_get_device) (struct mtd_info *mtd); 253 int (*_get_device) (struct mtd_info *mtd);
254 void (*_put_device) (struct mtd_info *mtd); 254 void (*_put_device) (struct mtd_info *mtd);
255 255
256 #ifndef __UBOOT__ 256 #ifndef __UBOOT__
257 /* Backing device capabilities for this device 257 /* Backing device capabilities for this device
258 * - provides mmap capabilities 258 * - provides mmap capabilities
259 */ 259 */
260 struct backing_dev_info *backing_dev_info; 260 struct backing_dev_info *backing_dev_info;
261 261
262 struct notifier_block reboot_notifier; /* default mode before reboot */ 262 struct notifier_block reboot_notifier; /* default mode before reboot */
263 #endif 263 #endif
264 264
265 /* ECC status information */ 265 /* ECC status information */
266 struct mtd_ecc_stats ecc_stats; 266 struct mtd_ecc_stats ecc_stats;
267 /* Subpage shift (NAND) */ 267 /* Subpage shift (NAND) */
268 int subpage_sft; 268 int subpage_sft;
269 269
270 void *priv; 270 void *priv;
271 271
272 struct module *owner; 272 struct module *owner;
273 #ifndef __UBOOT__ 273 #ifndef __UBOOT__
274 struct device dev; 274 struct device dev;
275 #else
276 struct udevice *dev;
275 #endif 277 #endif
276 int usecount; 278 int usecount;
277 }; 279 };
278 280
279 int mtd_erase(struct mtd_info *mtd, struct erase_info *instr); 281 int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
280 #ifndef __UBOOT__ 282 #ifndef __UBOOT__
281 int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, 283 int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
282 void **virt, resource_size_t *phys); 284 void **virt, resource_size_t *phys);
283 int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len); 285 int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len);
284 #endif 286 #endif
285 unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len, 287 unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len,
286 unsigned long offset, unsigned long flags); 288 unsigned long offset, unsigned long flags);
287 int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, 289 int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
288 u_char *buf); 290 u_char *buf);
289 int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, 291 int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
290 const u_char *buf); 292 const u_char *buf);
291 int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, 293 int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
292 const u_char *buf); 294 const u_char *buf);
293 295
294 int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); 296 int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
295 297
296 static inline int mtd_write_oob(struct mtd_info *mtd, loff_t to, 298 static inline int mtd_write_oob(struct mtd_info *mtd, loff_t to,
297 struct mtd_oob_ops *ops) 299 struct mtd_oob_ops *ops)
298 { 300 {
299 ops->retlen = ops->oobretlen = 0; 301 ops->retlen = ops->oobretlen = 0;
300 if (!mtd->_write_oob) 302 if (!mtd->_write_oob)
301 return -EOPNOTSUPP; 303 return -EOPNOTSUPP;
302 if (!(mtd->flags & MTD_WRITEABLE)) 304 if (!(mtd->flags & MTD_WRITEABLE))
303 return -EROFS; 305 return -EROFS;
304 return mtd->_write_oob(mtd, to, ops); 306 return mtd->_write_oob(mtd, to, ops);
305 } 307 }
306 308
307 int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen, 309 int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
308 struct otp_info *buf); 310 struct otp_info *buf);
309 int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, 311 int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
310 size_t *retlen, u_char *buf); 312 size_t *retlen, u_char *buf);
311 int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen, 313 int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
312 struct otp_info *buf); 314 struct otp_info *buf);
313 int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, 315 int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
314 size_t *retlen, u_char *buf); 316 size_t *retlen, u_char *buf);
315 int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len, 317 int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
316 size_t *retlen, u_char *buf); 318 size_t *retlen, u_char *buf);
317 int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len); 319 int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len);
318 320
319 #ifndef __UBOOT__ 321 #ifndef __UBOOT__
320 int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, 322 int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
321 unsigned long count, loff_t to, size_t *retlen); 323 unsigned long count, loff_t to, size_t *retlen);
322 #endif 324 #endif
323 325
324 static inline void mtd_sync(struct mtd_info *mtd) 326 static inline void mtd_sync(struct mtd_info *mtd)
325 { 327 {
326 if (mtd->_sync) 328 if (mtd->_sync)
327 mtd->_sync(mtd); 329 mtd->_sync(mtd);
328 } 330 }
329 331
330 int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 332 int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
331 int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 333 int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
332 int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len); 334 int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
333 int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs); 335 int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs);
334 int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs); 336 int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs);
335 int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs); 337 int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs);
336 338
337 #ifndef __UBOOT__ 339 #ifndef __UBOOT__
338 static inline int mtd_suspend(struct mtd_info *mtd) 340 static inline int mtd_suspend(struct mtd_info *mtd)
339 { 341 {
340 return mtd->_suspend ? mtd->_suspend(mtd) : 0; 342 return mtd->_suspend ? mtd->_suspend(mtd) : 0;
341 } 343 }
342 344
343 static inline void mtd_resume(struct mtd_info *mtd) 345 static inline void mtd_resume(struct mtd_info *mtd)
344 { 346 {
345 if (mtd->_resume) 347 if (mtd->_resume)
346 mtd->_resume(mtd); 348 mtd->_resume(mtd);
347 } 349 }
348 #endif 350 #endif
349 351
350 static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd) 352 static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd)
351 { 353 {
352 if (mtd->erasesize_shift) 354 if (mtd->erasesize_shift)
353 return sz >> mtd->erasesize_shift; 355 return sz >> mtd->erasesize_shift;
354 do_div(sz, mtd->erasesize); 356 do_div(sz, mtd->erasesize);
355 return sz; 357 return sz;
356 } 358 }
357 359
358 static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd) 360 static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
359 { 361 {
360 if (mtd->erasesize_shift) 362 if (mtd->erasesize_shift)
361 return sz & mtd->erasesize_mask; 363 return sz & mtd->erasesize_mask;
362 return do_div(sz, mtd->erasesize); 364 return do_div(sz, mtd->erasesize);
363 } 365 }
364 366
365 static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd) 367 static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd)
366 { 368 {
367 if (mtd->writesize_shift) 369 if (mtd->writesize_shift)
368 return sz >> mtd->writesize_shift; 370 return sz >> mtd->writesize_shift;
369 do_div(sz, mtd->writesize); 371 do_div(sz, mtd->writesize);
370 return sz; 372 return sz;
371 } 373 }
372 374
373 static inline uint32_t mtd_mod_by_ws(uint64_t sz, struct mtd_info *mtd) 375 static inline uint32_t mtd_mod_by_ws(uint64_t sz, struct mtd_info *mtd)
374 { 376 {
375 if (mtd->writesize_shift) 377 if (mtd->writesize_shift)
376 return sz & mtd->writesize_mask; 378 return sz & mtd->writesize_mask;
377 return do_div(sz, mtd->writesize); 379 return do_div(sz, mtd->writesize);
378 } 380 }
379 381
380 static inline int mtd_has_oob(const struct mtd_info *mtd) 382 static inline int mtd_has_oob(const struct mtd_info *mtd)
381 { 383 {
382 return mtd->_read_oob && mtd->_write_oob; 384 return mtd->_read_oob && mtd->_write_oob;
383 } 385 }
384 386
385 static inline int mtd_type_is_nand(const struct mtd_info *mtd) 387 static inline int mtd_type_is_nand(const struct mtd_info *mtd)
386 { 388 {
387 return mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH; 389 return mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH;
388 } 390 }
389 391
390 static inline int mtd_can_have_bb(const struct mtd_info *mtd) 392 static inline int mtd_can_have_bb(const struct mtd_info *mtd)
391 { 393 {
392 return !!mtd->_block_isbad; 394 return !!mtd->_block_isbad;
393 } 395 }
394 396
395 /* Kernel-side ioctl definitions */ 397 /* Kernel-side ioctl definitions */
396 398
397 struct mtd_partition; 399 struct mtd_partition;
398 struct mtd_part_parser_data; 400 struct mtd_part_parser_data;
399 401
400 extern int mtd_device_parse_register(struct mtd_info *mtd, 402 extern int mtd_device_parse_register(struct mtd_info *mtd,
401 const char * const *part_probe_types, 403 const char * const *part_probe_types,
402 struct mtd_part_parser_data *parser_data, 404 struct mtd_part_parser_data *parser_data,
403 const struct mtd_partition *defparts, 405 const struct mtd_partition *defparts,
404 int defnr_parts); 406 int defnr_parts);
405 #define mtd_device_register(master, parts, nr_parts) \ 407 #define mtd_device_register(master, parts, nr_parts) \
406 mtd_device_parse_register(master, NULL, NULL, parts, nr_parts) 408 mtd_device_parse_register(master, NULL, NULL, parts, nr_parts)
407 extern int mtd_device_unregister(struct mtd_info *master); 409 extern int mtd_device_unregister(struct mtd_info *master);
408 extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); 410 extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num);
409 extern int __get_mtd_device(struct mtd_info *mtd); 411 extern int __get_mtd_device(struct mtd_info *mtd);
410 extern void __put_mtd_device(struct mtd_info *mtd); 412 extern void __put_mtd_device(struct mtd_info *mtd);
411 extern struct mtd_info *get_mtd_device_nm(const char *name); 413 extern struct mtd_info *get_mtd_device_nm(const char *name);
412 extern void put_mtd_device(struct mtd_info *mtd); 414 extern void put_mtd_device(struct mtd_info *mtd);
413 415
414 416
415 #ifndef __UBOOT__ 417 #ifndef __UBOOT__
416 struct mtd_notifier { 418 struct mtd_notifier {
417 void (*add)(struct mtd_info *mtd); 419 void (*add)(struct mtd_info *mtd);
418 void (*remove)(struct mtd_info *mtd); 420 void (*remove)(struct mtd_info *mtd);
419 struct list_head list; 421 struct list_head list;
420 }; 422 };
421 423
422 424
423 extern void register_mtd_user (struct mtd_notifier *new); 425 extern void register_mtd_user (struct mtd_notifier *new);
424 extern int unregister_mtd_user (struct mtd_notifier *old); 426 extern int unregister_mtd_user (struct mtd_notifier *old);
425 #endif 427 #endif
426 void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size); 428 void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size);
427 429
428 #ifdef CONFIG_MTD_PARTITIONS 430 #ifdef CONFIG_MTD_PARTITIONS
429 void mtd_erase_callback(struct erase_info *instr); 431 void mtd_erase_callback(struct erase_info *instr);
430 #else 432 #else
431 static inline void mtd_erase_callback(struct erase_info *instr) 433 static inline void mtd_erase_callback(struct erase_info *instr)
432 { 434 {
433 if (instr->callback) 435 if (instr->callback)
434 instr->callback(instr); 436 instr->callback(instr);
435 } 437 }
436 #endif 438 #endif
437 439
438 #ifdef __UBOOT__ 440 #ifdef __UBOOT__
439 /* 441 /*
440 * Debugging macro and defines 442 * Debugging macro and defines
441 */ 443 */
442 #define MTD_DEBUG_LEVEL0 (0) /* Quiet */ 444 #define MTD_DEBUG_LEVEL0 (0) /* Quiet */
443 #define MTD_DEBUG_LEVEL1 (1) /* Audible */ 445 #define MTD_DEBUG_LEVEL1 (1) /* Audible */
444 #define MTD_DEBUG_LEVEL2 (2) /* Loud */ 446 #define MTD_DEBUG_LEVEL2 (2) /* Loud */
445 #define MTD_DEBUG_LEVEL3 (3) /* Noisy */ 447 #define MTD_DEBUG_LEVEL3 (3) /* Noisy */
446 448
447 #ifdef CONFIG_MTD_DEBUG 449 #ifdef CONFIG_MTD_DEBUG
448 #define pr_debug(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) 450 #define pr_debug(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args)
449 #define MTDDEBUG(n, args...) \ 451 #define MTDDEBUG(n, args...) \
450 do { \ 452 do { \
451 if (n <= CONFIG_MTD_DEBUG_VERBOSE) \ 453 if (n <= CONFIG_MTD_DEBUG_VERBOSE) \
452 printk(KERN_INFO args); \ 454 printk(KERN_INFO args); \
453 } while(0) 455 } while(0)
454 #else /* CONFIG_MTD_DEBUG */ 456 #else /* CONFIG_MTD_DEBUG */
455 #define pr_debug(args...) 457 #define pr_debug(args...)
456 #define MTDDEBUG(n, args...) \ 458 #define MTDDEBUG(n, args...) \
457 do { \ 459 do { \
458 if (0) \ 460 if (0) \
459 printk(KERN_INFO args); \ 461 printk(KERN_INFO args); \
460 } while(0) 462 } while(0)
461 #endif /* CONFIG_MTD_DEBUG */ 463 #endif /* CONFIG_MTD_DEBUG */
462 #define pr_info(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) 464 #define pr_info(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args)
463 #define pr_warn(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) 465 #define pr_warn(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args)
464 #define pr_err(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) 466 #define pr_err(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args)
465 #define pr_crit(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) 467 #define pr_crit(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args)
466 #define pr_cont(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) 468 #define pr_cont(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args)
467 #define pr_notice(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) 469 #define pr_notice(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args)
468 #endif 470 #endif
469 471
470 static inline int mtd_is_bitflip(int err) { 472 static inline int mtd_is_bitflip(int err) {
471 return err == -EUCLEAN; 473 return err == -EUCLEAN;
472 } 474 }
473 475
474 static inline int mtd_is_eccerr(int err) { 476 static inline int mtd_is_eccerr(int err) {
475 return err == -EBADMSG; 477 return err == -EBADMSG;
476 } 478 }
477 479
478 static inline int mtd_is_bitflip_or_eccerr(int err) { 480 static inline int mtd_is_bitflip_or_eccerr(int err) {
479 return mtd_is_bitflip(err) || mtd_is_eccerr(err); 481 return mtd_is_bitflip(err) || mtd_is_eccerr(err);
480 } 482 }
481 483
482 unsigned mtd_mmap_capabilities(struct mtd_info *mtd); 484 unsigned mtd_mmap_capabilities(struct mtd_info *mtd);
483 485
484 #ifdef __UBOOT__ 486 #ifdef __UBOOT__
485 /* drivers/mtd/mtdcore.h */ 487 /* drivers/mtd/mtdcore.h */
486 int add_mtd_device(struct mtd_info *mtd); 488 int add_mtd_device(struct mtd_info *mtd);
487 int del_mtd_device(struct mtd_info *mtd); 489 int del_mtd_device(struct mtd_info *mtd);
488 int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); 490 int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int);
489 int del_mtd_partitions(struct mtd_info *); 491 int del_mtd_partitions(struct mtd_info *);
490 492
491 int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, 493 int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size,
492 loff_t *maxsize, int devtype, uint64_t chipsize); 494 loff_t *maxsize, int devtype, uint64_t chipsize);
493 int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, 495 int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off,
494 loff_t *size, loff_t *maxsize, int devtype, 496 loff_t *size, loff_t *maxsize, int devtype,
495 uint64_t chipsize); 497 uint64_t chipsize);
496 #endif 498 #endif
497 #endif /* __MTD_MTD_H__ */ 499 #endif /* __MTD_MTD_H__ */
498 500
File was created 1 /*
2 * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef _MTD_H_
8 #define _MTD_H_
9
10 #include <linux/mtd/mtd.h>
11
12 /*
13 * Get mtd_info structure of the dev, which is stored as uclass private.
14 *
15 * @dev: The MTD device
16 * @return: pointer to mtd_info, NULL on error
17 */
18 static inline struct mtd_info *mtd_get_info(struct udevice *dev)
19 {
20 return dev_get_uclass_priv(dev);
21 }
22
23 #endif /* _MTD_H_ */
24