Eric Lee / smarc-uboot

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/*

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/*

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*

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*

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* SPDX-License-Identifier: GPL-2.0+

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* SPDX-License-Identifier: GPL-2.0+

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*/

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*/

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#include <common.h>

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#include <common.h>

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#include <malloc.h>

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#include <malloc.h>

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#include <nand.h>

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#include <nand.h>

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#include <asm/errno.h>

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#include <asm/errno.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include "denali.h"

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#include "denali.h"

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#define NAND_DEFAULT_TIMINGS -1

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#define NAND_DEFAULT_TIMINGS -1

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static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;

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static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;

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/* We define a macro here that combines all interrupts this driver uses into

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/* We define a macro here that combines all interrupts this driver uses into

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* a single constant value, for convenience. */

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* a single constant value, for convenience. */

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#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \

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#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \

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INTR_STATUS__ECC_TRANSACTION_DONE | \

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INTR_STATUS__ECC_TRANSACTION_DONE | \

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INTR_STATUS__ECC_ERR | \

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INTR_STATUS__ECC_ERR | \

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INTR_STATUS__PROGRAM_FAIL | \

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INTR_STATUS__PROGRAM_FAIL | \

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INTR_STATUS__LOAD_COMP | \

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INTR_STATUS__LOAD_COMP | \

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INTR_STATUS__PROGRAM_COMP | \

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INTR_STATUS__PROGRAM_COMP | \

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INTR_STATUS__TIME_OUT | \

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INTR_STATUS__TIME_OUT | \

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INTR_STATUS__ERASE_FAIL | \

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INTR_STATUS__ERASE_FAIL | \

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INTR_STATUS__RST_COMP | \

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INTR_STATUS__RST_COMP | \

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INTR_STATUS__ERASE_COMP | \

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INTR_STATUS__ERASE_COMP | \

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INTR_STATUS__ECC_UNCOR_ERR | \

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INTR_STATUS__ECC_UNCOR_ERR | \

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INTR_STATUS__INT_ACT | \

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INTR_STATUS__INT_ACT | \

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INTR_STATUS__LOCKED_BLK)

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INTR_STATUS__LOCKED_BLK)

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/* indicates whether or not the internal value for the flash bank is

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/* indicates whether or not the internal value for the flash bank is

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* valid or not */

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* valid or not */

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#define CHIP_SELECT_INVALID -1

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#define CHIP_SELECT_INVALID -1

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#define SUPPORT_8BITECC 1

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#define SUPPORT_8BITECC 1

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/*

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/*

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* this macro allows us to convert from an MTD structure to our own

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* this macro allows us to convert from an MTD structure to our own

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* device context (denali) structure.

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* device context (denali) structure.

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*/

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*/

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#define mtd_to_denali(m) (((struct nand_chip *)mtd->priv)->priv)

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#define mtd_to_denali(m) (((struct nand_chip *)mtd->priv)->priv)

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/* These constants are defined by the driver to enable common driver

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/* These constants are defined by the driver to enable common driver

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* configuration options. */

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* configuration options. */

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#define SPARE_ACCESS 0x41

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#define SPARE_ACCESS 0x41

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#define MAIN_ACCESS 0x42

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#define MAIN_ACCESS 0x42

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#define MAIN_SPARE_ACCESS 0x43

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#define MAIN_SPARE_ACCESS 0x43

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#define DENALI_UNLOCK_START 0x10

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#define DENALI_UNLOCK_START 0x10

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#define DENALI_UNLOCK_END 0x11

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#define DENALI_UNLOCK_END 0x11

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#define DENALI_LOCK 0x21

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#define DENALI_LOCK 0x21

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#define DENALI_LOCK_TIGHT 0x31

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#define DENALI_LOCK_TIGHT 0x31

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#define DENALI_BUFFER_LOAD 0x60

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#define DENALI_BUFFER_LOAD 0x60

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#define DENALI_BUFFER_WRITE 0x62

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#define DENALI_BUFFER_WRITE 0x62

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#define DENALI_READ 0

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#define DENALI_READ 0

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#define DENALI_WRITE 0x100

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#define DENALI_WRITE 0x100

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/* types of device accesses. We can issue commands and get status */

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/* types of device accesses. We can issue commands and get status */

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#define COMMAND_CYCLE 0

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#define COMMAND_CYCLE 0

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#define ADDR_CYCLE 1

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#define ADDR_CYCLE 1

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#define STATUS_CYCLE 2

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#define STATUS_CYCLE 2

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/* this is a helper macro that allows us to

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/* this is a helper macro that allows us to

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* format the bank into the proper bits for the controller */

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* format the bank into the proper bits for the controller */

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#define BANK(x) ((x) << 24)

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#define BANK(x) ((x) << 24)

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/* Interrupts are cleared by writing a 1 to the appropriate status bit */

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/* Interrupts are cleared by writing a 1 to the appropriate status bit */

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static inline void clear_interrupt(struct denali_nand_info *denali,

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static inline void clear_interrupt(struct denali_nand_info *denali,

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uint32_t irq_mask)

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uint32_t irq_mask)

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{

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{

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uint32_t intr_status_reg;

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uint32_t intr_status_reg;

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intr_status_reg = INTR_STATUS(denali->flash_bank);

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intr_status_reg = INTR_STATUS(denali->flash_bank);

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writel(irq_mask, denali->flash_reg + intr_status_reg);

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writel(irq_mask, denali->flash_reg + intr_status_reg);

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}

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}

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static uint32_t read_interrupt_status(struct denali_nand_info *denali)

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static uint32_t read_interrupt_status(struct denali_nand_info *denali)

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{

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{

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uint32_t intr_status_reg;

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uint32_t intr_status_reg;

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intr_status_reg = INTR_STATUS(denali->flash_bank);

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intr_status_reg = INTR_STATUS(denali->flash_bank);

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return readl(denali->flash_reg + intr_status_reg);

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return readl(denali->flash_reg + intr_status_reg);

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}

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}

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static void clear_interrupts(struct denali_nand_info *denali)

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static void clear_interrupts(struct denali_nand_info *denali)

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{

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{

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uint32_t status;

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uint32_t status;

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status = read_interrupt_status(denali);

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status = read_interrupt_status(denali);

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clear_interrupt(denali, status);

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clear_interrupt(denali, status);

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denali->irq_status = 0;

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denali->irq_status = 0;

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}

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}

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static void denali_irq_enable(struct denali_nand_info *denali,

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static void denali_irq_enable(struct denali_nand_info *denali,

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uint32_t int_mask)

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uint32_t int_mask)

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{

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{

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int i;

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int i;

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for (i = 0; i < denali->max_banks; ++i)

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for (i = 0; i < denali->max_banks; ++i)

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writel(int_mask, denali->flash_reg + INTR_EN(i));

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writel(int_mask, denali->flash_reg + INTR_EN(i));

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}

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}

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static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)

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static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)

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{

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{

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unsigned long timeout = 1000000;

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unsigned long timeout = 1000000;

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uint32_t intr_status;

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uint32_t intr_status;

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do {

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do {

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intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;

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intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;

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if (intr_status & irq_mask) {

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if (intr_status & irq_mask) {

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denali->irq_status &= ~irq_mask;

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denali->irq_status &= ~irq_mask;

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/* our interrupt was detected */

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/* our interrupt was detected */

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break;

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break;

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}

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}

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udelay(1);

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udelay(1);

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timeout--;

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timeout--;

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} while (timeout != 0);

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} while (timeout != 0);

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if (timeout == 0) {

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if (timeout == 0) {

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/* timeout */

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/* timeout */

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printf("Denali timeout with interrupt status %08x\n",

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printf("Denali timeout with interrupt status %08x\n",

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read_interrupt_status(denali));

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read_interrupt_status(denali));

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intr_status = 0;

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intr_status = 0;

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}

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}

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return intr_status;

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return intr_status;

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}

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}

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/*

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/*

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* Certain operations for the denali NAND controller use an indexed mode to

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* Certain operations for the denali NAND controller use an indexed mode to

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* read/write data. The operation is performed by writing the address value

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* read/write data. The operation is performed by writing the address value

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* of the command to the device memory followed by the data. This function

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* of the command to the device memory followed by the data. This function

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* abstracts this common operation.

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* abstracts this common operation.

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*/

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*/

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static void index_addr(struct denali_nand_info *denali,

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static void index_addr(struct denali_nand_info *denali,

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uint32_t address, uint32_t data)

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uint32_t address, uint32_t data)

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{

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{

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writel(address, denali->flash_mem + INDEX_CTRL_REG);

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writel(address, denali->flash_mem + INDEX_CTRL_REG);

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writel(data, denali->flash_mem + INDEX_DATA_REG);

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writel(data, denali->flash_mem + INDEX_DATA_REG);

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}

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}

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/* Perform an indexed read of the device */

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/* Perform an indexed read of the device */

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static void index_addr_read_data(struct denali_nand_info *denali,

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static void index_addr_read_data(struct denali_nand_info *denali,

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uint32_t address, uint32_t *pdata)

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uint32_t address, uint32_t *pdata)

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{

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{

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writel(address, denali->flash_mem + INDEX_CTRL_REG);

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writel(address, denali->flash_mem + INDEX_CTRL_REG);

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*pdata = readl(denali->flash_mem + INDEX_DATA_REG);

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*pdata = readl(denali->flash_mem + INDEX_DATA_REG);

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}

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}

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/* We need to buffer some data for some of the NAND core routines.

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/* We need to buffer some data for some of the NAND core routines.

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* The operations manage buffering that data. */

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* The operations manage buffering that data. */

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static void reset_buf(struct denali_nand_info *denali)

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static void reset_buf(struct denali_nand_info *denali)

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{

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{

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denali->buf.head = 0;

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denali->buf.head = 0;

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denali->buf.tail = 0;

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denali->buf.tail = 0;

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}

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}

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static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)

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static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)

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{

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{

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denali->buf.buf[denali->buf.tail++] = byte;

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denali->buf.buf[denali->buf.tail++] = byte;

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}

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}

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/* resets a specific device connected to the core */

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/* resets a specific device connected to the core */

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static void reset_bank(struct denali_nand_info *denali)

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static void reset_bank(struct denali_nand_info *denali)

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{

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{

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uint32_t irq_status;

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uint32_t irq_status;

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uint32_t irq_mask = INTR_STATUS__RST_COMP |

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uint32_t irq_mask = INTR_STATUS__RST_COMP |

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INTR_STATUS__TIME_OUT;

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INTR_STATUS__TIME_OUT;

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clear_interrupts(denali);

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clear_interrupts(denali);

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writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);

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writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);

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irq_status = wait_for_irq(denali, irq_mask);

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irq_status = wait_for_irq(denali, irq_mask);

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if (irq_status & INTR_STATUS__TIME_OUT)

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if (irq_status & INTR_STATUS__TIME_OUT)

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debug("reset bank failed.\n");

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debug("reset bank failed.\n");

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}

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}

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/* Reset the flash controller */

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/* Reset the flash controller */

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static uint32_t denali_nand_reset(struct denali_nand_info *denali)

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static uint32_t denali_nand_reset(struct denali_nand_info *denali)

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{

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{

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uint32_t i;

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uint32_t i;

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for (i = 0; i < denali->max_banks; i++)

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for (i = 0; i < denali->max_banks; i++)

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writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,

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writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,

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denali->flash_reg + INTR_STATUS(i));

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denali->flash_reg + INTR_STATUS(i));

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for (i = 0; i < denali->max_banks; i++) {

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for (i = 0; i < denali->max_banks; i++) {

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writel(1 << i, denali->flash_reg + DEVICE_RESET);

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writel(1 << i, denali->flash_reg + DEVICE_RESET);

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while (!(readl(denali->flash_reg + INTR_STATUS(i)) &

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while (!(readl(denali->flash_reg + INTR_STATUS(i)) &

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(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))

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(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))

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if (readl(denali->flash_reg + INTR_STATUS(i)) &

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if (readl(denali->flash_reg + INTR_STATUS(i)) &

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INTR_STATUS__TIME_OUT)

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INTR_STATUS__TIME_OUT)

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debug("NAND Reset operation timed out on bank"

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debug("NAND Reset operation timed out on bank"

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" %d\n", i);

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" %d\n", i);

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}

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}

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for (i = 0; i < denali->max_banks; i++)

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for (i = 0; i < denali->max_banks; i++)

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writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,

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writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,

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denali->flash_reg + INTR_STATUS(i));

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denali->flash_reg + INTR_STATUS(i));

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return 0;

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return 0;

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}

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}

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/*

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/*

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* this routine calculates the ONFI timing values for a given mode and

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* this routine calculates the ONFI timing values for a given mode and

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* programs the clocking register accordingly. The mode is determined by

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* programs the clocking register accordingly. The mode is determined by

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* the get_onfi_nand_para routine.

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* the get_onfi_nand_para routine.

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*/

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*/

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static void nand_onfi_timing_set(struct denali_nand_info *denali,

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static void nand_onfi_timing_set(struct denali_nand_info *denali,

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uint16_t mode)

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uint16_t mode)

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{

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{

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uint32_t trea[6] = {40, 30, 25, 20, 20, 16};

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uint32_t trea[6] = {40, 30, 25, 20, 20, 16};

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uint32_t trp[6] = {50, 25, 17, 15, 12, 10};

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uint32_t trp[6] = {50, 25, 17, 15, 12, 10};

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uint32_t treh[6] = {30, 15, 15, 10, 10, 7};

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uint32_t treh[6] = {30, 15, 15, 10, 10, 7};

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uint32_t trc[6] = {100, 50, 35, 30, 25, 20};

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uint32_t trc[6] = {100, 50, 35, 30, 25, 20};

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uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};

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uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};

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uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};

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uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};

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uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};

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uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};

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uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};

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uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};

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uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};

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uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};

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uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};

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uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};

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uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};

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uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};

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uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};

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uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};

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uint32_t tclsrising = 1;

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uint32_t tclsrising = 1;

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uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;

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uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;

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uint32_t dv_window = 0;

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uint32_t dv_window = 0;

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uint32_t en_lo, en_hi;

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uint32_t en_lo, en_hi;

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uint32_t acc_clks;

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uint32_t acc_clks;

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uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;

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uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;

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en_lo = DIV_ROUND_UP(trp[mode], CLK_X);

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en_lo = DIV_ROUND_UP(trp[mode], CLK_X);

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en_hi = DIV_ROUND_UP(treh[mode], CLK_X);

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en_hi = DIV_ROUND_UP(treh[mode], CLK_X);

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if ((en_hi * CLK_X) < (treh[mode] + 2))

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if ((en_hi * CLK_X) < (treh[mode] + 2))

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en_hi++;

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en_hi++;

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if ((en_lo + en_hi) * CLK_X < trc[mode])

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if ((en_lo + en_hi) * CLK_X < trc[mode])

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en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),

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en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),

249

CLK_X);

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CLK_X);

250

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if ((en_lo + en_hi) < CLK_MULTI)

251

if ((en_lo + en_hi) < CLK_MULTI)

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en_lo += CLK_MULTI - en_lo - en_hi;

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en_lo += CLK_MULTI - en_lo - en_hi;

253

254

while (dv_window < 8) {

254

while (dv_window < 8) {

255

data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];

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data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];

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data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];

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data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];

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data_invalid =

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data_invalid =

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data_invalid_rhoh <

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data_invalid_rhoh <

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data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;

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data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;

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263

dv_window = data_invalid - trea[mode];

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dv_window = data_invalid - trea[mode];

264

265

if (dv_window < 8)

265

if (dv_window < 8)

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en_lo++;

266

en_lo++;

267

}

267

}

268

269

acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);

269

acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);

270

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while (((acc_clks * CLK_X) - trea[mode]) < 3)

271

while (((acc_clks * CLK_X) - trea[mode]) < 3)

272

acc_clks++;

272

acc_clks++;

273

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if ((data_invalid - acc_clks * CLK_X) < 2)

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if ((data_invalid - acc_clks * CLK_X) < 2)

275

debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);

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debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);

276

277

addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);

277

addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);

278

re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);

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re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);

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re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);

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re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);

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we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);

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we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);

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cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);

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cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);

282

if (!tclsrising)

282

if (!tclsrising)

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cs_cnt = DIV_ROUND_UP(tcs[mode], CLK_X);

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cs_cnt = DIV_ROUND_UP(tcs[mode], CLK_X);

284

if (cs_cnt == 0)

284

if (cs_cnt == 0)

285

cs_cnt = 1;

285

cs_cnt = 1;

286

287

if (tcea[mode]) {

287

if (tcea[mode]) {

288

while (((cs_cnt * CLK_X) + trea[mode]) < tcea[mode])

288

while (((cs_cnt * CLK_X) + trea[mode]) < tcea[mode])

289

cs_cnt++;

289

cs_cnt++;

290

}

290

}

291

292

/* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */

292

/* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */

293

if ((readl(denali->flash_reg + MANUFACTURER_ID) == 0) &&

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if ((readl(denali->flash_reg + MANUFACTURER_ID) == 0) &&

294

(readl(denali->flash_reg + DEVICE_ID) == 0x88))

294

(readl(denali->flash_reg + DEVICE_ID) == 0x88))

295

acc_clks = 6;

295

acc_clks = 6;

296

297

writel(acc_clks, denali->flash_reg + ACC_CLKS);

297

writel(acc_clks, denali->flash_reg + ACC_CLKS);

298

writel(re_2_we, denali->flash_reg + RE_2_WE);

298

writel(re_2_we, denali->flash_reg + RE_2_WE);

299

writel(re_2_re, denali->flash_reg + RE_2_RE);

299

writel(re_2_re, denali->flash_reg + RE_2_RE);

300

writel(we_2_re, denali->flash_reg + WE_2_RE);

300

writel(we_2_re, denali->flash_reg + WE_2_RE);

301

writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);

301

writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);

302

writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);

302

writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);

303

writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);

303

writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);

304

writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);

304

writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);

305

}

305

}

306

307

/* queries the NAND device to see what ONFI modes it supports. */

307

/* queries the NAND device to see what ONFI modes it supports. */

308

static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)

308

static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)

309

{

309

{

310

int i;

310

int i;

311

/*

311

/*

312

* we needn't to do a reset here because driver has already

312

* we needn't to do a reset here because driver has already

313

* reset all the banks before

313

* reset all the banks before

314

*/

314

*/

315

if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &

315

if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &

316

ONFI_TIMING_MODE__VALUE))

316

ONFI_TIMING_MODE__VALUE))

317

return -EIO;

317

return -EIO;

318

319

for (i = 5; i > 0; i--) {

319

for (i = 5; i > 0; i--) {

320

if (readl(denali->flash_reg + ONFI_TIMING_MODE) &

320

if (readl(denali->flash_reg + ONFI_TIMING_MODE) &

321

(0x01 << i))

321

(0x01 << i))

322

break;

322

break;

323

}

323

}

324

325

nand_onfi_timing_set(denali, i);

325

nand_onfi_timing_set(denali, i);

326

327

/* By now, all the ONFI devices we know support the page cache */

327

/* By now, all the ONFI devices we know support the page cache */

328

/* rw feature. So here we enable the pipeline_rw_ahead feature */

328

/* rw feature. So here we enable the pipeline_rw_ahead feature */

329

return 0;

329

return 0;

330

}

330

}

331

332

static void get_samsung_nand_para(struct denali_nand_info *denali,

332

static void get_samsung_nand_para(struct denali_nand_info *denali,

333

uint8_t device_id)

333

uint8_t device_id)

334

{

334

{

335

if (device_id == 0xd3) { /* Samsung K9WAG08U1A */

335

if (device_id == 0xd3) { /* Samsung K9WAG08U1A */

336

/* Set timing register values according to datasheet */

336

/* Set timing register values according to datasheet */

337

writel(5, denali->flash_reg + ACC_CLKS);

337

writel(5, denali->flash_reg + ACC_CLKS);

338

writel(20, denali->flash_reg + RE_2_WE);

338

writel(20, denali->flash_reg + RE_2_WE);

339

writel(12, denali->flash_reg + WE_2_RE);

339

writel(12, denali->flash_reg + WE_2_RE);

340

writel(14, denali->flash_reg + ADDR_2_DATA);

340

writel(14, denali->flash_reg + ADDR_2_DATA);

341

writel(3, denali->flash_reg + RDWR_EN_LO_CNT);

341

writel(3, denali->flash_reg + RDWR_EN_LO_CNT);

342

writel(2, denali->flash_reg + RDWR_EN_HI_CNT);

342

writel(2, denali->flash_reg + RDWR_EN_HI_CNT);

343

writel(2, denali->flash_reg + CS_SETUP_CNT);

343

writel(2, denali->flash_reg + CS_SETUP_CNT);

344

}

344

}

345

}

345

}

346

347

static void get_toshiba_nand_para(struct denali_nand_info *denali)

347

static void get_toshiba_nand_para(struct denali_nand_info *denali)

348

{

348

{

349

uint32_t tmp;

349

uint32_t tmp;

350

351

/* Workaround to fix a controller bug which reports a wrong */

351

/* Workaround to fix a controller bug which reports a wrong */

352

/* spare area size for some kind of Toshiba NAND device */

352

/* spare area size for some kind of Toshiba NAND device */

353

if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&

353

if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&

354

(readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {

354

(readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {

355

writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);

355

writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);

356

tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *

356

tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *

357

readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);

357

readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);

358

writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);

358

writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);

359

}

359

}

360

}

360

}

361

362

static void get_hynix_nand_para(struct denali_nand_info *denali,

362

static void get_hynix_nand_para(struct denali_nand_info *denali,

363

uint8_t device_id)

363

uint8_t device_id)

364

{

364

{

365

uint32_t main_size, spare_size;

365

uint32_t main_size, spare_size;

366

367

switch (device_id) {

367

switch (device_id) {

368

case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */

368

case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */

369

case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */

369

case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */

370

writel(128, denali->flash_reg + PAGES_PER_BLOCK);

370

writel(128, denali->flash_reg + PAGES_PER_BLOCK);

371

writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);

371

writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);

372

writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);

372

writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);

373

main_size = 4096 *

373

main_size = 4096 *

374

readl(denali->flash_reg + DEVICES_CONNECTED);

374

readl(denali->flash_reg + DEVICES_CONNECTED);

375

spare_size = 224 *

375

spare_size = 224 *

376

readl(denali->flash_reg + DEVICES_CONNECTED);

376

readl(denali->flash_reg + DEVICES_CONNECTED);

377

writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);

377

writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);

378

writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);

378

writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);

379

writel(0, denali->flash_reg + DEVICE_WIDTH);

379

writel(0, denali->flash_reg + DEVICE_WIDTH);

380

break;

380

break;

381

default:

381

default:

382

debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x)."

382

debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x)."

383

"Will use default parameter values instead.\n",

383

"Will use default parameter values instead.\n",

384

device_id);

384

device_id);

385

}

385

}

386

}

386

}

387

388

/*

388

/*

389

* determines how many NAND chips are connected to the controller. Note for

389

* determines how many NAND chips are connected to the controller. Note for

390

* Intel CE4100 devices we don't support more than one device.

390

* Intel CE4100 devices we don't support more than one device.

391

*/

391

*/

392

static void find_valid_banks(struct denali_nand_info *denali)

392

static void find_valid_banks(struct denali_nand_info *denali)

393

{

393

{

394

uint32_t id[denali->max_banks];

394

uint32_t id[denali->max_banks];

395

int i;

395

int i;

396

397

denali->total_used_banks = 1;

397

denali->total_used_banks = 1;

398

for (i = 0; i < denali->max_banks; i++) {

398

for (i = 0; i < denali->max_banks; i++) {

399

index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);

399

index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);

400

index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);

400

index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);

401

index_addr_read_data(denali,

401

index_addr_read_data(denali,

402

(uint32_t)(MODE_11 | (i << 24) | 2),

402

(uint32_t)(MODE_11 | (i << 24) | 2),

403

&id[i]);

403

&id[i]);

404

405

if (i == 0) {

405

if (i == 0) {

406

if (!(id[i] & 0x0ff))

406

if (!(id[i] & 0x0ff))

407

break;

407

break;

408

} else {

408

} else {

409

if ((id[i] & 0x0ff) == (id[0] & 0x0ff))

409

if ((id[i] & 0x0ff) == (id[0] & 0x0ff))

410

denali->total_used_banks++;

410

denali->total_used_banks++;

411

else

411

else

412

break;

412

break;

413

}

413

}

414

}

414

}

415

}

415

}

416

417

/*

417

/*

418

* Use the configuration feature register to determine the maximum number of

418

* Use the configuration feature register to determine the maximum number of

419

* banks that the hardware supports.

419

* banks that the hardware supports.

420

*/

420

*/

421

static void detect_max_banks(struct denali_nand_info *denali)

421

static void detect_max_banks(struct denali_nand_info *denali)

422

{

422

{

423

uint32_t features = readl(denali->flash_reg + FEATURES);

423

uint32_t features = readl(denali->flash_reg + FEATURES);

424

denali->max_banks = 2 << (features & FEATURES__N_BANKS);

424

denali->max_banks = 2 << (features & FEATURES__N_BANKS);

425

}

425

}

426

427

static void detect_partition_feature(struct denali_nand_info *denali)

427

static void detect_partition_feature(struct denali_nand_info *denali)

428

{

428

{

429

/*

429

/*

430

* For MRST platform, denali->fwblks represent the

430

* For MRST platform, denali->fwblks represent the

431

* number of blocks firmware is taken,

431

* number of blocks firmware is taken,

432

* FW is in protect partition and MTD driver has no

432

* FW is in protect partition and MTD driver has no

433

* permission to access it. So let driver know how many

433

* permission to access it. So let driver know how many

434

* blocks it can't touch.

434

* blocks it can't touch.

435

*/

435

*/

436

if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {

436

if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {

437

if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &

437

if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &

438

PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {

438

PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {

439

denali->fwblks =

439

denali->fwblks =

440

((readl(denali->flash_reg + MIN_MAX_BANK(1)) &

440

((readl(denali->flash_reg + MIN_MAX_BANK(1)) &

441

MIN_MAX_BANK__MIN_VALUE) *

441

MIN_MAX_BANK__MIN_VALUE) *

442

denali->blksperchip)

442

denali->blksperchip)

443

+

443

+

444

(readl(denali->flash_reg + MIN_BLK_ADDR(1)) &

444

(readl(denali->flash_reg + MIN_BLK_ADDR(1)) &

445

MIN_BLK_ADDR__VALUE);

445

MIN_BLK_ADDR__VALUE);

446

} else {

446

} else {

447

denali->fwblks = SPECTRA_START_BLOCK;

447

denali->fwblks = SPECTRA_START_BLOCK;

448

}

448

}

449

} else {

449

} else {

450

denali->fwblks = SPECTRA_START_BLOCK;

450

denali->fwblks = SPECTRA_START_BLOCK;

451

}

451

}

452

}

452

}

453

454

static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)

454

static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)

455

{

455

{

456

uint32_t id_bytes[5], addr;

456

uint32_t id_bytes[5], addr;

457

uint8_t i, maf_id, device_id;

457

uint8_t i, maf_id, device_id;

458

459

/* Use read id method to get device ID and other

459

/* Use read id method to get device ID and other

460

* params. For some NAND chips, controller can't

460

* params. For some NAND chips, controller can't

461

* report the correct device ID by reading from

461

* report the correct device ID by reading from

462

* DEVICE_ID register

462

* DEVICE_ID register

463

* */

463

* */

464

addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);

464

addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);

465

index_addr(denali, (uint32_t)addr | 0, 0x90);

465

index_addr(denali, (uint32_t)addr | 0, 0x90);

466

index_addr(denali, (uint32_t)addr | 1, 0);

466

index_addr(denali, (uint32_t)addr | 1, 0);

467

for (i = 0; i < 5; i++)

467

for (i = 0; i < 5; i++)

468

index_addr_read_data(denali, addr | 2, &id_bytes[i]);

468

index_addr_read_data(denali, addr | 2, &id_bytes[i]);

469

maf_id = id_bytes[0];

469

maf_id = id_bytes[0];

470

device_id = id_bytes[1];

470

device_id = id_bytes[1];

471

472

if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &

472

if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &

473

ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */

473

ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */

474

if (get_onfi_nand_para(denali))

474

if (get_onfi_nand_para(denali))

475

return -EIO;

475

return -EIO;

476

} else if (maf_id == 0xEC) { /* Samsung NAND */

476

} else if (maf_id == 0xEC) { /* Samsung NAND */

477

get_samsung_nand_para(denali, device_id);

477

get_samsung_nand_para(denali, device_id);

478

} else if (maf_id == 0x98) { /* Toshiba NAND */

478

} else if (maf_id == 0x98) { /* Toshiba NAND */

479

get_toshiba_nand_para(denali);

479

get_toshiba_nand_para(denali);

480

} else if (maf_id == 0xAD) { /* Hynix NAND */

480

} else if (maf_id == 0xAD) { /* Hynix NAND */

481

get_hynix_nand_para(denali, device_id);

481

get_hynix_nand_para(denali, device_id);

482

}

482

}

483

484

find_valid_banks(denali);

484

find_valid_banks(denali);

485

486

detect_partition_feature(denali);

486

detect_partition_feature(denali);

487

488

/* If the user specified to override the default timings

488

/* If the user specified to override the default timings

489

* with a specific ONFI mode, we apply those changes here.

489

* with a specific ONFI mode, we apply those changes here.

490

*/

490

*/

491

if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)

491

if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)

492

nand_onfi_timing_set(denali, onfi_timing_mode);

492

nand_onfi_timing_set(denali, onfi_timing_mode);

493

494

return 0;

494

return 0;

495

}

495

}

496

497

/* validation function to verify that the controlling software is making

497

/* validation function to verify that the controlling software is making

498

* a valid request

498

* a valid request

499

*/

499

*/

500

static inline bool is_flash_bank_valid(int flash_bank)

500

static inline bool is_flash_bank_valid(int flash_bank)

501

{

501

{

502

return flash_bank >= 0 && flash_bank < 4;

502

return flash_bank >= 0 && flash_bank < 4;

503

}

503

}

504

505

static void denali_irq_init(struct denali_nand_info *denali)

505

static void denali_irq_init(struct denali_nand_info *denali)

506

{

506

{

507

uint32_t int_mask = 0;

507

uint32_t int_mask = 0;

508

int i;

508

int i;

509

510

/* Disable global interrupts */

510

/* Disable global interrupts */

511

writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);

511

writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);

512

513

int_mask = DENALI_IRQ_ALL;

513

int_mask = DENALI_IRQ_ALL;

514

515

/* Clear all status bits */

515

/* Clear all status bits */

516

for (i = 0; i < denali->max_banks; ++i)

516

for (i = 0; i < denali->max_banks; ++i)

517

writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));

517

writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));

518

519

denali_irq_enable(denali, int_mask);

519

denali_irq_enable(denali, int_mask);

520

}

520

}

521

522

/* This helper function setups the registers for ECC and whether or not

522

/* This helper function setups the registers for ECC and whether or not

523

* the spare area will be transferred. */

523

* the spare area will be transferred. */

524

static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,

524

static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,

525

bool transfer_spare)

525

bool transfer_spare)

526

{

526

{

527

int ecc_en_flag = 0, transfer_spare_flag = 0;

527

int ecc_en_flag = 0, transfer_spare_flag = 0;

528

529

/* set ECC, transfer spare bits if needed */

529

/* set ECC, transfer spare bits if needed */

530

ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;

530

ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;

531

transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;

531

transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;

532

533

/* Enable spare area/ECC per user's request. */

533

/* Enable spare area/ECC per user's request. */

534

writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);

534

writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);

535

/* applicable for MAP01 only */

535

/* applicable for MAP01 only */

536

writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);

536

writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);

537

}

537

}

538

539

/* sends a pipeline command operation to the controller. See the Denali NAND

539

/* sends a pipeline command operation to the controller. See the Denali NAND

540

* controller's user guide for more information (section 4.2.3.6).

540

* controller's user guide for more information (section 4.2.3.6).

541

*/

541

*/

542

static int denali_send_pipeline_cmd(struct denali_nand_info *denali,

542

static int denali_send_pipeline_cmd(struct denali_nand_info *denali,

543

bool ecc_en, bool transfer_spare,

543

bool ecc_en, bool transfer_spare,

544

int access_type, int op)

544

int access_type, int op)

545

{

545

{

546

uint32_t addr, cmd, irq_status;

546

uint32_t addr, cmd, irq_status;

547

static uint32_t page_count = 1;

547

static uint32_t page_count = 1;

548

549

setup_ecc_for_xfer(denali, ecc_en, transfer_spare);

549

setup_ecc_for_xfer(denali, ecc_en, transfer_spare);

550

551

/* clear interrupts */

551

/* clear interrupts */

552

clear_interrupts(denali);

552

clear_interrupts(denali);

553

554

addr = BANK(denali->flash_bank) | denali->page;

554

addr = BANK(denali->flash_bank) | denali->page;

555

556

/* setup the acccess type */

556

/* setup the acccess type */

557

cmd = MODE_10 | addr;

557

cmd = MODE_10 | addr;

558

index_addr(denali, cmd, access_type);

558

index_addr(denali, cmd, access_type);

559

560

/* setup the pipeline command */

560

/* setup the pipeline command */

561

index_addr(denali, cmd, 0x2000 | op | page_count);

561

index_addr(denali, cmd, 0x2000 | op | page_count);

562

563

cmd = MODE_01 | addr;

563

cmd = MODE_01 | addr;

564

writel(cmd, denali->flash_mem + INDEX_CTRL_REG);

564

writel(cmd, denali->flash_mem + INDEX_CTRL_REG);

565

566

if (op == DENALI_READ) {

566

if (op == DENALI_READ) {

567

/* wait for command to be accepted */

567

/* wait for command to be accepted */

568

irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);

568

irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);

569

570

if (irq_status == 0)

570

if (irq_status == 0)

571

return -EIO;

571

return -EIO;

572

}

572

}

573

574

return 0;

574

return 0;

575

}

575

}

576

577

/* helper function that simply writes a buffer to the flash */

577

/* helper function that simply writes a buffer to the flash */

578

static int write_data_to_flash_mem(struct denali_nand_info *denali,

578

static int write_data_to_flash_mem(struct denali_nand_info *denali,

579

const uint8_t *buf, int len)

579

const uint8_t *buf, int len)

580

{

580

{

581

uint32_t i = 0, *buf32;

581

uint32_t i = 0, *buf32;

582

583

/* verify that the len is a multiple of 4. see comment in

583

/* verify that the len is a multiple of 4. see comment in

584

* read_data_from_flash_mem() */

584

* read_data_from_flash_mem() */

585

BUG_ON((len % 4) != 0);

585

BUG_ON((len % 4) != 0);

586

587

/* write the data to the flash memory */

587

/* write the data to the flash memory */

588

buf32 = (uint32_t *)buf;

588

buf32 = (uint32_t *)buf;

589

for (i = 0; i < len / 4; i++)

589

for (i = 0; i < len / 4; i++)

590

writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);

590

writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);

591

return i * 4; /* intent is to return the number of bytes read */

591

return i * 4; /* intent is to return the number of bytes read */

592

}

592

}

593

594

/* helper function that simply reads a buffer from the flash */

594

/* helper function that simply reads a buffer from the flash */

595

static int read_data_from_flash_mem(struct denali_nand_info *denali,

595

static int read_data_from_flash_mem(struct denali_nand_info *denali,

596

uint8_t *buf, int len)

596

uint8_t *buf, int len)

597

{

597

{

598

uint32_t i, *buf32;

598

uint32_t i, *buf32;

599

600

/*

600

/*

601

* we assume that len will be a multiple of 4, if not

601

* we assume that len will be a multiple of 4, if not

602

* it would be nice to know about it ASAP rather than

602

* it would be nice to know about it ASAP rather than

603

* have random failures...

603

* have random failures...

604

* This assumption is based on the fact that this

604

* This assumption is based on the fact that this

605

* function is designed to be used to read flash pages,

605

* function is designed to be used to read flash pages,

606

* which are typically multiples of 4...

606

* which are typically multiples of 4...

607

*/

607

*/

608

609

BUG_ON((len % 4) != 0);

609

BUG_ON((len % 4) != 0);

610

611

/* transfer the data from the flash */

611

/* transfer the data from the flash */

612

buf32 = (uint32_t *)buf;

612

buf32 = (uint32_t *)buf;

613

for (i = 0; i < len / 4; i++)

613

for (i = 0; i < len / 4; i++)

614

*buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);

614

*buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);

615

616

return i * 4; /* intent is to return the number of bytes read */

616

return i * 4; /* intent is to return the number of bytes read */

617

}

617

}

618

619

static void denali_mode_main_access(struct denali_nand_info *denali)

619

static void denali_mode_main_access(struct denali_nand_info *denali)

620

{

620

{

621

uint32_t addr, cmd;

621

uint32_t addr, cmd;

622

623

addr = BANK(denali->flash_bank) | denali->page;

623

addr = BANK(denali->flash_bank) | denali->page;

624

cmd = MODE_10 | addr;

624

cmd = MODE_10 | addr;

625

index_addr(denali, cmd, MAIN_ACCESS);

625

index_addr(denali, cmd, MAIN_ACCESS);

626

}

626

}

627

628

static void denali_mode_main_spare_access(struct denali_nand_info *denali)

628

static void denali_mode_main_spare_access(struct denali_nand_info *denali)

629

{

629

{

630

uint32_t addr, cmd;

630

uint32_t addr, cmd;

631

632

addr = BANK(denali->flash_bank) | denali->page;

632

addr = BANK(denali->flash_bank) | denali->page;

633

cmd = MODE_10 | addr;

633

cmd = MODE_10 | addr;

634

index_addr(denali, cmd, MAIN_SPARE_ACCESS);

634

index_addr(denali, cmd, MAIN_SPARE_ACCESS);

635

}

635

}

636

637

/* writes OOB data to the device */

637

/* writes OOB data to the device */

638

static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)

638

static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)

639

{

639

{

640

struct denali_nand_info *denali = mtd_to_denali(mtd);

640

struct denali_nand_info *denali = mtd_to_denali(mtd);

641

uint32_t irq_status;

641

uint32_t irq_status;

642

uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |

642

uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |

643

INTR_STATUS__PROGRAM_FAIL;

643

INTR_STATUS__PROGRAM_FAIL;

644

int status = 0;

644

int status = 0;

645

646

denali->page = page;

646

denali->page = page;

647

648

if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,

648

if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,

649

DENALI_WRITE) == 0) {

649

DENALI_WRITE) == 0) {

650

write_data_to_flash_mem(denali, buf, mtd->oobsize);

650

write_data_to_flash_mem(denali, buf, mtd->oobsize);

651

652

/* wait for operation to complete */

652

/* wait for operation to complete */

653

irq_status = wait_for_irq(denali, irq_mask);

653

irq_status = wait_for_irq(denali, irq_mask);

654

655

if (irq_status == 0) {

655

if (irq_status == 0) {

656

dev_err(denali->dev, "OOB write failed\n");

656

dev_err(denali->dev, "OOB write failed\n");

657

status = -EIO;

657

status = -EIO;

658

}

658

}

659

} else {

659

} else {

660

printf("unable to send pipeline command\n");

660

printf("unable to send pipeline command\n");

661

status = -EIO;

661

status = -EIO;

662

}

662

}

663

return status;

663

return status;

664

}

664

}

665

666

/* reads OOB data from the device */

666

/* reads OOB data from the device */

667

static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)

667

static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)

668

{

668

{

669

struct denali_nand_info *denali = mtd_to_denali(mtd);

669

struct denali_nand_info *denali = mtd_to_denali(mtd);

670

uint32_t irq_mask = INTR_STATUS__LOAD_COMP,

670

uint32_t irq_mask = INTR_STATUS__LOAD_COMP,

671

irq_status = 0, addr = 0x0, cmd = 0x0;

671

irq_status = 0, addr = 0x0, cmd = 0x0;

672

673

denali->page = page;

673

denali->page = page;

674

675

if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,

675

if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,

676

DENALI_READ) == 0) {

676

DENALI_READ) == 0) {

677

read_data_from_flash_mem(denali, buf, mtd->oobsize);

677

read_data_from_flash_mem(denali, buf, mtd->oobsize);

678

679

/* wait for command to be accepted

679

/* wait for command to be accepted

680

* can always use status0 bit as the mask is identical for each

680

* can always use status0 bit as the mask is identical for each

681

* bank. */

681

* bank. */

682

irq_status = wait_for_irq(denali, irq_mask);

682

irq_status = wait_for_irq(denali, irq_mask);

683

684

if (irq_status == 0)

684

if (irq_status == 0)

685

printf("page on OOB timeout %d\n", denali->page);

685

printf("page on OOB timeout %d\n", denali->page);

686

687

/* We set the device back to MAIN_ACCESS here as I observed

687

/* We set the device back to MAIN_ACCESS here as I observed

688

* instability with the controller if you do a block erase

688

* instability with the controller if you do a block erase

689

* and the last transaction was a SPARE_ACCESS. Block erase

689

* and the last transaction was a SPARE_ACCESS. Block erase

690

* is reliable (according to the MTD test infrastructure)

690

* is reliable (according to the MTD test infrastructure)

691

* if you are in MAIN_ACCESS.

691

* if you are in MAIN_ACCESS.

692

*/

692

*/

693

addr = BANK(denali->flash_bank) | denali->page;

693

addr = BANK(denali->flash_bank) | denali->page;

694

cmd = MODE_10 | addr;

694

cmd = MODE_10 | addr;

695

index_addr(denali, cmd, MAIN_ACCESS);

695

index_addr(denali, cmd, MAIN_ACCESS);

696

}

696

}

697

}

697

}

698

699

/* this function examines buffers to see if they contain data that

699

/* this function examines buffers to see if they contain data that

700

* indicate that the buffer is part of an erased region of flash.

700

* indicate that the buffer is part of an erased region of flash.

701

*/

701

*/

702

static bool is_erased(uint8_t *buf, int len)

702

static bool is_erased(uint8_t *buf, int len)

703

{

703

{

704

int i = 0;

704

int i = 0;

705

for (i = 0; i < len; i++)

705

for (i = 0; i < len; i++)

706

if (buf[i] != 0xFF)

706

if (buf[i] != 0xFF)

707

return false;

707

return false;

708

return true;

708

return true;

709

}

709

}

710

711

/* programs the controller to either enable/disable DMA transfers */

711

/* programs the controller to either enable/disable DMA transfers */

712

static void denali_enable_dma(struct denali_nand_info *denali, bool en)

712

static void denali_enable_dma(struct denali_nand_info *denali, bool en)

713

{

713

{

714

uint32_t reg_val = 0x0;

714

uint32_t reg_val = 0x0;

715

716

if (en)

716

if (en)

717

reg_val = DMA_ENABLE__FLAG;

717

reg_val = DMA_ENABLE__FLAG;

718

719

writel(reg_val, denali->flash_reg + DMA_ENABLE);

719

writel(reg_val, denali->flash_reg + DMA_ENABLE);

720

readl(denali->flash_reg + DMA_ENABLE);

720

readl(denali->flash_reg + DMA_ENABLE);

721

}

721

}

722

723

/* setups the HW to perform the data DMA */

723

/* setups the HW to perform the data DMA */

724

static void denali_setup_dma(struct denali_nand_info *denali, int op)

724

static void denali_setup_dma(struct denali_nand_info *denali, int op)

725

{

725

{

726

uint32_t mode;

726

uint32_t mode;

727

const int page_count = 1;

727

const int page_count = 1;

728

uint32_t addr = (uint32_t)denali->buf.dma_buf;

728

uint32_t addr = (uint32_t)denali->buf.dma_buf;

729

730

flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));

730

flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));

731

732

/* For Denali controller that is 64 bit bus IP core */

732

/* For Denali controller that is 64 bit bus IP core */

733

#ifdef CONFIG_SYS_NAND_DENALI_64BIT

733

#ifdef CONFIG_SYS_NAND_DENALI_64BIT

734

mode = MODE_10 | BANK(denali->flash_bank) | denali->page;

734

mode = MODE_10 | BANK(denali->flash_bank) | denali->page;

735

736

/* DMA is a three step process */

736

/* DMA is a three step process */

737

738

/* 1. setup transfer type, interrupt when complete,

738

/* 1. setup transfer type, interrupt when complete,

739

burst len = 64 bytes, the number of pages */

739

burst len = 64 bytes, the number of pages */

740

index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);

740

index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);

741

742

/* 2. set memory low address bits 31:0 */

742

/* 2. set memory low address bits 31:0 */

743

index_addr(denali, mode, addr);

743

index_addr(denali, mode, addr);

744

745

/* 3. set memory high address bits 64:32 */

745

/* 3. set memory high address bits 64:32 */

746

index_addr(denali, mode, 0);

746

index_addr(denali, mode, 0);

747

#else

747

#else

748

mode = MODE_10 | BANK(denali->flash_bank);

748

mode = MODE_10 | BANK(denali->flash_bank);

749

750

/* DMA is a four step process */

750

/* DMA is a four step process */

751

752

/* 1. setup transfer type and # of pages */

752

/* 1. setup transfer type and # of pages */

753

index_addr(denali, mode | denali->page, 0x2000 | op | page_count);

753

index_addr(denali, mode | denali->page, 0x2000 | op | page_count);

754

755

/* 2. set memory high address bits 23:8 */

755

/* 2. set memory high address bits 23:8 */

756

index_addr(denali, mode | ((uint32_t)(addr >> 16) << 8), 0x2200);

756

index_addr(denali, mode | ((uint32_t)(addr >> 16) << 8), 0x2200);

757

758

/* 3. set memory low address bits 23:8 */

758

/* 3. set memory low address bits 23:8 */

759

index_addr(denali, mode | ((uint32_t)addr << 8), 0x2300);

759

index_addr(denali, mode | ((uint32_t)addr << 8), 0x2300);

760

761

/* 4. interrupt when complete, burst len = 64 bytes*/

761

/* 4. interrupt when complete, burst len = 64 bytes*/

762

index_addr(denali, mode | 0x14000, 0x2400);

762

index_addr(denali, mode | 0x14000, 0x2400);

763

#endif

763

#endif

764

}

764

}

765

766

/* Common DMA function */

766

/* Common DMA function */

767

static uint32_t denali_dma_configuration(struct denali_nand_info *denali,

767

static uint32_t denali_dma_configuration(struct denali_nand_info *denali,

768

uint32_t ops, bool raw_xfer,

768

uint32_t ops, bool raw_xfer,

769

uint32_t irq_mask, int oob_required)

769

uint32_t irq_mask, int oob_required)

770

{

770

{

771

uint32_t irq_status = 0;

771

uint32_t irq_status = 0;

772

/* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */

772

/* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */

773

setup_ecc_for_xfer(denali, !raw_xfer, oob_required);

773

setup_ecc_for_xfer(denali, !raw_xfer, oob_required);

774

775

/* clear any previous interrupt flags */

775

/* clear any previous interrupt flags */

776

clear_interrupts(denali);

776

clear_interrupts(denali);

777

778

/* enable the DMA */

778

/* enable the DMA */

779

denali_enable_dma(denali, true);

779

denali_enable_dma(denali, true);

780

781

/* setup the DMA */

781

/* setup the DMA */

782

denali_setup_dma(denali, ops);

782

denali_setup_dma(denali, ops);

783

784

/* wait for operation to complete */

784

/* wait for operation to complete */

785

irq_status = wait_for_irq(denali, irq_mask);

785

irq_status = wait_for_irq(denali, irq_mask);

786

787

/* if ECC fault happen, seems we need delay before turning off DMA.

787

/* if ECC fault happen, seems we need delay before turning off DMA.

788

* If not, the controller will go into non responsive condition */

788

* If not, the controller will go into non responsive condition */

789

if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)

789

if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)

790

udelay(100);

790

udelay(100);

791

792

/* disable the DMA */

792

/* disable the DMA */

793

denali_enable_dma(denali, false);

793

denali_enable_dma(denali, false);

794

795

return irq_status;

795

return irq_status;

796

}

796

}

797

798

static int write_page(struct mtd_info *mtd, struct nand_chip *chip,

798

static int write_page(struct mtd_info *mtd, struct nand_chip *chip,

799

const uint8_t *buf, bool raw_xfer, int oob_required)

799

const uint8_t *buf, bool raw_xfer, int oob_required)

800

{

800

{

801

struct denali_nand_info *denali = mtd_to_denali(mtd);

801

struct denali_nand_info *denali = mtd_to_denali(mtd);

802

803

uint32_t irq_status = 0;

803

uint32_t irq_status = 0;

804

uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;

804

uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;

805

806

denali->status = 0;

806

denali->status = 0;

807

808

/* copy buffer into DMA buffer */

808

/* copy buffer into DMA buffer */

809

memcpy(denali->buf.dma_buf, buf, mtd->writesize);

809

memcpy(denali->buf.dma_buf, buf, mtd->writesize);

810

811

/* need extra memcpy for raw transfer */

811

/* need extra memcpy for raw transfer */

812

if (raw_xfer)

812

if (raw_xfer)

813

memcpy(denali->buf.dma_buf + mtd->writesize,

813

memcpy(denali->buf.dma_buf + mtd->writesize,

814

chip->oob_poi, mtd->oobsize);

814

chip->oob_poi, mtd->oobsize);

815

816

/* setting up DMA */

816

/* setting up DMA */

817

irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,

817

irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,

818

irq_mask, oob_required);

818

irq_mask, oob_required);

819

820

/* if timeout happen, error out */

820

/* if timeout happen, error out */

821

if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {

821

if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {

822

debug("DMA timeout for denali write_page\n");

822

debug("DMA timeout for denali write_page\n");

823

denali->status = NAND_STATUS_FAIL;

823

denali->status = NAND_STATUS_FAIL;

824

return -EIO;

824

return -EIO;

825

}

825

}

826

827

if (irq_status & INTR_STATUS__LOCKED_BLK) {

827

if (irq_status & INTR_STATUS__LOCKED_BLK) {

828

debug("Failed as write to locked block\n");

828

debug("Failed as write to locked block\n");

829

denali->status = NAND_STATUS_FAIL;

829

denali->status = NAND_STATUS_FAIL;

830

return -EIO;

830

return -EIO;

831

}

831

}

832

return 0;

832

return 0;

833

}

833

}

834

835

/* NAND core entry points */

835

/* NAND core entry points */

836

837

/*

837

/*

838

* this is the callback that the NAND core calls to write a page. Since

838

* this is the callback that the NAND core calls to write a page. Since

839

* writing a page with ECC or without is similar, all the work is done

839

* writing a page with ECC or without is similar, all the work is done

840

* by write_page above.

840

* by write_page above.

841

*/

841

*/

842

static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,

842

static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,

843

const uint8_t *buf, int oob_required)

843

const uint8_t *buf, int oob_required)

844

{

844

{

845

struct denali_nand_info *denali = mtd_to_denali(mtd);

845

struct denali_nand_info *denali = mtd_to_denali(mtd);

846

847

/*

847

/*

848

* for regular page writes, we let HW handle all the ECC

848

* for regular page writes, we let HW handle all the ECC

849

* data written to the device.

849

* data written to the device.

850

*/

850

*/

851

if (oob_required)

851

if (oob_required)

852

/* switch to main + spare access */

852

/* switch to main + spare access */

853

denali_mode_main_spare_access(denali);

853

denali_mode_main_spare_access(denali);

854

else

854

else

855

/* switch to main access only */

855

/* switch to main access only */

856

denali_mode_main_access(denali);

856

denali_mode_main_access(denali);

857

858

return write_page(mtd, chip, buf, false, oob_required);

858

return write_page(mtd, chip, buf, false, oob_required);

859

}

859

}

860

861

/*

861

/*

862

* This is the callback that the NAND core calls to write a page without ECC.

862

* This is the callback that the NAND core calls to write a page without ECC.

863

* raw access is similar to ECC page writes, so all the work is done in the

863

* raw access is similar to ECC page writes, so all the work is done in the

864

* write_page() function above.

864

* write_page() function above.

865

*/

865

*/

866

static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

866

static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

867

const uint8_t *buf, int oob_required)

867

const uint8_t *buf, int oob_required)

868

{

868

{

869

struct denali_nand_info *denali = mtd_to_denali(mtd);

869

struct denali_nand_info *denali = mtd_to_denali(mtd);

870

871

/*

871

/*

872

* for raw page writes, we want to disable ECC and simply write

872

* for raw page writes, we want to disable ECC and simply write

873

* whatever data is in the buffer.

873

* whatever data is in the buffer.

874

*/

874

*/

875

876

if (oob_required)

876

if (oob_required)

877

/* switch to main + spare access */

877

/* switch to main + spare access */

878

denali_mode_main_spare_access(denali);

878

denali_mode_main_spare_access(denali);

879

else

879

else

880

/* switch to main access only */

880

/* switch to main access only */

881

denali_mode_main_access(denali);

881

denali_mode_main_access(denali);

882

883

return write_page(mtd, chip, buf, true, oob_required);

883

return write_page(mtd, chip, buf, true, oob_required);

884

}

884

}

885

886

static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,

886

static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,

887

int page)

887

int page)

888

{

888

{

889

return write_oob_data(mtd, chip->oob_poi, page);

889

return write_oob_data(mtd, chip->oob_poi, page);

890

}

890

}

891

892

/* raw include ECC value and all the spare area */

892

/* raw include ECC value and all the spare area */

893

static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

893

static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

894

uint8_t *buf, int oob_required, int page)

894

uint8_t *buf, int oob_required, int page)

895

{

895

{

896

struct denali_nand_info *denali = mtd_to_denali(mtd);

896

struct denali_nand_info *denali = mtd_to_denali(mtd);

897

898

uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;

898

uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;

899

900

if (denali->page != page) {

900

if (denali->page != page) {

901

debug("Missing NAND_CMD_READ0 command\n");

901

debug("Missing NAND_CMD_READ0 command\n");

902

return -EIO;

902

return -EIO;

903

}

903

}

904

905

if (oob_required)

905

if (oob_required)

906

/* switch to main + spare access */

906

/* switch to main + spare access */

907

denali_mode_main_spare_access(denali);

907

denali_mode_main_spare_access(denali);

908

else

908

else

909

/* switch to main access only */

909

/* switch to main access only */

910

denali_mode_main_access(denali);

910

denali_mode_main_access(denali);

911

912

/* setting up the DMA where ecc_enable is false */

912

/* setting up the DMA where ecc_enable is false */

913

irq_status = denali_dma_configuration(denali, DENALI_READ, true,

913

irq_status = denali_dma_configuration(denali, DENALI_READ, true,

914

irq_mask, oob_required);

914

irq_mask, oob_required);

915

916

/* if timeout happen, error out */

916

/* if timeout happen, error out */

917

if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {

917

if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {

918

debug("DMA timeout for denali_read_page_raw\n");

918

debug("DMA timeout for denali_read_page_raw\n");

919

return -EIO;

919

return -EIO;

920

}

920

}

921

922

/* splitting the content to destination buffer holder */

922

/* splitting the content to destination buffer holder */

923

memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),

923

memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),

924

mtd->oobsize);

924

mtd->oobsize);

925

memcpy(buf, denali->buf.dma_buf, mtd->writesize);

925

memcpy(buf, denali->buf.dma_buf, mtd->writesize);

926

927

return 0;

927

return 0;

928

}

928

}

929

930

static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,

930

static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,

931

uint8_t *buf, int oob_required, int page)

931

uint8_t *buf, int oob_required, int page)

932

{

932

{

933

struct denali_nand_info *denali = mtd_to_denali(mtd);

933

struct denali_nand_info *denali = mtd_to_denali(mtd);

934

uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;

934

uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;

935

936

if (denali->page != page) {

936

if (denali->page != page) {

937

debug("Missing NAND_CMD_READ0 command\n");

937

debug("Missing NAND_CMD_READ0 command\n");

938

return -EIO;

938

return -EIO;

939

}

939

}

940

941

if (oob_required)

941

if (oob_required)

942

/* switch to main + spare access */

942

/* switch to main + spare access */

943

denali_mode_main_spare_access(denali);

943

denali_mode_main_spare_access(denali);

944

else

944

else

945

/* switch to main access only */

945

/* switch to main access only */

946

denali_mode_main_access(denali);

946

denali_mode_main_access(denali);

947

948

/* setting up the DMA where ecc_enable is true */

948

/* setting up the DMA where ecc_enable is true */

949

irq_status = denali_dma_configuration(denali, DENALI_READ, false,

949

irq_status = denali_dma_configuration(denali, DENALI_READ, false,

950

irq_mask, oob_required);

950

irq_mask, oob_required);

951

952

memcpy(buf, denali->buf.dma_buf, mtd->writesize);

952

memcpy(buf, denali->buf.dma_buf, mtd->writesize);

953

954

/* check whether any ECC error */

954

/* check whether any ECC error */

955

if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {

955

if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {

956

/* is the ECC cause by erase page, check using read_page_raw */

956

/* is the ECC cause by erase page, check using read_page_raw */

957

debug(" Uncorrected ECC detected\n");

957

debug(" Uncorrected ECC detected\n");

958

denali_read_page_raw(mtd, chip, buf, oob_required,

958

denali_read_page_raw(mtd, chip, buf, oob_required,

959

denali->page);

959

denali->page);

960

961

if (is_erased(buf, mtd->writesize) == true &&

961

if (is_erased(buf, mtd->writesize) == true &&

962

is_erased(chip->oob_poi, mtd->oobsize) == true) {

962

is_erased(chip->oob_poi, mtd->oobsize) == true) {

963

debug(" ECC error cause by erased block\n");

963

debug(" ECC error cause by erased block\n");

964

/* false alarm, return the 0xFF */

964

/* false alarm, return the 0xFF */

965

} else {

965

} else {

966

return -EIO;

966

return -EIO;

967

}

967

}

968

}

968

}

969

memcpy(buf, denali->buf.dma_buf, mtd->writesize);

969

memcpy(buf, denali->buf.dma_buf, mtd->writesize);

970

return 0;

970

return 0;

971

}

971

}

972

973

static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,

973

static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,

974

int page)

974

int page)

975

{

975

{

976

read_oob_data(mtd, chip->oob_poi, page);

976

read_oob_data(mtd, chip->oob_poi, page);

977

978

return 0;

978

return 0;

979

}

979

}

980

981

static uint8_t denali_read_byte(struct mtd_info *mtd)

981

static uint8_t denali_read_byte(struct mtd_info *mtd)

982

{

982

{

983

struct denali_nand_info *denali = mtd_to_denali(mtd);

983

struct denali_nand_info *denali = mtd_to_denali(mtd);

984

uint32_t addr, result;

984

uint32_t addr, result;

985

986

addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);

986

addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);

987

index_addr_read_data(denali, addr | 2, &result);

987

index_addr_read_data(denali, addr | 2, &result);

988

return (uint8_t)result & 0xFF;

988

return (uint8_t)result & 0xFF;

989

}

989

}

990

991

static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)

991

static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)

992

{

992

{

993

struct denali_nand_info *denali = mtd_to_denali(mtd);

993

struct denali_nand_info *denali = mtd_to_denali(mtd);

994

uint32_t i, addr, result;

994

uint32_t i, addr, result;

995

996

/* delay for tR (data transfer from Flash array to data register) */

996

/* delay for tR (data transfer from Flash array to data register) */

997

udelay(25);

997

udelay(25);

998

999

/* ensure device completed else additional delay and polling */

999

/* ensure device completed else additional delay and polling */

1000

wait_for_irq(denali, INTR_STATUS__INT_ACT);

1000

wait_for_irq(denali, INTR_STATUS__INT_ACT);

1001

1002

addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);

1002

addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);

1003

for (i = 0; i < len; i++) {

1003

for (i = 0; i < len; i++) {

1004

index_addr_read_data(denali, (uint32_t)addr | 2, &result);

1004

index_addr_read_data(denali, (uint32_t)addr | 2, &result);

1005

write_byte_to_buf(denali, result);

1005

write_byte_to_buf(denali, result);

1006

}

1006

}

1007

memcpy(buf, denali->buf.buf, len);

1007

memcpy(buf, denali->buf.buf, len);

1008

}

1008

}

1009

1010

static void denali_select_chip(struct mtd_info *mtd, int chip)

1010

static void denali_select_chip(struct mtd_info *mtd, int chip)

1011

{

1011

{

1012

struct denali_nand_info *denali = mtd_to_denali(mtd);

1012

struct denali_nand_info *denali = mtd_to_denali(mtd);

1013

1014

denali->flash_bank = chip;

1014

denali->flash_bank = chip;

1015

}

1015

}

1016

1017

static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)

1017

static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)

1018

{

1018

{

1019

struct denali_nand_info *denali = mtd_to_denali(mtd);

1019

struct denali_nand_info *denali = mtd_to_denali(mtd);

1020

int status = denali->status;

1020

int status = denali->status;

1021

denali->status = 0;

1021

denali->status = 0;

1022

1023

return status;

1023

return status;

1024

}

1024

}

1025

1026

static void denali_erase(struct mtd_info *mtd, int page)

1026

static void denali_erase(struct mtd_info *mtd, int page)

1027

{

1027

{

1028

struct denali_nand_info *denali = mtd_to_denali(mtd);

1028

struct denali_nand_info *denali = mtd_to_denali(mtd);

1029

uint32_t cmd, irq_status;

1029

uint32_t cmd, irq_status;

1030

1031

/* clear interrupts */

1031

/* clear interrupts */

1032

clear_interrupts(denali);

1032

clear_interrupts(denali);

1033

1034

/* setup page read request for access type */

1034

/* setup page read request for access type */

1035

cmd = MODE_10 | BANK(denali->flash_bank) | page;

1035

cmd = MODE_10 | BANK(denali->flash_bank) | page;

1036

index_addr(denali, cmd, 0x1);

1036

index_addr(denali, cmd, 0x1);

1037

1038

/* wait for erase to complete or failure to occur */

1038

/* wait for erase to complete or failure to occur */

1039

irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |

1039

irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |

1040

INTR_STATUS__ERASE_FAIL);

1040

INTR_STATUS__ERASE_FAIL);

1041

1042

if (irq_status & INTR_STATUS__ERASE_FAIL ||

1042

if (irq_status & INTR_STATUS__ERASE_FAIL ||

1043

irq_status & INTR_STATUS__LOCKED_BLK)

1043

irq_status & INTR_STATUS__LOCKED_BLK)

1044

denali->status = NAND_STATUS_FAIL;

1044

denali->status = NAND_STATUS_FAIL;

1045

else

1045

else

1046

denali->status = 0;

1046

denali->status = 0;

1047

}

1047

}

1048

1049

static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,

1049

static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,

1050

int page)

1050

int page)

1051

{

1051

{

1052

struct denali_nand_info *denali = mtd_to_denali(mtd);

1052

struct denali_nand_info *denali = mtd_to_denali(mtd);

1053

uint32_t addr;

1053

uint32_t addr;

1054

1055

switch (cmd) {

1055

switch (cmd) {

1056

case NAND_CMD_PAGEPROG:

1056

case NAND_CMD_PAGEPROG:

1057

break;

1057

break;

1058

case NAND_CMD_STATUS:

1058

case NAND_CMD_STATUS:

1059

addr = MODE_11 | BANK(denali->flash_bank);

1059

addr = MODE_11 | BANK(denali->flash_bank);

1060

index_addr(denali, addr | 0, cmd);

1060

index_addr(denali, addr | 0, cmd);

1061

break;

1061

break;

1062

case NAND_CMD_PARAM:

1063

clear_interrupts(denali);

1064

case NAND_CMD_READID:

1062

case NAND_CMD_READID:

1063

case NAND_CMD_PARAM:

1065

reset_buf(denali);

1064

reset_buf(denali);

1066

/* sometimes ManufactureId read from register is not right

1065

/* sometimes ManufactureId read from register is not right

1067

* e.g. some of Micron MT29F32G08QAA MLC NAND chips

1066

* e.g. some of Micron MT29F32G08QAA MLC NAND chips

1068

* So here we send READID cmd to NAND insteand

1067

* So here we send READID cmd to NAND insteand

1069

* */

1068

* */

1070

addr = MODE_11 | BANK(denali->flash_bank);

1069

addr = MODE_11 | BANK(denali->flash_bank);

1071

index_addr(denali, addr | 0, cmd);

1070

index_addr(denali, addr | 0, cmd);

1072

index_addr(denali, addr | 1, col & 0xFF);

1071

index_addr(denali, addr | 1, col & 0xFF);

1072

if (cmd == NAND_CMD_PARAM)

1073

udelay(50);

1074

break;

1075

case NAND_CMD_RNDOUT:

1076

addr = MODE_11 | BANK(denali->flash_bank);

1077

index_addr(denali, addr | 0, cmd);

1078

index_addr(denali, addr | 1, col & 0xFF);

1079

index_addr(denali, addr | 1, col >> 8);

1080

index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART);

1073

break;

1081

break;

1074

case NAND_CMD_READ0:

1082

case NAND_CMD_READ0:

1075

case NAND_CMD_SEQIN:

1083

case NAND_CMD_SEQIN:

1076

denali->page = page;

1084

denali->page = page;

1077

break;

1085

break;

1078

case NAND_CMD_RESET:

1086

case NAND_CMD_RESET:

1079

reset_bank(denali);

1087

reset_bank(denali);

1080

break;

1088

break;

1081

case NAND_CMD_READOOB:

1089

case NAND_CMD_READOOB:

1082

/* TODO: Read OOB data */

1090

/* TODO: Read OOB data */

1083

break;

1091

break;

1084

case NAND_CMD_ERASE1:

1092

case NAND_CMD_ERASE1:

1085

/*

1093

/*

1086

* supporting block erase only, not multiblock erase as

1094

* supporting block erase only, not multiblock erase as

1087

* it will cross plane and software need complex calculation

1095

* it will cross plane and software need complex calculation

1088

* to identify the block count for the cross plane

1096

* to identify the block count for the cross plane

1089

*/

1097

*/

1090

denali_erase(mtd, page);

1098

denali_erase(mtd, page);

1091

break;

1099

break;

1092

case NAND_CMD_ERASE2:

1100

case NAND_CMD_ERASE2:

1093

/* nothing to do here as it was done during NAND_CMD_ERASE1 */

1101

/* nothing to do here as it was done during NAND_CMD_ERASE1 */

1094

break;

1102

break;

1095

case NAND_CMD_UNLOCK1:

1103

case NAND_CMD_UNLOCK1:

1096

addr = MODE_10 | BANK(denali->flash_bank) | page;

1104

addr = MODE_10 | BANK(denali->flash_bank) | page;

1097

index_addr(denali, addr | 0, DENALI_UNLOCK_START);

1105

index_addr(denali, addr | 0, DENALI_UNLOCK_START);

1098

break;

1106

break;

1099

case NAND_CMD_UNLOCK2:

1107

case NAND_CMD_UNLOCK2:

1100

addr = MODE_10 | BANK(denali->flash_bank) | page;

1108

addr = MODE_10 | BANK(denali->flash_bank) | page;

1101

index_addr(denali, addr | 0, DENALI_UNLOCK_END);

1109

index_addr(denali, addr | 0, DENALI_UNLOCK_END);

1102

break;

1110

break;

1103

case NAND_CMD_LOCK:

1111

case NAND_CMD_LOCK:

1104

addr = MODE_10 | BANK(denali->flash_bank);

1112

addr = MODE_10 | BANK(denali->flash_bank);

1105

index_addr(denali, addr | 0, DENALI_LOCK);

1113

index_addr(denali, addr | 0, DENALI_LOCK);

1106

break;

1114

break;

1107

default:

1115

default:

1108

printf(": unsupported command received 0x%x\n", cmd);

1116

printf(": unsupported command received 0x%x\n", cmd);

1109

break;

1117

break;

1110

}

1118

}

1111

}

1119

}

1112

/* end NAND core entry points */

1120

/* end NAND core entry points */

1113

1121

1114

/* Initialization code to bring the device up to a known good state */

1122

/* Initialization code to bring the device up to a known good state */

1115

static void denali_hw_init(struct denali_nand_info *denali)

1123

static void denali_hw_init(struct denali_nand_info *denali)

1116

{

1124

{

1117

/*

1125

/*

1118

* tell driver how many bit controller will skip before writing

1126

* tell driver how many bit controller will skip before writing

1119

* ECC code in OOB. This is normally used for bad block marker

1127

* ECC code in OOB. This is normally used for bad block marker

1120

*/

1128

*/

1121

writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,

1129

writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,

1122

denali->flash_reg + SPARE_AREA_SKIP_BYTES);

1130

denali->flash_reg + SPARE_AREA_SKIP_BYTES);

1123

detect_max_banks(denali);

1131

detect_max_banks(denali);

1124

denali_nand_reset(denali);

1132

denali_nand_reset(denali);

1125

writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);

1133

writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);

1126

writel(CHIP_EN_DONT_CARE__FLAG,

1134

writel(CHIP_EN_DONT_CARE__FLAG,

1127

denali->flash_reg + CHIP_ENABLE_DONT_CARE);

1135

denali->flash_reg + CHIP_ENABLE_DONT_CARE);

1128

writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);

1136

writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);

1129

1137

1130

/* Should set value for these registers when init */

1138

/* Should set value for these registers when init */

1131

writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);

1139

writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);

1132

writel(1, denali->flash_reg + ECC_ENABLE);

1140

writel(1, denali->flash_reg + ECC_ENABLE);

1133

denali_nand_timing_set(denali);

1141

denali_nand_timing_set(denali);

1134

denali_irq_init(denali);

1142

denali_irq_init(denali);

1135

}

1143

}

1136

1144

1137

static struct nand_ecclayout nand_oob;

1145

static struct nand_ecclayout nand_oob;

1138

1146

1139

static int denali_nand_init(struct nand_chip *nand)

1147

static int denali_nand_init(struct nand_chip *nand)

1140

{

1148

{

1141

struct denali_nand_info *denali;

1149

struct denali_nand_info *denali;

1142

1150

1143

denali = malloc(sizeof(*denali));

1151

denali = malloc(sizeof(*denali));

1144

if (!denali)

1152

if (!denali)

1145

return -ENOMEM;

1153

return -ENOMEM;

1146

1154

1147

nand->priv = denali;

1155

nand->priv = denali;

1148

1156

1149

denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;

1157

denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;

1150

denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;

1158

denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;

1151

1159

1152

#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT

1160

#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT

1153

/* check whether flash got BBT table (located at end of flash). As we

1161

/* check whether flash got BBT table (located at end of flash). As we

1154

* use NAND_BBT_NO_OOB, the BBT page will start with

1162

* use NAND_BBT_NO_OOB, the BBT page will start with

1155

* bbt_pattern. We will have mirror pattern too */

1163

* bbt_pattern. We will have mirror pattern too */

1156

nand->bbt_options |= NAND_BBT_USE_FLASH;

1164

nand->bbt_options |= NAND_BBT_USE_FLASH;

1157

/*

1165

/*

1158

* We are using main + spare with ECC support. As BBT need ECC support,

1166

* We are using main + spare with ECC support. As BBT need ECC support,

1159

* we need to ensure BBT code don't write to OOB for the BBT pattern.

1167

* we need to ensure BBT code don't write to OOB for the BBT pattern.

1160

* All BBT info will be stored into data area with ECC support.

1168

* All BBT info will be stored into data area with ECC support.

1161

*/

1169

*/

1162

nand->bbt_options |= NAND_BBT_NO_OOB;

1170

nand->bbt_options |= NAND_BBT_NO_OOB;

1163

#endif

1171

#endif

1164

1172

1165

nand->ecc.mode = NAND_ECC_HW;

1173

nand->ecc.mode = NAND_ECC_HW;

1166

nand->ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;

1174

nand->ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;

1167

nand->ecc.read_oob = denali_read_oob;

1175

nand->ecc.read_oob = denali_read_oob;

1168

nand->ecc.write_oob = denali_write_oob;

1176

nand->ecc.write_oob = denali_write_oob;

1169

nand->ecc.read_page = denali_read_page;

1177

nand->ecc.read_page = denali_read_page;

1170

nand->ecc.read_page_raw = denali_read_page_raw;

1178

nand->ecc.read_page_raw = denali_read_page_raw;

1171

nand->ecc.write_page = denali_write_page;

1179

nand->ecc.write_page = denali_write_page;

1172

nand->ecc.write_page_raw = denali_write_page_raw;

1180

nand->ecc.write_page_raw = denali_write_page_raw;

1173

/*

1181

/*

1174

* Tell driver the ecc strength. This register may be already set

1182

* Tell driver the ecc strength. This register may be already set

1175

* correctly. So we read this value out.

1183

* correctly. So we read this value out.

1176

*/

1184

*/

1177

nand->ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);

1185

nand->ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);

1178

switch (nand->ecc.size) {

1186

switch (nand->ecc.size) {

1179

case 512:

1187

case 512:

1180

nand->ecc.bytes = (nand->ecc.strength * 13 + 15) / 16 * 2;

1188

nand->ecc.bytes = (nand->ecc.strength * 13 + 15) / 16 * 2;

1181

break;

1189

break;

1182

case 1024:

1190

case 1024:

1183

nand->ecc.bytes = (nand->ecc.strength * 14 + 15) / 16 * 2;

1191

nand->ecc.bytes = (nand->ecc.strength * 14 + 15) / 16 * 2;

1184

break;

1192

break;

1185

default:

1193

default:

1186

pr_err("Unsupported ECC size\n");

1194

pr_err("Unsupported ECC size\n");

1187

return -EINVAL;

1195

return -EINVAL;

1188

}

1196

}

1189

nand_oob.eccbytes = nand->ecc.bytes;

1197

nand_oob.eccbytes = nand->ecc.bytes;

1190

nand->ecc.layout = &nand_oob;

1198

nand->ecc.layout = &nand_oob;

1191

1199

1192

/* Set address of hardware control function */

1200

/* Set address of hardware control function */

1193

nand->cmdfunc = denali_cmdfunc;

1201

nand->cmdfunc = denali_cmdfunc;

1194

nand->read_byte = denali_read_byte;

1202

nand->read_byte = denali_read_byte;

1195

nand->read_buf = denali_read_buf;

1203

nand->read_buf = denali_read_buf;

1196

nand->select_chip = denali_select_chip;

1204

nand->select_chip = denali_select_chip;

1197

nand->waitfunc = denali_waitfunc;

1205

nand->waitfunc = denali_waitfunc;

1198

denali_hw_init(denali);

1206

denali_hw_init(denali);

1199

return 0;

1207

return 0;

1200

}

1208

}

1201

1209

1202

int board_nand_init(struct nand_chip *chip)

1210

int board_nand_init(struct nand_chip *chip)

1203

{

1211

{

1204

return denali_nand_init(chip);

1212

return denali_nand_init(chip);

GITLAB

Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

 /*
  * Copyright (C) 2014       Panasonic Corporation
  * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
  * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <malloc.h>
 #include <nand.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include "denali.h"
 #define NAND_DEFAULT_TIMINGS	-1
 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
 /* We define a macro here that combines all interrupts this driver uses into
  * a single constant value, for convenience. */
 #define DENALI_IRQ_ALL	(INTR_STATUS__DMA_CMD_COMP | \
 			INTR_STATUS__ECC_TRANSACTION_DONE | \
 			INTR_STATUS__ECC_ERR | \
 			INTR_STATUS__PROGRAM_FAIL | \
 			INTR_STATUS__LOAD_COMP | \
 			INTR_STATUS__PROGRAM_COMP | \
 			INTR_STATUS__TIME_OUT | \
 			INTR_STATUS__ERASE_FAIL | \
 			INTR_STATUS__RST_COMP | \
 			INTR_STATUS__ERASE_COMP | \
 			INTR_STATUS__ECC_UNCOR_ERR | \
 			INTR_STATUS__INT_ACT | \
 			INTR_STATUS__LOCKED_BLK)
 /* indicates whether or not the internal value for the flash bank is
  * valid or not */
 #define CHIP_SELECT_INVALID	-1
 #define SUPPORT_8BITECC		1
 /*
  * this macro allows us to convert from an MTD structure to our own
  * device context (denali) structure.
  */
 #define mtd_to_denali(m) (((struct nand_chip *)mtd->priv)->priv)
 /* These constants are defined by the driver to enable common driver
  * configuration options. */
 #define SPARE_ACCESS		0x41
 #define MAIN_ACCESS		0x42
 #define MAIN_SPARE_ACCESS	0x43
 #define DENALI_UNLOCK_START	0x10
 #define DENALI_UNLOCK_END	0x11
 #define DENALI_LOCK		0x21
 #define DENALI_LOCK_TIGHT	0x31
 #define DENALI_BUFFER_LOAD	0x60
 #define DENALI_BUFFER_WRITE	0x62
 #define DENALI_READ	0
 #define DENALI_WRITE	0x100
 /* types of device accesses. We can issue commands and get status */
 #define COMMAND_CYCLE	0
 #define ADDR_CYCLE	1
 #define STATUS_CYCLE	2
 /* this is a helper macro that allows us to
  * format the bank into the proper bits for the controller */
 #define BANK(x) ((x) << 24)
 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
 static inline void clear_interrupt(struct denali_nand_info *denali,
 							uint32_t irq_mask)
 {
 	uint32_t intr_status_reg;
 	intr_status_reg = INTR_STATUS(denali->flash_bank);
 	writel(irq_mask, denali->flash_reg + intr_status_reg);
 }
 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
 {
 	uint32_t intr_status_reg;
 	intr_status_reg = INTR_STATUS(denali->flash_bank);
 	return readl(denali->flash_reg + intr_status_reg);
 }
 static void clear_interrupts(struct denali_nand_info *denali)
 {
 	uint32_t status;
 	status = read_interrupt_status(denali);
 	clear_interrupt(denali, status);
 	denali->irq_status = 0;
 }
 static void denali_irq_enable(struct denali_nand_info *denali,
 							uint32_t int_mask)
 {
 	int i;
 	for (i = 0; i < denali->max_banks; ++i)
 		writel(int_mask, denali->flash_reg + INTR_EN(i));
 }
 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
 {
 	unsigned long timeout = 1000000;
 	uint32_t intr_status;
 	do {
 		intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;
 		if (intr_status & irq_mask) {
 			denali->irq_status &= ~irq_mask;
 			/* our interrupt was detected */
 			break;
 		}
 		udelay(1);
 		timeout--;
 	} while (timeout != 0);
 	if (timeout == 0) {
 		/* timeout */
 		printf("Denali timeout with interrupt status %08x\n",
 		       read_interrupt_status(denali));
 		intr_status = 0;
 	}
 	return intr_status;
 }
 /*
  * Certain operations for the denali NAND controller use an indexed mode to
  * read/write data. The operation is performed by writing the address value
  * of the command to the device memory followed by the data. This function
  * abstracts this common operation.
 */
 static void index_addr(struct denali_nand_info *denali,
 				uint32_t address, uint32_t data)
 {
 	writel(address, denali->flash_mem + INDEX_CTRL_REG);
 	writel(data, denali->flash_mem + INDEX_DATA_REG);
 }
 /* Perform an indexed read of the device */
 static void index_addr_read_data(struct denali_nand_info *denali,
 				 uint32_t address, uint32_t *pdata)
 {
 	writel(address, denali->flash_mem + INDEX_CTRL_REG);
 	*pdata = readl(denali->flash_mem + INDEX_DATA_REG);
 }
 /* We need to buffer some data for some of the NAND core routines.
  * The operations manage buffering that data. */
 static void reset_buf(struct denali_nand_info *denali)
 {
 	denali->buf.head = 0;
 	denali->buf.tail = 0;
 }
 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
 {
 	denali->buf.buf[denali->buf.tail++] = byte;
 }
 /* resets a specific device connected to the core */
 static void reset_bank(struct denali_nand_info *denali)
 {
 	uint32_t irq_status;
 	uint32_t irq_mask = INTR_STATUS__RST_COMP |
 			    INTR_STATUS__TIME_OUT;
 	clear_interrupts(denali);
 	writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
 	irq_status = wait_for_irq(denali, irq_mask);
 	if (irq_status & INTR_STATUS__TIME_OUT)
 		debug("reset bank failed.\n");
 }
 /* Reset the flash controller */
 static uint32_t denali_nand_reset(struct denali_nand_info *denali)
 {
 	uint32_t i;
 	for (i = 0; i < denali->max_banks; i++)
 		writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
 		       denali->flash_reg + INTR_STATUS(i));
 	for (i = 0; i < denali->max_banks; i++) {
 		writel(1 << i, denali->flash_reg + DEVICE_RESET);
 		while (!(readl(denali->flash_reg + INTR_STATUS(i)) &
 			(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
 			if (readl(denali->flash_reg + INTR_STATUS(i)) &
 				INTR_STATUS__TIME_OUT)
 				debug("NAND Reset operation timed out on bank"
 				      " %d\n", i);
 	}
 	for (i = 0; i < denali->max_banks; i++)
 		writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
 		       denali->flash_reg + INTR_STATUS(i));
 	return 0;
 }
 /*
  * this routine calculates the ONFI timing values for a given mode and
  * programs the clocking register accordingly. The mode is determined by
  * the get_onfi_nand_para routine.
  */
 static void nand_onfi_timing_set(struct denali_nand_info *denali,
 								uint16_t mode)
 {
 	uint32_t trea[6] = {40, 30, 25, 20, 20, 16};
 	uint32_t trp[6] = {50, 25, 17, 15, 12, 10};
 	uint32_t treh[6] = {30, 15, 15, 10, 10, 7};
 	uint32_t trc[6] = {100, 50, 35, 30, 25, 20};
 	uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};
 	uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};
 	uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};
 	uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};
 	uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};
 	uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};
 	uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};
 	uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};
 	uint32_t tclsrising = 1;
 	uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
 	uint32_t dv_window = 0;
 	uint32_t en_lo, en_hi;
 	uint32_t acc_clks;
 	uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
 	en_lo = DIV_ROUND_UP(trp[mode], CLK_X);
 	en_hi = DIV_ROUND_UP(treh[mode], CLK_X);
 	if ((en_hi * CLK_X) < (treh[mode] + 2))
 		en_hi++;
 	if ((en_lo + en_hi) * CLK_X < trc[mode])
 		en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),
 				      CLK_X);
 	if ((en_lo + en_hi) < CLK_MULTI)
 		en_lo += CLK_MULTI - en_lo - en_hi;
 	while (dv_window < 8) {
 		data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];
 		data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];
 		data_invalid =
 		    data_invalid_rhoh <
 		    data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
 		dv_window = data_invalid - trea[mode];
 		if (dv_window < 8)
 			en_lo++;
 	}
 	acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);
 	while (((acc_clks * CLK_X) - trea[mode]) < 3)
 		acc_clks++;
 	if ((data_invalid - acc_clks * CLK_X) < 2)
 		debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);
 	addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);
 	re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);
 	re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);
 	we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);
 	cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);
 	if (!tclsrising)
 		cs_cnt = DIV_ROUND_UP(tcs[mode], CLK_X);
 	if (cs_cnt == 0)
 		cs_cnt = 1;
 	if (tcea[mode]) {
 		while (((cs_cnt * CLK_X) + trea[mode]) < tcea[mode])
 			cs_cnt++;
 	}
 	/* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
 	if ((readl(denali->flash_reg + MANUFACTURER_ID) == 0) &&
 	    (readl(denali->flash_reg + DEVICE_ID) == 0x88))
 		acc_clks = 6;
 	writel(acc_clks, denali->flash_reg + ACC_CLKS);
 	writel(re_2_we, denali->flash_reg + RE_2_WE);
 	writel(re_2_re, denali->flash_reg + RE_2_RE);
 	writel(we_2_re, denali->flash_reg + WE_2_RE);
 	writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);
 	writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
 	writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
 	writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
 }
 /* queries the NAND device to see what ONFI modes it supports. */
 static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)
 {
 	int i;
 	/*
 	 * we needn't to do a reset here because driver has already
 	 * reset all the banks before
 	 */
 	if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &
 	    ONFI_TIMING_MODE__VALUE))
 		return -EIO;
 	for (i = 5; i > 0; i--) {
 		if (readl(denali->flash_reg + ONFI_TIMING_MODE) &
 			(0x01 << i))
 			break;
 	}
 	nand_onfi_timing_set(denali, i);
 	/* By now, all the ONFI devices we know support the page cache */
 	/* rw feature. So here we enable the pipeline_rw_ahead feature */
 	return 0;
 }
 static void get_samsung_nand_para(struct denali_nand_info *denali,
 							uint8_t device_id)
 {
 	if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
 		/* Set timing register values according to datasheet */
 		writel(5, denali->flash_reg + ACC_CLKS);
 		writel(20, denali->flash_reg + RE_2_WE);
 		writel(12, denali->flash_reg + WE_2_RE);
 		writel(14, denali->flash_reg + ADDR_2_DATA);
 		writel(3, denali->flash_reg + RDWR_EN_LO_CNT);
 		writel(2, denali->flash_reg + RDWR_EN_HI_CNT);
 		writel(2, denali->flash_reg + CS_SETUP_CNT);
 	}
 }
 static void get_toshiba_nand_para(struct denali_nand_info *denali)
 {
 	uint32_t tmp;
 	/* Workaround to fix a controller bug which reports a wrong */
 	/* spare area size for some kind of Toshiba NAND device */
 	if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
 	    (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
 		writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
 		tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *
 			readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
 		writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
 	}
 }
 static void get_hynix_nand_para(struct denali_nand_info *denali,
 							uint8_t device_id)
 {
 	uint32_t main_size, spare_size;
 	switch (device_id) {
 	case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
 	case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
 		writel(128, denali->flash_reg + PAGES_PER_BLOCK);
 		writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
 		writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
 		main_size = 4096 *
 			readl(denali->flash_reg + DEVICES_CONNECTED);
 		spare_size = 224 *
 			readl(denali->flash_reg + DEVICES_CONNECTED);
 		writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
 		writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
 		writel(0, denali->flash_reg + DEVICE_WIDTH);
 		break;
 	default:
 		debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
 		      "Will use default parameter values instead.\n",
 		      device_id);
 	}
 }
 /*
  * determines how many NAND chips are connected to the controller. Note for
  * Intel CE4100 devices we don't support more than one device.
  */
 static void find_valid_banks(struct denali_nand_info *denali)
 {
 	uint32_t id[denali->max_banks];
 	int i;
 	denali->total_used_banks = 1;
 	for (i = 0; i < denali->max_banks; i++) {
 		index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
 		index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
 		index_addr_read_data(denali,
 				     (uint32_t)(MODE_11 | (i << 24) | 2),
 				     &id[i]);
 		if (i == 0) {
 			if (!(id[i] & 0x0ff))
 				break;
 		} else {
 			if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
 				denali->total_used_banks++;
 			else
 				break;
 		}
 	}
 }
 /*
  * Use the configuration feature register to determine the maximum number of
  * banks that the hardware supports.
  */
 static void detect_max_banks(struct denali_nand_info *denali)
 {
 	uint32_t features = readl(denali->flash_reg + FEATURES);
 	denali->max_banks = 2 << (features & FEATURES__N_BANKS);
 }
 static void detect_partition_feature(struct denali_nand_info *denali)
 {
 	/*
 	 * For MRST platform, denali->fwblks represent the
 	 * number of blocks firmware is taken,
 	 * FW is in protect partition and MTD driver has no
 	 * permission to access it. So let driver know how many
 	 * blocks it can't touch.
 	 */
 	if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
 		if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &
 			PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
 			denali->fwblks =
 			    ((readl(denali->flash_reg + MIN_MAX_BANK(1)) &
 			      MIN_MAX_BANK__MIN_VALUE) *
 			     denali->blksperchip)
 			    +
 			    (readl(denali->flash_reg + MIN_BLK_ADDR(1)) &
 			    MIN_BLK_ADDR__VALUE);
 		} else {
 			denali->fwblks = SPECTRA_START_BLOCK;
 		}
 	} else {
 		denali->fwblks = SPECTRA_START_BLOCK;
 	}
 }
 static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)
 {
 	uint32_t id_bytes[5], addr;
 	uint8_t i, maf_id, device_id;
 	/* Use read id method to get device ID and other
 	 * params. For some NAND chips, controller can't
 	 * report the correct device ID by reading from
 	 * DEVICE_ID register
 	 * */
 	addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
 	index_addr(denali, (uint32_t)addr | 0, 0x90);
 	index_addr(denali, (uint32_t)addr | 1, 0);
 	for (i = 0; i < 5; i++)
 		index_addr_read_data(denali, addr | 2, &id_bytes[i]);
 	maf_id = id_bytes[0];
 	device_id = id_bytes[1];
 	if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
 		ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
 		if (get_onfi_nand_para(denali))
 			return -EIO;
 	} else if (maf_id == 0xEC) { /* Samsung NAND */
 		get_samsung_nand_para(denali, device_id);
 	} else if (maf_id == 0x98) { /* Toshiba NAND */
 		get_toshiba_nand_para(denali);
 	} else if (maf_id == 0xAD) { /* Hynix NAND */
 		get_hynix_nand_para(denali, device_id);
 	}
 	find_valid_banks(denali);
 	detect_partition_feature(denali);
 	/* If the user specified to override the default timings
 	 * with a specific ONFI mode, we apply those changes here.
 	 */
 	if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
 		nand_onfi_timing_set(denali, onfi_timing_mode);
 	return 0;
 }
 /* validation function to verify that the controlling software is making
  * a valid request
  */
 static inline bool is_flash_bank_valid(int flash_bank)
 {
 	return flash_bank >= 0 && flash_bank < 4;
 }
 static void denali_irq_init(struct denali_nand_info *denali)
 {
 	uint32_t int_mask = 0;
 	int i;
 	/* Disable global interrupts */
 	writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);
 	int_mask = DENALI_IRQ_ALL;
 	/* Clear all status bits */
 	for (i = 0; i < denali->max_banks; ++i)
 		writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));
 	denali_irq_enable(denali, int_mask);
 }
 /* This helper function setups the registers for ECC and whether or not
  * the spare area will be transferred. */
 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
 				bool transfer_spare)
 {
 	int ecc_en_flag = 0, transfer_spare_flag = 0;
 	/* set ECC, transfer spare bits if needed */
 	ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
 	transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
 	/* Enable spare area/ECC per user's request. */
 	writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
 	/* applicable for MAP01 only */
 	writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
 }
 /* sends a pipeline command operation to the controller. See the Denali NAND
  * controller's user guide for more information (section 4.2.3.6).
  */
 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
 					bool ecc_en, bool transfer_spare,
 					int access_type, int op)
 {
 	uint32_t addr, cmd, irq_status;
 	static uint32_t page_count = 1;
 	setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
 	/* clear interrupts */
 	clear_interrupts(denali);
 	addr = BANK(denali->flash_bank) | denali->page;
 	/* setup the acccess type */
 	cmd = MODE_10 | addr;
 	index_addr(denali, cmd, access_type);
 	/* setup the pipeline command */
 	index_addr(denali, cmd, 0x2000 | op | page_count);
 	cmd = MODE_01 | addr;
 	writel(cmd, denali->flash_mem + INDEX_CTRL_REG);
 	if (op == DENALI_READ) {
 		/* wait for command to be accepted */
 		irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);
 		if (irq_status == 0)
 			return -EIO;
 	}
 	return 0;
 }
 /* helper function that simply writes a buffer to the flash */
 static int write_data_to_flash_mem(struct denali_nand_info *denali,
 						const uint8_t *buf, int len)
 {
 	uint32_t i = 0, *buf32;
 	/* verify that the len is a multiple of 4. see comment in
 	 * read_data_from_flash_mem() */
 	BUG_ON((len % 4) != 0);
 	/* write the data to the flash memory */
 	buf32 = (uint32_t *)buf;
 	for (i = 0; i < len / 4; i++)
 		writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);
 	return i * 4; /* intent is to return the number of bytes read */
 }
 /* helper function that simply reads a buffer from the flash */
 static int read_data_from_flash_mem(struct denali_nand_info *denali,
 						uint8_t *buf, int len)
 {
 	uint32_t i, *buf32;
 	/*
 	 * we assume that len will be a multiple of 4, if not
 	 * it would be nice to know about it ASAP rather than
 	 * have random failures...
 	 * This assumption is based on the fact that this
 	 * function is designed to be used to read flash pages,
 	 * which are typically multiples of 4...
 	 */
 	BUG_ON((len % 4) != 0);
 	/* transfer the data from the flash */
 	buf32 = (uint32_t *)buf;
 	for (i = 0; i < len / 4; i++)
 		*buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);
 	return i * 4; /* intent is to return the number of bytes read */
 }
 static void denali_mode_main_access(struct denali_nand_info *denali)
 {
 	uint32_t addr, cmd;
 	addr = BANK(denali->flash_bank) | denali->page;
 	cmd = MODE_10 | addr;
 	index_addr(denali, cmd, MAIN_ACCESS);
 }
 static void denali_mode_main_spare_access(struct denali_nand_info *denali)
 {
 	uint32_t addr, cmd;
 	addr = BANK(denali->flash_bank) | denali->page;
 	cmd = MODE_10 | addr;
 	index_addr(denali, cmd, MAIN_SPARE_ACCESS);
 }
 /* writes OOB data to the device */
 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	uint32_t irq_status;
 	uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
 						INTR_STATUS__PROGRAM_FAIL;
 	int status = 0;
 	denali->page = page;
 	if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
 				     DENALI_WRITE) == 0) {
 		write_data_to_flash_mem(denali, buf, mtd->oobsize);
 		/* wait for operation to complete */
 		irq_status = wait_for_irq(denali, irq_mask);
 		if (irq_status == 0) {
 			dev_err(denali->dev, "OOB write failed\n");
 			status = -EIO;
 		}
 	} else {
 		printf("unable to send pipeline command\n");
 		status = -EIO;
 	}
 	return status;
 }
 /* reads OOB data from the device */
 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	uint32_t irq_mask = INTR_STATUS__LOAD_COMP,
 			 irq_status = 0, addr = 0x0, cmd = 0x0;
 	denali->page = page;
 	if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
 				     DENALI_READ) == 0) {
 		read_data_from_flash_mem(denali, buf, mtd->oobsize);
 		/* wait for command to be accepted
 		 * can always use status0 bit as the mask is identical for each
 		 * bank. */
 		irq_status = wait_for_irq(denali, irq_mask);
 		if (irq_status == 0)
 			printf("page on OOB timeout %d\n", denali->page);
 		/* We set the device back to MAIN_ACCESS here as I observed
 		 * instability with the controller if you do a block erase
 		 * and the last transaction was a SPARE_ACCESS. Block erase
 		 * is reliable (according to the MTD test infrastructure)
 		 * if you are in MAIN_ACCESS.
 		 */
 		addr = BANK(denali->flash_bank) | denali->page;
 		cmd = MODE_10 | addr;
 		index_addr(denali, cmd, MAIN_ACCESS);
 	}
 }
 /* this function examines buffers to see if they contain data that
  * indicate that the buffer is part of an erased region of flash.
  */
 static bool is_erased(uint8_t *buf, int len)
 {
 	int i = 0;
 	for (i = 0; i < len; i++)
 		if (buf[i] != 0xFF)
 			return false;
 	return true;
 }
 /* programs the controller to either enable/disable DMA transfers */
 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
 {
 	uint32_t reg_val = 0x0;
 	if (en)
 		reg_val = DMA_ENABLE__FLAG;
 	writel(reg_val, denali->flash_reg + DMA_ENABLE);
 	readl(denali->flash_reg + DMA_ENABLE);
 }
 /* setups the HW to perform the data DMA */
 static void denali_setup_dma(struct denali_nand_info *denali, int op)
 {
 	uint32_t mode;
 	const int page_count = 1;
 	uint32_t addr = (uint32_t)denali->buf.dma_buf;
 	flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));
 /* For Denali controller that is 64 bit bus IP core */
 #ifdef CONFIG_SYS_NAND_DENALI_64BIT
 	mode = MODE_10 | BANK(denali->flash_bank) | denali->page;
 	/* DMA is a three step process */
 	/* 1. setup transfer type, interrupt when complete,
 	      burst len = 64 bytes, the number of pages */
 	index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);
 	/* 2. set memory low address bits 31:0 */
 	index_addr(denali, mode, addr);
 	/* 3. set memory high address bits 64:32 */
 	index_addr(denali, mode, 0);
 #else
 	mode = MODE_10 | BANK(denali->flash_bank);
 	/* DMA is a four step process */
 	/* 1. setup transfer type and # of pages */
 	index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
 	/* 2. set memory high address bits 23:8 */
 	index_addr(denali, mode | ((uint32_t)(addr >> 16) << 8), 0x2200);
 	/* 3. set memory low address bits 23:8 */
 	index_addr(denali, mode | ((uint32_t)addr << 8), 0x2300);
 	/* 4.  interrupt when complete, burst len = 64 bytes*/
 	index_addr(denali, mode | 0x14000, 0x2400);
 #endif
 }
 /* Common DMA function */
 static uint32_t denali_dma_configuration(struct denali_nand_info *denali,
 					 uint32_t ops, bool raw_xfer,
 					 uint32_t irq_mask, int oob_required)
 {
 	uint32_t irq_status = 0;
 	/* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */
 	setup_ecc_for_xfer(denali, !raw_xfer, oob_required);
 	/* clear any previous interrupt flags */
 	clear_interrupts(denali);
 	/* enable the DMA */
 	denali_enable_dma(denali, true);
 	/* setup the DMA */
 	denali_setup_dma(denali, ops);
 	/* wait for operation to complete */
 	irq_status = wait_for_irq(denali, irq_mask);
 	/* if ECC fault happen, seems we need delay before turning off DMA.
 	 * If not, the controller will go into non responsive condition */
 	if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)
 		udelay(100);
 	/* disable the DMA */
 	denali_enable_dma(denali, false);
 	return irq_status;
 }
 static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
 			const uint8_t *buf, bool raw_xfer, int oob_required)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	uint32_t irq_status = 0;
 	uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
 	denali->status = 0;
 	/* copy buffer into DMA buffer */
 	memcpy(denali->buf.dma_buf, buf, mtd->writesize);
 	/* need extra memcpy for raw transfer */
 	if (raw_xfer)
 		memcpy(denali->buf.dma_buf + mtd->writesize,
 		       chip->oob_poi, mtd->oobsize);
 	/* setting up DMA */
 	irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,
 					      irq_mask, oob_required);
 	/* if timeout happen, error out */
 	if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
 		debug("DMA timeout for denali write_page\n");
 		denali->status = NAND_STATUS_FAIL;
 		return -EIO;
 	}
 	if (irq_status & INTR_STATUS__LOCKED_BLK) {
 		debug("Failed as write to locked block\n");
 		denali->status = NAND_STATUS_FAIL;
 		return -EIO;
 	}
 	return 0;
 }
 /* NAND core entry points */
 /*
  * this is the callback that the NAND core calls to write a page. Since
  * writing a page with ECC or without is similar, all the work is done
  * by write_page above.
  */
 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 				const uint8_t *buf, int oob_required)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	/*
 	 * for regular page writes, we let HW handle all the ECC
 	 * data written to the device.
 	 */
 	if (oob_required)
 		/* switch to main + spare access */
 		denali_mode_main_spare_access(denali);
 	else
 		/* switch to main access only */
 		denali_mode_main_access(denali);
 	return write_page(mtd, chip, buf, false, oob_required);
 }
 /*
  * This is the callback that the NAND core calls to write a page without ECC.
  * raw access is similar to ECC page writes, so all the work is done in the
  * write_page() function above.
  */
 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 					const uint8_t *buf, int oob_required)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	/*
 	 * for raw page writes, we want to disable ECC and simply write
 	 * whatever data is in the buffer.
 	 */
 	if (oob_required)
 		/* switch to main + spare access */
 		denali_mode_main_spare_access(denali);
 	else
 		/* switch to main access only */
 		denali_mode_main_access(denali);
 	return write_page(mtd, chip, buf, true, oob_required);
 }
 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 				int page)
 {
 	return write_oob_data(mtd, chip->oob_poi, page);
 }
 /* raw include ECC value and all the spare area */
 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 				uint8_t *buf, int oob_required, int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
 	if (denali->page != page) {
 		debug("Missing NAND_CMD_READ0 command\n");
 		return -EIO;
 	}
 	if (oob_required)
 		/* switch to main + spare access */
 		denali_mode_main_spare_access(denali);
 	else
 		/* switch to main access only */
 		denali_mode_main_access(denali);
 	/* setting up the DMA where ecc_enable is false */
 	irq_status = denali_dma_configuration(denali, DENALI_READ, true,
 					      irq_mask, oob_required);
 	/* if timeout happen, error out */
 	if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
 		debug("DMA timeout for denali_read_page_raw\n");
 		return -EIO;
 	}
 	/* splitting the content to destination buffer holder */
 	memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),
 	       mtd->oobsize);
 	memcpy(buf, denali->buf.dma_buf, mtd->writesize);
 	return 0;
 }
 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 				uint8_t *buf, int oob_required, int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	uint32_t irq_status, irq_mask =	INTR_STATUS__DMA_CMD_COMP;
 	if (denali->page != page) {
 		debug("Missing NAND_CMD_READ0 command\n");
 		return -EIO;
 	}
 	if (oob_required)
 		/* switch to main + spare access */
 		denali_mode_main_spare_access(denali);
 	else
 		/* switch to main access only */
 		denali_mode_main_access(denali);
 	/* setting up the DMA where ecc_enable is true */
 	irq_status = denali_dma_configuration(denali, DENALI_READ, false,
 					      irq_mask, oob_required);
 	memcpy(buf, denali->buf.dma_buf, mtd->writesize);
 	/* check whether any ECC error */
 	if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {
 		/* is the ECC cause by erase page, check using read_page_raw */
 		debug("  Uncorrected ECC detected\n");
 		denali_read_page_raw(mtd, chip, buf, oob_required,
 				     denali->page);
 		if (is_erased(buf, mtd->writesize) == true &&
 		    is_erased(chip->oob_poi, mtd->oobsize) == true) {
 			debug("  ECC error cause by erased block\n");
 			/* false alarm, return the 0xFF */
 		} else {
 			return -EIO;
 		}
 	}
 	memcpy(buf, denali->buf.dma_buf, mtd->writesize);
 	return 0;
 }
 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 				int page)
 {
 	read_oob_data(mtd, chip->oob_poi, page);
 	return 0;
 }
 static uint8_t denali_read_byte(struct mtd_info *mtd)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	uint32_t addr, result;
 	addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
 	index_addr_read_data(denali, addr | 2, &result);
 	return (uint8_t)result & 0xFF;
 }
 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	uint32_t i, addr, result;
 	/* delay for tR (data transfer from Flash array to data register) */
 	udelay(25);
 	/* ensure device completed else additional delay and polling */
 	wait_for_irq(denali, INTR_STATUS__INT_ACT);
 	addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
 	for (i = 0; i < len; i++) {
 		index_addr_read_data(denali, (uint32_t)addr | 2, &result);
 		write_byte_to_buf(denali, result);
 	}
 	memcpy(buf, denali->buf.buf, len);
 }
 static void denali_select_chip(struct mtd_info *mtd, int chip)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	denali->flash_bank = chip;
 }
 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	int status = denali->status;
 	denali->status = 0;
 	return status;
 }
 static void denali_erase(struct mtd_info *mtd, int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	uint32_t cmd, irq_status;
 	/* clear interrupts */
 	clear_interrupts(denali);
 	/* setup page read request for access type */
 	cmd = MODE_10 | BANK(denali->flash_bank) | page;
 	index_addr(denali, cmd, 0x1);
 	/* wait for erase to complete or failure to occur */
 	irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
 					INTR_STATUS__ERASE_FAIL);
 	if (irq_status & INTR_STATUS__ERASE_FAIL ||
 	    irq_status & INTR_STATUS__LOCKED_BLK)
 		denali->status = NAND_STATUS_FAIL;
 	else
 		denali->status = 0;
 }
 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
 			   int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 	uint32_t addr;
 	switch (cmd) {
 	case NAND_CMD_PAGEPROG:
 		break;
 	case NAND_CMD_STATUS:
 		addr = MODE_11 | BANK(denali->flash_bank);
 		index_addr(denali, addr | 0, cmd);
 		break;
-	case NAND_CMD_PARAM:
-		clear_interrupts(denali);
 	case NAND_CMD_READID:
+	case NAND_CMD_PARAM:
 		reset_buf(denali);
 		/* sometimes ManufactureId read from register is not right
 		 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
 		 * So here we send READID cmd to NAND insteand
 		 * */
 		addr = MODE_11 | BANK(denali->flash_bank);
 		index_addr(denali, addr | 0, cmd);
 		index_addr(denali, addr | 1, col & 0xFF);
+		if (cmd == NAND_CMD_PARAM)
+			udelay(50);
+		break;
+	case NAND_CMD_RNDOUT:
+		addr = MODE_11 | BANK(denali->flash_bank);
+		index_addr(denali, addr | 0, cmd);
+		index_addr(denali, addr | 1, col & 0xFF);
+		index_addr(denali, addr | 1, col >> 8);
+		index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART);
 		break;
 	case NAND_CMD_READ0:
 	case NAND_CMD_SEQIN:
 		denali->page = page;
 		break;
 	case NAND_CMD_RESET:
 		reset_bank(denali);
 		break;
 	case NAND_CMD_READOOB:
 		/* TODO: Read OOB data */
 		break;
 	case NAND_CMD_ERASE1:
 		/*
 		 * supporting block erase only, not multiblock erase as
 		 * it will cross plane and software need complex calculation
 		 * to identify the block count for the cross plane
 		 */
 		denali_erase(mtd, page);
 		break;
 	case NAND_CMD_ERASE2:
 		/* nothing to do here as it was done during NAND_CMD_ERASE1 */
 		break;
 	case NAND_CMD_UNLOCK1:
 		addr = MODE_10 | BANK(denali->flash_bank) | page;
 		index_addr(denali, addr | 0, DENALI_UNLOCK_START);
 		break;
 	case NAND_CMD_UNLOCK2:
 		addr = MODE_10 | BANK(denali->flash_bank) | page;
 		index_addr(denali, addr | 0, DENALI_UNLOCK_END);
 		break;
 	case NAND_CMD_LOCK:
 		addr = MODE_10 | BANK(denali->flash_bank);
 		index_addr(denali, addr | 0, DENALI_LOCK);
 		break;
 	default:
 		printf(": unsupported command received 0x%x\n", cmd);
 		break;
 	}
 }
 /* end NAND core entry points */
 /* Initialization code to bring the device up to a known good state */
 static void denali_hw_init(struct denali_nand_info *denali)
 {
 	/*
 	 * tell driver how many bit controller will skip before writing
 	 * ECC code in OOB. This is normally used for bad block marker
 	 */
 	writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
 	       denali->flash_reg + SPARE_AREA_SKIP_BYTES);
 	detect_max_banks(denali);
 	denali_nand_reset(denali);
 	writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);
 	writel(CHIP_EN_DONT_CARE__FLAG,
 	       denali->flash_reg + CHIP_ENABLE_DONT_CARE);
 	writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
 	/* Should set value for these registers when init */
 	writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
 	writel(1, denali->flash_reg + ECC_ENABLE);
 	denali_nand_timing_set(denali);
 	denali_irq_init(denali);
 }
 static struct nand_ecclayout nand_oob;
 static int denali_nand_init(struct nand_chip *nand)
 {
 	struct denali_nand_info *denali;
 	denali = malloc(sizeof(*denali));
 	if (!denali)
 		return -ENOMEM;
 	nand->priv = denali;
 	denali->flash_reg = (void  __iomem *)CONFIG_SYS_NAND_REGS_BASE;
 	denali->flash_mem = (void  __iomem *)CONFIG_SYS_NAND_DATA_BASE;
 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
 	/* check whether flash got BBT table (located at end of flash). As we
 	 * use NAND_BBT_NO_OOB, the BBT page will start with
 	 * bbt_pattern. We will have mirror pattern too */
 	nand->bbt_options |= NAND_BBT_USE_FLASH;
 	/*
 	 * We are using main + spare with ECC support. As BBT need ECC support,
 	 * we need to ensure BBT code don't write to OOB for the BBT pattern.
 	 * All BBT info will be stored into data area with ECC support.
 	 */
 	nand->bbt_options |= NAND_BBT_NO_OOB;
 #endif
 	nand->ecc.mode = NAND_ECC_HW;
 	nand->ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
 	nand->ecc.read_oob = denali_read_oob;
 	nand->ecc.write_oob = denali_write_oob;
 	nand->ecc.read_page = denali_read_page;
 	nand->ecc.read_page_raw = denali_read_page_raw;
 	nand->ecc.write_page = denali_write_page;
 	nand->ecc.write_page_raw = denali_write_page_raw;
 	/*
 	 * Tell driver the ecc strength. This register may be already set
 	 * correctly. So we read this value out.
 	 */
 	nand->ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
 	switch (nand->ecc.size) {
 	case 512:
 		nand->ecc.bytes = (nand->ecc.strength * 13 + 15) / 16 * 2;
 		break;
 	case 1024:
 		nand->ecc.bytes = (nand->ecc.strength * 14 + 15) / 16 * 2;
 		break;
 	default:
 		pr_err("Unsupported ECC size\n");
 		return -EINVAL;
 	}
 	nand_oob.eccbytes = nand->ecc.bytes;
 	nand->ecc.layout = &nand_oob;
 	/* Set address of hardware control function */
 	nand->cmdfunc = denali_cmdfunc;
 	nand->read_byte = denali_read_byte;
 	nand->read_buf = denali_read_buf;
 	nand->select_chip = denali_select_chip;
 	nand->waitfunc = denali_waitfunc;
 	denali_hw_init(denali);
 	return 0;
 }
 int board_nand_init(struct nand_chip *chip)
 {
 	return denali_nand_init(chip);