Eric Lee / smarc-uboot | Embedian Git Server

Commit de6f604de245b19ce2e330bc63b6522af134d7ae

Authored by Troy Kisky 2012-04-25 01:33:25 +0800

Committed by Heiko Schocher 2012-07-11 16:54:29 +0800

Exists in master and in 54 other branches

mxc_i2c: specify i2c base address in config file

The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>

Showing 10 changed files with 20 additions and 29 deletions Inline Diff

arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/imx-regs.h
drivers/i2c/mxc_i2c.c
include/configs/flea3.h
include/configs/imx31_phycore.h
include/configs/mx35pdk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h

arch/arm/include/asm/arch-mx31/imx-regs.h

Diff comments View file @ de6f604

 /*
  *
  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __ASM_ARCH_MX31_IMX_REGS_H
 #define __ASM_ARCH_MX31_IMX_REGS_H
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 /* Clock control module registers */
 struct clock_control_regs {
 	u32 ccmr;
 	u32 pdr0;
 	u32 pdr1;
 	u32 rcsr;
 	u32 mpctl;
 	u32 upctl;
 	u32 spctl;
 	u32 cosr;
 	u32 cgr0;
 	u32 cgr1;
 	u32 cgr2;
 	u32 wimr0;
 	u32 ldc;
 	u32 dcvr0;
 	u32 dcvr1;
 	u32 dcvr2;
 	u32 dcvr3;
 	u32 ltr0;
 	u32 ltr1;
 	u32 ltr2;
 	u32 ltr3;
 	u32 ltbr0;
 	u32 ltbr1;
 	u32 pmcr0;
 	u32 pmcr1;
 	u32 pdr2;
 };
 struct cspi_regs {
 	u32 rxdata;
 	u32 txdata;
 	u32 ctrl;
 	u32 intr;
 	u32 dma;
 	u32 stat;
 	u32 period;
 	u32 test;
 };
 /* Watchdog Timer (WDOG) registers */
 #define WDOG_ENABLE	(1 << 2)
 #define WDOG_WT_SHIFT	8
 #define WDOG_WDZST	(1 << 0)
 struct wdog_regs {
 	u16 wcr;	/* Control */
 	u16 wsr;	/* Service */
 	u16 wrsr;	/* Reset Status */
 };
 /* IIM Control Registers */
 struct iim_regs {
 	u32 iim_stat;
 	u32 iim_statm;
 	u32 iim_err;
 	u32 iim_emask;
 	u32 iim_fctl;
 	u32 iim_ua;
 	u32 iim_la;
 	u32 iim_sdat;
 	u32 iim_prev;
 	u32 iim_srev;
 	u32 iim_prog_p;
 	u32 iim_scs0;
 	u32 iim_scs1;
 	u32 iim_scs2;
 	u32 iim_scs3;
 };
 struct iomuxc_regs {
 	u32 unused1;
 	u32 unused2;
 	u32 gpr;
 };
 struct mx3_cpu_type {
 	u8 srev;
 	u32 v;
 };
 #define IOMUX_PADNUM_MASK	0x1ff
 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
 /*
  * various IOMUX pad functions
  */
 enum iomux_pad_config {
 	PAD_CTL_NOLOOPBACK	= 0x0 << 9,
 	PAD_CTL_LOOPBACK	= 0x1 << 9,
 	PAD_CTL_PKE_NONE	= 0x0 << 8,
 	PAD_CTL_PKE_ENABLE	= 0x1 << 8,
 	PAD_CTL_PUE_KEEPER	= 0x0 << 7,
 	PAD_CTL_PUE_PUD		= 0x1 << 7,
 	PAD_CTL_100K_PD		= 0x0 << 5,
 	PAD_CTL_100K_PU		= 0x1 << 5,
 	PAD_CTL_47K_PU		= 0x2 << 5,
 	PAD_CTL_22K_PU		= 0x3 << 5,
 	PAD_CTL_HYS_CMOS	= 0x0 << 4,
 	PAD_CTL_HYS_SCHMITZ	= 0x1 << 4,
 	PAD_CTL_ODE_CMOS	= 0x0 << 3,
 	PAD_CTL_ODE_OpenDrain	= 0x1 << 3,
 	PAD_CTL_DRV_NORMAL	= 0x0 << 1,
 	PAD_CTL_DRV_HIGH	= 0x1 << 1,
 	PAD_CTL_DRV_MAX		= 0x2 << 1,
 	PAD_CTL_SRE_SLOW	= 0x0 << 0,
 	PAD_CTL_SRE_FAST	= 0x1 << 0
 };
 /*
  * This enumeration is constructed based on the Section
  * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
  * value is constructed based on the rules described above.
  */
 enum iomux_pins {
 	MX31_PIN_TTM_PAD	= IOMUX_PIN(0xff,   0),
 	MX31_PIN_CSPI3_SPI_RDY	= IOMUX_PIN(0xff,   1),
 	MX31_PIN_CSPI3_SCLK	= IOMUX_PIN(0xff,   2),
 	MX31_PIN_CSPI3_MISO	= IOMUX_PIN(0xff,   3),
 	MX31_PIN_CSPI3_MOSI	= IOMUX_PIN(0xff,   4),
 	MX31_PIN_CLKSS		= IOMUX_PIN(0xff,   5),
 	MX31_PIN_CE_CONTROL	= IOMUX_PIN(0xff,   6),
 	MX31_PIN_ATA_RESET_B	= IOMUX_PIN(95,     7),
 	MX31_PIN_ATA_DMACK	= IOMUX_PIN(94,     8),
 	MX31_PIN_ATA_DIOW	= IOMUX_PIN(93,     9),
 	MX31_PIN_ATA_DIOR	= IOMUX_PIN(92,    10),
 	MX31_PIN_ATA_CS1	= IOMUX_PIN(91,    11),
 	MX31_PIN_ATA_CS0	= IOMUX_PIN(90,    12),
 	MX31_PIN_SD1_DATA3	= IOMUX_PIN(63,    13),
 	MX31_PIN_SD1_DATA2	= IOMUX_PIN(62,    14),
 	MX31_PIN_SD1_DATA1	= IOMUX_PIN(61,    15),
 	MX31_PIN_SD1_DATA0	= IOMUX_PIN(60,    16),
 	MX31_PIN_SD1_CLK	= IOMUX_PIN(59,    17),
 	MX31_PIN_SD1_CMD	= IOMUX_PIN(58,    18),
 	MX31_PIN_D3_SPL		= IOMUX_PIN(0xff,  19),
 	MX31_PIN_D3_CLS		= IOMUX_PIN(0xff,  20),
 	MX31_PIN_D3_REV		= IOMUX_PIN(0xff,  21),
 	MX31_PIN_CONTRAST	= IOMUX_PIN(0xff,  22),
 	MX31_PIN_VSYNC3		= IOMUX_PIN(0xff,  23),
 	MX31_PIN_READ		= IOMUX_PIN(0xff,  24),
 	MX31_PIN_WRITE		= IOMUX_PIN(0xff,  25),
 	MX31_PIN_PAR_RS		= IOMUX_PIN(0xff,  26),
 	MX31_PIN_SER_RS		= IOMUX_PIN(89,    27),
 	MX31_PIN_LCS1		= IOMUX_PIN(88,    28),
 	MX31_PIN_LCS0		= IOMUX_PIN(87,    29),
 	MX31_PIN_SD_D_CLK	= IOMUX_PIN(86,    30),
 	MX31_PIN_SD_D_IO	= IOMUX_PIN(85,    31),
 	MX31_PIN_SD_D_I		= IOMUX_PIN(84,    32),
 	MX31_PIN_DRDY0		= IOMUX_PIN(0xff,  33),
 	MX31_PIN_FPSHIFT	= IOMUX_PIN(0xff,  34),
 	MX31_PIN_HSYNC		= IOMUX_PIN(0xff,  35),
 	MX31_PIN_VSYNC0		= IOMUX_PIN(0xff,  36),
 	MX31_PIN_LD17		= IOMUX_PIN(0xff,  37),
 	MX31_PIN_LD16		= IOMUX_PIN(0xff,  38),
 	MX31_PIN_LD15		= IOMUX_PIN(0xff,  39),
 	MX31_PIN_LD14		= IOMUX_PIN(0xff,  40),
 	MX31_PIN_LD13		= IOMUX_PIN(0xff,  41),
 	MX31_PIN_LD12		= IOMUX_PIN(0xff,  42),
 	MX31_PIN_LD11		= IOMUX_PIN(0xff,  43),
 	MX31_PIN_LD10		= IOMUX_PIN(0xff,  44),
 	MX31_PIN_LD9		= IOMUX_PIN(0xff,  45),
 	MX31_PIN_LD8		= IOMUX_PIN(0xff,  46),
 	MX31_PIN_LD7		= IOMUX_PIN(0xff,  47),
 	MX31_PIN_LD6		= IOMUX_PIN(0xff,  48),
 	MX31_PIN_LD5		= IOMUX_PIN(0xff,  49),
 	MX31_PIN_LD4		= IOMUX_PIN(0xff,  50),
 	MX31_PIN_LD3		= IOMUX_PIN(0xff,  51),
 	MX31_PIN_LD2		= IOMUX_PIN(0xff,  52),
 	MX31_PIN_LD1		= IOMUX_PIN(0xff,  53),
 	MX31_PIN_LD0		= IOMUX_PIN(0xff,  54),
 	MX31_PIN_USBH2_DATA1	= IOMUX_PIN(0xff,  55),
 	MX31_PIN_USBH2_DATA0	= IOMUX_PIN(0xff,  56),
 	MX31_PIN_USBH2_NXT	= IOMUX_PIN(0xff,  57),
 	MX31_PIN_USBH2_STP	= IOMUX_PIN(0xff,  58),
 	MX31_PIN_USBH2_DIR	= IOMUX_PIN(0xff,  59),
 	MX31_PIN_USBH2_CLK	= IOMUX_PIN(0xff,  60),
 	MX31_PIN_USBOTG_DATA7	= IOMUX_PIN(0xff,  61),
 	MX31_PIN_USBOTG_DATA6	= IOMUX_PIN(0xff,  62),
 	MX31_PIN_USBOTG_DATA5	= IOMUX_PIN(0xff,  63),
 	MX31_PIN_USBOTG_DATA4	= IOMUX_PIN(0xff,  64),
 	MX31_PIN_USBOTG_DATA3	= IOMUX_PIN(0xff,  65),
 	MX31_PIN_USBOTG_DATA2	= IOMUX_PIN(0xff,  66),
 	MX31_PIN_USBOTG_DATA1	= IOMUX_PIN(0xff,  67),
 	MX31_PIN_USBOTG_DATA0	= IOMUX_PIN(0xff,  68),
 	MX31_PIN_USBOTG_NXT	= IOMUX_PIN(0xff,  69),
 	MX31_PIN_USBOTG_STP	= IOMUX_PIN(0xff,  70),
 	MX31_PIN_USBOTG_DIR	= IOMUX_PIN(0xff,  71),
 	MX31_PIN_USBOTG_CLK	= IOMUX_PIN(0xff,  72),
 	MX31_PIN_USB_BYP	= IOMUX_PIN(31,    73),
 	MX31_PIN_USB_OC		= IOMUX_PIN(30,    74),
 	MX31_PIN_USB_PWR	= IOMUX_PIN(29,    75),
 	MX31_PIN_SJC_MOD	= IOMUX_PIN(0xff,  76),
 	MX31_PIN_DE_B		= IOMUX_PIN(0xff,  77),
 	MX31_PIN_TRSTB		= IOMUX_PIN(0xff,  78),
 	MX31_PIN_TDO		= IOMUX_PIN(0xff,  79),
 	MX31_PIN_TDI		= IOMUX_PIN(0xff,  80),
 	MX31_PIN_TMS		= IOMUX_PIN(0xff,  81),
 	MX31_PIN_TCK		= IOMUX_PIN(0xff,  82),
 	MX31_PIN_RTCK		= IOMUX_PIN(0xff,  83),
 	MX31_PIN_KEY_COL7	= IOMUX_PIN(57,    84),
 	MX31_PIN_KEY_COL6	= IOMUX_PIN(56,    85),
 	MX31_PIN_KEY_COL5	= IOMUX_PIN(55,    86),
 	MX31_PIN_KEY_COL4	= IOMUX_PIN(54,    87),
 	MX31_PIN_KEY_COL3	= IOMUX_PIN(0xff,  88),
 	MX31_PIN_KEY_COL2	= IOMUX_PIN(0xff,  89),
 	MX31_PIN_KEY_COL1	= IOMUX_PIN(0xff,  90),
 	MX31_PIN_KEY_COL0	= IOMUX_PIN(0xff,  91),
 	MX31_PIN_KEY_ROW7	= IOMUX_PIN(53,    92),
 	MX31_PIN_KEY_ROW6	= IOMUX_PIN(52,    93),
 	MX31_PIN_KEY_ROW5	= IOMUX_PIN(51,    94),
 	MX31_PIN_KEY_ROW4	= IOMUX_PIN(50,    95),
 	MX31_PIN_KEY_ROW3	= IOMUX_PIN(0xff,  96),
 	MX31_PIN_KEY_ROW2	= IOMUX_PIN(0xff,  97),
 	MX31_PIN_KEY_ROW1	= IOMUX_PIN(0xff,  98),
 	MX31_PIN_KEY_ROW0	= IOMUX_PIN(0xff,  99),
 	MX31_PIN_BATT_LINE	= IOMUX_PIN(49,   100),
 	MX31_PIN_CTS2		= IOMUX_PIN(0xff, 101),
 	MX31_PIN_RTS2		= IOMUX_PIN(0xff, 102),
 	MX31_PIN_TXD2		= IOMUX_PIN(28,   103),
 	MX31_PIN_RXD2		= IOMUX_PIN(27,   104),
 	MX31_PIN_DTR_DCE2	= IOMUX_PIN(48,   105),
 	MX31_PIN_DCD_DTE1	= IOMUX_PIN(47,   106),
 	MX31_PIN_RI_DTE1	= IOMUX_PIN(46,   107),
 	MX31_PIN_DSR_DTE1	= IOMUX_PIN(45,   108),
 	MX31_PIN_DTR_DTE1	= IOMUX_PIN(44,   109),
 	MX31_PIN_DCD_DCE1	= IOMUX_PIN(43,   110),
 	MX31_PIN_RI_DCE1	= IOMUX_PIN(42,   111),
 	MX31_PIN_DSR_DCE1	= IOMUX_PIN(41,   112),
 	MX31_PIN_DTR_DCE1	= IOMUX_PIN(40,   113),
 	MX31_PIN_CTS1		= IOMUX_PIN(39,   114),
 	MX31_PIN_RTS1		= IOMUX_PIN(38,   115),
 	MX31_PIN_TXD1		= IOMUX_PIN(37,   116),
 	MX31_PIN_RXD1		= IOMUX_PIN(36,   117),
 	MX31_PIN_CSPI2_SPI_RDY	= IOMUX_PIN(0xff, 118),
 	MX31_PIN_CSPI2_SCLK	= IOMUX_PIN(0xff, 119),
 	MX31_PIN_CSPI2_SS2	= IOMUX_PIN(0xff, 120),
 	MX31_PIN_CSPI2_SS1	= IOMUX_PIN(0xff, 121),
 	MX31_PIN_CSPI2_SS0	= IOMUX_PIN(0xff, 122),
 	MX31_PIN_CSPI2_MISO	= IOMUX_PIN(0xff, 123),
 	MX31_PIN_CSPI2_MOSI	= IOMUX_PIN(0xff, 124),
 	MX31_PIN_CSPI1_SPI_RDY	= IOMUX_PIN(0xff, 125),
 	MX31_PIN_CSPI1_SCLK	= IOMUX_PIN(0xff, 126),
 	MX31_PIN_CSPI1_SS2	= IOMUX_PIN(0xff, 127),
 	MX31_PIN_CSPI1_SS1	= IOMUX_PIN(0xff, 128),
 	MX31_PIN_CSPI1_SS0	= IOMUX_PIN(0xff, 129),
 	MX31_PIN_CSPI1_MISO	= IOMUX_PIN(0xff, 130),
 	MX31_PIN_CSPI1_MOSI	= IOMUX_PIN(0xff, 131),
 	MX31_PIN_SFS6		= IOMUX_PIN(26,   132),
 	MX31_PIN_SCK6		= IOMUX_PIN(25,   133),
 	MX31_PIN_SRXD6		= IOMUX_PIN(24,   134),
 	MX31_PIN_STXD6		= IOMUX_PIN(23,   135),
 	MX31_PIN_SFS5		= IOMUX_PIN(0xff, 136),
 	MX31_PIN_SCK5		= IOMUX_PIN(0xff, 137),
 	MX31_PIN_SRXD5		= IOMUX_PIN(22,   138),
 	MX31_PIN_STXD5		= IOMUX_PIN(21,   139),
 	MX31_PIN_SFS4		= IOMUX_PIN(0xff, 140),
 	MX31_PIN_SCK4		= IOMUX_PIN(0xff, 141),
 	MX31_PIN_SRXD4		= IOMUX_PIN(20,   142),
 	MX31_PIN_STXD4		= IOMUX_PIN(19,   143),
 	MX31_PIN_SFS3		= IOMUX_PIN(0xff, 144),
 	MX31_PIN_SCK3		= IOMUX_PIN(0xff, 145),
 	MX31_PIN_SRXD3		= IOMUX_PIN(18,   146),
 	MX31_PIN_STXD3		= IOMUX_PIN(17,   147),
 	MX31_PIN_I2C_DAT	= IOMUX_PIN(0xff, 148),
 	MX31_PIN_I2C_CLK	= IOMUX_PIN(0xff, 149),
 	MX31_PIN_CSI_PIXCLK	= IOMUX_PIN(83,   150),
 	MX31_PIN_CSI_HSYNC	= IOMUX_PIN(82,   151),
 	MX31_PIN_CSI_VSYNC	= IOMUX_PIN(81,   152),
 	MX31_PIN_CSI_MCLK	= IOMUX_PIN(80,   153),
 	MX31_PIN_CSI_D15	= IOMUX_PIN(79,   154),
 	MX31_PIN_CSI_D14	= IOMUX_PIN(78,   155),
 	MX31_PIN_CSI_D13	= IOMUX_PIN(77,   156),
 	MX31_PIN_CSI_D12	= IOMUX_PIN(76,   157),
 	MX31_PIN_CSI_D11	= IOMUX_PIN(75,   158),
 	MX31_PIN_CSI_D10	= IOMUX_PIN(74,   159),
 	MX31_PIN_CSI_D9		= IOMUX_PIN(73,   160),
 	MX31_PIN_CSI_D8		= IOMUX_PIN(72,   161),
 	MX31_PIN_CSI_D7		= IOMUX_PIN(71,   162),
 	MX31_PIN_CSI_D6		= IOMUX_PIN(70,   163),
 	MX31_PIN_CSI_D5		= IOMUX_PIN(69,   164),
 	MX31_PIN_CSI_D4		= IOMUX_PIN(68,   165),
 	MX31_PIN_M_GRANT	= IOMUX_PIN(0xff, 166),
 	MX31_PIN_M_REQUEST	= IOMUX_PIN(0xff, 167),
 	MX31_PIN_PC_POE		= IOMUX_PIN(0xff, 168),
 	MX31_PIN_PC_RW_B	= IOMUX_PIN(0xff, 169),
 	MX31_PIN_IOIS16		= IOMUX_PIN(0xff, 170),
 	MX31_PIN_PC_RST		= IOMUX_PIN(0xff, 171),
 	MX31_PIN_PC_BVD2	= IOMUX_PIN(0xff, 172),
 	MX31_PIN_PC_BVD1	= IOMUX_PIN(0xff, 173),
 	MX31_PIN_PC_VS2		= IOMUX_PIN(0xff, 174),
 	MX31_PIN_PC_VS1		= IOMUX_PIN(0xff, 175),
 	MX31_PIN_PC_PWRON	= IOMUX_PIN(0xff, 176),
 	MX31_PIN_PC_READY	= IOMUX_PIN(0xff, 177),
 	MX31_PIN_PC_WAIT_B	= IOMUX_PIN(0xff, 178),
 	MX31_PIN_PC_CD2_B	= IOMUX_PIN(0xff, 179),
 	MX31_PIN_PC_CD1_B	= IOMUX_PIN(0xff, 180),
 	MX31_PIN_D0		= IOMUX_PIN(0xff, 181),
 	MX31_PIN_D1		= IOMUX_PIN(0xff, 182),
 	MX31_PIN_D2		= IOMUX_PIN(0xff, 183),
 	MX31_PIN_D3		= IOMUX_PIN(0xff, 184),
 	MX31_PIN_D4		= IOMUX_PIN(0xff, 185),
 	MX31_PIN_D5		= IOMUX_PIN(0xff, 186),
 	MX31_PIN_D6		= IOMUX_PIN(0xff, 187),
 	MX31_PIN_D7		= IOMUX_PIN(0xff, 188),
 	MX31_PIN_D8		= IOMUX_PIN(0xff, 189),
 	MX31_PIN_D9		= IOMUX_PIN(0xff, 190),
 	MX31_PIN_D10		= IOMUX_PIN(0xff, 191),
 	MX31_PIN_D11		= IOMUX_PIN(0xff, 192),
 	MX31_PIN_D12		= IOMUX_PIN(0xff, 193),
 	MX31_PIN_D13		= IOMUX_PIN(0xff, 194),
 	MX31_PIN_D14		= IOMUX_PIN(0xff, 195),
 	MX31_PIN_D15		= IOMUX_PIN(0xff, 196),
 	MX31_PIN_NFRB		= IOMUX_PIN(16,   197),
 	MX31_PIN_NFCE_B		= IOMUX_PIN(15,   198),
 	MX31_PIN_NFWP_B		= IOMUX_PIN(14,   199),
 	MX31_PIN_NFCLE		= IOMUX_PIN(13,   200),
 	MX31_PIN_NFALE		= IOMUX_PIN(12,   201),
 	MX31_PIN_NFRE_B		= IOMUX_PIN(11,   202),
 	MX31_PIN_NFWE_B		= IOMUX_PIN(10,   203),
 	MX31_PIN_SDQS3		= IOMUX_PIN(0xff, 204),
 	MX31_PIN_SDQS2		= IOMUX_PIN(0xff, 205),
 	MX31_PIN_SDQS1		= IOMUX_PIN(0xff, 206),
 	MX31_PIN_SDQS0		= IOMUX_PIN(0xff, 207),
 	MX31_PIN_SDCLK_B	= IOMUX_PIN(0xff, 208),
 	MX31_PIN_SDCLK		= IOMUX_PIN(0xff, 209),
 	MX31_PIN_SDCKE1		= IOMUX_PIN(0xff, 210),
 	MX31_PIN_SDCKE0		= IOMUX_PIN(0xff, 211),
 	MX31_PIN_SDWE		= IOMUX_PIN(0xff, 212),
 	MX31_PIN_CAS		= IOMUX_PIN(0xff, 213),
 	MX31_PIN_RAS		= IOMUX_PIN(0xff, 214),
 	MX31_PIN_RW		= IOMUX_PIN(0xff, 215),
 	MX31_PIN_BCLK		= IOMUX_PIN(0xff, 216),
 	MX31_PIN_LBA		= IOMUX_PIN(0xff, 217),
 	MX31_PIN_ECB		= IOMUX_PIN(0xff, 218),
 	MX31_PIN_CS5		= IOMUX_PIN(0xff, 219),
 	MX31_PIN_CS4		= IOMUX_PIN(0xff, 220),
 	MX31_PIN_CS3		= IOMUX_PIN(0xff, 221),
 	MX31_PIN_CS2		= IOMUX_PIN(0xff, 222),
 	MX31_PIN_CS1		= IOMUX_PIN(0xff, 223),
 	MX31_PIN_CS0		= IOMUX_PIN(0xff, 224),
 	MX31_PIN_OE		= IOMUX_PIN(0xff, 225),
 	MX31_PIN_EB1		= IOMUX_PIN(0xff, 226),
 	MX31_PIN_EB0		= IOMUX_PIN(0xff, 227),
 	MX31_PIN_DQM3		= IOMUX_PIN(0xff, 228),
 	MX31_PIN_DQM2		= IOMUX_PIN(0xff, 229),
 	MX31_PIN_DQM1		= IOMUX_PIN(0xff, 230),
 	MX31_PIN_DQM0		= IOMUX_PIN(0xff, 231),
 	MX31_PIN_SD31		= IOMUX_PIN(0xff, 232),
 	MX31_PIN_SD30		= IOMUX_PIN(0xff, 233),
 	MX31_PIN_SD29		= IOMUX_PIN(0xff, 234),
 	MX31_PIN_SD28		= IOMUX_PIN(0xff, 235),
 	MX31_PIN_SD27		= IOMUX_PIN(0xff, 236),
 	MX31_PIN_SD26		= IOMUX_PIN(0xff, 237),
 	MX31_PIN_SD25		= IOMUX_PIN(0xff, 238),
 	MX31_PIN_SD24		= IOMUX_PIN(0xff, 239),
 	MX31_PIN_SD23		= IOMUX_PIN(0xff, 240),
 	MX31_PIN_SD22		= IOMUX_PIN(0xff, 241),
 	MX31_PIN_SD21		= IOMUX_PIN(0xff, 242),
 	MX31_PIN_SD20		= IOMUX_PIN(0xff, 243),
 	MX31_PIN_SD19		= IOMUX_PIN(0xff, 244),
 	MX31_PIN_SD18		= IOMUX_PIN(0xff, 245),
 	MX31_PIN_SD17		= IOMUX_PIN(0xff, 246),
 	MX31_PIN_SD16		= IOMUX_PIN(0xff, 247),
 	MX31_PIN_SD15		= IOMUX_PIN(0xff, 248),
 	MX31_PIN_SD14		= IOMUX_PIN(0xff, 249),
 	MX31_PIN_SD13		= IOMUX_PIN(0xff, 250),
 	MX31_PIN_SD12		= IOMUX_PIN(0xff, 251),
 	MX31_PIN_SD11		= IOMUX_PIN(0xff, 252),
 	MX31_PIN_SD10		= IOMUX_PIN(0xff, 253),
 	MX31_PIN_SD9		= IOMUX_PIN(0xff, 254),
 	MX31_PIN_SD8		= IOMUX_PIN(0xff, 255),
 	MX31_PIN_SD7		= IOMUX_PIN(0xff, 256),
 	MX31_PIN_SD6		= IOMUX_PIN(0xff, 257),
 	MX31_PIN_SD5		= IOMUX_PIN(0xff, 258),
 	MX31_PIN_SD4		= IOMUX_PIN(0xff, 259),
 	MX31_PIN_SD3		= IOMUX_PIN(0xff, 260),
 	MX31_PIN_SD2		= IOMUX_PIN(0xff, 261),
 	MX31_PIN_SD1		= IOMUX_PIN(0xff, 262),
 	MX31_PIN_SD0		= IOMUX_PIN(0xff, 263),
 	MX31_PIN_SDBA0		= IOMUX_PIN(0xff, 264),
 	MX31_PIN_SDBA1		= IOMUX_PIN(0xff, 265),
 	MX31_PIN_A25		= IOMUX_PIN(0xff, 266),
 	MX31_PIN_A24		= IOMUX_PIN(0xff, 267),
 	MX31_PIN_A23		= IOMUX_PIN(0xff, 268),
 	MX31_PIN_A22		= IOMUX_PIN(0xff, 269),
 	MX31_PIN_A21		= IOMUX_PIN(0xff, 270),
 	MX31_PIN_A20		= IOMUX_PIN(0xff, 271),
 	MX31_PIN_A19		= IOMUX_PIN(0xff, 272),
 	MX31_PIN_A18		= IOMUX_PIN(0xff, 273),
 	MX31_PIN_A17		= IOMUX_PIN(0xff, 274),
 	MX31_PIN_A16		= IOMUX_PIN(0xff, 275),
 	MX31_PIN_A14		= IOMUX_PIN(0xff, 276),
 	MX31_PIN_A15		= IOMUX_PIN(0xff, 277),
 	MX31_PIN_A13		= IOMUX_PIN(0xff, 278),
 	MX31_PIN_A12		= IOMUX_PIN(0xff, 279),
 	MX31_PIN_A11		= IOMUX_PIN(0xff, 280),
 	MX31_PIN_MA10		= IOMUX_PIN(0xff, 281),
 	MX31_PIN_A10		= IOMUX_PIN(0xff, 282),
 	MX31_PIN_A9		= IOMUX_PIN(0xff, 283),
 	MX31_PIN_A8		= IOMUX_PIN(0xff, 284),
 	MX31_PIN_A7		= IOMUX_PIN(0xff, 285),
 	MX31_PIN_A6		= IOMUX_PIN(0xff, 286),
 	MX31_PIN_A5		= IOMUX_PIN(0xff, 287),
 	MX31_PIN_A4		= IOMUX_PIN(0xff, 288),
 	MX31_PIN_A3		= IOMUX_PIN(0xff, 289),
 	MX31_PIN_A2		= IOMUX_PIN(0xff, 290),
 	MX31_PIN_A1		= IOMUX_PIN(0xff, 291),
 	MX31_PIN_A0		= IOMUX_PIN(0xff, 292),
 	MX31_PIN_VPG1		= IOMUX_PIN(0xff, 293),
 	MX31_PIN_VPG0		= IOMUX_PIN(0xff, 294),
 	MX31_PIN_DVFS1		= IOMUX_PIN(0xff, 295),
 	MX31_PIN_DVFS0		= IOMUX_PIN(0xff, 296),
 	MX31_PIN_VSTBY		= IOMUX_PIN(0xff, 297),
 	MX31_PIN_POWER_FAIL	= IOMUX_PIN(0xff, 298),
 	MX31_PIN_CKIL		= IOMUX_PIN(0xff, 299),
 	MX31_PIN_BOOT_MODE4	= IOMUX_PIN(0xff, 300),
 	MX31_PIN_BOOT_MODE3	= IOMUX_PIN(0xff, 301),
 	MX31_PIN_BOOT_MODE2	= IOMUX_PIN(0xff, 302),
 	MX31_PIN_BOOT_MODE1	= IOMUX_PIN(0xff, 303),
 	MX31_PIN_BOOT_MODE0	= IOMUX_PIN(0xff, 304),
 	MX31_PIN_CLKO		= IOMUX_PIN(0xff, 305),
 	MX31_PIN_POR_B		= IOMUX_PIN(0xff, 306),
 	MX31_PIN_RESET_IN_B	= IOMUX_PIN(0xff, 307),
 	MX31_PIN_CKIH		= IOMUX_PIN(0xff, 308),
 	MX31_PIN_SIMPD0		= IOMUX_PIN(35,   309),
 	MX31_PIN_SRX0		= IOMUX_PIN(34,   310),
 	MX31_PIN_STX0		= IOMUX_PIN(33,   311),
 	MX31_PIN_SVEN0		= IOMUX_PIN(32,   312),
 	MX31_PIN_SRST0		= IOMUX_PIN(67,   313),
 	MX31_PIN_SCLK0		= IOMUX_PIN(66,   314),
 	MX31_PIN_GPIO3_1	= IOMUX_PIN(65,   315),
 	MX31_PIN_GPIO3_0	= IOMUX_PIN(64,   316),
 	MX31_PIN_GPIO1_6	= IOMUX_PIN(6,    317),
 	MX31_PIN_GPIO1_5	= IOMUX_PIN(5,    318),
 	MX31_PIN_GPIO1_4	= IOMUX_PIN(4,    319),
 	MX31_PIN_GPIO1_3	= IOMUX_PIN(3,    320),
 	MX31_PIN_GPIO1_2	= IOMUX_PIN(2,    321),
 	MX31_PIN_GPIO1_1	= IOMUX_PIN(1,    322),
 	MX31_PIN_GPIO1_0	= IOMUX_PIN(0,    323),
 	MX31_PIN_PWMO		= IOMUX_PIN(9,    324),
 	MX31_PIN_WATCHDOG_RST	= IOMUX_PIN(0xff, 325),
 	MX31_PIN_COMPARE	= IOMUX_PIN(8,    326),
 	MX31_PIN_CAPTURE	= IOMUX_PIN(7,    327),
 };
 /*
  * various IOMUX general purpose functions
  */
 enum iomux_gp_func {
 	MUX_PGP_FIRI			= 1 << 0,
 	MUX_DDR_MODE			= 1 << 1,
 	MUX_PGP_CSPI_BB			= 1 << 2,
 	MUX_PGP_ATA_1			= 1 << 3,
 	MUX_PGP_ATA_2			= 1 << 4,
 	MUX_PGP_ATA_3			= 1 << 5,
 	MUX_PGP_ATA_4			= 1 << 6,
 	MUX_PGP_ATA_5			= 1 << 7,
 	MUX_PGP_ATA_6			= 1 << 8,
 	MUX_PGP_ATA_7			= 1 << 9,
 	MUX_PGP_ATA_8			= 1 << 10,
 	MUX_PGP_UH2			= 1 << 11,
 	MUX_SDCTL_CSD0_SEL		= 1 << 12,
 	MUX_SDCTL_CSD1_SEL		= 1 << 13,
 	MUX_CSPI1_UART3			= 1 << 14,
 	MUX_EXTDMAREQ2_MBX_SEL		= 1 << 15,
 	MUX_TAMPER_DETECT_EN		= 1 << 16,
 	MUX_PGP_USB_4WIRE		= 1 << 17,
 	MUX_PGP_USB_COMMON		= 1 << 18,
 	MUX_SDHC_MEMSTICK1		= 1 << 19,
 	MUX_SDHC_MEMSTICK2		= 1 << 20,
 	MUX_PGP_SPLL_BYP		= 1 << 21,
 	MUX_PGP_UPLL_BYP		= 1 << 22,
 	MUX_PGP_MSHC1_CLK_SEL		= 1 << 23,
 	MUX_PGP_MSHC2_CLK_SEL		= 1 << 24,
 	MUX_CSPI3_UART5_SEL		= 1 << 25,
 	MUX_PGP_ATA_9			= 1 << 26,
 	MUX_PGP_USB_SUSPEND		= 1 << 27,
 	MUX_PGP_USB_OTG_LOOPBACK	= 1 << 28,
 	MUX_PGP_USB_HS1_LOOPBACK	= 1 << 29,
 	MUX_PGP_USB_HS2_LOOPBACK	= 1 << 30,
 	MUX_CLKO_DDR_MODE		= 1 << 31,
 };
 /* Bit definitions for RCSR register in CCM */
 #define CCM_RCSR_NF16B	(1 << 31)
 #define CCM_RCSR_NFMS	(1 << 30)
 /* WEIM CS control registers */
 struct mx31_weim_cscr {
 	u32 upper;
 	u32 lower;
 	u32 additional;
 	u32 reserved;
 };
 struct mx31_weim {
 	struct mx31_weim_cscr cscr[6];
 };
 /* ESD control registers */
 struct esdc_regs {
 	u32 ctl0;
 	u32 cfg0;
 	u32 ctl1;
 	u32 cfg1;
 	u32 misc;
 	u32 dly[5];
 	u32 dlyl;
 };
 #endif
 #define __REG(x)     (*((volatile u32 *)(x)))
 #define __REG16(x)   (*((volatile u16 *)(x)))
 #define __REG8(x)    (*((volatile u8 *)(x)))
 #define CCM_BASE	0x53f80000
 #define CCM_CCMR	(CCM_BASE + 0x00)
 #define CCM_PDR0	(CCM_BASE + 0x04)
 #define CCM_PDR1	(CCM_BASE + 0x08)
 #define CCM_RCSR	(CCM_BASE + 0x0c)
 #define CCM_MPCTL	(CCM_BASE + 0x10)
 #define CCM_UPCTL	(CCM_BASE + 0x14)
 #define CCM_SPCTL	(CCM_BASE + 0x18)
 #define CCM_COSR	(CCM_BASE + 0x1C)
 #define CCM_CGR0	(CCM_BASE + 0x20)
 #define CCM_CGR1	(CCM_BASE + 0x24)
 #define CCM_CGR2	(CCM_BASE + 0x28)
 #define CCMR_MDS	(1 << 7)
 #define CCMR_SBYCS	(1 << 4)
 #define CCMR_MPE	(1 << 3)
 #define CCMR_PRCS_MASK	(3 << 1)
 #define CCMR_FPM	(1 << 1)
 #define CCMR_CKIH	(2 << 1)
 #define MX31_IIM_BASE_ADDR	0x5001C000
 #define PDR0_CSI_PODF(x)	(((x) & 0x1ff) << 23)
 #define PDR0_PER_PODF(x)	(((x) & 0x1f) << 16)
 #define PDR0_HSP_PODF(x)	(((x) & 0x7) << 11)
 #define PDR0_NFC_PODF(x)	(((x) & 0x7) << 8)
 #define PDR0_IPG_PODF(x)	(((x) & 0x3) << 6)
 #define PDR0_MAX_PODF(x)	(((x) & 0x7) << 3)
 #define PDR0_MCU_PODF(x)	((x) & 0x7)
 #define PLL_PD(x)		(((x) & 0xf) << 26)
 #define PLL_MFD(x)		(((x) & 0x3ff) << 16)
 #define PLL_MFI(x)		(((x) & 0xf) << 10)
 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
 #define GET_PDR0_CSI_PODF(x)	(((x) >> 23) & 0x1ff)
 #define GET_PDR0_PER_PODF(x)	(((x) >> 16) & 0x1f)
 #define GET_PDR0_HSP_PODF(x)	(((x) >> 11) & 0x7)
 #define GET_PDR0_NFC_PODF(x)	(((x) >> 8) & 0x7)
 #define GET_PDR0_IPG_PODF(x)	(((x) >> 6) & 0x3)
 #define GET_PDR0_MAX_PODF(x)	(((x) >> 3) & 0x7)
 #define GET_PDR0_MCU_PODF(x)	((x) & 0x7)
 #define GET_PLL_PD(x)		(((x) >> 26) & 0xf)
 #define GET_PLL_MFD(x)		(((x) >> 16) & 0x3ff)
 #define GET_PLL_MFI(x)		(((x) >> 10) & 0xf)
 #define GET_PLL_MFN(x)		(((x) >> 0) & 0x3ff)
 #define WEIM_ESDCTL0	0xB8001000
 #define WEIM_ESDCFG0	0xB8001004
 #define WEIM_ESDCTL1	0xB8001008
 #define WEIM_ESDCFG1	0xB800100C
 #define WEIM_ESDMISC	0xB8001010
 #define UART1_BASE	0x43F90000
 #define UART2_BASE	0x43F94000
 #define UART3_BASE	0x5000C000
 #define UART4_BASE	0x43FB0000
 #define UART5_BASE	0x43FB4000
+#define I2C1_BASE_ADDR          0x43f80000
+#define I2C1_CLK_OFFSET		26
+#define I2C2_BASE_ADDR          0x43F98000
+#define I2C2_CLK_OFFSET		28
+#define I2C3_BASE_ADDR          0x43f84000
+#define I2C3_CLK_OFFSET		30
 #define ESDCTL_SDE			(1 << 31)
 #define ESDCTL_CMD_RW			(0 << 28)
 #define ESDCTL_CMD_PRECHARGE		(1 << 28)
 #define ESDCTL_CMD_AUTOREFRESH		(2 << 28)
 #define ESDCTL_CMD_LOADMODEREG		(3 << 28)
 #define ESDCTL_CMD_MANUALREFRESH	(4 << 28)
 #define ESDCTL_ROW_13			(2 << 24)
 #define ESDCTL_ROW(x)			((x) << 24)
 #define ESDCTL_COL_9			(1 << 20)
 #define ESDCTL_COL(x)			((x) << 20)
 #define ESDCTL_DSIZ(x)			((x) << 16)
 #define ESDCTL_SREFR(x)			((x) << 13)
 #define ESDCTL_PWDT(x)			((x) << 10)
 #define ESDCTL_FP(x)			((x) << 8)
 #define ESDCTL_BL(x)			((x) << 7)
 #define ESDCTL_PRCT(x)			((x) << 0)
 #define ESDCTL_BASE_ADDR	0xB8001000
 /* 13 fields of the upper CS control register */
 #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
 		cnc, wsc, ew, wws, edc) \
 	((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
 	 (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
 	 (wws) << 4 | (edc) << 0)
 /* 12 fields of the lower CS control register */
 #define CSCR_L(oea, oen, ebwa, ebwn, \
 		csa, ebc, dsz, csn, psr, cre, wrap, csen) \
 	((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
 	 (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
 	 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
 /* 14 fields of the additional CS control register */
 #define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
 		wwu, age, cnc2, fce) \
 	((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
 	 (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
 	 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
 	 (age) << 2 | (cnc2) << 1 | (fce) << 0)
 #define WEIM_BASE	0xb8002000
 #define IOMUXC_BASE	0x43FAC000
 #define IOMUXC_SW_MUX_CTL(x)	(IOMUXC_BASE + 0xc + (x) * 4)
 #define IOMUXC_SW_PAD_CTL(x)	(IOMUXC_BASE + 0x154 + (x) * 4)
 #define IPU_BASE		0x53fc0000
 #define IPU_CONF		IPU_BASE
 #define IPU_CONF_PXL_ENDIAN	(1<<8)
 #define IPU_CONF_DU_EN		(1<<7)
 #define IPU_CONF_DI_EN		(1<<6)
 #define IPU_CONF_ADC_EN		(1<<5)
 #define IPU_CONF_SDC_EN		(1<<4)
 #define IPU_CONF_PF_EN		(1<<3)
 #define IPU_CONF_ROT_EN		(1<<2)
 #define IPU_CONF_IC_EN		(1<<1)
 #define IPU_CONF_SCI_EN		(1<<0)
 #define ARM_PPMRR		0x40000015
 #define WDOG_BASE		0x53FDC000
 /*
  * GPIO
  */
 #define GPIO1_BASE_ADDR	0x53FCC000
 #define GPIO2_BASE_ADDR	0x53FD0000
 #define GPIO3_BASE_ADDR	0x53FA4000
 #define GPIO_DR		0x00000000	/* data register */
 #define GPIO_GDIR	0x00000004	/* direction register */
 #define GPIO_PSR	0x00000008	/* pad status register */
 /*
  * Signal Multiplexing (IOMUX)
  */
 /* bits in the SW_MUX_CTL registers */
 #define MUX_CTL_OUT_GPIO_DR	(0 << 4)
 #define MUX_CTL_OUT_FUNC	(1 << 4)
 #define MUX_CTL_OUT_ALT1	(2 << 4)
 #define MUX_CTL_OUT_ALT2	(3 << 4)
 #define MUX_CTL_OUT_ALT3	(4 << 4)
 #define MUX_CTL_OUT_ALT4	(5 << 4)
 #define MUX_CTL_OUT_ALT5	(6 << 4)
 #define MUX_CTL_OUT_ALT6	(7 << 4)
 #define MUX_CTL_IN_NONE		(0 << 0)
 #define MUX_CTL_IN_GPIO		(1 << 0)
 #define MUX_CTL_IN_FUNC		(2 << 0)
 #define MUX_CTL_IN_ALT1		(4 << 0)
 #define MUX_CTL_IN_ALT2		(8 << 0)
 #define MUX_CTL_FUNC		(MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
 #define MUX_CTL_ALT1		(MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
 #define MUX_CTL_ALT2		(MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
 #define MUX_CTL_GPIO		(MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
 /* Register offsets based on IOMUXC_BASE */
 /* 0x00 .. 0x7b */
 #define MUX_CTL_CSPI3_MISO		0x0c
 #define MUX_CTL_CSPI3_SCLK		0x0d
 #define MUX_CTL_CSPI3_SPI_RDY	0x0e
 #define MUX_CTL_CSPI3_MOSI		0x13
 #define MUX_CTL_SD1_DATA1	0x18
 #define MUX_CTL_SD1_DATA2	0x19
 #define MUX_CTL_SD1_DATA3	0x1a
 #define MUX_CTL_SD1_CMD		0x1d
 #define MUX_CTL_SD1_CLK		0x1e
 #define MUX_CTL_SD1_DATA0	0x1f
 #define MUX_CTL_USBH2_DATA1	0x40
 #define MUX_CTL_USBH2_DIR	0x44
 #define MUX_CTL_USBH2_STP	0x45
 #define MUX_CTL_USBH2_NXT	0x46
 #define MUX_CTL_USBH2_DATA0	0x47
 #define MUX_CTL_USBH2_CLK	0x4B
 #define MUX_CTL_TXD2		0x70
 #define MUX_CTL_RTS2		0x71
 #define MUX_CTL_CTS2		0x72
 #define MUX_CTL_RXD2		0x77
 #define MUX_CTL_RTS1		0x7c
 #define MUX_CTL_CTS1		0x7d
 #define MUX_CTL_DTR_DCE1	0x7e
 #define MUX_CTL_DSR_DCE1	0x7f
 #define MUX_CTL_CSPI2_SCLK	0x80
 #define MUX_CTL_CSPI2_SPI_RDY	0x81
 #define MUX_CTL_RXD1		0x82
 #define MUX_CTL_TXD1		0x83
 #define MUX_CTL_CSPI2_MISO	0x84
 #define MUX_CTL_CSPI2_SS0	0x85
 #define MUX_CTL_CSPI2_SS1	0x86
 #define MUX_CTL_CSPI2_SS2	0x87
 #define MUX_CTL_CSPI1_SS2	0x88
 #define MUX_CTL_CSPI1_SCLK	0x89
 #define MUX_CTL_CSPI1_SPI_RDY	0x8a
 #define MUX_CTL_CSPI2_MOSI	0x8b
 #define MUX_CTL_CSPI1_MOSI	0x8c
 #define MUX_CTL_CSPI1_MISO	0x8d
 #define MUX_CTL_CSPI1_SS0	0x8e
 #define MUX_CTL_CSPI1_SS1	0x8f
 #define MUX_CTL_STXD6		0x90
 #define MUX_CTL_SRXD6		0x91
 #define MUX_CTL_SCK6		0x92
 #define MUX_CTL_SFS6		0x93
 #define MUX_CTL_STXD3		0x9C
 #define MUX_CTL_SRXD3		0x9D
 #define MUX_CTL_SCK3		0x9E
 #define MUX_CTL_SFS3		0x9F
 #define MUX_CTL_NFC_WP		0xD0
 #define MUX_CTL_NFC_CE		0xD1
 #define MUX_CTL_NFC_RB		0xD2
 #define MUX_CTL_NFC_WE		0xD4
 #define MUX_CTL_NFC_RE		0xD5
 #define MUX_CTL_NFC_ALE		0xD6
 #define MUX_CTL_NFC_CLE		0xD7
 #define MUX_CTL_CAPTURE		0x150
 #define MUX_CTL_COMPARE		0x151
 /*
  * Helper macros for the MUX_[contact name]__[pin function] macros
  */
 #define IOMUX_MODE_POS 9
 #define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
 /*
  * These macros can be used in mx31_gpio_mux() and have the form
  * MUX_[contact name]__[pin function]
  */
 #define MUX_RXD1__UART1_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
 #define MUX_TXD1__UART1_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
 #define MUX_RTS1__UART1_RTS_B	IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
 #define MUX_CTS1__UART1_CTS_B	IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
 #define MUX_RXD2__UART2_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
 #define MUX_TXD2__UART2_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
 #define MUX_RTS2__UART2_RTS_B	IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
 #define MUX_CTS2__UART2_CTS_B	IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
 #define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
 #define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
 #define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
 	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
 #define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
 #define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
 #define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
 #define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
 #define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
 #define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
 	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
 #define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 /* PAD control registers for SDR/DDR */
 #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B	(IOMUXC_BASE + 0x26C)
 #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0	(IOMUXC_BASE + 0x270)
 #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS		(IOMUXC_BASE + 0x274)
 #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA		(IOMUXC_BASE + 0x278)
 #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4		(IOMUXC_BASE + 0x27C)
 #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1		(IOMUXC_BASE + 0x280)
 #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1		(IOMUXC_BASE + 0x284)
 #define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2	(IOMUXC_BASE + 0x288)
 #define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31	(IOMUXC_BASE + 0x28C)
 #define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28	(IOMUXC_BASE + 0x290)
 #define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25	(IOMUXC_BASE + 0x294)
 #define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22	(IOMUXC_BASE + 0x298)
 #define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19	(IOMUXC_BASE + 0x29C)
 #define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16	(IOMUXC_BASE + 0x2A0)
 #define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13	(IOMUXC_BASE + 0x2A4)
 #define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10		(IOMUXC_BASE + 0x2A8)
 #define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7		(IOMUXC_BASE + 0x2AC)
 #define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4		(IOMUXC_BASE + 0x2B0)
 #define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1		(IOMUXC_BASE + 0x2B4)
 #define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1		(IOMUXC_BASE + 0x2B8)
 #define IOMUXC_SW_PAD_CTL_A21_A22_A23		(IOMUXC_BASE + 0x2BC)
 #define IOMUXC_SW_PAD_CTL_A18_A19_A20		(IOMUXC_BASE + 0x2C0)
 #define IOMUXC_SW_PAD_CTL_A15_A16_A17		(IOMUXC_BASE + 0x2C4)
 #define IOMUXC_SW_PAD_CTL_A12_A13_A14		(IOMUXC_BASE + 0x2C8)
 #define IOMUXC_SW_PAD_CTL_A10_MA10_A11		(IOMUXC_BASE + 0x2CC)
 #define IOMUXC_SW_PAD_CTL_A7_A8_A9		(IOMUXC_BASE + 0x2D0)
 #define IOMUXC_SW_PAD_CTL_A4_A5_A6		(IOMUXC_BASE + 0x2D4)
 #define IOMUXC_SW_PAD_CTL_A1_A2_A3		(IOMUXC_BASE + 0x2D8)
 #define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0		(IOMUXC_BASE + 0x2DC)
 /*
  * Memory regions and CS
  */
 #define IPU_MEM_BASE	0x70000000
 #define CSD0_BASE	0x80000000
 #define CSD1_BASE	0x90000000
 #define CS0_BASE	0xA0000000
 #define CS1_BASE	0xA8000000
 #define CS2_BASE	0xB0000000
 #define CS3_BASE	0xB2000000
 #define CS4_BASE	0xB4000000
 #define CS4_PSRAM_BASE	0xB5000000
 #define CS5_BASE	0xB6000000
 #define PCMCIA_MEM_BASE	0xC0000000
 /*
  * NAND controller
  */
 #define NFC_BASE_ADDR	0xB8000000
 /* SD card controller */
 #define SDHC1_BASE_ADDR	0x50004000
 #define SDHC2_BASE_ADDR	0x50008000
 /*
  * Internal RAM (16KB)
  */
 #define	IRAM_BASE_ADDR	0x1FFFC000
 #define IRAM_SIZE	(16 * 1024)
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
 /* USB portsc */
 /* values for portsc field */
 #define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
 #define MXC_EHCI_FORCE_FS		(1 << 24)
 #define MXC_EHCI_UTMI_8BIT		(0 << 28)
 #define MXC_EHCI_UTMI_16BIT		(1 << 28)
 #define MXC_EHCI_SERIAL			(1 << 29)
 #define MXC_EHCI_MODE_UTMI		(0 << 30)
 #define MXC_EHCI_MODE_PHILIPS		(1 << 30)
 #define MXC_EHCI_MODE_ULPI		(2 << 30)
 #define MXC_EHCI_MODE_SERIAL		(3 << 30)
 /* values for flags field */
 #define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
 #define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
 #define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
 #define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
 #define MXC_EHCI_INTERFACE_MASK		(0xf)
 #define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
 #define MXC_EHCI_TTL_ENABLED		(1 << 6)
 #define MXC_EHCI_INTERNAL_PHY		(1 << 7)
 #define MXC_EHCI_IPPUE_DOWN		(1 << 8)
 #define MXC_EHCI_IPPUE_UP		(1 << 9)
 /*
  * CSPI register definitions
  */
 #define MXC_CSPI
 #define MXC_CSPICTRL_EN		(1 << 0)
 #define MXC_CSPICTRL_MODE	(1 << 1)
 #define MXC_CSPICTRL_XCH	(1 << 2)
 #define MXC_CSPICTRL_SMC	(1 << 3)
 #define MXC_CSPICTRL_POL	(1 << 4)
 #define MXC_CSPICTRL_PHA	(1 << 5)
 #define MXC_CSPICTRL_SSCTL	(1 << 6)
 #define MXC_CSPICTRL_SSPOL	(1 << 7)
 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
 #define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
 #define MXC_CSPICTRL_TC		(1 << 8)
 #define MXC_CSPICTRL_RXOVF	(1 << 6)
 #define MXC_CSPICTRL_MAXBITS	0x1f
 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
 #define MAX_SPI_BYTES	4
 #define MXC_SPI_BASE_ADDRESSES \
 	0x43fa4000, \
 	0x50010000, \
 	0x53f84000,
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */

arch/arm/include/asm/arch-mx35/imx-regs.h

Diff comments View file @ de6f604

1	/*	1	/*
2	* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>	2	* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3	*	3	*
4	* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.	4	* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
5	*	5	*
6	* See file CREDITS for list of people who contributed to this	6	* See file CREDITS for list of people who contributed to this
7	* project.	7	* project.
8	*	8	*
9	* This program is free software; you can redistribute it and/or	9	* This program is free software; you can redistribute it and/or
10	* modify it under the terms of the GNU General Public License as	10	* modify it under the terms of the GNU General Public License as
11	* published by the Free Software Foundation; either version 2 of	11	* published by the Free Software Foundation; either version 2 of
12	* the License, or (at your option) any later version.	12	* the License, or (at your option) any later version.
13	*	13	*
14	* This program is distributed in the hope that it will be useful,	14	* This program is distributed in the hope that it will be useful,
15	* but WITHOUT ANY WARRANTY; without even the implied warranty of	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17	* GNU General Public License for more details.	17	* GNU General Public License for more details.
18	*	18	*
19	* You should have received a copy of the GNU General Public License	19	* You should have received a copy of the GNU General Public License
20	* along with this program; if not, write to the Free Software	20	* along with this program; if not, write to the Free Software
21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22	* MA 02111-1307 USA	22	* MA 02111-1307 USA
23	*/	23	*/
24		24
25	#ifndef __ASM_ARCH_MX35_H	25	#ifndef __ASM_ARCH_MX35_H
26	#define __ASM_ARCH_MX35_H	26	#define __ASM_ARCH_MX35_H
27		27
28	/*	28	/*
29	* IRAM	29	* IRAM
30	*/	30	*/
31	#define IRAM_BASE_ADDR 0x10000000 /* internal ram */	31	#define IRAM_BASE_ADDR 0x10000000 /* internal ram */
32	#define IRAM_SIZE 0x00020000 /* 128 KB */	32	#define IRAM_SIZE 0x00020000 /* 128 KB */
33		33
34	/*	34	/*
35	* AIPS 1	35	* AIPS 1
36	*/	36	*/
37	#define AIPS1_BASE_ADDR 0x43F00000	37	#define AIPS1_BASE_ADDR 0x43F00000
38	#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR	38	#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
39	#define MAX_BASE_ADDR 0x43F04000	39	#define MAX_BASE_ADDR 0x43F04000
40	#define EVTMON_BASE_ADDR 0x43F08000	40	#define EVTMON_BASE_ADDR 0x43F08000
41	#define CLKCTL_BASE_ADDR 0x43F0C000	41	#define CLKCTL_BASE_ADDR 0x43F0C000
42	#define I2C_BASE_ADDR 0x43F80000	42	#define I2C1_BASE_ADDR 0x43F80000
43	#define I2C3_BASE_ADDR 0x43F84000	43	#define I2C3_BASE_ADDR 0x43F84000
44	#define ATA_BASE_ADDR 0x43F8C000	44	#define ATA_BASE_ADDR 0x43F8C000
45	#define UART1_BASE 0x43F90000	45	#define UART1_BASE 0x43F90000
46	#define UART2_BASE 0x43F94000	46	#define UART2_BASE 0x43F94000
47	#define I2C2_BASE_ADDR 0x43F98000	47	#define I2C2_BASE_ADDR 0x43F98000
48	#define CSPI1_BASE_ADDR 0x43FA4000	48	#define CSPI1_BASE_ADDR 0x43FA4000
49	#define IOMUXC_BASE_ADDR 0x43FAC000	49	#define IOMUXC_BASE_ADDR 0x43FAC000
50		50
51	/*	51	/*
52	* SPBA	52	* SPBA
53	*/	53	*/
54	#define SPBA_BASE_ADDR 0x50000000	54	#define SPBA_BASE_ADDR 0x50000000
55	#define UART3_BASE 0x5000C000	55	#define UART3_BASE 0x5000C000
56	#define CSPI2_BASE_ADDR 0x50010000	56	#define CSPI2_BASE_ADDR 0x50010000
57	#define ATA_DMA_BASE_ADDR 0x50020000	57	#define ATA_DMA_BASE_ADDR 0x50020000
58	#define FEC_BASE_ADDR 0x50038000	58	#define FEC_BASE_ADDR 0x50038000
59	#define SPBA_CTRL_BASE_ADDR 0x5003C000	59	#define SPBA_CTRL_BASE_ADDR 0x5003C000
60		60
61	/*	61	/*
62	* AIPS 2	62	* AIPS 2
63	*/	63	*/
64	#define AIPS2_BASE_ADDR 0x53F00000	64	#define AIPS2_BASE_ADDR 0x53F00000
65	#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR	65	#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
66	#define CCM_BASE_ADDR 0x53F80000	66	#define CCM_BASE_ADDR 0x53F80000
67	#define GPT1_BASE_ADDR 0x53F90000	67	#define GPT1_BASE_ADDR 0x53F90000
68	#define EPIT1_BASE_ADDR 0x53F94000	68	#define EPIT1_BASE_ADDR 0x53F94000
69	#define EPIT2_BASE_ADDR 0x53F98000	69	#define EPIT2_BASE_ADDR 0x53F98000
70	#define GPIO3_BASE_ADDR 0x53FA4000	70	#define GPIO3_BASE_ADDR 0x53FA4000
71	#define MMC_SDHC1_BASE_ADDR 0x53FB4000	71	#define MMC_SDHC1_BASE_ADDR 0x53FB4000
72	#define MMC_SDHC2_BASE_ADDR 0x53FB8000	72	#define MMC_SDHC2_BASE_ADDR 0x53FB8000
73	#define MMC_SDHC3_BASE_ADDR 0x53FBC000	73	#define MMC_SDHC3_BASE_ADDR 0x53FBC000
74	#define IPU_CTRL_BASE_ADDR 0x53FC0000	74	#define IPU_CTRL_BASE_ADDR 0x53FC0000
75	#define GPIO3_BASE_ADDR 0x53FA4000	75	#define GPIO3_BASE_ADDR 0x53FA4000
76	#define GPIO1_BASE_ADDR 0x53FCC000	76	#define GPIO1_BASE_ADDR 0x53FCC000
77	#define GPIO2_BASE_ADDR 0x53FD0000	77	#define GPIO2_BASE_ADDR 0x53FD0000
78	#define SDMA_BASE_ADDR 0x53FD4000	78	#define SDMA_BASE_ADDR 0x53FD4000
79	#define RTC_BASE_ADDR 0x53FD8000	79	#define RTC_BASE_ADDR 0x53FD8000
80	#define WDOG_BASE_ADDR 0x53FDC000	80	#define WDOG_BASE_ADDR 0x53FDC000
81	#define PWM_BASE_ADDR 0x53FE0000	81	#define PWM_BASE_ADDR 0x53FE0000
82	#define RTIC_BASE_ADDR 0x53FEC000	82	#define RTIC_BASE_ADDR 0x53FEC000
83	#define IIM_BASE_ADDR 0x53FF0000	83	#define IIM_BASE_ADDR 0x53FF0000
84		84
85	#define IMX_CCM_BASE CCM_BASE_ADDR	85	#define IMX_CCM_BASE CCM_BASE_ADDR
86		86
87	/*	87	/*
88	* ROMPATCH and AVIC	88	* ROMPATCH and AVIC
89	*/	89	*/
90	#define ROMPATCH_BASE_ADDR 0x60000000	90	#define ROMPATCH_BASE_ADDR 0x60000000
91	#define AVIC_BASE_ADDR 0x68000000	91	#define AVIC_BASE_ADDR 0x68000000
92		92
93	/*	93	/*
94	* NAND, SDRAM, WEIM, M3IF, EMI controllers	94	* NAND, SDRAM, WEIM, M3IF, EMI controllers
95	*/	95	*/
96	#define EXT_MEM_CTRL_BASE 0xB8000000	96	#define EXT_MEM_CTRL_BASE 0xB8000000
97	#define ESDCTL_BASE_ADDR 0xB8001000	97	#define ESDCTL_BASE_ADDR 0xB8001000
98	#define WEIM_BASE_ADDR 0xB8002000	98	#define WEIM_BASE_ADDR 0xB8002000
99	#define WEIM_CTRL_CS0 WEIM_BASE_ADDR	99	#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
100	#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)	100	#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
101	#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)	101	#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
102	#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)	102	#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
103	#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)	103	#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
104	#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)	104	#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
105	#define M3IF_BASE_ADDR 0xB8003000	105	#define M3IF_BASE_ADDR 0xB8003000
106	#define EMI_BASE_ADDR 0xB8004000	106	#define EMI_BASE_ADDR 0xB8004000
107		107
108	#define NFC_BASE_ADDR 0xBB000000	108	#define NFC_BASE_ADDR 0xBB000000
109		109
110	/*	110	/*
111	* Memory regions and CS	111	* Memory regions and CS
112	*/	112	*/
113	#define IPU_MEM_BASE_ADDR 0x70000000	113	#define IPU_MEM_BASE_ADDR 0x70000000
114	#define CSD0_BASE_ADDR 0x80000000	114	#define CSD0_BASE_ADDR 0x80000000
115	#define CSD1_BASE_ADDR 0x90000000	115	#define CSD1_BASE_ADDR 0x90000000
116	#define CS0_BASE_ADDR 0xA0000000	116	#define CS0_BASE_ADDR 0xA0000000
117	#define CS1_BASE_ADDR 0xA8000000	117	#define CS1_BASE_ADDR 0xA8000000
118	#define CS2_BASE_ADDR 0xB0000000	118	#define CS2_BASE_ADDR 0xB0000000
119	#define CS3_BASE_ADDR 0xB2000000	119	#define CS3_BASE_ADDR 0xB2000000
120	#define CS4_BASE_ADDR 0xB4000000	120	#define CS4_BASE_ADDR 0xB4000000
121	#define CS5_BASE_ADDR 0xB6000000	121	#define CS5_BASE_ADDR 0xB6000000
122		122
123	/*	123	/*
124	* IRQ Controller Register Definitions.	124	* IRQ Controller Register Definitions.
125	*/	125	*/
126	#define AVIC_NIMASK 0x04	126	#define AVIC_NIMASK 0x04
127	#define AVIC_INTTYPEH 0x18	127	#define AVIC_INTTYPEH 0x18
128	#define AVIC_INTTYPEL 0x1C	128	#define AVIC_INTTYPEL 0x1C
129		129
130	/* L210 */	130	/* L210 */
131	#define L2CC_BASE_ADDR 0x30000000	131	#define L2CC_BASE_ADDR 0x30000000
132	#define L2_CACHE_LINE_SIZE 32	132	#define L2_CACHE_LINE_SIZE 32
133	#define L2_CACHE_CTL_REG 0x100	133	#define L2_CACHE_CTL_REG 0x100
134	#define L2_CACHE_AUX_CTL_REG 0x104	134	#define L2_CACHE_AUX_CTL_REG 0x104
135	#define L2_CACHE_SYNC_REG 0x730	135	#define L2_CACHE_SYNC_REG 0x730
136	#define L2_CACHE_INV_LINE_REG 0x770	136	#define L2_CACHE_INV_LINE_REG 0x770
137	#define L2_CACHE_INV_WAY_REG 0x77C	137	#define L2_CACHE_INV_WAY_REG 0x77C
138	#define L2_CACHE_CLEAN_LINE_REG 0x7B0	138	#define L2_CACHE_CLEAN_LINE_REG 0x7B0
139	#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0	139	#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
140	#define L2_CACHE_DBG_CTL_REG 0xF40	140	#define L2_CACHE_DBG_CTL_REG 0xF40
141		141
142	#define CLKMODE_AUTO 0	142	#define CLKMODE_AUTO 0
143	#define CLKMODE_CONSUMER 1	143	#define CLKMODE_CONSUMER 1
144		144
145	#define PLL_PD(x) (((x) & 0xf) << 26)	145	#define PLL_PD(x) (((x) & 0xf) << 26)
146	#define PLL_MFD(x) (((x) & 0x3ff) << 16)	146	#define PLL_MFD(x) (((x) & 0x3ff) << 16)
147	#define PLL_MFI(x) (((x) & 0xf) << 10)	147	#define PLL_MFI(x) (((x) & 0xf) << 10)
148	#define PLL_MFN(x) (((x) & 0x3ff) << 0)	148	#define PLL_MFN(x) (((x) & 0x3ff) << 0)
149		149
150	#define _PLL_BRM(x) ((x) << 31)	150	#define _PLL_BRM(x) ((x) << 31)
151	#define _PLL_PD(x) (((x) - 1) << 26)	151	#define _PLL_PD(x) (((x) - 1) << 26)
152	#define _PLL_MFD(x) (((x) - 1) << 16)	152	#define _PLL_MFD(x) (((x) - 1) << 16)
153	#define _PLL_MFI(x) ((x) << 10)	153	#define _PLL_MFI(x) ((x) << 10)
154	#define _PLL_MFN(x) (x)	154	#define _PLL_MFN(x) (x)
155	#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \	155	#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
156	(_PLL_BRM(brm) \| _PLL_PD(pd) \| _PLL_MFD(mfd) \| _PLL_MFI(mfi) \|\	156	(_PLL_BRM(brm) \| _PLL_PD(pd) \| _PLL_MFD(mfd) \| _PLL_MFI(mfi) \|\
157	_PLL_MFN(mfn))	157	_PLL_MFN(mfn))
158		158
159	#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)	159	#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
160	#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)	160	#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
161	#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)	161	#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
162		162
163	#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)	163	#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
164	#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)	164	#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
165	#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)	165	#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
166		166
167	#define IIM_SREV 0x24	167	#define IIM_SREV 0x24
168	#define ROMPATCH_REV 0x40	168	#define ROMPATCH_REV 0x40
169		169
170	#define IPU_CONF IPU_CTRL_BASE_ADDR	170	#define IPU_CONF IPU_CTRL_BASE_ADDR
171		171
172	#define IPU_CONF_PXL_ENDIAN (1<<8)	172	#define IPU_CONF_PXL_ENDIAN (1<<8)
173	#define IPU_CONF_DU_EN (1<<7)	173	#define IPU_CONF_DU_EN (1<<7)
174	#define IPU_CONF_DI_EN (1<<6)	174	#define IPU_CONF_DI_EN (1<<6)
175	#define IPU_CONF_ADC_EN (1<<5)	175	#define IPU_CONF_ADC_EN (1<<5)
176	#define IPU_CONF_SDC_EN (1<<4)	176	#define IPU_CONF_SDC_EN (1<<4)
177	#define IPU_CONF_PF_EN (1<<3)	177	#define IPU_CONF_PF_EN (1<<3)
178	#define IPU_CONF_ROT_EN (1<<2)	178	#define IPU_CONF_ROT_EN (1<<2)
179	#define IPU_CONF_IC_EN (1<<1)	179	#define IPU_CONF_IC_EN (1<<1)
180	#define IPU_CONF_SCI_EN (1<<0)	180	#define IPU_CONF_SCI_EN (1<<0)
181		181
182	/*	182	/*
183	* CSPI register definitions	183	* CSPI register definitions
184	*/	184	*/
185	#define MXC_CSPI	185	#define MXC_CSPI
186	#define MXC_CSPICTRL_EN (1 << 0)	186	#define MXC_CSPICTRL_EN (1 << 0)
187	#define MXC_CSPICTRL_MODE (1 << 1)	187	#define MXC_CSPICTRL_MODE (1 << 1)
188	#define MXC_CSPICTRL_XCH (1 << 2)	188	#define MXC_CSPICTRL_XCH (1 << 2)
189	#define MXC_CSPICTRL_SMC (1 << 3)	189	#define MXC_CSPICTRL_SMC (1 << 3)
190	#define MXC_CSPICTRL_POL (1 << 4)	190	#define MXC_CSPICTRL_POL (1 << 4)
191	#define MXC_CSPICTRL_PHA (1 << 5)	191	#define MXC_CSPICTRL_PHA (1 << 5)
192	#define MXC_CSPICTRL_SSCTL (1 << 6)	192	#define MXC_CSPICTRL_SSCTL (1 << 6)
193	#define MXC_CSPICTRL_SSPOL (1 << 7)	193	#define MXC_CSPICTRL_SSPOL (1 << 7)
194	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)	194	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
195	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)	195	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
196	#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)	196	#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
197	#define MXC_CSPICTRL_TC (1 << 7)	197	#define MXC_CSPICTRL_TC (1 << 7)
198	#define MXC_CSPICTRL_RXOVF (1 << 6)	198	#define MXC_CSPICTRL_RXOVF (1 << 6)
199	#define MXC_CSPICTRL_MAXBITS 0xfff	199	#define MXC_CSPICTRL_MAXBITS 0xfff
200	#define MXC_CSPIPERIOD_32KHZ (1 << 15)	200	#define MXC_CSPIPERIOD_32KHZ (1 << 15)
201	#define MAX_SPI_BYTES 4	201	#define MAX_SPI_BYTES 4
202		202
203	#define MXC_SPI_BASE_ADDRESSES \	203	#define MXC_SPI_BASE_ADDRESSES \
204	0x43fa4000, \	204	0x43fa4000, \
205	0x50010000,	205	0x50010000,
206		206
207	#define GPIO_PORT_NUM 3	207	#define GPIO_PORT_NUM 3
208	#define GPIO_NUM_PIN 32	208	#define GPIO_NUM_PIN 32
209		209
210	#define CHIP_REV_1_0 0x10	210	#define CHIP_REV_1_0 0x10
211	#define CHIP_REV_2_0 0x20	211	#define CHIP_REV_2_0 0x20
212		212
213	#define BOARD_REV_1_0 0x0	213	#define BOARD_REV_1_0 0x0
214	#define BOARD_REV_2_0 0x1	214	#define BOARD_REV_2_0 0x1
215		215
216	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))	216	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
217	#include <asm/types.h>	217	#include <asm/types.h>
218		218
219	enum mxc_main_clocks {	219	enum mxc_main_clocks {
220	CPU_CLK,	220	CPU_CLK,
221	AHB_CLK,	221	AHB_CLK,
222	IPG_CLK,	222	IPG_CLK,
223	IPG_PER_CLK,	223	IPG_PER_CLK,
224	NFC_CLK,	224	NFC_CLK,
225	USB_CLK,	225	USB_CLK,
226	HSP_CLK,	226	HSP_CLK,
227	};	227	};
228		228
229	enum mxc_peri_clocks {	229	enum mxc_peri_clocks {
230	UART1_BAUD,	230	UART1_BAUD,
231	UART2_BAUD,	231	UART2_BAUD,
232	UART3_BAUD,	232	UART3_BAUD,
233	SSI1_BAUD,	233	SSI1_BAUD,
234	SSI2_BAUD,	234	SSI2_BAUD,
235	CSI_BAUD,	235	CSI_BAUD,
236	MSHC_CLK,	236	MSHC_CLK,
237	ESDHC1_CLK,	237	ESDHC1_CLK,
238	ESDHC2_CLK,	238	ESDHC2_CLK,
239	ESDHC3_CLK,	239	ESDHC3_CLK,
240	SPDIF_CLK,	240	SPDIF_CLK,
241	SPI1_CLK,	241	SPI1_CLK,
242	SPI2_CLK,	242	SPI2_CLK,
243	};	243	};
244		244
245	/* Clock Control Module (CCM) registers */	245	/* Clock Control Module (CCM) registers */
246	struct ccm_regs {	246	struct ccm_regs {
247	u32 ccmr; /* Control */	247	u32 ccmr; /* Control */
248	u32 pdr0; /* Post divider 0 */	248	u32 pdr0; /* Post divider 0 */
249	u32 pdr1; /* Post divider 1 */	249	u32 pdr1; /* Post divider 1 */
250	u32 pdr2; /* Post divider 2 */	250	u32 pdr2; /* Post divider 2 */
251	u32 pdr3; /* Post divider 3 */	251	u32 pdr3; /* Post divider 3 */
252	u32 pdr4; /* Post divider 4 */	252	u32 pdr4; /* Post divider 4 */
253	u32 rcsr; /* CCM Status */	253	u32 rcsr; /* CCM Status */
254	u32 mpctl; /* Core PLL Control */	254	u32 mpctl; /* Core PLL Control */
255	u32 ppctl; /* Peripheral PLL Control */	255	u32 ppctl; /* Peripheral PLL Control */
256	u32 acmr; /* Audio clock mux */	256	u32 acmr; /* Audio clock mux */
257	u32 cosr; /* Clock out source */	257	u32 cosr; /* Clock out source */
258	u32 cgr0; /* Clock Gating Control 0 */	258	u32 cgr0; /* Clock Gating Control 0 */
259	u32 cgr1; /* Clock Gating Control 1 */	259	u32 cgr1; /* Clock Gating Control 1 */
260	u32 cgr2; /* Clock Gating Control 2 */	260	u32 cgr2; /* Clock Gating Control 2 */
261	u32 cgr3; /* Clock Gating Control 3 */	261	u32 cgr3; /* Clock Gating Control 3 */
262	u32 reserved;	262	u32 reserved;
263	u32 dcvr0; /* DPTC Comparator 0 */	263	u32 dcvr0; /* DPTC Comparator 0 */
264	u32 dcvr1; /* DPTC Comparator 0 */	264	u32 dcvr1; /* DPTC Comparator 0 */
265	u32 dcvr2; /* DPTC Comparator 0 */	265	u32 dcvr2; /* DPTC Comparator 0 */
266	u32 dcvr3; /* DPTC Comparator 0 */	266	u32 dcvr3; /* DPTC Comparator 0 */
267	u32 ltr0; /* Load Tracking 0 */	267	u32 ltr0; /* Load Tracking 0 */
268	u32 ltr1; /* Load Tracking 1 */	268	u32 ltr1; /* Load Tracking 1 */
269	u32 ltr2; /* Load Tracking 2 */	269	u32 ltr2; /* Load Tracking 2 */
270	u32 ltr3; /* Load Tracking 3 */	270	u32 ltr3; /* Load Tracking 3 */
271	u32 ltbr0; /* Load Tracking Buffer 0 */	271	u32 ltbr0; /* Load Tracking Buffer 0 */
272	};	272	};
273		273
274	/* IIM control registers */	274	/* IIM control registers */
275	struct iim_regs {	275	struct iim_regs {
276	u32 iim_stat;	276	u32 iim_stat;
277	u32 iim_statm;	277	u32 iim_statm;
278	u32 iim_err;	278	u32 iim_err;
279	u32 iim_emask;	279	u32 iim_emask;
280	u32 iim_fctl;	280	u32 iim_fctl;
281	u32 iim_ua;	281	u32 iim_ua;
282	u32 iim_la;	282	u32 iim_la;
283	u32 iim_sdat;	283	u32 iim_sdat;
284	u32 iim_prev;	284	u32 iim_prev;
285	u32 iim_srev;	285	u32 iim_srev;
286	u32 iim_prog_p;	286	u32 iim_prog_p;
287	u32 iim_scs0;	287	u32 iim_scs0;
288	u32 iim_scs1;	288	u32 iim_scs1;
289	u32 iim_scs2;	289	u32 iim_scs2;
290	u32 iim_scs3;	290	u32 iim_scs3;
291	};	291	};
292		292
293	/* General Purpose Timer (GPT) registers */	293	/* General Purpose Timer (GPT) registers */
294	struct gpt_regs {	294	struct gpt_regs {
295	u32 ctrl; /* control */	295	u32 ctrl; /* control */
296	u32 pre; /* prescaler */	296	u32 pre; /* prescaler */
297	u32 stat; /* status */	297	u32 stat; /* status */
298	u32 intr; /* interrupt */	298	u32 intr; /* interrupt */
299	u32 cmp[3]; /* output compare 1-3 */	299	u32 cmp[3]; /* output compare 1-3 */
300	u32 capt[2]; /* input capture 1-2 */	300	u32 capt[2]; /* input capture 1-2 */
301	u32 counter; /* counter */	301	u32 counter; /* counter */
302	};	302	};
303		303
304	/* CSPI registers */	304	/* CSPI registers */
305	struct cspi_regs {	305	struct cspi_regs {
306	u32 rxdata;	306	u32 rxdata;
307	u32 txdata;	307	u32 txdata;
308	u32 ctrl;	308	u32 ctrl;
309	u32 intr;	309	u32 intr;
310	u32 dma;	310	u32 dma;
311	u32 stat;	311	u32 stat;
312	u32 period;	312	u32 period;
313	u32 test;	313	u32 test;
314	};	314	};
315		315
316	/* Watchdog Timer (WDOG) registers */	316	/* Watchdog Timer (WDOG) registers */
317	struct wdog_regs {	317	struct wdog_regs {
318	u16 wcr; /* Control */	318	u16 wcr; /* Control */
319	u16 wsr; /* Service */	319	u16 wsr; /* Service */
320	u16 wrsr; /* Reset Status */	320	u16 wrsr; /* Reset Status */
321	u16 wicr; /* Interrupt Control */	321	u16 wicr; /* Interrupt Control */
322	u16 wmcr; /* Misc Control */	322	u16 wmcr; /* Misc Control */
323	};	323	};
324		324
325	struct esdc_regs {	325	struct esdc_regs {
326	u32 esdctl0;	326	u32 esdctl0;
327	u32 esdcfg0;	327	u32 esdcfg0;
328	u32 esdctl1;	328	u32 esdctl1;
329	u32 esdcfg1;	329	u32 esdcfg1;
330	u32 esdmisc;	330	u32 esdmisc;
331	u32 reserved[4];	331	u32 reserved[4];
332	u32 esdcdly[5];	332	u32 esdcdly[5];
333	u32 esdcdlyl;	333	u32 esdcdlyl;
334	};	334	};
335		335
336	#define ESDC_MISC_RST (1 << 1)	336	#define ESDC_MISC_RST (1 << 1)
337	#define ESDC_MISC_MDDR_EN (1 << 2)	337	#define ESDC_MISC_MDDR_EN (1 << 2)
338	#define ESDC_MISC_MDDR_DL_RST (1 << 3)	338	#define ESDC_MISC_MDDR_DL_RST (1 << 3)
339	#define ESDC_MISC_DDR_EN (1 << 8)	339	#define ESDC_MISC_DDR_EN (1 << 8)
340	#define ESDC_MISC_DDR2_EN (1 << 9)	340	#define ESDC_MISC_DDR2_EN (1 << 9)
341		341
342	/*	342	/*
343	* NFMS bit in RCSR register for pagesize of nandflash	343	* NFMS bit in RCSR register for pagesize of nandflash
344	*/	344	*/
345	#define NFMS_BIT 8	345	#define NFMS_BIT 8
346	#define NFMS_NF_DWIDTH 14	346	#define NFMS_NF_DWIDTH 14
347	#define NFMS_NF_PG_SZ 8	347	#define NFMS_NF_PG_SZ 8
348		348
349	#define CCM_RCSR_NF_16BIT_SEL (1 << 14)	349	#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
350		350
351	#endif	351	#endif
352	#endif /* __ASM_ARCH_MX35_H */	352	#endif /* __ASM_ARCH_MX35_H */
353		353

drivers/i2c/mxc_i2c.c

Diff comments View file @ de6f604

 /*
  * i2c driver for Freescale i.MX series
  *
  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
  *
  * Based on i2c-imx.c from linux kernel:
  *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
  *  Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  *  Copyright (C) 2007 RightHand Technologies, Inc.
  *  Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  *
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <asm/io.h>
 #if defined(CONFIG_HARD_I2C)
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <i2c.h>
 struct mxc_i2c_regs {
 	uint32_t	iadr;
 	uint32_t	ifdr;
 	uint32_t	i2cr;
 	uint32_t	i2sr;
 	uint32_t	i2dr;
 };
 #define I2CR_IEN	(1 << 7)
 #define I2CR_IIEN	(1 << 6)
 #define I2CR_MSTA	(1 << 5)
 #define I2CR_MTX	(1 << 4)
 #define I2CR_TX_NO_AK	(1 << 3)
 #define I2CR_RSTA	(1 << 2)
 #define I2SR_ICF	(1 << 7)
 #define I2SR_IBB	(1 << 5)
 #define I2SR_IIF	(1 << 1)
 #define I2SR_RX_NO_AK	(1 << 0)
-#if defined(CONFIG_SYS_I2C_MX31_PORT1)
+#ifdef CONFIG_SYS_I2C_BASE
-#define I2C_BASE	0x43f80000
+#define I2C_BASE	CONFIG_SYS_I2C_BASE
-#define I2C_CLK_OFFSET	26
-#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
-#define I2C_BASE	0x43f98000
-#define I2C_CLK_OFFSET	28
-#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
-#define I2C_BASE	0x43f84000
-#define I2C_CLK_OFFSET	30
-#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
-#define I2C_BASE        I2C1_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
-#define I2C_BASE        I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
-#define I2C_BASE	I2C_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
-#define I2C_BASE	I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
-#define I2C_BASE	I2C3_BASE_ADDR
 #else
-#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
+#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
 #endif
 #define I2C_MAX_TIMEOUT		10000
 static u16 i2c_clk_div[50][2] = {
 	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
 	{ 30,	0x00 }, { 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
 	{ 42,	0x03 }, { 44,	0x27 }, { 48,	0x28 }, { 52,	0x05 },
 	{ 56,	0x29 }, { 60,	0x06 }, { 64,	0x2A }, { 72,	0x2B },
 	{ 80,	0x2C }, { 88,	0x09 }, { 96,	0x2D }, { 104,	0x0A },
 	{ 112,	0x2E }, { 128,	0x2F }, { 144,	0x0C }, { 160,	0x30 },
 	{ 192,	0x31 }, { 224,	0x32 }, { 240,	0x0F }, { 256,	0x33 },
 	{ 288,	0x10 }, { 320,	0x34 }, { 384,	0x35 }, { 448,	0x36 },
 	{ 480,	0x13 }, { 512,	0x37 }, { 576,	0x14 }, { 640,	0x38 },
 	{ 768,	0x39 }, { 896,	0x3A }, { 960,	0x17 }, { 1024,	0x3B },
 	{ 1152,	0x18 }, { 1280,	0x3C }, { 1536,	0x3D }, { 1792,	0x3E },
 	{ 1920,	0x1B }, { 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
 	{ 3072,	0x1E }, { 3840,	0x1F }
 };
 /*
  * Calculate and set proper clock divider
  */
 static uint8_t i2c_imx_get_clk(unsigned int rate)
 {
 	unsigned int i2c_clk_rate;
 	unsigned int div;
 	u8 clk_div;
 #if defined(CONFIG_MX31)
 	struct clock_control_regs *sc_regs =
 		(struct clock_control_regs *)CCM_BASE;
 	/* start the required I2C clock */
-	writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
+	writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
 		&sc_regs->cgr0);
 #endif
 	/* Divider value calculation */
 	i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
 	div = (i2c_clk_rate + rate - 1) / rate;
 	if (div < i2c_clk_div[0][0])
 		clk_div = 0;
 	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
 		clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
 	else
 		for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
 			;
 	/* Store divider value */
 	return clk_div;
 }
 /*
  * Reset I2C Controller
  */
 void i2c_reset(void)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	writeb(0, &i2c_regs->i2cr);	/* Reset module */
 	writeb(0, &i2c_regs->i2sr);
 }
 /*
  * Init I2C Bus
  */
 void i2c_init(int speed, int unused)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	u8 clk_idx = i2c_imx_get_clk(speed);
 	u8 idx = i2c_clk_div[clk_idx][1];
 	/* Store divider value */
 	writeb(idx, &i2c_regs->ifdr);
 	i2c_reset();
 }
 /*
  * Set I2C Speed
  */
 int i2c_set_bus_speed(unsigned int speed)
 {
 	i2c_init(speed, 0);
 	return 0;
 }
 /*
  * Get I2C Speed
  */
 unsigned int i2c_get_bus_speed(void)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	u8 clk_idx = readb(&i2c_regs->ifdr);
 	u8 clk_div;
 	for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
 		;
 	return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
 }
 /*
  * Wait for bus to be busy (or free if for_busy = 0)
  *
  * for_busy = 1: Wait for IBB to be asserted
  * for_busy = 0: Wait for IBB to be de-asserted
  */
 int i2c_imx_bus_busy(int for_busy)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	unsigned int temp;
 	int timeout = I2C_MAX_TIMEOUT;
 	while (timeout--) {
 		temp = readb(&i2c_regs->i2sr);
 		if (for_busy && (temp & I2SR_IBB))
 			return 0;
 		if (!for_busy && !(temp & I2SR_IBB))
 			return 0;
 		udelay(1);
 	}
 	return 1;
 }
 /*
  * Wait for transaction to complete
  */
 int i2c_imx_trx_complete(void)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	int timeout = I2C_MAX_TIMEOUT;
 	while (timeout--) {
 		if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
 			writeb(0, &i2c_regs->i2sr);
 			return 0;
 		}
 		udelay(1);
 	}
 	return 1;
 }
 /*
  * Check if the transaction was ACKed
  */
 int i2c_imx_acked(void)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK;
 }
 /*
  * Start the controller
  */
 int i2c_imx_start(void)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	unsigned int temp = 0;
 	int result;
 	int speed = i2c_get_bus_speed();
 	u8 clk_idx = i2c_imx_get_clk(speed);
 	u8 idx = i2c_clk_div[clk_idx][1];
 	/* Store divider value */
 	writeb(idx, &i2c_regs->ifdr);
 	/* Enable I2C controller */
 	writeb(0, &i2c_regs->i2sr);
 	writeb(I2CR_IEN, &i2c_regs->i2cr);
 	/* Wait controller to be stable */
 	udelay(50);
 	/* Start I2C transaction */
 	temp = readb(&i2c_regs->i2cr);
 	temp |= I2CR_MSTA;
 	writeb(temp, &i2c_regs->i2cr);
 	result = i2c_imx_bus_busy(1);
 	if (result)
 		return result;
 	temp |= I2CR_MTX | I2CR_TX_NO_AK;
 	writeb(temp, &i2c_regs->i2cr);
 	return 0;
 }
 /*
  * Stop the controller
  */
 void i2c_imx_stop(void)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	unsigned int temp = 0;
 	/* Stop I2C transaction */
 	temp = readb(&i2c_regs->i2cr);
 	temp |= ~(I2CR_MSTA | I2CR_MTX);
 	writeb(temp, &i2c_regs->i2cr);
 	i2c_imx_bus_busy(0);
 	/* Disable I2C controller */
 	writeb(0, &i2c_regs->i2cr);
 }
 /*
  * Set chip address and access mode
  *
  * read = 1: READ access
  * read = 0: WRITE access
  */
 int i2c_imx_set_chip_addr(uchar chip, int read)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	int ret;
 	writeb((chip << 1) | read, &i2c_regs->i2dr);
 	ret = i2c_imx_trx_complete();
 	if (ret)
 		return ret;
 	ret = i2c_imx_acked();
 	if (ret)
 		return ret;
 	return ret;
 }
 /*
  * Write register address
  */
 int i2c_imx_set_reg_addr(uint addr, int alen)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	int ret = 0;
 	while (alen--) {
 		writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
 		ret = i2c_imx_trx_complete();
 		if (ret)
 			break;
 		ret = i2c_imx_acked();
 		if (ret)
 			break;
 	}
 	return ret;
 }
 /*
  * Try if a chip add given address responds (probe the chip)
  */
 int i2c_probe(uchar chip)
 {
 	int ret;
 	ret = i2c_imx_start();
 	if (ret)
 		return ret;
 	ret = i2c_imx_set_chip_addr(chip, 0);
 	if (ret)
 		return ret;
 	i2c_imx_stop();
 	return ret;
 }
 /*
  * Read data from I2C device
  */
 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	int ret;
 	unsigned int temp;
 	int i;
 	ret = i2c_imx_start();
 	if (ret)
 		return ret;
 	/* write slave address */
 	ret = i2c_imx_set_chip_addr(chip, 0);
 	if (ret)
 		return ret;
 	ret = i2c_imx_set_reg_addr(addr, alen);
 	if (ret)
 		return ret;
 	temp = readb(&i2c_regs->i2cr);
 	temp |= I2CR_RSTA;
 	writeb(temp, &i2c_regs->i2cr);
 	ret = i2c_imx_set_chip_addr(chip, 1);
 	if (ret)
 		return ret;
 	/* setup bus to read data */
 	temp = readb(&i2c_regs->i2cr);
 	temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
 	if (len == 1)
 		temp |= I2CR_TX_NO_AK;
 	writeb(temp, &i2c_regs->i2cr);
 	readb(&i2c_regs->i2dr);
 	/* read data */
 	for (i = 0; i < len; i++) {
 		ret = i2c_imx_trx_complete();
 		if (ret)
 			return ret;
 		/*
 		 * It must generate STOP before read I2DR to prevent
 		 * controller from generating another clock cycle
 		 */
 		if (i == (len - 1)) {
 			temp = readb(&i2c_regs->i2cr);
 			temp &= ~(I2CR_MSTA | I2CR_MTX);
 			writeb(temp, &i2c_regs->i2cr);
 			i2c_imx_bus_busy(0);
 		} else if (i == (len - 2)) {
 			temp = readb(&i2c_regs->i2cr);
 			temp |= I2CR_TX_NO_AK;
 			writeb(temp, &i2c_regs->i2cr);
 		}
 		buf[i] = readb(&i2c_regs->i2dr);
 	}
 	i2c_imx_stop();
 	return ret;
 }
 /*
  * Write data to I2C device
  */
 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	int ret;
 	int i;
 	ret = i2c_imx_start();
 	if (ret)
 		return ret;
 	/* write slave address */
 	ret = i2c_imx_set_chip_addr(chip, 0);
 	if (ret)
 		return ret;
 	ret = i2c_imx_set_reg_addr(addr, alen);
 	if (ret)
 		return ret;
 	for (i = 0; i < len; i++) {
 		writeb(buf[i], &i2c_regs->i2dr);
 		ret = i2c_imx_trx_complete();
 		if (ret)
 			return ret;
 		ret = i2c_imx_acked();
 		if (ret)
 			return ret;
 	}
 	i2c_imx_stop();
 	return ret;
 }
 #endif /* CONFIG_HARD_I2C */

include/configs/flea3.h

Diff comments View file @ de6f604

include/configs/imx31_phycore.h

Diff comments View file @ de6f604

 /*
  * (C) Copyright 2004
  * Texas Instruments.
  * Richard Woodruff <r-woodruff2@ti.com>
  * Kshitij Gupta <kshitij@ti.com>
  *
  * Configuration settings for the phyCORE-i.MX31 board.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <asm/arch/imx-regs.h>
 /* High Level Configuration Options */
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
 #define CONFIG_MX31_HCLK_FREQ	26000000
 #define CONFIG_MX31_CLK32	32000
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)
 /*
  * Hardware drivers
  */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX31_PORT2
+#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
 /***********************************************************
  * Command definition
  ***********************************************************/
 #include <config_cmd_default.h>
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
 #define CONFIG_BOOTDELAY	3
 #define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
 					"1536k(kernel),-(root)"
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_IPADDR		192.168.23.168
 #define CONFIG_SERVERIP		192.168.23.2
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
 	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
 		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
 	"bootargs_flash=setenv bootargs $(bootargs) "			\
 		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
 	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
 	"bootcmd=run bootcmd_net\0"					\
 	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;"	\
 		"tftpboot 0x80000000 $(uimage);bootm\0"			\
 	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;"	\
 		"bootm 0x80000000\0"					\
 	"unlock=yes\0"							\
 	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
 	"prg_uboot=tftpboot 0x80000000 $(uboot);"			\
 		"protect off 0xa0000000 +0x20000;"			\
 		"erase 0xa0000000 +0x20000;"				\
 		"cp.b 0x80000000 0xa0000000 $(filesize)\0"		\
 	"prg_kernel=tftpboot 0x80000000 $(uimage);"			\
 		"erase 0xa0040000 +0x180000;"				\
 		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
 	"prg_jffs2=tftpboot 0x80000000 $(jffs2);"			\
 		"erase 0xa01c0000 0xa1ffffff;"				\
 		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"		\
 	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,"		\
 		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
 		"sync:1241513985,vmode:0\0"
 #define CONFIG_SMC911X
 #define CONFIG_SMC911X_BASE	0xa8000000
 #define CONFIG_SMC911X_32_BIT
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_PROMPT		"uboot> "
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		256
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					 sizeof(CONFIG_SYS_PROMPT) + 16)
 /* max number of command args */
 #define CONFIG_SYS_MAXARGS		16
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x10000
 #define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_CMDLINE_EDITING
 /*
  * Stack sizes
  *
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE	(128 * 1024) /* regular stack */
 /*
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_1_SIZE		(128 * 1024 * 1024)
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_SYS_TEXT_BASE		0xA0000000
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
 						CONFIG_SYS_GBL_DATA_OFFSET)
 /*
  * FLASH and environment organization
  */
 #define CONFIG_SYS_FLASH_BASE		0xa0000000
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	259	/* max # of sectors/chip */
 /* Monitor at beginning of flash */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_OFFSET			0x00	/* env. starts here */
 #define CONFIG_ENV_SIZE				4096
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10 ms delay */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* byte addr. lenght */
 /*
  * CFI FLASH driver setup
  */
 #define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/mtd/cfi_flash.c */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
 #define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
 /*
  * Timeout for Flash Erase and Flash Write
  * timeout values are in ticks
  */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ)
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ)
 /*
  * JFFS2 partitions
  */
 #undef CONFIG_CMD_MTDPARTS
 #define CONFIG_JFFS2_DEV	"nor0"
 /* EET platform additions */
 #ifdef CONFIG_IMX31_PHYCORE_EET
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 #define CONFIG_HARD_SPI
 #define CONFIG_MXC_SPI
 #define CONFIG_CMD_SPI
 #define CONFIG_S6E63D6
 #define CONFIG_VIDEO
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_MX3
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #endif
 #endif /* __CONFIG_H */

include/configs/mx35pdk.h

Diff comments View file @ de6f604

include/configs/mx53ard.h

Diff comments View file @ de6f604

1	/*	1	/*
2	* Copyright (C) 2011 Freescale Semiconductor, Inc.	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
3	*	3	*
4	* Configuration settings for the MX53ARD Freescale board.	4	* Configuration settings for the MX53ARD Freescale board.
5	*	5	*
6	* This program is free software; you can redistribute it and/or	6	* This program is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU General Public License as	7	* modify it under the terms of the GNU General Public License as
8	* published by the Free Software Foundation; either version 2 of	8	* published by the Free Software Foundation; either version 2 of
9	* the License, or (at your option) any later version.	9	* the License, or (at your option) any later version.
10	*	10	*
11	* This program is distributed in the hope that it will be useful,	11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.	14	* GNU General Public License for more details.
15	*	15	*
16	* You should have received a copy of the GNU General Public License	16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software	17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19	* MA 02111-1307 USA	19	* MA 02111-1307 USA
20	*/	20	*/
21		21
22	#ifndef __CONFIG_H	22	#ifndef __CONFIG_H
23	#define __CONFIG_H	23	#define __CONFIG_H
24		24
25	#define CONFIG_MX53	25	#define CONFIG_MX53
26		26
27	#define CONFIG_SYS_MX5_HCLK 24000000	27	#define CONFIG_SYS_MX5_HCLK 24000000
28	#define CONFIG_SYS_MX5_CLK32 32768	28	#define CONFIG_SYS_MX5_CLK32 32768
29	#define CONFIG_DISPLAY_CPUINFO	29	#define CONFIG_DISPLAY_CPUINFO
30	#define CONFIG_DISPLAY_BOARDINFO	30	#define CONFIG_DISPLAY_BOARDINFO
31		31
32	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD	32	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
33		33
34	#include <asm/arch/imx-regs.h>	34	#include <asm/arch/imx-regs.h>
35		35
36	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */	36	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
37	#define CONFIG_SETUP_MEMORY_TAGS	37	#define CONFIG_SETUP_MEMORY_TAGS
38	#define CONFIG_INITRD_TAG	38	#define CONFIG_INITRD_TAG
39		39
40	/* Size of malloc() pool */	40	/* Size of malloc() pool */
41	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)	41	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
42		42
43	#define CONFIG_BOARD_EARLY_INIT_F	43	#define CONFIG_BOARD_EARLY_INIT_F
44	#define CONFIG_MXC_GPIO	44	#define CONFIG_MXC_GPIO
45		45
46	#define CONFIG_MXC_UART	46	#define CONFIG_MXC_UART
47	#define CONFIG_MXC_UART_BASE UART1_BASE	47	#define CONFIG_MXC_UART_BASE UART1_BASE
48		48
49	/* I2C Configs */	49	/* I2C Configs */
50	#define CONFIG_CMD_I2C	50	#define CONFIG_CMD_I2C
51	#define CONFIG_HARD_I2C	51	#define CONFIG_HARD_I2C
52	#define CONFIG_I2C_MXC	52	#define CONFIG_I2C_MXC
53	#define CONFIG_SYS_I2C_MX53_PORT2	53	#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
54	#define CONFIG_SYS_I2C_SPEED 100000	54	#define CONFIG_SYS_I2C_SPEED 100000
55		55
56	/* MMC Configs */	56	/* MMC Configs */
57	#define CONFIG_FSL_ESDHC	57	#define CONFIG_FSL_ESDHC
58	#define CONFIG_SYS_FSL_ESDHC_ADDR 0	58	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
59	#define CONFIG_SYS_FSL_ESDHC_NUM 2	59	#define CONFIG_SYS_FSL_ESDHC_NUM 2
60		60
61	#define CONFIG_MMC	61	#define CONFIG_MMC
62	#define CONFIG_CMD_MMC	62	#define CONFIG_CMD_MMC
63	#define CONFIG_GENERIC_MMC	63	#define CONFIG_GENERIC_MMC
64	#define CONFIG_CMD_FAT	64	#define CONFIG_CMD_FAT
65	#define CONFIG_DOS_PARTITION	65	#define CONFIG_DOS_PARTITION
66		66
67	/* Eth Configs */	67	/* Eth Configs */
68	#define CONFIG_HAS_ETH1	68	#define CONFIG_HAS_ETH1
69	#define CONFIG_MII	69	#define CONFIG_MII
70	#define CONFIG_DISCOVER_PHY	70	#define CONFIG_DISCOVER_PHY
71		71
72	#define CONFIG_CMD_PING	72	#define CONFIG_CMD_PING
73	#define CONFIG_CMD_DHCP	73	#define CONFIG_CMD_DHCP
74	#define CONFIG_CMD_MII	74	#define CONFIG_CMD_MII
75	#define CONFIG_CMD_NET	75	#define CONFIG_CMD_NET
76		76
77	/* allow to overwrite serial and ethaddr */	77	/* allow to overwrite serial and ethaddr */
78	#define CONFIG_ENV_OVERWRITE	78	#define CONFIG_ENV_OVERWRITE
79	#define CONFIG_CONS_INDEX 1	79	#define CONFIG_CONS_INDEX 1
80	#define CONFIG_BAUDRATE 115200	80	#define CONFIG_BAUDRATE 115200
81		81
82	/* Command definition */	82	/* Command definition */
83	#include <config_cmd_default.h>	83	#include <config_cmd_default.h>
84		84
85	#undef CONFIG_CMD_IMLS	85	#undef CONFIG_CMD_IMLS
86		86
87	#define CONFIG_BOOTDELAY 3	87	#define CONFIG_BOOTDELAY 3
88		88
89	#define CONFIG_ETHPRIME "smc911x"	89	#define CONFIG_ETHPRIME "smc911x"
90		90
91	/Support LAN9217/	91	/Support LAN9217/
92	#define CONFIG_SMC911X	92	#define CONFIG_SMC911X
93	#define CONFIG_SMC911X_16_BIT	93	#define CONFIG_SMC911X_16_BIT
94	#define CONFIG_SMC911X_BASE CS1_BASE_ADDR	94	#define CONFIG_SMC911X_BASE CS1_BASE_ADDR
95		95
96	#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */	96	#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
97	#define CONFIG_SYS_TEXT_BASE 0x77800000	97	#define CONFIG_SYS_TEXT_BASE 0x77800000
98		98
99	#define CONFIG_EXTRA_ENV_SETTINGS \	99	#define CONFIG_EXTRA_ENV_SETTINGS \
100	"script=boot.scr\0" \	100	"script=boot.scr\0" \
101	"uimage=uImage\0" \	101	"uimage=uImage\0" \
102	"mmcdev=0\0" \	102	"mmcdev=0\0" \
103	"mmcpart=2\0" \	103	"mmcpart=2\0" \
104	"mmcroot=/dev/mmcblk0p3 rw\0" \	104	"mmcroot=/dev/mmcblk0p3 rw\0" \
105	"mmcrootfstype=ext3 rootwait\0" \	105	"mmcrootfstype=ext3 rootwait\0" \
106	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \	106	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
107	"root=${mmcroot} " \	107	"root=${mmcroot} " \
108	"rootfstype=${mmcrootfstype}\0" \	108	"rootfstype=${mmcrootfstype}\0" \
109	"loadbootscript=" \	109	"loadbootscript=" \
110	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \	110	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
111	"bootscript=echo Running bootscript from mmc ...; " \	111	"bootscript=echo Running bootscript from mmc ...; " \
112	"source\0" \	112	"source\0" \
113	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \	113	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
114	"mmcboot=echo Booting from mmc ...; " \	114	"mmcboot=echo Booting from mmc ...; " \
115	"run mmcargs; " \	115	"run mmcargs; " \
116	"bootm\0" \	116	"bootm\0" \
117	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \	117	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
118	"root=/dev/nfs " \	118	"root=/dev/nfs " \
119	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \	119	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
120	"netboot=echo Booting from net ...; " \	120	"netboot=echo Booting from net ...; " \
121	"run netargs; " \	121	"run netargs; " \
122	"dhcp ${uimage}; bootm\0" \	122	"dhcp ${uimage}; bootm\0" \
123		123
124	#define CONFIG_BOOTCOMMAND \	124	#define CONFIG_BOOTCOMMAND \
125	"if mmc rescan ${mmcdev}; then " \	125	"if mmc rescan ${mmcdev}; then " \
126	"if run loadbootscript; then " \	126	"if run loadbootscript; then " \
127	"run bootscript; " \	127	"run bootscript; " \
128	"else " \	128	"else " \
129	"if run loaduimage; then " \	129	"if run loaduimage; then " \
130	"run mmcboot; " \	130	"run mmcboot; " \
131	"else run netboot; " \	131	"else run netboot; " \
132	"fi; " \	132	"fi; " \
133	"fi; " \	133	"fi; " \
134	"else run netboot; fi"	134	"else run netboot; fi"
135	#define CONFIG_ARP_TIMEOUT 200UL	135	#define CONFIG_ARP_TIMEOUT 200UL
136		136
137	/* Miscellaneous configurable options */	137	/* Miscellaneous configurable options */
138	#define CONFIG_SYS_LONGHELP /* undef to save memory */	138	#define CONFIG_SYS_LONGHELP /* undef to save memory */
139	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */	139	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
140	#define CONFIG_SYS_PROMPT "MX53ARD U-Boot > "	140	#define CONFIG_SYS_PROMPT "MX53ARD U-Boot > "
141	#define CONFIG_AUTO_COMPLETE	141	#define CONFIG_AUTO_COMPLETE
142	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */	142	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
143		143
144	/* Print Buffer Size */	144	/* Print Buffer Size */
145	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	145	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
146	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */	146	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
147	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */	147	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
148		148
149	#define CONFIG_SYS_MEMTEST_START 0x70000000	149	#define CONFIG_SYS_MEMTEST_START 0x70000000
150	#define CONFIG_SYS_MEMTEST_END 0x70010000	150	#define CONFIG_SYS_MEMTEST_END 0x70010000
151		151
152	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR	152	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
153		153
154	#define CONFIG_SYS_HZ 1000	154	#define CONFIG_SYS_HZ 1000
155	#define CONFIG_CMDLINE_EDITING	155	#define CONFIG_CMDLINE_EDITING
156		156
157	/* Stack sizes */	157	/* Stack sizes */
158	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */	158	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
159		159
160	/* Physical Memory Map */	160	/* Physical Memory Map */
161	#define CONFIG_NR_DRAM_BANKS 2	161	#define CONFIG_NR_DRAM_BANKS 2
162	#define PHYS_SDRAM_1 CSD0_BASE_ADDR	162	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
163	#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)	163	#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
164	#define PHYS_SDRAM_2 CSD1_BASE_ADDR	164	#define PHYS_SDRAM_2 CSD1_BASE_ADDR
165	#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)	165	#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
166	#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)	166	#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
167		167
168	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)	168	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
169	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)	169	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
170	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)	170	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
171		171
172	#define CONFIG_SYS_INIT_SP_OFFSET \	172	#define CONFIG_SYS_INIT_SP_OFFSET \
173	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)	173	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
174	#define CONFIG_SYS_INIT_SP_ADDR \	174	#define CONFIG_SYS_INIT_SP_ADDR \
175	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)	175	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
176		176
177	/* FLASH and environment organization */	177	/* FLASH and environment organization */
178	#define CONFIG_SYS_NO_FLASH	178	#define CONFIG_SYS_NO_FLASH
179		179
180	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)	180	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
181	#define CONFIG_ENV_SIZE (8 * 1024)	181	#define CONFIG_ENV_SIZE (8 * 1024)
182	#define CONFIG_ENV_IS_IN_MMC	182	#define CONFIG_ENV_IS_IN_MMC
183	#define CONFIG_SYS_MMC_ENV_DEV 0	183	#define CONFIG_SYS_MMC_ENV_DEV 0
184		184
185	#define CONFIG_OF_LIBFDT	185	#define CONFIG_OF_LIBFDT
186		186
187	#define MX53ARD_CS1GCR1 (CSEN \| DSZ(2))	187	#define MX53ARD_CS1GCR1 (CSEN \| DSZ(2))
188	#define MX53ARD_CS1RCR1 (RCSN(2) \| OEN (1) \| RWSC(22))	188	#define MX53ARD_CS1RCR1 (RCSN(2) \| OEN (1) \| RWSC(22))
189	#define MX53ARD_CS1RCR2 RBEN(2)	189	#define MX53ARD_CS1RCR2 RBEN(2)
190	#define MX53ARD_CS1WCR1 (WCSN(2) \| WEN(2) \| WBEN(2) \| WWSC(22))	190	#define MX53ARD_CS1WCR1 (WCSN(2) \| WEN(2) \| WBEN(2) \| WWSC(22))
191		191
192	#endif /* __CONFIG_H */	192	#endif /* __CONFIG_H */
193		193

include/configs/mx53evk.h

Diff comments View file @ de6f604

1	/*	1	/*
2	* Copyright (C) 2010 Freescale Semiconductor, Inc.	2	* Copyright (C) 2010 Freescale Semiconductor, Inc.
3	*	3	*
4	* Configuration settings for the MX53-EVK Freescale board.	4	* Configuration settings for the MX53-EVK Freescale board.
5	*	5	*
6	* This program is free software; you can redistribute it and/or	6	* This program is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU General Public License as	7	* modify it under the terms of the GNU General Public License as
8	* published by the Free Software Foundation; either version 2 of	8	* published by the Free Software Foundation; either version 2 of
9	* the License, or (at your option) any later version.	9	* the License, or (at your option) any later version.
10	*	10	*
11	* This program is distributed in the hope that it will be useful,	11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.	14	* GNU General Public License for more details.
15	*	15	*
16	* You should have received a copy of the GNU General Public License	16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software	17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19	* MA 02111-1307 USA	19	* MA 02111-1307 USA
20	*/	20	*/
21		21
22	#ifndef __CONFIG_H	22	#ifndef __CONFIG_H
23	#define __CONFIG_H	23	#define __CONFIG_H
24		24
25	#define CONFIG_MX53	25	#define CONFIG_MX53
26		26
27	#define CONFIG_SYS_MX5_HCLK 24000000	27	#define CONFIG_SYS_MX5_HCLK 24000000
28	#define CONFIG_SYS_MX5_CLK32 32768	28	#define CONFIG_SYS_MX5_CLK32 32768
29	#define CONFIG_DISPLAY_CPUINFO	29	#define CONFIG_DISPLAY_CPUINFO
30	#define CONFIG_DISPLAY_BOARDINFO	30	#define CONFIG_DISPLAY_BOARDINFO
31		31
32	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK	32	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK
33		33
34	#include <asm/arch/imx-regs.h>	34	#include <asm/arch/imx-regs.h>
35		35
36	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */	36	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
37	#define CONFIG_SETUP_MEMORY_TAGS	37	#define CONFIG_SETUP_MEMORY_TAGS
38	#define CONFIG_INITRD_TAG	38	#define CONFIG_INITRD_TAG
39		39
40	#define CONFIG_OF_LIBFDT	40	#define CONFIG_OF_LIBFDT
41		41
42	/* Size of malloc() pool */	42	/* Size of malloc() pool */
43	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)	43	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
44		44
45	#define CONFIG_BOARD_EARLY_INIT_F	45	#define CONFIG_BOARD_EARLY_INIT_F
46	#define CONFIG_BOARD_LATE_INIT	46	#define CONFIG_BOARD_LATE_INIT
47	#define CONFIG_MXC_GPIO	47	#define CONFIG_MXC_GPIO
48		48
49	#define CONFIG_MXC_UART	49	#define CONFIG_MXC_UART
50	#define CONFIG_MXC_UART_BASE UART1_BASE	50	#define CONFIG_MXC_UART_BASE UART1_BASE
51		51
52	/* I2C Configs */	52	/* I2C Configs */
53	#define CONFIG_CMD_I2C	53	#define CONFIG_CMD_I2C
54	#define CONFIG_HARD_I2C	54	#define CONFIG_HARD_I2C
55	#define CONFIG_I2C_MXC	55	#define CONFIG_I2C_MXC
56	#define CONFIG_SYS_I2C_MX53_PORT2 1	56	#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
57	#define CONFIG_SYS_I2C_SPEED 100000	57	#define CONFIG_SYS_I2C_SPEED 100000
58		58
59	/* PMIC Configs */	59	/* PMIC Configs */
60	#define CONFIG_PMIC	60	#define CONFIG_PMIC
61	#define CONFIG_PMIC_I2C	61	#define CONFIG_PMIC_I2C
62	#define CONFIG_PMIC_FSL	62	#define CONFIG_PMIC_FSL
63	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8	63	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
64	#define CONFIG_RTC_MC13XXX	64	#define CONFIG_RTC_MC13XXX
65		65
66	/* MMC Configs */	66	/* MMC Configs */
67	#define CONFIG_FSL_ESDHC	67	#define CONFIG_FSL_ESDHC
68	#define CONFIG_SYS_FSL_ESDHC_ADDR 0	68	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
69	#define CONFIG_SYS_FSL_ESDHC_NUM 2	69	#define CONFIG_SYS_FSL_ESDHC_NUM 2
70		70
71	#define CONFIG_MMC	71	#define CONFIG_MMC
72	#define CONFIG_CMD_MMC	72	#define CONFIG_CMD_MMC
73	#define CONFIG_GENERIC_MMC	73	#define CONFIG_GENERIC_MMC
74	#define CONFIG_CMD_FAT	74	#define CONFIG_CMD_FAT
75	#define CONFIG_DOS_PARTITION	75	#define CONFIG_DOS_PARTITION
76		76
77	/* Eth Configs */	77	/* Eth Configs */
78	#define CONFIG_HAS_ETH1	78	#define CONFIG_HAS_ETH1
79	#define CONFIG_MII	79	#define CONFIG_MII
80	#define CONFIG_DISCOVER_PHY	80	#define CONFIG_DISCOVER_PHY
81		81
82	#define CONFIG_FEC_MXC	82	#define CONFIG_FEC_MXC
83	#define IMX_FEC_BASE FEC_BASE_ADDR	83	#define IMX_FEC_BASE FEC_BASE_ADDR
84	#define CONFIG_FEC_MXC_PHYADDR 0x1F	84	#define CONFIG_FEC_MXC_PHYADDR 0x1F
85		85
86	#define CONFIG_CMD_PING	86	#define CONFIG_CMD_PING
87	#define CONFIG_CMD_DHCP	87	#define CONFIG_CMD_DHCP
88	#define CONFIG_CMD_MII	88	#define CONFIG_CMD_MII
89	#define CONFIG_CMD_NET	89	#define CONFIG_CMD_NET
90	#define CONFIG_CMD_DATE	90	#define CONFIG_CMD_DATE
91		91
92	/* allow to overwrite serial and ethaddr */	92	/* allow to overwrite serial and ethaddr */
93	#define CONFIG_ENV_OVERWRITE	93	#define CONFIG_ENV_OVERWRITE
94	#define CONFIG_CONS_INDEX 1	94	#define CONFIG_CONS_INDEX 1
95	#define CONFIG_BAUDRATE 115200	95	#define CONFIG_BAUDRATE 115200
96		96
97	/* Command definition */	97	/* Command definition */
98	#include <config_cmd_default.h>	98	#include <config_cmd_default.h>
99		99
100	#undef CONFIG_CMD_IMLS	100	#undef CONFIG_CMD_IMLS
101		101
102	#define CONFIG_BOOTDELAY 3	102	#define CONFIG_BOOTDELAY 3
103		103
104	#define CONFIG_ETHPRIME "FEC0"	104	#define CONFIG_ETHPRIME "FEC0"
105		105
106	#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */	106	#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
107	#define CONFIG_SYS_TEXT_BASE 0x77800000	107	#define CONFIG_SYS_TEXT_BASE 0x77800000
108		108
109	#define CONFIG_EXTRA_ENV_SETTINGS \	109	#define CONFIG_EXTRA_ENV_SETTINGS \
110	"script=boot.scr\0" \	110	"script=boot.scr\0" \
111	"uimage=uImage\0" \	111	"uimage=uImage\0" \
112	"mmcdev=0\0" \	112	"mmcdev=0\0" \
113	"mmcpart=2\0" \	113	"mmcpart=2\0" \
114	"mmcroot=/dev/mmcblk0p3 rw\0" \	114	"mmcroot=/dev/mmcblk0p3 rw\0" \
115	"mmcrootfstype=ext3 rootwait\0" \	115	"mmcrootfstype=ext3 rootwait\0" \
116	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \	116	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
117	"root=${mmcroot} " \	117	"root=${mmcroot} " \
118	"rootfstype=${mmcrootfstype}\0" \	118	"rootfstype=${mmcrootfstype}\0" \
119	"loadbootscript=" \	119	"loadbootscript=" \
120	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \	120	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
121	"bootscript=echo Running bootscript from mmc ...; " \	121	"bootscript=echo Running bootscript from mmc ...; " \
122	"source\0" \	122	"source\0" \
123	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \	123	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
124	"mmcboot=echo Booting from mmc ...; " \	124	"mmcboot=echo Booting from mmc ...; " \
125	"run mmcargs; " \	125	"run mmcargs; " \
126	"bootm\0" \	126	"bootm\0" \
127	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \	127	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
128	"root=/dev/nfs " \	128	"root=/dev/nfs " \
129	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \	129	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
130	"netboot=echo Booting from net ...; " \	130	"netboot=echo Booting from net ...; " \
131	"run netargs; " \	131	"run netargs; " \
132	"dhcp ${uimage}; bootm\0" \	132	"dhcp ${uimage}; bootm\0" \
133		133
134	#define CONFIG_BOOTCOMMAND \	134	#define CONFIG_BOOTCOMMAND \
135	"if mmc rescan ${mmcdev}; then " \	135	"if mmc rescan ${mmcdev}; then " \
136	"if run loadbootscript; then " \	136	"if run loadbootscript; then " \
137	"run bootscript; " \	137	"run bootscript; " \
138	"else " \	138	"else " \
139	"if run loaduimage; then " \	139	"if run loaduimage; then " \
140	"run mmcboot; " \	140	"run mmcboot; " \
141	"else run netboot; " \	141	"else run netboot; " \
142	"fi; " \	142	"fi; " \
143	"fi; " \	143	"fi; " \
144	"else run netboot; fi"	144	"else run netboot; fi"
145		145
146	#define CONFIG_ARP_TIMEOUT 200UL	146	#define CONFIG_ARP_TIMEOUT 200UL
147		147
148	/* Miscellaneous configurable options */	148	/* Miscellaneous configurable options */
149	#define CONFIG_SYS_LONGHELP /* undef to save memory */	149	#define CONFIG_SYS_LONGHELP /* undef to save memory */
150	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */	150	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
151	#define CONFIG_SYS_PROMPT "MX53EVK U-Boot > "	151	#define CONFIG_SYS_PROMPT "MX53EVK U-Boot > "
152	#define CONFIG_AUTO_COMPLETE	152	#define CONFIG_AUTO_COMPLETE
153	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */	153	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
154		154
155	/* Print Buffer Size */	155	/* Print Buffer Size */
156	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	156	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
157	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */	157	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
158	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */	158	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
159		159
160	#define CONFIG_SYS_MEMTEST_START 0x70000000	160	#define CONFIG_SYS_MEMTEST_START 0x70000000
161	#define CONFIG_SYS_MEMTEST_END 0x70010000	161	#define CONFIG_SYS_MEMTEST_END 0x70010000
162		162
163	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR	163	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
164		164
165	#define CONFIG_SYS_HZ 1000	165	#define CONFIG_SYS_HZ 1000
166	#define CONFIG_CMDLINE_EDITING	166	#define CONFIG_CMDLINE_EDITING
167		167
168	/* Stack sizes */	168	/* Stack sizes */
169	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */	169	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
170		170
171	/* Physical Memory Map */	171	/* Physical Memory Map */
172	#define CONFIG_NR_DRAM_BANKS 1	172	#define CONFIG_NR_DRAM_BANKS 1
173	#define PHYS_SDRAM_1 CSD0_BASE_ADDR	173	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
174	#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)	174	#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
175		175
176	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)	176	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
177	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)	177	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
178	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)	178	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
179		179
180	#define CONFIG_SYS_INIT_SP_OFFSET \	180	#define CONFIG_SYS_INIT_SP_OFFSET \
181	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)	181	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
182	#define CONFIG_SYS_INIT_SP_ADDR \	182	#define CONFIG_SYS_INIT_SP_ADDR \
183	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)	183	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
184		184
185	/* FLASH and environment organization */	185	/* FLASH and environment organization */
186	#define CONFIG_SYS_NO_FLASH	186	#define CONFIG_SYS_NO_FLASH
187		187
188	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)	188	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
189	#define CONFIG_ENV_SIZE (8 * 1024)	189	#define CONFIG_ENV_SIZE (8 * 1024)
190	#define CONFIG_ENV_IS_IN_MMC	190	#define CONFIG_ENV_IS_IN_MMC
191	#define CONFIG_SYS_MMC_ENV_DEV 0	191	#define CONFIG_SYS_MMC_ENV_DEV 0
192		192
193	#endif /* __CONFIG_H */	193	#endif /* __CONFIG_H */
194		194

include/configs/mx53loco.h

Diff comments View file @ de6f604

1	/*	1	/*
2	* Copyright (C) 2011 Freescale Semiconductor, Inc.	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
3	* Jason Liu <r64343@freescale.com>	3	* Jason Liu <r64343@freescale.com>
4	*	4	*
5	* Configuration settings for Freescale MX53 low cost board.	5	* Configuration settings for Freescale MX53 low cost board.
6	*	6	*
7	* This program is free software; you can redistribute it and/or	7	* This program is free software; you can redistribute it and/or
8	* modify it under the terms of the GNU General Public License as	8	* modify it under the terms of the GNU General Public License as
9	* published by the Free Software Foundation; either version 2 of	9	* published by the Free Software Foundation; either version 2 of
10	* the License, or (at your option) any later version.	10	* the License, or (at your option) any later version.
11	*	11	*
12	* This program is distributed in the hope that it will be useful,	12	* This program is distributed in the hope that it will be useful,
13	* but WITHOUT ANY WARRANTY; without even the implied warranty of	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	* GNU General Public License for more details.	15	* GNU General Public License for more details.
16	*	16	*
17	* You should have received a copy of the GNU General Public License	17	* You should have received a copy of the GNU General Public License
18	* along with this program; if not, write to the Free Software	18	* along with this program; if not, write to the Free Software
19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20	* MA 02111-1307 USA	20	* MA 02111-1307 USA
21	*/	21	*/
22		22
23	#ifndef __CONFIG_H	23	#ifndef __CONFIG_H
24	#define __CONFIG_H	24	#define __CONFIG_H
25		25
26	#define CONFIG_MX53	26	#define CONFIG_MX53
27		27
28	#define CONFIG_SYS_MX5_HCLK 24000000	28	#define CONFIG_SYS_MX5_HCLK 24000000
29	#define CONFIG_SYS_MX5_CLK32 32768	29	#define CONFIG_SYS_MX5_CLK32 32768
30	#define CONFIG_DISPLAY_BOARDINFO	30	#define CONFIG_DISPLAY_BOARDINFO
31		31
32	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO	32	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
33		33
34	#include <asm/arch/imx-regs.h>	34	#include <asm/arch/imx-regs.h>
35		35
36	#define CONFIG_CMDLINE_TAG	36	#define CONFIG_CMDLINE_TAG
37	#define CONFIG_SETUP_MEMORY_TAGS	37	#define CONFIG_SETUP_MEMORY_TAGS
38	#define CONFIG_INITRD_TAG	38	#define CONFIG_INITRD_TAG
39		39
40	/* Size of malloc() pool */	40	/* Size of malloc() pool */
41	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)	41	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
42		42
43	#define CONFIG_BOARD_EARLY_INIT_F	43	#define CONFIG_BOARD_EARLY_INIT_F
44	#define CONFIG_MXC_GPIO	44	#define CONFIG_MXC_GPIO
45	#define CONFIG_REVISION_TAG	45	#define CONFIG_REVISION_TAG
46		46
47	#define CONFIG_MXC_UART	47	#define CONFIG_MXC_UART
48	#define CONFIG_MXC_UART_BASE UART1_BASE	48	#define CONFIG_MXC_UART_BASE UART1_BASE
49		49
50	/* MMC Configs */	50	/* MMC Configs */
51	#define CONFIG_FSL_ESDHC	51	#define CONFIG_FSL_ESDHC
52	#define CONFIG_SYS_FSL_ESDHC_ADDR 0	52	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
53	#define CONFIG_SYS_FSL_ESDHC_NUM 2	53	#define CONFIG_SYS_FSL_ESDHC_NUM 2
54		54
55	#define CONFIG_MMC	55	#define CONFIG_MMC
56	#define CONFIG_CMD_MMC	56	#define CONFIG_CMD_MMC
57	#define CONFIG_GENERIC_MMC	57	#define CONFIG_GENERIC_MMC
58	#define CONFIG_CMD_FAT	58	#define CONFIG_CMD_FAT
59	#define CONFIG_CMD_EXT2	59	#define CONFIG_CMD_EXT2
60	#define CONFIG_DOS_PARTITION	60	#define CONFIG_DOS_PARTITION
61		61
62	/* Eth Configs */	62	/* Eth Configs */
63	#define CONFIG_HAS_ETH1	63	#define CONFIG_HAS_ETH1
64	#define CONFIG_MII	64	#define CONFIG_MII
65	#define CONFIG_DISCOVER_PHY	65	#define CONFIG_DISCOVER_PHY
66		66
67	#define CONFIG_FEC_MXC	67	#define CONFIG_FEC_MXC
68	#define IMX_FEC_BASE FEC_BASE_ADDR	68	#define IMX_FEC_BASE FEC_BASE_ADDR
69	#define CONFIG_FEC_MXC_PHYADDR 0x1F	69	#define CONFIG_FEC_MXC_PHYADDR 0x1F
70		70
71	#define CONFIG_CMD_PING	71	#define CONFIG_CMD_PING
72	#define CONFIG_CMD_DHCP	72	#define CONFIG_CMD_DHCP
73	#define CONFIG_CMD_MII	73	#define CONFIG_CMD_MII
74	#define CONFIG_CMD_NET	74	#define CONFIG_CMD_NET
75		75
76	/* USB Configs */	76	/* USB Configs */
77	#define CONFIG_CMD_USB	77	#define CONFIG_CMD_USB
78	#define CONFIG_CMD_FAT	78	#define CONFIG_CMD_FAT
79	#define CONFIG_USB_EHCI	79	#define CONFIG_USB_EHCI
80	#define CONFIG_USB_EHCI_MX5	80	#define CONFIG_USB_EHCI_MX5
81	#define CONFIG_USB_STORAGE	81	#define CONFIG_USB_STORAGE
82	#define CONFIG_USB_HOST_ETHER	82	#define CONFIG_USB_HOST_ETHER
83	#define CONFIG_USB_ETHER_ASIX	83	#define CONFIG_USB_ETHER_ASIX
84	#define CONFIG_USB_ETHER_SMSC95XX	84	#define CONFIG_USB_ETHER_SMSC95XX
85	#define CONFIG_MXC_USB_PORT 1	85	#define CONFIG_MXC_USB_PORT 1
86	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)	86	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
87	#define CONFIG_MXC_USB_FLAGS 0	87	#define CONFIG_MXC_USB_FLAGS 0
88		88
89	/* I2C Configs */	89	/* I2C Configs */
90	#define CONFIG_HARD_I2C	90	#define CONFIG_HARD_I2C
91	#define CONFIG_I2C_MXC	91	#define CONFIG_I2C_MXC
92	#define CONFIG_SYS_I2C_MX53_PORT1	92	#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
93	#define CONFIG_SYS_I2C_SPEED 100000	93	#define CONFIG_SYS_I2C_SPEED 100000
94		94
95	/* PMIC Controller */	95	/* PMIC Controller */
96	#define CONFIG_PMIC	96	#define CONFIG_PMIC
97	#define CONFIG_PMIC_I2C	97	#define CONFIG_PMIC_I2C
98	#define CONFIG_DIALOG_PMIC	98	#define CONFIG_DIALOG_PMIC
99	#define CONFIG_PMIC_FSL	99	#define CONFIG_PMIC_FSL
100	#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48	100	#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
101	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8	101	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
102		102
103	/* allow to overwrite serial and ethaddr */	103	/* allow to overwrite serial and ethaddr */
104	#define CONFIG_ENV_OVERWRITE	104	#define CONFIG_ENV_OVERWRITE
105	#define CONFIG_CONS_INDEX 1	105	#define CONFIG_CONS_INDEX 1
106	#define CONFIG_BAUDRATE 115200	106	#define CONFIG_BAUDRATE 115200
107		107
108	/* Command definition */	108	/* Command definition */
109	#include <config_cmd_default.h>	109	#include <config_cmd_default.h>
110		110
111	#undef CONFIG_CMD_IMLS	111	#undef CONFIG_CMD_IMLS
112		112
113	#define CONFIG_BOOTDELAY 3	113	#define CONFIG_BOOTDELAY 3
114		114
115	#define CONFIG_ETHPRIME "FEC0"	115	#define CONFIG_ETHPRIME "FEC0"
116		116
117	#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */	117	#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
118	#define CONFIG_SYS_TEXT_BASE 0x77800000	118	#define CONFIG_SYS_TEXT_BASE 0x77800000
119		119
120	#define CONFIG_EXTRA_ENV_SETTINGS \	120	#define CONFIG_EXTRA_ENV_SETTINGS \
121	"script=boot.scr\0" \	121	"script=boot.scr\0" \
122	"uimage=uImage\0" \	122	"uimage=uImage\0" \
123	"mmcdev=0\0" \	123	"mmcdev=0\0" \
124	"mmcpart=2\0" \	124	"mmcpart=2\0" \
125	"mmcroot=/dev/mmcblk0p3 rw\0" \	125	"mmcroot=/dev/mmcblk0p3 rw\0" \
126	"mmcrootfstype=ext3 rootwait\0" \	126	"mmcrootfstype=ext3 rootwait\0" \
127	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \	127	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
128	"root=${mmcroot} " \	128	"root=${mmcroot} " \
129	"rootfstype=${mmcrootfstype}\0" \	129	"rootfstype=${mmcrootfstype}\0" \
130	"loadbootscript=" \	130	"loadbootscript=" \
131	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \	131	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
132	"bootscript=echo Running bootscript from mmc ...; " \	132	"bootscript=echo Running bootscript from mmc ...; " \
133	"source\0" \	133	"source\0" \
134	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \	134	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
135	"mmcboot=echo Booting from mmc ...; " \	135	"mmcboot=echo Booting from mmc ...; " \
136	"run mmcargs; " \	136	"run mmcargs; " \
137	"bootm\0" \	137	"bootm\0" \
138	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \	138	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
139	"root=/dev/nfs " \	139	"root=/dev/nfs " \
140	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \	140	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
141	"netboot=echo Booting from net ...; " \	141	"netboot=echo Booting from net ...; " \
142	"run netargs; " \	142	"run netargs; " \
143	"dhcp ${uimage}; bootm\0" \	143	"dhcp ${uimage}; bootm\0" \
144		144
145	#define CONFIG_BOOTCOMMAND \	145	#define CONFIG_BOOTCOMMAND \
146	"if mmc rescan ${mmcdev}; then " \	146	"if mmc rescan ${mmcdev}; then " \
147	"if run loadbootscript; then " \	147	"if run loadbootscript; then " \
148	"run bootscript; " \	148	"run bootscript; " \
149	"else " \	149	"else " \
150	"if run loaduimage; then " \	150	"if run loaduimage; then " \
151	"run mmcboot; " \	151	"run mmcboot; " \
152	"else run netboot; " \	152	"else run netboot; " \
153	"fi; " \	153	"fi; " \
154	"fi; " \	154	"fi; " \
155	"else run netboot; fi"	155	"else run netboot; fi"
156		156
157	#define CONFIG_ARP_TIMEOUT 200UL	157	#define CONFIG_ARP_TIMEOUT 200UL
158		158
159	/* Miscellaneous configurable options */	159	/* Miscellaneous configurable options */
160	#define CONFIG_SYS_LONGHELP /* undef to save memory */	160	#define CONFIG_SYS_LONGHELP /* undef to save memory */
161	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */	161	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
162	#define CONFIG_SYS_PROMPT "MX53LOCO U-Boot > "	162	#define CONFIG_SYS_PROMPT "MX53LOCO U-Boot > "
163	#define CONFIG_AUTO_COMPLETE	163	#define CONFIG_AUTO_COMPLETE
164	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */	164	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
165		165
166	/* Print Buffer Size */	166	/* Print Buffer Size */
167	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	167	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
168	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */	168	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
169	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */	169	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
170		170
171	#define CONFIG_SYS_MEMTEST_START 0x70000000	171	#define CONFIG_SYS_MEMTEST_START 0x70000000
172	#define CONFIG_SYS_MEMTEST_END 0x70010000	172	#define CONFIG_SYS_MEMTEST_END 0x70010000
173		173
174	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR	174	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
175		175
176	#define CONFIG_SYS_HZ 1000	176	#define CONFIG_SYS_HZ 1000
177	#define CONFIG_CMDLINE_EDITING	177	#define CONFIG_CMDLINE_EDITING
178		178
179	/* Stack sizes */	179	/* Stack sizes */
180	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */	180	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
181		181
182	/* Physical Memory Map */	182	/* Physical Memory Map */
183	#define CONFIG_NR_DRAM_BANKS 2	183	#define CONFIG_NR_DRAM_BANKS 2
184	#define PHYS_SDRAM_1 CSD0_BASE_ADDR	184	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
185	#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)	185	#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
186	#define PHYS_SDRAM_2 CSD1_BASE_ADDR	186	#define PHYS_SDRAM_2 CSD1_BASE_ADDR
187	#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)	187	#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
188	#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)	188	#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
189		189
190	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)	190	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
191	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)	191	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
192	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)	192	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
193		193
194	#define CONFIG_SYS_INIT_SP_OFFSET \	194	#define CONFIG_SYS_INIT_SP_OFFSET \
195	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)	195	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
196	#define CONFIG_SYS_INIT_SP_ADDR \	196	#define CONFIG_SYS_INIT_SP_ADDR \
197	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)	197	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
198		198
199	/* FLASH and environment organization */	199	/* FLASH and environment organization */
200	#define CONFIG_SYS_NO_FLASH	200	#define CONFIG_SYS_NO_FLASH
201		201
202	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)	202	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
203	#define CONFIG_ENV_SIZE (8 * 1024)	203	#define CONFIG_ENV_SIZE (8 * 1024)
204	#define CONFIG_ENV_IS_IN_MMC	204	#define CONFIG_ENV_IS_IN_MMC
205	#define CONFIG_SYS_MMC_ENV_DEV 0	205	#define CONFIG_SYS_MMC_ENV_DEV 0
206		206
207	#define CONFIG_OF_LIBFDT	207	#define CONFIG_OF_LIBFDT
208		208
209	#define CONFIG_CMD_SATA	209	#define CONFIG_CMD_SATA
210	#ifdef CONFIG_CMD_SATA	210	#ifdef CONFIG_CMD_SATA
211	#define CONFIG_DWC_AHSATA	211	#define CONFIG_DWC_AHSATA
212	#define CONFIG_SYS_SATA_MAX_DEVICE 1	212	#define CONFIG_SYS_SATA_MAX_DEVICE 1
213	#define CONFIG_DWC_AHSATA_PORT_ID 0	213	#define CONFIG_DWC_AHSATA_PORT_ID 0
214	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR	214	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
215	#define CONFIG_LBA48	215	#define CONFIG_LBA48
216	#define CONFIG_LIBATA	216	#define CONFIG_LIBATA
217	#endif	217	#endif
218		218
219	/* Framebuffer and LCD */	219	/* Framebuffer and LCD */
220	#define CONFIG_PREBOOT	220	#define CONFIG_PREBOOT
221	#define CONFIG_VIDEO	221	#define CONFIG_VIDEO
222	#define CONFIG_VIDEO_MX5	222	#define CONFIG_VIDEO_MX5
223	#define CONFIG_CFB_CONSOLE	223	#define CONFIG_CFB_CONSOLE
224	#define CONFIG_VGA_AS_SINGLE_DEVICE	224	#define CONFIG_VGA_AS_SINGLE_DEVICE
225	#define CONFIG_VIDEO_BMP_RLE8	225	#define CONFIG_VIDEO_BMP_RLE8
226	#define CONFIG_SPLASH_SCREEN	226	#define CONFIG_SPLASH_SCREEN
227	#define CONFIG_BMP_16BPP	227	#define CONFIG_BMP_16BPP
228	#define CONFIG_VIDEO_LOGO	228	#define CONFIG_VIDEO_LOGO
229		229
230	#endif /* __CONFIG_H */	230	#endif /* __CONFIG_H */
231		231

include/configs/mx53smd.h

Diff comments View file @ de6f604

1	/*	1	/*
2	* Copyright (C) 2011 Freescale Semiconductor, Inc.	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
3	*	3	*
4	* Configuration settings for the MX53SMD Freescale board.	4	* Configuration settings for the MX53SMD Freescale board.
5	*	5	*
6	* This program is free software; you can redistribute it and/or	6	* This program is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU General Public License as	7	* modify it under the terms of the GNU General Public License as
8	* published by the Free Software Foundation; either version 2 of	8	* published by the Free Software Foundation; either version 2 of
9	* the License, or (at your option) any later version.	9	* the License, or (at your option) any later version.
10	*	10	*
11	* This program is distributed in the hope that it will be useful,	11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.	14	* GNU General Public License for more details.
15	*	15	*
16	* You should have received a copy of the GNU General Public License	16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software	17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19	* MA 02111-1307 USA	19	* MA 02111-1307 USA
20	*/	20	*/
21		21
22	#ifndef __CONFIG_H	22	#ifndef __CONFIG_H
23	#define __CONFIG_H	23	#define __CONFIG_H
24		24
25	#define CONFIG_MX53	25	#define CONFIG_MX53
26		26
27	#define CONFIG_SYS_MX5_HCLK 24000000	27	#define CONFIG_SYS_MX5_HCLK 24000000
28	#define CONFIG_SYS_MX5_CLK32 32768	28	#define CONFIG_SYS_MX5_CLK32 32768
29	#define CONFIG_DISPLAY_CPUINFO	29	#define CONFIG_DISPLAY_CPUINFO
30	#define CONFIG_DISPLAY_BOARDINFO	30	#define CONFIG_DISPLAY_BOARDINFO
31		31
32	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD	32	#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
33		33
34	#include <asm/arch/imx-regs.h>	34	#include <asm/arch/imx-regs.h>
35		35
36	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */	36	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
37	#define CONFIG_SETUP_MEMORY_TAGS	37	#define CONFIG_SETUP_MEMORY_TAGS
38	#define CONFIG_INITRD_TAG	38	#define CONFIG_INITRD_TAG
39		39
40	/* Size of malloc() pool */	40	/* Size of malloc() pool */
41	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)	41	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
42		42
43	#define CONFIG_BOARD_EARLY_INIT_F	43	#define CONFIG_BOARD_EARLY_INIT_F
44	#define CONFIG_MXC_GPIO	44	#define CONFIG_MXC_GPIO
45		45
46	#define CONFIG_MXC_UART	46	#define CONFIG_MXC_UART
47	#define CONFIG_MXC_UART_BASE UART1_BASE	47	#define CONFIG_MXC_UART_BASE UART1_BASE
48		48
49	/* I2C Configs */	49	/* I2C Configs */
50	#define CONFIG_CMD_I2C	50	#define CONFIG_CMD_I2C
51	#define CONFIG_HARD_I2C	51	#define CONFIG_HARD_I2C
52	#define CONFIG_I2C_MXC	52	#define CONFIG_I2C_MXC
53	#define CONFIG_SYS_I2C_MX53_PORT2	53	#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
54	#define CONFIG_SYS_I2C_SPEED 100000	54	#define CONFIG_SYS_I2C_SPEED 100000
55		55
56	/* MMC Configs */	56	/* MMC Configs */
57	#define CONFIG_FSL_ESDHC	57	#define CONFIG_FSL_ESDHC
58	#define CONFIG_SYS_FSL_ESDHC_ADDR 0	58	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
59	#define CONFIG_SYS_FSL_ESDHC_NUM 1	59	#define CONFIG_SYS_FSL_ESDHC_NUM 1
60		60
61	#define CONFIG_MMC	61	#define CONFIG_MMC
62	#define CONFIG_CMD_MMC	62	#define CONFIG_CMD_MMC
63	#define CONFIG_GENERIC_MMC	63	#define CONFIG_GENERIC_MMC
64	#define CONFIG_CMD_FAT	64	#define CONFIG_CMD_FAT
65	#define CONFIG_DOS_PARTITION	65	#define CONFIG_DOS_PARTITION
66		66
67	/* Eth Configs */	67	/* Eth Configs */
68	#define CONFIG_HAS_ETH1	68	#define CONFIG_HAS_ETH1
69	#define CONFIG_MII	69	#define CONFIG_MII
70	#define CONFIG_DISCOVER_PHY	70	#define CONFIG_DISCOVER_PHY
71		71
72	#define CONFIG_FEC_MXC	72	#define CONFIG_FEC_MXC
73	#define IMX_FEC_BASE FEC_BASE_ADDR	73	#define IMX_FEC_BASE FEC_BASE_ADDR
74	#define CONFIG_FEC_MXC_PHYADDR 0x1F	74	#define CONFIG_FEC_MXC_PHYADDR 0x1F
75		75
76	#define CONFIG_CMD_PING	76	#define CONFIG_CMD_PING
77	#define CONFIG_CMD_DHCP	77	#define CONFIG_CMD_DHCP
78	#define CONFIG_CMD_MII	78	#define CONFIG_CMD_MII
79	#define CONFIG_CMD_NET	79	#define CONFIG_CMD_NET
80		80
81	/* allow to overwrite serial and ethaddr */	81	/* allow to overwrite serial and ethaddr */
82	#define CONFIG_ENV_OVERWRITE	82	#define CONFIG_ENV_OVERWRITE
83	#define CONFIG_CONS_INDEX 1	83	#define CONFIG_CONS_INDEX 1
84	#define CONFIG_BAUDRATE 115200	84	#define CONFIG_BAUDRATE 115200
85		85
86	/* Command definition */	86	/* Command definition */
87	#include <config_cmd_default.h>	87	#include <config_cmd_default.h>
88		88
89	#undef CONFIG_CMD_IMLS	89	#undef CONFIG_CMD_IMLS
90		90
91	#define CONFIG_BOOTDELAY 3	91	#define CONFIG_BOOTDELAY 3
92		92
93	#define CONFIG_ETHPRIME "FEC0"	93	#define CONFIG_ETHPRIME "FEC0"
94		94
95	#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */	95	#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
96	#define CONFIG_SYS_TEXT_BASE 0x77800000	96	#define CONFIG_SYS_TEXT_BASE 0x77800000
97		97
98	#define CONFIG_EXTRA_ENV_SETTINGS \	98	#define CONFIG_EXTRA_ENV_SETTINGS \
99	"script=boot.scr\0" \	99	"script=boot.scr\0" \
100	"uimage=uImage\0" \	100	"uimage=uImage\0" \
101	"mmcdev=0\0" \	101	"mmcdev=0\0" \
102	"mmcpart=2\0" \	102	"mmcpart=2\0" \
103	"mmcroot=/dev/mmcblk0p3 rw\0" \	103	"mmcroot=/dev/mmcblk0p3 rw\0" \
104	"mmcrootfstype=ext3 rootwait\0" \	104	"mmcrootfstype=ext3 rootwait\0" \
105	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \	105	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
106	"root=${mmcroot} " \	106	"root=${mmcroot} " \
107	"rootfstype=${mmcrootfstype}\0" \	107	"rootfstype=${mmcrootfstype}\0" \
108	"loadbootscript=" \	108	"loadbootscript=" \
109	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \	109	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
110	"bootscript=echo Running bootscript from mmc ...; " \	110	"bootscript=echo Running bootscript from mmc ...; " \
111	"source\0" \	111	"source\0" \
112	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \	112	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
113	"mmcboot=echo Booting from mmc ...; " \	113	"mmcboot=echo Booting from mmc ...; " \
114	"run mmcargs; " \	114	"run mmcargs; " \
115	"bootm\0" \	115	"bootm\0" \
116	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \	116	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
117	"root=/dev/nfs " \	117	"root=/dev/nfs " \
118	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \	118	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
119	"netboot=echo Booting from net ...; " \	119	"netboot=echo Booting from net ...; " \
120	"run netargs; " \	120	"run netargs; " \
121	"dhcp ${uimage}; bootm\0" \	121	"dhcp ${uimage}; bootm\0" \
122		122
123	#define CONFIG_BOOTCOMMAND \	123	#define CONFIG_BOOTCOMMAND \
124	"if mmc rescan ${mmcdev}; then " \	124	"if mmc rescan ${mmcdev}; then " \
125	"if run loadbootscript; then " \	125	"if run loadbootscript; then " \
126	"run bootscript; " \	126	"run bootscript; " \
127	"else " \	127	"else " \
128	"if run loaduimage; then " \	128	"if run loaduimage; then " \
129	"run mmcboot; " \	129	"run mmcboot; " \
130	"else run netboot; " \	130	"else run netboot; " \
131	"fi; " \	131	"fi; " \
132	"fi; " \	132	"fi; " \
133	"else run netboot; fi"	133	"else run netboot; fi"
134	#define CONFIG_ARP_TIMEOUT 200UL	134	#define CONFIG_ARP_TIMEOUT 200UL
135		135
136	/* Miscellaneous configurable options */	136	/* Miscellaneous configurable options */
137	#define CONFIG_SYS_LONGHELP /* undef to save memory */	137	#define CONFIG_SYS_LONGHELP /* undef to save memory */
138	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */	138	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
139	#define CONFIG_SYS_PROMPT "MX53SMD U-Boot > "	139	#define CONFIG_SYS_PROMPT "MX53SMD U-Boot > "
140	#define CONFIG_AUTO_COMPLETE	140	#define CONFIG_AUTO_COMPLETE
141	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */	141	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
142		142
143	/* Print Buffer Size */	143	/* Print Buffer Size */
144	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	144	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
145	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */	145	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */	146	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
147		147
148	#define CONFIG_SYS_MEMTEST_START 0x70000000	148	#define CONFIG_SYS_MEMTEST_START 0x70000000
149	#define CONFIG_SYS_MEMTEST_END 0x70010000	149	#define CONFIG_SYS_MEMTEST_END 0x70010000
150		150
151	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR	151	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
152		152
153	#define CONFIG_SYS_HZ 1000	153	#define CONFIG_SYS_HZ 1000
154	#define CONFIG_CMDLINE_EDITING	154	#define CONFIG_CMDLINE_EDITING
155		155
156	/* Stack sizes */	156	/* Stack sizes */
157	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */	157	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
158		158
159	/* Physical Memory Map */	159	/* Physical Memory Map */
160	#define CONFIG_NR_DRAM_BANKS 2	160	#define CONFIG_NR_DRAM_BANKS 2
161	#define PHYS_SDRAM_1 CSD0_BASE_ADDR	161	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
162	#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)	162	#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
163	#define PHYS_SDRAM_2 CSD1_BASE_ADDR	163	#define PHYS_SDRAM_2 CSD1_BASE_ADDR
164	#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)	164	#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
165	#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)	165	#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
166		166
167	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)	167	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
168	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)	168	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
169	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)	169	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
170		170
171	#define CONFIG_SYS_INIT_SP_OFFSET \	171	#define CONFIG_SYS_INIT_SP_OFFSET \
172	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)	172	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
173	#define CONFIG_SYS_INIT_SP_ADDR \	173	#define CONFIG_SYS_INIT_SP_ADDR \
174	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)	174	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
175		175
176	/* FLASH and environment organization */	176	/* FLASH and environment organization */
177	#define CONFIG_SYS_NO_FLASH	177	#define CONFIG_SYS_NO_FLASH
178		178
179	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)	179	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
180	#define CONFIG_ENV_SIZE (8 * 1024)	180	#define CONFIG_ENV_SIZE (8 * 1024)
181	#define CONFIG_ENV_IS_IN_MMC	181	#define CONFIG_ENV_IS_IN_MMC
182	#define CONFIG_SYS_MMC_ENV_DEV 0	182	#define CONFIG_SYS_MMC_ENV_DEV 0
183		183
184	#define CONFIG_OF_LIBFDT	184	#define CONFIG_OF_LIBFDT
185		185
186	#endif /* __CONFIG_H */	186	#endif /* __CONFIG_H */
187		187

1	/*	1	/*
2	* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>	2	* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
3	*	3	*
4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.	4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5	*	5	*
6	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>	6	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
7	*	7	*
8	* Configuration for the flea3 board.	8	* Configuration for the flea3 board.
9	*	9	*
10	* This program is free software; you can redistribute it and/or	10	* This program is free software; you can redistribute it and/or
11	* modify it under the terms of the GNU General Public License as	11	* modify it under the terms of the GNU General Public License as
12	* published by the Free Software Foundation; either version 2 of	12	* published by the Free Software Foundation; either version 2 of
13	* the License, or (at your option) any later version.	13	* the License, or (at your option) any later version.
14	*	14	*
15	* This program is distributed in the hope that it will be useful,	15	* This program is distributed in the hope that it will be useful,
16	* but WITHOUT ANY WARRANTY; without even the implied warranty of	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18	* GNU General Public License for more details.	18	* GNU General Public License for more details.
19	*	19	*
20	* You should have received a copy of the GNU General Public License	20	* You should have received a copy of the GNU General Public License
21	* along with this program; if not, write to the Free Software	21	* along with this program; if not, write to the Free Software
22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23	* MA 02111-1307 USA	23	* MA 02111-1307 USA
24	*/	24	*/
25		25
26	#ifndef __CONFIG_H	26	#ifndef __CONFIG_H
27	#define __CONFIG_H	27	#define __CONFIG_H
28		28
29	#include <asm/arch/imx-regs.h>	29	#include <asm/arch/imx-regs.h>
30		30
31	/* High Level Configuration Options */	31	/* High Level Configuration Options */
32	#define CONFIG_ARM1136 /* This is an arm1136 CPU core */	32	#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
33	#define CONFIG_MX35	33	#define CONFIG_MX35
34	#define CONFIG_MX35_HCLK_FREQ 24000000	34	#define CONFIG_MX35_HCLK_FREQ 24000000
35		35
36	#define CONFIG_SYS_DCACHE_OFF	36	#define CONFIG_SYS_DCACHE_OFF
37	#define CONFIG_SYS_CACHELINE_SIZE 32	37	#define CONFIG_SYS_CACHELINE_SIZE 32
38		38
39	#define CONFIG_DISPLAY_CPUINFO	39	#define CONFIG_DISPLAY_CPUINFO
40		40
41	/* Only in case the value is not present in mach-types.h */	41	/* Only in case the value is not present in mach-types.h */
42	#ifndef MACH_TYPE_FLEA3	42	#ifndef MACH_TYPE_FLEA3
43	#define MACH_TYPE_FLEA3 3668	43	#define MACH_TYPE_FLEA3 3668
44	#endif	44	#endif
45		45
46	#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3	46	#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
47		47
48	/* Set TEXT at the beginning of the NOR flash */	48	/* Set TEXT at the beginning of the NOR flash */
49	#define CONFIG_SYS_TEXT_BASE 0xA0000000	49	#define CONFIG_SYS_TEXT_BASE 0xA0000000
50		50
51	/* This is required to setup the ESDC controller */	51	/* This is required to setup the ESDC controller */
52	#define CONFIG_BOARD_EARLY_INIT_F	52	#define CONFIG_BOARD_EARLY_INIT_F
53		53
54	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */	54	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
55	#define CONFIG_REVISION_TAG	55	#define CONFIG_REVISION_TAG
56	#define CONFIG_SETUP_MEMORY_TAGS	56	#define CONFIG_SETUP_MEMORY_TAGS
57	#define CONFIG_INITRD_TAG	57	#define CONFIG_INITRD_TAG
58		58
59	/*	59	/*
60	* Size of malloc() pool	60	* Size of malloc() pool
61	*/	61	*/
62	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)	62	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
63		63
64	/*	64	/*
65	* Hardware drivers	65	* Hardware drivers
66	*/	66	*/
67	#define CONFIG_HARD_I2C	67	#define CONFIG_HARD_I2C
68	#define CONFIG_I2C_MXC	68	#define CONFIG_I2C_MXC
69	#define CONFIG_SYS_I2C_MX35_PORT3	69	#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
70	#define CONFIG_SYS_I2C_SPEED 100000	70	#define CONFIG_SYS_I2C_SPEED 100000
71	#define CONFIG_SYS_I2C_SLAVE 0xfe	71	#define CONFIG_SYS_I2C_SLAVE 0xfe
72	#define CONFIG_MXC_SPI	72	#define CONFIG_MXC_SPI
73	#define CONFIG_MXC_GPIO	73	#define CONFIG_MXC_GPIO
74		74
75	/*	75	/*
76	* UART (console)	76	* UART (console)
77	*/	77	*/
78	#define CONFIG_MXC_UART	78	#define CONFIG_MXC_UART
79	#define CONFIG_MXC_UART_BASE UART3_BASE	79	#define CONFIG_MXC_UART_BASE UART3_BASE
80		80
81	/* allow to overwrite serial and ethaddr */	81	/* allow to overwrite serial and ethaddr */
82	#define CONFIG_ENV_OVERWRITE	82	#define CONFIG_ENV_OVERWRITE
83	#define CONFIG_CONS_INDEX 1	83	#define CONFIG_CONS_INDEX 1
84	#define CONFIG_BAUDRATE 115200	84	#define CONFIG_BAUDRATE 115200
85		85
86	/*	86	/*
87	* Command definition	87	* Command definition
88	*/	88	*/
89		89
90	#include <config_cmd_default.h>	90	#include <config_cmd_default.h>
91		91
92	#define CONFIG_CMD_PING	92	#define CONFIG_CMD_PING
93	#define CONFIG_CMD_DHCP	93	#define CONFIG_CMD_DHCP
94	#define CONFIG_BOOTP_SUBNETMASK	94	#define CONFIG_BOOTP_SUBNETMASK
95	#define CONFIG_BOOTP_GATEWAY	95	#define CONFIG_BOOTP_GATEWAY
96	#define CONFIG_BOOTP_DNS	96	#define CONFIG_BOOTP_DNS
97		97
98	#define CONFIG_CMD_NAND	98	#define CONFIG_CMD_NAND
99	#define CONFIG_CMD_CACHE	99	#define CONFIG_CMD_CACHE
100		100
101	#define CONFIG_CMD_I2C	101	#define CONFIG_CMD_I2C
102	#define CONFIG_CMD_SPI	102	#define CONFIG_CMD_SPI
103	#define CONFIG_CMD_MII	103	#define CONFIG_CMD_MII
104	#define CONFIG_CMD_NET	104	#define CONFIG_CMD_NET
105	#define CONFIG_NET_RETRY_COUNT 100	105	#define CONFIG_NET_RETRY_COUNT 100
106		106
107	#define CONFIG_BOOTDELAY 3	107	#define CONFIG_BOOTDELAY 3
108		108
109	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */	109	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
110		110
111		111
112	/*	112	/*
113	* Ethernet on SOC (FEC)	113	* Ethernet on SOC (FEC)
114	*/	114	*/
115	#define CONFIG_FEC_MXC	115	#define CONFIG_FEC_MXC
116	#define IMX_FEC_BASE FEC_BASE_ADDR	116	#define IMX_FEC_BASE FEC_BASE_ADDR
117	#define CONFIG_PHYLIB	117	#define CONFIG_PHYLIB
118	#define CONFIG_PHY_MICREL	118	#define CONFIG_PHY_MICREL
119	#define CONFIG_FEC_MXC_PHYADDR 0x1	119	#define CONFIG_FEC_MXC_PHYADDR 0x1
120		120
121	#define CONFIG_MII	121	#define CONFIG_MII
122	#define CONFIG_DISCOVER_PHY	122	#define CONFIG_DISCOVER_PHY
123		123
124	#define CONFIG_ARP_TIMEOUT 200UL	124	#define CONFIG_ARP_TIMEOUT 200UL
125		125
126	/*	126	/*
127	* Miscellaneous configurable options	127	* Miscellaneous configurable options
128	*/	128	*/
129	#define CONFIG_SYS_LONGHELP /* undef to save memory */	129	#define CONFIG_SYS_LONGHELP /* undef to save memory */
130	#define CONFIG_SYS_PROMPT "flea3 U-Boot > "	130	#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
131	#define CONFIG_CMDLINE_EDITING	131	#define CONFIG_CMDLINE_EDITING
132	#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */	132	#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
133		133
134	#define CONFIG_AUTO_COMPLETE	134	#define CONFIG_AUTO_COMPLETE
135	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */	135	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
136	/* Print Buffer Size */	136	/* Print Buffer Size */
137	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	137	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
138	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */	138	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
139	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */	139	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
140		140
141	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */	141	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
142	#define CONFIG_SYS_MEMTEST_END 0x10000	142	#define CONFIG_SYS_MEMTEST_END 0x10000
143		143
144	#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */	144	#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
145		145
146	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR	146	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
147		147
148	#define CONFIG_SYS_HZ 1000	148	#define CONFIG_SYS_HZ 1000
149		149
150		150
151	/*	151	/*
152	* Stack sizes	152	* Stack sizes
153	*	153	*
154	* The stack sizes are set up in start.S using the settings below	154	* The stack sizes are set up in start.S using the settings below
155	*/	155	*/
156	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */	156	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
157		157
158	/*	158	/*
159	* Physical Memory Map	159	* Physical Memory Map
160	*/	160	*/
161	#define CONFIG_NR_DRAM_BANKS 1	161	#define CONFIG_NR_DRAM_BANKS 1
162	#define PHYS_SDRAM_1 CSD0_BASE_ADDR	162	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
163	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)	163	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
164		164
165	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR	165	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
166	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)	166	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
167	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)	167	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
168	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \	168	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
169	GENERATED_GBL_DATA_SIZE)	169	GENERATED_GBL_DATA_SIZE)
170	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \	170	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
171	CONFIG_SYS_GBL_DATA_OFFSET)	171	CONFIG_SYS_GBL_DATA_OFFSET)
172		172
173	/*	173	/*
174	* MTD Command for mtdparts	174	* MTD Command for mtdparts
175	*/	175	*/
176	#define CONFIG_CMD_MTDPARTS	176	#define CONFIG_CMD_MTDPARTS
177	#define CONFIG_MTD_DEVICE	177	#define CONFIG_MTD_DEVICE
178	#define CONFIG_FLASH_CFI_MTD	178	#define CONFIG_FLASH_CFI_MTD
179	#define CONFIG_MTD_PARTITIONS	179	#define CONFIG_MTD_PARTITIONS
180	#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"	180	#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
181	#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \	181	#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \
182	"32m(rootfb)," \	182	"32m(rootfb)," \
183	"64m(pcache)," \	183	"64m(pcache)," \
184	"64m(app1)," \	184	"64m(app1)," \
185	"10m(app2),-(spool);" \	185	"10m(app2),-(spool);" \
186	"physmap-flash.0:512k(u-boot),64k(env1)," \	186	"physmap-flash.0:512k(u-boot),64k(env1)," \
187	"64k(env2),3776k(kernel1),3776k(kernel2)"	187	"64k(env2),3776k(kernel1),3776k(kernel2)"
188		188
189	/*	189	/*
190	* FLASH and environment organization	190	* FLASH and environment organization
191	*/	191	*/
192	#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR	192	#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
193	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */	193	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
194	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */	194	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
195	/* Monitor at beginning of flash */	195	/* Monitor at beginning of flash */
196	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE	196	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
197	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)	197	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
198		198
199	#define CONFIG_ENV_SECT_SIZE (64 * 1024)	199	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
200	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE	200	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
201		201
202	/* Address and size of Redundant Environment Sector */	202	/* Address and size of Redundant Environment Sector */
203	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)	203	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
204	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE	204	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
205		205
206	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \	206	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
207	CONFIG_SYS_MONITOR_LEN)	207	CONFIG_SYS_MONITOR_LEN)
208		208
209	#define CONFIG_ENV_IS_IN_FLASH	209	#define CONFIG_ENV_IS_IN_FLASH
210		210
211	/*	211	/*
212	* CFI FLASH driver setup	212	* CFI FLASH driver setup
213	*/	213	*/
214	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */	214	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
215	#define CONFIG_FLASH_CFI_DRIVER	215	#define CONFIG_FLASH_CFI_DRIVER
216		216
217	/* A non-standard buffered write algorithm */	217	/* A non-standard buffered write algorithm */
218	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */	218	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
219	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */	219	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
220		220
221	/*	221	/*
222	* NAND FLASH driver setup	222	* NAND FLASH driver setup
223	*/	223	*/
224	#define CONFIG_NAND_MXC	224	#define CONFIG_NAND_MXC
225	#define CONFIG_NAND_MXC_V1_1	225	#define CONFIG_NAND_MXC_V1_1
226	#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)	226	#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
227	#define CONFIG_SYS_MAX_NAND_DEVICE 1	227	#define CONFIG_SYS_MAX_NAND_DEVICE 1
228	#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)	228	#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
229	#define CONFIG_MXC_NAND_HWECC	229	#define CONFIG_MXC_NAND_HWECC
230	#define CONFIG_SYS_NAND_LARGEPAGE	230	#define CONFIG_SYS_NAND_LARGEPAGE
231		231
232	/*	232	/*
233	* Default environment and default scripts	233	* Default environment and default scripts
234	* to update uboot and load kernel	234	* to update uboot and load kernel
235	*/	235	*/
236	#define xstr(s) str(s)	236	#define xstr(s) str(s)
237	#define str(s) #s	237	#define str(s) #s
238		238
239	#define CONFIG_HOSTNAME flea3	239	#define CONFIG_HOSTNAME flea3
240	#define CONFIG_EXTRA_ENV_SETTINGS \	240	#define CONFIG_EXTRA_ENV_SETTINGS \
241	"netdev=eth0\0" \	241	"netdev=eth0\0" \
242	"nfsargs=setenv bootargs root=/dev/nfs rw " \	242	"nfsargs=setenv bootargs root=/dev/nfs rw " \
243	"nfsroot=${serverip}:${rootpath}\0" \	243	"nfsroot=${serverip}:${rootpath}\0" \
244	"ramargs=setenv bootargs root=/dev/ram rw\0" \	244	"ramargs=setenv bootargs root=/dev/ram rw\0" \
245	"addip_sta=setenv bootargs ${bootargs} " \	245	"addip_sta=setenv bootargs ${bootargs} " \
246	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \	246	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
247	":${hostname}:${netdev}:off panic=1\0" \	247	":${hostname}:${netdev}:off panic=1\0" \
248	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \	248	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
249	"addip=if test -n ${ipdyn};then run addip_dyn;" \	249	"addip=if test -n ${ipdyn};then run addip_dyn;" \
250	"else run addip_sta;fi\0" \	250	"else run addip_sta;fi\0" \
251	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \	251	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
252	"addtty=setenv bootargs ${bootargs}" \	252	"addtty=setenv bootargs ${bootargs}" \
253	" console=ttymxc2,${baudrate}\0" \	253	" console=ttymxc2,${baudrate}\0" \
254	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \	254	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
255	"loadaddr=80800000\0" \	255	"loadaddr=80800000\0" \
256	"kernel_addr_r=80800000\0" \	256	"kernel_addr_r=80800000\0" \
257	"hostname=" xstr(CONFIG_HOSTNAME) "\0" \	257	"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
258	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \	258	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
259	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \	259	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
260	"flash_self=run ramargs addip addtty addmtd addmisc;" \	260	"flash_self=run ramargs addip addtty addmtd addmisc;" \
261	"bootm ${kernel_addr} ${ramdisk_addr}\0" \	261	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
262	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \	262	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
263	"bootm ${kernel_addr}\0" \	263	"bootm ${kernel_addr}\0" \
264	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \	264	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
265	"run nfsargs addip addtty addmtd addmisc;" \	265	"run nfsargs addip addtty addmtd addmisc;" \
266	"bootm ${kernel_addr_r}\0" \	266	"bootm ${kernel_addr_r}\0" \
267	"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \	267	"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
268	"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \	268	"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
269	"net_self=if run net_self_load;then " \	269	"net_self=if run net_self_load;then " \
270	"run ramargs addip addtty addmtd addmisc;" \	270	"run ramargs addip addtty addmtd addmisc;" \
271	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \	271	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
272	"else echo Images not loades;fi\0" \	272	"else echo Images not loades;fi\0" \
273	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \	273	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
274	"load=tftp ${loadaddr} ${u-boot}\0" \	274	"load=tftp ${loadaddr} ${u-boot}\0" \
275	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \	275	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
276	"update=protect off ${uboot_addr} +40000;" \	276	"update=protect off ${uboot_addr} +40000;" \
277	"erase ${uboot_addr} +40000;" \	277	"erase ${uboot_addr} +40000;" \
278	"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \	278	"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
279	"upd=if run load;then echo Updating u-boot;if run update;" \	279	"upd=if run load;then echo Updating u-boot;if run update;" \
280	"then echo U-Boot updated;" \	280	"then echo U-Boot updated;" \
281	"else echo Error updating u-boot !;" \	281	"else echo Error updating u-boot !;" \
282	"echo Board without bootloader !!;" \	282	"echo Board without bootloader !!;" \
283	"fi;" \	283	"fi;" \
284	"else echo U-Boot not downloaded..exiting;fi\0" \	284	"else echo U-Boot not downloaded..exiting;fi\0" \
285	"bootcmd=run net_nfs\0"	285	"bootcmd=run net_nfs\0"
286		286
287	#endif /* __CONFIG_H */	287	#endif /* __CONFIG_H */
288		288

1	/*	1	/*
2	* (C) Copyright 2010, Stefano Babic <sbabic@denx.de>	2	* (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
3	*	3	*
4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.	4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5	*	5	*
6	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>	6	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
7	*	7	*
8	* Configuration for the MX35pdk Freescale board.	8	* Configuration for the MX35pdk Freescale board.
9	*	9	*
10	* This program is free software; you can redistribute it and/or	10	* This program is free software; you can redistribute it and/or
11	* modify it under the terms of the GNU General Public License as	11	* modify it under the terms of the GNU General Public License as
12	* published by the Free Software Foundation; either version 2 of	12	* published by the Free Software Foundation; either version 2 of
13	* the License, or (at your option) any later version.	13	* the License, or (at your option) any later version.
14	*	14	*
15	* This program is distributed in the hope that it will be useful,	15	* This program is distributed in the hope that it will be useful,
16	* but WITHOUT ANY WARRANTY; without even the implied warranty of	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18	* GNU General Public License for more details.	18	* GNU General Public License for more details.
19	*	19	*
20	* You should have received a copy of the GNU General Public License	20	* You should have received a copy of the GNU General Public License
21	* along with this program; if not, write to the Free Software	21	* along with this program; if not, write to the Free Software
22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23	* MA 02111-1307 USA	23	* MA 02111-1307 USA
24	*/	24	*/
25		25
26	#ifndef __CONFIG_H	26	#ifndef __CONFIG_H
27	#define __CONFIG_H	27	#define __CONFIG_H
28		28
29	#include <asm/arch/imx-regs.h>	29	#include <asm/arch/imx-regs.h>
30		30
31	/* High Level Configuration Options */	31	/* High Level Configuration Options */
32	#define CONFIG_ARM1136 /* This is an arm1136 CPU core */	32	#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
33	#define CONFIG_MX35	33	#define CONFIG_MX35
34	#define CONFIG_MX35_HCLK_FREQ 24000000	34	#define CONFIG_MX35_HCLK_FREQ 24000000
35		35
36	#define CONFIG_DISPLAY_CPUINFO	36	#define CONFIG_DISPLAY_CPUINFO
37		37
38	/* Set TEXT at the beginning of the NOR flash */	38	/* Set TEXT at the beginning of the NOR flash */
39	#define CONFIG_SYS_TEXT_BASE 0xA0000000	39	#define CONFIG_SYS_TEXT_BASE 0xA0000000
40	#define CONFIG_SYS_CACHELINE_SIZE 32	40	#define CONFIG_SYS_CACHELINE_SIZE 32
41		41
42	#define CONFIG_BOARD_EARLY_INIT_F	42	#define CONFIG_BOARD_EARLY_INIT_F
43	#define CONFIG_BOARD_LATE_INIT	43	#define CONFIG_BOARD_LATE_INIT
44		44
45	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */	45	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
46	#define CONFIG_REVISION_TAG	46	#define CONFIG_REVISION_TAG
47	#define CONFIG_SETUP_MEMORY_TAGS	47	#define CONFIG_SETUP_MEMORY_TAGS
48	#define CONFIG_INITRD_TAG	48	#define CONFIG_INITRD_TAG
49		49
50	/*	50	/*
51	* Size of malloc() pool	51	* Size of malloc() pool
52	*/	52	*/
53	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)	53	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
54		54
55	/*	55	/*
56	* Hardware drivers	56	* Hardware drivers
57	*/	57	*/
58	#define CONFIG_HARD_I2C	58	#define CONFIG_HARD_I2C
59	#define CONFIG_I2C_MXC	59	#define CONFIG_I2C_MXC
60	#define CONFIG_SYS_I2C_MX35_PORT1	60	#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
61	#define CONFIG_SYS_I2C_SPEED 100000	61	#define CONFIG_SYS_I2C_SPEED 100000
62	#define CONFIG_MXC_SPI	62	#define CONFIG_MXC_SPI
63	#define CONFIG_MXC_GPIO	63	#define CONFIG_MXC_GPIO
64		64
65		65
66	/*	66	/*
67	* PMIC Configs	67	* PMIC Configs
68	*/	68	*/
69	#define CONFIG_PMIC	69	#define CONFIG_PMIC
70	#define CONFIG_PMIC_I2C	70	#define CONFIG_PMIC_I2C
71	#define CONFIG_PMIC_FSL	71	#define CONFIG_PMIC_FSL
72	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08	72	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
73	#define CONFIG_RTC_MC13XXX	73	#define CONFIG_RTC_MC13XXX
74		74
75	/*	75	/*
76	* MFD MC9SDZ60	76	* MFD MC9SDZ60
77	*/	77	*/
78	#define CONFIG_FSL_MC9SDZ60	78	#define CONFIG_FSL_MC9SDZ60
79	#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69	79	#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
80		80
81	/*	81	/*
82	* UART (console)	82	* UART (console)
83	*/	83	*/
84	#define CONFIG_MXC_UART	84	#define CONFIG_MXC_UART
85	#define CONFIG_MXC_UART_BASE UART1_BASE	85	#define CONFIG_MXC_UART_BASE UART1_BASE
86		86
87	/* allow to overwrite serial and ethaddr */	87	/* allow to overwrite serial and ethaddr */
88	#define CONFIG_ENV_OVERWRITE	88	#define CONFIG_ENV_OVERWRITE
89	#define CONFIG_CONS_INDEX 1	89	#define CONFIG_CONS_INDEX 1
90	#define CONFIG_BAUDRATE 115200	90	#define CONFIG_BAUDRATE 115200
91		91
92	/*	92	/*
93	* Command definition	93	* Command definition
94	*/	94	*/
95		95
96	#include <config_cmd_default.h>	96	#include <config_cmd_default.h>
97		97
98	#define CONFIG_CMD_PING	98	#define CONFIG_CMD_PING
99	#define CONFIG_CMD_DHCP	99	#define CONFIG_CMD_DHCP
100	#define CONFIG_BOOTP_SUBNETMASK	100	#define CONFIG_BOOTP_SUBNETMASK
101	#define CONFIG_BOOTP_GATEWAY	101	#define CONFIG_BOOTP_GATEWAY
102	#define CONFIG_BOOTP_DNS	102	#define CONFIG_BOOTP_DNS
103		103
104	#define CONFIG_CMD_NAND	104	#define CONFIG_CMD_NAND
105	#define CONFIG_CMD_CACHE	105	#define CONFIG_CMD_CACHE
106		106
107	#define CONFIG_CMD_I2C	107	#define CONFIG_CMD_I2C
108	#define CONFIG_CMD_SPI	108	#define CONFIG_CMD_SPI
109	#define CONFIG_CMD_MII	109	#define CONFIG_CMD_MII
110	#define CONFIG_CMD_NET	110	#define CONFIG_CMD_NET
111	#define CONFIG_NET_RETRY_COUNT 100	111	#define CONFIG_NET_RETRY_COUNT 100
112	#define CONFIG_CMD_DATE	112	#define CONFIG_CMD_DATE
113		113
114	#define CONFIG_BOOTDELAY 3	114	#define CONFIG_BOOTDELAY 3
115		115
116	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */	116	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
117		117
118	/*	118	/*
119	* Ethernet on the debug board (SMC911)	119	* Ethernet on the debug board (SMC911)
120	*/	120	*/
121	#define CONFIG_SMC911X	121	#define CONFIG_SMC911X
122	#define CONFIG_SMC911X_16_BIT 1	122	#define CONFIG_SMC911X_16_BIT 1
123	#define CONFIG_SMC911X_BASE CS5_BASE_ADDR	123	#define CONFIG_SMC911X_BASE CS5_BASE_ADDR
124		124
125	#define CONFIG_HAS_ETH1	125	#define CONFIG_HAS_ETH1
126	#define CONFIG_ETHPRIME	126	#define CONFIG_ETHPRIME
127		127
128	/*	128	/*
129	* Ethernet on SOC (FEC)	129	* Ethernet on SOC (FEC)
130	*/	130	*/
131	#define CONFIG_FEC_MXC	131	#define CONFIG_FEC_MXC
132	#define IMX_FEC_BASE FEC_BASE_ADDR	132	#define IMX_FEC_BASE FEC_BASE_ADDR
133	#define CONFIG_FEC_MXC_PHYADDR 0x1F	133	#define CONFIG_FEC_MXC_PHYADDR 0x1F
134		134
135	#define CONFIG_MII	135	#define CONFIG_MII
136	#define CONFIG_DISCOVER_PHY	136	#define CONFIG_DISCOVER_PHY
137		137
138	#define CONFIG_ARP_TIMEOUT 200UL	138	#define CONFIG_ARP_TIMEOUT 200UL
139		139
140	/*	140	/*
141	* Miscellaneous configurable options	141	* Miscellaneous configurable options
142	*/	142	*/
143	#define CONFIG_SYS_LONGHELP /* undef to save memory */	143	#define CONFIG_SYS_LONGHELP /* undef to save memory */
144	#define CONFIG_SYS_PROMPT "MX35 U-Boot > "	144	#define CONFIG_SYS_PROMPT "MX35 U-Boot > "
145	#define CONFIG_CMDLINE_EDITING	145	#define CONFIG_CMDLINE_EDITING
146	#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */	146	#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
147		147
148	#define CONFIG_AUTO_COMPLETE	148	#define CONFIG_AUTO_COMPLETE
149	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */	149	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
150	/* Print Buffer Size */	150	/* Print Buffer Size */
151	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	151	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
152	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */	152	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
153	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */	153	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
154		154
155	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */	155	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
156	#define CONFIG_SYS_MEMTEST_END 0x10000	156	#define CONFIG_SYS_MEMTEST_END 0x10000
157		157
158	#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */	158	#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
159		159
160	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR	160	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
161		161
162	#define CONFIG_SYS_HZ 1000	162	#define CONFIG_SYS_HZ 1000
163		163
164		164
165	/*	165	/*
166	* Stack sizes	166	* Stack sizes
167	*	167	*
168	* The stack sizes are set up in start.S using the settings below	168	* The stack sizes are set up in start.S using the settings below
169	*/	169	*/
170	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */	170	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
171		171
172	/*	172	/*
173	* Physical Memory Map	173	* Physical Memory Map
174	*/	174	*/
175	#define CONFIG_NR_DRAM_BANKS 2	175	#define CONFIG_NR_DRAM_BANKS 2
176	#define PHYS_SDRAM_1 CSD0_BASE_ADDR	176	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
177	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)	177	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
178	#define PHYS_SDRAM_2 CSD1_BASE_ADDR	178	#define PHYS_SDRAM_2 CSD1_BASE_ADDR
179	#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024)	179	#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024)
180		180
181	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR	181	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
182	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)	182	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
183	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)	183	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
184	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \	184	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
185	GENERATED_GBL_DATA_SIZE)	185	GENERATED_GBL_DATA_SIZE)
186	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \	186	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
187	CONFIG_SYS_GBL_DATA_OFFSET)	187	CONFIG_SYS_GBL_DATA_OFFSET)
188		188
189	/*	189	/*
190	* MTD Command for mtdparts	190	* MTD Command for mtdparts
191	*/	191	*/
192	#define CONFIG_CMD_MTDPARTS	192	#define CONFIG_CMD_MTDPARTS
193	#define CONFIG_MTD_DEVICE	193	#define CONFIG_MTD_DEVICE
194	#define CONFIG_FLASH_CFI_MTD	194	#define CONFIG_FLASH_CFI_MTD
195	#define CONFIG_MTD_PARTITIONS	195	#define CONFIG_MTD_PARTITIONS
196	#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"	196	#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
197	#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:1m(boot),5m(linux)," \	197	#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:1m(boot),5m(linux)," \
198	"96m(root),8m(cfg),1938m(user);" \	198	"96m(root),8m(cfg),1938m(user);" \
199	"physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"	199	"physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
200		200
201	/*	201	/*
202	* FLASH and environment organization	202	* FLASH and environment organization
203	*/	203	*/
204	#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR	204	#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
205	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */	205	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
206	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */	206	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
207	/* Monitor at beginning of flash */	207	/* Monitor at beginning of flash */
208	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE	208	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
209	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)	209	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
210		210
211	#define CONFIG_ENV_SECT_SIZE (128 * 1024)	211	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
212	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE	212	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
213		213
214	/* Address and size of Redundant Environment Sector */	214	/* Address and size of Redundant Environment Sector */
215	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)	215	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
216	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE	216	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
217		217
218	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \	218	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
219	CONFIG_SYS_MONITOR_LEN)	219	CONFIG_SYS_MONITOR_LEN)
220		220
221	#define CONFIG_ENV_IS_IN_FLASH	221	#define CONFIG_ENV_IS_IN_FLASH
222		222
223	#if defined(CONFIG_FSL_ENV_IN_NAND)	223	#if defined(CONFIG_FSL_ENV_IN_NAND)
224	#define CONFIG_ENV_IS_IN_NAND	224	#define CONFIG_ENV_IS_IN_NAND
225	#define CONFIG_ENV_OFFSET (1024 * 1024)	225	#define CONFIG_ENV_OFFSET (1024 * 1024)
226	#endif	226	#endif
227		227
228	/*	228	/*
229	* CFI FLASH driver setup	229	* CFI FLASH driver setup
230	*/	230	*/
231	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */	231	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
232	#define CONFIG_FLASH_CFI_DRIVER	232	#define CONFIG_FLASH_CFI_DRIVER
233		233
234	/* A non-standard buffered write algorithm */	234	/* A non-standard buffered write algorithm */
235	#define CONFIG_FLASH_SPANSION_S29WS_N	235	#define CONFIG_FLASH_SPANSION_S29WS_N
236	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */	236	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
237	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */	237	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
238		238
239	/*	239	/*
240	* NAND FLASH driver setup	240	* NAND FLASH driver setup
241	*/	241	*/
242	#define CONFIG_NAND_MXC	242	#define CONFIG_NAND_MXC
243	#define CONFIG_NAND_MXC_V1_1	243	#define CONFIG_NAND_MXC_V1_1
244	#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)	244	#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
245	#define CONFIG_SYS_MAX_NAND_DEVICE 1	245	#define CONFIG_SYS_MAX_NAND_DEVICE 1
246	#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)	246	#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
247	#define CONFIG_MXC_NAND_HWECC	247	#define CONFIG_MXC_NAND_HWECC
248	#define CONFIG_SYS_NAND_LARGEPAGE	248	#define CONFIG_SYS_NAND_LARGEPAGE
249		249
250	/*	250	/*
251	* Default environment and default scripts	251	* Default environment and default scripts
252	* to update uboot and load kernel	252	* to update uboot and load kernel
253	*/	253	*/
254	#define xstr(s) str(s)	254	#define xstr(s) str(s)
255	#define str(s) #s	255	#define str(s) #s
256		256
257	#define CONFIG_HOSTNAME "mx35pdk"	257	#define CONFIG_HOSTNAME "mx35pdk"
258	#define CONFIG_EXTRA_ENV_SETTINGS \	258	#define CONFIG_EXTRA_ENV_SETTINGS \
259	"netdev=eth1\0" \	259	"netdev=eth1\0" \
260	"ethprime=smc911x\0" \	260	"ethprime=smc911x\0" \
261	"nfsargs=setenv bootargs root=/dev/nfs rw " \	261	"nfsargs=setenv bootargs root=/dev/nfs rw " \
262	"nfsroot=${serverip}:${rootpath}\0" \	262	"nfsroot=${serverip}:${rootpath}\0" \
263	"ramargs=setenv bootargs root=/dev/ram rw\0" \	263	"ramargs=setenv bootargs root=/dev/ram rw\0" \
264	"addip_sta=setenv bootargs ${bootargs} " \	264	"addip_sta=setenv bootargs ${bootargs} " \
265	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \	265	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
266	":${hostname}:${netdev}:off panic=1\0" \	266	":${hostname}:${netdev}:off panic=1\0" \
267	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \	267	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
268	"addip=if test -n ${ipdyn};then run addip_dyn;" \	268	"addip=if test -n ${ipdyn};then run addip_dyn;" \
269	"else run addip_sta;fi\0" \	269	"else run addip_sta;fi\0" \
270	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \	270	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
271	"addtty=setenv bootargs ${bootargs}" \	271	"addtty=setenv bootargs ${bootargs}" \
272	" console=ttymxc0,${baudrate}\0" \	272	" console=ttymxc0,${baudrate}\0" \
273	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \	273	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
274	"loadaddr=80800000\0" \	274	"loadaddr=80800000\0" \
275	"kernel_addr_r=80800000\0" \	275	"kernel_addr_r=80800000\0" \
276	"hostname=" xstr(CONFIG_HOSTNAME) "\0" \	276	"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
277	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \	277	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
278	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \	278	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
279	"flash_self=run ramargs addip addtty addmtd addmisc;" \	279	"flash_self=run ramargs addip addtty addmtd addmisc;" \
280	"bootm ${kernel_addr} ${ramdisk_addr}\0" \	280	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
281	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \	281	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
282	"bootm ${kernel_addr}\0" \	282	"bootm ${kernel_addr}\0" \
283	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \	283	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
284	"run nfsargs addip addtty addmtd addmisc;" \	284	"run nfsargs addip addtty addmtd addmisc;" \
285	"bootm ${kernel_addr_r}\0" \	285	"bootm ${kernel_addr_r}\0" \
286	"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \	286	"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
287	"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \	287	"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
288	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \	288	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
289	"load=tftp ${loadaddr} ${u-boot}\0" \	289	"load=tftp ${loadaddr} ${u-boot}\0" \
290	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \	290	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
291	"update=protect off ${uboot_addr} +40000;" \	291	"update=protect off ${uboot_addr} +40000;" \
292	"erase ${uboot_addr} +40000;" \	292	"erase ${uboot_addr} +40000;" \
293	"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \	293	"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
294	"upd=if run load;then echo Updating u-boot;if run update;" \	294	"upd=if run load;then echo Updating u-boot;if run update;" \
295	"then echo U-Boot updated;" \	295	"then echo U-Boot updated;" \
296	"else echo Error updating u-boot !;" \	296	"else echo Error updating u-boot !;" \
297	"echo Board without bootloader !!;" \	297	"echo Board without bootloader !!;" \
298	"fi;" \	298	"fi;" \
299	"else echo U-Boot not downloaded..exiting;fi\0" \	299	"else echo U-Boot not downloaded..exiting;fi\0" \
300	"bootcmd=run net_nfs\0"	300	"bootcmd=run net_nfs\0"
301		301
302	#endif /* __CONFIG_H */	302	#endif /* __CONFIG_H */
303		303