Eric Lee / smarc-uboot

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Commit e37197acad30928b434c54842642b11ce5f3639b

Authored by Fabio Estevam
Committed by Stefano Babic
1 parent 44b9841d78
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ot1200: Fix error handling in board_mmc_init() 

When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Showing 1 changed file with 6 additions and 4 deletions Inline Diff

board/bachmann/ot1200/ot1200.c
Diff comments   View file @ e37197a
1 /* 1 /*
2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2014, Bachmann electronic GmbH 3 * Copyright (C) 2014, Bachmann electronic GmbH
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <asm/arch/clock.h> 9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h> 11 #include <asm/arch/iomux.h>
12 #include <malloc.h> 12 #include <malloc.h>
13 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/mx6-pins.h>
14 #include <asm/imx-common/iomux-v3.h> 14 #include <asm/imx-common/iomux-v3.h>
15 #include <asm/imx-common/sata.h> 15 #include <asm/imx-common/sata.h>
16 #include <asm/imx-common/mxc_i2c.h> 16 #include <asm/imx-common/mxc_i2c.h>
17 #include <asm/imx-common/boot_mode.h> 17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/arch/crm_regs.h> 18 #include <asm/arch/crm_regs.h>
19 #include <mmc.h> 19 #include <mmc.h>
20 #include <fsl_esdhc.h> 20 #include <fsl_esdhc.h>
21 #include <netdev.h> 21 #include <netdev.h>
22 #include <i2c.h> 22 #include <i2c.h>
23 #include <pca953x.h> 23 #include <pca953x.h>
24 #include <asm/gpio.h> 24 #include <asm/gpio.h>
25 #include <phy.h> 25 #include <phy.h>
26 26
27 DECLARE_GLOBAL_DATA_PTR; 27 DECLARE_GLOBAL_DATA_PTR;
28 28
29 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 29 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
30 30
31 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 31 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
32 OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 32 OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33 33
34 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 34 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
35 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 35 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
36 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 36 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37 37
38 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ 38 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
39 PAD_CTL_HYS) 39 PAD_CTL_HYS)
40 40
41 #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \ 41 #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
42 PAD_CTL_SRE_FAST) 42 PAD_CTL_SRE_FAST)
43 43
44 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ 44 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
45 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) 45 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
46 46
47 int dram_init(void) 47 int dram_init(void)
48 { 48 {
49 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 49 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
50 50
51 return 0; 51 return 0;
52 } 52 }
53 53
54 static iomux_v3_cfg_t const uart1_pads[] = { 54 static iomux_v3_cfg_t const uart1_pads[] = {
55 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 55 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
56 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 56 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
57 }; 57 };
58 58
59 static void setup_iomux_uart(void) 59 static void setup_iomux_uart(void)
60 { 60 {
61 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 61 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
62 } 62 }
63 63
64 static iomux_v3_cfg_t const enet_pads[] = { 64 static iomux_v3_cfg_t const enet_pads[] = {
65 MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), 65 MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), 66 MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 67 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 68 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 69 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 70 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 71 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 72 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 73 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 74 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 75 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 76 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 77 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 78 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 }; 82 };
83 83
84 static void setup_iomux_enet(void) 84 static void setup_iomux_enet(void)
85 { 85 {
86 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 86 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
87 } 87 }
88 88
89 static iomux_v3_cfg_t const ecspi1_pads[] = { 89 static iomux_v3_cfg_t const ecspi1_pads[] = {
90 MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL), 90 MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
91 MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL), 91 MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
92 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 92 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
93 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 93 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
94 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 94 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
95 }; 95 };
96 96
97 static void setup_iomux_spi(void) 97 static void setup_iomux_spi(void)
98 { 98 {
99 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 99 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
100 } 100 }
101 101
102 int board_spi_cs_gpio(unsigned bus, unsigned cs) 102 int board_spi_cs_gpio(unsigned bus, unsigned cs)
103 { 103 {
104 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1; 104 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
105 } 105 }
106 106
107 static iomux_v3_cfg_t const feature_pads[] = { 107 static iomux_v3_cfg_t const feature_pads[] = {
108 /* SD card detect */ 108 /* SD card detect */
109 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN), 109 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
110 110
111 /* eMMC soldered? */ 111 /* eMMC soldered? */
112 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP), 112 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
113 }; 113 };
114 114
115 static void setup_iomux_features(void) 115 static void setup_iomux_features(void)
116 { 116 {
117 imx_iomux_v3_setup_multiple_pads(feature_pads, 117 imx_iomux_v3_setup_multiple_pads(feature_pads,
118 ARRAY_SIZE(feature_pads)); 118 ARRAY_SIZE(feature_pads));
119 } 119 }
120 120
121 int board_early_init_f(void) 121 int board_early_init_f(void)
122 { 122 {
123 setup_iomux_uart(); 123 setup_iomux_uart();
124 setup_iomux_spi(); 124 setup_iomux_spi();
125 setup_iomux_features(); 125 setup_iomux_features();
126 126
127 return 0; 127 return 0;
128 } 128 }
129 129
130 static iomux_v3_cfg_t const usdhc3_pads[] = { 130 static iomux_v3_cfg_t const usdhc3_pads[] = {
131 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), 141 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 }; 142 };
143 143
144 iomux_v3_cfg_t const usdhc4_pads[] = { 144 iomux_v3_cfg_t const usdhc4_pads[] = {
145 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 145 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 146 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 147 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 148 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 149 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 150 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 }; 151 };
152 152
153 int board_mmc_getcd(struct mmc *mmc) 153 int board_mmc_getcd(struct mmc *mmc)
154 { 154 {
155 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 155 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
156 int ret; 156 int ret;
157 157
158 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 158 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
159 gpio_direction_input(IMX_GPIO_NR(4, 5)); 159 gpio_direction_input(IMX_GPIO_NR(4, 5));
160 ret = gpio_get_value(IMX_GPIO_NR(4, 5)); 160 ret = gpio_get_value(IMX_GPIO_NR(4, 5));
161 } else { 161 } else {
162 gpio_direction_input(IMX_GPIO_NR(1, 5)); 162 gpio_direction_input(IMX_GPIO_NR(1, 5));
163 ret = !gpio_get_value(IMX_GPIO_NR(1, 5)); 163 ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
164 } 164 }
165 165
166 return ret; 166 return ret;
167 } 167 }
168 168
169 struct fsl_esdhc_cfg usdhc_cfg[2] = { 169 struct fsl_esdhc_cfg usdhc_cfg[2] = {
170 {USDHC3_BASE_ADDR}, 170 {USDHC3_BASE_ADDR},
171 {USDHC4_BASE_ADDR}, 171 {USDHC4_BASE_ADDR},
172 }; 172 };
173 173
174 int board_mmc_init(bd_t *bis) 174 int board_mmc_init(bd_t *bis)
175 { 175 {
176 s32 status = 0; 176 int ret;
177 u32 index = 0; 177 u32 index = 0;
178 178
179 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 179 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
180 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 180 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
181 181
182 usdhc_cfg[0].max_bus_width = 8; 182 usdhc_cfg[0].max_bus_width = 8;
183 usdhc_cfg[1].max_bus_width = 4; 183 usdhc_cfg[1].max_bus_width = 4;
184 184
185 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 185 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
186 switch (index) { 186 switch (index) {
187 case 0: 187 case 0:
188 imx_iomux_v3_setup_multiple_pads( 188 imx_iomux_v3_setup_multiple_pads(
189 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 189 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
190 break; 190 break;
191 case 1: 191 case 1:
192 imx_iomux_v3_setup_multiple_pads( 192 imx_iomux_v3_setup_multiple_pads(
193 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 193 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
194 break; 194 break;
195 default: 195 default:
196 printf("Warning: you configured more USDHC controllers" 196 printf("Warning: you configured more USDHC controllers"
197 "(%d) then supported by the board (%d)\n", 197 "(%d) then supported by the board (%d)\n",
198 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 198 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
199 return status; 199 return -EINVAL;
200 } 200 }
201 201
202 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 202 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
203 if (ret)
204 return ret;
203 } 205 }
204 206
205 return status; 207 return 0;
206 } 208 }
207 209
208 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 210 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
209 211
210 /* I2C3 - IO expander */ 212 /* I2C3 - IO expander */
211 static struct i2c_pads_info i2c_pad_info2 = { 213 static struct i2c_pads_info i2c_pad_info2 = {
212 .scl = { 214 .scl = {
213 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 215 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
214 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 216 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
215 .gp = IMX_GPIO_NR(3, 17) 217 .gp = IMX_GPIO_NR(3, 17)
216 }, 218 },
217 .sda = { 219 .sda = {
218 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 220 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
219 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 221 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
220 .gp = IMX_GPIO_NR(3, 18) 222 .gp = IMX_GPIO_NR(3, 18)
221 } 223 }
222 }; 224 };
223 225
224 static iomux_v3_cfg_t const pwm_pad[] = { 226 static iomux_v3_cfg_t const pwm_pad[] = {
225 MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM), 227 MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
226 }; 228 };
227 229
228 static void leds_on(void) 230 static void leds_on(void)
229 { 231 {
230 /* turn on all possible leds connected via GPIO expander */ 232 /* turn on all possible leds connected via GPIO expander */
231 i2c_set_bus_num(2); 233 i2c_set_bus_num(2);
232 pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT); 234 pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
233 pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0); 235 pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
234 } 236 }
235 237
236 static void backlight_lcd_off(void) 238 static void backlight_lcd_off(void)
237 { 239 {
238 unsigned gpio = IMX_GPIO_NR(2, 0); 240 unsigned gpio = IMX_GPIO_NR(2, 0);
239 gpio_direction_output(gpio, 0); 241 gpio_direction_output(gpio, 0);
240 242
241 gpio = IMX_GPIO_NR(2, 3); 243 gpio = IMX_GPIO_NR(2, 3);
242 gpio_direction_output(gpio, 0); 244 gpio_direction_output(gpio, 0);
243 } 245 }
244 246
245 int board_eth_init(bd_t *bis) 247 int board_eth_init(bd_t *bis)
246 { 248 {
247 uint32_t base = IMX_FEC_BASE; 249 uint32_t base = IMX_FEC_BASE;
248 struct mii_dev *bus = NULL; 250 struct mii_dev *bus = NULL;
249 struct phy_device *phydev = NULL; 251 struct phy_device *phydev = NULL;
250 int ret; 252 int ret;
251 253
252 setup_iomux_enet(); 254 setup_iomux_enet();
253 255
254 bus = fec_get_miibus(base, -1); 256 bus = fec_get_miibus(base, -1);
255 if (!bus) 257 if (!bus)
256 return 0; 258 return 0;
257 259
258 /* scan phy 0 and 5 */ 260 /* scan phy 0 and 5 */
259 phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII); 261 phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
260 if (!phydev) { 262 if (!phydev) {
261 free(bus); 263 free(bus);
262 return 0; 264 return 0;
263 } 265 }
264 266
265 /* depending on the phy address we can detect our board version */ 267 /* depending on the phy address we can detect our board version */
266 if (phydev->addr == 0) 268 if (phydev->addr == 0)
267 setenv("boardver", ""); 269 setenv("boardver", "");
268 else 270 else
269 setenv("boardver", "mr"); 271 setenv("boardver", "mr");
270 272
271 printf("using phy at %d\n", phydev->addr); 273 printf("using phy at %d\n", phydev->addr);
272 ret = fec_probe(bis, -1, base, bus, phydev); 274 ret = fec_probe(bis, -1, base, bus, phydev);
273 if (ret) { 275 if (ret) {
274 printf("FEC MXC: %s:failed\n", __func__); 276 printf("FEC MXC: %s:failed\n", __func__);
275 free(phydev); 277 free(phydev);
276 free(bus); 278 free(bus);
277 } 279 }
278 return 0; 280 return 0;
279 } 281 }
280 282
281 int board_init(void) 283 int board_init(void)
282 { 284 {
283 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 285 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
284 286
285 backlight_lcd_off(); 287 backlight_lcd_off();
286 288
287 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 289 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
288 290
289 leds_on(); 291 leds_on();
290 292
291 /* enable ecspi3 clocks */ 293 /* enable ecspi3 clocks */
292 enable_cspi_clock(1, 2); 294 enable_cspi_clock(1, 2);
293 295
294 #ifdef CONFIG_CMD_SATA 296 #ifdef CONFIG_CMD_SATA
295 setup_sata(); 297 setup_sata();
296 #endif 298 #endif
297 299
298 return 0; 300 return 0;
299 } 301 }
300 302
301 int checkboard(void) 303 int checkboard(void)
302 { 304 {
303 puts("Board: "CONFIG_SYS_BOARD"\n"); 305 puts("Board: "CONFIG_SYS_BOARD"\n");
304 return 0; 306 return 0;
305 } 307 }
306 308
307 #ifdef CONFIG_CMD_BMODE 309 #ifdef CONFIG_CMD_BMODE
308 static const struct boot_mode board_boot_modes[] = { 310 static const struct boot_mode board_boot_modes[] = {
309 /* 4 bit bus width */ 311 /* 4 bit bus width */
310 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 312 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
311 {NULL, 0}, 313 {NULL, 0},
312 }; 314 };
313 #endif 315 #endif
314 316
315 int misc_init_r(void) 317 int misc_init_r(void)
316 { 318 {
317 #ifdef CONFIG_CMD_BMODE 319 #ifdef CONFIG_CMD_BMODE
318 add_board_boot_modes(board_boot_modes); 320 add_board_boot_modes(board_boot_modes);
319 #endif 321 #endif
320 return 0; 322 return 0;
321 } 323 }
322 324