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Commit e4691564ccd366618934e70b7f621df7e1c5d70b

Authored by Heinrich Schuchardt
Committed by Joe Hershberger
1 parent 10710b4ec5
Exists in smarc_8mq_lf_v2020.04 and in 20 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

net: fix typos 

%s/Desriptor/Descriptor/g

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Showing 3 changed files with 3 additions and 3 deletions Inline Diff

drivers/net/fsl_mcdmafec.c
Diff comments   View file @ e469156
1 /* 1 /*
2 * (C) Copyright 2000-2004 2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * (C) Copyright 2007 Freescale Semiconductor, Inc. 5 * (C) Copyright 2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <malloc.h> 12 #include <malloc.h>
13 #include <command.h> 13 #include <command.h>
14 #include <config.h> 14 #include <config.h>
15 #include <net.h> 15 #include <net.h>
16 #include <miiphy.h> 16 #include <miiphy.h>
17 17
18 #undef ET_DEBUG 18 #undef ET_DEBUG
19 #undef MII_DEBUG 19 #undef MII_DEBUG
20 20
21 /* Ethernet Transmit and Receive Buffers */ 21 /* Ethernet Transmit and Receive Buffers */
22 #define DBUF_LENGTH 1520 22 #define DBUF_LENGTH 1520
23 #define PKT_MAXBUF_SIZE 1518 23 #define PKT_MAXBUF_SIZE 1518
24 #define PKT_MINBUF_SIZE 64 24 #define PKT_MINBUF_SIZE 64
25 #define PKT_MAXBLR_SIZE 1536 25 #define PKT_MAXBLR_SIZE 1536
26 #define LAST_PKTBUFSRX PKTBUFSRX - 1 26 #define LAST_PKTBUFSRX PKTBUFSRX - 1
27 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 27 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
28 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 28 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
29 #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF) 29 #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
30 30
31 /* RxBD bits definitions */ 31 /* RxBD bits definitions */
32 #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ 32 #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
33 BD_ENET_RX_OV | BD_ENET_RX_TR) 33 BD_ENET_RX_OV | BD_ENET_RX_TR)
34 34
35 #include <asm/immap.h> 35 #include <asm/immap.h>
36 #include <asm/fsl_mcdmafec.h> 36 #include <asm/fsl_mcdmafec.h>
37 37
38 #include "MCD_dma.h" 38 #include "MCD_dma.h"
39 39
40 DECLARE_GLOBAL_DATA_PTR; 40 DECLARE_GLOBAL_DATA_PTR;
41 41
42 struct fec_info_dma fec_info[] = { 42 struct fec_info_dma fec_info[] = {
43 #ifdef CONFIG_SYS_FEC0_IOBASE 43 #ifdef CONFIG_SYS_FEC0_IOBASE
44 { 44 {
45 0, /* index */ 45 0, /* index */
46 CONFIG_SYS_FEC0_IOBASE, /* io base */ 46 CONFIG_SYS_FEC0_IOBASE, /* io base */
47 CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ 47 CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
48 CONFIG_SYS_FEC0_MIIBASE, /* mii base */ 48 CONFIG_SYS_FEC0_MIIBASE, /* mii base */
49 -1, /* phy_addr */ 49 -1, /* phy_addr */
50 0, /* duplex and speed */ 50 0, /* duplex and speed */
51 0, /* phy name */ 51 0, /* phy name */
52 0, /* phyname init */ 52 0, /* phyname init */
53 0, /* RX BD */ 53 0, /* RX BD */
54 0, /* TX BD */ 54 0, /* TX BD */
55 0, /* rx Index */ 55 0, /* rx Index */
56 0, /* tx Index */ 56 0, /* tx Index */
57 0, /* tx buffer */ 57 0, /* tx buffer */
58 0, /* initialized flag */ 58 0, /* initialized flag */
59 (struct fec_info_dma *)-1, /* next */ 59 (struct fec_info_dma *)-1, /* next */
60 FEC0_RX_TASK, /* rxTask */ 60 FEC0_RX_TASK, /* rxTask */
61 FEC0_TX_TASK, /* txTask */ 61 FEC0_TX_TASK, /* txTask */
62 FEC0_RX_PRIORITY, /* rxPri */ 62 FEC0_RX_PRIORITY, /* rxPri */
63 FEC0_TX_PRIORITY, /* txPri */ 63 FEC0_TX_PRIORITY, /* txPri */
64 FEC0_RX_INIT, /* rxInit */ 64 FEC0_RX_INIT, /* rxInit */
65 FEC0_TX_INIT, /* txInit */ 65 FEC0_TX_INIT, /* txInit */
66 0, /* usedTbdIndex */ 66 0, /* usedTbdIndex */
67 0, /* cleanTbdNum */ 67 0, /* cleanTbdNum */
68 }, 68 },
69 #endif 69 #endif
70 #ifdef CONFIG_SYS_FEC1_IOBASE 70 #ifdef CONFIG_SYS_FEC1_IOBASE
71 { 71 {
72 1, /* index */ 72 1, /* index */
73 CONFIG_SYS_FEC1_IOBASE, /* io base */ 73 CONFIG_SYS_FEC1_IOBASE, /* io base */
74 CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ 74 CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
75 CONFIG_SYS_FEC1_MIIBASE, /* mii base */ 75 CONFIG_SYS_FEC1_MIIBASE, /* mii base */
76 -1, /* phy_addr */ 76 -1, /* phy_addr */
77 0, /* duplex and speed */ 77 0, /* duplex and speed */
78 0, /* phy name */ 78 0, /* phy name */
79 0, /* phy name init */ 79 0, /* phy name init */
80 #ifdef CONFIG_SYS_DMA_USE_INTSRAM 80 #ifdef CONFIG_SYS_DMA_USE_INTSRAM
81 (cbd_t *)DBUF_LENGTH, /* RX BD */ 81 (cbd_t *)DBUF_LENGTH, /* RX BD */
82 #else 82 #else
83 0, /* RX BD */ 83 0, /* RX BD */
84 #endif 84 #endif
85 0, /* TX BD */ 85 0, /* TX BD */
86 0, /* rx Index */ 86 0, /* rx Index */
87 0, /* tx Index */ 87 0, /* tx Index */
88 0, /* tx buffer */ 88 0, /* tx buffer */
89 0, /* initialized flag */ 89 0, /* initialized flag */
90 (struct fec_info_dma *)-1, /* next */ 90 (struct fec_info_dma *)-1, /* next */
91 FEC1_RX_TASK, /* rxTask */ 91 FEC1_RX_TASK, /* rxTask */
92 FEC1_TX_TASK, /* txTask */ 92 FEC1_TX_TASK, /* txTask */
93 FEC1_RX_PRIORITY, /* rxPri */ 93 FEC1_RX_PRIORITY, /* rxPri */
94 FEC1_TX_PRIORITY, /* txPri */ 94 FEC1_TX_PRIORITY, /* txPri */
95 FEC1_RX_INIT, /* rxInit */ 95 FEC1_RX_INIT, /* rxInit */
96 FEC1_TX_INIT, /* txInit */ 96 FEC1_TX_INIT, /* txInit */
97 0, /* usedTbdIndex */ 97 0, /* usedTbdIndex */
98 0, /* cleanTbdNum */ 98 0, /* cleanTbdNum */
99 } 99 }
100 #endif 100 #endif
101 }; 101 };
102 102
103 static int fec_send(struct eth_device *dev, void *packet, int length); 103 static int fec_send(struct eth_device *dev, void *packet, int length);
104 static int fec_recv(struct eth_device *dev); 104 static int fec_recv(struct eth_device *dev);
105 static int fec_init(struct eth_device *dev, bd_t * bd); 105 static int fec_init(struct eth_device *dev, bd_t * bd);
106 static void fec_halt(struct eth_device *dev); 106 static void fec_halt(struct eth_device *dev);
107 107
108 #ifdef ET_DEBUG 108 #ifdef ET_DEBUG
109 static void dbg_fec_regs(struct eth_device *dev) 109 static void dbg_fec_regs(struct eth_device *dev)
110 { 110 {
111 struct fec_info_dma *info = dev->priv; 111 struct fec_info_dma *info = dev->priv;
112 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 112 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
113 113
114 printf("=====\n"); 114 printf("=====\n");
115 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 115 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
116 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 116 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
117 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 117 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
118 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 118 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
119 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 119 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
120 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 120 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
121 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 121 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
122 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr); 122 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
123 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 123 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
124 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 124 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
125 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 125 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
126 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 126 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
127 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 127 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
128 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 128 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
129 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 129 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
130 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 130 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
131 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 131 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
132 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr); 132 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
133 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr); 133 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
134 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr); 134 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
135 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp); 135 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
136 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp); 136 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
137 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar); 137 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
138 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp); 138 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
139 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp); 139 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
140 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr); 140 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
141 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr); 141 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
142 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr); 142 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
143 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp); 143 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
144 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp); 144 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
145 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar); 145 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
146 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp); 146 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
147 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp); 147 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
148 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst); 148 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
149 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr); 149 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
150 } 150 }
151 #endif 151 #endif
152 152
153 static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, 153 static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
154 int dup_spd) 154 int dup_spd)
155 { 155 {
156 if ((dup_spd >> 16) == FULL) { 156 if ((dup_spd >> 16) == FULL) {
157 /* Set maximum frame length */ 157 /* Set maximum frame length */
158 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 158 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
159 FEC_RCR_PROM | 0x100; 159 FEC_RCR_PROM | 0x100;
160 fecp->tcr = FEC_TCR_FDEN; 160 fecp->tcr = FEC_TCR_FDEN;
161 } else { 161 } else {
162 /* Half duplex mode */ 162 /* Half duplex mode */
163 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 163 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
164 FEC_RCR_MII_MODE | FEC_RCR_DRT; 164 FEC_RCR_MII_MODE | FEC_RCR_DRT;
165 fecp->tcr &= ~FEC_TCR_FDEN; 165 fecp->tcr &= ~FEC_TCR_FDEN;
166 } 166 }
167 167
168 if ((dup_spd & 0xFFFF) == _100BASET) { 168 if ((dup_spd & 0xFFFF) == _100BASET) {
169 #ifdef MII_DEBUG 169 #ifdef MII_DEBUG
170 printf("100Mbps\n"); 170 printf("100Mbps\n");
171 #endif 171 #endif
172 bd->bi_ethspeed = 100; 172 bd->bi_ethspeed = 100;
173 } else { 173 } else {
174 #ifdef MII_DEBUG 174 #ifdef MII_DEBUG
175 printf("10Mbps\n"); 175 printf("10Mbps\n");
176 #endif 176 #endif
177 bd->bi_ethspeed = 10; 177 bd->bi_ethspeed = 10;
178 } 178 }
179 } 179 }
180 180
181 static int fec_send(struct eth_device *dev, void *packet, int length) 181 static int fec_send(struct eth_device *dev, void *packet, int length)
182 { 182 {
183 struct fec_info_dma *info = dev->priv; 183 struct fec_info_dma *info = dev->priv;
184 cbd_t *pTbd, *pUsedTbd; 184 cbd_t *pTbd, *pUsedTbd;
185 u16 phyStatus; 185 u16 phyStatus;
186 186
187 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); 187 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
188 188
189 /* process all the consumed TBDs */ 189 /* process all the consumed TBDs */
190 while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) { 190 while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
191 pUsedTbd = &info->txbd[info->usedTbdIdx]; 191 pUsedTbd = &info->txbd[info->usedTbdIdx];
192 if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) { 192 if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
193 #ifdef ET_DEBUG 193 #ifdef ET_DEBUG
194 printf("Cannot clean TBD %d, in use\n", 194 printf("Cannot clean TBD %d, in use\n",
195 info->cleanTbdNum); 195 info->cleanTbdNum);
196 #endif 196 #endif
197 return 0; 197 return 0;
198 } 198 }
199 199
200 /* clean this buffer descriptor */ 200 /* clean this buffer descriptor */
201 if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1)) 201 if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
202 pUsedTbd->cbd_sc = BD_ENET_TX_WRAP; 202 pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
203 else 203 else
204 pUsedTbd->cbd_sc = 0; 204 pUsedTbd->cbd_sc = 0;
205 205
206 /* update some indeces for a correct handling of the TBD ring */ 206 /* update some indeces for a correct handling of the TBD ring */
207 info->cleanTbdNum++; 207 info->cleanTbdNum++;
208 info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; 208 info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
209 } 209 }
210 210
211 /* Check for valid length of data. */ 211 /* Check for valid length of data. */
212 if ((length > 1500) || (length <= 0)) { 212 if ((length > 1500) || (length <= 0)) {
213 return -1; 213 return -1;
214 } 214 }
215 215
216 /* Check the number of vacant TxBDs. */ 216 /* Check the number of vacant TxBDs. */
217 if (info->cleanTbdNum < 1) { 217 if (info->cleanTbdNum < 1) {
218 printf("No available TxBDs ...\n"); 218 printf("No available TxBDs ...\n");
219 return -1; 219 return -1;
220 } 220 }
221 221
222 /* Get the first TxBD to send the mac header */ 222 /* Get the first TxBD to send the mac header */
223 pTbd = &info->txbd[info->txIdx]; 223 pTbd = &info->txbd[info->txIdx];
224 pTbd->cbd_datlen = length; 224 pTbd->cbd_datlen = length;
225 pTbd->cbd_bufaddr = (u32) packet; 225 pTbd->cbd_bufaddr = (u32) packet;
226 pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; 226 pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
227 info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; 227 info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
228 228
229 /* Enable DMA transmit task */ 229 /* Enable DMA transmit task */
230 MCD_continDma(info->txTask); 230 MCD_continDma(info->txTask);
231 231
232 info->cleanTbdNum -= 1; 232 info->cleanTbdNum -= 1;
233 233
234 /* wait until frame is sent . */ 234 /* wait until frame is sent . */
235 while (pTbd->cbd_sc & BD_ENET_TX_READY) { 235 while (pTbd->cbd_sc & BD_ENET_TX_READY) {
236 udelay(10); 236 udelay(10);
237 } 237 }
238 238
239 return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 239 return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
240 } 240 }
241 241
242 static int fec_recv(struct eth_device *dev) 242 static int fec_recv(struct eth_device *dev)
243 { 243 {
244 struct fec_info_dma *info = dev->priv; 244 struct fec_info_dma *info = dev->priv;
245 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 245 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
246 246
247 cbd_t *prbd = &info->rxbd[info->rxIdx]; 247 cbd_t *prbd = &info->rxbd[info->rxIdx];
248 u32 ievent; 248 u32 ievent;
249 int frame_length, len = 0; 249 int frame_length, len = 0;
250 250
251 /* Check if any critical events have happened */ 251 /* Check if any critical events have happened */
252 ievent = fecp->eir; 252 ievent = fecp->eir;
253 if (ievent != 0) { 253 if (ievent != 0) {
254 fecp->eir = ievent; 254 fecp->eir = ievent;
255 255
256 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { 256 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
257 printf("fec_recv: error\n"); 257 printf("fec_recv: error\n");
258 fec_halt(dev); 258 fec_halt(dev);
259 fec_init(dev, NULL); 259 fec_init(dev, NULL);
260 return 0; 260 return 0;
261 } 261 }
262 262
263 if (ievent & FEC_EIR_HBERR) { 263 if (ievent & FEC_EIR_HBERR) {
264 /* Heartbeat error */ 264 /* Heartbeat error */
265 fecp->tcr |= FEC_TCR_GTS; 265 fecp->tcr |= FEC_TCR_GTS;
266 } 266 }
267 267
268 if (ievent & FEC_EIR_GRA) { 268 if (ievent & FEC_EIR_GRA) {
269 /* Graceful stop complete */ 269 /* Graceful stop complete */
270 if (fecp->tcr & FEC_TCR_GTS) { 270 if (fecp->tcr & FEC_TCR_GTS) {
271 printf("fec_recv: tcr_gts\n"); 271 printf("fec_recv: tcr_gts\n");
272 fec_halt(dev); 272 fec_halt(dev);
273 fecp->tcr &= ~FEC_TCR_GTS; 273 fecp->tcr &= ~FEC_TCR_GTS;
274 fec_init(dev, NULL); 274 fec_init(dev, NULL);
275 } 275 }
276 } 276 }
277 } 277 }
278 278
279 if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) { 279 if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
280 if ((prbd->cbd_sc & BD_ENET_RX_LAST) && 280 if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
281 !(prbd->cbd_sc & BD_ENET_RX_ERR) && 281 !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
282 ((prbd->cbd_datlen - 4) > 14)) { 282 ((prbd->cbd_datlen - 4) > 14)) {
283 283
284 /* Get buffer address and size */ 284 /* Get buffer address and size */
285 frame_length = prbd->cbd_datlen - 4; 285 frame_length = prbd->cbd_datlen - 4;
286 286
287 /* Fill the buffer and pass it to upper layers */ 287 /* Fill the buffer and pass it to upper layers */
288 net_process_received_packet((uchar *)prbd->cbd_bufaddr, 288 net_process_received_packet((uchar *)prbd->cbd_bufaddr,
289 frame_length); 289 frame_length);
290 len = frame_length; 290 len = frame_length;
291 } 291 }
292 292
293 /* Reset buffer descriptor as empty */ 293 /* Reset buffer descriptor as empty */
294 if ((info->rxIdx) == (PKTBUFSRX - 1)) 294 if ((info->rxIdx) == (PKTBUFSRX - 1))
295 prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); 295 prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
296 else 296 else
297 prbd->cbd_sc = BD_ENET_RX_EMPTY; 297 prbd->cbd_sc = BD_ENET_RX_EMPTY;
298 298
299 prbd->cbd_datlen = PKTSIZE_ALIGN; 299 prbd->cbd_datlen = PKTSIZE_ALIGN;
300 300
301 /* Now, we have an empty RxBD, restart the DMA receive task */ 301 /* Now, we have an empty RxBD, restart the DMA receive task */
302 MCD_continDma(info->rxTask); 302 MCD_continDma(info->rxTask);
303 303
304 /* Increment BD count */ 304 /* Increment BD count */
305 info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX; 305 info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
306 } 306 }
307 307
308 return len; 308 return len;
309 } 309 }
310 310
311 static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac) 311 static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
312 { 312 {
313 u8 currByte; /* byte for which to compute the CRC */ 313 u8 currByte; /* byte for which to compute the CRC */
314 int byte; /* loop - counter */ 314 int byte; /* loop - counter */
315 int bit; /* loop - counter */ 315 int bit; /* loop - counter */
316 u32 crc = 0xffffffff; /* initial value */ 316 u32 crc = 0xffffffff; /* initial value */
317 317
318 for (byte = 0; byte < 6; byte++) { 318 for (byte = 0; byte < 6; byte++) {
319 currByte = mac[byte]; 319 currByte = mac[byte];
320 for (bit = 0; bit < 8; bit++) { 320 for (bit = 0; bit < 8; bit++) {
321 if ((currByte & 0x01) ^ (crc & 0x01)) { 321 if ((currByte & 0x01) ^ (crc & 0x01)) {
322 crc >>= 1; 322 crc >>= 1;
323 crc = crc ^ 0xedb88320; 323 crc = crc ^ 0xedb88320;
324 } else { 324 } else {
325 crc >>= 1; 325 crc >>= 1;
326 } 326 }
327 currByte >>= 1; 327 currByte >>= 1;
328 } 328 }
329 } 329 }
330 330
331 crc = crc >> 26; 331 crc = crc >> 26;
332 332
333 /* Set individual hash table register */ 333 /* Set individual hash table register */
334 if (crc >= 32) { 334 if (crc >= 32) {
335 fecp->ialr = (1 << (crc - 32)); 335 fecp->ialr = (1 << (crc - 32));
336 fecp->iaur = 0; 336 fecp->iaur = 0;
337 } else { 337 } else {
338 fecp->ialr = 0; 338 fecp->ialr = 0;
339 fecp->iaur = (1 << crc); 339 fecp->iaur = (1 << crc);
340 } 340 }
341 341
342 /* Set physical address */ 342 /* Set physical address */
343 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; 343 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
344 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808; 344 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
345 345
346 /* Clear multicast address hash table */ 346 /* Clear multicast address hash table */
347 fecp->gaur = 0; 347 fecp->gaur = 0;
348 fecp->galr = 0; 348 fecp->galr = 0;
349 } 349 }
350 350
351 static int fec_init(struct eth_device *dev, bd_t * bd) 351 static int fec_init(struct eth_device *dev, bd_t * bd)
352 { 352 {
353 struct fec_info_dma *info = dev->priv; 353 struct fec_info_dma *info = dev->priv;
354 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 354 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
355 int i; 355 int i;
356 uchar enetaddr[6]; 356 uchar enetaddr[6];
357 357
358 #ifdef ET_DEBUG 358 #ifdef ET_DEBUG
359 printf("fec_init: iobase 0x%08x ...\n", info->iobase); 359 printf("fec_init: iobase 0x%08x ...\n", info->iobase);
360 #endif 360 #endif
361 361
362 fecpin_setclear(dev, 1); 362 fecpin_setclear(dev, 1);
363 363
364 fec_halt(dev); 364 fec_halt(dev);
365 365
366 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ 366 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
367 defined (CONFIG_SYS_DISCOVER_PHY) 367 defined (CONFIG_SYS_DISCOVER_PHY)
368 368
369 mii_init(); 369 mii_init();
370 370
371 set_fec_duplex_speed(fecp, bd, info->dup_spd); 371 set_fec_duplex_speed(fecp, bd, info->dup_spd);
372 #else 372 #else
373 #ifndef CONFIG_SYS_DISCOVER_PHY 373 #ifndef CONFIG_SYS_DISCOVER_PHY
374 set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 374 set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
375 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ 375 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
376 #endif /* CONFIG_CMD_MII || CONFIG_MII */ 376 #endif /* CONFIG_CMD_MII || CONFIG_MII */
377 377
378 /* We use strictly polling mode only */ 378 /* We use strictly polling mode only */
379 fecp->eimr = 0; 379 fecp->eimr = 0;
380 380
381 /* Clear any pending interrupt */ 381 /* Clear any pending interrupt */
382 fecp->eir = 0xffffffff; 382 fecp->eir = 0xffffffff;
383 383
384 /* Set station address */ 384 /* Set station address */
385 if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) 385 if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
386 eth_env_get_enetaddr("ethaddr", enetaddr); 386 eth_env_get_enetaddr("ethaddr", enetaddr);
387 else 387 else
388 eth_env_get_enetaddr("eth1addr", enetaddr); 388 eth_env_get_enetaddr("eth1addr", enetaddr);
389 fec_set_hwaddr(fecp, enetaddr); 389 fec_set_hwaddr(fecp, enetaddr);
390 390
391 /* Set Opcode/Pause Duration Register */ 391 /* Set Opcode/Pause Duration Register */
392 fecp->opd = 0x00010020; 392 fecp->opd = 0x00010020;
393 393
394 /* Setup Buffers and Buffer Desriptors */ 394 /* Setup Buffers and Buffer Descriptors */
395 info->rxIdx = 0; 395 info->rxIdx = 0;
396 info->txIdx = 0; 396 info->txIdx = 0;
397 397
398 /* Setup Receiver Buffer Descriptors (13.14.24.18) 398 /* Setup Receiver Buffer Descriptors (13.14.24.18)
399 * Settings: Empty, Wrap */ 399 * Settings: Empty, Wrap */
400 for (i = 0; i < PKTBUFSRX; i++) { 400 for (i = 0; i < PKTBUFSRX; i++) {
401 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 401 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
402 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; 402 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
403 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; 403 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
404 } 404 }
405 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 405 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
406 406
407 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 407 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
408 * Settings: Last, Tx CRC */ 408 * Settings: Last, Tx CRC */
409 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) { 409 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
410 info->txbd[i].cbd_sc = 0; 410 info->txbd[i].cbd_sc = 0;
411 info->txbd[i].cbd_datlen = 0; 411 info->txbd[i].cbd_datlen = 0;
412 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 412 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
413 } 413 }
414 info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; 414 info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
415 415
416 info->usedTbdIdx = 0; 416 info->usedTbdIdx = 0;
417 info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER; 417 info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
418 418
419 /* Set Rx FIFO alarm and granularity value */ 419 /* Set Rx FIFO alarm and granularity value */
420 fecp->rfcr = 0x0c000000; 420 fecp->rfcr = 0x0c000000;
421 fecp->rfar = 0x0000030c; 421 fecp->rfar = 0x0000030c;
422 422
423 /* Set Tx FIFO granularity value */ 423 /* Set Tx FIFO granularity value */
424 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000; 424 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
425 fecp->tfar = 0x00000080; 425 fecp->tfar = 0x00000080;
426 426
427 fecp->tfwr = 0x2; 427 fecp->tfwr = 0x2;
428 fecp->ctcwr = 0x03000000; 428 fecp->ctcwr = 0x03000000;
429 429
430 /* Enable DMA receive task */ 430 /* Enable DMA receive task */
431 MCD_startDma(info->rxTask, /* Dma channel */ 431 MCD_startDma(info->rxTask, /* Dma channel */
432 (s8 *) info->rxbd, /*Source Address */ 432 (s8 *) info->rxbd, /*Source Address */
433 0, /* Source increment */ 433 0, /* Source increment */
434 (s8 *) (&fecp->rfdr), /* dest */ 434 (s8 *) (&fecp->rfdr), /* dest */
435 4, /* dest increment */ 435 4, /* dest increment */
436 0, /* DMA size */ 436 0, /* DMA size */
437 4, /* xfer size */ 437 4, /* xfer size */
438 info->rxInit, /* initiator */ 438 info->rxInit, /* initiator */
439 info->rxPri, /* priority */ 439 info->rxPri, /* priority */
440 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ 440 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
441 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ 441 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
442 ); 442 );
443 443
444 /* Enable DMA tx task with no ready buffer descriptors */ 444 /* Enable DMA tx task with no ready buffer descriptors */
445 MCD_startDma(info->txTask, /* Dma channel */ 445 MCD_startDma(info->txTask, /* Dma channel */
446 (s8 *) info->txbd, /*Source Address */ 446 (s8 *) info->txbd, /*Source Address */
447 0, /* Source increment */ 447 0, /* Source increment */
448 (s8 *) (&fecp->tfdr), /* dest */ 448 (s8 *) (&fecp->tfdr), /* dest */
449 4, /* dest incr */ 449 4, /* dest incr */
450 0, /* DMA size */ 450 0, /* DMA size */
451 4, /* xfer size */ 451 4, /* xfer size */
452 info->txInit, /* initiator */ 452 info->txInit, /* initiator */
453 info->txPri, /* priority */ 453 info->txPri, /* priority */
454 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ 454 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
455 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ 455 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
456 ); 456 );
457 457
458 /* Now enable the transmit and receive processing */ 458 /* Now enable the transmit and receive processing */
459 fecp->ecr |= FEC_ECR_ETHER_EN; 459 fecp->ecr |= FEC_ECR_ETHER_EN;
460 460
461 return 1; 461 return 1;
462 } 462 }
463 463
464 static void fec_halt(struct eth_device *dev) 464 static void fec_halt(struct eth_device *dev)
465 { 465 {
466 struct fec_info_dma *info = dev->priv; 466 struct fec_info_dma *info = dev->priv;
467 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); 467 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
468 int counter = 0xffff; 468 int counter = 0xffff;
469 469
470 /* issue graceful stop command to the FEC transmitter if necessary */ 470 /* issue graceful stop command to the FEC transmitter if necessary */
471 fecp->tcr |= FEC_TCR_GTS; 471 fecp->tcr |= FEC_TCR_GTS;
472 472
473 /* wait for graceful stop to register */ 473 /* wait for graceful stop to register */
474 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ; 474 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
475 475
476 /* Disable DMA tasks */ 476 /* Disable DMA tasks */
477 MCD_killDma(info->txTask); 477 MCD_killDma(info->txTask);
478 MCD_killDma(info->rxTask); 478 MCD_killDma(info->rxTask);
479 479
480 /* Disable the Ethernet Controller */ 480 /* Disable the Ethernet Controller */
481 fecp->ecr &= ~FEC_ECR_ETHER_EN; 481 fecp->ecr &= ~FEC_ECR_ETHER_EN;
482 482
483 /* Clear FIFO status registers */ 483 /* Clear FIFO status registers */
484 fecp->rfsr &= FIFO_ERRSTAT; 484 fecp->rfsr &= FIFO_ERRSTAT;
485 fecp->tfsr &= FIFO_ERRSTAT; 485 fecp->tfsr &= FIFO_ERRSTAT;
486 486
487 fecp->frst = 0x01000000; 487 fecp->frst = 0x01000000;
488 488
489 /* Issue a reset command to the FEC chip */ 489 /* Issue a reset command to the FEC chip */
490 fecp->ecr |= FEC_ECR_RESET; 490 fecp->ecr |= FEC_ECR_RESET;
491 491
492 /* wait at least 20 clock cycles */ 492 /* wait at least 20 clock cycles */
493 udelay(10000); 493 udelay(10000);
494 494
495 #ifdef ET_DEBUG 495 #ifdef ET_DEBUG
496 printf("Ethernet task stopped\n"); 496 printf("Ethernet task stopped\n");
497 #endif 497 #endif
498 } 498 }
499 499
500 int mcdmafec_initialize(bd_t * bis) 500 int mcdmafec_initialize(bd_t * bis)
501 { 501 {
502 struct eth_device *dev; 502 struct eth_device *dev;
503 int i; 503 int i;
504 #ifdef CONFIG_SYS_DMA_USE_INTSRAM 504 #ifdef CONFIG_SYS_DMA_USE_INTSRAM
505 u32 tmp = CONFIG_SYS_INTSRAM + 0x2000; 505 u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
506 #endif 506 #endif
507 507
508 for (i = 0; i < ARRAY_SIZE(fec_info); i++) { 508 for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
509 509
510 dev = 510 dev =
511 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, 511 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
512 sizeof *dev); 512 sizeof *dev);
513 if (dev == NULL) 513 if (dev == NULL)
514 hang(); 514 hang();
515 515
516 memset(dev, 0, sizeof(*dev)); 516 memset(dev, 0, sizeof(*dev));
517 517
518 sprintf(dev->name, "FEC%d", fec_info[i].index); 518 sprintf(dev->name, "FEC%d", fec_info[i].index);
519 519
520 dev->priv = &fec_info[i]; 520 dev->priv = &fec_info[i];
521 dev->init = fec_init; 521 dev->init = fec_init;
522 dev->halt = fec_halt; 522 dev->halt = fec_halt;
523 dev->send = fec_send; 523 dev->send = fec_send;
524 dev->recv = fec_recv; 524 dev->recv = fec_recv;
525 525
526 /* setup Receive and Transmit buffer descriptor */ 526 /* setup Receive and Transmit buffer descriptor */
527 #ifdef CONFIG_SYS_DMA_USE_INTSRAM 527 #ifdef CONFIG_SYS_DMA_USE_INTSRAM
528 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); 528 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
529 tmp = (u32)fec_info[i].rxbd; 529 tmp = (u32)fec_info[i].rxbd;
530 fec_info[i].txbd = 530 fec_info[i].txbd =
531 (cbd_t *)((u32)fec_info[i].txbd + tmp + 531 (cbd_t *)((u32)fec_info[i].txbd + tmp +
532 (PKTBUFSRX * sizeof(cbd_t))); 532 (PKTBUFSRX * sizeof(cbd_t)));
533 tmp = (u32)fec_info[i].txbd; 533 tmp = (u32)fec_info[i].txbd;
534 fec_info[i].txbuf = 534 fec_info[i].txbuf =
535 (char *)((u32)fec_info[i].txbuf + tmp + 535 (char *)((u32)fec_info[i].txbuf + tmp +
536 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); 536 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
537 tmp = (u32)fec_info[i].txbuf; 537 tmp = (u32)fec_info[i].txbuf;
538 #else 538 #else
539 fec_info[i].rxbd = 539 fec_info[i].rxbd =
540 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, 540 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
541 (PKTBUFSRX * sizeof(cbd_t))); 541 (PKTBUFSRX * sizeof(cbd_t)));
542 fec_info[i].txbd = 542 fec_info[i].txbd =
543 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, 543 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
544 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); 544 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
545 fec_info[i].txbuf = 545 fec_info[i].txbuf =
546 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); 546 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
547 #endif 547 #endif
548 548
549 #ifdef ET_DEBUG 549 #ifdef ET_DEBUG
550 printf("rxbd %x txbd %x\n", 550 printf("rxbd %x txbd %x\n",
551 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 551 (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
552 #endif 552 #endif
553 553
554 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); 554 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
555 555
556 eth_register(dev); 556 eth_register(dev);
557 557
558 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 558 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
559 int retval; 559 int retval;
560 struct mii_dev *mdiodev = mdio_alloc(); 560 struct mii_dev *mdiodev = mdio_alloc();
561 if (!mdiodev) 561 if (!mdiodev)
562 return -ENOMEM; 562 return -ENOMEM;
563 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 563 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
564 mdiodev->read = mcffec_miiphy_read; 564 mdiodev->read = mcffec_miiphy_read;
565 mdiodev->write = mcffec_miiphy_write; 565 mdiodev->write = mcffec_miiphy_write;
566 566
567 retval = mdio_register(mdiodev); 567 retval = mdio_register(mdiodev);
568 if (retval < 0) 568 if (retval < 0)
569 return retval; 569 return retval;
570 #endif 570 #endif
571 571
572 if (i > 0) 572 if (i > 0)
573 fec_info[i - 1].next = &fec_info[i]; 573 fec_info[i - 1].next = &fec_info[i];
574 } 574 }
575 fec_info[i - 1].next = &fec_info[0]; 575 fec_info[i - 1].next = &fec_info[0];
576 576
577 /* default speed */ 577 /* default speed */
578 bis->bi_ethspeed = 10; 578 bis->bi_ethspeed = 10;
579 579
580 return 0; 580 return 0;
581 } 581 }
582 582
drivers/net/mcffec.c
Diff comments   View file @ e469156
1 /* 1 /*
2 * (C) Copyright 2000-2004 2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * (C) Copyright 2007 Freescale Semiconductor, Inc. 5 * (C) Copyright 2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <malloc.h> 12 #include <malloc.h>
13 13
14 #include <command.h> 14 #include <command.h>
15 #include <net.h> 15 #include <net.h>
16 #include <netdev.h> 16 #include <netdev.h>
17 #include <miiphy.h> 17 #include <miiphy.h>
18 18
19 #include <asm/fec.h> 19 #include <asm/fec.h>
20 #include <asm/immap.h> 20 #include <asm/immap.h>
21 21
22 #undef ET_DEBUG 22 #undef ET_DEBUG
23 #undef MII_DEBUG 23 #undef MII_DEBUG
24 24
25 /* Ethernet Transmit and Receive Buffers */ 25 /* Ethernet Transmit and Receive Buffers */
26 #define DBUF_LENGTH 1520 26 #define DBUF_LENGTH 1520
27 #define TX_BUF_CNT 2 27 #define TX_BUF_CNT 2
28 #define PKT_MAXBUF_SIZE 1518 28 #define PKT_MAXBUF_SIZE 1518
29 #define PKT_MINBUF_SIZE 64 29 #define PKT_MINBUF_SIZE 64
30 #define PKT_MAXBLR_SIZE 1520 30 #define PKT_MAXBLR_SIZE 1520
31 #define LAST_PKTBUFSRX PKTBUFSRX - 1 31 #define LAST_PKTBUFSRX PKTBUFSRX - 1
32 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 32 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
33 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 33 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
34 34
35 DECLARE_GLOBAL_DATA_PTR; 35 DECLARE_GLOBAL_DATA_PTR;
36 36
37 struct fec_info_s fec_info[] = { 37 struct fec_info_s fec_info[] = {
38 #ifdef CONFIG_SYS_FEC0_IOBASE 38 #ifdef CONFIG_SYS_FEC0_IOBASE
39 { 39 {
40 0, /* index */ 40 0, /* index */
41 CONFIG_SYS_FEC0_IOBASE, /* io base */ 41 CONFIG_SYS_FEC0_IOBASE, /* io base */
42 CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ 42 CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
43 CONFIG_SYS_FEC0_MIIBASE, /* mii base */ 43 CONFIG_SYS_FEC0_MIIBASE, /* mii base */
44 -1, /* phy_addr */ 44 -1, /* phy_addr */
45 0, /* duplex and speed */ 45 0, /* duplex and speed */
46 0, /* phy name */ 46 0, /* phy name */
47 0, /* phyname init */ 47 0, /* phyname init */
48 0, /* RX BD */ 48 0, /* RX BD */
49 0, /* TX BD */ 49 0, /* TX BD */
50 0, /* rx Index */ 50 0, /* rx Index */
51 0, /* tx Index */ 51 0, /* tx Index */
52 0, /* tx buffer */ 52 0, /* tx buffer */
53 0, /* initialized flag */ 53 0, /* initialized flag */
54 (struct fec_info_s *)-1, 54 (struct fec_info_s *)-1,
55 }, 55 },
56 #endif 56 #endif
57 #ifdef CONFIG_SYS_FEC1_IOBASE 57 #ifdef CONFIG_SYS_FEC1_IOBASE
58 { 58 {
59 1, /* index */ 59 1, /* index */
60 CONFIG_SYS_FEC1_IOBASE, /* io base */ 60 CONFIG_SYS_FEC1_IOBASE, /* io base */
61 CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ 61 CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
62 CONFIG_SYS_FEC1_MIIBASE, /* mii base */ 62 CONFIG_SYS_FEC1_MIIBASE, /* mii base */
63 -1, /* phy_addr */ 63 -1, /* phy_addr */
64 0, /* duplex and speed */ 64 0, /* duplex and speed */
65 0, /* phy name */ 65 0, /* phy name */
66 0, /* phy name init */ 66 0, /* phy name init */
67 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM 67 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
68 (cbd_t *)DBUF_LENGTH, /* RX BD */ 68 (cbd_t *)DBUF_LENGTH, /* RX BD */
69 #else 69 #else
70 0, /* RX BD */ 70 0, /* RX BD */
71 #endif 71 #endif
72 0, /* TX BD */ 72 0, /* TX BD */
73 0, /* rx Index */ 73 0, /* rx Index */
74 0, /* tx Index */ 74 0, /* tx Index */
75 0, /* tx buffer */ 75 0, /* tx buffer */
76 0, /* initialized flag */ 76 0, /* initialized flag */
77 (struct fec_info_s *)-1, 77 (struct fec_info_s *)-1,
78 } 78 }
79 #endif 79 #endif
80 }; 80 };
81 81
82 int fec_recv(struct eth_device *dev); 82 int fec_recv(struct eth_device *dev);
83 int fec_init(struct eth_device *dev, bd_t * bd); 83 int fec_init(struct eth_device *dev, bd_t * bd);
84 void fec_halt(struct eth_device *dev); 84 void fec_halt(struct eth_device *dev);
85 void fec_reset(struct eth_device *dev); 85 void fec_reset(struct eth_device *dev);
86 86
87 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) 87 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
88 { 88 {
89 if ((dup_spd >> 16) == FULL) { 89 if ((dup_spd >> 16) == FULL) {
90 /* Set maximum frame length */ 90 /* Set maximum frame length */
91 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 91 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
92 FEC_RCR_PROM | 0x100; 92 FEC_RCR_PROM | 0x100;
93 fecp->tcr = FEC_TCR_FDEN; 93 fecp->tcr = FEC_TCR_FDEN;
94 } else { 94 } else {
95 /* Half duplex mode */ 95 /* Half duplex mode */
96 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 96 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
97 FEC_RCR_MII_MODE | FEC_RCR_DRT; 97 FEC_RCR_MII_MODE | FEC_RCR_DRT;
98 fecp->tcr &= ~FEC_TCR_FDEN; 98 fecp->tcr &= ~FEC_TCR_FDEN;
99 } 99 }
100 100
101 if ((dup_spd & 0xFFFF) == _100BASET) { 101 if ((dup_spd & 0xFFFF) == _100BASET) {
102 #ifdef CONFIG_MCF5445x 102 #ifdef CONFIG_MCF5445x
103 fecp->rcr &= ~0x200; /* disabled 10T base */ 103 fecp->rcr &= ~0x200; /* disabled 10T base */
104 #endif 104 #endif
105 #ifdef MII_DEBUG 105 #ifdef MII_DEBUG
106 printf("100Mbps\n"); 106 printf("100Mbps\n");
107 #endif 107 #endif
108 bd->bi_ethspeed = 100; 108 bd->bi_ethspeed = 100;
109 } else { 109 } else {
110 #ifdef CONFIG_MCF5445x 110 #ifdef CONFIG_MCF5445x
111 fecp->rcr |= 0x200; /* enabled 10T base */ 111 fecp->rcr |= 0x200; /* enabled 10T base */
112 #endif 112 #endif
113 #ifdef MII_DEBUG 113 #ifdef MII_DEBUG
114 printf("10Mbps\n"); 114 printf("10Mbps\n");
115 #endif 115 #endif
116 bd->bi_ethspeed = 10; 116 bd->bi_ethspeed = 10;
117 } 117 }
118 } 118 }
119 119
120 static int fec_send(struct eth_device *dev, void *packet, int length) 120 static int fec_send(struct eth_device *dev, void *packet, int length)
121 { 121 {
122 struct fec_info_s *info = dev->priv; 122 struct fec_info_s *info = dev->priv;
123 volatile fec_t *fecp = (fec_t *) (info->iobase); 123 volatile fec_t *fecp = (fec_t *) (info->iobase);
124 int j, rc; 124 int j, rc;
125 u16 phyStatus; 125 u16 phyStatus;
126 126
127 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); 127 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
128 128
129 /* section 16.9.23.3 129 /* section 16.9.23.3
130 * Wait for ready 130 * Wait for ready
131 */ 131 */
132 j = 0; 132 j = 0;
133 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 133 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
134 (j < MCFFEC_TOUT_LOOP)) { 134 (j < MCFFEC_TOUT_LOOP)) {
135 udelay(1); 135 udelay(1);
136 j++; 136 j++;
137 } 137 }
138 if (j >= MCFFEC_TOUT_LOOP) { 138 if (j >= MCFFEC_TOUT_LOOP) {
139 printf("TX not ready\n"); 139 printf("TX not ready\n");
140 } 140 }
141 141
142 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; 142 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
143 info->txbd[info->txIdx].cbd_datlen = length; 143 info->txbd[info->txIdx].cbd_datlen = length;
144 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; 144 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
145 145
146 /* Activate transmit Buffer Descriptor polling */ 146 /* Activate transmit Buffer Descriptor polling */
147 fecp->tdar = 0x01000000; /* Descriptor polling active */ 147 fecp->tdar = 0x01000000; /* Descriptor polling active */
148 148
149 #ifndef CONFIG_SYS_FEC_BUF_USE_SRAM 149 #ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
150 /* 150 /*
151 * FEC unable to initial transmit data packet. 151 * FEC unable to initial transmit data packet.
152 * A nop will ensure the descriptor polling active completed. 152 * A nop will ensure the descriptor polling active completed.
153 * CF Internal RAM has shorter cycle access than DRAM. If use 153 * CF Internal RAM has shorter cycle access than DRAM. If use
154 * DRAM as Buffer descriptor and data, a nop is a must. 154 * DRAM as Buffer descriptor and data, a nop is a must.
155 * Affect only V2 and V3. 155 * Affect only V2 and V3.
156 */ 156 */
157 __asm__ ("nop"); 157 __asm__ ("nop");
158 158
159 #endif 159 #endif
160 160
161 #ifdef CONFIG_SYS_UNIFY_CACHE 161 #ifdef CONFIG_SYS_UNIFY_CACHE
162 icache_invalid(); 162 icache_invalid();
163 #endif 163 #endif
164 164
165 j = 0; 165 j = 0;
166 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 166 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
167 (j < MCFFEC_TOUT_LOOP)) { 167 (j < MCFFEC_TOUT_LOOP)) {
168 udelay(1); 168 udelay(1);
169 j++; 169 j++;
170 } 170 }
171 if (j >= MCFFEC_TOUT_LOOP) { 171 if (j >= MCFFEC_TOUT_LOOP) {
172 printf("TX timeout\n"); 172 printf("TX timeout\n");
173 } 173 }
174 174
175 #ifdef ET_DEBUG 175 #ifdef ET_DEBUG
176 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", 176 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
177 __FILE__, __LINE__, __FUNCTION__, j, 177 __FILE__, __LINE__, __FUNCTION__, j,
178 info->txbd[info->txIdx].cbd_sc, 178 info->txbd[info->txIdx].cbd_sc,
179 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); 179 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
180 #endif 180 #endif
181 181
182 /* return only status bits */ 182 /* return only status bits */
183 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 183 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
184 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; 184 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
185 185
186 return rc; 186 return rc;
187 } 187 }
188 188
189 int fec_recv(struct eth_device *dev) 189 int fec_recv(struct eth_device *dev)
190 { 190 {
191 struct fec_info_s *info = dev->priv; 191 struct fec_info_s *info = dev->priv;
192 volatile fec_t *fecp = (fec_t *) (info->iobase); 192 volatile fec_t *fecp = (fec_t *) (info->iobase);
193 int length; 193 int length;
194 194
195 for (;;) { 195 for (;;) {
196 #ifndef CONFIG_SYS_FEC_BUF_USE_SRAM 196 #ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
197 #endif 197 #endif
198 #ifdef CONFIG_SYS_UNIFY_CACHE 198 #ifdef CONFIG_SYS_UNIFY_CACHE
199 icache_invalid(); 199 icache_invalid();
200 #endif 200 #endif
201 /* section 16.9.23.2 */ 201 /* section 16.9.23.2 */
202 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { 202 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
203 length = -1; 203 length = -1;
204 break; /* nothing received - leave for() loop */ 204 break; /* nothing received - leave for() loop */
205 } 205 }
206 206
207 length = info->rxbd[info->rxIdx].cbd_datlen; 207 length = info->rxbd[info->rxIdx].cbd_datlen;
208 208
209 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { 209 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
210 printf("%s[%d] err: %x\n", 210 printf("%s[%d] err: %x\n",
211 __FUNCTION__, __LINE__, 211 __FUNCTION__, __LINE__,
212 info->rxbd[info->rxIdx].cbd_sc); 212 info->rxbd[info->rxIdx].cbd_sc);
213 #ifdef ET_DEBUG 213 #ifdef ET_DEBUG
214 printf("%s[%d] err: %x\n", 214 printf("%s[%d] err: %x\n",
215 __FUNCTION__, __LINE__, 215 __FUNCTION__, __LINE__,
216 info->rxbd[info->rxIdx].cbd_sc); 216 info->rxbd[info->rxIdx].cbd_sc);
217 #endif 217 #endif
218 } else { 218 } else {
219 219
220 length -= 4; 220 length -= 4;
221 /* Pass the packet up to the protocol layers. */ 221 /* Pass the packet up to the protocol layers. */
222 net_process_received_packet(net_rx_packets[info->rxIdx], 222 net_process_received_packet(net_rx_packets[info->rxIdx],
223 length); 223 length);
224 224
225 fecp->eir |= FEC_EIR_RXF; 225 fecp->eir |= FEC_EIR_RXF;
226 } 226 }
227 227
228 /* Give the buffer back to the FEC. */ 228 /* Give the buffer back to the FEC. */
229 info->rxbd[info->rxIdx].cbd_datlen = 0; 229 info->rxbd[info->rxIdx].cbd_datlen = 0;
230 230
231 /* wrap around buffer index when necessary */ 231 /* wrap around buffer index when necessary */
232 if (info->rxIdx == LAST_PKTBUFSRX) { 232 if (info->rxIdx == LAST_PKTBUFSRX) {
233 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; 233 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
234 info->rxIdx = 0; 234 info->rxIdx = 0;
235 } else { 235 } else {
236 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; 236 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
237 info->rxIdx++; 237 info->rxIdx++;
238 } 238 }
239 239
240 /* Try to fill Buffer Descriptors */ 240 /* Try to fill Buffer Descriptors */
241 fecp->rdar = 0x01000000; /* Descriptor polling active */ 241 fecp->rdar = 0x01000000; /* Descriptor polling active */
242 } 242 }
243 243
244 return length; 244 return length;
245 } 245 }
246 246
247 #ifdef ET_DEBUG 247 #ifdef ET_DEBUG
248 void dbgFecRegs(struct eth_device *dev) 248 void dbgFecRegs(struct eth_device *dev)
249 { 249 {
250 struct fec_info_s *info = dev->priv; 250 struct fec_info_s *info = dev->priv;
251 volatile fec_t *fecp = (fec_t *) (info->iobase); 251 volatile fec_t *fecp = (fec_t *) (info->iobase);
252 252
253 printf("=====\n"); 253 printf("=====\n");
254 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 254 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
255 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 255 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
256 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); 256 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
257 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); 257 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
258 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 258 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
259 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 259 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
260 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 260 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
261 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 261 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
262 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 262 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
263 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 263 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
264 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 264 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
265 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 265 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
266 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 266 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
267 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 267 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
268 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 268 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
269 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 269 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
270 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 270 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
271 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 271 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
272 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); 272 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
273 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); 273 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
274 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); 274 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
275 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); 275 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
276 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); 276 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
277 277
278 printf("\n"); 278 printf("\n");
279 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, 279 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
280 fecp->rmon_t_drop); 280 fecp->rmon_t_drop);
281 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, 281 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
282 fecp->rmon_t_packets); 282 fecp->rmon_t_packets);
283 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, 283 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
284 fecp->rmon_t_bc_pkt); 284 fecp->rmon_t_bc_pkt);
285 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, 285 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
286 fecp->rmon_t_mc_pkt); 286 fecp->rmon_t_mc_pkt);
287 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, 287 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
288 fecp->rmon_t_crc_align); 288 fecp->rmon_t_crc_align);
289 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, 289 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
290 fecp->rmon_t_undersize); 290 fecp->rmon_t_undersize);
291 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, 291 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
292 fecp->rmon_t_oversize); 292 fecp->rmon_t_oversize);
293 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, 293 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
294 fecp->rmon_t_frag); 294 fecp->rmon_t_frag);
295 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, 295 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
296 fecp->rmon_t_jab); 296 fecp->rmon_t_jab);
297 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, 297 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
298 fecp->rmon_t_col); 298 fecp->rmon_t_col);
299 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, 299 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
300 fecp->rmon_t_p64); 300 fecp->rmon_t_p64);
301 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, 301 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
302 fecp->rmon_t_p65to127); 302 fecp->rmon_t_p65to127);
303 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, 303 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
304 fecp->rmon_t_p128to255); 304 fecp->rmon_t_p128to255);
305 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, 305 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
306 fecp->rmon_t_p256to511); 306 fecp->rmon_t_p256to511);
307 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, 307 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
308 fecp->rmon_t_p512to1023); 308 fecp->rmon_t_p512to1023);
309 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, 309 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
310 fecp->rmon_t_p1024to2047); 310 fecp->rmon_t_p1024to2047);
311 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, 311 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
312 fecp->rmon_t_p_gte2048); 312 fecp->rmon_t_p_gte2048);
313 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, 313 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
314 fecp->rmon_t_octets); 314 fecp->rmon_t_octets);
315 315
316 printf("\n"); 316 printf("\n");
317 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, 317 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
318 fecp->ieee_t_drop); 318 fecp->ieee_t_drop);
319 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, 319 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
320 fecp->ieee_t_frame_ok); 320 fecp->ieee_t_frame_ok);
321 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, 321 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
322 fecp->ieee_t_1col); 322 fecp->ieee_t_1col);
323 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, 323 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
324 fecp->ieee_t_mcol); 324 fecp->ieee_t_mcol);
325 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, 325 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
326 fecp->ieee_t_def); 326 fecp->ieee_t_def);
327 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, 327 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
328 fecp->ieee_t_lcol); 328 fecp->ieee_t_lcol);
329 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, 329 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
330 fecp->ieee_t_excol); 330 fecp->ieee_t_excol);
331 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, 331 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
332 fecp->ieee_t_macerr); 332 fecp->ieee_t_macerr);
333 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, 333 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
334 fecp->ieee_t_cserr); 334 fecp->ieee_t_cserr);
335 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, 335 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
336 fecp->ieee_t_sqe); 336 fecp->ieee_t_sqe);
337 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, 337 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
338 fecp->ieee_t_fdxfc); 338 fecp->ieee_t_fdxfc);
339 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, 339 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
340 fecp->ieee_t_octets_ok); 340 fecp->ieee_t_octets_ok);
341 341
342 printf("\n"); 342 printf("\n");
343 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, 343 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
344 fecp->rmon_r_drop); 344 fecp->rmon_r_drop);
345 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, 345 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
346 fecp->rmon_r_packets); 346 fecp->rmon_r_packets);
347 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, 347 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
348 fecp->rmon_r_bc_pkt); 348 fecp->rmon_r_bc_pkt);
349 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, 349 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
350 fecp->rmon_r_mc_pkt); 350 fecp->rmon_r_mc_pkt);
351 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, 351 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
352 fecp->rmon_r_crc_align); 352 fecp->rmon_r_crc_align);
353 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, 353 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
354 fecp->rmon_r_undersize); 354 fecp->rmon_r_undersize);
355 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, 355 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
356 fecp->rmon_r_oversize); 356 fecp->rmon_r_oversize);
357 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, 357 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
358 fecp->rmon_r_frag); 358 fecp->rmon_r_frag);
359 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, 359 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
360 fecp->rmon_r_jab); 360 fecp->rmon_r_jab);
361 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, 361 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
362 fecp->rmon_r_p64); 362 fecp->rmon_r_p64);
363 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, 363 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
364 fecp->rmon_r_p65to127); 364 fecp->rmon_r_p65to127);
365 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, 365 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
366 fecp->rmon_r_p128to255); 366 fecp->rmon_r_p128to255);
367 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, 367 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
368 fecp->rmon_r_p256to511); 368 fecp->rmon_r_p256to511);
369 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, 369 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
370 fecp->rmon_r_p512to1023); 370 fecp->rmon_r_p512to1023);
371 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, 371 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
372 fecp->rmon_r_p1024to2047); 372 fecp->rmon_r_p1024to2047);
373 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, 373 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
374 fecp->rmon_r_p_gte2048); 374 fecp->rmon_r_p_gte2048);
375 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, 375 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
376 fecp->rmon_r_octets); 376 fecp->rmon_r_octets);
377 377
378 printf("\n"); 378 printf("\n");
379 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, 379 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
380 fecp->ieee_r_drop); 380 fecp->ieee_r_drop);
381 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, 381 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
382 fecp->ieee_r_frame_ok); 382 fecp->ieee_r_frame_ok);
383 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, 383 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
384 fecp->ieee_r_crc); 384 fecp->ieee_r_crc);
385 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, 385 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
386 fecp->ieee_r_align); 386 fecp->ieee_r_align);
387 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, 387 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
388 fecp->ieee_r_macerr); 388 fecp->ieee_r_macerr);
389 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, 389 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
390 fecp->ieee_r_fdxfc); 390 fecp->ieee_r_fdxfc);
391 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, 391 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
392 fecp->ieee_r_octets_ok); 392 fecp->ieee_r_octets_ok);
393 393
394 printf("\n\n\n"); 394 printf("\n\n\n");
395 } 395 }
396 #endif 396 #endif
397 397
398 int fec_init(struct eth_device *dev, bd_t * bd) 398 int fec_init(struct eth_device *dev, bd_t * bd)
399 { 399 {
400 struct fec_info_s *info = dev->priv; 400 struct fec_info_s *info = dev->priv;
401 volatile fec_t *fecp = (fec_t *) (info->iobase); 401 volatile fec_t *fecp = (fec_t *) (info->iobase);
402 int i; 402 int i;
403 uchar ea[6]; 403 uchar ea[6];
404 404
405 fecpin_setclear(dev, 1); 405 fecpin_setclear(dev, 1);
406 406
407 fec_reset(dev); 407 fec_reset(dev);
408 408
409 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ 409 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
410 defined (CONFIG_SYS_DISCOVER_PHY) 410 defined (CONFIG_SYS_DISCOVER_PHY)
411 411
412 mii_init(); 412 mii_init();
413 413
414 setFecDuplexSpeed(fecp, bd, info->dup_spd); 414 setFecDuplexSpeed(fecp, bd, info->dup_spd);
415 #else 415 #else
416 #ifndef CONFIG_SYS_DISCOVER_PHY 416 #ifndef CONFIG_SYS_DISCOVER_PHY
417 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 417 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
418 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ 418 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
419 #endif /* CONFIG_CMD_MII || CONFIG_MII */ 419 #endif /* CONFIG_CMD_MII || CONFIG_MII */
420 420
421 /* We use strictly polling mode only */ 421 /* We use strictly polling mode only */
422 fecp->eimr = 0; 422 fecp->eimr = 0;
423 423
424 /* Clear any pending interrupt */ 424 /* Clear any pending interrupt */
425 fecp->eir = 0xffffffff; 425 fecp->eir = 0xffffffff;
426 426
427 /* Set station address */ 427 /* Set station address */
428 if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) { 428 if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
429 #ifdef CONFIG_SYS_FEC1_IOBASE 429 #ifdef CONFIG_SYS_FEC1_IOBASE
430 volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE); 430 volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
431 eth_env_get_enetaddr("eth1addr", ea); 431 eth_env_get_enetaddr("eth1addr", ea);
432 fecp1->palr = 432 fecp1->palr =
433 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 433 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
434 fecp1->paur = (ea[4] << 24) | (ea[5] << 16); 434 fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
435 #endif 435 #endif
436 eth_env_get_enetaddr("ethaddr", ea); 436 eth_env_get_enetaddr("ethaddr", ea);
437 fecp->palr = 437 fecp->palr =
438 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 438 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
439 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 439 fecp->paur = (ea[4] << 24) | (ea[5] << 16);
440 } else { 440 } else {
441 #ifdef CONFIG_SYS_FEC0_IOBASE 441 #ifdef CONFIG_SYS_FEC0_IOBASE
442 volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE); 442 volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
443 eth_env_get_enetaddr("ethaddr", ea); 443 eth_env_get_enetaddr("ethaddr", ea);
444 fecp0->palr = 444 fecp0->palr =
445 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 445 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
446 fecp0->paur = (ea[4] << 24) | (ea[5] << 16); 446 fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
447 #endif 447 #endif
448 #ifdef CONFIG_SYS_FEC1_IOBASE 448 #ifdef CONFIG_SYS_FEC1_IOBASE
449 eth_env_get_enetaddr("eth1addr", ea); 449 eth_env_get_enetaddr("eth1addr", ea);
450 fecp->palr = 450 fecp->palr =
451 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 451 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
452 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 452 fecp->paur = (ea[4] << 24) | (ea[5] << 16);
453 #endif 453 #endif
454 } 454 }
455 455
456 /* Clear unicast address hash table */ 456 /* Clear unicast address hash table */
457 fecp->iaur = 0; 457 fecp->iaur = 0;
458 fecp->ialr = 0; 458 fecp->ialr = 0;
459 459
460 /* Clear multicast address hash table */ 460 /* Clear multicast address hash table */
461 fecp->gaur = 0; 461 fecp->gaur = 0;
462 fecp->galr = 0; 462 fecp->galr = 0;
463 463
464 /* Set maximum receive buffer size. */ 464 /* Set maximum receive buffer size. */
465 fecp->emrbr = PKT_MAXBLR_SIZE; 465 fecp->emrbr = PKT_MAXBLR_SIZE;
466 466
467 /* 467 /*
468 * Setup Buffers and Buffer Desriptors 468 * Setup Buffers and Buffer Descriptors
469 */ 469 */
470 info->rxIdx = 0; 470 info->rxIdx = 0;
471 info->txIdx = 0; 471 info->txIdx = 0;
472 472
473 /* 473 /*
474 * Setup Receiver Buffer Descriptors (13.14.24.18) 474 * Setup Receiver Buffer Descriptors (13.14.24.18)
475 * Settings: 475 * Settings:
476 * Empty, Wrap 476 * Empty, Wrap
477 */ 477 */
478 for (i = 0; i < PKTBUFSRX; i++) { 478 for (i = 0; i < PKTBUFSRX; i++) {
479 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 479 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
480 info->rxbd[i].cbd_datlen = 0; /* Reset */ 480 info->rxbd[i].cbd_datlen = 0; /* Reset */
481 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; 481 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
482 } 482 }
483 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 483 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
484 484
485 /* 485 /*
486 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 486 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
487 * Settings: 487 * Settings:
488 * Last, Tx CRC 488 * Last, Tx CRC
489 */ 489 */
490 for (i = 0; i < TX_BUF_CNT; i++) { 490 for (i = 0; i < TX_BUF_CNT; i++) {
491 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; 491 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
492 info->txbd[i].cbd_datlen = 0; /* Reset */ 492 info->txbd[i].cbd_datlen = 0; /* Reset */
493 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 493 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
494 } 494 }
495 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; 495 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
496 496
497 /* Set receive and transmit descriptor base */ 497 /* Set receive and transmit descriptor base */
498 fecp->erdsr = (unsigned int)(&info->rxbd[0]); 498 fecp->erdsr = (unsigned int)(&info->rxbd[0]);
499 fecp->etdsr = (unsigned int)(&info->txbd[0]); 499 fecp->etdsr = (unsigned int)(&info->txbd[0]);
500 500
501 /* Now enable the transmit and receive processing */ 501 /* Now enable the transmit and receive processing */
502 fecp->ecr |= FEC_ECR_ETHER_EN; 502 fecp->ecr |= FEC_ECR_ETHER_EN;
503 503
504 /* And last, try to fill Rx Buffer Descriptors */ 504 /* And last, try to fill Rx Buffer Descriptors */
505 fecp->rdar = 0x01000000; /* Descriptor polling active */ 505 fecp->rdar = 0x01000000; /* Descriptor polling active */
506 506
507 return 1; 507 return 1;
508 } 508 }
509 509
510 void fec_reset(struct eth_device *dev) 510 void fec_reset(struct eth_device *dev)
511 { 511 {
512 struct fec_info_s *info = dev->priv; 512 struct fec_info_s *info = dev->priv;
513 volatile fec_t *fecp = (fec_t *) (info->iobase); 513 volatile fec_t *fecp = (fec_t *) (info->iobase);
514 int i; 514 int i;
515 515
516 fecp->ecr = FEC_ECR_RESET; 516 fecp->ecr = FEC_ECR_RESET;
517 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { 517 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
518 udelay(1); 518 udelay(1);
519 } 519 }
520 if (i == FEC_RESET_DELAY) { 520 if (i == FEC_RESET_DELAY) {
521 printf("FEC_RESET_DELAY timeout\n"); 521 printf("FEC_RESET_DELAY timeout\n");
522 } 522 }
523 } 523 }
524 524
525 void fec_halt(struct eth_device *dev) 525 void fec_halt(struct eth_device *dev)
526 { 526 {
527 struct fec_info_s *info = dev->priv; 527 struct fec_info_s *info = dev->priv;
528 528
529 fec_reset(dev); 529 fec_reset(dev);
530 530
531 fecpin_setclear(dev, 0); 531 fecpin_setclear(dev, 0);
532 532
533 info->rxIdx = info->txIdx = 0; 533 info->rxIdx = info->txIdx = 0;
534 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); 534 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
535 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); 535 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
536 memset(info->txbuf, 0, DBUF_LENGTH); 536 memset(info->txbuf, 0, DBUF_LENGTH);
537 } 537 }
538 538
539 int mcffec_initialize(bd_t * bis) 539 int mcffec_initialize(bd_t * bis)
540 { 540 {
541 struct eth_device *dev; 541 struct eth_device *dev;
542 int i; 542 int i;
543 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM 543 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
544 u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; 544 u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
545 #endif 545 #endif
546 546
547 for (i = 0; i < ARRAY_SIZE(fec_info); i++) { 547 for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
548 548
549 dev = 549 dev =
550 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, 550 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
551 sizeof *dev); 551 sizeof *dev);
552 if (dev == NULL) 552 if (dev == NULL)
553 hang(); 553 hang();
554 554
555 memset(dev, 0, sizeof(*dev)); 555 memset(dev, 0, sizeof(*dev));
556 556
557 sprintf(dev->name, "FEC%d", fec_info[i].index); 557 sprintf(dev->name, "FEC%d", fec_info[i].index);
558 558
559 dev->priv = &fec_info[i]; 559 dev->priv = &fec_info[i];
560 dev->init = fec_init; 560 dev->init = fec_init;
561 dev->halt = fec_halt; 561 dev->halt = fec_halt;
562 dev->send = fec_send; 562 dev->send = fec_send;
563 dev->recv = fec_recv; 563 dev->recv = fec_recv;
564 564
565 /* setup Receive and Transmit buffer descriptor */ 565 /* setup Receive and Transmit buffer descriptor */
566 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM 566 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
567 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); 567 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
568 tmp = (u32)fec_info[i].rxbd; 568 tmp = (u32)fec_info[i].rxbd;
569 fec_info[i].txbd = 569 fec_info[i].txbd =
570 (cbd_t *)((u32)fec_info[i].txbd + tmp + 570 (cbd_t *)((u32)fec_info[i].txbd + tmp +
571 (PKTBUFSRX * sizeof(cbd_t))); 571 (PKTBUFSRX * sizeof(cbd_t)));
572 tmp = (u32)fec_info[i].txbd; 572 tmp = (u32)fec_info[i].txbd;
573 fec_info[i].txbuf = 573 fec_info[i].txbuf =
574 (char *)((u32)fec_info[i].txbuf + tmp + 574 (char *)((u32)fec_info[i].txbuf + tmp +
575 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); 575 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
576 tmp = (u32)fec_info[i].txbuf; 576 tmp = (u32)fec_info[i].txbuf;
577 #else 577 #else
578 fec_info[i].rxbd = 578 fec_info[i].rxbd =
579 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, 579 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
580 (PKTBUFSRX * sizeof(cbd_t))); 580 (PKTBUFSRX * sizeof(cbd_t)));
581 fec_info[i].txbd = 581 fec_info[i].txbd =
582 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, 582 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
583 (TX_BUF_CNT * sizeof(cbd_t))); 583 (TX_BUF_CNT * sizeof(cbd_t)));
584 fec_info[i].txbuf = 584 fec_info[i].txbuf =
585 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); 585 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
586 #endif 586 #endif
587 587
588 #ifdef ET_DEBUG 588 #ifdef ET_DEBUG
589 printf("rxbd %x txbd %x\n", 589 printf("rxbd %x txbd %x\n",
590 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 590 (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
591 #endif 591 #endif
592 592
593 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); 593 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
594 594
595 eth_register(dev); 595 eth_register(dev);
596 596
597 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 597 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
598 int retval; 598 int retval;
599 struct mii_dev *mdiodev = mdio_alloc(); 599 struct mii_dev *mdiodev = mdio_alloc();
600 if (!mdiodev) 600 if (!mdiodev)
601 return -ENOMEM; 601 return -ENOMEM;
602 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 602 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
603 mdiodev->read = mcffec_miiphy_read; 603 mdiodev->read = mcffec_miiphy_read;
604 mdiodev->write = mcffec_miiphy_write; 604 mdiodev->write = mcffec_miiphy_write;
605 605
606 retval = mdio_register(mdiodev); 606 retval = mdio_register(mdiodev);
607 if (retval < 0) 607 if (retval < 0)
608 return retval; 608 return retval;
609 #endif 609 #endif
610 if (i > 0) 610 if (i > 0)
611 fec_info[i - 1].next = &fec_info[i]; 611 fec_info[i - 1].next = &fec_info[i];
612 } 612 }
613 fec_info[i - 1].next = &fec_info[0]; 613 fec_info[i - 1].next = &fec_info[0];
614 614
615 /* default speed */ 615 /* default speed */
616 bis->bi_ethspeed = 10; 616 bis->bi_ethspeed = 10;
617 617
618 return 0; 618 return 0;
619 } 619 }
620 620
drivers/net/mvneta.c
Diff comments   View file @ e469156
1 /* 1 /*
2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
3 * 3 *
4 * U-Boot version: 4 * U-Boot version:
5 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 5 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
6 * 6 *
7 * Based on the Linux version which is: 7 * Based on the Linux version which is:
8 * Copyright (C) 2012 Marvell 8 * Copyright (C) 2012 Marvell
9 * 9 *
10 * Rami Rosen <rosenr@marvell.com> 10 * Rami Rosen <rosenr@marvell.com>
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * 12 *
13 * SPDX-License-Identifier: GPL-2.0 13 * SPDX-License-Identifier: GPL-2.0
14 */ 14 */
15 15
16 #include <common.h> 16 #include <common.h>
17 #include <dm.h> 17 #include <dm.h>
18 #include <net.h> 18 #include <net.h>
19 #include <netdev.h> 19 #include <netdev.h>
20 #include <config.h> 20 #include <config.h>
21 #include <malloc.h> 21 #include <malloc.h>
22 #include <asm/io.h> 22 #include <asm/io.h>
23 #include <linux/errno.h> 23 #include <linux/errno.h>
24 #include <phy.h> 24 #include <phy.h>
25 #include <miiphy.h> 25 #include <miiphy.h>
26 #include <watchdog.h> 26 #include <watchdog.h>
27 #include <asm/arch/cpu.h> 27 #include <asm/arch/cpu.h>
28 #include <asm/arch/soc.h> 28 #include <asm/arch/soc.h>
29 #include <linux/compat.h> 29 #include <linux/compat.h>
30 #include <linux/mbus.h> 30 #include <linux/mbus.h>
31 31
32 DECLARE_GLOBAL_DATA_PTR; 32 DECLARE_GLOBAL_DATA_PTR;
33 33
34 #if !defined(CONFIG_PHYLIB) 34 #if !defined(CONFIG_PHYLIB)
35 # error Marvell mvneta requires PHYLIB 35 # error Marvell mvneta requires PHYLIB
36 #endif 36 #endif
37 37
38 /* Some linux -> U-Boot compatibility stuff */ 38 /* Some linux -> U-Boot compatibility stuff */
39 #define netdev_err(dev, fmt, args...) \ 39 #define netdev_err(dev, fmt, args...) \
40 printf(fmt, ##args) 40 printf(fmt, ##args)
41 #define netdev_warn(dev, fmt, args...) \ 41 #define netdev_warn(dev, fmt, args...) \
42 printf(fmt, ##args) 42 printf(fmt, ##args)
43 #define netdev_info(dev, fmt, args...) \ 43 #define netdev_info(dev, fmt, args...) \
44 printf(fmt, ##args) 44 printf(fmt, ##args)
45 45
46 #define CONFIG_NR_CPUS 1 46 #define CONFIG_NR_CPUS 1
47 #define ETH_HLEN 14 /* Total octets in header */ 47 #define ETH_HLEN 14 /* Total octets in header */
48 48
49 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ 49 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
50 #define WRAP (2 + ETH_HLEN + 4 + 32) 50 #define WRAP (2 + ETH_HLEN + 4 + 32)
51 #define MTU 1500 51 #define MTU 1500
52 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) 52 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
53 53
54 #define MVNETA_SMI_TIMEOUT 10000 54 #define MVNETA_SMI_TIMEOUT 10000
55 55
56 /* Registers */ 56 /* Registers */
57 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 57 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
58 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) 58 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
59 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 59 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
60 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 60 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
61 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 61 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
62 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 62 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
63 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 63 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
64 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 64 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
65 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 65 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
66 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 66 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
67 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 67 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
68 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 68 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
69 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 69 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
70 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 70 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
71 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 71 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
72 #define MVNETA_PORT_RX_RESET 0x1cc0 72 #define MVNETA_PORT_RX_RESET 0x1cc0
73 #define MVNETA_PORT_RX_DMA_RESET BIT(0) 73 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
74 #define MVNETA_PHY_ADDR 0x2000 74 #define MVNETA_PHY_ADDR 0x2000
75 #define MVNETA_PHY_ADDR_MASK 0x1f 75 #define MVNETA_PHY_ADDR_MASK 0x1f
76 #define MVNETA_SMI 0x2004 76 #define MVNETA_SMI 0x2004
77 #define MVNETA_PHY_REG_MASK 0x1f 77 #define MVNETA_PHY_REG_MASK 0x1f
78 /* SMI register fields */ 78 /* SMI register fields */
79 #define MVNETA_SMI_DATA_OFFS 0 /* Data */ 79 #define MVNETA_SMI_DATA_OFFS 0 /* Data */
80 #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS) 80 #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
81 #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ 81 #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
82 #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ 82 #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
83 #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ 83 #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
84 #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS) 84 #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
85 #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */ 85 #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
86 #define MVNETA_SMI_BUSY (1 << 28) /* Busy */ 86 #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
87 #define MVNETA_MBUS_RETRY 0x2010 87 #define MVNETA_MBUS_RETRY 0x2010
88 #define MVNETA_UNIT_INTR_CAUSE 0x2080 88 #define MVNETA_UNIT_INTR_CAUSE 0x2080
89 #define MVNETA_UNIT_CONTROL 0x20B0 89 #define MVNETA_UNIT_CONTROL 0x20B0
90 #define MVNETA_PHY_POLLING_ENABLE BIT(1) 90 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
91 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 91 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
92 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 92 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
93 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 93 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
94 #define MVNETA_WIN_SIZE_MASK (0xffff0000) 94 #define MVNETA_WIN_SIZE_MASK (0xffff0000)
95 #define MVNETA_BASE_ADDR_ENABLE 0x2290 95 #define MVNETA_BASE_ADDR_ENABLE 0x2290
96 #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1 96 #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
97 #define MVNETA_PORT_ACCESS_PROTECT 0x2294 97 #define MVNETA_PORT_ACCESS_PROTECT 0x2294
98 #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3 98 #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
99 #define MVNETA_PORT_CONFIG 0x2400 99 #define MVNETA_PORT_CONFIG 0x2400
100 #define MVNETA_UNI_PROMISC_MODE BIT(0) 100 #define MVNETA_UNI_PROMISC_MODE BIT(0)
101 #define MVNETA_DEF_RXQ(q) ((q) << 1) 101 #define MVNETA_DEF_RXQ(q) ((q) << 1)
102 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 102 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
103 #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 103 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
104 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 104 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
105 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 105 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
106 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 106 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
107 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 107 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
108 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 108 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
109 MVNETA_DEF_RXQ_ARP(q) | \ 109 MVNETA_DEF_RXQ_ARP(q) | \
110 MVNETA_DEF_RXQ_TCP(q) | \ 110 MVNETA_DEF_RXQ_TCP(q) | \
111 MVNETA_DEF_RXQ_UDP(q) | \ 111 MVNETA_DEF_RXQ_UDP(q) | \
112 MVNETA_DEF_RXQ_BPDU(q) | \ 112 MVNETA_DEF_RXQ_BPDU(q) | \
113 MVNETA_TX_UNSET_ERR_SUM | \ 113 MVNETA_TX_UNSET_ERR_SUM | \
114 MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 114 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
115 #define MVNETA_PORT_CONFIG_EXTEND 0x2404 115 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
116 #define MVNETA_MAC_ADDR_LOW 0x2414 116 #define MVNETA_MAC_ADDR_LOW 0x2414
117 #define MVNETA_MAC_ADDR_HIGH 0x2418 117 #define MVNETA_MAC_ADDR_HIGH 0x2418
118 #define MVNETA_SDMA_CONFIG 0x241c 118 #define MVNETA_SDMA_CONFIG 0x241c
119 #define MVNETA_SDMA_BRST_SIZE_16 4 119 #define MVNETA_SDMA_BRST_SIZE_16 4
120 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 120 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
121 #define MVNETA_RX_NO_DATA_SWAP BIT(4) 121 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
122 #define MVNETA_TX_NO_DATA_SWAP BIT(5) 122 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
123 #define MVNETA_DESC_SWAP BIT(6) 123 #define MVNETA_DESC_SWAP BIT(6)
124 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 124 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
125 #define MVNETA_PORT_STATUS 0x2444 125 #define MVNETA_PORT_STATUS 0x2444
126 #define MVNETA_TX_IN_PRGRS BIT(1) 126 #define MVNETA_TX_IN_PRGRS BIT(1)
127 #define MVNETA_TX_FIFO_EMPTY BIT(8) 127 #define MVNETA_TX_FIFO_EMPTY BIT(8)
128 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 128 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
129 #define MVNETA_SERDES_CFG 0x24A0 129 #define MVNETA_SERDES_CFG 0x24A0
130 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 130 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
131 #define MVNETA_QSGMII_SERDES_PROTO 0x0667 131 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
132 #define MVNETA_TYPE_PRIO 0x24bc 132 #define MVNETA_TYPE_PRIO 0x24bc
133 #define MVNETA_FORCE_UNI BIT(21) 133 #define MVNETA_FORCE_UNI BIT(21)
134 #define MVNETA_TXQ_CMD_1 0x24e4 134 #define MVNETA_TXQ_CMD_1 0x24e4
135 #define MVNETA_TXQ_CMD 0x2448 135 #define MVNETA_TXQ_CMD 0x2448
136 #define MVNETA_TXQ_DISABLE_SHIFT 8 136 #define MVNETA_TXQ_DISABLE_SHIFT 8
137 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 137 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
138 #define MVNETA_ACC_MODE 0x2500 138 #define MVNETA_ACC_MODE 0x2500
139 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 139 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
140 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 140 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
141 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 141 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
142 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 142 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
143 143
144 /* Exception Interrupt Port/Queue Cause register */ 144 /* Exception Interrupt Port/Queue Cause register */
145 145
146 #define MVNETA_INTR_NEW_CAUSE 0x25a0 146 #define MVNETA_INTR_NEW_CAUSE 0x25a0
147 #define MVNETA_INTR_NEW_MASK 0x25a4 147 #define MVNETA_INTR_NEW_MASK 0x25a4
148 148
149 /* bits 0..7 = TXQ SENT, one bit per queue. 149 /* bits 0..7 = TXQ SENT, one bit per queue.
150 * bits 8..15 = RXQ OCCUP, one bit per queue. 150 * bits 8..15 = RXQ OCCUP, one bit per queue.
151 * bits 16..23 = RXQ FREE, one bit per queue. 151 * bits 16..23 = RXQ FREE, one bit per queue.
152 * bit 29 = OLD_REG_SUM, see old reg ? 152 * bit 29 = OLD_REG_SUM, see old reg ?
153 * bit 30 = TX_ERR_SUM, one bit for 4 ports 153 * bit 30 = TX_ERR_SUM, one bit for 4 ports
154 * bit 31 = MISC_SUM, one bit for 4 ports 154 * bit 31 = MISC_SUM, one bit for 4 ports
155 */ 155 */
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
157 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 157 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
159 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 159 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
160 160
161 #define MVNETA_INTR_OLD_CAUSE 0x25a8 161 #define MVNETA_INTR_OLD_CAUSE 0x25a8
162 #define MVNETA_INTR_OLD_MASK 0x25ac 162 #define MVNETA_INTR_OLD_MASK 0x25ac
163 163
164 /* Data Path Port/Queue Cause Register */ 164 /* Data Path Port/Queue Cause Register */
165 #define MVNETA_INTR_MISC_CAUSE 0x25b0 165 #define MVNETA_INTR_MISC_CAUSE 0x25b0
166 #define MVNETA_INTR_MISC_MASK 0x25b4 166 #define MVNETA_INTR_MISC_MASK 0x25b4
167 #define MVNETA_INTR_ENABLE 0x25b8 167 #define MVNETA_INTR_ENABLE 0x25b8
168 168
169 #define MVNETA_RXQ_CMD 0x2680 169 #define MVNETA_RXQ_CMD 0x2680
170 #define MVNETA_RXQ_DISABLE_SHIFT 8 170 #define MVNETA_RXQ_DISABLE_SHIFT 8
171 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 171 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
172 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 172 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
173 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 173 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
174 #define MVNETA_GMAC_CTRL_0 0x2c00 174 #define MVNETA_GMAC_CTRL_0 0x2c00
175 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 175 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
176 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 176 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
177 #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 177 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
178 #define MVNETA_GMAC_CTRL_2 0x2c08 178 #define MVNETA_GMAC_CTRL_2 0x2c08
179 #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 179 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
180 #define MVNETA_GMAC2_PORT_RGMII BIT(4) 180 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
181 #define MVNETA_GMAC2_PORT_RESET BIT(6) 181 #define MVNETA_GMAC2_PORT_RESET BIT(6)
182 #define MVNETA_GMAC_STATUS 0x2c10 182 #define MVNETA_GMAC_STATUS 0x2c10
183 #define MVNETA_GMAC_LINK_UP BIT(0) 183 #define MVNETA_GMAC_LINK_UP BIT(0)
184 #define MVNETA_GMAC_SPEED_1000 BIT(1) 184 #define MVNETA_GMAC_SPEED_1000 BIT(1)
185 #define MVNETA_GMAC_SPEED_100 BIT(2) 185 #define MVNETA_GMAC_SPEED_100 BIT(2)
186 #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 186 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
187 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 187 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
188 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 188 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
189 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 189 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
190 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 190 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
191 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 191 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
192 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 192 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
193 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 193 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
194 #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1)) 194 #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
195 #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3) 195 #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
196 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 196 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
197 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 197 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
198 #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 198 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
199 #define MVNETA_GMAC_SET_FC_EN BIT(8) 199 #define MVNETA_GMAC_SET_FC_EN BIT(8)
200 #define MVNETA_GMAC_ADVERT_FC_EN BIT(9) 200 #define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
201 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 201 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
202 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 202 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
203 #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15) 203 #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
204 #define MVNETA_MIB_COUNTERS_BASE 0x3080 204 #define MVNETA_MIB_COUNTERS_BASE 0x3080
205 #define MVNETA_MIB_LATE_COLLISION 0x7c 205 #define MVNETA_MIB_LATE_COLLISION 0x7c
206 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 206 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
207 #define MVNETA_DA_FILT_OTH_MCAST 0x3500 207 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
208 #define MVNETA_DA_FILT_UCAST_BASE 0x3600 208 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
209 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 209 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
210 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 210 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
211 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 211 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
212 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 212 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
213 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 213 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
214 #define MVNETA_TXQ_DEC_SENT_SHIFT 16 214 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
215 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 215 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
216 #define MVNETA_TXQ_SENT_DESC_SHIFT 16 216 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
217 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 217 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
218 #define MVNETA_PORT_TX_RESET 0x3cf0 218 #define MVNETA_PORT_TX_RESET 0x3cf0
219 #define MVNETA_PORT_TX_DMA_RESET BIT(0) 219 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
220 #define MVNETA_TX_MTU 0x3e0c 220 #define MVNETA_TX_MTU 0x3e0c
221 #define MVNETA_TX_TOKEN_SIZE 0x3e14 221 #define MVNETA_TX_TOKEN_SIZE 0x3e14
222 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 222 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
223 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 223 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
224 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 224 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
225 225
226 /* Descriptor ring Macros */ 226 /* Descriptor ring Macros */
227 #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 227 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
228 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 228 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
229 229
230 /* Various constants */ 230 /* Various constants */
231 231
232 /* Coalescing */ 232 /* Coalescing */
233 #define MVNETA_TXDONE_COAL_PKTS 16 233 #define MVNETA_TXDONE_COAL_PKTS 16
234 #define MVNETA_RX_COAL_PKTS 32 234 #define MVNETA_RX_COAL_PKTS 32
235 #define MVNETA_RX_COAL_USEC 100 235 #define MVNETA_RX_COAL_USEC 100
236 236
237 /* The two bytes Marvell header. Either contains a special value used 237 /* The two bytes Marvell header. Either contains a special value used
238 * by Marvell switches when a specific hardware mode is enabled (not 238 * by Marvell switches when a specific hardware mode is enabled (not
239 * supported by this driver) or is filled automatically by zeroes on 239 * supported by this driver) or is filled automatically by zeroes on
240 * the RX side. Those two bytes being at the front of the Ethernet 240 * the RX side. Those two bytes being at the front of the Ethernet
241 * header, they allow to have the IP header aligned on a 4 bytes 241 * header, they allow to have the IP header aligned on a 4 bytes
242 * boundary automatically: the hardware skips those two bytes on its 242 * boundary automatically: the hardware skips those two bytes on its
243 * own. 243 * own.
244 */ 244 */
245 #define MVNETA_MH_SIZE 2 245 #define MVNETA_MH_SIZE 2
246 246
247 #define MVNETA_VLAN_TAG_LEN 4 247 #define MVNETA_VLAN_TAG_LEN 4
248 248
249 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 249 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
250 #define MVNETA_TX_CSUM_MAX_SIZE 9800 250 #define MVNETA_TX_CSUM_MAX_SIZE 9800
251 #define MVNETA_ACC_MODE_EXT 1 251 #define MVNETA_ACC_MODE_EXT 1
252 252
253 /* Timeout constants */ 253 /* Timeout constants */
254 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 254 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
255 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 255 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
256 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 256 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
257 257
258 #define MVNETA_TX_MTU_MAX 0x3ffff 258 #define MVNETA_TX_MTU_MAX 0x3ffff
259 259
260 /* Max number of Rx descriptors */ 260 /* Max number of Rx descriptors */
261 #define MVNETA_MAX_RXD 16 261 #define MVNETA_MAX_RXD 16
262 262
263 /* Max number of Tx descriptors */ 263 /* Max number of Tx descriptors */
264 #define MVNETA_MAX_TXD 16 264 #define MVNETA_MAX_TXD 16
265 265
266 /* descriptor aligned size */ 266 /* descriptor aligned size */
267 #define MVNETA_DESC_ALIGNED_SIZE 32 267 #define MVNETA_DESC_ALIGNED_SIZE 32
268 268
269 struct mvneta_port { 269 struct mvneta_port {
270 void __iomem *base; 270 void __iomem *base;
271 struct mvneta_rx_queue *rxqs; 271 struct mvneta_rx_queue *rxqs;
272 struct mvneta_tx_queue *txqs; 272 struct mvneta_tx_queue *txqs;
273 273
274 u8 mcast_count[256]; 274 u8 mcast_count[256];
275 u16 tx_ring_size; 275 u16 tx_ring_size;
276 u16 rx_ring_size; 276 u16 rx_ring_size;
277 277
278 phy_interface_t phy_interface; 278 phy_interface_t phy_interface;
279 unsigned int link; 279 unsigned int link;
280 unsigned int duplex; 280 unsigned int duplex;
281 unsigned int speed; 281 unsigned int speed;
282 282
283 int init; 283 int init;
284 int phyaddr; 284 int phyaddr;
285 struct phy_device *phydev; 285 struct phy_device *phydev;
286 struct mii_dev *bus; 286 struct mii_dev *bus;
287 }; 287 };
288 288
289 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 289 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
290 * layout of the transmit and reception DMA descriptors, and their 290 * layout of the transmit and reception DMA descriptors, and their
291 * layout is therefore defined by the hardware design 291 * layout is therefore defined by the hardware design
292 */ 292 */
293 293
294 #define MVNETA_TX_L3_OFF_SHIFT 0 294 #define MVNETA_TX_L3_OFF_SHIFT 0
295 #define MVNETA_TX_IP_HLEN_SHIFT 8 295 #define MVNETA_TX_IP_HLEN_SHIFT 8
296 #define MVNETA_TX_L4_UDP BIT(16) 296 #define MVNETA_TX_L4_UDP BIT(16)
297 #define MVNETA_TX_L3_IP6 BIT(17) 297 #define MVNETA_TX_L3_IP6 BIT(17)
298 #define MVNETA_TXD_IP_CSUM BIT(18) 298 #define MVNETA_TXD_IP_CSUM BIT(18)
299 #define MVNETA_TXD_Z_PAD BIT(19) 299 #define MVNETA_TXD_Z_PAD BIT(19)
300 #define MVNETA_TXD_L_DESC BIT(20) 300 #define MVNETA_TXD_L_DESC BIT(20)
301 #define MVNETA_TXD_F_DESC BIT(21) 301 #define MVNETA_TXD_F_DESC BIT(21)
302 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 302 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
303 MVNETA_TXD_L_DESC | \ 303 MVNETA_TXD_L_DESC | \
304 MVNETA_TXD_F_DESC) 304 MVNETA_TXD_F_DESC)
305 #define MVNETA_TX_L4_CSUM_FULL BIT(30) 305 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
306 #define MVNETA_TX_L4_CSUM_NOT BIT(31) 306 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
307 307
308 #define MVNETA_RXD_ERR_CRC 0x0 308 #define MVNETA_RXD_ERR_CRC 0x0
309 #define MVNETA_RXD_ERR_SUMMARY BIT(16) 309 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
310 #define MVNETA_RXD_ERR_OVERRUN BIT(17) 310 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
311 #define MVNETA_RXD_ERR_LEN BIT(18) 311 #define MVNETA_RXD_ERR_LEN BIT(18)
312 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 312 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
313 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 313 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
314 #define MVNETA_RXD_L3_IP4 BIT(25) 314 #define MVNETA_RXD_L3_IP4 BIT(25)
315 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 315 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
316 #define MVNETA_RXD_L4_CSUM_OK BIT(30) 316 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
317 317
318 struct mvneta_tx_desc { 318 struct mvneta_tx_desc {
319 u32 command; /* Options used by HW for packet transmitting.*/ 319 u32 command; /* Options used by HW for packet transmitting.*/
320 u16 reserverd1; /* csum_l4 (for future use) */ 320 u16 reserverd1; /* csum_l4 (for future use) */
321 u16 data_size; /* Data size of transmitted packet in bytes */ 321 u16 data_size; /* Data size of transmitted packet in bytes */
322 u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 322 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
323 u32 reserved2; /* hw_cmd - (for future use, PMT) */ 323 u32 reserved2; /* hw_cmd - (for future use, PMT) */
324 u32 reserved3[4]; /* Reserved - (for future use) */ 324 u32 reserved3[4]; /* Reserved - (for future use) */
325 }; 325 };
326 326
327 struct mvneta_rx_desc { 327 struct mvneta_rx_desc {
328 u32 status; /* Info about received packet */ 328 u32 status; /* Info about received packet */
329 u16 reserved1; /* pnc_info - (for future use, PnC) */ 329 u16 reserved1; /* pnc_info - (for future use, PnC) */
330 u16 data_size; /* Size of received packet in bytes */ 330 u16 data_size; /* Size of received packet in bytes */
331 331
332 u32 buf_phys_addr; /* Physical address of the buffer */ 332 u32 buf_phys_addr; /* Physical address of the buffer */
333 u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 333 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
334 334
335 u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 335 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
336 u16 reserved3; /* prefetch_cmd, for future use */ 336 u16 reserved3; /* prefetch_cmd, for future use */
337 u16 reserved4; /* csum_l4 - (for future use, PnC) */ 337 u16 reserved4; /* csum_l4 - (for future use, PnC) */
338 338
339 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 339 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
340 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 340 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
341 }; 341 };
342 342
343 struct mvneta_tx_queue { 343 struct mvneta_tx_queue {
344 /* Number of this TX queue, in the range 0-7 */ 344 /* Number of this TX queue, in the range 0-7 */
345 u8 id; 345 u8 id;
346 346
347 /* Number of TX DMA descriptors in the descriptor ring */ 347 /* Number of TX DMA descriptors in the descriptor ring */
348 int size; 348 int size;
349 349
350 /* Index of last TX DMA descriptor that was inserted */ 350 /* Index of last TX DMA descriptor that was inserted */
351 int txq_put_index; 351 int txq_put_index;
352 352
353 /* Index of the TX DMA descriptor to be cleaned up */ 353 /* Index of the TX DMA descriptor to be cleaned up */
354 int txq_get_index; 354 int txq_get_index;
355 355
356 /* Virtual address of the TX DMA descriptors array */ 356 /* Virtual address of the TX DMA descriptors array */
357 struct mvneta_tx_desc *descs; 357 struct mvneta_tx_desc *descs;
358 358
359 /* DMA address of the TX DMA descriptors array */ 359 /* DMA address of the TX DMA descriptors array */
360 dma_addr_t descs_phys; 360 dma_addr_t descs_phys;
361 361
362 /* Index of the last TX DMA descriptor */ 362 /* Index of the last TX DMA descriptor */
363 int last_desc; 363 int last_desc;
364 364
365 /* Index of the next TX DMA descriptor to process */ 365 /* Index of the next TX DMA descriptor to process */
366 int next_desc_to_proc; 366 int next_desc_to_proc;
367 }; 367 };
368 368
369 struct mvneta_rx_queue { 369 struct mvneta_rx_queue {
370 /* rx queue number, in the range 0-7 */ 370 /* rx queue number, in the range 0-7 */
371 u8 id; 371 u8 id;
372 372
373 /* num of rx descriptors in the rx descriptor ring */ 373 /* num of rx descriptors in the rx descriptor ring */
374 int size; 374 int size;
375 375
376 /* Virtual address of the RX DMA descriptors array */ 376 /* Virtual address of the RX DMA descriptors array */
377 struct mvneta_rx_desc *descs; 377 struct mvneta_rx_desc *descs;
378 378
379 /* DMA address of the RX DMA descriptors array */ 379 /* DMA address of the RX DMA descriptors array */
380 dma_addr_t descs_phys; 380 dma_addr_t descs_phys;
381 381
382 /* Index of the last RX DMA descriptor */ 382 /* Index of the last RX DMA descriptor */
383 int last_desc; 383 int last_desc;
384 384
385 /* Index of the next RX DMA descriptor to process */ 385 /* Index of the next RX DMA descriptor to process */
386 int next_desc_to_proc; 386 int next_desc_to_proc;
387 }; 387 };
388 388
389 /* U-Boot doesn't use the queues, so set the number to 1 */ 389 /* U-Boot doesn't use the queues, so set the number to 1 */
390 static int rxq_number = 1; 390 static int rxq_number = 1;
391 static int txq_number = 1; 391 static int txq_number = 1;
392 static int rxq_def; 392 static int rxq_def;
393 393
394 struct buffer_location { 394 struct buffer_location {
395 struct mvneta_tx_desc *tx_descs; 395 struct mvneta_tx_desc *tx_descs;
396 struct mvneta_rx_desc *rx_descs; 396 struct mvneta_rx_desc *rx_descs;
397 u32 rx_buffers; 397 u32 rx_buffers;
398 }; 398 };
399 399
400 /* 400 /*
401 * All 4 interfaces use the same global buffer, since only one interface 401 * All 4 interfaces use the same global buffer, since only one interface
402 * can be enabled at once 402 * can be enabled at once
403 */ 403 */
404 static struct buffer_location buffer_loc; 404 static struct buffer_location buffer_loc;
405 405
406 /* 406 /*
407 * Page table entries are set to 1MB, or multiples of 1MB 407 * Page table entries are set to 1MB, or multiples of 1MB
408 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 408 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
409 */ 409 */
410 #define BD_SPACE (1 << 20) 410 #define BD_SPACE (1 << 20)
411 411
412 /* 412 /*
413 * Dummy implementation that can be overwritten by a board 413 * Dummy implementation that can be overwritten by a board
414 * specific function 414 * specific function
415 */ 415 */
416 __weak int board_network_enable(struct mii_dev *bus) 416 __weak int board_network_enable(struct mii_dev *bus)
417 { 417 {
418 return 0; 418 return 0;
419 } 419 }
420 420
421 /* Utility/helper methods */ 421 /* Utility/helper methods */
422 422
423 /* Write helper method */ 423 /* Write helper method */
424 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 424 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
425 { 425 {
426 writel(data, pp->base + offset); 426 writel(data, pp->base + offset);
427 } 427 }
428 428
429 /* Read helper method */ 429 /* Read helper method */
430 static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 430 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
431 { 431 {
432 return readl(pp->base + offset); 432 return readl(pp->base + offset);
433 } 433 }
434 434
435 /* Clear all MIB counters */ 435 /* Clear all MIB counters */
436 static void mvneta_mib_counters_clear(struct mvneta_port *pp) 436 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
437 { 437 {
438 int i; 438 int i;
439 439
440 /* Perform dummy reads from MIB counters */ 440 /* Perform dummy reads from MIB counters */
441 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 441 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
442 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 442 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
443 } 443 }
444 444
445 /* Rx descriptors helper methods */ 445 /* Rx descriptors helper methods */
446 446
447 /* Checks whether the RX descriptor having this status is both the first 447 /* Checks whether the RX descriptor having this status is both the first
448 * and the last descriptor for the RX packet. Each RX packet is currently 448 * and the last descriptor for the RX packet. Each RX packet is currently
449 * received through a single RX descriptor, so not having each RX 449 * received through a single RX descriptor, so not having each RX
450 * descriptor with its first and last bits set is an error 450 * descriptor with its first and last bits set is an error
451 */ 451 */
452 static int mvneta_rxq_desc_is_first_last(u32 status) 452 static int mvneta_rxq_desc_is_first_last(u32 status)
453 { 453 {
454 return (status & MVNETA_RXD_FIRST_LAST_DESC) == 454 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
455 MVNETA_RXD_FIRST_LAST_DESC; 455 MVNETA_RXD_FIRST_LAST_DESC;
456 } 456 }
457 457
458 /* Add number of descriptors ready to receive new packets */ 458 /* Add number of descriptors ready to receive new packets */
459 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 459 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
460 struct mvneta_rx_queue *rxq, 460 struct mvneta_rx_queue *rxq,
461 int ndescs) 461 int ndescs)
462 { 462 {
463 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 463 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
464 * be added at once 464 * be added at once
465 */ 465 */
466 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 466 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
467 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 467 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
468 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 468 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
469 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 469 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
470 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 470 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
471 } 471 }
472 472
473 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 473 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
474 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 474 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
475 } 475 }
476 476
477 /* Get number of RX descriptors occupied by received packets */ 477 /* Get number of RX descriptors occupied by received packets */
478 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 478 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
479 struct mvneta_rx_queue *rxq) 479 struct mvneta_rx_queue *rxq)
480 { 480 {
481 u32 val; 481 u32 val;
482 482
483 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 483 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
484 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 484 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
485 } 485 }
486 486
487 /* Update num of rx desc called upon return from rx path or 487 /* Update num of rx desc called upon return from rx path or
488 * from mvneta_rxq_drop_pkts(). 488 * from mvneta_rxq_drop_pkts().
489 */ 489 */
490 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 490 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
491 struct mvneta_rx_queue *rxq, 491 struct mvneta_rx_queue *rxq,
492 int rx_done, int rx_filled) 492 int rx_done, int rx_filled)
493 { 493 {
494 u32 val; 494 u32 val;
495 495
496 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 496 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
497 val = rx_done | 497 val = rx_done |
498 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 498 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
499 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 499 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
500 return; 500 return;
501 } 501 }
502 502
503 /* Only 255 descriptors can be added at once */ 503 /* Only 255 descriptors can be added at once */
504 while ((rx_done > 0) || (rx_filled > 0)) { 504 while ((rx_done > 0) || (rx_filled > 0)) {
505 if (rx_done <= 0xff) { 505 if (rx_done <= 0xff) {
506 val = rx_done; 506 val = rx_done;
507 rx_done = 0; 507 rx_done = 0;
508 } else { 508 } else {
509 val = 0xff; 509 val = 0xff;
510 rx_done -= 0xff; 510 rx_done -= 0xff;
511 } 511 }
512 if (rx_filled <= 0xff) { 512 if (rx_filled <= 0xff) {
513 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 513 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
514 rx_filled = 0; 514 rx_filled = 0;
515 } else { 515 } else {
516 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 516 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
517 rx_filled -= 0xff; 517 rx_filled -= 0xff;
518 } 518 }
519 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 519 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
520 } 520 }
521 } 521 }
522 522
523 /* Get pointer to next RX descriptor to be processed by SW */ 523 /* Get pointer to next RX descriptor to be processed by SW */
524 static struct mvneta_rx_desc * 524 static struct mvneta_rx_desc *
525 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 525 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
526 { 526 {
527 int rx_desc = rxq->next_desc_to_proc; 527 int rx_desc = rxq->next_desc_to_proc;
528 528
529 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 529 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
530 return rxq->descs + rx_desc; 530 return rxq->descs + rx_desc;
531 } 531 }
532 532
533 /* Tx descriptors helper methods */ 533 /* Tx descriptors helper methods */
534 534
535 /* Update HW with number of TX descriptors to be sent */ 535 /* Update HW with number of TX descriptors to be sent */
536 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 536 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
537 struct mvneta_tx_queue *txq, 537 struct mvneta_tx_queue *txq,
538 int pend_desc) 538 int pend_desc)
539 { 539 {
540 u32 val; 540 u32 val;
541 541
542 /* Only 255 descriptors can be added at once ; Assume caller 542 /* Only 255 descriptors can be added at once ; Assume caller
543 * process TX desriptors in quanta less than 256 543 * process TX descriptors in quanta less than 256
544 */ 544 */
545 val = pend_desc; 545 val = pend_desc;
546 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 546 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
547 } 547 }
548 548
549 /* Get pointer to next TX descriptor to be processed (send) by HW */ 549 /* Get pointer to next TX descriptor to be processed (send) by HW */
550 static struct mvneta_tx_desc * 550 static struct mvneta_tx_desc *
551 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 551 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
552 { 552 {
553 int tx_desc = txq->next_desc_to_proc; 553 int tx_desc = txq->next_desc_to_proc;
554 554
555 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 555 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
556 return txq->descs + tx_desc; 556 return txq->descs + tx_desc;
557 } 557 }
558 558
559 /* Set rxq buf size */ 559 /* Set rxq buf size */
560 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 560 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
561 struct mvneta_rx_queue *rxq, 561 struct mvneta_rx_queue *rxq,
562 int buf_size) 562 int buf_size)
563 { 563 {
564 u32 val; 564 u32 val;
565 565
566 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 566 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
567 567
568 val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 568 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
569 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 569 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
570 570
571 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 571 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
572 } 572 }
573 573
574 static int mvneta_port_is_fixed_link(struct mvneta_port *pp) 574 static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
575 { 575 {
576 /* phy_addr is set to invalid value for fixed link */ 576 /* phy_addr is set to invalid value for fixed link */
577 return pp->phyaddr > PHY_MAX_ADDR; 577 return pp->phyaddr > PHY_MAX_ADDR;
578 } 578 }
579 579
580 580
581 /* Start the Ethernet port RX and TX activity */ 581 /* Start the Ethernet port RX and TX activity */
582 static void mvneta_port_up(struct mvneta_port *pp) 582 static void mvneta_port_up(struct mvneta_port *pp)
583 { 583 {
584 int queue; 584 int queue;
585 u32 q_map; 585 u32 q_map;
586 586
587 /* Enable all initialized TXs. */ 587 /* Enable all initialized TXs. */
588 mvneta_mib_counters_clear(pp); 588 mvneta_mib_counters_clear(pp);
589 q_map = 0; 589 q_map = 0;
590 for (queue = 0; queue < txq_number; queue++) { 590 for (queue = 0; queue < txq_number; queue++) {
591 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 591 struct mvneta_tx_queue *txq = &pp->txqs[queue];
592 if (txq->descs != NULL) 592 if (txq->descs != NULL)
593 q_map |= (1 << queue); 593 q_map |= (1 << queue);
594 } 594 }
595 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 595 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
596 596
597 /* Enable all initialized RXQs. */ 597 /* Enable all initialized RXQs. */
598 q_map = 0; 598 q_map = 0;
599 for (queue = 0; queue < rxq_number; queue++) { 599 for (queue = 0; queue < rxq_number; queue++) {
600 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 600 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
601 if (rxq->descs != NULL) 601 if (rxq->descs != NULL)
602 q_map |= (1 << queue); 602 q_map |= (1 << queue);
603 } 603 }
604 mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 604 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
605 } 605 }
606 606
607 /* Stop the Ethernet port activity */ 607 /* Stop the Ethernet port activity */
608 static void mvneta_port_down(struct mvneta_port *pp) 608 static void mvneta_port_down(struct mvneta_port *pp)
609 { 609 {
610 u32 val; 610 u32 val;
611 int count; 611 int count;
612 612
613 /* Stop Rx port activity. Check port Rx activity. */ 613 /* Stop Rx port activity. Check port Rx activity. */
614 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 614 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
615 615
616 /* Issue stop command for active channels only */ 616 /* Issue stop command for active channels only */
617 if (val != 0) 617 if (val != 0)
618 mvreg_write(pp, MVNETA_RXQ_CMD, 618 mvreg_write(pp, MVNETA_RXQ_CMD,
619 val << MVNETA_RXQ_DISABLE_SHIFT); 619 val << MVNETA_RXQ_DISABLE_SHIFT);
620 620
621 /* Wait for all Rx activity to terminate. */ 621 /* Wait for all Rx activity to terminate. */
622 count = 0; 622 count = 0;
623 do { 623 do {
624 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 624 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
625 netdev_warn(pp->dev, 625 netdev_warn(pp->dev,
626 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", 626 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
627 val); 627 val);
628 break; 628 break;
629 } 629 }
630 mdelay(1); 630 mdelay(1);
631 631
632 val = mvreg_read(pp, MVNETA_RXQ_CMD); 632 val = mvreg_read(pp, MVNETA_RXQ_CMD);
633 } while (val & 0xff); 633 } while (val & 0xff);
634 634
635 /* Stop Tx port activity. Check port Tx activity. Issue stop 635 /* Stop Tx port activity. Check port Tx activity. Issue stop
636 * command for active channels only 636 * command for active channels only
637 */ 637 */
638 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 638 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
639 639
640 if (val != 0) 640 if (val != 0)
641 mvreg_write(pp, MVNETA_TXQ_CMD, 641 mvreg_write(pp, MVNETA_TXQ_CMD,
642 (val << MVNETA_TXQ_DISABLE_SHIFT)); 642 (val << MVNETA_TXQ_DISABLE_SHIFT));
643 643
644 /* Wait for all Tx activity to terminate. */ 644 /* Wait for all Tx activity to terminate. */
645 count = 0; 645 count = 0;
646 do { 646 do {
647 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 647 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
648 netdev_warn(pp->dev, 648 netdev_warn(pp->dev,
649 "TIMEOUT for TX stopped status=0x%08x\n", 649 "TIMEOUT for TX stopped status=0x%08x\n",
650 val); 650 val);
651 break; 651 break;
652 } 652 }
653 mdelay(1); 653 mdelay(1);
654 654
655 /* Check TX Command reg that all Txqs are stopped */ 655 /* Check TX Command reg that all Txqs are stopped */
656 val = mvreg_read(pp, MVNETA_TXQ_CMD); 656 val = mvreg_read(pp, MVNETA_TXQ_CMD);
657 657
658 } while (val & 0xff); 658 } while (val & 0xff);
659 659
660 /* Double check to verify that TX FIFO is empty */ 660 /* Double check to verify that TX FIFO is empty */
661 count = 0; 661 count = 0;
662 do { 662 do {
663 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 663 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
664 netdev_warn(pp->dev, 664 netdev_warn(pp->dev,
665 "TX FIFO empty timeout status=0x08%x\n", 665 "TX FIFO empty timeout status=0x08%x\n",
666 val); 666 val);
667 break; 667 break;
668 } 668 }
669 mdelay(1); 669 mdelay(1);
670 670
671 val = mvreg_read(pp, MVNETA_PORT_STATUS); 671 val = mvreg_read(pp, MVNETA_PORT_STATUS);
672 } while (!(val & MVNETA_TX_FIFO_EMPTY) && 672 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
673 (val & MVNETA_TX_IN_PRGRS)); 673 (val & MVNETA_TX_IN_PRGRS));
674 674
675 udelay(200); 675 udelay(200);
676 } 676 }
677 677
678 /* Enable the port by setting the port enable bit of the MAC control register */ 678 /* Enable the port by setting the port enable bit of the MAC control register */
679 static void mvneta_port_enable(struct mvneta_port *pp) 679 static void mvneta_port_enable(struct mvneta_port *pp)
680 { 680 {
681 u32 val; 681 u32 val;
682 682
683 /* Enable port */ 683 /* Enable port */
684 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 684 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
685 val |= MVNETA_GMAC0_PORT_ENABLE; 685 val |= MVNETA_GMAC0_PORT_ENABLE;
686 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 686 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
687 } 687 }
688 688
689 /* Disable the port and wait for about 200 usec before retuning */ 689 /* Disable the port and wait for about 200 usec before retuning */
690 static void mvneta_port_disable(struct mvneta_port *pp) 690 static void mvneta_port_disable(struct mvneta_port *pp)
691 { 691 {
692 u32 val; 692 u32 val;
693 693
694 /* Reset the Enable bit in the Serial Control Register */ 694 /* Reset the Enable bit in the Serial Control Register */
695 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 695 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
696 val &= ~MVNETA_GMAC0_PORT_ENABLE; 696 val &= ~MVNETA_GMAC0_PORT_ENABLE;
697 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 697 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
698 698
699 udelay(200); 699 udelay(200);
700 } 700 }
701 701
702 /* Multicast tables methods */ 702 /* Multicast tables methods */
703 703
704 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 704 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
705 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 705 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
706 { 706 {
707 int offset; 707 int offset;
708 u32 val; 708 u32 val;
709 709
710 if (queue == -1) { 710 if (queue == -1) {
711 val = 0; 711 val = 0;
712 } else { 712 } else {
713 val = 0x1 | (queue << 1); 713 val = 0x1 | (queue << 1);
714 val |= (val << 24) | (val << 16) | (val << 8); 714 val |= (val << 24) | (val << 16) | (val << 8);
715 } 715 }
716 716
717 for (offset = 0; offset <= 0xc; offset += 4) 717 for (offset = 0; offset <= 0xc; offset += 4)
718 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 718 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
719 } 719 }
720 720
721 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 721 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
722 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 722 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
723 { 723 {
724 int offset; 724 int offset;
725 u32 val; 725 u32 val;
726 726
727 if (queue == -1) { 727 if (queue == -1) {
728 val = 0; 728 val = 0;
729 } else { 729 } else {
730 val = 0x1 | (queue << 1); 730 val = 0x1 | (queue << 1);
731 val |= (val << 24) | (val << 16) | (val << 8); 731 val |= (val << 24) | (val << 16) | (val << 8);
732 } 732 }
733 733
734 for (offset = 0; offset <= 0xfc; offset += 4) 734 for (offset = 0; offset <= 0xfc; offset += 4)
735 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 735 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
736 } 736 }
737 737
738 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 738 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
739 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 739 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
740 { 740 {
741 int offset; 741 int offset;
742 u32 val; 742 u32 val;
743 743
744 if (queue == -1) { 744 if (queue == -1) {
745 memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 745 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
746 val = 0; 746 val = 0;
747 } else { 747 } else {
748 memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 748 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
749 val = 0x1 | (queue << 1); 749 val = 0x1 | (queue << 1);
750 val |= (val << 24) | (val << 16) | (val << 8); 750 val |= (val << 24) | (val << 16) | (val << 8);
751 } 751 }
752 752
753 for (offset = 0; offset <= 0xfc; offset += 4) 753 for (offset = 0; offset <= 0xfc; offset += 4)
754 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 754 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
755 } 755 }
756 756
757 /* This method sets defaults to the NETA port: 757 /* This method sets defaults to the NETA port:
758 * Clears interrupt Cause and Mask registers. 758 * Clears interrupt Cause and Mask registers.
759 * Clears all MAC tables. 759 * Clears all MAC tables.
760 * Sets defaults to all registers. 760 * Sets defaults to all registers.
761 * Resets RX and TX descriptor rings. 761 * Resets RX and TX descriptor rings.
762 * Resets PHY. 762 * Resets PHY.
763 * This method can be called after mvneta_port_down() to return the port 763 * This method can be called after mvneta_port_down() to return the port
764 * settings to defaults. 764 * settings to defaults.
765 */ 765 */
766 static void mvneta_defaults_set(struct mvneta_port *pp) 766 static void mvneta_defaults_set(struct mvneta_port *pp)
767 { 767 {
768 int cpu; 768 int cpu;
769 int queue; 769 int queue;
770 u32 val; 770 u32 val;
771 771
772 /* Clear all Cause registers */ 772 /* Clear all Cause registers */
773 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 773 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
774 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 774 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
775 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 775 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
776 776
777 /* Mask all interrupts */ 777 /* Mask all interrupts */
778 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 778 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
779 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 779 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
780 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 780 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
781 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 781 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
782 782
783 /* Enable MBUS Retry bit16 */ 783 /* Enable MBUS Retry bit16 */
784 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 784 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
785 785
786 /* Set CPU queue access map - all CPUs have access to all RX 786 /* Set CPU queue access map - all CPUs have access to all RX
787 * queues and to all TX queues 787 * queues and to all TX queues
788 */ 788 */
789 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) 789 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
790 mvreg_write(pp, MVNETA_CPU_MAP(cpu), 790 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
791 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | 791 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
792 MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); 792 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
793 793
794 /* Reset RX and TX DMAs */ 794 /* Reset RX and TX DMAs */
795 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 795 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
796 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 796 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
797 797
798 /* Disable Legacy WRR, Disable EJP, Release from reset */ 798 /* Disable Legacy WRR, Disable EJP, Release from reset */
799 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 799 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
800 for (queue = 0; queue < txq_number; queue++) { 800 for (queue = 0; queue < txq_number; queue++) {
801 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 801 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
802 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 802 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
803 } 803 }
804 804
805 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 805 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
806 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 806 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
807 807
808 /* Set Port Acceleration Mode */ 808 /* Set Port Acceleration Mode */
809 val = MVNETA_ACC_MODE_EXT; 809 val = MVNETA_ACC_MODE_EXT;
810 mvreg_write(pp, MVNETA_ACC_MODE, val); 810 mvreg_write(pp, MVNETA_ACC_MODE, val);
811 811
812 /* Update val of portCfg register accordingly with all RxQueue types */ 812 /* Update val of portCfg register accordingly with all RxQueue types */
813 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); 813 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
814 mvreg_write(pp, MVNETA_PORT_CONFIG, val); 814 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
815 815
816 val = 0; 816 val = 0;
817 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 817 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
818 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 818 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
819 819
820 /* Build PORT_SDMA_CONFIG_REG */ 820 /* Build PORT_SDMA_CONFIG_REG */
821 val = 0; 821 val = 0;
822 822
823 /* Default burst size */ 823 /* Default burst size */
824 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 824 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
825 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 825 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
826 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 826 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
827 827
828 /* Assign port SDMA configuration */ 828 /* Assign port SDMA configuration */
829 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 829 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
830 830
831 /* Enable PHY polling in hardware if not in fixed-link mode */ 831 /* Enable PHY polling in hardware if not in fixed-link mode */
832 if (!mvneta_port_is_fixed_link(pp)) { 832 if (!mvneta_port_is_fixed_link(pp)) {
833 val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 833 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
834 val |= MVNETA_PHY_POLLING_ENABLE; 834 val |= MVNETA_PHY_POLLING_ENABLE;
835 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 835 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
836 } 836 }
837 837
838 mvneta_set_ucast_table(pp, -1); 838 mvneta_set_ucast_table(pp, -1);
839 mvneta_set_special_mcast_table(pp, -1); 839 mvneta_set_special_mcast_table(pp, -1);
840 mvneta_set_other_mcast_table(pp, -1); 840 mvneta_set_other_mcast_table(pp, -1);
841 } 841 }
842 842
843 /* Set unicast address */ 843 /* Set unicast address */
844 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 844 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
845 int queue) 845 int queue)
846 { 846 {
847 unsigned int unicast_reg; 847 unsigned int unicast_reg;
848 unsigned int tbl_offset; 848 unsigned int tbl_offset;
849 unsigned int reg_offset; 849 unsigned int reg_offset;
850 850
851 /* Locate the Unicast table entry */ 851 /* Locate the Unicast table entry */
852 last_nibble = (0xf & last_nibble); 852 last_nibble = (0xf & last_nibble);
853 853
854 /* offset from unicast tbl base */ 854 /* offset from unicast tbl base */
855 tbl_offset = (last_nibble / 4) * 4; 855 tbl_offset = (last_nibble / 4) * 4;
856 856
857 /* offset within the above reg */ 857 /* offset within the above reg */
858 reg_offset = last_nibble % 4; 858 reg_offset = last_nibble % 4;
859 859
860 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 860 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
861 861
862 if (queue == -1) { 862 if (queue == -1) {
863 /* Clear accepts frame bit at specified unicast DA tbl entry */ 863 /* Clear accepts frame bit at specified unicast DA tbl entry */
864 unicast_reg &= ~(0xff << (8 * reg_offset)); 864 unicast_reg &= ~(0xff << (8 * reg_offset));
865 } else { 865 } else {
866 unicast_reg &= ~(0xff << (8 * reg_offset)); 866 unicast_reg &= ~(0xff << (8 * reg_offset));
867 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 867 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
868 } 868 }
869 869
870 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 870 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
871 } 871 }
872 872
873 /* Set mac address */ 873 /* Set mac address */
874 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 874 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
875 int queue) 875 int queue)
876 { 876 {
877 unsigned int mac_h; 877 unsigned int mac_h;
878 unsigned int mac_l; 878 unsigned int mac_l;
879 879
880 if (queue != -1) { 880 if (queue != -1) {
881 mac_l = (addr[4] << 8) | (addr[5]); 881 mac_l = (addr[4] << 8) | (addr[5]);
882 mac_h = (addr[0] << 24) | (addr[1] << 16) | 882 mac_h = (addr[0] << 24) | (addr[1] << 16) |
883 (addr[2] << 8) | (addr[3] << 0); 883 (addr[2] << 8) | (addr[3] << 0);
884 884
885 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 885 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
886 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 886 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
887 } 887 }
888 888
889 /* Accept frames of this address */ 889 /* Accept frames of this address */
890 mvneta_set_ucast_addr(pp, addr[5], queue); 890 mvneta_set_ucast_addr(pp, addr[5], queue);
891 } 891 }
892 892
893 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 893 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
894 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 894 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
895 u32 phys_addr, u32 cookie) 895 u32 phys_addr, u32 cookie)
896 { 896 {
897 rx_desc->buf_cookie = cookie; 897 rx_desc->buf_cookie = cookie;
898 rx_desc->buf_phys_addr = phys_addr; 898 rx_desc->buf_phys_addr = phys_addr;
899 } 899 }
900 900
901 /* Decrement sent descriptors counter */ 901 /* Decrement sent descriptors counter */
902 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 902 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
903 struct mvneta_tx_queue *txq, 903 struct mvneta_tx_queue *txq,
904 int sent_desc) 904 int sent_desc)
905 { 905 {
906 u32 val; 906 u32 val;
907 907
908 /* Only 255 TX descriptors can be updated at once */ 908 /* Only 255 TX descriptors can be updated at once */
909 while (sent_desc > 0xff) { 909 while (sent_desc > 0xff) {
910 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 910 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
911 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 911 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
912 sent_desc = sent_desc - 0xff; 912 sent_desc = sent_desc - 0xff;
913 } 913 }
914 914
915 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 915 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
916 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 916 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
917 } 917 }
918 918
919 /* Get number of TX descriptors already sent by HW */ 919 /* Get number of TX descriptors already sent by HW */
920 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 920 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
921 struct mvneta_tx_queue *txq) 921 struct mvneta_tx_queue *txq)
922 { 922 {
923 u32 val; 923 u32 val;
924 int sent_desc; 924 int sent_desc;
925 925
926 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 926 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
927 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 927 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
928 MVNETA_TXQ_SENT_DESC_SHIFT; 928 MVNETA_TXQ_SENT_DESC_SHIFT;
929 929
930 return sent_desc; 930 return sent_desc;
931 } 931 }
932 932
933 /* Display more error info */ 933 /* Display more error info */
934 static void mvneta_rx_error(struct mvneta_port *pp, 934 static void mvneta_rx_error(struct mvneta_port *pp,
935 struct mvneta_rx_desc *rx_desc) 935 struct mvneta_rx_desc *rx_desc)
936 { 936 {
937 u32 status = rx_desc->status; 937 u32 status = rx_desc->status;
938 938
939 if (!mvneta_rxq_desc_is_first_last(status)) { 939 if (!mvneta_rxq_desc_is_first_last(status)) {
940 netdev_err(pp->dev, 940 netdev_err(pp->dev,
941 "bad rx status %08x (buffer oversize), size=%d\n", 941 "bad rx status %08x (buffer oversize), size=%d\n",
942 status, rx_desc->data_size); 942 status, rx_desc->data_size);
943 return; 943 return;
944 } 944 }
945 945
946 switch (status & MVNETA_RXD_ERR_CODE_MASK) { 946 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
947 case MVNETA_RXD_ERR_CRC: 947 case MVNETA_RXD_ERR_CRC:
948 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 948 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
949 status, rx_desc->data_size); 949 status, rx_desc->data_size);
950 break; 950 break;
951 case MVNETA_RXD_ERR_OVERRUN: 951 case MVNETA_RXD_ERR_OVERRUN:
952 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 952 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
953 status, rx_desc->data_size); 953 status, rx_desc->data_size);
954 break; 954 break;
955 case MVNETA_RXD_ERR_LEN: 955 case MVNETA_RXD_ERR_LEN:
956 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 956 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
957 status, rx_desc->data_size); 957 status, rx_desc->data_size);
958 break; 958 break;
959 case MVNETA_RXD_ERR_RESOURCE: 959 case MVNETA_RXD_ERR_RESOURCE:
960 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 960 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
961 status, rx_desc->data_size); 961 status, rx_desc->data_size);
962 break; 962 break;
963 } 963 }
964 } 964 }
965 965
966 static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, 966 static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
967 int rxq) 967 int rxq)
968 { 968 {
969 return &pp->rxqs[rxq]; 969 return &pp->rxqs[rxq];
970 } 970 }
971 971
972 972
973 /* Drop packets received by the RXQ and free buffers */ 973 /* Drop packets received by the RXQ and free buffers */
974 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 974 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
975 struct mvneta_rx_queue *rxq) 975 struct mvneta_rx_queue *rxq)
976 { 976 {
977 int rx_done; 977 int rx_done;
978 978
979 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 979 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
980 if (rx_done) 980 if (rx_done)
981 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 981 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
982 } 982 }
983 983
984 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 984 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
985 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 985 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
986 int num) 986 int num)
987 { 987 {
988 int i; 988 int i;
989 989
990 for (i = 0; i < num; i++) { 990 for (i = 0; i < num; i++) {
991 u32 addr; 991 u32 addr;
992 992
993 /* U-Boot special: Fill in the rx buffer addresses */ 993 /* U-Boot special: Fill in the rx buffer addresses */
994 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE); 994 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
995 mvneta_rx_desc_fill(rxq->descs + i, addr, addr); 995 mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
996 } 996 }
997 997
998 /* Add this number of RX descriptors as non occupied (ready to 998 /* Add this number of RX descriptors as non occupied (ready to
999 * get packets) 999 * get packets)
1000 */ 1000 */
1001 mvneta_rxq_non_occup_desc_add(pp, rxq, i); 1001 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1002 1002
1003 return 0; 1003 return 0;
1004 } 1004 }
1005 1005
1006 /* Rx/Tx queue initialization/cleanup methods */ 1006 /* Rx/Tx queue initialization/cleanup methods */
1007 1007
1008 /* Create a specified RX queue */ 1008 /* Create a specified RX queue */
1009 static int mvneta_rxq_init(struct mvneta_port *pp, 1009 static int mvneta_rxq_init(struct mvneta_port *pp,
1010 struct mvneta_rx_queue *rxq) 1010 struct mvneta_rx_queue *rxq)
1011 1011
1012 { 1012 {
1013 rxq->size = pp->rx_ring_size; 1013 rxq->size = pp->rx_ring_size;
1014 1014
1015 /* Allocate memory for RX descriptors */ 1015 /* Allocate memory for RX descriptors */
1016 rxq->descs_phys = (dma_addr_t)rxq->descs; 1016 rxq->descs_phys = (dma_addr_t)rxq->descs;
1017 if (rxq->descs == NULL) 1017 if (rxq->descs == NULL)
1018 return -ENOMEM; 1018 return -ENOMEM;
1019 1019
1020 rxq->last_desc = rxq->size - 1; 1020 rxq->last_desc = rxq->size - 1;
1021 1021
1022 /* Set Rx descriptors queue starting address */ 1022 /* Set Rx descriptors queue starting address */
1023 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 1023 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1024 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 1024 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1025 1025
1026 /* Fill RXQ with buffers from RX pool */ 1026 /* Fill RXQ with buffers from RX pool */
1027 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE); 1027 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
1028 mvneta_rxq_fill(pp, rxq, rxq->size); 1028 mvneta_rxq_fill(pp, rxq, rxq->size);
1029 1029
1030 return 0; 1030 return 0;
1031 } 1031 }
1032 1032
1033 /* Cleanup Rx queue */ 1033 /* Cleanup Rx queue */
1034 static void mvneta_rxq_deinit(struct mvneta_port *pp, 1034 static void mvneta_rxq_deinit(struct mvneta_port *pp,
1035 struct mvneta_rx_queue *rxq) 1035 struct mvneta_rx_queue *rxq)
1036 { 1036 {
1037 mvneta_rxq_drop_pkts(pp, rxq); 1037 mvneta_rxq_drop_pkts(pp, rxq);
1038 1038
1039 rxq->descs = NULL; 1039 rxq->descs = NULL;
1040 rxq->last_desc = 0; 1040 rxq->last_desc = 0;
1041 rxq->next_desc_to_proc = 0; 1041 rxq->next_desc_to_proc = 0;
1042 rxq->descs_phys = 0; 1042 rxq->descs_phys = 0;
1043 } 1043 }
1044 1044
1045 /* Create and initialize a tx queue */ 1045 /* Create and initialize a tx queue */
1046 static int mvneta_txq_init(struct mvneta_port *pp, 1046 static int mvneta_txq_init(struct mvneta_port *pp,
1047 struct mvneta_tx_queue *txq) 1047 struct mvneta_tx_queue *txq)
1048 { 1048 {
1049 txq->size = pp->tx_ring_size; 1049 txq->size = pp->tx_ring_size;
1050 1050
1051 /* Allocate memory for TX descriptors */ 1051 /* Allocate memory for TX descriptors */
1052 txq->descs_phys = (dma_addr_t)txq->descs; 1052 txq->descs_phys = (dma_addr_t)txq->descs;
1053 if (txq->descs == NULL) 1053 if (txq->descs == NULL)
1054 return -ENOMEM; 1054 return -ENOMEM;
1055 1055
1056 txq->last_desc = txq->size - 1; 1056 txq->last_desc = txq->size - 1;
1057 1057
1058 /* Set maximum bandwidth for enabled TXQs */ 1058 /* Set maximum bandwidth for enabled TXQs */
1059 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 1059 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
1060 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 1060 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
1061 1061
1062 /* Set Tx descriptors queue starting address */ 1062 /* Set Tx descriptors queue starting address */
1063 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 1063 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
1064 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 1064 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
1065 1065
1066 return 0; 1066 return 0;
1067 } 1067 }
1068 1068
1069 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 1069 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
1070 static void mvneta_txq_deinit(struct mvneta_port *pp, 1070 static void mvneta_txq_deinit(struct mvneta_port *pp,
1071 struct mvneta_tx_queue *txq) 1071 struct mvneta_tx_queue *txq)
1072 { 1072 {
1073 txq->descs = NULL; 1073 txq->descs = NULL;
1074 txq->last_desc = 0; 1074 txq->last_desc = 0;
1075 txq->next_desc_to_proc = 0; 1075 txq->next_desc_to_proc = 0;
1076 txq->descs_phys = 0; 1076 txq->descs_phys = 0;
1077 1077
1078 /* Set minimum bandwidth for disabled TXQs */ 1078 /* Set minimum bandwidth for disabled TXQs */
1079 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 1079 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
1080 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 1080 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
1081 1081
1082 /* Set Tx descriptors queue starting address and size */ 1082 /* Set Tx descriptors queue starting address and size */
1083 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 1083 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
1084 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 1084 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
1085 } 1085 }
1086 1086
1087 /* Cleanup all Tx queues */ 1087 /* Cleanup all Tx queues */
1088 static void mvneta_cleanup_txqs(struct mvneta_port *pp) 1088 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
1089 { 1089 {
1090 int queue; 1090 int queue;
1091 1091
1092 for (queue = 0; queue < txq_number; queue++) 1092 for (queue = 0; queue < txq_number; queue++)
1093 mvneta_txq_deinit(pp, &pp->txqs[queue]); 1093 mvneta_txq_deinit(pp, &pp->txqs[queue]);
1094 } 1094 }
1095 1095
1096 /* Cleanup all Rx queues */ 1096 /* Cleanup all Rx queues */
1097 static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 1097 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
1098 { 1098 {
1099 int queue; 1099 int queue;
1100 1100
1101 for (queue = 0; queue < rxq_number; queue++) 1101 for (queue = 0; queue < rxq_number; queue++)
1102 mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 1102 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
1103 } 1103 }
1104 1104
1105 1105
1106 /* Init all Rx queues */ 1106 /* Init all Rx queues */
1107 static int mvneta_setup_rxqs(struct mvneta_port *pp) 1107 static int mvneta_setup_rxqs(struct mvneta_port *pp)
1108 { 1108 {
1109 int queue; 1109 int queue;
1110 1110
1111 for (queue = 0; queue < rxq_number; queue++) { 1111 for (queue = 0; queue < rxq_number; queue++) {
1112 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 1112 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
1113 if (err) { 1113 if (err) {
1114 netdev_err(pp->dev, "%s: can't create rxq=%d\n", 1114 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
1115 __func__, queue); 1115 __func__, queue);
1116 mvneta_cleanup_rxqs(pp); 1116 mvneta_cleanup_rxqs(pp);
1117 return err; 1117 return err;
1118 } 1118 }
1119 } 1119 }
1120 1120
1121 return 0; 1121 return 0;
1122 } 1122 }
1123 1123
1124 /* Init all tx queues */ 1124 /* Init all tx queues */
1125 static int mvneta_setup_txqs(struct mvneta_port *pp) 1125 static int mvneta_setup_txqs(struct mvneta_port *pp)
1126 { 1126 {
1127 int queue; 1127 int queue;
1128 1128
1129 for (queue = 0; queue < txq_number; queue++) { 1129 for (queue = 0; queue < txq_number; queue++) {
1130 int err = mvneta_txq_init(pp, &pp->txqs[queue]); 1130 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
1131 if (err) { 1131 if (err) {
1132 netdev_err(pp->dev, "%s: can't create txq=%d\n", 1132 netdev_err(pp->dev, "%s: can't create txq=%d\n",
1133 __func__, queue); 1133 __func__, queue);
1134 mvneta_cleanup_txqs(pp); 1134 mvneta_cleanup_txqs(pp);
1135 return err; 1135 return err;
1136 } 1136 }
1137 } 1137 }
1138 1138
1139 return 0; 1139 return 0;
1140 } 1140 }
1141 1141
1142 static void mvneta_start_dev(struct mvneta_port *pp) 1142 static void mvneta_start_dev(struct mvneta_port *pp)
1143 { 1143 {
1144 /* start the Rx/Tx activity */ 1144 /* start the Rx/Tx activity */
1145 mvneta_port_enable(pp); 1145 mvneta_port_enable(pp);
1146 } 1146 }
1147 1147
1148 static void mvneta_adjust_link(struct udevice *dev) 1148 static void mvneta_adjust_link(struct udevice *dev)
1149 { 1149 {
1150 struct mvneta_port *pp = dev_get_priv(dev); 1150 struct mvneta_port *pp = dev_get_priv(dev);
1151 struct phy_device *phydev = pp->phydev; 1151 struct phy_device *phydev = pp->phydev;
1152 int status_change = 0; 1152 int status_change = 0;
1153 1153
1154 if (mvneta_port_is_fixed_link(pp)) { 1154 if (mvneta_port_is_fixed_link(pp)) {
1155 debug("Using fixed link, skip link adjust\n"); 1155 debug("Using fixed link, skip link adjust\n");
1156 return; 1156 return;
1157 } 1157 }
1158 1158
1159 if (phydev->link) { 1159 if (phydev->link) {
1160 if ((pp->speed != phydev->speed) || 1160 if ((pp->speed != phydev->speed) ||
1161 (pp->duplex != phydev->duplex)) { 1161 (pp->duplex != phydev->duplex)) {
1162 u32 val; 1162 u32 val;
1163 1163
1164 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1164 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1165 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 1165 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
1166 MVNETA_GMAC_CONFIG_GMII_SPEED | 1166 MVNETA_GMAC_CONFIG_GMII_SPEED |
1167 MVNETA_GMAC_CONFIG_FULL_DUPLEX | 1167 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
1168 MVNETA_GMAC_AN_SPEED_EN | 1168 MVNETA_GMAC_AN_SPEED_EN |
1169 MVNETA_GMAC_AN_DUPLEX_EN); 1169 MVNETA_GMAC_AN_DUPLEX_EN);
1170 1170
1171 if (phydev->duplex) 1171 if (phydev->duplex)
1172 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 1172 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1173 1173
1174 if (phydev->speed == SPEED_1000) 1174 if (phydev->speed == SPEED_1000)
1175 val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 1175 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1176 else 1176 else
1177 val |= MVNETA_GMAC_CONFIG_MII_SPEED; 1177 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1178 1178
1179 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1179 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1180 1180
1181 pp->duplex = phydev->duplex; 1181 pp->duplex = phydev->duplex;
1182 pp->speed = phydev->speed; 1182 pp->speed = phydev->speed;
1183 } 1183 }
1184 } 1184 }
1185 1185
1186 if (phydev->link != pp->link) { 1186 if (phydev->link != pp->link) {
1187 if (!phydev->link) { 1187 if (!phydev->link) {
1188 pp->duplex = -1; 1188 pp->duplex = -1;
1189 pp->speed = 0; 1189 pp->speed = 0;
1190 } 1190 }
1191 1191
1192 pp->link = phydev->link; 1192 pp->link = phydev->link;
1193 status_change = 1; 1193 status_change = 1;
1194 } 1194 }
1195 1195
1196 if (status_change) { 1196 if (status_change) {
1197 if (phydev->link) { 1197 if (phydev->link) {
1198 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1198 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1199 val |= (MVNETA_GMAC_FORCE_LINK_PASS | 1199 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
1200 MVNETA_GMAC_FORCE_LINK_DOWN); 1200 MVNETA_GMAC_FORCE_LINK_DOWN);
1201 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1201 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1202 mvneta_port_up(pp); 1202 mvneta_port_up(pp);
1203 } else { 1203 } else {
1204 mvneta_port_down(pp); 1204 mvneta_port_down(pp);
1205 } 1205 }
1206 } 1206 }
1207 } 1207 }
1208 1208
1209 static int mvneta_open(struct udevice *dev) 1209 static int mvneta_open(struct udevice *dev)
1210 { 1210 {
1211 struct mvneta_port *pp = dev_get_priv(dev); 1211 struct mvneta_port *pp = dev_get_priv(dev);
1212 int ret; 1212 int ret;
1213 1213
1214 ret = mvneta_setup_rxqs(pp); 1214 ret = mvneta_setup_rxqs(pp);
1215 if (ret) 1215 if (ret)
1216 return ret; 1216 return ret;
1217 1217
1218 ret = mvneta_setup_txqs(pp); 1218 ret = mvneta_setup_txqs(pp);
1219 if (ret) 1219 if (ret)
1220 return ret; 1220 return ret;
1221 1221
1222 mvneta_adjust_link(dev); 1222 mvneta_adjust_link(dev);
1223 1223
1224 mvneta_start_dev(pp); 1224 mvneta_start_dev(pp);
1225 1225
1226 return 0; 1226 return 0;
1227 } 1227 }
1228 1228
1229 /* Initialize hw */ 1229 /* Initialize hw */
1230 static int mvneta_init2(struct mvneta_port *pp) 1230 static int mvneta_init2(struct mvneta_port *pp)
1231 { 1231 {
1232 int queue; 1232 int queue;
1233 1233
1234 /* Disable port */ 1234 /* Disable port */
1235 mvneta_port_disable(pp); 1235 mvneta_port_disable(pp);
1236 1236
1237 /* Set port default values */ 1237 /* Set port default values */
1238 mvneta_defaults_set(pp); 1238 mvneta_defaults_set(pp);
1239 1239
1240 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), 1240 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
1241 GFP_KERNEL); 1241 GFP_KERNEL);
1242 if (!pp->txqs) 1242 if (!pp->txqs)
1243 return -ENOMEM; 1243 return -ENOMEM;
1244 1244
1245 /* U-Boot special: use preallocated area */ 1245 /* U-Boot special: use preallocated area */
1246 pp->txqs[0].descs = buffer_loc.tx_descs; 1246 pp->txqs[0].descs = buffer_loc.tx_descs;
1247 1247
1248 /* Initialize TX descriptor rings */ 1248 /* Initialize TX descriptor rings */
1249 for (queue = 0; queue < txq_number; queue++) { 1249 for (queue = 0; queue < txq_number; queue++) {
1250 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1250 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1251 txq->id = queue; 1251 txq->id = queue;
1252 txq->size = pp->tx_ring_size; 1252 txq->size = pp->tx_ring_size;
1253 } 1253 }
1254 1254
1255 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), 1255 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
1256 GFP_KERNEL); 1256 GFP_KERNEL);
1257 if (!pp->rxqs) { 1257 if (!pp->rxqs) {
1258 kfree(pp->txqs); 1258 kfree(pp->txqs);
1259 return -ENOMEM; 1259 return -ENOMEM;
1260 } 1260 }
1261 1261
1262 /* U-Boot special: use preallocated area */ 1262 /* U-Boot special: use preallocated area */
1263 pp->rxqs[0].descs = buffer_loc.rx_descs; 1263 pp->rxqs[0].descs = buffer_loc.rx_descs;
1264 1264
1265 /* Create Rx descriptor rings */ 1265 /* Create Rx descriptor rings */
1266 for (queue = 0; queue < rxq_number; queue++) { 1266 for (queue = 0; queue < rxq_number; queue++) {
1267 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 1267 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1268 rxq->id = queue; 1268 rxq->id = queue;
1269 rxq->size = pp->rx_ring_size; 1269 rxq->size = pp->rx_ring_size;
1270 } 1270 }
1271 1271
1272 return 0; 1272 return 0;
1273 } 1273 }
1274 1274
1275 /* platform glue : initialize decoding windows */ 1275 /* platform glue : initialize decoding windows */
1276 1276
1277 /* 1277 /*
1278 * Not like A380, in Armada3700, there are two layers of decode windows for GBE: 1278 * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
1279 * First layer is: GbE Address window that resides inside the GBE unit, 1279 * First layer is: GbE Address window that resides inside the GBE unit,
1280 * Second layer is: Fabric address window which is located in the NIC400 1280 * Second layer is: Fabric address window which is located in the NIC400
1281 * (South Fabric). 1281 * (South Fabric).
1282 * To simplify the address decode configuration for Armada3700, we bypass the 1282 * To simplify the address decode configuration for Armada3700, we bypass the
1283 * first layer of GBE decode window by setting the first window to 4GB. 1283 * first layer of GBE decode window by setting the first window to 4GB.
1284 */ 1284 */
1285 static void mvneta_bypass_mbus_windows(struct mvneta_port *pp) 1285 static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
1286 { 1286 {
1287 /* 1287 /*
1288 * Set window size to 4GB, to bypass GBE address decode, leave the 1288 * Set window size to 4GB, to bypass GBE address decode, leave the
1289 * work to MBUS decode window 1289 * work to MBUS decode window
1290 */ 1290 */
1291 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK); 1291 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
1292 1292
1293 /* Enable GBE address decode window 0 by set bit 0 to 0 */ 1293 /* Enable GBE address decode window 0 by set bit 0 to 0 */
1294 clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE, 1294 clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
1295 MVNETA_BASE_ADDR_ENABLE_BIT); 1295 MVNETA_BASE_ADDR_ENABLE_BIT);
1296 1296
1297 /* Set GBE address decode window 0 to full Access (read or write) */ 1297 /* Set GBE address decode window 0 to full Access (read or write) */
1298 setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT, 1298 setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
1299 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW); 1299 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
1300 } 1300 }
1301 1301
1302 static void mvneta_conf_mbus_windows(struct mvneta_port *pp) 1302 static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
1303 { 1303 {
1304 const struct mbus_dram_target_info *dram; 1304 const struct mbus_dram_target_info *dram;
1305 u32 win_enable; 1305 u32 win_enable;
1306 u32 win_protect; 1306 u32 win_protect;
1307 int i; 1307 int i;
1308 1308
1309 dram = mvebu_mbus_dram_info(); 1309 dram = mvebu_mbus_dram_info();
1310 for (i = 0; i < 6; i++) { 1310 for (i = 0; i < 6; i++) {
1311 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1311 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1312 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1312 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1313 1313
1314 if (i < 4) 1314 if (i < 4)
1315 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1315 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1316 } 1316 }
1317 1317
1318 win_enable = 0x3f; 1318 win_enable = 0x3f;
1319 win_protect = 0; 1319 win_protect = 0;
1320 1320
1321 for (i = 0; i < dram->num_cs; i++) { 1321 for (i = 0; i < dram->num_cs; i++) {
1322 const struct mbus_dram_window *cs = dram->cs + i; 1322 const struct mbus_dram_window *cs = dram->cs + i;
1323 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | 1323 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
1324 (cs->mbus_attr << 8) | dram->mbus_dram_target_id); 1324 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
1325 1325
1326 mvreg_write(pp, MVNETA_WIN_SIZE(i), 1326 mvreg_write(pp, MVNETA_WIN_SIZE(i),
1327 (cs->size - 1) & 0xffff0000); 1327 (cs->size - 1) & 0xffff0000);
1328 1328
1329 win_enable &= ~(1 << i); 1329 win_enable &= ~(1 << i);
1330 win_protect |= 3 << (2 * i); 1330 win_protect |= 3 << (2 * i);
1331 } 1331 }
1332 1332
1333 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1333 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1334 } 1334 }
1335 1335
1336 /* Power up the port */ 1336 /* Power up the port */
1337 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 1337 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
1338 { 1338 {
1339 u32 ctrl; 1339 u32 ctrl;
1340 1340
1341 /* MAC Cause register should be cleared */ 1341 /* MAC Cause register should be cleared */
1342 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 1342 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
1343 1343
1344 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 1344 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1345 1345
1346 /* Even though it might look weird, when we're configured in 1346 /* Even though it might look weird, when we're configured in
1347 * SGMII or QSGMII mode, the RGMII bit needs to be set. 1347 * SGMII or QSGMII mode, the RGMII bit needs to be set.
1348 */ 1348 */
1349 switch (phy_mode) { 1349 switch (phy_mode) {
1350 case PHY_INTERFACE_MODE_QSGMII: 1350 case PHY_INTERFACE_MODE_QSGMII:
1351 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 1351 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
1352 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 1352 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1353 break; 1353 break;
1354 case PHY_INTERFACE_MODE_SGMII: 1354 case PHY_INTERFACE_MODE_SGMII:
1355 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 1355 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
1356 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 1356 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1357 break; 1357 break;
1358 case PHY_INTERFACE_MODE_RGMII: 1358 case PHY_INTERFACE_MODE_RGMII:
1359 case PHY_INTERFACE_MODE_RGMII_ID: 1359 case PHY_INTERFACE_MODE_RGMII_ID:
1360 ctrl |= MVNETA_GMAC2_PORT_RGMII; 1360 ctrl |= MVNETA_GMAC2_PORT_RGMII;
1361 break; 1361 break;
1362 default: 1362 default:
1363 return -EINVAL; 1363 return -EINVAL;
1364 } 1364 }
1365 1365
1366 /* Cancel Port Reset */ 1366 /* Cancel Port Reset */
1367 ctrl &= ~MVNETA_GMAC2_PORT_RESET; 1367 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
1368 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); 1368 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
1369 1369
1370 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 1370 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
1371 MVNETA_GMAC2_PORT_RESET) != 0) 1371 MVNETA_GMAC2_PORT_RESET) != 0)
1372 continue; 1372 continue;
1373 1373
1374 return 0; 1374 return 0;
1375 } 1375 }
1376 1376
1377 /* Device initialization routine */ 1377 /* Device initialization routine */
1378 static int mvneta_init(struct udevice *dev) 1378 static int mvneta_init(struct udevice *dev)
1379 { 1379 {
1380 struct eth_pdata *pdata = dev_get_platdata(dev); 1380 struct eth_pdata *pdata = dev_get_platdata(dev);
1381 struct mvneta_port *pp = dev_get_priv(dev); 1381 struct mvneta_port *pp = dev_get_priv(dev);
1382 int err; 1382 int err;
1383 1383
1384 pp->tx_ring_size = MVNETA_MAX_TXD; 1384 pp->tx_ring_size = MVNETA_MAX_TXD;
1385 pp->rx_ring_size = MVNETA_MAX_RXD; 1385 pp->rx_ring_size = MVNETA_MAX_RXD;
1386 1386
1387 err = mvneta_init2(pp); 1387 err = mvneta_init2(pp);
1388 if (err < 0) { 1388 if (err < 0) {
1389 dev_err(&pdev->dev, "can't init eth hal\n"); 1389 dev_err(&pdev->dev, "can't init eth hal\n");
1390 return err; 1390 return err;
1391 } 1391 }
1392 1392
1393 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def); 1393 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
1394 1394
1395 err = mvneta_port_power_up(pp, pp->phy_interface); 1395 err = mvneta_port_power_up(pp, pp->phy_interface);
1396 if (err < 0) { 1396 if (err < 0) {
1397 dev_err(&pdev->dev, "can't power up port\n"); 1397 dev_err(&pdev->dev, "can't power up port\n");
1398 return err; 1398 return err;
1399 } 1399 }
1400 1400
1401 /* Call open() now as it needs to be done before runing send() */ 1401 /* Call open() now as it needs to be done before runing send() */
1402 mvneta_open(dev); 1402 mvneta_open(dev);
1403 1403
1404 return 0; 1404 return 0;
1405 } 1405 }
1406 1406
1407 /* U-Boot only functions follow here */ 1407 /* U-Boot only functions follow here */
1408 1408
1409 /* SMI / MDIO functions */ 1409 /* SMI / MDIO functions */
1410 1410
1411 static int smi_wait_ready(struct mvneta_port *pp) 1411 static int smi_wait_ready(struct mvneta_port *pp)
1412 { 1412 {
1413 u32 timeout = MVNETA_SMI_TIMEOUT; 1413 u32 timeout = MVNETA_SMI_TIMEOUT;
1414 u32 smi_reg; 1414 u32 smi_reg;
1415 1415
1416 /* wait till the SMI is not busy */ 1416 /* wait till the SMI is not busy */
1417 do { 1417 do {
1418 /* read smi register */ 1418 /* read smi register */
1419 smi_reg = mvreg_read(pp, MVNETA_SMI); 1419 smi_reg = mvreg_read(pp, MVNETA_SMI);
1420 if (timeout-- == 0) { 1420 if (timeout-- == 0) {
1421 printf("Error: SMI busy timeout\n"); 1421 printf("Error: SMI busy timeout\n");
1422 return -EFAULT; 1422 return -EFAULT;
1423 } 1423 }
1424 } while (smi_reg & MVNETA_SMI_BUSY); 1424 } while (smi_reg & MVNETA_SMI_BUSY);
1425 1425
1426 return 0; 1426 return 0;
1427 } 1427 }
1428 1428
1429 /* 1429 /*
1430 * mvneta_mdio_read - miiphy_read callback function. 1430 * mvneta_mdio_read - miiphy_read callback function.
1431 * 1431 *
1432 * Returns 16bit phy register value, or 0xffff on error 1432 * Returns 16bit phy register value, or 0xffff on error
1433 */ 1433 */
1434 static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 1434 static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
1435 { 1435 {
1436 struct mvneta_port *pp = bus->priv; 1436 struct mvneta_port *pp = bus->priv;
1437 u32 smi_reg; 1437 u32 smi_reg;
1438 u32 timeout; 1438 u32 timeout;
1439 1439
1440 /* check parameters */ 1440 /* check parameters */
1441 if (addr > MVNETA_PHY_ADDR_MASK) { 1441 if (addr > MVNETA_PHY_ADDR_MASK) {
1442 printf("Error: Invalid PHY address %d\n", addr); 1442 printf("Error: Invalid PHY address %d\n", addr);
1443 return -EFAULT; 1443 return -EFAULT;
1444 } 1444 }
1445 1445
1446 if (reg > MVNETA_PHY_REG_MASK) { 1446 if (reg > MVNETA_PHY_REG_MASK) {
1447 printf("Err: Invalid register offset %d\n", reg); 1447 printf("Err: Invalid register offset %d\n", reg);
1448 return -EFAULT; 1448 return -EFAULT;
1449 } 1449 }
1450 1450
1451 /* wait till the SMI is not busy */ 1451 /* wait till the SMI is not busy */
1452 if (smi_wait_ready(pp) < 0) 1452 if (smi_wait_ready(pp) < 0)
1453 return -EFAULT; 1453 return -EFAULT;
1454 1454
1455 /* fill the phy address and regiser offset and read opcode */ 1455 /* fill the phy address and regiser offset and read opcode */
1456 smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS) 1456 smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1457 | (reg << MVNETA_SMI_REG_ADDR_OFFS) 1457 | (reg << MVNETA_SMI_REG_ADDR_OFFS)
1458 | MVNETA_SMI_OPCODE_READ; 1458 | MVNETA_SMI_OPCODE_READ;
1459 1459
1460 /* write the smi register */ 1460 /* write the smi register */
1461 mvreg_write(pp, MVNETA_SMI, smi_reg); 1461 mvreg_write(pp, MVNETA_SMI, smi_reg);
1462 1462
1463 /* wait till read value is ready */ 1463 /* wait till read value is ready */
1464 timeout = MVNETA_SMI_TIMEOUT; 1464 timeout = MVNETA_SMI_TIMEOUT;
1465 1465
1466 do { 1466 do {
1467 /* read smi register */ 1467 /* read smi register */
1468 smi_reg = mvreg_read(pp, MVNETA_SMI); 1468 smi_reg = mvreg_read(pp, MVNETA_SMI);
1469 if (timeout-- == 0) { 1469 if (timeout-- == 0) {
1470 printf("Err: SMI read ready timeout\n"); 1470 printf("Err: SMI read ready timeout\n");
1471 return -EFAULT; 1471 return -EFAULT;
1472 } 1472 }
1473 } while (!(smi_reg & MVNETA_SMI_READ_VALID)); 1473 } while (!(smi_reg & MVNETA_SMI_READ_VALID));
1474 1474
1475 /* Wait for the data to update in the SMI register */ 1475 /* Wait for the data to update in the SMI register */
1476 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) 1476 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
1477 ; 1477 ;
1478 1478
1479 return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK; 1479 return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
1480 } 1480 }
1481 1481
1482 /* 1482 /*
1483 * mvneta_mdio_write - miiphy_write callback function. 1483 * mvneta_mdio_write - miiphy_write callback function.
1484 * 1484 *
1485 * Returns 0 if write succeed, -EINVAL on bad parameters 1485 * Returns 0 if write succeed, -EINVAL on bad parameters
1486 * -ETIME on timeout 1486 * -ETIME on timeout
1487 */ 1487 */
1488 static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 1488 static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
1489 u16 value) 1489 u16 value)
1490 { 1490 {
1491 struct mvneta_port *pp = bus->priv; 1491 struct mvneta_port *pp = bus->priv;
1492 u32 smi_reg; 1492 u32 smi_reg;
1493 1493
1494 /* check parameters */ 1494 /* check parameters */
1495 if (addr > MVNETA_PHY_ADDR_MASK) { 1495 if (addr > MVNETA_PHY_ADDR_MASK) {
1496 printf("Error: Invalid PHY address %d\n", addr); 1496 printf("Error: Invalid PHY address %d\n", addr);
1497 return -EFAULT; 1497 return -EFAULT;
1498 } 1498 }
1499 1499
1500 if (reg > MVNETA_PHY_REG_MASK) { 1500 if (reg > MVNETA_PHY_REG_MASK) {
1501 printf("Err: Invalid register offset %d\n", reg); 1501 printf("Err: Invalid register offset %d\n", reg);
1502 return -EFAULT; 1502 return -EFAULT;
1503 } 1503 }
1504 1504
1505 /* wait till the SMI is not busy */ 1505 /* wait till the SMI is not busy */
1506 if (smi_wait_ready(pp) < 0) 1506 if (smi_wait_ready(pp) < 0)
1507 return -EFAULT; 1507 return -EFAULT;
1508 1508
1509 /* fill the phy addr and reg offset and write opcode and data */ 1509 /* fill the phy addr and reg offset and write opcode and data */
1510 smi_reg = value << MVNETA_SMI_DATA_OFFS; 1510 smi_reg = value << MVNETA_SMI_DATA_OFFS;
1511 smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS) 1511 smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1512 | (reg << MVNETA_SMI_REG_ADDR_OFFS); 1512 | (reg << MVNETA_SMI_REG_ADDR_OFFS);
1513 smi_reg &= ~MVNETA_SMI_OPCODE_READ; 1513 smi_reg &= ~MVNETA_SMI_OPCODE_READ;
1514 1514
1515 /* write the smi register */ 1515 /* write the smi register */
1516 mvreg_write(pp, MVNETA_SMI, smi_reg); 1516 mvreg_write(pp, MVNETA_SMI, smi_reg);
1517 1517
1518 return 0; 1518 return 0;
1519 } 1519 }
1520 1520
1521 static int mvneta_start(struct udevice *dev) 1521 static int mvneta_start(struct udevice *dev)
1522 { 1522 {
1523 struct mvneta_port *pp = dev_get_priv(dev); 1523 struct mvneta_port *pp = dev_get_priv(dev);
1524 struct phy_device *phydev; 1524 struct phy_device *phydev;
1525 1525
1526 mvneta_port_power_up(pp, pp->phy_interface); 1526 mvneta_port_power_up(pp, pp->phy_interface);
1527 1527
1528 if (!pp->init || pp->link == 0) { 1528 if (!pp->init || pp->link == 0) {
1529 if (mvneta_port_is_fixed_link(pp)) { 1529 if (mvneta_port_is_fixed_link(pp)) {
1530 u32 val; 1530 u32 val;
1531 1531
1532 pp->init = 1; 1532 pp->init = 1;
1533 pp->link = 1; 1533 pp->link = 1;
1534 mvneta_init(dev); 1534 mvneta_init(dev);
1535 1535
1536 val = MVNETA_GMAC_FORCE_LINK_UP | 1536 val = MVNETA_GMAC_FORCE_LINK_UP |
1537 MVNETA_GMAC_IB_BYPASS_AN_EN | 1537 MVNETA_GMAC_IB_BYPASS_AN_EN |
1538 MVNETA_GMAC_SET_FC_EN | 1538 MVNETA_GMAC_SET_FC_EN |
1539 MVNETA_GMAC_ADVERT_FC_EN | 1539 MVNETA_GMAC_ADVERT_FC_EN |
1540 MVNETA_GMAC_SAMPLE_TX_CFG_EN; 1540 MVNETA_GMAC_SAMPLE_TX_CFG_EN;
1541 1541
1542 if (pp->duplex) 1542 if (pp->duplex)
1543 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 1543 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1544 1544
1545 if (pp->speed == SPEED_1000) 1545 if (pp->speed == SPEED_1000)
1546 val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 1546 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1547 else if (pp->speed == SPEED_100) 1547 else if (pp->speed == SPEED_100)
1548 val |= MVNETA_GMAC_CONFIG_MII_SPEED; 1548 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1549 1549
1550 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1550 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1551 } else { 1551 } else {
1552 /* Set phy address of the port */ 1552 /* Set phy address of the port */
1553 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); 1553 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
1554 1554
1555 phydev = phy_connect(pp->bus, pp->phyaddr, dev, 1555 phydev = phy_connect(pp->bus, pp->phyaddr, dev,
1556 pp->phy_interface); 1556 pp->phy_interface);
1557 1557
1558 pp->phydev = phydev; 1558 pp->phydev = phydev;
1559 phy_config(phydev); 1559 phy_config(phydev);
1560 phy_startup(phydev); 1560 phy_startup(phydev);
1561 if (!phydev->link) { 1561 if (!phydev->link) {
1562 printf("%s: No link.\n", phydev->dev->name); 1562 printf("%s: No link.\n", phydev->dev->name);
1563 return -1; 1563 return -1;
1564 } 1564 }
1565 1565
1566 /* Full init on first call */ 1566 /* Full init on first call */
1567 mvneta_init(dev); 1567 mvneta_init(dev);
1568 pp->init = 1; 1568 pp->init = 1;
1569 return 0; 1569 return 0;
1570 } 1570 }
1571 } 1571 }
1572 1572
1573 /* Upon all following calls, this is enough */ 1573 /* Upon all following calls, this is enough */
1574 mvneta_port_up(pp); 1574 mvneta_port_up(pp);
1575 mvneta_port_enable(pp); 1575 mvneta_port_enable(pp);
1576 1576
1577 return 0; 1577 return 0;
1578 } 1578 }
1579 1579
1580 static int mvneta_send(struct udevice *dev, void *packet, int length) 1580 static int mvneta_send(struct udevice *dev, void *packet, int length)
1581 { 1581 {
1582 struct mvneta_port *pp = dev_get_priv(dev); 1582 struct mvneta_port *pp = dev_get_priv(dev);
1583 struct mvneta_tx_queue *txq = &pp->txqs[0]; 1583 struct mvneta_tx_queue *txq = &pp->txqs[0];
1584 struct mvneta_tx_desc *tx_desc; 1584 struct mvneta_tx_desc *tx_desc;
1585 int sent_desc; 1585 int sent_desc;
1586 u32 timeout = 0; 1586 u32 timeout = 0;
1587 1587
1588 /* Get a descriptor for the first part of the packet */ 1588 /* Get a descriptor for the first part of the packet */
1589 tx_desc = mvneta_txq_next_desc_get(txq); 1589 tx_desc = mvneta_txq_next_desc_get(txq);
1590 1590
1591 tx_desc->buf_phys_addr = (u32)(uintptr_t)packet; 1591 tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
1592 tx_desc->data_size = length; 1592 tx_desc->data_size = length;
1593 flush_dcache_range((ulong)packet, 1593 flush_dcache_range((ulong)packet,
1594 (ulong)packet + ALIGN(length, PKTALIGN)); 1594 (ulong)packet + ALIGN(length, PKTALIGN));
1595 1595
1596 /* First and Last descriptor */ 1596 /* First and Last descriptor */
1597 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; 1597 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
1598 mvneta_txq_pend_desc_add(pp, txq, 1); 1598 mvneta_txq_pend_desc_add(pp, txq, 1);
1599 1599
1600 /* Wait for packet to be sent (queue might help with speed here) */ 1600 /* Wait for packet to be sent (queue might help with speed here) */
1601 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1601 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1602 while (!sent_desc) { 1602 while (!sent_desc) {
1603 if (timeout++ > 10000) { 1603 if (timeout++ > 10000) {
1604 printf("timeout: packet not sent\n"); 1604 printf("timeout: packet not sent\n");
1605 return -1; 1605 return -1;
1606 } 1606 }
1607 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1607 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1608 } 1608 }
1609 1609
1610 /* txDone has increased - hw sent packet */ 1610 /* txDone has increased - hw sent packet */
1611 mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1611 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1612 1612
1613 return 0; 1613 return 0;
1614 } 1614 }
1615 1615
1616 static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp) 1616 static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
1617 { 1617 {
1618 struct mvneta_port *pp = dev_get_priv(dev); 1618 struct mvneta_port *pp = dev_get_priv(dev);
1619 int rx_done; 1619 int rx_done;
1620 struct mvneta_rx_queue *rxq; 1620 struct mvneta_rx_queue *rxq;
1621 int rx_bytes = 0; 1621 int rx_bytes = 0;
1622 1622
1623 /* get rx queue */ 1623 /* get rx queue */
1624 rxq = mvneta_rxq_handle_get(pp, rxq_def); 1624 rxq = mvneta_rxq_handle_get(pp, rxq_def);
1625 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1625 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1626 1626
1627 if (rx_done) { 1627 if (rx_done) {
1628 struct mvneta_rx_desc *rx_desc; 1628 struct mvneta_rx_desc *rx_desc;
1629 unsigned char *data; 1629 unsigned char *data;
1630 u32 rx_status; 1630 u32 rx_status;
1631 1631
1632 /* 1632 /*
1633 * No cache invalidation needed here, since the desc's are 1633 * No cache invalidation needed here, since the desc's are
1634 * located in a uncached memory region 1634 * located in a uncached memory region
1635 */ 1635 */
1636 rx_desc = mvneta_rxq_next_desc_get(rxq); 1636 rx_desc = mvneta_rxq_next_desc_get(rxq);
1637 1637
1638 rx_status = rx_desc->status; 1638 rx_status = rx_desc->status;
1639 if (!mvneta_rxq_desc_is_first_last(rx_status) || 1639 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1640 (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 1640 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1641 mvneta_rx_error(pp, rx_desc); 1641 mvneta_rx_error(pp, rx_desc);
1642 /* leave the descriptor untouched */ 1642 /* leave the descriptor untouched */
1643 return -EIO; 1643 return -EIO;
1644 } 1644 }
1645 1645
1646 /* 2 bytes for marvell header. 4 bytes for crc */ 1646 /* 2 bytes for marvell header. 4 bytes for crc */
1647 rx_bytes = rx_desc->data_size - 6; 1647 rx_bytes = rx_desc->data_size - 6;
1648 1648
1649 /* give packet to stack - skip on first 2 bytes */ 1649 /* give packet to stack - skip on first 2 bytes */
1650 data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2; 1650 data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
1651 /* 1651 /*
1652 * No cache invalidation needed here, since the rx_buffer's are 1652 * No cache invalidation needed here, since the rx_buffer's are
1653 * located in a uncached memory region 1653 * located in a uncached memory region
1654 */ 1654 */
1655 *packetp = data; 1655 *packetp = data;
1656 1656
1657 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1657 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1658 } 1658 }
1659 1659
1660 return rx_bytes; 1660 return rx_bytes;
1661 } 1661 }
1662 1662
1663 static int mvneta_probe(struct udevice *dev) 1663 static int mvneta_probe(struct udevice *dev)
1664 { 1664 {
1665 struct eth_pdata *pdata = dev_get_platdata(dev); 1665 struct eth_pdata *pdata = dev_get_platdata(dev);
1666 struct mvneta_port *pp = dev_get_priv(dev); 1666 struct mvneta_port *pp = dev_get_priv(dev);
1667 void *blob = (void *)gd->fdt_blob; 1667 void *blob = (void *)gd->fdt_blob;
1668 int node = dev_of_offset(dev); 1668 int node = dev_of_offset(dev);
1669 struct mii_dev *bus; 1669 struct mii_dev *bus;
1670 unsigned long addr; 1670 unsigned long addr;
1671 void *bd_space; 1671 void *bd_space;
1672 int ret; 1672 int ret;
1673 int fl_node; 1673 int fl_node;
1674 1674
1675 /* 1675 /*
1676 * Allocate buffer area for descs and rx_buffers. This is only 1676 * Allocate buffer area for descs and rx_buffers. This is only
1677 * done once for all interfaces. As only one interface can 1677 * done once for all interfaces. As only one interface can
1678 * be active. Make this area DMA safe by disabling the D-cache 1678 * be active. Make this area DMA safe by disabling the D-cache
1679 */ 1679 */
1680 if (!buffer_loc.tx_descs) { 1680 if (!buffer_loc.tx_descs) {
1681 /* Align buffer area for descs and rx_buffers to 1MiB */ 1681 /* Align buffer area for descs and rx_buffers to 1MiB */
1682 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 1682 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
1683 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, 1683 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
1684 DCACHE_OFF); 1684 DCACHE_OFF);
1685 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; 1685 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
1686 buffer_loc.rx_descs = (struct mvneta_rx_desc *) 1686 buffer_loc.rx_descs = (struct mvneta_rx_desc *)
1687 ((phys_addr_t)bd_space + 1687 ((phys_addr_t)bd_space +
1688 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc)); 1688 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
1689 buffer_loc.rx_buffers = (phys_addr_t) 1689 buffer_loc.rx_buffers = (phys_addr_t)
1690 (bd_space + 1690 (bd_space +
1691 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) + 1691 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
1692 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); 1692 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
1693 } 1693 }
1694 1694
1695 pp->base = (void __iomem *)pdata->iobase; 1695 pp->base = (void __iomem *)pdata->iobase;
1696 1696
1697 /* Configure MBUS address windows */ 1697 /* Configure MBUS address windows */
1698 if (device_is_compatible(dev, "marvell,armada-3700-neta")) 1698 if (device_is_compatible(dev, "marvell,armada-3700-neta"))
1699 mvneta_bypass_mbus_windows(pp); 1699 mvneta_bypass_mbus_windows(pp);
1700 else 1700 else
1701 mvneta_conf_mbus_windows(pp); 1701 mvneta_conf_mbus_windows(pp);
1702 1702
1703 /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ 1703 /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
1704 pp->phy_interface = pdata->phy_interface; 1704 pp->phy_interface = pdata->phy_interface;
1705 1705
1706 /* fetch 'fixed-link' property from 'neta' node */ 1706 /* fetch 'fixed-link' property from 'neta' node */
1707 fl_node = fdt_subnode_offset(blob, node, "fixed-link"); 1707 fl_node = fdt_subnode_offset(blob, node, "fixed-link");
1708 if (fl_node != -FDT_ERR_NOTFOUND) { 1708 if (fl_node != -FDT_ERR_NOTFOUND) {
1709 /* set phy_addr to invalid value for fixed link */ 1709 /* set phy_addr to invalid value for fixed link */
1710 pp->phyaddr = PHY_MAX_ADDR + 1; 1710 pp->phyaddr = PHY_MAX_ADDR + 1;
1711 pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex"); 1711 pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
1712 pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0); 1712 pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
1713 } else { 1713 } else {
1714 /* Now read phyaddr from DT */ 1714 /* Now read phyaddr from DT */
1715 addr = fdtdec_get_int(blob, node, "phy", 0); 1715 addr = fdtdec_get_int(blob, node, "phy", 0);
1716 addr = fdt_node_offset_by_phandle(blob, addr); 1716 addr = fdt_node_offset_by_phandle(blob, addr);
1717 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); 1717 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
1718 } 1718 }
1719 1719
1720 bus = mdio_alloc(); 1720 bus = mdio_alloc();
1721 if (!bus) { 1721 if (!bus) {
1722 printf("Failed to allocate MDIO bus\n"); 1722 printf("Failed to allocate MDIO bus\n");
1723 return -ENOMEM; 1723 return -ENOMEM;
1724 } 1724 }
1725 1725
1726 bus->read = mvneta_mdio_read; 1726 bus->read = mvneta_mdio_read;
1727 bus->write = mvneta_mdio_write; 1727 bus->write = mvneta_mdio_write;
1728 snprintf(bus->name, sizeof(bus->name), dev->name); 1728 snprintf(bus->name, sizeof(bus->name), dev->name);
1729 bus->priv = (void *)pp; 1729 bus->priv = (void *)pp;
1730 pp->bus = bus; 1730 pp->bus = bus;
1731 1731
1732 ret = mdio_register(bus); 1732 ret = mdio_register(bus);
1733 if (ret) 1733 if (ret)
1734 return ret; 1734 return ret;
1735 1735
1736 return board_network_enable(bus); 1736 return board_network_enable(bus);
1737 } 1737 }
1738 1738
1739 static void mvneta_stop(struct udevice *dev) 1739 static void mvneta_stop(struct udevice *dev)
1740 { 1740 {
1741 struct mvneta_port *pp = dev_get_priv(dev); 1741 struct mvneta_port *pp = dev_get_priv(dev);
1742 1742
1743 mvneta_port_down(pp); 1743 mvneta_port_down(pp);
1744 mvneta_port_disable(pp); 1744 mvneta_port_disable(pp);
1745 } 1745 }
1746 1746
1747 static const struct eth_ops mvneta_ops = { 1747 static const struct eth_ops mvneta_ops = {
1748 .start = mvneta_start, 1748 .start = mvneta_start,
1749 .send = mvneta_send, 1749 .send = mvneta_send,
1750 .recv = mvneta_recv, 1750 .recv = mvneta_recv,
1751 .stop = mvneta_stop, 1751 .stop = mvneta_stop,
1752 }; 1752 };
1753 1753
1754 static int mvneta_ofdata_to_platdata(struct udevice *dev) 1754 static int mvneta_ofdata_to_platdata(struct udevice *dev)
1755 { 1755 {
1756 struct eth_pdata *pdata = dev_get_platdata(dev); 1756 struct eth_pdata *pdata = dev_get_platdata(dev);
1757 const char *phy_mode; 1757 const char *phy_mode;
1758 1758
1759 pdata->iobase = devfdt_get_addr(dev); 1759 pdata->iobase = devfdt_get_addr(dev);
1760 1760
1761 /* Get phy-mode / phy_interface from DT */ 1761 /* Get phy-mode / phy_interface from DT */
1762 pdata->phy_interface = -1; 1762 pdata->phy_interface = -1;
1763 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1763 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1764 NULL); 1764 NULL);
1765 if (phy_mode) 1765 if (phy_mode)
1766 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 1766 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1767 if (pdata->phy_interface == -1) { 1767 if (pdata->phy_interface == -1) {
1768 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1768 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1769 return -EINVAL; 1769 return -EINVAL;
1770 } 1770 }
1771 1771
1772 return 0; 1772 return 0;
1773 } 1773 }
1774 1774
1775 static const struct udevice_id mvneta_ids[] = { 1775 static const struct udevice_id mvneta_ids[] = {
1776 { .compatible = "marvell,armada-370-neta" }, 1776 { .compatible = "marvell,armada-370-neta" },
1777 { .compatible = "marvell,armada-xp-neta" }, 1777 { .compatible = "marvell,armada-xp-neta" },
1778 { .compatible = "marvell,armada-3700-neta" }, 1778 { .compatible = "marvell,armada-3700-neta" },
1779 { } 1779 { }
1780 }; 1780 };
1781 1781
1782 U_BOOT_DRIVER(mvneta) = { 1782 U_BOOT_DRIVER(mvneta) = {
1783 .name = "mvneta", 1783 .name = "mvneta",
1784 .id = UCLASS_ETH, 1784 .id = UCLASS_ETH,
1785 .of_match = mvneta_ids, 1785 .of_match = mvneta_ids,
1786 .ofdata_to_platdata = mvneta_ofdata_to_platdata, 1786 .ofdata_to_platdata = mvneta_ofdata_to_platdata,
1787 .probe = mvneta_probe, 1787 .probe = mvneta_probe,
1788 .ops = &mvneta_ops, 1788 .ops = &mvneta_ops,
1789 .priv_auto_alloc_size = sizeof(struct mvneta_port), 1789 .priv_auto_alloc_size = sizeof(struct mvneta_port),
1790 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1790 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1791 }; 1791 };
1792 1792